Denis Nyzovets / FT810_DISCO-F429ZI

Library for FT810 EVE chip

Fork of FT810 by Curtis Mattull

src/FT_GPU_Hal.cpp@1:75efdc9d4bc2, 2016-09-07 (annotated)

Committer:
cpm219
Date:
Wed Sep 07 22:22:32 2016 +0000
Revision:
1:75efdc9d4bc2
Parent:
0:2d0ef4830603
Child:
2:293363bbeeda
latest version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cpm219 0:2d0ef4830603 1 /* mbed Library for FTDI FT800 Enbedded Video Engine "EVE"
cpm219 0:2d0ef4830603 2 * based on Original Code Sample from FTDI
cpm219 0:2d0ef4830603 3 * ported to mbed by Peter Drescher, DC2PD 2014
cpm219 0:2d0ef4830603 4 * Released under the MIT License: http://mbed.org/license/mit
cpm219 0:2d0ef4830603 5 * 19.09.14 changed to shorter function names
cpm219 0:2d0ef4830603 6 * FTDI was using very long names.
cpm219 0:2d0ef4830603 7 * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ... */
cpm219 0:2d0ef4830603 8
cpm219 0:2d0ef4830603 9 #include "FT_Platform.h"
cpm219 0:2d0ef4830603 10 #include "mbed.h"
cpm219 0:2d0ef4830603 11 #include "FT_LCD_Type.h"
cpm219 0:2d0ef4830603 12 Serial pc(USBTX, USBRX);
cpm219 0:2d0ef4830603 13
cpm219 0:2d0ef4830603 14 FT800::FT800(PinName mosi,
cpm219 0:2d0ef4830603 15 PinName miso,
cpm219 0:2d0ef4830603 16 PinName sck,
cpm219 0:2d0ef4830603 17 PinName ss,
cpm219 0:2d0ef4830603 18 PinName intr,
cpm219 0:2d0ef4830603 19 PinName pd)
cpm219 0:2d0ef4830603 20 :
cpm219 0:2d0ef4830603 21 _spi(mosi, miso, sck),
cpm219 0:2d0ef4830603 22 _ss(ss),
cpm219 0:2d0ef4830603 23 _pd(pd),
cpm219 0:2d0ef4830603 24 _f800_isr(InterruptIn(intr))
cpm219 0:2d0ef4830603 25 {
cpm219 0:2d0ef4830603 26 _spi.format(8,0); // 8 bit spi mode 0
cpm219 0:2d0ef4830603 27 _spi.frequency(1000000); // start with 10 Mhz SPI clock
cpm219 0:2d0ef4830603 28 _ss = 1; // cs high
cpm219 0:2d0ef4830603 29 _pd = 1; // PD high
cpm219 0:2d0ef4830603 30 Bootup();
cpm219 0:2d0ef4830603 31 }
cpm219 0:2d0ef4830603 32
cpm219 0:2d0ef4830603 33
cpm219 0:2d0ef4830603 34 ft_bool_t FT800::Bootup(void){
cpm219 0:2d0ef4830603 35 Open();
cpm219 0:2d0ef4830603 36 BootupConfig();
cpm219 0:2d0ef4830603 37
cpm219 0:2d0ef4830603 38 return(1);
cpm219 0:2d0ef4830603 39 }
cpm219 0:2d0ef4830603 40
cpm219 0:2d0ef4830603 41
cpm219 0:2d0ef4830603 42 ft_void_t FT800::BootupConfig(void){
cpm219 0:2d0ef4830603 43 ft_uint8_t chipid;
cpm219 0:2d0ef4830603 44 /* Do a power cycle for safer side */
cpm219 0:2d0ef4830603 45 Powercycle( FT_TRUE);
cpm219 0:2d0ef4830603 46 /*
cpm219 0:2d0ef4830603 47 7/8/16: Curt added the sleep delay below...
cpm219 0:2d0ef4830603 48 */
cpm219 0:2d0ef4830603 49 // Sleep(30);
cpm219 0:2d0ef4830603 50
cpm219 0:2d0ef4830603 51 /* Set the clk to external clock */
cpm219 0:2d0ef4830603 52 HostCommand( FT_GPU_EXTERNAL_OSC);
cpm219 0:2d0ef4830603 53 Sleep(10);
cpm219 0:2d0ef4830603 54
cpm219 0:2d0ef4830603 55 /* Access address 0 to wake up the FT800 */
cpm219 0:2d0ef4830603 56 HostCommand( FT_GPU_ACTIVE_M);
cpm219 0:2d0ef4830603 57 Sleep(500);
cpm219 0:2d0ef4830603 58
cpm219 0:2d0ef4830603 59 /* Switch PLL output to 48MHz */
cpm219 0:2d0ef4830603 60 // HostCommand( FT_GPU_PLL_48M);
cpm219 0:2d0ef4830603 61 Sleep(10);
cpm219 0:2d0ef4830603 62
cpm219 0:2d0ef4830603 63 /* Do a core reset for safer side */
cpm219 0:2d0ef4830603 64 HostCommand( FT_GPU_CORE_RESET);
cpm219 0:2d0ef4830603 65 Sleep(500);
cpm219 0:2d0ef4830603 66 //Read Register ID to check if FT800 is ready.
cpm219 0:2d0ef4830603 67 chipid = Rd8( REG_ID);
cpm219 0:2d0ef4830603 68 // chipid = Rd8(0x0C0000);
cpm219 0:2d0ef4830603 69 pc.printf("ID%08X\n", chipid);
cpm219 0:2d0ef4830603 70 while(chipid != 0x7C)
cpm219 0:2d0ef4830603 71
cpm219 0:2d0ef4830603 72
cpm219 0:2d0ef4830603 73 // Speed up
cpm219 0:2d0ef4830603 74 _spi.frequency(20000000); // 20 Mhz SPI clock DC
cpm219 0:2d0ef4830603 75 // _spi.frequency(12000000); // 12 Mhz SPI clock
cpm219 0:2d0ef4830603 76 /* Configuration of LCD display */
cpm219 0:2d0ef4830603 77 DispHCycle = my_DispHCycle;
cpm219 0:2d0ef4830603 78 Wr16( REG_HCYCLE, DispHCycle);
cpm219 0:2d0ef4830603 79 DispHOffset = my_DispHOffset;
cpm219 0:2d0ef4830603 80 Wr16( REG_HOFFSET, DispHOffset);
cpm219 0:2d0ef4830603 81 DispWidth = my_DispWidth;
cpm219 0:2d0ef4830603 82 Wr16( REG_HSIZE, DispWidth);
cpm219 0:2d0ef4830603 83 DispHSync0 = my_DispHSync0;
cpm219 0:2d0ef4830603 84 Wr16( REG_HSYNC0, DispHSync0);
cpm219 0:2d0ef4830603 85 DispHSync1 = my_DispHSync1;
cpm219 0:2d0ef4830603 86 Wr16( REG_HSYNC1, DispHSync1);
cpm219 0:2d0ef4830603 87 DispVCycle = my_DispVCycle;
cpm219 0:2d0ef4830603 88 Wr16( REG_VCYCLE, DispVCycle);
cpm219 0:2d0ef4830603 89 DispVOffset = my_DispVOffset;
cpm219 0:2d0ef4830603 90 Wr16( REG_VOFFSET, DispVOffset);
cpm219 0:2d0ef4830603 91 DispHeight = my_DispHeight;
cpm219 0:2d0ef4830603 92 Wr16( REG_VSIZE, DispHeight);
cpm219 0:2d0ef4830603 93 DispVSync0 = my_DispVSync0;
cpm219 0:2d0ef4830603 94 Wr16( REG_VSYNC0, DispVSync0);
cpm219 0:2d0ef4830603 95 DispVSync1 = my_DispVSync1;
cpm219 0:2d0ef4830603 96 Wr16( REG_VSYNC1, DispVSync1);
cpm219 0:2d0ef4830603 97 DispSwizzle = my_DispSwizzle;
cpm219 0:2d0ef4830603 98 Wr8( REG_SWIZZLE, DispSwizzle);
cpm219 0:2d0ef4830603 99 DispPCLKPol = my_DispPCLKPol;
cpm219 0:2d0ef4830603 100 Wr8( REG_PCLK_POL, DispPCLKPol);
cpm219 0:2d0ef4830603 101 Wr8( REG_CSPREAD, 0);
cpm219 0:2d0ef4830603 102 DispPCLK = my_DispPCLK;
cpm219 0:2d0ef4830603 103 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
cpm219 0:2d0ef4830603 104
cpm219 1:75efdc9d4bc2 105 Wr16( REG_PWM_HZ, 250);
cpm219 0:2d0ef4830603 106
cpm219 0:2d0ef4830603 107 #ifdef Inv_Backlite // turn on backlite
cpm219 0:2d0ef4830603 108 Wr16( REG_PWM_DUTY, 0);
cpm219 0:2d0ef4830603 109 #else
cpm219 1:75efdc9d4bc2 110 Wr16( REG_PWM_DUTY, 128);
cpm219 0:2d0ef4830603 111 #endif
cpm219 0:2d0ef4830603 112
cpm219 0:2d0ef4830603 113 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
cpm219 0:2d0ef4830603 114 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 115
cpm219 0:2d0ef4830603 116 Wr32( RAM_DL, CLEAR(1,1,1));
cpm219 0:2d0ef4830603 117 Wr32( RAM_DL+4, DISPLAY());
cpm219 0:2d0ef4830603 118 Wr32( REG_DLSWAP,1);
cpm219 0:2d0ef4830603 119
cpm219 0:2d0ef4830603 120 Wr16( REG_PCLK, DispPCLK);
cpm219 0:2d0ef4830603 121
cpm219 0:2d0ef4830603 122 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
cpm219 0:2d0ef4830603 123 Wr16( REG_TOUCH_RZTHRESH,2400);
cpm219 0:2d0ef4830603 124
cpm219 0:2d0ef4830603 125 }
cpm219 0:2d0ef4830603 126
cpm219 0:2d0ef4830603 127
cpm219 0:2d0ef4830603 128
cpm219 0:2d0ef4830603 129 /* API to initialize the SPI interface */
cpm219 0:2d0ef4830603 130 ft_bool_t FT800::Init()
cpm219 0:2d0ef4830603 131 {
cpm219 0:2d0ef4830603 132 // is done in constructor
cpm219 0:2d0ef4830603 133 return 1;
cpm219 0:2d0ef4830603 134 }
cpm219 0:2d0ef4830603 135
cpm219 0:2d0ef4830603 136
cpm219 0:2d0ef4830603 137 ft_bool_t FT800::Open()
cpm219 0:2d0ef4830603 138 {
cpm219 0:2d0ef4830603 139 cmd_fifo_wp = dl_buff_wp = 0;
cpm219 0:2d0ef4830603 140 status = OPENED;
cpm219 0:2d0ef4830603 141 return 1;
cpm219 0:2d0ef4830603 142 }
cpm219 0:2d0ef4830603 143
cpm219 0:2d0ef4830603 144 ft_void_t FT800::Close( )
cpm219 0:2d0ef4830603 145 {
cpm219 0:2d0ef4830603 146 status = CLOSED;
cpm219 0:2d0ef4830603 147 }
cpm219 0:2d0ef4830603 148
cpm219 0:2d0ef4830603 149 ft_void_t FT800::DeInit()
cpm219 0:2d0ef4830603 150 {
cpm219 0:2d0ef4830603 151
cpm219 0:2d0ef4830603 152 }
cpm219 0:2d0ef4830603 153
cpm219 0:2d0ef4830603 154 /*The APIs for reading/writing transfer continuously only with small buffer system*/
cpm219 0:2d0ef4830603 155 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
cpm219 0:2d0ef4830603 156 {
cpm219 0:2d0ef4830603 157 if (FT_GPU_READ == rw){
cpm219 0:2d0ef4830603 158 _ss = 0; // cs low
cpm219 0:2d0ef4830603 159 _spi.write(addr >> 16);
cpm219 0:2d0ef4830603 160 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 161 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 162 _spi.write(0); //Dummy Read Byte
cpm219 0:2d0ef4830603 163 status = READING;
cpm219 0:2d0ef4830603 164 }else{
cpm219 0:2d0ef4830603 165 _ss = 0; // cs low
cpm219 0:2d0ef4830603 166 _spi.write(0x80 | (addr >> 16));
cpm219 0:2d0ef4830603 167 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 168 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 169 status = WRITING;
cpm219 0:2d0ef4830603 170 }
cpm219 0:2d0ef4830603 171 }
cpm219 0:2d0ef4830603 172
cpm219 0:2d0ef4830603 173
cpm219 0:2d0ef4830603 174 /*The APIs for writing transfer continuously only*/
cpm219 0:2d0ef4830603 175 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
cpm219 0:2d0ef4830603 176 {
cpm219 0:2d0ef4830603 177 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
cpm219 0:2d0ef4830603 178 }
cpm219 0:2d0ef4830603 179
cpm219 0:2d0ef4830603 180 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
cpm219 0:2d0ef4830603 181 {
cpm219 0:2d0ef4830603 182 ft_uint16_t length = strlen(string);
cpm219 0:2d0ef4830603 183 while(length --){
cpm219 0:2d0ef4830603 184 Transfer8( *string);
cpm219 0:2d0ef4830603 185 string ++;
cpm219 0:2d0ef4830603 186 }
cpm219 0:2d0ef4830603 187 //Append one null as ending flag
cpm219 0:2d0ef4830603 188 Transfer8( 0);
cpm219 0:2d0ef4830603 189 return(1);
cpm219 0:2d0ef4830603 190 }
cpm219 0:2d0ef4830603 191
cpm219 0:2d0ef4830603 192
cpm219 0:2d0ef4830603 193 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
cpm219 0:2d0ef4830603 194 {
cpm219 0:2d0ef4830603 195 return _spi.write(value);
cpm219 0:2d0ef4830603 196 }
cpm219 0:2d0ef4830603 197
cpm219 0:2d0ef4830603 198
cpm219 0:2d0ef4830603 199 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
cpm219 0:2d0ef4830603 200 {
cpm219 0:2d0ef4830603 201 ft_uint16_t retVal = 0;
cpm219 0:2d0ef4830603 202
cpm219 0:2d0ef4830603 203 if (status == WRITING){
cpm219 0:2d0ef4830603 204 Transfer8( value & 0xFF);//LSB first
cpm219 0:2d0ef4830603 205 Transfer8( (value >> 8) & 0xFF);
cpm219 0:2d0ef4830603 206 }else{
cpm219 0:2d0ef4830603 207 retVal = Transfer8( 0);
cpm219 0:2d0ef4830603 208 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
cpm219 0:2d0ef4830603 209 }
cpm219 0:2d0ef4830603 210
cpm219 0:2d0ef4830603 211 return retVal;
cpm219 0:2d0ef4830603 212 }
cpm219 0:2d0ef4830603 213
cpm219 0:2d0ef4830603 214 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
cpm219 0:2d0ef4830603 215 {
cpm219 0:2d0ef4830603 216 ft_uint32_t retVal = 0;
cpm219 0:2d0ef4830603 217 if (status == WRITING){
cpm219 0:2d0ef4830603 218 Transfer16( value & 0xFFFF);//LSB first
cpm219 0:2d0ef4830603 219 Transfer16( (value >> 16) & 0xFFFF);
cpm219 0:2d0ef4830603 220 }else{
cpm219 0:2d0ef4830603 221 retVal = Transfer16( 0);
cpm219 0:2d0ef4830603 222 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
cpm219 0:2d0ef4830603 223 }
cpm219 0:2d0ef4830603 224 return retVal;
cpm219 0:2d0ef4830603 225 }
cpm219 0:2d0ef4830603 226
cpm219 0:2d0ef4830603 227 ft_void_t FT800::EndTransfer( )
cpm219 0:2d0ef4830603 228 {
cpm219 0:2d0ef4830603 229 _ss = 1;
cpm219 0:2d0ef4830603 230 status = OPENED;
cpm219 0:2d0ef4830603 231 }
cpm219 0:2d0ef4830603 232
cpm219 0:2d0ef4830603 233
cpm219 0:2d0ef4830603 234 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
cpm219 0:2d0ef4830603 235 {
cpm219 0:2d0ef4830603 236 ft_uint8_t value;
cpm219 0:2d0ef4830603 237 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 238 value = Transfer8( 0);
cpm219 0:2d0ef4830603 239 EndTransfer( );
cpm219 0:2d0ef4830603 240 return value;
cpm219 0:2d0ef4830603 241 }
cpm219 0:2d0ef4830603 242 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
cpm219 0:2d0ef4830603 243 {
cpm219 0:2d0ef4830603 244 ft_uint16_t value;
cpm219 0:2d0ef4830603 245 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 246 value = Transfer16( 0);
cpm219 0:2d0ef4830603 247 EndTransfer( );
cpm219 0:2d0ef4830603 248 return value;
cpm219 0:2d0ef4830603 249 }
cpm219 0:2d0ef4830603 250 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
cpm219 0:2d0ef4830603 251 {
cpm219 0:2d0ef4830603 252 ft_uint32_t value;
cpm219 0:2d0ef4830603 253 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 254 value = Transfer32( 0);
cpm219 0:2d0ef4830603 255 EndTransfer( );
cpm219 0:2d0ef4830603 256 return value;
cpm219 0:2d0ef4830603 257 }
cpm219 0:2d0ef4830603 258
cpm219 0:2d0ef4830603 259 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
cpm219 0:2d0ef4830603 260 {
cpm219 0:2d0ef4830603 261 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 262 Transfer8( v);
cpm219 0:2d0ef4830603 263 EndTransfer( );
cpm219 0:2d0ef4830603 264 }
cpm219 0:2d0ef4830603 265 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
cpm219 0:2d0ef4830603 266 {
cpm219 0:2d0ef4830603 267 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 268 Transfer16( v);
cpm219 0:2d0ef4830603 269 EndTransfer( );
cpm219 0:2d0ef4830603 270 }
cpm219 0:2d0ef4830603 271 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
cpm219 0:2d0ef4830603 272 {
cpm219 0:2d0ef4830603 273 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 274 Transfer32( v);
cpm219 0:2d0ef4830603 275 EndTransfer( );
cpm219 0:2d0ef4830603 276 }
cpm219 0:2d0ef4830603 277
cpm219 0:2d0ef4830603 278 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
cpm219 0:2d0ef4830603 279 {
cpm219 0:2d0ef4830603 280 _ss = 0;
cpm219 0:2d0ef4830603 281 _spi.write(cmd);
cpm219 0:2d0ef4830603 282 _spi.write(0);
cpm219 0:2d0ef4830603 283 _spi.write(0);
cpm219 0:2d0ef4830603 284 _ss = 1;
cpm219 0:2d0ef4830603 285 }
cpm219 0:2d0ef4830603 286
cpm219 0:2d0ef4830603 287 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
cpm219 0:2d0ef4830603 288 {
cpm219 0:2d0ef4830603 289 HostCommand( pllsource);
cpm219 0:2d0ef4830603 290 }
cpm219 0:2d0ef4830603 291
cpm219 0:2d0ef4830603 292 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
cpm219 0:2d0ef4830603 293 {
cpm219 0:2d0ef4830603 294 HostCommand( freq);
cpm219 0:2d0ef4830603 295 }
cpm219 0:2d0ef4830603 296
cpm219 0:2d0ef4830603 297 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
cpm219 0:2d0ef4830603 298 {
cpm219 0:2d0ef4830603 299 HostCommand( pwrmode);
cpm219 0:2d0ef4830603 300 }
cpm219 0:2d0ef4830603 301
cpm219 0:2d0ef4830603 302 ft_void_t FT800::CoreReset( )
cpm219 0:2d0ef4830603 303 {
cpm219 0:2d0ef4830603 304 HostCommand( 0x68);
cpm219 0:2d0ef4830603 305 }
cpm219 0:2d0ef4830603 306
cpm219 0:2d0ef4830603 307
cpm219 0:2d0ef4830603 308 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
cpm219 0:2d0ef4830603 309 {
cpm219 0:2d0ef4830603 310 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
cpm219 0:2d0ef4830603 311 //4 byte alignment
cpm219 0:2d0ef4830603 312 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
cpm219 0:2d0ef4830603 313 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
cpm219 0:2d0ef4830603 314 }
cpm219 0:2d0ef4830603 315
cpm219 0:2d0ef4830603 316
cpm219 0:2d0ef4830603 317 ft_uint16_t FT800::fifo_Freespace( )
cpm219 0:2d0ef4830603 318 {
cpm219 0:2d0ef4830603 319 ft_uint16_t fullness,retval;
cpm219 0:2d0ef4830603 320
cpm219 0:2d0ef4830603 321 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
cpm219 0:2d0ef4830603 322 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
cpm219 0:2d0ef4830603 323 return (retval);
cpm219 0:2d0ef4830603 324 }
cpm219 0:2d0ef4830603 325
cpm219 0:2d0ef4830603 326 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 327 {
cpm219 0:2d0ef4830603 328 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 329
cpm219 0:2d0ef4830603 330 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 331 do {
cpm219 0:2d0ef4830603 332 length = count;
cpm219 0:2d0ef4830603 333 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 334 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 335 }
cpm219 0:2d0ef4830603 336 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 337
cpm219 0:2d0ef4830603 338 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 339
cpm219 0:2d0ef4830603 340 SizeTransfered = 0;
cpm219 0:2d0ef4830603 341 while (length--) {
cpm219 0:2d0ef4830603 342 Transfer8( *buffer);
cpm219 0:2d0ef4830603 343 buffer++;
cpm219 0:2d0ef4830603 344 SizeTransfered ++;
cpm219 0:2d0ef4830603 345 }
cpm219 0:2d0ef4830603 346 length = SizeTransfered;
cpm219 0:2d0ef4830603 347
cpm219 0:2d0ef4830603 348 EndTransfer( );
cpm219 0:2d0ef4830603 349 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 350
cpm219 0:2d0ef4830603 351 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 352
cpm219 0:2d0ef4830603 353 count -= length;
cpm219 0:2d0ef4830603 354 }while (count > 0);
cpm219 0:2d0ef4830603 355 }
cpm219 0:2d0ef4830603 356
cpm219 0:2d0ef4830603 357
cpm219 0:2d0ef4830603 358 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 359 {
cpm219 0:2d0ef4830603 360 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 361
cpm219 0:2d0ef4830603 362 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 363 do {
cpm219 0:2d0ef4830603 364 length = count;
cpm219 0:2d0ef4830603 365 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 366 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 367 }
cpm219 0:2d0ef4830603 368 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 369
cpm219 0:2d0ef4830603 370 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 371
cpm219 0:2d0ef4830603 372
cpm219 0:2d0ef4830603 373 SizeTransfered = 0;
cpm219 0:2d0ef4830603 374 while (length--) {
cpm219 0:2d0ef4830603 375 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 376 buffer++;
cpm219 0:2d0ef4830603 377 SizeTransfered ++;
cpm219 0:2d0ef4830603 378 }
cpm219 0:2d0ef4830603 379 length = SizeTransfered;
cpm219 0:2d0ef4830603 380
cpm219 0:2d0ef4830603 381 EndTransfer( );
cpm219 0:2d0ef4830603 382 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 383
cpm219 0:2d0ef4830603 384 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 385
cpm219 0:2d0ef4830603 386 count -= length;
cpm219 0:2d0ef4830603 387 }while (count > 0);
cpm219 0:2d0ef4830603 388 }
cpm219 0:2d0ef4830603 389
cpm219 0:2d0ef4830603 390
cpm219 0:2d0ef4830603 391 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
cpm219 0:2d0ef4830603 392 {
cpm219 0:2d0ef4830603 393 ft_uint16_t getfreespace;
cpm219 0:2d0ef4830603 394 do{
cpm219 0:2d0ef4830603 395 getfreespace = fifo_Freespace( );
cpm219 0:2d0ef4830603 396 }while(getfreespace < count);
cpm219 0:2d0ef4830603 397 }
cpm219 0:2d0ef4830603 398
cpm219 0:2d0ef4830603 399 ft_void_t FT800::WaitCmdfifo_empty( )
cpm219 0:2d0ef4830603 400 {
cpm219 0:2d0ef4830603 401 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
cpm219 0:2d0ef4830603 402
cpm219 0:2d0ef4830603 403 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 404 }
cpm219 0:2d0ef4830603 405
cpm219 0:2d0ef4830603 406 ft_void_t FT800::WaitLogo_Finish( )
cpm219 0:2d0ef4830603 407 {
cpm219 0:2d0ef4830603 408 ft_int16_t cmdrdptr,cmdwrptr;
cpm219 0:2d0ef4830603 409
cpm219 0:2d0ef4830603 410 do{
cpm219 0:2d0ef4830603 411 cmdrdptr = Rd16( REG_CMD_READ);
cpm219 0:2d0ef4830603 412 cmdwrptr = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 413 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
cpm219 0:2d0ef4830603 414 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 415 }
cpm219 0:2d0ef4830603 416
cpm219 0:2d0ef4830603 417
cpm219 0:2d0ef4830603 418 ft_void_t FT800::ResetCmdFifo( )
cpm219 0:2d0ef4830603 419 {
cpm219 0:2d0ef4830603 420 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 421 }
cpm219 0:2d0ef4830603 422
cpm219 0:2d0ef4830603 423
cpm219 0:2d0ef4830603 424 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
cpm219 0:2d0ef4830603 425 {
cpm219 0:2d0ef4830603 426 CheckCmdBuffer( sizeof(cmd));
cpm219 0:2d0ef4830603 427
cpm219 0:2d0ef4830603 428 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
cpm219 0:2d0ef4830603 429
cpm219 0:2d0ef4830603 430 Updatecmdfifo( sizeof(cmd));
cpm219 0:2d0ef4830603 431 }
cpm219 0:2d0ef4830603 432
cpm219 0:2d0ef4830603 433
cpm219 0:2d0ef4830603 434 ft_void_t FT800::ResetDLBuffer( )
cpm219 0:2d0ef4830603 435 {
cpm219 0:2d0ef4830603 436 dl_buff_wp = 0;
cpm219 0:2d0ef4830603 437 }
cpm219 0:2d0ef4830603 438
cpm219 0:2d0ef4830603 439 /* Toggle PD_N pin of FT800 board for a power cycle*/
cpm219 0:2d0ef4830603 440 ft_void_t FT800::Powercycle( ft_bool_t up)
cpm219 0:2d0ef4830603 441 {
cpm219 0:2d0ef4830603 442 if (up)
cpm219 0:2d0ef4830603 443 {
cpm219 0:2d0ef4830603 444 //Toggle PD_N from low to high for power up switch
cpm219 0:2d0ef4830603 445 _pd = 0;
cpm219 0:2d0ef4830603 446 Sleep(20);
cpm219 0:2d0ef4830603 447
cpm219 0:2d0ef4830603 448 _pd = 1;
cpm219 0:2d0ef4830603 449 Sleep(20);
cpm219 0:2d0ef4830603 450 }else
cpm219 0:2d0ef4830603 451 {
cpm219 0:2d0ef4830603 452 //Toggle PD_N from high to low for power down switch
cpm219 0:2d0ef4830603 453 _pd = 1;
cpm219 0:2d0ef4830603 454 Sleep(20);
cpm219 0:2d0ef4830603 455
cpm219 0:2d0ef4830603 456 _pd = 0;
cpm219 0:2d0ef4830603 457 Sleep(20);
cpm219 0:2d0ef4830603 458 }
cpm219 0:2d0ef4830603 459 }
cpm219 0:2d0ef4830603 460
cpm219 0:2d0ef4830603 461 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 462 {
cpm219 0:2d0ef4830603 463 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 464
cpm219 0:2d0ef4830603 465 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 466
cpm219 0:2d0ef4830603 467 while (length--) {
cpm219 0:2d0ef4830603 468 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 469 buffer++;
cpm219 0:2d0ef4830603 470 }
cpm219 0:2d0ef4830603 471
cpm219 0:2d0ef4830603 472 EndTransfer( );
cpm219 0:2d0ef4830603 473 }
cpm219 0:2d0ef4830603 474
cpm219 0:2d0ef4830603 475 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 476 {
cpm219 0:2d0ef4830603 477 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 478
cpm219 0:2d0ef4830603 479 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 480
cpm219 0:2d0ef4830603 481 while (length--) {
cpm219 0:2d0ef4830603 482 Transfer8( *buffer);
cpm219 0:2d0ef4830603 483 buffer++;
cpm219 0:2d0ef4830603 484 }
cpm219 0:2d0ef4830603 485
cpm219 0:2d0ef4830603 486 EndTransfer( );
cpm219 0:2d0ef4830603 487 }
cpm219 0:2d0ef4830603 488
cpm219 0:2d0ef4830603 489
cpm219 0:2d0ef4830603 490 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 491 {
cpm219 0:2d0ef4830603 492 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 493
cpm219 0:2d0ef4830603 494 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 495
cpm219 0:2d0ef4830603 496 while (length--) {
cpm219 0:2d0ef4830603 497 *buffer = Transfer8( 0);
cpm219 0:2d0ef4830603 498 buffer++;
cpm219 0:2d0ef4830603 499 }
cpm219 0:2d0ef4830603 500
cpm219 0:2d0ef4830603 501 EndTransfer( );
cpm219 0:2d0ef4830603 502 }
cpm219 0:2d0ef4830603 503
cpm219 0:2d0ef4830603 504 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
cpm219 0:2d0ef4830603 505 {
cpm219 0:2d0ef4830603 506 ft_int16_t Length;
cpm219 0:2d0ef4830603 507 ft_char8_t *pdst,charval;
cpm219 0:2d0ef4830603 508 ft_int32_t CurrVal = value,tmpval,i;
cpm219 0:2d0ef4830603 509 ft_char8_t tmparray[16],idx = 0;
cpm219 0:2d0ef4830603 510
cpm219 0:2d0ef4830603 511 Length = strlen(pSrc);
cpm219 0:2d0ef4830603 512 pdst = pSrc + Length;
cpm219 0:2d0ef4830603 513
cpm219 0:2d0ef4830603 514 if(0 == value)
cpm219 0:2d0ef4830603 515 {
cpm219 0:2d0ef4830603 516 *pdst++ = '0';
cpm219 0:2d0ef4830603 517 *pdst++ = '\0';
cpm219 0:2d0ef4830603 518 return 0;
cpm219 0:2d0ef4830603 519 }
cpm219 0:2d0ef4830603 520
cpm219 0:2d0ef4830603 521 if(CurrVal < 0)
cpm219 0:2d0ef4830603 522 {
cpm219 0:2d0ef4830603 523 *pdst++ = '-';
cpm219 0:2d0ef4830603 524 CurrVal = - CurrVal;
cpm219 0:2d0ef4830603 525 }
cpm219 0:2d0ef4830603 526 /* insert the value */
cpm219 0:2d0ef4830603 527 while(CurrVal > 0){
cpm219 0:2d0ef4830603 528 tmpval = CurrVal;
cpm219 0:2d0ef4830603 529 CurrVal /= 10;
cpm219 0:2d0ef4830603 530 tmpval = tmpval - CurrVal*10;
cpm219 0:2d0ef4830603 531 charval = '0' + tmpval;
cpm219 0:2d0ef4830603 532 tmparray[idx++] = charval;
cpm219 0:2d0ef4830603 533 }
cpm219 0:2d0ef4830603 534
cpm219 0:2d0ef4830603 535 for(i=0;i<idx;i++)
cpm219 0:2d0ef4830603 536 {
cpm219 0:2d0ef4830603 537 *pdst++ = tmparray[idx - i - 1];
cpm219 0:2d0ef4830603 538 }
cpm219 0:2d0ef4830603 539 *pdst++ = '\0';
cpm219 0:2d0ef4830603 540
cpm219 0:2d0ef4830603 541 return 0;
cpm219 0:2d0ef4830603 542 }
cpm219 0:2d0ef4830603 543
cpm219 0:2d0ef4830603 544
cpm219 0:2d0ef4830603 545 ft_void_t FT800::Sleep(ft_uint16_t ms)
cpm219 0:2d0ef4830603 546 {
cpm219 0:2d0ef4830603 547 wait_ms(ms);
cpm219 0:2d0ef4830603 548 }
cpm219 0:2d0ef4830603 549
cpm219 0:2d0ef4830603 550 ft_void_t FT800::Sound_ON(){
cpm219 0:2d0ef4830603 551 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 552 }
cpm219 0:2d0ef4830603 553
cpm219 0:2d0ef4830603 554 ft_void_t FT800::Sound_OFF(){
cpm219 0:2d0ef4830603 555 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 556 }
cpm219 0:2d0ef4830603 557
cpm219 0:2d0ef4830603 558
cpm219 0:2d0ef4830603 559
cpm219 0:2d0ef4830603 560