Denis Nyzovets / FT810_DISCO-F429ZI

Library for FT810 EVE chip

Fork of FT810 by Curtis Mattull

src/FT_GPU_Hal.cpp@11:435747a1f2ae, 2017-09-16 (annotated)

Committer:
mozillain
Date:
Sat Sep 16 23:40:11 2017 +0000
Revision:
11:435747a1f2ae
Parent:
10:4c10e6aeb239 
test2

Who changed what in which revision?

UserRevisionLine numberNew contents of line
cpm219 0:2d0ef4830603 1 #include "FT_Platform.h"
cpm219 0:2d0ef4830603 2 #include "mbed.h"
cpm219 0:2d0ef4830603 3 #include "FT_LCD_Type.h"
cpm219 0:2d0ef4830603 4
cpm219 0:2d0ef4830603 5 FT800::FT800(PinName mosi,
cpm219 0:2d0ef4830603 6 PinName miso,
cpm219 0:2d0ef4830603 7 PinName sck,
cpm219 0:2d0ef4830603 8 PinName ss,
cpm219 0:2d0ef4830603 9 PinName intr,
cpm219 0:2d0ef4830603 10 PinName pd)
cpm219 0:2d0ef4830603 11 :
cpm219 5:506e2de9a9e6 12
cpm219 0:2d0ef4830603 13 _spi(mosi, miso, sck),
cpm219 0:2d0ef4830603 14 _ss(ss),
cpm219 0:2d0ef4830603 15 _pd(pd),
cpm219 0:2d0ef4830603 16 _f800_isr(InterruptIn(intr))
cpm219 0:2d0ef4830603 17 {
cpm219 0:2d0ef4830603 18 _spi.format(8,0); // 8 bit spi mode 0
cpm219 6:ce30c1530d71 19 _spi.frequency(1000000); // start with 10 Mhz SPI clock
cpm219 0:2d0ef4830603 20 _ss = 1; // cs high
cpm219 0:2d0ef4830603 21 _pd = 1; // PD high
cpm219 0:2d0ef4830603 22 Bootup();
cpm219 0:2d0ef4830603 23 }
cpm219 0:2d0ef4830603 24
cpm219 0:2d0ef4830603 25
cpm219 0:2d0ef4830603 26 ft_bool_t FT800::Bootup(void){
mozillain 10:4c10e6aeb239 27 //pc.printf("Bootup() entered\r\n");
cpm219 0:2d0ef4830603 28 Open();
cpm219 5:506e2de9a9e6 29
cpm219 0:2d0ef4830603 30 BootupConfig();
cpm219 0:2d0ef4830603 31
cpm219 0:2d0ef4830603 32 return(1);
cpm219 0:2d0ef4830603 33 }
cpm219 0:2d0ef4830603 34
cpm219 0:2d0ef4830603 35
cpm219 0:2d0ef4830603 36 ft_void_t FT800::BootupConfig(void){
cpm219 0:2d0ef4830603 37 ft_uint8_t chipid;
cpm219 0:2d0ef4830603 38 /* Do a power cycle for safer side */
cpm219 0:2d0ef4830603 39 Powercycle( FT_TRUE);
mozillain 11:435747a1f2ae 40 HostCommand(FT_GPU_EXTERNAL_OSC);
cpm219 0:2d0ef4830603 41 HostCommand( FT_GPU_ACTIVE_M);
cpm219 0:2d0ef4830603 42
mozillain 11:435747a1f2ae 43 //Read Register ID to check if FT811 is ready.
mozillain 11:435747a1f2ae 44 chipid = Rd8(REG_ID);
cpm219 0:2d0ef4830603 45 while(chipid != 0x7C)
mozillain 10:4c10e6aeb239 46
mozillain 11:435747a1f2ae 47
cpm219 0:2d0ef4830603 48 /* Configuration of LCD display */
cpm219 0:2d0ef4830603 49 DispHCycle = my_DispHCycle;
cpm219 0:2d0ef4830603 50 Wr16( REG_HCYCLE, DispHCycle);
cpm219 0:2d0ef4830603 51 DispHOffset = my_DispHOffset;
cpm219 0:2d0ef4830603 52 Wr16( REG_HOFFSET, DispHOffset);
cpm219 0:2d0ef4830603 53 DispWidth = my_DispWidth;
cpm219 0:2d0ef4830603 54 Wr16( REG_HSIZE, DispWidth);
cpm219 0:2d0ef4830603 55 DispHSync0 = my_DispHSync0;
cpm219 0:2d0ef4830603 56 Wr16( REG_HSYNC0, DispHSync0);
cpm219 0:2d0ef4830603 57 DispHSync1 = my_DispHSync1;
cpm219 0:2d0ef4830603 58 Wr16( REG_HSYNC1, DispHSync1);
cpm219 0:2d0ef4830603 59 DispVCycle = my_DispVCycle;
cpm219 0:2d0ef4830603 60 Wr16( REG_VCYCLE, DispVCycle);
cpm219 0:2d0ef4830603 61 DispVOffset = my_DispVOffset;
cpm219 0:2d0ef4830603 62 Wr16( REG_VOFFSET, DispVOffset);
cpm219 0:2d0ef4830603 63 DispHeight = my_DispHeight;
cpm219 0:2d0ef4830603 64 Wr16( REG_VSIZE, DispHeight);
cpm219 0:2d0ef4830603 65 DispVSync0 = my_DispVSync0;
cpm219 0:2d0ef4830603 66 Wr16( REG_VSYNC0, DispVSync0);
cpm219 0:2d0ef4830603 67 DispVSync1 = my_DispVSync1;
cpm219 0:2d0ef4830603 68 Wr16( REG_VSYNC1, DispVSync1);
cpm219 0:2d0ef4830603 69 DispSwizzle = my_DispSwizzle;
cpm219 0:2d0ef4830603 70 Wr8( REG_SWIZZLE, DispSwizzle);
cpm219 0:2d0ef4830603 71 DispPCLKPol = my_DispPCLKPol;
cpm219 0:2d0ef4830603 72 Wr8( REG_PCLK_POL, DispPCLKPol);
mozillain 10:4c10e6aeb239 73 Wr8( REG_CSPREAD, 0);
cpm219 0:2d0ef4830603 74 DispPCLK = my_DispPCLK;
cpm219 0:2d0ef4830603 75 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
mozillain 10:4c10e6aeb239 76
mozillain 11:435747a1f2ae 77 // Speed up
mozillain 11:435747a1f2ae 78 _spi.frequency(30000000); // 30 Mhz SPI clock DC
mozillain 11:435747a1f2ae 79 // _spi.frequency(20000000); // 20 Mhz SPI clock DC
mozillain 11:435747a1f2ae 80 // _spi.frequency(12000000); // 12 Mhz SPI clock
mozillain 11:435747a1f2ae 81
mozillain 10:4c10e6aeb239 82 ft_uint8_t temp = Rd8(REG_PCLK);
mozillain 10:4c10e6aeb239 83 if (temp!=DispPCLK){DigitalOut led(LED1); led=1;}
mozillain 10:4c10e6aeb239 84 Serial pc(SERIAL_TX, SERIAL_RX);
mozillain 10:4c10e6aeb239 85 ft_uint8_t chipid1 = Rd8(0x0C0000);
mozillain 10:4c10e6aeb239 86 pc.printf("ID:%08X\n", chipid1);
cpm219 0:2d0ef4830603 87
cpm219 4:03932ce8a04e 88 Wr16( REG_PWM_HZ, 10000);
mozillain 10:4c10e6aeb239 89 pc.printf("ID:%08X\n", Rd16(REG_PWM_HZ));
mozillain 11:435747a1f2ae 90
cpm219 5:506e2de9a9e6 91 Wr16( REG_PWM_DUTY, 127);
mozillain 11:435747a1f2ae 92 //Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
mozillain 11:435747a1f2ae 93 //Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
mozillain 11:435747a1f2ae 94 Wr8( REG_GPIO_DIR,0x82| Rd8( REG_GPIO_DIR));
mozillain 11:435747a1f2ae 95 Wr8( REG_GPIO,0x80| Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 96
cpm219 0:2d0ef4830603 97 Wr32( RAM_DL, CLEAR(1,1,1));
cpm219 0:2d0ef4830603 98 Wr32( RAM_DL+4, DISPLAY());
cpm219 0:2d0ef4830603 99 Wr32( REG_DLSWAP,1);
cpm219 0:2d0ef4830603 100
cpm219 0:2d0ef4830603 101 Wr16( REG_PCLK, DispPCLK);
cpm219 0:2d0ef4830603 102
cpm219 0:2d0ef4830603 103 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
mozillain 10:4c10e6aeb239 104 Wr16( REG_TOUCH_RZTHRESH,1200);
cpm219 0:2d0ef4830603 105 }
cpm219 0:2d0ef4830603 106
cpm219 0:2d0ef4830603 107
cpm219 0:2d0ef4830603 108
cpm219 0:2d0ef4830603 109 /* API to initialize the SPI interface */
cpm219 0:2d0ef4830603 110 ft_bool_t FT800::Init()
cpm219 0:2d0ef4830603 111 {
cpm219 0:2d0ef4830603 112 // is done in constructor
cpm219 0:2d0ef4830603 113 return 1;
cpm219 0:2d0ef4830603 114 }
cpm219 0:2d0ef4830603 115
cpm219 0:2d0ef4830603 116
cpm219 0:2d0ef4830603 117 ft_bool_t FT800::Open()
cpm219 0:2d0ef4830603 118 {
cpm219 0:2d0ef4830603 119 cmd_fifo_wp = dl_buff_wp = 0;
cpm219 0:2d0ef4830603 120 status = OPENED;
cpm219 0:2d0ef4830603 121 return 1;
cpm219 0:2d0ef4830603 122 }
cpm219 0:2d0ef4830603 123
cpm219 0:2d0ef4830603 124 ft_void_t FT800::Close( )
cpm219 0:2d0ef4830603 125 {
cpm219 0:2d0ef4830603 126 status = CLOSED;
cpm219 0:2d0ef4830603 127 }
cpm219 0:2d0ef4830603 128
cpm219 0:2d0ef4830603 129 ft_void_t FT800::DeInit()
cpm219 0:2d0ef4830603 130 {
cpm219 0:2d0ef4830603 131
cpm219 0:2d0ef4830603 132 }
cpm219 0:2d0ef4830603 133
cpm219 0:2d0ef4830603 134 /*The APIs for reading/writing transfer continuously only with small buffer system*/
cpm219 0:2d0ef4830603 135 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
cpm219 0:2d0ef4830603 136 {
cpm219 0:2d0ef4830603 137 if (FT_GPU_READ == rw){
cpm219 0:2d0ef4830603 138 _ss = 0; // cs low
cpm219 0:2d0ef4830603 139 _spi.write(addr >> 16);
cpm219 0:2d0ef4830603 140 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 141 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 142 _spi.write(0); //Dummy Read Byte
cpm219 0:2d0ef4830603 143 status = READING;
cpm219 0:2d0ef4830603 144 }else{
cpm219 0:2d0ef4830603 145 _ss = 0; // cs low
cpm219 0:2d0ef4830603 146 _spi.write(0x80 | (addr >> 16));
cpm219 0:2d0ef4830603 147 _spi.write(addr >> 8);
cpm219 0:2d0ef4830603 148 _spi.write(addr & 0xff);
cpm219 0:2d0ef4830603 149 status = WRITING;
cpm219 0:2d0ef4830603 150 }
cpm219 0:2d0ef4830603 151 }
cpm219 0:2d0ef4830603 152
cpm219 0:2d0ef4830603 153
cpm219 0:2d0ef4830603 154 /*The APIs for writing transfer continuously only*/
cpm219 0:2d0ef4830603 155 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
cpm219 0:2d0ef4830603 156 {
cpm219 0:2d0ef4830603 157 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
cpm219 0:2d0ef4830603 158 }
cpm219 0:2d0ef4830603 159
cpm219 0:2d0ef4830603 160 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
cpm219 0:2d0ef4830603 161 {
cpm219 0:2d0ef4830603 162 ft_uint16_t length = strlen(string);
cpm219 0:2d0ef4830603 163 while(length --){
cpm219 0:2d0ef4830603 164 Transfer8( *string);
cpm219 0:2d0ef4830603 165 string ++;
cpm219 0:2d0ef4830603 166 }
cpm219 0:2d0ef4830603 167 //Append one null as ending flag
cpm219 0:2d0ef4830603 168 Transfer8( 0);
cpm219 0:2d0ef4830603 169 return(1);
cpm219 0:2d0ef4830603 170 }
cpm219 0:2d0ef4830603 171
cpm219 0:2d0ef4830603 172
cpm219 0:2d0ef4830603 173 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
cpm219 0:2d0ef4830603 174 {
cpm219 0:2d0ef4830603 175 return _spi.write(value);
cpm219 0:2d0ef4830603 176 }
cpm219 0:2d0ef4830603 177
cpm219 0:2d0ef4830603 178
cpm219 0:2d0ef4830603 179 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
cpm219 0:2d0ef4830603 180 {
cpm219 0:2d0ef4830603 181 ft_uint16_t retVal = 0;
cpm219 0:2d0ef4830603 182
cpm219 0:2d0ef4830603 183 if (status == WRITING){
cpm219 0:2d0ef4830603 184 Transfer8( value & 0xFF);//LSB first
cpm219 0:2d0ef4830603 185 Transfer8( (value >> 8) & 0xFF);
cpm219 0:2d0ef4830603 186 }else{
cpm219 0:2d0ef4830603 187 retVal = Transfer8( 0);
cpm219 0:2d0ef4830603 188 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
cpm219 0:2d0ef4830603 189 }
cpm219 0:2d0ef4830603 190
cpm219 0:2d0ef4830603 191 return retVal;
cpm219 0:2d0ef4830603 192 }
cpm219 0:2d0ef4830603 193
cpm219 0:2d0ef4830603 194 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
cpm219 0:2d0ef4830603 195 {
cpm219 0:2d0ef4830603 196 ft_uint32_t retVal = 0;
cpm219 0:2d0ef4830603 197 if (status == WRITING){
cpm219 0:2d0ef4830603 198 Transfer16( value & 0xFFFF);//LSB first
cpm219 0:2d0ef4830603 199 Transfer16( (value >> 16) & 0xFFFF);
cpm219 0:2d0ef4830603 200 }else{
cpm219 0:2d0ef4830603 201 retVal = Transfer16( 0);
cpm219 0:2d0ef4830603 202 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
cpm219 0:2d0ef4830603 203 }
cpm219 0:2d0ef4830603 204 return retVal;
cpm219 0:2d0ef4830603 205 }
cpm219 0:2d0ef4830603 206
cpm219 0:2d0ef4830603 207 ft_void_t FT800::EndTransfer( )
cpm219 0:2d0ef4830603 208 {
cpm219 0:2d0ef4830603 209 _ss = 1;
cpm219 0:2d0ef4830603 210 status = OPENED;
cpm219 0:2d0ef4830603 211 }
cpm219 0:2d0ef4830603 212
cpm219 0:2d0ef4830603 213
cpm219 0:2d0ef4830603 214 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
cpm219 0:2d0ef4830603 215 {
cpm219 0:2d0ef4830603 216 ft_uint8_t value;
cpm219 0:2d0ef4830603 217 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 218 value = Transfer8( 0);
cpm219 0:2d0ef4830603 219 EndTransfer( );
cpm219 0:2d0ef4830603 220 return value;
cpm219 0:2d0ef4830603 221 }
cpm219 0:2d0ef4830603 222 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
cpm219 0:2d0ef4830603 223 {
cpm219 0:2d0ef4830603 224 ft_uint16_t value;
cpm219 0:2d0ef4830603 225 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 226 value = Transfer16( 0);
cpm219 0:2d0ef4830603 227 EndTransfer( );
cpm219 0:2d0ef4830603 228 return value;
cpm219 0:2d0ef4830603 229 }
cpm219 0:2d0ef4830603 230 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
cpm219 0:2d0ef4830603 231 {
cpm219 0:2d0ef4830603 232 ft_uint32_t value;
cpm219 0:2d0ef4830603 233 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 234 value = Transfer32( 0);
cpm219 0:2d0ef4830603 235 EndTransfer( );
cpm219 0:2d0ef4830603 236 return value;
cpm219 0:2d0ef4830603 237 }
cpm219 0:2d0ef4830603 238
cpm219 0:2d0ef4830603 239 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
cpm219 0:2d0ef4830603 240 {
cpm219 0:2d0ef4830603 241 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 242 Transfer8( v);
cpm219 0:2d0ef4830603 243 EndTransfer( );
cpm219 0:2d0ef4830603 244 }
cpm219 0:2d0ef4830603 245 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
cpm219 0:2d0ef4830603 246 {
cpm219 0:2d0ef4830603 247 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 248 Transfer16( v);
cpm219 0:2d0ef4830603 249 EndTransfer( );
cpm219 0:2d0ef4830603 250 }
cpm219 0:2d0ef4830603 251 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
cpm219 0:2d0ef4830603 252 {
cpm219 0:2d0ef4830603 253 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 254 Transfer32( v);
cpm219 0:2d0ef4830603 255 EndTransfer( );
cpm219 0:2d0ef4830603 256 }
cpm219 0:2d0ef4830603 257
cpm219 0:2d0ef4830603 258 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
cpm219 0:2d0ef4830603 259 {
cpm219 0:2d0ef4830603 260 _ss = 0;
cpm219 0:2d0ef4830603 261 _spi.write(cmd);
cpm219 0:2d0ef4830603 262 _spi.write(0);
cpm219 0:2d0ef4830603 263 _spi.write(0);
cpm219 0:2d0ef4830603 264 _ss = 1;
cpm219 0:2d0ef4830603 265 }
cpm219 0:2d0ef4830603 266
cpm219 0:2d0ef4830603 267 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
cpm219 0:2d0ef4830603 268 {
cpm219 0:2d0ef4830603 269 HostCommand( pllsource);
cpm219 0:2d0ef4830603 270 }
cpm219 0:2d0ef4830603 271
cpm219 0:2d0ef4830603 272 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
cpm219 0:2d0ef4830603 273 {
cpm219 0:2d0ef4830603 274 HostCommand( freq);
cpm219 0:2d0ef4830603 275 }
cpm219 0:2d0ef4830603 276
cpm219 0:2d0ef4830603 277 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
cpm219 0:2d0ef4830603 278 {
cpm219 0:2d0ef4830603 279 HostCommand( pwrmode);
cpm219 0:2d0ef4830603 280 }
cpm219 0:2d0ef4830603 281
cpm219 0:2d0ef4830603 282 ft_void_t FT800::CoreReset( )
cpm219 0:2d0ef4830603 283 {
cpm219 0:2d0ef4830603 284 HostCommand( 0x68);
cpm219 0:2d0ef4830603 285 }
cpm219 0:2d0ef4830603 286
cpm219 0:2d0ef4830603 287
cpm219 0:2d0ef4830603 288 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
cpm219 0:2d0ef4830603 289 {
cpm219 0:2d0ef4830603 290 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
cpm219 0:2d0ef4830603 291 //4 byte alignment
cpm219 0:2d0ef4830603 292 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
cpm219 0:2d0ef4830603 293 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
cpm219 0:2d0ef4830603 294 }
cpm219 0:2d0ef4830603 295
cpm219 0:2d0ef4830603 296
cpm219 0:2d0ef4830603 297 ft_uint16_t FT800::fifo_Freespace( )
cpm219 0:2d0ef4830603 298 {
cpm219 0:2d0ef4830603 299 ft_uint16_t fullness,retval;
cpm219 0:2d0ef4830603 300
cpm219 0:2d0ef4830603 301 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
cpm219 0:2d0ef4830603 302 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
cpm219 0:2d0ef4830603 303 return (retval);
cpm219 0:2d0ef4830603 304 }
cpm219 0:2d0ef4830603 305
cpm219 0:2d0ef4830603 306 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 307 {
cpm219 0:2d0ef4830603 308 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 309
cpm219 0:2d0ef4830603 310 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 311 do {
cpm219 0:2d0ef4830603 312 length = count;
cpm219 0:2d0ef4830603 313 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 314 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 315 }
cpm219 0:2d0ef4830603 316 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 317
cpm219 0:2d0ef4830603 318 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 319
cpm219 0:2d0ef4830603 320 SizeTransfered = 0;
cpm219 0:2d0ef4830603 321 while (length--) {
cpm219 0:2d0ef4830603 322 Transfer8( *buffer);
cpm219 0:2d0ef4830603 323 buffer++;
cpm219 0:2d0ef4830603 324 SizeTransfered ++;
cpm219 0:2d0ef4830603 325 }
cpm219 0:2d0ef4830603 326 length = SizeTransfered;
cpm219 0:2d0ef4830603 327
cpm219 0:2d0ef4830603 328 EndTransfer( );
cpm219 0:2d0ef4830603 329 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 330
cpm219 0:2d0ef4830603 331 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 332
cpm219 0:2d0ef4830603 333 count -= length;
cpm219 0:2d0ef4830603 334 }while (count > 0);
cpm219 0:2d0ef4830603 335 }
cpm219 0:2d0ef4830603 336
cpm219 0:2d0ef4830603 337
cpm219 0:2d0ef4830603 338 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
cpm219 0:2d0ef4830603 339 {
cpm219 0:2d0ef4830603 340 ft_uint32_t length =0, SizeTransfered = 0;
cpm219 0:2d0ef4830603 341
cpm219 0:2d0ef4830603 342 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
cpm219 0:2d0ef4830603 343 do {
cpm219 0:2d0ef4830603 344 length = count;
cpm219 0:2d0ef4830603 345 if (length > MAX_CMD_FIFO_TRANSFER){
cpm219 0:2d0ef4830603 346 length = MAX_CMD_FIFO_TRANSFER;
cpm219 0:2d0ef4830603 347 }
cpm219 0:2d0ef4830603 348 CheckCmdBuffer( length);
cpm219 0:2d0ef4830603 349
cpm219 0:2d0ef4830603 350 StartCmdTransfer( FT_GPU_WRITE,length);
cpm219 0:2d0ef4830603 351
cpm219 0:2d0ef4830603 352
cpm219 0:2d0ef4830603 353 SizeTransfered = 0;
cpm219 0:2d0ef4830603 354 while (length--) {
cpm219 0:2d0ef4830603 355 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 356 buffer++;
cpm219 0:2d0ef4830603 357 SizeTransfered ++;
cpm219 0:2d0ef4830603 358 }
cpm219 0:2d0ef4830603 359 length = SizeTransfered;
cpm219 0:2d0ef4830603 360
cpm219 0:2d0ef4830603 361 EndTransfer( );
cpm219 0:2d0ef4830603 362 Updatecmdfifo( length);
cpm219 0:2d0ef4830603 363
cpm219 0:2d0ef4830603 364 WaitCmdfifo_empty( );
cpm219 0:2d0ef4830603 365
cpm219 0:2d0ef4830603 366 count -= length;
cpm219 0:2d0ef4830603 367 }while (count > 0);
cpm219 0:2d0ef4830603 368 }
cpm219 0:2d0ef4830603 369
cpm219 0:2d0ef4830603 370
cpm219 0:2d0ef4830603 371 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
cpm219 0:2d0ef4830603 372 {
cpm219 0:2d0ef4830603 373 ft_uint16_t getfreespace;
cpm219 0:2d0ef4830603 374 do{
cpm219 0:2d0ef4830603 375 getfreespace = fifo_Freespace( );
cpm219 0:2d0ef4830603 376 }while(getfreespace < count);
cpm219 0:2d0ef4830603 377 }
cpm219 0:2d0ef4830603 378
cpm219 0:2d0ef4830603 379 ft_void_t FT800::WaitCmdfifo_empty( )
cpm219 0:2d0ef4830603 380 {
cpm219 0:2d0ef4830603 381 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
cpm219 0:2d0ef4830603 382
cpm219 0:2d0ef4830603 383 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 384 }
cpm219 0:2d0ef4830603 385
cpm219 0:2d0ef4830603 386 ft_void_t FT800::WaitLogo_Finish( )
cpm219 0:2d0ef4830603 387 {
cpm219 0:2d0ef4830603 388 ft_int16_t cmdrdptr,cmdwrptr;
cpm219 0:2d0ef4830603 389
cpm219 0:2d0ef4830603 390 do{
cpm219 0:2d0ef4830603 391 cmdrdptr = Rd16( REG_CMD_READ);
cpm219 0:2d0ef4830603 392 cmdwrptr = Rd16( REG_CMD_WRITE);
cpm219 0:2d0ef4830603 393 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
cpm219 0:2d0ef4830603 394 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 395 }
cpm219 0:2d0ef4830603 396
cpm219 0:2d0ef4830603 397
cpm219 0:2d0ef4830603 398 ft_void_t FT800::ResetCmdFifo( )
cpm219 0:2d0ef4830603 399 {
cpm219 0:2d0ef4830603 400 cmd_fifo_wp = 0;
cpm219 0:2d0ef4830603 401 }
cpm219 0:2d0ef4830603 402
cpm219 0:2d0ef4830603 403
cpm219 0:2d0ef4830603 404 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
cpm219 0:2d0ef4830603 405 {
cpm219 0:2d0ef4830603 406 CheckCmdBuffer( sizeof(cmd));
cpm219 0:2d0ef4830603 407
cpm219 0:2d0ef4830603 408 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
cpm219 0:2d0ef4830603 409
cpm219 0:2d0ef4830603 410 Updatecmdfifo( sizeof(cmd));
cpm219 0:2d0ef4830603 411 }
cpm219 0:2d0ef4830603 412
cpm219 0:2d0ef4830603 413
cpm219 0:2d0ef4830603 414 ft_void_t FT800::ResetDLBuffer( )
cpm219 0:2d0ef4830603 415 {
cpm219 0:2d0ef4830603 416 dl_buff_wp = 0;
cpm219 0:2d0ef4830603 417 }
cpm219 0:2d0ef4830603 418
cpm219 0:2d0ef4830603 419 /* Toggle PD_N pin of FT800 board for a power cycle*/
cpm219 0:2d0ef4830603 420 ft_void_t FT800::Powercycle( ft_bool_t up)
cpm219 0:2d0ef4830603 421 {
cpm219 0:2d0ef4830603 422 if (up)
cpm219 0:2d0ef4830603 423 {
cpm219 0:2d0ef4830603 424 //Toggle PD_N from low to high for power up switch
cpm219 0:2d0ef4830603 425 _pd = 0;
cpm219 0:2d0ef4830603 426 Sleep(20);
cpm219 0:2d0ef4830603 427
cpm219 0:2d0ef4830603 428 _pd = 1;
cpm219 0:2d0ef4830603 429 Sleep(20);
cpm219 0:2d0ef4830603 430 }else
cpm219 0:2d0ef4830603 431 {
cpm219 0:2d0ef4830603 432 //Toggle PD_N from high to low for power down switch
cpm219 0:2d0ef4830603 433 _pd = 1;
cpm219 0:2d0ef4830603 434 Sleep(20);
cpm219 0:2d0ef4830603 435
cpm219 0:2d0ef4830603 436 _pd = 0;
cpm219 0:2d0ef4830603 437 Sleep(20);
cpm219 0:2d0ef4830603 438 }
cpm219 0:2d0ef4830603 439 }
cpm219 0:2d0ef4830603 440
cpm219 0:2d0ef4830603 441 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 442 {
cpm219 0:2d0ef4830603 443 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 444
cpm219 0:2d0ef4830603 445 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 446
cpm219 0:2d0ef4830603 447 while (length--) {
cpm219 0:2d0ef4830603 448 Transfer8( ft_pgm_read_byte_near(buffer));
cpm219 0:2d0ef4830603 449 buffer++;
cpm219 0:2d0ef4830603 450 }
cpm219 0:2d0ef4830603 451
cpm219 0:2d0ef4830603 452 EndTransfer( );
cpm219 0:2d0ef4830603 453 }
cpm219 0:2d0ef4830603 454
cpm219 0:2d0ef4830603 455 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 456 {
cpm219 0:2d0ef4830603 457 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 458
cpm219 0:2d0ef4830603 459 StartTransfer( FT_GPU_WRITE,addr);
cpm219 0:2d0ef4830603 460
cpm219 0:2d0ef4830603 461 while (length--) {
cpm219 0:2d0ef4830603 462 Transfer8( *buffer);
cpm219 0:2d0ef4830603 463 buffer++;
cpm219 0:2d0ef4830603 464 }
cpm219 0:2d0ef4830603 465
cpm219 0:2d0ef4830603 466 EndTransfer( );
cpm219 0:2d0ef4830603 467 }
cpm219 0:2d0ef4830603 468
cpm219 0:2d0ef4830603 469
cpm219 0:2d0ef4830603 470 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
cpm219 0:2d0ef4830603 471 {
cpm219 0:2d0ef4830603 472 //ft_uint32_t SizeTransfered = 0;
cpm219 0:2d0ef4830603 473
cpm219 0:2d0ef4830603 474 StartTransfer( FT_GPU_READ,addr);
cpm219 0:2d0ef4830603 475
cpm219 0:2d0ef4830603 476 while (length--) {
cpm219 0:2d0ef4830603 477 *buffer = Transfer8( 0);
cpm219 0:2d0ef4830603 478 buffer++;
cpm219 0:2d0ef4830603 479 }
cpm219 0:2d0ef4830603 480
cpm219 0:2d0ef4830603 481 EndTransfer( );
cpm219 0:2d0ef4830603 482 }
cpm219 0:2d0ef4830603 483
cpm219 0:2d0ef4830603 484 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
cpm219 0:2d0ef4830603 485 {
cpm219 0:2d0ef4830603 486 ft_int16_t Length;
cpm219 0:2d0ef4830603 487 ft_char8_t *pdst,charval;
cpm219 0:2d0ef4830603 488 ft_int32_t CurrVal = value,tmpval,i;
cpm219 0:2d0ef4830603 489 ft_char8_t tmparray[16],idx = 0;
cpm219 0:2d0ef4830603 490
cpm219 0:2d0ef4830603 491 Length = strlen(pSrc);
cpm219 0:2d0ef4830603 492 pdst = pSrc + Length;
cpm219 0:2d0ef4830603 493
cpm219 0:2d0ef4830603 494 if(0 == value)
cpm219 0:2d0ef4830603 495 {
cpm219 0:2d0ef4830603 496 *pdst++ = '0';
cpm219 0:2d0ef4830603 497 *pdst++ = '\0';
cpm219 0:2d0ef4830603 498 return 0;
cpm219 0:2d0ef4830603 499 }
cpm219 0:2d0ef4830603 500
cpm219 0:2d0ef4830603 501 if(CurrVal < 0)
cpm219 0:2d0ef4830603 502 {
cpm219 0:2d0ef4830603 503 *pdst++ = '-';
cpm219 0:2d0ef4830603 504 CurrVal = - CurrVal;
cpm219 0:2d0ef4830603 505 }
cpm219 0:2d0ef4830603 506 /* insert the value */
cpm219 0:2d0ef4830603 507 while(CurrVal > 0){
cpm219 0:2d0ef4830603 508 tmpval = CurrVal;
cpm219 0:2d0ef4830603 509 CurrVal /= 10;
cpm219 0:2d0ef4830603 510 tmpval = tmpval - CurrVal*10;
cpm219 0:2d0ef4830603 511 charval = '0' + tmpval;
cpm219 0:2d0ef4830603 512 tmparray[idx++] = charval;
cpm219 0:2d0ef4830603 513 }
cpm219 0:2d0ef4830603 514
cpm219 0:2d0ef4830603 515 for(i=0;i<idx;i++)
cpm219 0:2d0ef4830603 516 {
cpm219 0:2d0ef4830603 517 *pdst++ = tmparray[idx - i - 1];
cpm219 0:2d0ef4830603 518 }
cpm219 0:2d0ef4830603 519 *pdst++ = '\0';
cpm219 0:2d0ef4830603 520
cpm219 0:2d0ef4830603 521 return 0;
cpm219 0:2d0ef4830603 522 }
cpm219 0:2d0ef4830603 523
cpm219 0:2d0ef4830603 524
cpm219 0:2d0ef4830603 525 ft_void_t FT800::Sleep(ft_uint16_t ms)
cpm219 0:2d0ef4830603 526 {
cpm219 0:2d0ef4830603 527 wait_ms(ms);
cpm219 0:2d0ef4830603 528 }
cpm219 0:2d0ef4830603 529
cpm219 0:2d0ef4830603 530 ft_void_t FT800::Sound_ON(){
cpm219 0:2d0ef4830603 531 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 532 }
cpm219 0:2d0ef4830603 533
cpm219 0:2d0ef4830603 534 ft_void_t FT800::Sound_OFF(){
cpm219 0:2d0ef4830603 535 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
cpm219 0:2d0ef4830603 536 }
cpm219 0:2d0ef4830603 537
cpm219 0:2d0ef4830603 538
cpm219 0:2d0ef4830603 539
cpm219 0:2d0ef4830603 540