Revision 12:74108436751e, committed 2018-01-24

Comitter:

mozillain

Date:

Wed Jan 24 13:04:36 2018 +0000

Parent:

11:435747a1f2ae

Commit message:

Diff

Changed in this revision

--- a/inc/FT_Gpu.h	Sat Sep 16 23:40:11 2017 +0000
+++ b/inc/FT_Gpu.h	Wed Jan 24 13:04:36 2018 +0000
@@ -1,36 +1,3 @@
-/*
-
-Copyright (c) Future Technology Devices International 2014
-
-THIS SOFTWARE IS PROVIDED BY FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
-OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
-FUTURE TECHNOLOGY DEVICES INTERNATIONAL LIMITED BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
-SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT
-OF SUBSTITUTE GOODS OR SERVICES LOSS OF USE, DATA, OR PROFITS OR BUSINESS INTERRUPTION)
-HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR
-TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
-EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-
-FTDI DRIVERS MAY BE USED ONLY IN CONJUNCTION WITH PRODUCTS BASED ON FTDI PARTS.
-
-FTDI DRIVERS MAY BE DISTRIBUTED IN ANY FORM AS LONG AS LICENSE INFORMATION IS NOT MODIFIED.
-
-IF A CUSTOM VENDOR ID AND/OR PRODUCT ID OR DESCRIPTION STRING ARE USED, IT IS THE
-RESPONSIBILITY OF THE PRODUCT MANUFACTURER TO MAINTAIN ANY CHANGES AND SUBSEQUENT WHQL
-RE-CERTIFICATION AS A RESULT OF MAKING THESE CHANGES.
-
-Author : FTDI 
-
-Revision History: 
-0.1 - date 2013.04.24 - Initial Version
-0.2 - date 2013.08.19 - added few registers.
-1.0 - date 2013.12.10 - Version 1.0.
-2.0 - date 2014.11.24 - version 2.0 which includes support for FT81x series.
-
- 
-*/
-
 #ifndef _FT_GPU_H_
 #define _FT_GPU_H_
 

--- a/inc/FT_LCD_Type.h	Sat Sep 16 23:40:11 2017 +0000
+++ b/inc/FT_LCD_Type.h	Wed Jan 24 13:04:36 2018 +0000
@@ -12,7 +12,7 @@
 #define my_DispVOffset  32
 #define my_DispVSync0  0
 #define my_DispVSync1  3
-#define my_DispPCLK  5 //2
+#define my_DispPCLK  2 //2 or 5
 #define my_DispSwizzle  0
 #define my_DispPCLKPol  1
 #define my_DispCSpread 0

--- a/inc/FT_Platform.h	Sat Sep 16 23:40:11 2017 +0000
+++ b/inc/FT_Platform.h	Wed Jan 24 13:04:36 2018 +0000
@@ -1,31 +1,11 @@
 #ifndef _FT_PLATFORM_H_
 #define _FT_PLATFORM_H_
 
-//#define ARDUINO_PLATFORM
-
-/* Module specific configurations */
-#define VM800P43_50
-
-#ifdef VM800P43_50
-
 #define DISPLAY_RESOLUTION_WVGA                     (1)
 #define FT_811_ENABLE                           (1)
 #define ENABLE_SPI_SINGLE                       (1)
-#define FT_ARDUINO_ATMEGA328P_I2C               (1)
-#define RTC_PRESENT                             (1)
-#define FT800_CS                                (9)
-#define FT_SDCARD_CS                            (8)
-#define FT800_INT                               (3)
-#define FT800_PD_N                              (4)
-#define FT_ARDUINO_PRO_SPI_CS FT800_CS
-#define ARDUINO_PLATFORM_SPI
-#define ARDUINO_PLATFORM_COCMD_BURST
-#define RESISTANCE_THRESHOLD                    (1200)
-#endif
+#define FT_81X_ENABLE                               (1)
 
-#if (defined(FT_810_ENABLE) || defined(FT_811_ENABLE) || defined(FT_812_ENABLE) || defined(FT_813_ENABLE))
-#define FT_81X_ENABLE                               (1)
-#endif
 
 
 /* HAL inclusions */

--- a/src/FT_GPU_Hal.cpp	Sat Sep 16 23:40:11 2017 +0000
+++ b/src/FT_GPU_Hal.cpp	Wed Jan 24 13:04:36 2018 +0000
@@ -37,14 +37,30 @@
     ft_uint8_t chipid;
     /* Do a power cycle for safer side */
     Powercycle( FT_TRUE);
-    HostCommand(FT_GPU_EXTERNAL_OSC);
+    
+    /* Set the clk to external clock */
+    HostCommand( FT_GPU_EXTERNAL_OSC);
+    Sleep(10);
+    
+    /* Access address 0 to wake up the FT800 */
     HostCommand( FT_GPU_ACTIVE_M);
+    Sleep(500);
 
-    //Read Register ID to check if FT811 is ready.
-    chipid = Rd8(REG_ID);
+    /* Switch PLL output to 48MHz */
+//  HostCommand( FT_GPU_PLL_48M);
+    Sleep(10);
+
+    /* Do a core reset for safer side */
+    HostCommand( FT_GPU_CORE_RESET);
+    Sleep(500);
+    //Read Register ID to check if FT800 is ready.
+    chipid = Rd8(  REG_ID);
     while(chipid != 0x7C)
     
-
+    _spi.frequency(30000000);           // 30 Mhz SPI clock DC
+//    _spi.frequency(20000000);           // 20 Mhz SPI clock DC
+//  _spi.frequency(12000000);           // 12 Mhz SPI clock
+    /* Configuration of LCD display */
     /* Configuration of LCD display */
     DispHCycle = my_DispHCycle;
     Wr16(  REG_HCYCLE, DispHCycle);
@@ -73,26 +89,21 @@
     Wr8(  REG_CSPREAD, 0);      
     DispPCLK = my_DispPCLK;
     Wr8(  REG_PCLK, DispPCLK);//after this display is visible on the LCD
-    
-    // Speed up
-    _spi.frequency(30000000);           // 30 Mhz SPI clock DC
-//    _spi.frequency(20000000);           // 20 Mhz SPI clock DC
-//  _spi.frequency(12000000);           // 12 Mhz SPI clock
-    
+
+
     ft_uint8_t temp = Rd8(REG_PCLK);
     if (temp!=DispPCLK){DigitalOut led(LED1); led=1;}
     Serial pc(SERIAL_TX, SERIAL_RX);
-    ft_uint8_t chipid1 = Rd8(0x0C0000);
-    pc.printf("ID:%08X\n", chipid1);
-
-    Wr16(  REG_PWM_HZ, 10000);
-    pc.printf("ID:%08X\n", Rd16(REG_PWM_HZ));
+    pc.printf("ID:%08X\n", Rd8(0x0C0000));
 
-    Wr16(  REG_PWM_DUTY, 127);
-    //Wr8(  REG_GPIO_DIR,0x82);  //| Rd8( REG_GPIO_DIR));
-    //Wr8(  REG_GPIO,0x080);     //| Rd8( REG_GPIO));
-    Wr8(  REG_GPIO_DIR,0x82| Rd8( REG_GPIO_DIR));
-    Wr8(  REG_GPIO,0x80| Rd8( REG_GPIO));
+    Wr16(REG_PWM_HZ, 10000);
+    pc.printf("PWM:%08X\n", Rd16(REG_PWM_HZ));
+    Wr16(REG_PWM_DUTY, 127);
+    Wr8(REG_GPIO_DIR,0x82);
+    Wr8(REG_GPIO,0x82);
+    pc.printf("GPIO:%08X\n", Rd8(REG_GPIO));
+    Wr16(REG_GPIOX_DIR,0x8000);
+    Wr16(REG_GPIOX,0x8000);
 
     Wr32(  RAM_DL, CLEAR(1,1,1));
     Wr32(  RAM_DL+4, DISPLAY());