Diff: inc/FT_Gpu_Hal.h

Revision:

11:435747a1f2ae

Parent:

10:4c10e6aeb239

--- a/inc/FT_Gpu_Hal.h	Sat Sep 16 18:34:14 2017 +0000
+++ b/inc/FT_Gpu_Hal.h	Sat Sep 16 23:40:11 2017 +0000
@@ -1,26 +1,3 @@
-/*!
- * \file FT_GPU_HAL.h
- *
- 
- Curt added Load_raw 7/22/16
- 
- 
- 
- * \author FTDI
- * \date 2013.04.24
- *
- * Copyright 2013 Future Technology Devices International Limited
- *
- * Project: FT800 or EVE compatible silicon
- * File Description:
- *    This file defines the generic APIs of host access layer for the FT800 or EVE compatible silicon.
- *    Application shall access FT800 or EVE resources over these APIs. In addition, there are
- *    some helper functions defined for FT800 coprocessor engine as well as host commands.
- * Rivision History:
- * ported to mbed by Peter Drescher, DC2PD 2014
- *
- */
- 
 #ifndef FT_GPU_HAL_H
 #define FT_GPU_HAL_H
  
@@ -173,8 +150,87 @@
         FT_GPU_SLEEP_M =   0x42,
         FT_GPU_POWERDOWN_M = 0x50,
     } FT_GPU_POWER_MODE_T;
+    
+    #ifdef FT_81X_ENABLE
+    typedef enum {
+        FT_GPU_SYSCLK_DEFAULT = 0x00,  //default 60mhz
+        FT_GPU_SYSCLK_72M = 0x06, 
+        FT_GPU_SYSCLK_60M = 0x05,  
+        FT_GPU_SYSCLK_48M = 0x04,  
+        FT_GPU_SYSCLK_36M = 0x03,
+        FT_GPU_SYSCLK_24M = 0x02,
+    }FT_GPU_81X_PLL_FREQ_T;
+
+    typedef enum{
+        FT_GPU_MAIN_ROM = 0x80,  //main graphicas ROM used 
+        FT_GPU_RCOSATAN_ROM = 0x40,  //line slope table used for 
+        FT_GPU_SAMPLE_ROM = 0x20,  //JA samples
+        FT_GPU_JABOOT_ROM = 0x10, //JA microcode
+        FT_GPU_J1BOOT_ROM = 0x08, //J1 microcode
+        FT_GPU_ADC = 0x01,  //
+        FT_GPU_POWER_ON_ROM_AND_ADC = 0x00,  //specify this element to power on all ROMs and ADCs
+    }FT_GPU_81X_ROM_AND_ADC_T;
+
+    typedef enum{
+        FT_GPU_5MA = 0x00,  //default current
+        FT_GPU_10MA = 0x01,
+        FT_GPU_15MA = 0x02,
+        FT_GPU_20MA = 0x03,
+    }FT_GPU_81X_GPIO_DRIVE_STRENGTH_T;
+
+    typedef enum{
+        FT_GPU_GPIO0 = 0x00,
+        FT_GPU_GPIO1 = 0x04,
+        FT_GPU_GPIO2 = 0x08,
+        FT_GPU_GPIO3 = 0x0C,
+        FT_GPU_GPIO4 = 0x10,
+        FT_GPU_DISP = 0x20,
+        FT_GPU_DE = 0x24,
+        FT_GPU_VSYNC_HSYNC = 0x28,
+        FT_GPU_PCLK = 0x2C,
+        FT_GPU_BACKLIGHT = 0x30,
+        FT_GPU_R_G_B = 0x34,
+        FT_GPU_AUDIO_L = 0x38,
+        FT_GPU_INT_N = 0x3C,
+        FT_GPU_TOUCHWAKE = 0x40,
+        FT_GPU_SCL = 0x44,
+        FT_GPU_SDA = 0x48,
+        FT_GPU_SPI_MISO_MOSI_IO2_IO3 = 0x4C,
+    }FT_GPU_81X_GPIO_GROUP_T;
+
+    #define FT_GPU_81X_RESET_ACTIVE 0x000268
+
+    #define FT_GPU_81X_RESET_REMOVAL 0x002068
+#endif 
  
 #define FT_GPU_CORE_RESET  (0x68)
+
+/* Enums for number of SPI dummy bytes and number of channels */
+typedef enum {
+    FT_GPU_SPI_SINGLE_CHANNEL = 0,
+    FT_GPU_SPI_DUAL_CHANNEL = 1,
+    FT_GPU_SPI_QUAD_CHANNEL = 2,
+}FT_GPU_SPI_NUMCHANNELS_T;
+typedef enum {
+    FT_GPU_SPI_ONEDUMMY = 1,
+    FT_GPU_SPI_TWODUMMY = 2,
+}FT_GPU_SPI_NUMDUMMYBYTES;
+
+#define FT_SPI_ONE_DUMMY_BYTE   (0x00)
+#define FT_SPI_TWO_DUMMY_BYTE   (0x04)
+#define FT_SPI_SINGLE_CHANNEL   (0x00)
+#define FT_SPI_DUAL_CHANNEL     (0x01)
+#define FT_SPI_QUAD_CHANNEL     (0x02)  
+
+/*
+#ifdef FT_81X_ENABLE
+ft_void_t Ft_Gpu_81X_SelectSysCLK(Ft_Gpu_Hal_Context_t *host, FT_GPU_81X_PLL_FREQ_T freq);
+ft_void_t Ft_GPU_81X_PowerOffComponents(Ft_Gpu_Hal_Context_t *host, ft_uint8_t val);
+ft_void_t Ft_GPU_81X_PadDriveStrength(Ft_Gpu_Hal_Context_t *host, FT_GPU_81X_GPIO_DRIVE_STRENGTH_T strength, FT_GPU_81X_GPIO_GROUP_T group);
+ft_void_t Ft_Gpu_81X_ResetActive(Ft_Gpu_Hal_Context_t *host);
+ft_void_t Ft_Gpu_81X_ResetRemoval(Ft_Gpu_Hal_Context_t *host);
+#endif
+*/  
  
     ft_int32_t hal_strlen(const ft_char8_t *s);
     ft_void_t Sleep(ft_uint16_t ms);