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targets/cmsis/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L053R8/system_stm32l0xx.c@445:9a3ffe6cfa19, 2015-01-14 (annotated)
- Committer:
- moirans2
- Date:
- Wed Jan 14 20:53:08 2015 +0000
- Revision:
- 445:9a3ffe6cfa19
- Parent:
- 436:cef2a8a56f9e
internal clock stm32L051
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mbed_official | 382:ee426a420dbb | 1 | /** |
mbed_official | 382:ee426a420dbb | 2 | ****************************************************************************** |
mbed_official | 382:ee426a420dbb | 3 | * @file system_stm32l0xx.c |
mbed_official | 382:ee426a420dbb | 4 | * @author MCD Application Team |
mbed_official | 386:ea0442aaf784 | 5 | * @version V1.1.0 |
mbed_official | 386:ea0442aaf784 | 6 | * @date 18-June-2014 |
mbed_official | 382:ee426a420dbb | 7 | * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer System Source File. |
mbed_official | 382:ee426a420dbb | 8 | * |
mbed_official | 382:ee426a420dbb | 9 | * This file provides two functions and one global variable to be called from |
mbed_official | 382:ee426a420dbb | 10 | * user application: |
mbed_official | 382:ee426a420dbb | 11 | * - SystemInit(): This function is called at startup just after reset and |
mbed_official | 382:ee426a420dbb | 12 | * before branch to main program. This call is made inside |
mbed_official | 382:ee426a420dbb | 13 | * the "startup_stm32l0xx.s" file. |
mbed_official | 382:ee426a420dbb | 14 | * |
mbed_official | 382:ee426a420dbb | 15 | * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used |
mbed_official | 382:ee426a420dbb | 16 | * by the user application to setup the SysTick |
mbed_official | 382:ee426a420dbb | 17 | * timer or configure other parameters. |
mbed_official | 382:ee426a420dbb | 18 | * |
mbed_official | 382:ee426a420dbb | 19 | * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must |
mbed_official | 382:ee426a420dbb | 20 | * be called whenever the core clock is changed |
mbed_official | 382:ee426a420dbb | 21 | * during program execution. |
mbed_official | 382:ee426a420dbb | 22 | * |
mbed_official | 382:ee426a420dbb | 23 | * This file configures the system clock as follows: |
mbed_official | 382:ee426a420dbb | 24 | *----------------------------------------------------------------------------- |
mbed_official | 382:ee426a420dbb | 25 | * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI |
mbed_official | 382:ee426a420dbb | 26 | * | (external 8 MHz clock) | (internal 16 MHz) |
mbed_official | 382:ee426a420dbb | 27 | * | 2- PLL_HSE_XTAL | |
mbed_official | 382:ee426a420dbb | 28 | * | (external 8 MHz xtal) | |
mbed_official | 382:ee426a420dbb | 29 | *----------------------------------------------------------------------------- |
mbed_official | 382:ee426a420dbb | 30 | * SYSCLK(MHz) | 32 | 32 |
mbed_official | 382:ee426a420dbb | 31 | *----------------------------------------------------------------------------- |
mbed_official | 382:ee426a420dbb | 32 | * AHBCLK (MHz) | 32 | 32 |
mbed_official | 382:ee426a420dbb | 33 | *----------------------------------------------------------------------------- |
mbed_official | 382:ee426a420dbb | 34 | * APB1CLK (MHz) | 32 | 32 |
mbed_official | 382:ee426a420dbb | 35 | *----------------------------------------------------------------------------- |
mbed_official | 382:ee426a420dbb | 36 | * APB2CLK (MHz) | 32 | 32 |
mbed_official | 382:ee426a420dbb | 37 | *----------------------------------------------------------------------------- |
mbed_official | 382:ee426a420dbb | 38 | * USB capable (48 MHz precise clock) | YES | YES |
mbed_official | 382:ee426a420dbb | 39 | *----------------------------------------------------------------------------- |
mbed_official | 382:ee426a420dbb | 40 | ****************************************************************************** |
mbed_official | 382:ee426a420dbb | 41 | * @attention |
mbed_official | 382:ee426a420dbb | 42 | * |
mbed_official | 382:ee426a420dbb | 43 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
mbed_official | 382:ee426a420dbb | 44 | * |
mbed_official | 382:ee426a420dbb | 45 | * Redistribution and use in source and binary forms, with or without modification, |
mbed_official | 382:ee426a420dbb | 46 | * are permitted provided that the following conditions are met: |
mbed_official | 382:ee426a420dbb | 47 | * 1. Redistributions of source code must retain the above copyright notice, |
mbed_official | 382:ee426a420dbb | 48 | * this list of conditions and the following disclaimer. |
mbed_official | 382:ee426a420dbb | 49 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
mbed_official | 382:ee426a420dbb | 50 | * this list of conditions and the following disclaimer in the documentation |
mbed_official | 382:ee426a420dbb | 51 | * and/or other materials provided with the distribution. |
mbed_official | 382:ee426a420dbb | 52 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
mbed_official | 382:ee426a420dbb | 53 | * may be used to endorse or promote products derived from this software |
mbed_official | 382:ee426a420dbb | 54 | * without specific prior written permission. |
mbed_official | 382:ee426a420dbb | 55 | * |
mbed_official | 382:ee426a420dbb | 56 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
mbed_official | 382:ee426a420dbb | 57 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
mbed_official | 382:ee426a420dbb | 58 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
mbed_official | 382:ee426a420dbb | 59 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
mbed_official | 382:ee426a420dbb | 60 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
mbed_official | 382:ee426a420dbb | 61 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
mbed_official | 382:ee426a420dbb | 62 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
mbed_official | 382:ee426a420dbb | 63 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
mbed_official | 382:ee426a420dbb | 64 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
mbed_official | 382:ee426a420dbb | 65 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
mbed_official | 382:ee426a420dbb | 66 | * |
mbed_official | 382:ee426a420dbb | 67 | ****************************************************************************** |
mbed_official | 382:ee426a420dbb | 68 | */ |
mbed_official | 382:ee426a420dbb | 69 | |
mbed_official | 382:ee426a420dbb | 70 | /** @addtogroup CMSIS |
mbed_official | 382:ee426a420dbb | 71 | * @{ |
mbed_official | 382:ee426a420dbb | 72 | */ |
mbed_official | 382:ee426a420dbb | 73 | |
mbed_official | 382:ee426a420dbb | 74 | /** @addtogroup stm32l0xx_system |
mbed_official | 382:ee426a420dbb | 75 | * @{ |
mbed_official | 382:ee426a420dbb | 76 | */ |
mbed_official | 382:ee426a420dbb | 77 | |
mbed_official | 382:ee426a420dbb | 78 | /** @addtogroup STM32L0xx_System_Private_Includes |
mbed_official | 382:ee426a420dbb | 79 | * @{ |
mbed_official | 382:ee426a420dbb | 80 | */ |
mbed_official | 382:ee426a420dbb | 81 | |
mbed_official | 382:ee426a420dbb | 82 | #include "stm32l0xx.h" |
mbed_official | 436:cef2a8a56f9e | 83 | #include "hal_tick.h" |
mbed_official | 382:ee426a420dbb | 84 | |
mbed_official | 382:ee426a420dbb | 85 | #if !defined (HSE_VALUE) |
mbed_official | 382:ee426a420dbb | 86 | #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External oscillator in Hz */ |
mbed_official | 382:ee426a420dbb | 87 | #endif /* HSE_VALUE */ |
mbed_official | 382:ee426a420dbb | 88 | |
mbed_official | 382:ee426a420dbb | 89 | #if !defined (MSI_VALUE) |
mbed_official | 382:ee426a420dbb | 90 | #define MSI_VALUE ((uint32_t)2000000) /*!< Value of the Internal oscillator in Hz*/ |
mbed_official | 382:ee426a420dbb | 91 | #endif /* MSI_VALUE */ |
mbed_official | 382:ee426a420dbb | 92 | |
mbed_official | 382:ee426a420dbb | 93 | #if !defined (HSI_VALUE) |
mbed_official | 382:ee426a420dbb | 94 | #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/ |
mbed_official | 382:ee426a420dbb | 95 | #endif /* HSI_VALUE */ |
mbed_official | 382:ee426a420dbb | 96 | |
mbed_official | 382:ee426a420dbb | 97 | |
mbed_official | 382:ee426a420dbb | 98 | /** |
mbed_official | 382:ee426a420dbb | 99 | * @} |
mbed_official | 382:ee426a420dbb | 100 | */ |
mbed_official | 382:ee426a420dbb | 101 | |
mbed_official | 382:ee426a420dbb | 102 | /** @addtogroup STM32L0xx_System_Private_TypesDefinitions |
mbed_official | 382:ee426a420dbb | 103 | * @{ |
mbed_official | 382:ee426a420dbb | 104 | */ |
mbed_official | 382:ee426a420dbb | 105 | |
mbed_official | 382:ee426a420dbb | 106 | /** |
mbed_official | 382:ee426a420dbb | 107 | * @} |
mbed_official | 382:ee426a420dbb | 108 | */ |
mbed_official | 382:ee426a420dbb | 109 | |
mbed_official | 382:ee426a420dbb | 110 | /** @addtogroup STM32L0xx_System_Private_Defines |
mbed_official | 382:ee426a420dbb | 111 | * @{ |
mbed_official | 382:ee426a420dbb | 112 | */ |
mbed_official | 382:ee426a420dbb | 113 | /************************* Miscellaneous Configuration ************************/ |
mbed_official | 382:ee426a420dbb | 114 | |
mbed_official | 382:ee426a420dbb | 115 | /*!< Uncomment the following line if you need to relocate your vector Table in |
mbed_official | 382:ee426a420dbb | 116 | Internal SRAM. */ |
mbed_official | 382:ee426a420dbb | 117 | /* #define VECT_TAB_SRAM */ |
mbed_official | 382:ee426a420dbb | 118 | #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field. |
mbed_official | 382:ee426a420dbb | 119 | This value must be a multiple of 0x200. */ |
mbed_official | 382:ee426a420dbb | 120 | /******************************************************************************/ |
mbed_official | 382:ee426a420dbb | 121 | /** |
mbed_official | 382:ee426a420dbb | 122 | * @} |
mbed_official | 382:ee426a420dbb | 123 | */ |
mbed_official | 382:ee426a420dbb | 124 | |
mbed_official | 382:ee426a420dbb | 125 | /** @addtogroup STM32L0xx_System_Private_Macros |
mbed_official | 382:ee426a420dbb | 126 | * @{ |
mbed_official | 382:ee426a420dbb | 127 | */ |
mbed_official | 382:ee426a420dbb | 128 | |
mbed_official | 382:ee426a420dbb | 129 | /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */ |
moirans2 | 445:9a3ffe6cfa19 | 130 | #define USE_PLL_HSE_EXTC (0) /* Use external clock */ |
moirans2 | 445:9a3ffe6cfa19 | 131 | #define USE_PLL_HSE_XTAL (0) /* Use external xtal */ |
mbed_official | 382:ee426a420dbb | 132 | |
mbed_official | 382:ee426a420dbb | 133 | /** |
mbed_official | 382:ee426a420dbb | 134 | * @} |
mbed_official | 382:ee426a420dbb | 135 | */ |
mbed_official | 382:ee426a420dbb | 136 | |
mbed_official | 382:ee426a420dbb | 137 | /** @addtogroup STM32L0xx_System_Private_Variables |
mbed_official | 382:ee426a420dbb | 138 | * @{ |
mbed_official | 382:ee426a420dbb | 139 | */ |
mbed_official | 382:ee426a420dbb | 140 | /* This variable is updated in three ways: |
mbed_official | 382:ee426a420dbb | 141 | 1) by calling CMSIS function SystemCoreClockUpdate() |
mbed_official | 382:ee426a420dbb | 142 | 2) by calling HAL API function HAL_RCC_GetHCLKFreq() |
mbed_official | 382:ee426a420dbb | 143 | 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency |
mbed_official | 382:ee426a420dbb | 144 | Note: If you use this function to configure the system clock; then there |
mbed_official | 382:ee426a420dbb | 145 | is no need to call the 2 first functions listed above, since SystemCoreClock |
mbed_official | 382:ee426a420dbb | 146 | variable is updated automatically. |
mbed_official | 382:ee426a420dbb | 147 | */ |
mbed_official | 382:ee426a420dbb | 148 | uint32_t SystemCoreClock = 32000000; |
mbed_official | 382:ee426a420dbb | 149 | |
mbed_official | 382:ee426a420dbb | 150 | const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 382:ee426a420dbb | 151 | const uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48}; |
mbed_official | 382:ee426a420dbb | 152 | const uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9}; |
mbed_official | 382:ee426a420dbb | 153 | //const uint32_t MSIRangeTable[7] = {64000, 128000, 256000, 512000, 1000000, 2000000, 4000000}; |
mbed_official | 382:ee426a420dbb | 154 | |
mbed_official | 382:ee426a420dbb | 155 | /** |
mbed_official | 382:ee426a420dbb | 156 | * @} |
mbed_official | 382:ee426a420dbb | 157 | */ |
mbed_official | 382:ee426a420dbb | 158 | |
mbed_official | 382:ee426a420dbb | 159 | /** @addtogroup STM32L0xx_System_Private_FunctionPrototypes |
mbed_official | 382:ee426a420dbb | 160 | * @{ |
mbed_official | 382:ee426a420dbb | 161 | */ |
mbed_official | 382:ee426a420dbb | 162 | |
mbed_official | 382:ee426a420dbb | 163 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 382:ee426a420dbb | 164 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass); |
mbed_official | 382:ee426a420dbb | 165 | #endif |
mbed_official | 382:ee426a420dbb | 166 | |
mbed_official | 382:ee426a420dbb | 167 | uint8_t SetSysClock_PLL_HSI(void); |
mbed_official | 382:ee426a420dbb | 168 | |
mbed_official | 382:ee426a420dbb | 169 | /** |
mbed_official | 382:ee426a420dbb | 170 | * @} |
mbed_official | 382:ee426a420dbb | 171 | */ |
mbed_official | 382:ee426a420dbb | 172 | |
mbed_official | 382:ee426a420dbb | 173 | /** @addtogroup STM32L0xx_System_Private_Functions |
mbed_official | 382:ee426a420dbb | 174 | * @{ |
mbed_official | 382:ee426a420dbb | 175 | */ |
mbed_official | 382:ee426a420dbb | 176 | |
mbed_official | 382:ee426a420dbb | 177 | /** |
mbed_official | 382:ee426a420dbb | 178 | * @brief Setup the microcontroller system. |
mbed_official | 382:ee426a420dbb | 179 | * @param None |
mbed_official | 382:ee426a420dbb | 180 | * @retval None |
mbed_official | 382:ee426a420dbb | 181 | */ |
mbed_official | 382:ee426a420dbb | 182 | void SystemInit (void) |
mbed_official | 382:ee426a420dbb | 183 | { |
mbed_official | 382:ee426a420dbb | 184 | /*!< Set MSION bit */ |
mbed_official | 382:ee426a420dbb | 185 | RCC->CR |= (uint32_t)0x00000100; |
mbed_official | 382:ee426a420dbb | 186 | |
mbed_official | 382:ee426a420dbb | 187 | /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */ |
mbed_official | 382:ee426a420dbb | 188 | RCC->CFGR &= (uint32_t) 0x88FF400C; |
mbed_official | 382:ee426a420dbb | 189 | |
mbed_official | 382:ee426a420dbb | 190 | /*!< Reset HSION, HSIDIVEN, HSEON, CSSON and PLLON bits */ |
mbed_official | 382:ee426a420dbb | 191 | RCC->CR &= (uint32_t)0xFEF6FFF6; |
mbed_official | 382:ee426a420dbb | 192 | |
mbed_official | 382:ee426a420dbb | 193 | /*!< Reset HSI48ON bit */ |
mbed_official | 382:ee426a420dbb | 194 | RCC->CRRCR &= (uint32_t)0xFFFFFFFE; |
mbed_official | 382:ee426a420dbb | 195 | |
mbed_official | 382:ee426a420dbb | 196 | /*!< Reset HSEBYP bit */ |
mbed_official | 382:ee426a420dbb | 197 | RCC->CR &= (uint32_t)0xFFFBFFFF; |
mbed_official | 382:ee426a420dbb | 198 | |
mbed_official | 382:ee426a420dbb | 199 | /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */ |
mbed_official | 382:ee426a420dbb | 200 | RCC->CFGR &= (uint32_t)0xFF02FFFF; |
mbed_official | 382:ee426a420dbb | 201 | |
mbed_official | 382:ee426a420dbb | 202 | /*!< Disable all interrupts */ |
mbed_official | 382:ee426a420dbb | 203 | RCC->CIER = 0x00000000; |
mbed_official | 382:ee426a420dbb | 204 | |
mbed_official | 382:ee426a420dbb | 205 | /* Configure the Vector Table location add offset address ------------------*/ |
mbed_official | 382:ee426a420dbb | 206 | #ifdef VECT_TAB_SRAM |
mbed_official | 382:ee426a420dbb | 207 | SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */ |
mbed_official | 382:ee426a420dbb | 208 | #else |
mbed_official | 382:ee426a420dbb | 209 | SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */ |
mbed_official | 382:ee426a420dbb | 210 | #endif |
mbed_official | 382:ee426a420dbb | 211 | |
mbed_official | 382:ee426a420dbb | 212 | /* Configure the Cube driver */ |
mbed_official | 436:cef2a8a56f9e | 213 | SystemCoreClock = 8000000; // At this stage the HSI is used as system clock |
mbed_official | 382:ee426a420dbb | 214 | HAL_Init(); |
mbed_official | 382:ee426a420dbb | 215 | |
mbed_official | 382:ee426a420dbb | 216 | /* Configure the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 382:ee426a420dbb | 217 | AHB/APBx prescalers and Flash settings */ |
mbed_official | 382:ee426a420dbb | 218 | SetSysClock(); |
mbed_official | 436:cef2a8a56f9e | 219 | |
mbed_official | 436:cef2a8a56f9e | 220 | /* Reset the timer to avoid issues after the RAM initialization */ |
mbed_official | 436:cef2a8a56f9e | 221 | TIM_MST_RESET_ON; |
mbed_official | 436:cef2a8a56f9e | 222 | TIM_MST_RESET_OFF; |
mbed_official | 382:ee426a420dbb | 223 | } |
mbed_official | 382:ee426a420dbb | 224 | |
mbed_official | 382:ee426a420dbb | 225 | /** |
mbed_official | 382:ee426a420dbb | 226 | * @brief Update SystemCoreClock according to Clock Register Values |
mbed_official | 382:ee426a420dbb | 227 | * The SystemCoreClock variable contains the core clock (HCLK), it can |
mbed_official | 382:ee426a420dbb | 228 | * be used by the user application to setup the SysTick timer or configure |
mbed_official | 382:ee426a420dbb | 229 | * other parameters. |
mbed_official | 382:ee426a420dbb | 230 | * |
mbed_official | 382:ee426a420dbb | 231 | * @note Each time the core clock (HCLK) changes, this function must be called |
mbed_official | 382:ee426a420dbb | 232 | * to update SystemCoreClock variable value. Otherwise, any configuration |
mbed_official | 382:ee426a420dbb | 233 | * based on this variable will be incorrect. |
mbed_official | 382:ee426a420dbb | 234 | * |
mbed_official | 382:ee426a420dbb | 235 | * @note - The system frequency computed by this function is not the real |
mbed_official | 382:ee426a420dbb | 236 | * frequency in the chip. It is calculated based on the predefined |
mbed_official | 382:ee426a420dbb | 237 | * constant and the selected clock source: |
mbed_official | 382:ee426a420dbb | 238 | * |
mbed_official | 382:ee426a420dbb | 239 | * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI |
mbed_official | 382:ee426a420dbb | 240 | * value as defined by the MSI range. |
mbed_official | 382:ee426a420dbb | 241 | * |
mbed_official | 382:ee426a420dbb | 242 | * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*) |
mbed_official | 382:ee426a420dbb | 243 | * |
mbed_official | 382:ee426a420dbb | 244 | * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 382:ee426a420dbb | 245 | * |
mbed_official | 382:ee426a420dbb | 246 | * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) |
mbed_official | 382:ee426a420dbb | 247 | * or HSI_VALUE(*) multiplied/divided by the PLL factors. |
mbed_official | 382:ee426a420dbb | 248 | * |
mbed_official | 382:ee426a420dbb | 249 | * (*) HSI_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
mbed_official | 382:ee426a420dbb | 250 | * 16 MHz) but the real value may vary depending on the variations |
mbed_official | 382:ee426a420dbb | 251 | * in voltage and temperature. |
mbed_official | 382:ee426a420dbb | 252 | * |
mbed_official | 382:ee426a420dbb | 253 | * (**) HSE_VALUE is a constant defined in stm32l0xx_hal.h file (default value |
mbed_official | 382:ee426a420dbb | 254 | * 8 MHz), user has to ensure that HSE_VALUE is same as the real |
mbed_official | 382:ee426a420dbb | 255 | * frequency of the crystal used. Otherwise, this function may |
mbed_official | 382:ee426a420dbb | 256 | * have wrong result. |
mbed_official | 382:ee426a420dbb | 257 | * |
mbed_official | 382:ee426a420dbb | 258 | * - The result of this function could be not correct when using fractional |
mbed_official | 382:ee426a420dbb | 259 | * value for HSE crystal. |
mbed_official | 382:ee426a420dbb | 260 | * @param None |
mbed_official | 382:ee426a420dbb | 261 | * @retval None |
mbed_official | 382:ee426a420dbb | 262 | */ |
mbed_official | 382:ee426a420dbb | 263 | void SystemCoreClockUpdate (void) |
mbed_official | 382:ee426a420dbb | 264 | { |
mbed_official | 382:ee426a420dbb | 265 | uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0; |
mbed_official | 382:ee426a420dbb | 266 | |
mbed_official | 382:ee426a420dbb | 267 | /* Get SYSCLK source -------------------------------------------------------*/ |
mbed_official | 382:ee426a420dbb | 268 | tmp = RCC->CFGR & RCC_CFGR_SWS; |
mbed_official | 382:ee426a420dbb | 269 | |
mbed_official | 382:ee426a420dbb | 270 | switch (tmp) |
mbed_official | 382:ee426a420dbb | 271 | { |
mbed_official | 382:ee426a420dbb | 272 | case 0x00: /* MSI used as system clock */ |
mbed_official | 382:ee426a420dbb | 273 | SystemCoreClock = ((1 <<((RCC->ICSCR & RCC_ICSCR_MSIRANGE)>>13 ))* 64000); |
mbed_official | 382:ee426a420dbb | 274 | break; |
mbed_official | 382:ee426a420dbb | 275 | case 0x04: /* HSI used as system clock */ |
mbed_official | 382:ee426a420dbb | 276 | SystemCoreClock = HSI_VALUE; |
mbed_official | 382:ee426a420dbb | 277 | break; |
mbed_official | 382:ee426a420dbb | 278 | case 0x08: /* HSE used as system clock */ |
mbed_official | 382:ee426a420dbb | 279 | SystemCoreClock = HSE_VALUE; |
mbed_official | 382:ee426a420dbb | 280 | break; |
mbed_official | 382:ee426a420dbb | 281 | case 0x0C: /* PLL used as system clock */ |
mbed_official | 382:ee426a420dbb | 282 | /* Get PLL clock source and multiplication factor ----------------------*/ |
mbed_official | 382:ee426a420dbb | 283 | pllmul = RCC->CFGR & RCC_CFGR_PLLMUL; |
mbed_official | 382:ee426a420dbb | 284 | plldiv = RCC->CFGR & RCC_CFGR_PLLDIV; |
mbed_official | 382:ee426a420dbb | 285 | pllmul = PLLMulTable[(pllmul >> 18)]; |
mbed_official | 382:ee426a420dbb | 286 | plldiv = (plldiv >> 22) + 1; |
mbed_official | 382:ee426a420dbb | 287 | |
mbed_official | 382:ee426a420dbb | 288 | pllsource = RCC->CFGR & RCC_CFGR_PLLSRC; |
mbed_official | 382:ee426a420dbb | 289 | |
mbed_official | 382:ee426a420dbb | 290 | if (pllsource == 0x00) |
mbed_official | 382:ee426a420dbb | 291 | { |
mbed_official | 382:ee426a420dbb | 292 | /* HSI oscillator clock selected as PLL clock entry */ |
mbed_official | 382:ee426a420dbb | 293 | SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv); |
mbed_official | 382:ee426a420dbb | 294 | } |
mbed_official | 382:ee426a420dbb | 295 | else |
mbed_official | 382:ee426a420dbb | 296 | { |
mbed_official | 382:ee426a420dbb | 297 | /* HSE selected as PLL clock entry */ |
mbed_official | 382:ee426a420dbb | 298 | SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv); |
mbed_official | 382:ee426a420dbb | 299 | } |
mbed_official | 382:ee426a420dbb | 300 | break; |
mbed_official | 382:ee426a420dbb | 301 | default: /* MSI used as system clock */ |
mbed_official | 382:ee426a420dbb | 302 | msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13; |
mbed_official | 382:ee426a420dbb | 303 | SystemCoreClock = (32768 * (1 << (msirange + 1))); |
mbed_official | 382:ee426a420dbb | 304 | break; |
mbed_official | 382:ee426a420dbb | 305 | } |
mbed_official | 382:ee426a420dbb | 306 | /* Compute HCLK clock frequency --------------------------------------------*/ |
mbed_official | 382:ee426a420dbb | 307 | /* Get HCLK prescaler */ |
mbed_official | 382:ee426a420dbb | 308 | tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)]; |
mbed_official | 382:ee426a420dbb | 309 | /* HCLK clock frequency */ |
mbed_official | 382:ee426a420dbb | 310 | SystemCoreClock >>= tmp; |
mbed_official | 382:ee426a420dbb | 311 | } |
mbed_official | 382:ee426a420dbb | 312 | |
mbed_official | 382:ee426a420dbb | 313 | /** |
mbed_official | 382:ee426a420dbb | 314 | * @brief Configures the System clock source, PLL Multiplier and Divider factors, |
mbed_official | 382:ee426a420dbb | 315 | * AHB/APBx prescalers and Flash settings |
mbed_official | 382:ee426a420dbb | 316 | * @note This function should be called only once the RCC clock configuration |
mbed_official | 382:ee426a420dbb | 317 | * is reset to the default reset state (done in SystemInit() function). |
mbed_official | 382:ee426a420dbb | 318 | * @param None |
mbed_official | 382:ee426a420dbb | 319 | * @retval None |
mbed_official | 382:ee426a420dbb | 320 | */ |
mbed_official | 382:ee426a420dbb | 321 | void SetSysClock(void) |
mbed_official | 382:ee426a420dbb | 322 | { |
mbed_official | 382:ee426a420dbb | 323 | /* 1- Try to start with HSE and external clock */ |
mbed_official | 382:ee426a420dbb | 324 | #if USE_PLL_HSE_EXTC != 0 |
mbed_official | 382:ee426a420dbb | 325 | if (SetSysClock_PLL_HSE(1) == 0) |
mbed_official | 382:ee426a420dbb | 326 | #endif |
mbed_official | 382:ee426a420dbb | 327 | { |
mbed_official | 382:ee426a420dbb | 328 | /* 2- If fail try to start with HSE and external xtal */ |
mbed_official | 382:ee426a420dbb | 329 | #if USE_PLL_HSE_XTAL != 0 |
mbed_official | 382:ee426a420dbb | 330 | if (SetSysClock_PLL_HSE(0) == 0) |
mbed_official | 382:ee426a420dbb | 331 | #endif |
mbed_official | 382:ee426a420dbb | 332 | { |
mbed_official | 382:ee426a420dbb | 333 | /* 3- If fail start with HSI clock */ |
mbed_official | 382:ee426a420dbb | 334 | if (SetSysClock_PLL_HSI() == 0) |
mbed_official | 382:ee426a420dbb | 335 | { |
mbed_official | 382:ee426a420dbb | 336 | while(1) |
mbed_official | 382:ee426a420dbb | 337 | { |
mbed_official | 382:ee426a420dbb | 338 | // [TODO] Put something here to tell the user that a problem occured... |
mbed_official | 382:ee426a420dbb | 339 | } |
mbed_official | 382:ee426a420dbb | 340 | } |
mbed_official | 382:ee426a420dbb | 341 | } |
mbed_official | 382:ee426a420dbb | 342 | } |
mbed_official | 382:ee426a420dbb | 343 | |
mbed_official | 382:ee426a420dbb | 344 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
mbed_official | 382:ee426a420dbb | 345 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_SYSCLK, RCC_MCODIV_1); |
mbed_official | 382:ee426a420dbb | 346 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI48, RCC_MCODIV_1); |
mbed_official | 382:ee426a420dbb | 347 | } |
mbed_official | 382:ee426a420dbb | 348 | |
mbed_official | 382:ee426a420dbb | 349 | #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0) |
mbed_official | 382:ee426a420dbb | 350 | /******************************************************************************/ |
mbed_official | 382:ee426a420dbb | 351 | /* PLL (clocked by HSE) used as System clock source */ |
mbed_official | 382:ee426a420dbb | 352 | /******************************************************************************/ |
mbed_official | 382:ee426a420dbb | 353 | uint8_t SetSysClock_PLL_HSE(uint8_t bypass) |
mbed_official | 382:ee426a420dbb | 354 | { |
mbed_official | 382:ee426a420dbb | 355 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
mbed_official | 382:ee426a420dbb | 356 | RCC_OscInitTypeDef RCC_OscInitStruct; |
mbed_official | 382:ee426a420dbb | 357 | |
mbed_official | 382:ee426a420dbb | 358 | /* Used to gain time after DeepSleep in case HSI is used */ |
mbed_official | 382:ee426a420dbb | 359 | if (__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET) |
mbed_official | 382:ee426a420dbb | 360 | { |
mbed_official | 382:ee426a420dbb | 361 | return 0; |
mbed_official | 382:ee426a420dbb | 362 | } |
mbed_official | 382:ee426a420dbb | 363 | |
mbed_official | 382:ee426a420dbb | 364 | /* The voltage scaling allows optimizing the power consumption when the device is |
mbed_official | 382:ee426a420dbb | 365 | clocked below the maximum system frequency, to update the voltage scaling value |
mbed_official | 382:ee426a420dbb | 366 | regarding system frequency refer to product datasheet. */ |
mbed_official | 382:ee426a420dbb | 367 | __PWR_CLK_ENABLE(); |
mbed_official | 382:ee426a420dbb | 368 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
mbed_official | 382:ee426a420dbb | 369 | |
mbed_official | 382:ee426a420dbb | 370 | /* Enable HSE and HSI48 oscillators and activate PLL with HSE as source */ |
mbed_official | 382:ee426a420dbb | 371 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48; |
mbed_official | 382:ee426a420dbb | 372 | if (bypass == 0) |
mbed_official | 382:ee426a420dbb | 373 | { |
mbed_official | 382:ee426a420dbb | 374 | RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */ |
mbed_official | 382:ee426a420dbb | 375 | } |
mbed_official | 382:ee426a420dbb | 376 | else |
mbed_official | 382:ee426a420dbb | 377 | { |
mbed_official | 382:ee426a420dbb | 378 | RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */ |
mbed_official | 382:ee426a420dbb | 379 | } |
mbed_official | 382:ee426a420dbb | 380 | RCC_OscInitStruct.HSIState = RCC_HSI_OFF; |
mbed_official | 382:ee426a420dbb | 381 | RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ |
mbed_official | 382:ee426a420dbb | 382 | // PLLCLK = (8 MHz * 8)/2 = 32 MHz |
mbed_official | 382:ee426a420dbb | 383 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
mbed_official | 382:ee426a420dbb | 384 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; |
mbed_official | 382:ee426a420dbb | 385 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_8; |
mbed_official | 382:ee426a420dbb | 386 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; |
mbed_official | 382:ee426a420dbb | 387 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
mbed_official | 382:ee426a420dbb | 388 | { |
mbed_official | 382:ee426a420dbb | 389 | return 0; // FAIL |
mbed_official | 382:ee426a420dbb | 390 | } |
mbed_official | 382:ee426a420dbb | 391 | |
mbed_official | 382:ee426a420dbb | 392 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
mbed_official | 382:ee426a420dbb | 393 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
mbed_official | 382:ee426a420dbb | 394 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz |
mbed_official | 382:ee426a420dbb | 395 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz |
mbed_official | 382:ee426a420dbb | 396 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 382:ee426a420dbb | 397 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 382:ee426a420dbb | 398 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
mbed_official | 382:ee426a420dbb | 399 | { |
mbed_official | 382:ee426a420dbb | 400 | return 0; // FAIL |
mbed_official | 382:ee426a420dbb | 401 | } |
mbed_official | 382:ee426a420dbb | 402 | |
mbed_official | 382:ee426a420dbb | 403 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
mbed_official | 382:ee426a420dbb | 404 | //if (bypass == 0) |
mbed_official | 382:ee426a420dbb | 405 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz |
mbed_official | 382:ee426a420dbb | 406 | //else |
mbed_official | 382:ee426a420dbb | 407 | // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz |
mbed_official | 382:ee426a420dbb | 408 | |
mbed_official | 382:ee426a420dbb | 409 | return 1; // OK |
mbed_official | 382:ee426a420dbb | 410 | } |
mbed_official | 382:ee426a420dbb | 411 | #endif |
mbed_official | 382:ee426a420dbb | 412 | |
mbed_official | 382:ee426a420dbb | 413 | /******************************************************************************/ |
mbed_official | 382:ee426a420dbb | 414 | /* PLL (clocked by HSI) used as System clock source */ |
mbed_official | 382:ee426a420dbb | 415 | /******************************************************************************/ |
mbed_official | 382:ee426a420dbb | 416 | uint8_t SetSysClock_PLL_HSI(void) |
mbed_official | 382:ee426a420dbb | 417 | { |
mbed_official | 382:ee426a420dbb | 418 | RCC_ClkInitTypeDef RCC_ClkInitStruct; |
mbed_official | 382:ee426a420dbb | 419 | RCC_OscInitTypeDef RCC_OscInitStruct; |
mbed_official | 382:ee426a420dbb | 420 | |
mbed_official | 382:ee426a420dbb | 421 | /* The voltage scaling allows optimizing the power consumption when the device is |
mbed_official | 382:ee426a420dbb | 422 | clocked below the maximum system frequency, to update the voltage scaling value |
mbed_official | 382:ee426a420dbb | 423 | regarding system frequency refer to product datasheet. */ |
mbed_official | 382:ee426a420dbb | 424 | __PWR_CLK_ENABLE(); |
mbed_official | 382:ee426a420dbb | 425 | __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE1); |
mbed_official | 382:ee426a420dbb | 426 | |
mbed_official | 382:ee426a420dbb | 427 | /* Enable HSI and HSI48 oscillators and activate PLL with HSI as source */ |
mbed_official | 382:ee426a420dbb | 428 | RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI48; |
mbed_official | 382:ee426a420dbb | 429 | RCC_OscInitStruct.HSEState = RCC_HSE_OFF; |
mbed_official | 382:ee426a420dbb | 430 | RCC_OscInitStruct.HSIState = RCC_HSI_ON; |
mbed_official | 382:ee426a420dbb | 431 | RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */ |
mbed_official | 382:ee426a420dbb | 432 | // PLLCLK = (16 MHz * 4)/2 = 32 MHz |
mbed_official | 382:ee426a420dbb | 433 | RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON; |
mbed_official | 382:ee426a420dbb | 434 | RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI; |
mbed_official | 382:ee426a420dbb | 435 | RCC_OscInitStruct.PLL.PLLMUL = RCC_PLLMUL_4; |
mbed_official | 382:ee426a420dbb | 436 | RCC_OscInitStruct.PLL.PLLDIV = RCC_PLLDIV_2; |
mbed_official | 382:ee426a420dbb | 437 | if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) |
mbed_official | 382:ee426a420dbb | 438 | { |
mbed_official | 382:ee426a420dbb | 439 | return 0; // FAIL |
mbed_official | 382:ee426a420dbb | 440 | } |
mbed_official | 382:ee426a420dbb | 441 | |
mbed_official | 382:ee426a420dbb | 442 | /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */ |
mbed_official | 382:ee426a420dbb | 443 | RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2); |
mbed_official | 382:ee426a420dbb | 444 | RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 32 MHz |
mbed_official | 382:ee426a420dbb | 445 | RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 32 MHz |
mbed_official | 382:ee426a420dbb | 446 | RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 382:ee426a420dbb | 447 | RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 32 MHz |
mbed_official | 382:ee426a420dbb | 448 | if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_1) != HAL_OK) |
mbed_official | 382:ee426a420dbb | 449 | { |
mbed_official | 382:ee426a420dbb | 450 | return 0; // FAIL |
mbed_official | 382:ee426a420dbb | 451 | } |
mbed_official | 382:ee426a420dbb | 452 | |
mbed_official | 382:ee426a420dbb | 453 | /* Output clock on MCO1 pin(PA8) for debugging purpose */ |
mbed_official | 382:ee426a420dbb | 454 | //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz |
mbed_official | 382:ee426a420dbb | 455 | |
mbed_official | 382:ee426a420dbb | 456 | return 1; // OK |
mbed_official | 382:ee426a420dbb | 457 | } |
mbed_official | 382:ee426a420dbb | 458 | |
mbed_official | 382:ee426a420dbb | 459 | /** |
mbed_official | 382:ee426a420dbb | 460 | * @} |
mbed_official | 382:ee426a420dbb | 461 | */ |
mbed_official | 382:ee426a420dbb | 462 | |
mbed_official | 382:ee426a420dbb | 463 | /** |
mbed_official | 382:ee426a420dbb | 464 | * @} |
mbed_official | 382:ee426a420dbb | 465 | */ |
mbed_official | 382:ee426a420dbb | 466 | |
mbed_official | 382:ee426a420dbb | 467 | /** |
mbed_official | 382:ee426a420dbb | 468 | * @} |
mbed_official | 382:ee426a420dbb | 469 | */ |
mbed_official | 382:ee426a420dbb | 470 | |
mbed_official | 382:ee426a420dbb | 471 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |