gabriel della-monica / mbed-src

mbed library sources

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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c@139:e3413eddde57, 2014-03-27 (annotated)

Committer:
mbed_official
Date:
Thu Mar 27 09:45:07 2014 +0000
Revision:
139:e3413eddde57
Parent:
129:0182c99221bc
Child:
354:e67efb2aab0e
Synchronized with git revision 3d49a491d4dd16466354746d3c329428840f5a03



Full URL: https://github.com/mbedmicro/mbed/commit/3d49a491d4dd16466354746d3c329428840f5a03/



Fixed readNB() bug

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 76:aeb1df146756 1 /**
mbed_official 76:aeb1df146756 2 ******************************************************************************
mbed_official 76:aeb1df146756 3 * @file system_stm32l1xx.c
mbed_official 76:aeb1df146756 4 * @author MCD Application Team
mbed_official 76:aeb1df146756 5 * @version V1.2.0
mbed_official 129:0182c99221bc 6 * @date 14-March-2014
mbed_official 76:aeb1df146756 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official 76:aeb1df146756 8 * This file contains the system clock configuration for STM32L1xx Ultra
mbed_official 76:aeb1df146756 9 * Low power devices, and is generated by the clock configuration
mbed_official 76:aeb1df146756 10 * tool STM32L1xx_Clock_Configuration_V1.2.0.xls
mbed_official 76:aeb1df146756 11 *
mbed_official 76:aeb1df146756 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 76:aeb1df146756 13 * user application:
mbed_official 76:aeb1df146756 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 76:aeb1df146756 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 76:aeb1df146756 16 * depending on the configuration made in the clock xls tool.
mbed_official 76:aeb1df146756 17 * This function is called at startup just after reset and
mbed_official 76:aeb1df146756 18 * before branch to main program. This call is made inside
mbed_official 76:aeb1df146756 19 * the "startup_stm32l1xx_xx.s" file.
mbed_official 76:aeb1df146756 20 *
mbed_official 76:aeb1df146756 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 76:aeb1df146756 22 * by the user application to setup the SysTick
mbed_official 76:aeb1df146756 23 * timer or configure other parameters.
mbed_official 76:aeb1df146756 24 *
mbed_official 76:aeb1df146756 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 76:aeb1df146756 26 * be called whenever the core clock is changed
mbed_official 76:aeb1df146756 27 * during program execution.
mbed_official 76:aeb1df146756 28 *
mbed_official 76:aeb1df146756 29 * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
mbed_official 76:aeb1df146756 30 * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
mbed_official 76:aeb1df146756 31 * configure the system clock before to branch to main program.
mbed_official 76:aeb1df146756 32 *
mbed_official 76:aeb1df146756 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 76:aeb1df146756 34 * function will do nothing and MSI still used as system clock source. User can
mbed_official 76:aeb1df146756 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 76:aeb1df146756 36 *
mbed_official 76:aeb1df146756 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 76:aeb1df146756 38 * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
mbed_official 76:aeb1df146756 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 76:aeb1df146756 40 * value to your own configuration.
mbed_official 139:e3413eddde57 41 *
mbed_official 139:e3413eddde57 42 * 5. This file configures the system clock as follows:
mbed_official 139:e3413eddde57 43 *-----------------------------------------------------------------------------
mbed_official 139:e3413eddde57 44 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 139:e3413eddde57 45 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 139:e3413eddde57 46 * | 2- PLL_HSE_XTAL |
mbed_official 139:e3413eddde57 47 * | (external 8 MHz xtal) |
mbed_official 139:e3413eddde57 48 *-----------------------------------------------------------------------------
mbed_official 139:e3413eddde57 49 * SYSCLK(MHz) | 24 | 32
mbed_official 139:e3413eddde57 50 *-----------------------------------------------------------------------------
mbed_official 139:e3413eddde57 51 * AHBCLK (MHz) | 24 | 32
mbed_official 139:e3413eddde57 52 *-----------------------------------------------------------------------------
mbed_official 139:e3413eddde57 53 * APB1CLK (MHz) | 24 | 32
mbed_official 139:e3413eddde57 54 *-----------------------------------------------------------------------------
mbed_official 139:e3413eddde57 55 * APB2CLK (MHz) | 24 | 32
mbed_official 139:e3413eddde57 56 *-----------------------------------------------------------------------------
mbed_official 139:e3413eddde57 57 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 139:e3413eddde57 58 *-----------------------------------------------------------------------------
mbed_official 139:e3413eddde57 59 ******************************************************************************
mbed_official 76:aeb1df146756 60 * @attention
mbed_official 76:aeb1df146756 61 *
mbed_official 106:ced8cbb51063 62 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 76:aeb1df146756 63 *
mbed_official 106:ced8cbb51063 64 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 106:ced8cbb51063 65 * are permitted provided that the following conditions are met:
mbed_official 106:ced8cbb51063 66 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 106:ced8cbb51063 67 * this list of conditions and the following disclaimer.
mbed_official 106:ced8cbb51063 68 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 106:ced8cbb51063 69 * this list of conditions and the following disclaimer in the documentation
mbed_official 106:ced8cbb51063 70 * and/or other materials provided with the distribution.
mbed_official 106:ced8cbb51063 71 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 106:ced8cbb51063 72 * may be used to endorse or promote products derived from this software
mbed_official 106:ced8cbb51063 73 * without specific prior written permission.
mbed_official 76:aeb1df146756 74 *
mbed_official 106:ced8cbb51063 75 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 106:ced8cbb51063 76 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 106:ced8cbb51063 77 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 106:ced8cbb51063 78 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 106:ced8cbb51063 79 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 106:ced8cbb51063 80 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 106:ced8cbb51063 81 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 106:ced8cbb51063 82 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 106:ced8cbb51063 83 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 106:ced8cbb51063 84 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 76:aeb1df146756 85 *
mbed_official 76:aeb1df146756 86 ******************************************************************************
mbed_official 76:aeb1df146756 87 */
mbed_official 76:aeb1df146756 88
mbed_official 76:aeb1df146756 89 /** @addtogroup CMSIS
mbed_official 76:aeb1df146756 90 * @{
mbed_official 76:aeb1df146756 91 */
mbed_official 76:aeb1df146756 92
mbed_official 76:aeb1df146756 93 /** @addtogroup stm32l1xx_system
mbed_official 76:aeb1df146756 94 * @{
mbed_official 76:aeb1df146756 95 */
mbed_official 76:aeb1df146756 96
mbed_official 76:aeb1df146756 97 /** @addtogroup STM32L1xx_System_Private_Includes
mbed_official 76:aeb1df146756 98 * @{
mbed_official 76:aeb1df146756 99 */
mbed_official 76:aeb1df146756 100
mbed_official 76:aeb1df146756 101 #include "stm32l1xx.h"
mbed_official 76:aeb1df146756 102
mbed_official 76:aeb1df146756 103 /**
mbed_official 76:aeb1df146756 104 * @}
mbed_official 76:aeb1df146756 105 */
mbed_official 76:aeb1df146756 106
mbed_official 76:aeb1df146756 107 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
mbed_official 76:aeb1df146756 108 * @{
mbed_official 76:aeb1df146756 109 */
mbed_official 76:aeb1df146756 110
mbed_official 76:aeb1df146756 111 /**
mbed_official 76:aeb1df146756 112 * @}
mbed_official 76:aeb1df146756 113 */
mbed_official 76:aeb1df146756 114
mbed_official 76:aeb1df146756 115 /** @addtogroup STM32L1xx_System_Private_Defines
mbed_official 76:aeb1df146756 116 * @{
mbed_official 76:aeb1df146756 117 */
mbed_official 76:aeb1df146756 118
mbed_official 76:aeb1df146756 119 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 76:aeb1df146756 120 Internal SRAM. */
mbed_official 76:aeb1df146756 121 /* #define VECT_TAB_SRAM */
mbed_official 76:aeb1df146756 122 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 76:aeb1df146756 123 This value must be a multiple of 0x200. */
mbed_official 76:aeb1df146756 124 /**
mbed_official 76:aeb1df146756 125 * @}
mbed_official 76:aeb1df146756 126 */
mbed_official 76:aeb1df146756 127
mbed_official 76:aeb1df146756 128 /** @addtogroup STM32L1xx_System_Private_Macros
mbed_official 76:aeb1df146756 129 * @{
mbed_official 76:aeb1df146756 130 */
mbed_official 76:aeb1df146756 131
mbed_official 139:e3413eddde57 132 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 139:e3413eddde57 133 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 139:e3413eddde57 134 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 139:e3413eddde57 135
mbed_official 76:aeb1df146756 136 /**
mbed_official 76:aeb1df146756 137 * @}
mbed_official 76:aeb1df146756 138 */
mbed_official 76:aeb1df146756 139
mbed_official 76:aeb1df146756 140 /** @addtogroup STM32L1xx_System_Private_Variables
mbed_official 76:aeb1df146756 141 * @{
mbed_official 76:aeb1df146756 142 */
mbed_official 139:e3413eddde57 143
mbed_official 139:e3413eddde57 144 uint32_t SystemCoreClock = 32000000; /* Default with HSI. Will be updated if HSE is used */
mbed_official 139:e3413eddde57 145
mbed_official 76:aeb1df146756 146 __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official 76:aeb1df146756 147 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 76:aeb1df146756 148
mbed_official 76:aeb1df146756 149 /**
mbed_official 76:aeb1df146756 150 * @}
mbed_official 76:aeb1df146756 151 */
mbed_official 76:aeb1df146756 152
mbed_official 76:aeb1df146756 153 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
mbed_official 76:aeb1df146756 154 * @{
mbed_official 76:aeb1df146756 155 */
mbed_official 76:aeb1df146756 156
mbed_official 129:0182c99221bc 157 void SetSysClock(void);
mbed_official 76:aeb1df146756 158
mbed_official 139:e3413eddde57 159 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 139:e3413eddde57 160 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 139:e3413eddde57 161 #endif
mbed_official 139:e3413eddde57 162
mbed_official 139:e3413eddde57 163 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 139:e3413eddde57 164
mbed_official 76:aeb1df146756 165 /**
mbed_official 76:aeb1df146756 166 * @}
mbed_official 76:aeb1df146756 167 */
mbed_official 76:aeb1df146756 168
mbed_official 76:aeb1df146756 169 /** @addtogroup STM32L1xx_System_Private_Functions
mbed_official 76:aeb1df146756 170 * @{
mbed_official 76:aeb1df146756 171 */
mbed_official 76:aeb1df146756 172
mbed_official 76:aeb1df146756 173 /**
mbed_official 76:aeb1df146756 174 * @brief Setup the microcontroller system.
mbed_official 76:aeb1df146756 175 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 76:aeb1df146756 176 * SystemCoreClock variable.
mbed_official 76:aeb1df146756 177 * @param None
mbed_official 76:aeb1df146756 178 * @retval None
mbed_official 76:aeb1df146756 179 */
mbed_official 76:aeb1df146756 180 void SystemInit (void)
mbed_official 76:aeb1df146756 181 {
mbed_official 76:aeb1df146756 182 /*!< Set MSION bit */
mbed_official 76:aeb1df146756 183 RCC->CR |= (uint32_t)0x00000100;
mbed_official 76:aeb1df146756 184
mbed_official 76:aeb1df146756 185 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
mbed_official 76:aeb1df146756 186 RCC->CFGR &= (uint32_t)0x88FFC00C;
mbed_official 76:aeb1df146756 187
mbed_official 76:aeb1df146756 188 /*!< Reset HSION, HSEON, CSSON and PLLON bits */
mbed_official 76:aeb1df146756 189 RCC->CR &= (uint32_t)0xEEFEFFFE;
mbed_official 76:aeb1df146756 190
mbed_official 76:aeb1df146756 191 /*!< Reset HSEBYP bit */
mbed_official 76:aeb1df146756 192 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 76:aeb1df146756 193
mbed_official 76:aeb1df146756 194 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
mbed_official 76:aeb1df146756 195 RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official 76:aeb1df146756 196
mbed_official 76:aeb1df146756 197 /*!< Disable all interrupts */
mbed_official 76:aeb1df146756 198 RCC->CIR = 0x00000000;
mbed_official 76:aeb1df146756 199
mbed_official 139:e3413eddde57 200 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 139:e3413eddde57 201 AHB/APBx prescalers and Flash settings */
mbed_official 76:aeb1df146756 202 SetSysClock();
mbed_official 76:aeb1df146756 203
mbed_official 139:e3413eddde57 204 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 76:aeb1df146756 205 #ifdef VECT_TAB_SRAM
mbed_official 139:e3413eddde57 206 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 76:aeb1df146756 207 #else
mbed_official 139:e3413eddde57 208 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 76:aeb1df146756 209 #endif
mbed_official 76:aeb1df146756 210 }
mbed_official 76:aeb1df146756 211
mbed_official 76:aeb1df146756 212 /**
mbed_official 139:e3413eddde57 213 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 76:aeb1df146756 214 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 76:aeb1df146756 215 * be used by the user application to setup the SysTick timer or configure
mbed_official 76:aeb1df146756 216 * other parameters.
mbed_official 76:aeb1df146756 217 *
mbed_official 76:aeb1df146756 218 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 76:aeb1df146756 219 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 76:aeb1df146756 220 * based on this variable will be incorrect.
mbed_official 76:aeb1df146756 221 *
mbed_official 76:aeb1df146756 222 * @note - The system frequency computed by this function is not the real
mbed_official 76:aeb1df146756 223 * frequency in the chip. It is calculated based on the predefined
mbed_official 76:aeb1df146756 224 * constant and the selected clock source:
mbed_official 76:aeb1df146756 225 *
mbed_official 76:aeb1df146756 226 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official 76:aeb1df146756 227 * value as defined by the MSI range.
mbed_official 76:aeb1df146756 228 *
mbed_official 76:aeb1df146756 229 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 76:aeb1df146756 230 *
mbed_official 76:aeb1df146756 231 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 76:aeb1df146756 232 *
mbed_official 76:aeb1df146756 233 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 76:aeb1df146756 234 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 76:aeb1df146756 235 *
mbed_official 76:aeb1df146756 236 * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official 76:aeb1df146756 237 * 16 MHz) but the real value may vary depending on the variations
mbed_official 76:aeb1df146756 238 * in voltage and temperature.
mbed_official 76:aeb1df146756 239 *
mbed_official 76:aeb1df146756 240 * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official 76:aeb1df146756 241 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 76:aeb1df146756 242 * frequency of the crystal used. Otherwise, this function may
mbed_official 76:aeb1df146756 243 * have wrong result.
mbed_official 76:aeb1df146756 244 *
mbed_official 76:aeb1df146756 245 * - The result of this function could be not correct when using fractional
mbed_official 76:aeb1df146756 246 * value for HSE crystal.
mbed_official 76:aeb1df146756 247 * @param None
mbed_official 76:aeb1df146756 248 * @retval None
mbed_official 76:aeb1df146756 249 */
mbed_official 76:aeb1df146756 250 void SystemCoreClockUpdate (void)
mbed_official 76:aeb1df146756 251 {
mbed_official 76:aeb1df146756 252 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official 76:aeb1df146756 253
mbed_official 76:aeb1df146756 254 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 76:aeb1df146756 255 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 76:aeb1df146756 256
mbed_official 76:aeb1df146756 257 switch (tmp)
mbed_official 76:aeb1df146756 258 {
mbed_official 76:aeb1df146756 259 case 0x00: /* MSI used as system clock */
mbed_official 76:aeb1df146756 260 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 76:aeb1df146756 261 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 76:aeb1df146756 262 break;
mbed_official 76:aeb1df146756 263 case 0x04: /* HSI used as system clock */
mbed_official 76:aeb1df146756 264 SystemCoreClock = HSI_VALUE;
mbed_official 76:aeb1df146756 265 break;
mbed_official 76:aeb1df146756 266 case 0x08: /* HSE used as system clock */
mbed_official 76:aeb1df146756 267 SystemCoreClock = HSE_VALUE;
mbed_official 76:aeb1df146756 268 break;
mbed_official 76:aeb1df146756 269 case 0x0C: /* PLL used as system clock */
mbed_official 76:aeb1df146756 270 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 76:aeb1df146756 271 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 76:aeb1df146756 272 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official 76:aeb1df146756 273 pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official 76:aeb1df146756 274 plldiv = (plldiv >> 22) + 1;
mbed_official 76:aeb1df146756 275
mbed_official 76:aeb1df146756 276 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 76:aeb1df146756 277
mbed_official 76:aeb1df146756 278 if (pllsource == 0x00)
mbed_official 76:aeb1df146756 279 {
mbed_official 76:aeb1df146756 280 /* HSI oscillator clock selected as PLL clock entry */
mbed_official 76:aeb1df146756 281 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official 76:aeb1df146756 282 }
mbed_official 76:aeb1df146756 283 else
mbed_official 76:aeb1df146756 284 {
mbed_official 76:aeb1df146756 285 /* HSE selected as PLL clock entry */
mbed_official 76:aeb1df146756 286 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official 76:aeb1df146756 287 }
mbed_official 76:aeb1df146756 288 break;
mbed_official 76:aeb1df146756 289 default: /* MSI used as system clock */
mbed_official 76:aeb1df146756 290 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 76:aeb1df146756 291 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 76:aeb1df146756 292 break;
mbed_official 76:aeb1df146756 293 }
mbed_official 76:aeb1df146756 294 /* Compute HCLK clock frequency --------------------------------------------*/
mbed_official 76:aeb1df146756 295 /* Get HCLK prescaler */
mbed_official 76:aeb1df146756 296 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 76:aeb1df146756 297 /* HCLK clock frequency */
mbed_official 76:aeb1df146756 298 SystemCoreClock >>= tmp;
mbed_official 76:aeb1df146756 299 }
mbed_official 76:aeb1df146756 300
mbed_official 76:aeb1df146756 301 /**
mbed_official 139:e3413eddde57 302 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 139:e3413eddde57 303 * AHB/APBx prescalers and Flash settings
mbed_official 76:aeb1df146756 304 * @note This function should be called only once the RCC clock configuration
mbed_official 76:aeb1df146756 305 * is reset to the default reset state (done in SystemInit() function).
mbed_official 76:aeb1df146756 306 * @param None
mbed_official 76:aeb1df146756 307 * @retval None
mbed_official 76:aeb1df146756 308 */
mbed_official 129:0182c99221bc 309 void SetSysClock(void)
mbed_official 76:aeb1df146756 310 {
mbed_official 139:e3413eddde57 311 /* 1- Try to start with HSE and external clock */
mbed_official 139:e3413eddde57 312 #if USE_PLL_HSE_EXTC != 0
mbed_official 139:e3413eddde57 313 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 139:e3413eddde57 314 #endif
mbed_official 139:e3413eddde57 315 {
mbed_official 139:e3413eddde57 316 /* 2- If fail try to start with HSE and external xtal */
mbed_official 139:e3413eddde57 317 #if USE_PLL_HSE_XTAL != 0
mbed_official 139:e3413eddde57 318 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 139:e3413eddde57 319 #endif
mbed_official 139:e3413eddde57 320 {
mbed_official 139:e3413eddde57 321 /* 3- If fail start with HSI clock */
mbed_official 139:e3413eddde57 322 if (SetSysClock_PLL_HSI() == 0)
mbed_official 139:e3413eddde57 323 {
mbed_official 139:e3413eddde57 324 while(1)
mbed_official 139:e3413eddde57 325 {
mbed_official 139:e3413eddde57 326 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 139:e3413eddde57 327 }
mbed_official 139:e3413eddde57 328 }
mbed_official 139:e3413eddde57 329 }
mbed_official 139:e3413eddde57 330 }
mbed_official 76:aeb1df146756 331
mbed_official 139:e3413eddde57 332 /* Output SYSCLK on MCO pin(PA8) for debugging purpose */
mbed_official 139:e3413eddde57 333 /*
mbed_official 139:e3413eddde57 334 // Enable GPIOA clock
mbed_official 139:e3413eddde57 335 RCC_AHBPeriphClockCmd(RCC_AHBPeriph_GPIOA, ENABLE);
mbed_official 139:e3413eddde57 336 // Configure MCO pin (PA8)
mbed_official 139:e3413eddde57 337 GPIO_InitTypeDef GPIO_InitStructure;
mbed_official 139:e3413eddde57 338 GPIO_InitStructure.GPIO_Pin = GPIO_Pin_8;
mbed_official 139:e3413eddde57 339 GPIO_InitStructure.GPIO_Speed = GPIO_Speed_40MHz;
mbed_official 139:e3413eddde57 340 GPIO_InitStructure.GPIO_Mode = GPIO_Mode_AF;
mbed_official 139:e3413eddde57 341 GPIO_InitStructure.GPIO_OType = GPIO_OType_PP;
mbed_official 139:e3413eddde57 342 GPIO_InitStructure.GPIO_PuPd = GPIO_PuPd_UP;
mbed_official 139:e3413eddde57 343 GPIO_Init(GPIOA, &GPIO_InitStructure);
mbed_official 139:e3413eddde57 344 // Select the clock to output
mbed_official 139:e3413eddde57 345 RCC_MCOConfig(RCC_MCOSource_SYSCLK, RCC_MCODiv_1);
mbed_official 139:e3413eddde57 346 */
mbed_official 139:e3413eddde57 347 }
mbed_official 139:e3413eddde57 348
mbed_official 139:e3413eddde57 349 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 139:e3413eddde57 350 /******************************************************************************/
mbed_official 139:e3413eddde57 351 /* PLL (clocked by HSE) used as System clock source */
mbed_official 139:e3413eddde57 352 /******************************************************************************/
mbed_official 139:e3413eddde57 353 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 139:e3413eddde57 354 {
mbed_official 139:e3413eddde57 355 __IO uint32_t StartUpCounter = 0;
mbed_official 139:e3413eddde57 356 __IO uint32_t HSEStatus = 0;
mbed_official 139:e3413eddde57 357
mbed_official 139:e3413eddde57 358 /* Bypass HSE: can be done only if HSE is OFF */
mbed_official 139:e3413eddde57 359 RCC->CR &= ((uint32_t)~RCC_CR_HSEON); /* To be sure HSE is OFF */
mbed_official 139:e3413eddde57 360 if (bypass != 0)
mbed_official 76:aeb1df146756 361 {
mbed_official 139:e3413eddde57 362 RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
mbed_official 76:aeb1df146756 363 }
mbed_official 76:aeb1df146756 364 else
mbed_official 76:aeb1df146756 365 {
mbed_official 139:e3413eddde57 366 RCC->CR &= ((uint32_t)~RCC_CR_HSEBYP);
mbed_official 76:aeb1df146756 367 }
mbed_official 139:e3413eddde57 368
mbed_official 139:e3413eddde57 369 /* Enable HSE */
mbed_official 139:e3413eddde57 370 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
mbed_official 139:e3413eddde57 371
mbed_official 139:e3413eddde57 372 /* Wait till HSE is ready */
mbed_official 139:e3413eddde57 373 do
mbed_official 139:e3413eddde57 374 {
mbed_official 139:e3413eddde57 375 HSEStatus = RCC->CR & RCC_CR_HSERDY;
mbed_official 139:e3413eddde57 376 StartUpCounter++;
mbed_official 139:e3413eddde57 377 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
mbed_official 139:e3413eddde57 378
mbed_official 139:e3413eddde57 379 /* Check if HSE has started correctly */
mbed_official 139:e3413eddde57 380 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
mbed_official 76:aeb1df146756 381 {
mbed_official 129:0182c99221bc 382 /* Enable 64-bit access */
mbed_official 129:0182c99221bc 383 FLASH->ACR |= FLASH_ACR_ACC64;
mbed_official 139:e3413eddde57 384
mbed_official 129:0182c99221bc 385 /* Enable Prefetch Buffer */
mbed_official 129:0182c99221bc 386 FLASH->ACR |= FLASH_ACR_PRFTEN;
mbed_official 76:aeb1df146756 387
mbed_official 129:0182c99221bc 388 /* Flash 1 wait state (latency) */
mbed_official 129:0182c99221bc 389 FLASH->ACR |= FLASH_ACR_LATENCY;
mbed_official 139:e3413eddde57 390
mbed_official 76:aeb1df146756 391 /* Power enable */
mbed_official 76:aeb1df146756 392 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
mbed_official 139:e3413eddde57 393
mbed_official 76:aeb1df146756 394 /* Select the Voltage Range 1 (1.8 V) */
mbed_official 76:aeb1df146756 395 PWR->CR = PWR_CR_VOS_0;
mbed_official 129:0182c99221bc 396
mbed_official 76:aeb1df146756 397 /* Wait Until the Voltage Regulator is ready */
mbed_official 76:aeb1df146756 398 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
mbed_official 76:aeb1df146756 399 {
mbed_official 76:aeb1df146756 400 }
mbed_official 129:0182c99221bc 401
mbed_official 129:0182c99221bc 402 /* PLL configuration */
mbed_official 139:e3413eddde57 403 /* SYSCLK = 24 MHz ((8 MHz * 6) / 2) */
mbed_official 139:e3413eddde57 404 /* USBCLK = 48 MHz (8 MHz * 6) --> USB OK */
mbed_official 129:0182c99221bc 405 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV));
mbed_official 139:e3413eddde57 406 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSE | RCC_CFGR_PLLMUL6 | RCC_CFGR_PLLDIV2
mbed_official 139:e3413eddde57 407 | RCC_CFGR_HPRE_DIV1 /* HCLK = 24 MHz */
mbed_official 139:e3413eddde57 408 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 24 MHz */
mbed_official 139:e3413eddde57 409 | RCC_CFGR_PPRE1_DIV1); /* PCLK1 = 24 MHz */
mbed_official 129:0182c99221bc 410
mbed_official 129:0182c99221bc 411 /* Enable PLL */
mbed_official 129:0182c99221bc 412 RCC->CR |= RCC_CR_PLLON;
mbed_official 129:0182c99221bc 413
mbed_official 129:0182c99221bc 414 /* Wait till PLL is ready */
mbed_official 129:0182c99221bc 415 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 129:0182c99221bc 416 {
mbed_official 129:0182c99221bc 417 }
mbed_official 139:e3413eddde57 418
mbed_official 129:0182c99221bc 419 /* Select PLL as system clock source */
mbed_official 76:aeb1df146756 420 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 129:0182c99221bc 421 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 76:aeb1df146756 422
mbed_official 129:0182c99221bc 423 /* Wait till PLL is used as system clock source */
mbed_official 129:0182c99221bc 424 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 76:aeb1df146756 425 {
mbed_official 76:aeb1df146756 426 }
mbed_official 139:e3413eddde57 427
mbed_official 139:e3413eddde57 428 return 1; // OK
mbed_official 76:aeb1df146756 429 }
mbed_official 76:aeb1df146756 430 else
mbed_official 76:aeb1df146756 431 {
mbed_official 139:e3413eddde57 432 return 0; // FAIL
mbed_official 139:e3413eddde57 433 }
mbed_official 139:e3413eddde57 434 }
mbed_official 139:e3413eddde57 435 #endif
mbed_official 139:e3413eddde57 436
mbed_official 139:e3413eddde57 437 /******************************************************************************/
mbed_official 139:e3413eddde57 438 /* PLL (clocked by HSI) used as System clock source */
mbed_official 139:e3413eddde57 439 /******************************************************************************/
mbed_official 139:e3413eddde57 440 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 139:e3413eddde57 441 {
mbed_official 139:e3413eddde57 442 __IO uint32_t StartUpCounter = 0;
mbed_official 139:e3413eddde57 443 __IO uint32_t HSIStatus = 0;
mbed_official 139:e3413eddde57 444
mbed_official 139:e3413eddde57 445 /* Enable HSI */
mbed_official 139:e3413eddde57 446 RCC->CR |= ((uint32_t)RCC_CR_HSION);
mbed_official 139:e3413eddde57 447
mbed_official 139:e3413eddde57 448 /* Wait till HSI is ready */
mbed_official 139:e3413eddde57 449 do
mbed_official 139:e3413eddde57 450 {
mbed_official 139:e3413eddde57 451 HSIStatus = RCC->CR & RCC_CR_HSIRDY;
mbed_official 139:e3413eddde57 452 StartUpCounter++;
mbed_official 139:e3413eddde57 453 } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
mbed_official 139:e3413eddde57 454
mbed_official 139:e3413eddde57 455 if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
mbed_official 139:e3413eddde57 456 {
mbed_official 139:e3413eddde57 457 /* Enable 64-bit access */
mbed_official 139:e3413eddde57 458 FLASH->ACR |= FLASH_ACR_ACC64;
mbed_official 139:e3413eddde57 459
mbed_official 139:e3413eddde57 460 /* Enable Prefetch Buffer */
mbed_official 139:e3413eddde57 461 FLASH->ACR |= FLASH_ACR_PRFTEN;
mbed_official 139:e3413eddde57 462
mbed_official 139:e3413eddde57 463 /* Flash 1 wait state (latency) */
mbed_official 139:e3413eddde57 464 FLASH->ACR |= FLASH_ACR_LATENCY;
mbed_official 139:e3413eddde57 465
mbed_official 139:e3413eddde57 466 /* Power enable */
mbed_official 139:e3413eddde57 467 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
mbed_official 139:e3413eddde57 468
mbed_official 139:e3413eddde57 469 /* Select the Voltage Range 1 (1.8 V) */
mbed_official 139:e3413eddde57 470 PWR->CR = PWR_CR_VOS_0;
mbed_official 139:e3413eddde57 471
mbed_official 139:e3413eddde57 472 /* Wait Until the Voltage Regulator is ready */
mbed_official 139:e3413eddde57 473 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
mbed_official 139:e3413eddde57 474 {
mbed_official 139:e3413eddde57 475 }
mbed_official 139:e3413eddde57 476
mbed_official 139:e3413eddde57 477 /* PLL configuration */
mbed_official 139:e3413eddde57 478 /* SYSCLK = 32 MHz ((16 MHz * 4) / 2) */
mbed_official 139:e3413eddde57 479 /* USBCLK = 64 MHz (16 MHz * 4) --> USB not possible */
mbed_official 139:e3413eddde57 480 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL | RCC_CFGR_PLLDIV));
mbed_official 139:e3413eddde57 481 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI | RCC_CFGR_PLLMUL4 | RCC_CFGR_PLLDIV2
mbed_official 139:e3413eddde57 482 | RCC_CFGR_HPRE_DIV1 /* HCLK = 32 MHz */
mbed_official 139:e3413eddde57 483 | RCC_CFGR_PPRE2_DIV1 /* PCLK2 = 32 MHz */
mbed_official 139:e3413eddde57 484 | RCC_CFGR_PPRE1_DIV1); /* PCLK1 = 32 MHz */
mbed_official 139:e3413eddde57 485
mbed_official 139:e3413eddde57 486 /* Enable PLL */
mbed_official 139:e3413eddde57 487 RCC->CR |= RCC_CR_PLLON;
mbed_official 139:e3413eddde57 488
mbed_official 139:e3413eddde57 489 /* Wait till PLL is ready */
mbed_official 139:e3413eddde57 490 while((RCC->CR & RCC_CR_PLLRDY) == 0)
mbed_official 139:e3413eddde57 491 {
mbed_official 139:e3413eddde57 492 }
mbed_official 139:e3413eddde57 493
mbed_official 139:e3413eddde57 494 /* Select PLL as system clock source */
mbed_official 139:e3413eddde57 495 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 139:e3413eddde57 496 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
mbed_official 139:e3413eddde57 497
mbed_official 139:e3413eddde57 498 /* Wait till PLL is used as system clock source */
mbed_official 139:e3413eddde57 499 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
mbed_official 139:e3413eddde57 500 {
mbed_official 139:e3413eddde57 501 }
mbed_official 139:e3413eddde57 502
mbed_official 139:e3413eddde57 503 return 1; // OK
mbed_official 139:e3413eddde57 504 }
mbed_official 139:e3413eddde57 505 else
mbed_official 139:e3413eddde57 506 {
mbed_official 139:e3413eddde57 507 return 0; // FAIL
mbed_official 76:aeb1df146756 508 }
mbed_official 76:aeb1df146756 509 }
mbed_official 76:aeb1df146756 510
mbed_official 76:aeb1df146756 511 /**
mbed_official 76:aeb1df146756 512 * @}
mbed_official 76:aeb1df146756 513 */
mbed_official 76:aeb1df146756 514
mbed_official 76:aeb1df146756 515 /**
mbed_official 76:aeb1df146756 516 * @}
mbed_official 76:aeb1df146756 517 */
mbed_official 76:aeb1df146756 518
mbed_official 76:aeb1df146756 519 /**
mbed_official 76:aeb1df146756 520 * @}
mbed_official 76:aeb1df146756 521 */
mbed_official 76:aeb1df146756 522
mbed_official 76:aeb1df146756 523 /******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/