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targets/cmsis/TARGET_STM/TARGET_NUCLEO_L152RE/system_stm32l1xx.c@76:aeb1df146756, 2014-01-27 (annotated)

Committer:
mbed_official
Date:
Mon Jan 27 14:30:07 2014 +0000
Revision:
76:aeb1df146756
Child:
106:ced8cbb51063
Synchronized with git revision a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd



Full URL: https://github.com/mbedmicro/mbed/commit/a31ec9c5f7bcb5c8a1b2eced103f6a1dfa921abd/



Add NUCLEO_L152RE

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UserRevisionLine numberNew contents of line
mbed_official 76:aeb1df146756 1 /**
mbed_official 76:aeb1df146756 2 ******************************************************************************
mbed_official 76:aeb1df146756 3 * @file system_stm32l1xx.c
mbed_official 76:aeb1df146756 4 * @author MCD Application Team
mbed_official 76:aeb1df146756 5 * @version V1.2.0
mbed_official 76:aeb1df146756 6 * @date 11-January-2014
mbed_official 76:aeb1df146756 7 * @brief CMSIS Cortex-M3 Device Peripheral Access Layer System Source File.
mbed_official 76:aeb1df146756 8 * This file contains the system clock configuration for STM32L1xx Ultra
mbed_official 76:aeb1df146756 9 * Low power devices, and is generated by the clock configuration
mbed_official 76:aeb1df146756 10 * tool STM32L1xx_Clock_Configuration_V1.2.0.xls
mbed_official 76:aeb1df146756 11 *
mbed_official 76:aeb1df146756 12 * 1. This file provides two functions and one global variable to be called from
mbed_official 76:aeb1df146756 13 * user application:
mbed_official 76:aeb1df146756 14 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
mbed_official 76:aeb1df146756 15 * and Divider factors, AHB/APBx prescalers and Flash settings),
mbed_official 76:aeb1df146756 16 * depending on the configuration made in the clock xls tool.
mbed_official 76:aeb1df146756 17 * This function is called at startup just after reset and
mbed_official 76:aeb1df146756 18 * before branch to main program. This call is made inside
mbed_official 76:aeb1df146756 19 * the "startup_stm32l1xx_xx.s" file.
mbed_official 76:aeb1df146756 20 *
mbed_official 76:aeb1df146756 21 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 76:aeb1df146756 22 * by the user application to setup the SysTick
mbed_official 76:aeb1df146756 23 * timer or configure other parameters.
mbed_official 76:aeb1df146756 24 *
mbed_official 76:aeb1df146756 25 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 76:aeb1df146756 26 * be called whenever the core clock is changed
mbed_official 76:aeb1df146756 27 * during program execution.
mbed_official 76:aeb1df146756 28 *
mbed_official 76:aeb1df146756 29 * 2. After each device reset the MSI (2.1 MHz Range) is used as system clock source.
mbed_official 76:aeb1df146756 30 * Then SystemInit() function is called, in "startup_stm32l1xx_xx.s" file, to
mbed_official 76:aeb1df146756 31 * configure the system clock before to branch to main program.
mbed_official 76:aeb1df146756 32 *
mbed_official 76:aeb1df146756 33 * 3. If the system clock source selected by user fails to startup, the SystemInit()
mbed_official 76:aeb1df146756 34 * function will do nothing and MSI still used as system clock source. User can
mbed_official 76:aeb1df146756 35 * add some code to deal with this issue inside the SetSysClock() function.
mbed_official 76:aeb1df146756 36 *
mbed_official 76:aeb1df146756 37 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
mbed_official 76:aeb1df146756 38 * in "stm32l1xx.h" file. When HSE is used as system clock source, directly or
mbed_official 76:aeb1df146756 39 * through PLL, and you are using different crystal you have to adapt the HSE
mbed_official 76:aeb1df146756 40 * value to your own configuration.
mbed_official 76:aeb1df146756 41 *
mbed_official 76:aeb1df146756 42 * 5. This file configures the system clock as follows:
mbed_official 76:aeb1df146756 43 *=============================================================================
mbed_official 76:aeb1df146756 44 * System Clock Configuration
mbed_official 76:aeb1df146756 45 *=============================================================================
mbed_official 76:aeb1df146756 46 * System clock source | HSI
mbed_official 76:aeb1df146756 47 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 48 * SYSCLK | 16000000 Hz
mbed_official 76:aeb1df146756 49 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 50 * HCLK | 16000000 Hz
mbed_official 76:aeb1df146756 51 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 52 * AHB Prescaler | 1
mbed_official 76:aeb1df146756 53 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 54 * APB1 Prescaler | 1
mbed_official 76:aeb1df146756 55 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 56 * APB2 Prescaler | 1
mbed_official 76:aeb1df146756 57 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 58 * HSE Frequency | 8000000 Hz
mbed_official 76:aeb1df146756 59 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 60 * PLL DIV | Not Used
mbed_official 76:aeb1df146756 61 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 62 * PLL MUL | Not Used
mbed_official 76:aeb1df146756 63 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 64 * VDD | 3.3 V
mbed_official 76:aeb1df146756 65 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 66 * Vcore | 1.8 V (Range 1)
mbed_official 76:aeb1df146756 67 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 68 * Flash Latency | 0 WS
mbed_official 76:aeb1df146756 69 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 70 * Require 48MHz for USB clock | Disabled
mbed_official 76:aeb1df146756 71 *-----------------------------------------------------------------------------
mbed_official 76:aeb1df146756 72 *=============================================================================
mbed_official 76:aeb1df146756 73 * @attention
mbed_official 76:aeb1df146756 74 *
mbed_official 76:aeb1df146756 75 * <h2><center>&copy; COPYRIGHT 2013 STMicroelectronics</center></h2>
mbed_official 76:aeb1df146756 76 *
mbed_official 76:aeb1df146756 77 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mbed_official 76:aeb1df146756 78 * You may not use this file except in compliance with the License.
mbed_official 76:aeb1df146756 79 * You may obtain a copy of the License at:
mbed_official 76:aeb1df146756 80 *
mbed_official 76:aeb1df146756 81 * http://www.st.com/software_license_agreement_liberty_v2
mbed_official 76:aeb1df146756 82 *
mbed_official 76:aeb1df146756 83 * Unless required by applicable law or agreed to in writing, software
mbed_official 76:aeb1df146756 84 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 76:aeb1df146756 85 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 76:aeb1df146756 86 * See the License for the specific language governing permissions and
mbed_official 76:aeb1df146756 87 * limitations under the License.
mbed_official 76:aeb1df146756 88 *
mbed_official 76:aeb1df146756 89 ******************************************************************************
mbed_official 76:aeb1df146756 90 */
mbed_official 76:aeb1df146756 91
mbed_official 76:aeb1df146756 92 /** @addtogroup CMSIS
mbed_official 76:aeb1df146756 93 * @{
mbed_official 76:aeb1df146756 94 */
mbed_official 76:aeb1df146756 95
mbed_official 76:aeb1df146756 96 /** @addtogroup stm32l1xx_system
mbed_official 76:aeb1df146756 97 * @{
mbed_official 76:aeb1df146756 98 */
mbed_official 76:aeb1df146756 99
mbed_official 76:aeb1df146756 100 /** @addtogroup STM32L1xx_System_Private_Includes
mbed_official 76:aeb1df146756 101 * @{
mbed_official 76:aeb1df146756 102 */
mbed_official 76:aeb1df146756 103
mbed_official 76:aeb1df146756 104 #include "stm32l1xx.h"
mbed_official 76:aeb1df146756 105
mbed_official 76:aeb1df146756 106 /**
mbed_official 76:aeb1df146756 107 * @}
mbed_official 76:aeb1df146756 108 */
mbed_official 76:aeb1df146756 109
mbed_official 76:aeb1df146756 110 /** @addtogroup STM32L1xx_System_Private_TypesDefinitions
mbed_official 76:aeb1df146756 111 * @{
mbed_official 76:aeb1df146756 112 */
mbed_official 76:aeb1df146756 113
mbed_official 76:aeb1df146756 114 /**
mbed_official 76:aeb1df146756 115 * @}
mbed_official 76:aeb1df146756 116 */
mbed_official 76:aeb1df146756 117
mbed_official 76:aeb1df146756 118 /** @addtogroup STM32L1xx_System_Private_Defines
mbed_official 76:aeb1df146756 119 * @{
mbed_official 76:aeb1df146756 120 */
mbed_official 76:aeb1df146756 121
mbed_official 76:aeb1df146756 122 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 76:aeb1df146756 123 Internal SRAM. */
mbed_official 76:aeb1df146756 124 /* #define VECT_TAB_SRAM */
mbed_official 76:aeb1df146756 125 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
mbed_official 76:aeb1df146756 126 This value must be a multiple of 0x200. */
mbed_official 76:aeb1df146756 127 /**
mbed_official 76:aeb1df146756 128 * @}
mbed_official 76:aeb1df146756 129 */
mbed_official 76:aeb1df146756 130
mbed_official 76:aeb1df146756 131 /** @addtogroup STM32L1xx_System_Private_Macros
mbed_official 76:aeb1df146756 132 * @{
mbed_official 76:aeb1df146756 133 */
mbed_official 76:aeb1df146756 134
mbed_official 76:aeb1df146756 135 /**
mbed_official 76:aeb1df146756 136 * @}
mbed_official 76:aeb1df146756 137 */
mbed_official 76:aeb1df146756 138
mbed_official 76:aeb1df146756 139 /** @addtogroup STM32L1xx_System_Private_Variables
mbed_official 76:aeb1df146756 140 * @{
mbed_official 76:aeb1df146756 141 */
mbed_official 76:aeb1df146756 142 uint32_t SystemCoreClock = 16000000;
mbed_official 76:aeb1df146756 143 __I uint8_t PLLMulTable[9] = {3, 4, 6, 8, 12, 16, 24, 32, 48};
mbed_official 76:aeb1df146756 144 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 76:aeb1df146756 145
mbed_official 76:aeb1df146756 146 /**
mbed_official 76:aeb1df146756 147 * @}
mbed_official 76:aeb1df146756 148 */
mbed_official 76:aeb1df146756 149
mbed_official 76:aeb1df146756 150 /** @addtogroup STM32L1xx_System_Private_FunctionPrototypes
mbed_official 76:aeb1df146756 151 * @{
mbed_official 76:aeb1df146756 152 */
mbed_official 76:aeb1df146756 153
mbed_official 76:aeb1df146756 154 static void SetSysClock(void);
mbed_official 76:aeb1df146756 155
mbed_official 76:aeb1df146756 156 /**
mbed_official 76:aeb1df146756 157 * @}
mbed_official 76:aeb1df146756 158 */
mbed_official 76:aeb1df146756 159
mbed_official 76:aeb1df146756 160 /** @addtogroup STM32L1xx_System_Private_Functions
mbed_official 76:aeb1df146756 161 * @{
mbed_official 76:aeb1df146756 162 */
mbed_official 76:aeb1df146756 163
mbed_official 76:aeb1df146756 164 /**
mbed_official 76:aeb1df146756 165 * @brief Setup the microcontroller system.
mbed_official 76:aeb1df146756 166 * Initialize the Embedded Flash Interface, the PLL and update the
mbed_official 76:aeb1df146756 167 * SystemCoreClock variable.
mbed_official 76:aeb1df146756 168 * @param None
mbed_official 76:aeb1df146756 169 * @retval None
mbed_official 76:aeb1df146756 170 */
mbed_official 76:aeb1df146756 171 void SystemInit (void)
mbed_official 76:aeb1df146756 172 {
mbed_official 76:aeb1df146756 173 /*!< Set MSION bit */
mbed_official 76:aeb1df146756 174 RCC->CR |= (uint32_t)0x00000100;
mbed_official 76:aeb1df146756 175
mbed_official 76:aeb1df146756 176 /*!< Reset SW[1:0], HPRE[3:0], PPRE1[2:0], PPRE2[2:0], MCOSEL[2:0] and MCOPRE[2:0] bits */
mbed_official 76:aeb1df146756 177 RCC->CFGR &= (uint32_t)0x88FFC00C;
mbed_official 76:aeb1df146756 178
mbed_official 76:aeb1df146756 179 /*!< Reset HSION, HSEON, CSSON and PLLON bits */
mbed_official 76:aeb1df146756 180 RCC->CR &= (uint32_t)0xEEFEFFFE;
mbed_official 76:aeb1df146756 181
mbed_official 76:aeb1df146756 182 /*!< Reset HSEBYP bit */
mbed_official 76:aeb1df146756 183 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 76:aeb1df146756 184
mbed_official 76:aeb1df146756 185 /*!< Reset PLLSRC, PLLMUL[3:0] and PLLDIV[1:0] bits */
mbed_official 76:aeb1df146756 186 RCC->CFGR &= (uint32_t)0xFF02FFFF;
mbed_official 76:aeb1df146756 187
mbed_official 76:aeb1df146756 188 /*!< Disable all interrupts */
mbed_official 76:aeb1df146756 189 RCC->CIR = 0x00000000;
mbed_official 76:aeb1df146756 190
mbed_official 76:aeb1df146756 191 /* Configure the System clock frequency, AHB/APBx prescalers and Flash settings */
mbed_official 76:aeb1df146756 192 SetSysClock();
mbed_official 76:aeb1df146756 193
mbed_official 76:aeb1df146756 194 #ifdef VECT_TAB_SRAM
mbed_official 76:aeb1df146756 195 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
mbed_official 76:aeb1df146756 196 #else
mbed_official 76:aeb1df146756 197 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
mbed_official 76:aeb1df146756 198 #endif
mbed_official 76:aeb1df146756 199 }
mbed_official 76:aeb1df146756 200
mbed_official 76:aeb1df146756 201 /**
mbed_official 76:aeb1df146756 202 * @brief Update SystemCoreClock according to Clock Register Values
mbed_official 76:aeb1df146756 203 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 76:aeb1df146756 204 * be used by the user application to setup the SysTick timer or configure
mbed_official 76:aeb1df146756 205 * other parameters.
mbed_official 76:aeb1df146756 206 *
mbed_official 76:aeb1df146756 207 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 76:aeb1df146756 208 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 76:aeb1df146756 209 * based on this variable will be incorrect.
mbed_official 76:aeb1df146756 210 *
mbed_official 76:aeb1df146756 211 * @note - The system frequency computed by this function is not the real
mbed_official 76:aeb1df146756 212 * frequency in the chip. It is calculated based on the predefined
mbed_official 76:aeb1df146756 213 * constant and the selected clock source:
mbed_official 76:aeb1df146756 214 *
mbed_official 76:aeb1df146756 215 * - If SYSCLK source is MSI, SystemCoreClock will contain the MSI
mbed_official 76:aeb1df146756 216 * value as defined by the MSI range.
mbed_official 76:aeb1df146756 217 *
mbed_official 76:aeb1df146756 218 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 76:aeb1df146756 219 *
mbed_official 76:aeb1df146756 220 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 76:aeb1df146756 221 *
mbed_official 76:aeb1df146756 222 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 76:aeb1df146756 223 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 76:aeb1df146756 224 *
mbed_official 76:aeb1df146756 225 * (*) HSI_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official 76:aeb1df146756 226 * 16 MHz) but the real value may vary depending on the variations
mbed_official 76:aeb1df146756 227 * in voltage and temperature.
mbed_official 76:aeb1df146756 228 *
mbed_official 76:aeb1df146756 229 * (**) HSE_VALUE is a constant defined in stm32l1xx.h file (default value
mbed_official 76:aeb1df146756 230 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
mbed_official 76:aeb1df146756 231 * frequency of the crystal used. Otherwise, this function may
mbed_official 76:aeb1df146756 232 * have wrong result.
mbed_official 76:aeb1df146756 233 *
mbed_official 76:aeb1df146756 234 * - The result of this function could be not correct when using fractional
mbed_official 76:aeb1df146756 235 * value for HSE crystal.
mbed_official 76:aeb1df146756 236 * @param None
mbed_official 76:aeb1df146756 237 * @retval None
mbed_official 76:aeb1df146756 238 */
mbed_official 76:aeb1df146756 239 void SystemCoreClockUpdate (void)
mbed_official 76:aeb1df146756 240 {
mbed_official 76:aeb1df146756 241 uint32_t tmp = 0, pllmul = 0, plldiv = 0, pllsource = 0, msirange = 0;
mbed_official 76:aeb1df146756 242
mbed_official 76:aeb1df146756 243 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 76:aeb1df146756 244 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 76:aeb1df146756 245
mbed_official 76:aeb1df146756 246 switch (tmp)
mbed_official 76:aeb1df146756 247 {
mbed_official 76:aeb1df146756 248 case 0x00: /* MSI used as system clock */
mbed_official 76:aeb1df146756 249 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 76:aeb1df146756 250 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 76:aeb1df146756 251 break;
mbed_official 76:aeb1df146756 252 case 0x04: /* HSI used as system clock */
mbed_official 76:aeb1df146756 253 SystemCoreClock = HSI_VALUE;
mbed_official 76:aeb1df146756 254 break;
mbed_official 76:aeb1df146756 255 case 0x08: /* HSE used as system clock */
mbed_official 76:aeb1df146756 256 SystemCoreClock = HSE_VALUE;
mbed_official 76:aeb1df146756 257 break;
mbed_official 76:aeb1df146756 258 case 0x0C: /* PLL used as system clock */
mbed_official 76:aeb1df146756 259 /* Get PLL clock source and multiplication factor ----------------------*/
mbed_official 76:aeb1df146756 260 pllmul = RCC->CFGR & RCC_CFGR_PLLMUL;
mbed_official 76:aeb1df146756 261 plldiv = RCC->CFGR & RCC_CFGR_PLLDIV;
mbed_official 76:aeb1df146756 262 pllmul = PLLMulTable[(pllmul >> 18)];
mbed_official 76:aeb1df146756 263 plldiv = (plldiv >> 22) + 1;
mbed_official 76:aeb1df146756 264
mbed_official 76:aeb1df146756 265 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
mbed_official 76:aeb1df146756 266
mbed_official 76:aeb1df146756 267 if (pllsource == 0x00)
mbed_official 76:aeb1df146756 268 {
mbed_official 76:aeb1df146756 269 /* HSI oscillator clock selected as PLL clock entry */
mbed_official 76:aeb1df146756 270 SystemCoreClock = (((HSI_VALUE) * pllmul) / plldiv);
mbed_official 76:aeb1df146756 271 }
mbed_official 76:aeb1df146756 272 else
mbed_official 76:aeb1df146756 273 {
mbed_official 76:aeb1df146756 274 /* HSE selected as PLL clock entry */
mbed_official 76:aeb1df146756 275 SystemCoreClock = (((HSE_VALUE) * pllmul) / plldiv);
mbed_official 76:aeb1df146756 276 }
mbed_official 76:aeb1df146756 277 break;
mbed_official 76:aeb1df146756 278 default: /* MSI used as system clock */
mbed_official 76:aeb1df146756 279 msirange = (RCC->ICSCR & RCC_ICSCR_MSIRANGE) >> 13;
mbed_official 76:aeb1df146756 280 SystemCoreClock = (32768 * (1 << (msirange + 1)));
mbed_official 76:aeb1df146756 281 break;
mbed_official 76:aeb1df146756 282 }
mbed_official 76:aeb1df146756 283 /* Compute HCLK clock frequency --------------------------------------------*/
mbed_official 76:aeb1df146756 284 /* Get HCLK prescaler */
mbed_official 76:aeb1df146756 285 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 76:aeb1df146756 286 /* HCLK clock frequency */
mbed_official 76:aeb1df146756 287 SystemCoreClock >>= tmp;
mbed_official 76:aeb1df146756 288 }
mbed_official 76:aeb1df146756 289
mbed_official 76:aeb1df146756 290 /**
mbed_official 76:aeb1df146756 291 * @brief Configures the System clock frequency, AHB/APBx prescalers and Flash
mbed_official 76:aeb1df146756 292 * settings.
mbed_official 76:aeb1df146756 293 * @note This function should be called only once the RCC clock configuration
mbed_official 76:aeb1df146756 294 * is reset to the default reset state (done in SystemInit() function).
mbed_official 76:aeb1df146756 295 * @param None
mbed_official 76:aeb1df146756 296 * @retval None
mbed_official 76:aeb1df146756 297 */
mbed_official 76:aeb1df146756 298 static void SetSysClock(void)
mbed_official 76:aeb1df146756 299 {
mbed_official 76:aeb1df146756 300 __IO uint32_t StartUpCounter = 0, HSIStatus = 0;
mbed_official 76:aeb1df146756 301
mbed_official 76:aeb1df146756 302 /* SYSCLK, HCLK, PCLK2 and PCLK1 configuration ---------------------------*/
mbed_official 76:aeb1df146756 303 /* Enable HSI */
mbed_official 76:aeb1df146756 304 RCC->CR |= ((uint32_t)RCC_CR_HSION);
mbed_official 76:aeb1df146756 305
mbed_official 76:aeb1df146756 306 /* Wait till HSI is ready and if Time out is reached exit */
mbed_official 76:aeb1df146756 307 do
mbed_official 76:aeb1df146756 308 {
mbed_official 76:aeb1df146756 309 HSIStatus = RCC->CR & RCC_CR_HSIRDY;
mbed_official 76:aeb1df146756 310 } while((HSIStatus == 0) && (StartUpCounter != HSI_STARTUP_TIMEOUT));
mbed_official 76:aeb1df146756 311
mbed_official 76:aeb1df146756 312 if ((RCC->CR & RCC_CR_HSIRDY) != RESET)
mbed_official 76:aeb1df146756 313 {
mbed_official 76:aeb1df146756 314 HSIStatus = (uint32_t)0x01;
mbed_official 76:aeb1df146756 315 }
mbed_official 76:aeb1df146756 316 else
mbed_official 76:aeb1df146756 317 {
mbed_official 76:aeb1df146756 318 HSIStatus = (uint32_t)0x00;
mbed_official 76:aeb1df146756 319 }
mbed_official 76:aeb1df146756 320
mbed_official 76:aeb1df146756 321 if (HSIStatus == (uint32_t)0x01)
mbed_official 76:aeb1df146756 322 {
mbed_official 76:aeb1df146756 323 /* Flash 0 wait state */
mbed_official 76:aeb1df146756 324 FLASH->ACR &= ~FLASH_ACR_LATENCY;
mbed_official 76:aeb1df146756 325
mbed_official 76:aeb1df146756 326 /* Disable Prefetch Buffer */
mbed_official 76:aeb1df146756 327 FLASH->ACR &= ~FLASH_ACR_PRFTEN;
mbed_official 76:aeb1df146756 328
mbed_official 76:aeb1df146756 329 /* Disable 64-bit access */
mbed_official 76:aeb1df146756 330 FLASH->ACR &= ~FLASH_ACR_ACC64;
mbed_official 76:aeb1df146756 331
mbed_official 76:aeb1df146756 332
mbed_official 76:aeb1df146756 333 /* Power enable */
mbed_official 76:aeb1df146756 334 RCC->APB1ENR |= RCC_APB1ENR_PWREN;
mbed_official 76:aeb1df146756 335
mbed_official 76:aeb1df146756 336 /* Select the Voltage Range 1 (1.8 V) */
mbed_official 76:aeb1df146756 337 PWR->CR = PWR_CR_VOS_0;
mbed_official 76:aeb1df146756 338
mbed_official 76:aeb1df146756 339
mbed_official 76:aeb1df146756 340 /* Wait Until the Voltage Regulator is ready */
mbed_official 76:aeb1df146756 341 while((PWR->CSR & PWR_CSR_VOSF) != RESET)
mbed_official 76:aeb1df146756 342 {
mbed_official 76:aeb1df146756 343 }
mbed_official 76:aeb1df146756 344
mbed_official 76:aeb1df146756 345 /* HCLK = SYSCLK /1*/
mbed_official 76:aeb1df146756 346 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
mbed_official 76:aeb1df146756 347 /* PCLK2 = HCLK /1*/
mbed_official 76:aeb1df146756 348 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
mbed_official 76:aeb1df146756 349
mbed_official 76:aeb1df146756 350 /* PCLK1 = HCLK /1*/
mbed_official 76:aeb1df146756 351 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV1;
mbed_official 76:aeb1df146756 352
mbed_official 76:aeb1df146756 353 /* Select HSI as system clock source */
mbed_official 76:aeb1df146756 354 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
mbed_official 76:aeb1df146756 355 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_HSI;
mbed_official 76:aeb1df146756 356
mbed_official 76:aeb1df146756 357 /* Wait till HSI is used as system clock source */
mbed_official 76:aeb1df146756 358 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_HSI)
mbed_official 76:aeb1df146756 359 {
mbed_official 76:aeb1df146756 360 }
mbed_official 76:aeb1df146756 361 }
mbed_official 76:aeb1df146756 362 else
mbed_official 76:aeb1df146756 363 {
mbed_official 76:aeb1df146756 364 /* If HSI fails to start-up, the application will have wrong clock
mbed_official 76:aeb1df146756 365 configuration. User can add here some code to deal with this error */
mbed_official 76:aeb1df146756 366 }
mbed_official 76:aeb1df146756 367 }
mbed_official 76:aeb1df146756 368
mbed_official 76:aeb1df146756 369 /**
mbed_official 76:aeb1df146756 370 * @}
mbed_official 76:aeb1df146756 371 */
mbed_official 76:aeb1df146756 372
mbed_official 76:aeb1df146756 373 /**
mbed_official 76:aeb1df146756 374 * @}
mbed_official 76:aeb1df146756 375 */
mbed_official 76:aeb1df146756 376
mbed_official 76:aeb1df146756 377 /**
mbed_official 76:aeb1df146756 378 * @}
mbed_official 76:aeb1df146756 379 */
mbed_official 76:aeb1df146756 380
mbed_official 76:aeb1df146756 381 /******************* (C) COPYRIGHT 2013 STMicroelectronics *****END OF FILE****/