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targets/cmsis/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/system_stm32f4xx.c@429:cc5da43e7bf6, 2014-12-09 (annotated)

Committer:
mbed_official
Date:
Tue Dec 09 14:15:07 2014 +0000
Revision:
429:cc5da43e7bf6
Synchronized with git revision 75673df767b901eda5c6ea6c737b58deb390c955



Full URL: https://github.com/mbedmicro/mbed/commit/75673df767b901eda5c6ea6c737b58deb390c955/



Add support for mDot with STM32F411RE processor

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 429:cc5da43e7bf6 1 /**
mbed_official 429:cc5da43e7bf6 2 ******************************************************************************
mbed_official 429:cc5da43e7bf6 3 * @file system_stm32f4xx.c
mbed_official 429:cc5da43e7bf6 4 * @author MCD Application Team
mbed_official 429:cc5da43e7bf6 5 * @version V2.1.0
mbed_official 429:cc5da43e7bf6 6 * @date 19-June-2014
mbed_official 429:cc5da43e7bf6 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
mbed_official 429:cc5da43e7bf6 8 *
mbed_official 429:cc5da43e7bf6 9 * This file provides two functions and one global variable to be called from
mbed_official 429:cc5da43e7bf6 10 * user application:
mbed_official 429:cc5da43e7bf6 11 * - SystemInit(): This function is called at startup just after reset and
mbed_official 429:cc5da43e7bf6 12 * before branch to main program. This call is made inside
mbed_official 429:cc5da43e7bf6 13 * the "startup_stm32f4xx.s" file.
mbed_official 429:cc5da43e7bf6 14 *
mbed_official 429:cc5da43e7bf6 15 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
mbed_official 429:cc5da43e7bf6 16 * by the user application to setup the SysTick
mbed_official 429:cc5da43e7bf6 17 * timer or configure other parameters.
mbed_official 429:cc5da43e7bf6 18 *
mbed_official 429:cc5da43e7bf6 19 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
mbed_official 429:cc5da43e7bf6 20 * be called whenever the core clock is changed
mbed_official 429:cc5da43e7bf6 21 * during program execution.
mbed_official 429:cc5da43e7bf6 22 *
mbed_official 429:cc5da43e7bf6 23 * This file configures the system clock as follows:
mbed_official 429:cc5da43e7bf6 24 *-----------------------------------------------------------------------------
mbed_official 429:cc5da43e7bf6 25 * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
mbed_official 429:cc5da43e7bf6 26 * | (external 8 MHz clock) | (internal 16 MHz)
mbed_official 429:cc5da43e7bf6 27 * | 2- PLL_HSE_XTAL |
mbed_official 429:cc5da43e7bf6 28 * | (external 8 MHz xtal) |
mbed_official 429:cc5da43e7bf6 29 *-----------------------------------------------------------------------------
mbed_official 429:cc5da43e7bf6 30 * SYSCLK(MHz) | 96 | 96
mbed_official 429:cc5da43e7bf6 31 *-----------------------------------------------------------------------------
mbed_official 429:cc5da43e7bf6 32 * AHBCLK (MHz) | 96 | 96
mbed_official 429:cc5da43e7bf6 33 *-----------------------------------------------------------------------------
mbed_official 429:cc5da43e7bf6 34 * APB1CLK (MHz) | 48 | 48
mbed_official 429:cc5da43e7bf6 35 *-----------------------------------------------------------------------------
mbed_official 429:cc5da43e7bf6 36 * APB2CLK (MHz) | 96 | 96
mbed_official 429:cc5da43e7bf6 37 *-----------------------------------------------------------------------------
mbed_official 429:cc5da43e7bf6 38 * USB capable (48 MHz precise clock) | YES | NO
mbed_official 429:cc5da43e7bf6 39 *-----------------------------------------------------------------------------
mbed_official 429:cc5da43e7bf6 40 ******************************************************************************
mbed_official 429:cc5da43e7bf6 41 * @attention
mbed_official 429:cc5da43e7bf6 42 *
mbed_official 429:cc5da43e7bf6 43 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
mbed_official 429:cc5da43e7bf6 44 *
mbed_official 429:cc5da43e7bf6 45 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 429:cc5da43e7bf6 46 * are permitted provided that the following conditions are met:
mbed_official 429:cc5da43e7bf6 47 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 429:cc5da43e7bf6 48 * this list of conditions and the following disclaimer.
mbed_official 429:cc5da43e7bf6 49 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 429:cc5da43e7bf6 50 * this list of conditions and the following disclaimer in the documentation
mbed_official 429:cc5da43e7bf6 51 * and/or other materials provided with the distribution.
mbed_official 429:cc5da43e7bf6 52 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 429:cc5da43e7bf6 53 * may be used to endorse or promote products derived from this software
mbed_official 429:cc5da43e7bf6 54 * without specific prior written permission.
mbed_official 429:cc5da43e7bf6 55 *
mbed_official 429:cc5da43e7bf6 56 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 429:cc5da43e7bf6 57 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 429:cc5da43e7bf6 58 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 429:cc5da43e7bf6 59 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 429:cc5da43e7bf6 60 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 429:cc5da43e7bf6 61 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 429:cc5da43e7bf6 62 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 429:cc5da43e7bf6 63 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 429:cc5da43e7bf6 64 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 429:cc5da43e7bf6 65 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 429:cc5da43e7bf6 66 *
mbed_official 429:cc5da43e7bf6 67 ******************************************************************************
mbed_official 429:cc5da43e7bf6 68 */
mbed_official 429:cc5da43e7bf6 69
mbed_official 429:cc5da43e7bf6 70 /** @addtogroup CMSIS
mbed_official 429:cc5da43e7bf6 71 * @{
mbed_official 429:cc5da43e7bf6 72 */
mbed_official 429:cc5da43e7bf6 73
mbed_official 429:cc5da43e7bf6 74 /** @addtogroup stm32f4xx_system
mbed_official 429:cc5da43e7bf6 75 * @{
mbed_official 429:cc5da43e7bf6 76 */
mbed_official 429:cc5da43e7bf6 77
mbed_official 429:cc5da43e7bf6 78 /** @addtogroup STM32F4xx_System_Private_Includes
mbed_official 429:cc5da43e7bf6 79 * @{
mbed_official 429:cc5da43e7bf6 80 */
mbed_official 429:cc5da43e7bf6 81
mbed_official 429:cc5da43e7bf6 82
mbed_official 429:cc5da43e7bf6 83 #include "stm32f4xx.h"
mbed_official 429:cc5da43e7bf6 84 #include "hal_tick.h"
mbed_official 429:cc5da43e7bf6 85
mbed_official 429:cc5da43e7bf6 86 #if !defined (HSE_VALUE)
mbed_official 429:cc5da43e7bf6 87 #define HSE_VALUE ((uint32_t)8000000) /*!< Default value of the External oscillator in Hz */
mbed_official 429:cc5da43e7bf6 88 #endif /* HSE_VALUE */
mbed_official 429:cc5da43e7bf6 89
mbed_official 429:cc5da43e7bf6 90 #if !defined (HSI_VALUE)
mbed_official 429:cc5da43e7bf6 91 #define HSI_VALUE ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
mbed_official 429:cc5da43e7bf6 92 #endif /* HSI_VALUE */
mbed_official 429:cc5da43e7bf6 93
mbed_official 429:cc5da43e7bf6 94 /**
mbed_official 429:cc5da43e7bf6 95 * @}
mbed_official 429:cc5da43e7bf6 96 */
mbed_official 429:cc5da43e7bf6 97
mbed_official 429:cc5da43e7bf6 98 /** @addtogroup STM32F4xx_System_Private_TypesDefinitions
mbed_official 429:cc5da43e7bf6 99 * @{
mbed_official 429:cc5da43e7bf6 100 */
mbed_official 429:cc5da43e7bf6 101
mbed_official 429:cc5da43e7bf6 102 /**
mbed_official 429:cc5da43e7bf6 103 * @}
mbed_official 429:cc5da43e7bf6 104 */
mbed_official 429:cc5da43e7bf6 105
mbed_official 429:cc5da43e7bf6 106 /** @addtogroup STM32F4xx_System_Private_Defines
mbed_official 429:cc5da43e7bf6 107 * @{
mbed_official 429:cc5da43e7bf6 108 */
mbed_official 429:cc5da43e7bf6 109
mbed_official 429:cc5da43e7bf6 110 /************************* Miscellaneous Configuration ************************/
mbed_official 429:cc5da43e7bf6 111 /*!< Uncomment the following line if you need to use external SRAM or SDRAM mounted
mbed_official 429:cc5da43e7bf6 112 on STM324xG_EVAL/STM324x9I_EVAL boards as data memory */
mbed_official 429:cc5da43e7bf6 113 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 429:cc5da43e7bf6 114 /* #define DATA_IN_ExtSRAM */
mbed_official 429:cc5da43e7bf6 115 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 429:cc5da43e7bf6 116
mbed_official 429:cc5da43e7bf6 117 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 429:cc5da43e7bf6 118 /* #define DATA_IN_ExtSDRAM */
mbed_official 429:cc5da43e7bf6 119 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 429:cc5da43e7bf6 120
mbed_official 429:cc5da43e7bf6 121 #if defined(DATA_IN_ExtSRAM) && defined(DATA_IN_ExtSDRAM)
mbed_official 429:cc5da43e7bf6 122 #error "Please select DATA_IN_ExtSRAM or DATA_IN_ExtSDRAM "
mbed_official 429:cc5da43e7bf6 123 #endif /* DATA_IN_ExtSRAM && DATA_IN_ExtSDRAM */
mbed_official 429:cc5da43e7bf6 124
mbed_official 429:cc5da43e7bf6 125 /*!< Uncomment the following line if you need to relocate your vector Table in
mbed_official 429:cc5da43e7bf6 126 Internal SRAM. */
mbed_official 429:cc5da43e7bf6 127 /* #define VECT_TAB_SRAM */
mbed_official 429:cc5da43e7bf6 128 #define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
mbed_official 429:cc5da43e7bf6 129 This value must be a multiple of 0x200. */
mbed_official 429:cc5da43e7bf6 130 /******************************************************************************/
mbed_official 429:cc5da43e7bf6 131
mbed_official 429:cc5da43e7bf6 132 /**
mbed_official 429:cc5da43e7bf6 133 * @}
mbed_official 429:cc5da43e7bf6 134 */
mbed_official 429:cc5da43e7bf6 135
mbed_official 429:cc5da43e7bf6 136 /** @addtogroup STM32F4xx_System_Private_Macros
mbed_official 429:cc5da43e7bf6 137 * @{
mbed_official 429:cc5da43e7bf6 138 */
mbed_official 429:cc5da43e7bf6 139
mbed_official 429:cc5da43e7bf6 140 /* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
mbed_official 429:cc5da43e7bf6 141 #if !defined (USE_PLL_HSE_EXTC)
mbed_official 429:cc5da43e7bf6 142 #define USE_PLL_HSE_EXTC (1) /* Use external clock */
mbed_official 429:cc5da43e7bf6 143 #endif
mbed_official 429:cc5da43e7bf6 144 #if !defined (USE_PLL_HSE_XTAL)
mbed_official 429:cc5da43e7bf6 145 #define USE_PLL_HSE_XTAL (1) /* Use external xtal */
mbed_official 429:cc5da43e7bf6 146 #endif
mbed_official 429:cc5da43e7bf6 147
mbed_official 429:cc5da43e7bf6 148 /**
mbed_official 429:cc5da43e7bf6 149 * @}
mbed_official 429:cc5da43e7bf6 150 */
mbed_official 429:cc5da43e7bf6 151
mbed_official 429:cc5da43e7bf6 152 /** @addtogroup STM32F4xx_System_Private_Variables
mbed_official 429:cc5da43e7bf6 153 * @{
mbed_official 429:cc5da43e7bf6 154 */
mbed_official 429:cc5da43e7bf6 155 /* This variable is updated in three ways:
mbed_official 429:cc5da43e7bf6 156 1) by calling CMSIS function SystemCoreClockUpdate()
mbed_official 429:cc5da43e7bf6 157 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
mbed_official 429:cc5da43e7bf6 158 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
mbed_official 429:cc5da43e7bf6 159 Note: If you use this function to configure the system clock; then there
mbed_official 429:cc5da43e7bf6 160 is no need to call the 2 first functions listed above, since SystemCoreClock
mbed_official 429:cc5da43e7bf6 161 variable is updated automatically.
mbed_official 429:cc5da43e7bf6 162 */
mbed_official 429:cc5da43e7bf6 163 uint32_t SystemCoreClock = 16000000;
mbed_official 429:cc5da43e7bf6 164 __IO const uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
mbed_official 429:cc5da43e7bf6 165
mbed_official 429:cc5da43e7bf6 166 /**
mbed_official 429:cc5da43e7bf6 167 * @}
mbed_official 429:cc5da43e7bf6 168 */
mbed_official 429:cc5da43e7bf6 169
mbed_official 429:cc5da43e7bf6 170 /** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
mbed_official 429:cc5da43e7bf6 171 * @{
mbed_official 429:cc5da43e7bf6 172 */
mbed_official 429:cc5da43e7bf6 173
mbed_official 429:cc5da43e7bf6 174 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 429:cc5da43e7bf6 175 static void SystemInit_ExtMemCtl(void);
mbed_official 429:cc5da43e7bf6 176 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 429:cc5da43e7bf6 177
mbed_official 429:cc5da43e7bf6 178 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 429:cc5da43e7bf6 179 uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
mbed_official 429:cc5da43e7bf6 180 #endif
mbed_official 429:cc5da43e7bf6 181
mbed_official 429:cc5da43e7bf6 182 uint8_t SetSysClock_PLL_HSI(void);
mbed_official 429:cc5da43e7bf6 183
mbed_official 429:cc5da43e7bf6 184 /**
mbed_official 429:cc5da43e7bf6 185 * @}
mbed_official 429:cc5da43e7bf6 186 */
mbed_official 429:cc5da43e7bf6 187
mbed_official 429:cc5da43e7bf6 188 /** @addtogroup STM32F4xx_System_Private_Functions
mbed_official 429:cc5da43e7bf6 189 * @{
mbed_official 429:cc5da43e7bf6 190 */
mbed_official 429:cc5da43e7bf6 191
mbed_official 429:cc5da43e7bf6 192 /**
mbed_official 429:cc5da43e7bf6 193 * @brief Setup the microcontroller system
mbed_official 429:cc5da43e7bf6 194 * Initialize the FPU setting, vector table location and External memory
mbed_official 429:cc5da43e7bf6 195 * configuration.
mbed_official 429:cc5da43e7bf6 196 * @param None
mbed_official 429:cc5da43e7bf6 197 * @retval None
mbed_official 429:cc5da43e7bf6 198 */
mbed_official 429:cc5da43e7bf6 199 void SystemInit(void)
mbed_official 429:cc5da43e7bf6 200 {
mbed_official 429:cc5da43e7bf6 201 /* FPU settings ------------------------------------------------------------*/
mbed_official 429:cc5da43e7bf6 202 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mbed_official 429:cc5da43e7bf6 203 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
mbed_official 429:cc5da43e7bf6 204 #endif
mbed_official 429:cc5da43e7bf6 205 /* Reset the RCC clock configuration to the default reset state ------------*/
mbed_official 429:cc5da43e7bf6 206 /* Set HSION bit */
mbed_official 429:cc5da43e7bf6 207 RCC->CR |= (uint32_t)0x00000001;
mbed_official 429:cc5da43e7bf6 208
mbed_official 429:cc5da43e7bf6 209 /* Reset CFGR register */
mbed_official 429:cc5da43e7bf6 210 RCC->CFGR = 0x00000000;
mbed_official 429:cc5da43e7bf6 211
mbed_official 429:cc5da43e7bf6 212 /* Reset HSEON, CSSON and PLLON bits */
mbed_official 429:cc5da43e7bf6 213 RCC->CR &= (uint32_t)0xFEF6FFFF;
mbed_official 429:cc5da43e7bf6 214
mbed_official 429:cc5da43e7bf6 215 /* Reset PLLCFGR register */
mbed_official 429:cc5da43e7bf6 216 RCC->PLLCFGR = 0x24003010;
mbed_official 429:cc5da43e7bf6 217
mbed_official 429:cc5da43e7bf6 218 /* Reset HSEBYP bit */
mbed_official 429:cc5da43e7bf6 219 RCC->CR &= (uint32_t)0xFFFBFFFF;
mbed_official 429:cc5da43e7bf6 220
mbed_official 429:cc5da43e7bf6 221 /* Disable all interrupts */
mbed_official 429:cc5da43e7bf6 222 RCC->CIR = 0x00000000;
mbed_official 429:cc5da43e7bf6 223
mbed_official 429:cc5da43e7bf6 224 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 429:cc5da43e7bf6 225 SystemInit_ExtMemCtl();
mbed_official 429:cc5da43e7bf6 226 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 429:cc5da43e7bf6 227
mbed_official 429:cc5da43e7bf6 228 /* Configure the Vector Table location add offset address ------------------*/
mbed_official 429:cc5da43e7bf6 229 #ifdef VECT_TAB_SRAM
mbed_official 429:cc5da43e7bf6 230 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
mbed_official 429:cc5da43e7bf6 231 #else
mbed_official 429:cc5da43e7bf6 232 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
mbed_official 429:cc5da43e7bf6 233 #endif
mbed_official 429:cc5da43e7bf6 234
mbed_official 429:cc5da43e7bf6 235 /* Configure the Cube driver */
mbed_official 429:cc5da43e7bf6 236 SystemCoreClock = 16000000; // At this stage the HSI is used as system clock
mbed_official 429:cc5da43e7bf6 237 HAL_Init();
mbed_official 429:cc5da43e7bf6 238
mbed_official 429:cc5da43e7bf6 239 /* Configure the System clock source, PLL Multiplier and Divider factors,
mbed_official 429:cc5da43e7bf6 240 AHB/APBx prescalers and Flash settings */
mbed_official 429:cc5da43e7bf6 241 SetSysClock();
mbed_official 429:cc5da43e7bf6 242
mbed_official 429:cc5da43e7bf6 243 /* Reset the timer to avoid issues after the RAM initialization */
mbed_official 429:cc5da43e7bf6 244 TIM_MST_RESET_ON;
mbed_official 429:cc5da43e7bf6 245 TIM_MST_RESET_OFF;
mbed_official 429:cc5da43e7bf6 246 }
mbed_official 429:cc5da43e7bf6 247
mbed_official 429:cc5da43e7bf6 248 /**
mbed_official 429:cc5da43e7bf6 249 * @brief Update SystemCoreClock variable according to Clock Register Values.
mbed_official 429:cc5da43e7bf6 250 * The SystemCoreClock variable contains the core clock (HCLK), it can
mbed_official 429:cc5da43e7bf6 251 * be used by the user application to setup the SysTick timer or configure
mbed_official 429:cc5da43e7bf6 252 * other parameters.
mbed_official 429:cc5da43e7bf6 253 *
mbed_official 429:cc5da43e7bf6 254 * @note Each time the core clock (HCLK) changes, this function must be called
mbed_official 429:cc5da43e7bf6 255 * to update SystemCoreClock variable value. Otherwise, any configuration
mbed_official 429:cc5da43e7bf6 256 * based on this variable will be incorrect.
mbed_official 429:cc5da43e7bf6 257 *
mbed_official 429:cc5da43e7bf6 258 * @note - The system frequency computed by this function is not the real
mbed_official 429:cc5da43e7bf6 259 * frequency in the chip. It is calculated based on the predefined
mbed_official 429:cc5da43e7bf6 260 * constant and the selected clock source:
mbed_official 429:cc5da43e7bf6 261 *
mbed_official 429:cc5da43e7bf6 262 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
mbed_official 429:cc5da43e7bf6 263 *
mbed_official 429:cc5da43e7bf6 264 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 429:cc5da43e7bf6 265 *
mbed_official 429:cc5da43e7bf6 266 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
mbed_official 429:cc5da43e7bf6 267 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
mbed_official 429:cc5da43e7bf6 268 *
mbed_official 429:cc5da43e7bf6 269 * (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
mbed_official 429:cc5da43e7bf6 270 * 16 MHz) but the real value may vary depending on the variations
mbed_official 429:cc5da43e7bf6 271 * in voltage and temperature.
mbed_official 429:cc5da43e7bf6 272 *
mbed_official 429:cc5da43e7bf6 273 * (**) HSE_VALUE is a constant defined in stm32f4xx_hal_conf.h file (its value
mbed_official 429:cc5da43e7bf6 274 * depends on the application requirements), user has to ensure that HSE_VALUE
mbed_official 429:cc5da43e7bf6 275 * is same as the real frequency of the crystal used. Otherwise, this function
mbed_official 429:cc5da43e7bf6 276 * may have wrong result.
mbed_official 429:cc5da43e7bf6 277 *
mbed_official 429:cc5da43e7bf6 278 * - The result of this function could be not correct when using fractional
mbed_official 429:cc5da43e7bf6 279 * value for HSE crystal.
mbed_official 429:cc5da43e7bf6 280 *
mbed_official 429:cc5da43e7bf6 281 * @param None
mbed_official 429:cc5da43e7bf6 282 * @retval None
mbed_official 429:cc5da43e7bf6 283 */
mbed_official 429:cc5da43e7bf6 284 void SystemCoreClockUpdate(void)
mbed_official 429:cc5da43e7bf6 285 {
mbed_official 429:cc5da43e7bf6 286 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
mbed_official 429:cc5da43e7bf6 287
mbed_official 429:cc5da43e7bf6 288 /* Get SYSCLK source -------------------------------------------------------*/
mbed_official 429:cc5da43e7bf6 289 tmp = RCC->CFGR & RCC_CFGR_SWS;
mbed_official 429:cc5da43e7bf6 290
mbed_official 429:cc5da43e7bf6 291 switch (tmp)
mbed_official 429:cc5da43e7bf6 292 {
mbed_official 429:cc5da43e7bf6 293 case 0x00: /* HSI used as system clock source */
mbed_official 429:cc5da43e7bf6 294 SystemCoreClock = HSI_VALUE;
mbed_official 429:cc5da43e7bf6 295 break;
mbed_official 429:cc5da43e7bf6 296 case 0x04: /* HSE used as system clock source */
mbed_official 429:cc5da43e7bf6 297 SystemCoreClock = HSE_VALUE;
mbed_official 429:cc5da43e7bf6 298 break;
mbed_official 429:cc5da43e7bf6 299 case 0x08: /* PLL used as system clock source */
mbed_official 429:cc5da43e7bf6 300
mbed_official 429:cc5da43e7bf6 301 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
mbed_official 429:cc5da43e7bf6 302 SYSCLK = PLL_VCO / PLL_P
mbed_official 429:cc5da43e7bf6 303 */
mbed_official 429:cc5da43e7bf6 304 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
mbed_official 429:cc5da43e7bf6 305 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
mbed_official 429:cc5da43e7bf6 306
mbed_official 429:cc5da43e7bf6 307 if (pllsource != 0)
mbed_official 429:cc5da43e7bf6 308 {
mbed_official 429:cc5da43e7bf6 309 /* HSE used as PLL clock source */
mbed_official 429:cc5da43e7bf6 310 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 429:cc5da43e7bf6 311 }
mbed_official 429:cc5da43e7bf6 312 else
mbed_official 429:cc5da43e7bf6 313 {
mbed_official 429:cc5da43e7bf6 314 /* HSI used as PLL clock source */
mbed_official 429:cc5da43e7bf6 315 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
mbed_official 429:cc5da43e7bf6 316 }
mbed_official 429:cc5da43e7bf6 317
mbed_official 429:cc5da43e7bf6 318 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
mbed_official 429:cc5da43e7bf6 319 SystemCoreClock = pllvco/pllp;
mbed_official 429:cc5da43e7bf6 320 break;
mbed_official 429:cc5da43e7bf6 321 default:
mbed_official 429:cc5da43e7bf6 322 SystemCoreClock = HSI_VALUE;
mbed_official 429:cc5da43e7bf6 323 break;
mbed_official 429:cc5da43e7bf6 324 }
mbed_official 429:cc5da43e7bf6 325 /* Compute HCLK frequency --------------------------------------------------*/
mbed_official 429:cc5da43e7bf6 326 /* Get HCLK prescaler */
mbed_official 429:cc5da43e7bf6 327 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
mbed_official 429:cc5da43e7bf6 328 /* HCLK frequency */
mbed_official 429:cc5da43e7bf6 329 SystemCoreClock >>= tmp;
mbed_official 429:cc5da43e7bf6 330 }
mbed_official 429:cc5da43e7bf6 331
mbed_official 429:cc5da43e7bf6 332 #if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
mbed_official 429:cc5da43e7bf6 333 /**
mbed_official 429:cc5da43e7bf6 334 * @brief Setup the external memory controller.
mbed_official 429:cc5da43e7bf6 335 * Called in startup_stm32f4xx.s before jump to main.
mbed_official 429:cc5da43e7bf6 336 * This function configures the external memories (SRAM/SDRAM)
mbed_official 429:cc5da43e7bf6 337 * This SRAM/SDRAM will be used as program data memory (including heap and stack).
mbed_official 429:cc5da43e7bf6 338 * @param None
mbed_official 429:cc5da43e7bf6 339 * @retval None
mbed_official 429:cc5da43e7bf6 340 */
mbed_official 429:cc5da43e7bf6 341 void SystemInit_ExtMemCtl(void)
mbed_official 429:cc5da43e7bf6 342 {
mbed_official 429:cc5da43e7bf6 343 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 429:cc5da43e7bf6 344 #if defined (DATA_IN_ExtSDRAM)
mbed_official 429:cc5da43e7bf6 345 register uint32_t tmpreg = 0, timeout = 0xFFFF;
mbed_official 429:cc5da43e7bf6 346 register uint32_t index;
mbed_official 429:cc5da43e7bf6 347
mbed_official 429:cc5da43e7bf6 348 /* Enable GPIOC, GPIOD, GPIOE, GPIOF, GPIOG, GPIOH and GPIOI interface
mbed_official 429:cc5da43e7bf6 349 clock */
mbed_official 429:cc5da43e7bf6 350 RCC->AHB1ENR |= 0x000001F8;
mbed_official 429:cc5da43e7bf6 351
mbed_official 429:cc5da43e7bf6 352 /* Connect PDx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 353 GPIOD->AFR[0] = 0x000000CC;
mbed_official 429:cc5da43e7bf6 354 GPIOD->AFR[1] = 0xCC000CCC;
mbed_official 429:cc5da43e7bf6 355 /* Configure PDx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 356 GPIOD->MODER = 0xA02A000A;
mbed_official 429:cc5da43e7bf6 357 /* Configure PDx pins speed to 50 MHz */
mbed_official 429:cc5da43e7bf6 358 GPIOD->OSPEEDR = 0xA02A000A;
mbed_official 429:cc5da43e7bf6 359 /* Configure PDx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 360 GPIOD->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 361 /* No pull-up, pull-down for PDx pins */
mbed_official 429:cc5da43e7bf6 362 GPIOD->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 363
mbed_official 429:cc5da43e7bf6 364 /* Connect PEx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 365 GPIOE->AFR[0] = 0xC00000CC;
mbed_official 429:cc5da43e7bf6 366 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 367 /* Configure PEx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 368 GPIOE->MODER = 0xAAAA800A;
mbed_official 429:cc5da43e7bf6 369 /* Configure PEx pins speed to 50 MHz */
mbed_official 429:cc5da43e7bf6 370 GPIOE->OSPEEDR = 0xAAAA800A;
mbed_official 429:cc5da43e7bf6 371 /* Configure PEx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 372 GPIOE->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 373 /* No pull-up, pull-down for PEx pins */
mbed_official 429:cc5da43e7bf6 374 GPIOE->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 375
mbed_official 429:cc5da43e7bf6 376 /* Connect PFx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 377 GPIOF->AFR[0] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 378 GPIOF->AFR[1] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 379 /* Configure PFx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 380 GPIOF->MODER = 0xAA800AAA;
mbed_official 429:cc5da43e7bf6 381 /* Configure PFx pins speed to 50 MHz */
mbed_official 429:cc5da43e7bf6 382 GPIOF->OSPEEDR = 0xAA800AAA;
mbed_official 429:cc5da43e7bf6 383 /* Configure PFx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 384 GPIOF->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 385 /* No pull-up, pull-down for PFx pins */
mbed_official 429:cc5da43e7bf6 386 GPIOF->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 387
mbed_official 429:cc5da43e7bf6 388 /* Connect PGx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 389 GPIOG->AFR[0] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 390 GPIOG->AFR[1] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 391 /* Configure PGx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 392 GPIOG->MODER = 0xAAAAAAAA;
mbed_official 429:cc5da43e7bf6 393 /* Configure PGx pins speed to 50 MHz */
mbed_official 429:cc5da43e7bf6 394 GPIOG->OSPEEDR = 0xAAAAAAAA;
mbed_official 429:cc5da43e7bf6 395 /* Configure PGx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 396 GPIOG->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 397 /* No pull-up, pull-down for PGx pins */
mbed_official 429:cc5da43e7bf6 398 GPIOG->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 399
mbed_official 429:cc5da43e7bf6 400 /* Connect PHx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 401 GPIOH->AFR[0] = 0x00C0CC00;
mbed_official 429:cc5da43e7bf6 402 GPIOH->AFR[1] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 403 /* Configure PHx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 404 GPIOH->MODER = 0xAAAA08A0;
mbed_official 429:cc5da43e7bf6 405 /* Configure PHx pins speed to 50 MHz */
mbed_official 429:cc5da43e7bf6 406 GPIOH->OSPEEDR = 0xAAAA08A0;
mbed_official 429:cc5da43e7bf6 407 /* Configure PHx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 408 GPIOH->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 409 /* No pull-up, pull-down for PHx pins */
mbed_official 429:cc5da43e7bf6 410 GPIOH->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 411
mbed_official 429:cc5da43e7bf6 412 /* Connect PIx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 413 GPIOI->AFR[0] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 414 GPIOI->AFR[1] = 0x00000CC0;
mbed_official 429:cc5da43e7bf6 415 /* Configure PIx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 416 GPIOI->MODER = 0x0028AAAA;
mbed_official 429:cc5da43e7bf6 417 /* Configure PIx pins speed to 50 MHz */
mbed_official 429:cc5da43e7bf6 418 GPIOI->OSPEEDR = 0x0028AAAA;
mbed_official 429:cc5da43e7bf6 419 /* Configure PIx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 420 GPIOI->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 421 /* No pull-up, pull-down for PIx pins */
mbed_official 429:cc5da43e7bf6 422 GPIOI->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 423
mbed_official 429:cc5da43e7bf6 424 /*-- FMC Configuration ------------------------------------------------------*/
mbed_official 429:cc5da43e7bf6 425 /* Enable the FMC interface clock */
mbed_official 429:cc5da43e7bf6 426 RCC->AHB3ENR |= 0x00000001;
mbed_official 429:cc5da43e7bf6 427
mbed_official 429:cc5da43e7bf6 428 /* Configure and enable SDRAM bank1 */
mbed_official 429:cc5da43e7bf6 429 FMC_Bank5_6->SDCR[0] = 0x000019E0;
mbed_official 429:cc5da43e7bf6 430 FMC_Bank5_6->SDTR[0] = 0x01115351;
mbed_official 429:cc5da43e7bf6 431
mbed_official 429:cc5da43e7bf6 432 /* SDRAM initialization sequence */
mbed_official 429:cc5da43e7bf6 433 /* Clock enable command */
mbed_official 429:cc5da43e7bf6 434 FMC_Bank5_6->SDCMR = 0x00000011;
mbed_official 429:cc5da43e7bf6 435 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 429:cc5da43e7bf6 436 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 429:cc5da43e7bf6 437 {
mbed_official 429:cc5da43e7bf6 438 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 429:cc5da43e7bf6 439 }
mbed_official 429:cc5da43e7bf6 440
mbed_official 429:cc5da43e7bf6 441 /* Delay */
mbed_official 429:cc5da43e7bf6 442 for (index = 0; index<1000; index++);
mbed_official 429:cc5da43e7bf6 443
mbed_official 429:cc5da43e7bf6 444 /* PALL command */
mbed_official 429:cc5da43e7bf6 445 FMC_Bank5_6->SDCMR = 0x00000012;
mbed_official 429:cc5da43e7bf6 446 timeout = 0xFFFF;
mbed_official 429:cc5da43e7bf6 447 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 429:cc5da43e7bf6 448 {
mbed_official 429:cc5da43e7bf6 449 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 429:cc5da43e7bf6 450 }
mbed_official 429:cc5da43e7bf6 451
mbed_official 429:cc5da43e7bf6 452 /* Auto refresh command */
mbed_official 429:cc5da43e7bf6 453 FMC_Bank5_6->SDCMR = 0x00000073;
mbed_official 429:cc5da43e7bf6 454 timeout = 0xFFFF;
mbed_official 429:cc5da43e7bf6 455 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 429:cc5da43e7bf6 456 {
mbed_official 429:cc5da43e7bf6 457 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 429:cc5da43e7bf6 458 }
mbed_official 429:cc5da43e7bf6 459
mbed_official 429:cc5da43e7bf6 460 /* MRD register program */
mbed_official 429:cc5da43e7bf6 461 FMC_Bank5_6->SDCMR = 0x00046014;
mbed_official 429:cc5da43e7bf6 462 timeout = 0xFFFF;
mbed_official 429:cc5da43e7bf6 463 while((tmpreg != 0) && (timeout-- > 0))
mbed_official 429:cc5da43e7bf6 464 {
mbed_official 429:cc5da43e7bf6 465 tmpreg = FMC_Bank5_6->SDSR & 0x00000020;
mbed_official 429:cc5da43e7bf6 466 }
mbed_official 429:cc5da43e7bf6 467
mbed_official 429:cc5da43e7bf6 468 /* Set refresh count */
mbed_official 429:cc5da43e7bf6 469 tmpreg = FMC_Bank5_6->SDRTR;
mbed_official 429:cc5da43e7bf6 470 FMC_Bank5_6->SDRTR = (tmpreg | (0x0000027C<<1));
mbed_official 429:cc5da43e7bf6 471
mbed_official 429:cc5da43e7bf6 472 /* Disable write protection */
mbed_official 429:cc5da43e7bf6 473 tmpreg = FMC_Bank5_6->SDCR[0];
mbed_official 429:cc5da43e7bf6 474 FMC_Bank5_6->SDCR[0] = (tmpreg & 0xFFFFFDFF);
mbed_official 429:cc5da43e7bf6 475 #endif /* DATA_IN_ExtSDRAM */
mbed_official 429:cc5da43e7bf6 476 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 429:cc5da43e7bf6 477
mbed_official 429:cc5da43e7bf6 478 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
mbed_official 429:cc5da43e7bf6 479 #if defined(DATA_IN_ExtSRAM)
mbed_official 429:cc5da43e7bf6 480 /*-- GPIOs Configuration -----------------------------------------------------*/
mbed_official 429:cc5da43e7bf6 481 /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
mbed_official 429:cc5da43e7bf6 482 RCC->AHB1ENR |= 0x00000078;
mbed_official 429:cc5da43e7bf6 483
mbed_official 429:cc5da43e7bf6 484 /* Connect PDx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 485 GPIOD->AFR[0] = 0x00CCC0CC;
mbed_official 429:cc5da43e7bf6 486 GPIOD->AFR[1] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 487 /* Configure PDx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 488 GPIOD->MODER = 0xAAAA0A8A;
mbed_official 429:cc5da43e7bf6 489 /* Configure PDx pins speed to 100 MHz */
mbed_official 429:cc5da43e7bf6 490 GPIOD->OSPEEDR = 0xFFFF0FCF;
mbed_official 429:cc5da43e7bf6 491 /* Configure PDx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 492 GPIOD->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 493 /* No pull-up, pull-down for PDx pins */
mbed_official 429:cc5da43e7bf6 494 GPIOD->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 495
mbed_official 429:cc5da43e7bf6 496 /* Connect PEx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 497 GPIOE->AFR[0] = 0xC00CC0CC;
mbed_official 429:cc5da43e7bf6 498 GPIOE->AFR[1] = 0xCCCCCCCC;
mbed_official 429:cc5da43e7bf6 499 /* Configure PEx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 500 GPIOE->MODER = 0xAAAA828A;
mbed_official 429:cc5da43e7bf6 501 /* Configure PEx pins speed to 100 MHz */
mbed_official 429:cc5da43e7bf6 502 GPIOE->OSPEEDR = 0xFFFFC3CF;
mbed_official 429:cc5da43e7bf6 503 /* Configure PEx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 504 GPIOE->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 505 /* No pull-up, pull-down for PEx pins */
mbed_official 429:cc5da43e7bf6 506 GPIOE->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 507
mbed_official 429:cc5da43e7bf6 508 /* Connect PFx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 509 GPIOF->AFR[0] = 0x00CCCCCC;
mbed_official 429:cc5da43e7bf6 510 GPIOF->AFR[1] = 0xCCCC0000;
mbed_official 429:cc5da43e7bf6 511 /* Configure PFx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 512 GPIOF->MODER = 0xAA000AAA;
mbed_official 429:cc5da43e7bf6 513 /* Configure PFx pins speed to 100 MHz */
mbed_official 429:cc5da43e7bf6 514 GPIOF->OSPEEDR = 0xFF000FFF;
mbed_official 429:cc5da43e7bf6 515 /* Configure PFx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 516 GPIOF->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 517 /* No pull-up, pull-down for PFx pins */
mbed_official 429:cc5da43e7bf6 518 GPIOF->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 519
mbed_official 429:cc5da43e7bf6 520 /* Connect PGx pins to FMC Alternate function */
mbed_official 429:cc5da43e7bf6 521 GPIOG->AFR[0] = 0x00CCCCCC;
mbed_official 429:cc5da43e7bf6 522 GPIOG->AFR[1] = 0x000000C0;
mbed_official 429:cc5da43e7bf6 523 /* Configure PGx pins in Alternate function mode */
mbed_official 429:cc5da43e7bf6 524 GPIOG->MODER = 0x00085AAA;
mbed_official 429:cc5da43e7bf6 525 /* Configure PGx pins speed to 100 MHz */
mbed_official 429:cc5da43e7bf6 526 GPIOG->OSPEEDR = 0x000CAFFF;
mbed_official 429:cc5da43e7bf6 527 /* Configure PGx pins Output type to push-pull */
mbed_official 429:cc5da43e7bf6 528 GPIOG->OTYPER = 0x00000000;
mbed_official 429:cc5da43e7bf6 529 /* No pull-up, pull-down for PGx pins */
mbed_official 429:cc5da43e7bf6 530 GPIOG->PUPDR = 0x00000000;
mbed_official 429:cc5da43e7bf6 531
mbed_official 429:cc5da43e7bf6 532 /*-- FMC/FSMC Configuration --------------------------------------------------*/
mbed_official 429:cc5da43e7bf6 533 /* Enable the FMC/FSMC interface clock */
mbed_official 429:cc5da43e7bf6 534 RCC->AHB3ENR |= 0x00000001;
mbed_official 429:cc5da43e7bf6 535
mbed_official 429:cc5da43e7bf6 536 #if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx)|| defined(STM32F439xx)
mbed_official 429:cc5da43e7bf6 537 /* Configure and enable Bank1_SRAM2 */
mbed_official 429:cc5da43e7bf6 538 FMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 429:cc5da43e7bf6 539 FMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 429:cc5da43e7bf6 540 FMC_Bank1E->BWTR[2] = 0x0fffffff;
mbed_official 429:cc5da43e7bf6 541 #endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 429:cc5da43e7bf6 542
mbed_official 429:cc5da43e7bf6 543 #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx)|| defined(STM32F417xx)
mbed_official 429:cc5da43e7bf6 544 /* Configure and enable Bank1_SRAM2 */
mbed_official 429:cc5da43e7bf6 545 FSMC_Bank1->BTCR[2] = 0x00001011;
mbed_official 429:cc5da43e7bf6 546 FSMC_Bank1->BTCR[3] = 0x00000201;
mbed_official 429:cc5da43e7bf6 547 FSMC_Bank1E->BWTR[2] = 0x0FFFFFFF;
mbed_official 429:cc5da43e7bf6 548 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx */
mbed_official 429:cc5da43e7bf6 549
mbed_official 429:cc5da43e7bf6 550 #endif /* DATA_IN_ExtSRAM */
mbed_official 429:cc5da43e7bf6 551 #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
mbed_official 429:cc5da43e7bf6 552 }
mbed_official 429:cc5da43e7bf6 553 #endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
mbed_official 429:cc5da43e7bf6 554
mbed_official 429:cc5da43e7bf6 555 /**
mbed_official 429:cc5da43e7bf6 556 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
mbed_official 429:cc5da43e7bf6 557 * AHB/APBx prescalers and Flash settings
mbed_official 429:cc5da43e7bf6 558 * @note This function should be called only once the RCC clock configuration
mbed_official 429:cc5da43e7bf6 559 * is reset to the default reset state (done in SystemInit() function).
mbed_official 429:cc5da43e7bf6 560 * @param None
mbed_official 429:cc5da43e7bf6 561 * @retval None
mbed_official 429:cc5da43e7bf6 562 */
mbed_official 429:cc5da43e7bf6 563 void SetSysClock(void)
mbed_official 429:cc5da43e7bf6 564 {
mbed_official 429:cc5da43e7bf6 565 /* 1- Try to start with HSE and external clock */
mbed_official 429:cc5da43e7bf6 566 #if USE_PLL_HSE_EXTC != 0
mbed_official 429:cc5da43e7bf6 567 if (SetSysClock_PLL_HSE(1) == 0)
mbed_official 429:cc5da43e7bf6 568 #endif
mbed_official 429:cc5da43e7bf6 569 {
mbed_official 429:cc5da43e7bf6 570 /* 2- If fail try to start with HSE and external xtal */
mbed_official 429:cc5da43e7bf6 571 #if USE_PLL_HSE_XTAL != 0
mbed_official 429:cc5da43e7bf6 572 if (SetSysClock_PLL_HSE(0) == 0)
mbed_official 429:cc5da43e7bf6 573 #endif
mbed_official 429:cc5da43e7bf6 574 {
mbed_official 429:cc5da43e7bf6 575 /* 3- If fail start with HSI clock */
mbed_official 429:cc5da43e7bf6 576 if (SetSysClock_PLL_HSI() == 0)
mbed_official 429:cc5da43e7bf6 577 {
mbed_official 429:cc5da43e7bf6 578 while(1)
mbed_official 429:cc5da43e7bf6 579 {
mbed_official 429:cc5da43e7bf6 580 // [TODO] Put something here to tell the user that a problem occured...
mbed_official 429:cc5da43e7bf6 581 }
mbed_official 429:cc5da43e7bf6 582 }
mbed_official 429:cc5da43e7bf6 583 }
mbed_official 429:cc5da43e7bf6 584 }
mbed_official 429:cc5da43e7bf6 585
mbed_official 429:cc5da43e7bf6 586 /* Output clock on MCO2 pin(PC9) for debugging purpose */
mbed_official 429:cc5da43e7bf6 587 //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4); // 100 MHz / 4 = 25 MHz
mbed_official 429:cc5da43e7bf6 588 }
mbed_official 429:cc5da43e7bf6 589
mbed_official 429:cc5da43e7bf6 590 #if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
mbed_official 429:cc5da43e7bf6 591 /******************************************************************************/
mbed_official 429:cc5da43e7bf6 592 /* PLL (clocked by HSE) used as System clock source */
mbed_official 429:cc5da43e7bf6 593 /******************************************************************************/
mbed_official 429:cc5da43e7bf6 594 uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
mbed_official 429:cc5da43e7bf6 595 {
mbed_official 429:cc5da43e7bf6 596 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 429:cc5da43e7bf6 597 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 429:cc5da43e7bf6 598
mbed_official 429:cc5da43e7bf6 599 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 429:cc5da43e7bf6 600 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 429:cc5da43e7bf6 601 regarding system frequency refer to product datasheet. */
mbed_official 429:cc5da43e7bf6 602 __PWR_CLK_ENABLE();
mbed_official 429:cc5da43e7bf6 603 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 429:cc5da43e7bf6 604
mbed_official 429:cc5da43e7bf6 605 /* Enable HSE oscillator and activate PLL with HSE as source */
mbed_official 429:cc5da43e7bf6 606 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
mbed_official 429:cc5da43e7bf6 607 if (bypass == 0)
mbed_official 429:cc5da43e7bf6 608 {
mbed_official 429:cc5da43e7bf6 609 RCC_OscInitStruct.HSEState = RCC_HSE_ON; /* External 8 MHz xtal on OSC_IN/OSC_OUT */
mbed_official 429:cc5da43e7bf6 610 }
mbed_official 429:cc5da43e7bf6 611 else
mbed_official 429:cc5da43e7bf6 612 {
mbed_official 429:cc5da43e7bf6 613 RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; /* External 8 MHz clock on OSC_IN */
mbed_official 429:cc5da43e7bf6 614 }
mbed_official 429:cc5da43e7bf6 615 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 429:cc5da43e7bf6 616 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
mbed_official 429:cc5da43e7bf6 617 RCC_OscInitStruct.PLL.PLLM = HSE_VALUE/1000000; // VCO input clock = 1 MHz
mbed_official 429:cc5da43e7bf6 618 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
mbed_official 429:cc5da43e7bf6 619 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
mbed_official 429:cc5da43e7bf6 620 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4)
mbed_official 429:cc5da43e7bf6 621 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 429:cc5da43e7bf6 622 {
mbed_official 429:cc5da43e7bf6 623 return 0; // FAIL
mbed_official 429:cc5da43e7bf6 624 }
mbed_official 429:cc5da43e7bf6 625
mbed_official 429:cc5da43e7bf6 626 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 429:cc5da43e7bf6 627 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 429:cc5da43e7bf6 628 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
mbed_official 429:cc5da43e7bf6 629 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
mbed_official 429:cc5da43e7bf6 630 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
mbed_official 429:cc5da43e7bf6 631 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
mbed_official 429:cc5da43e7bf6 632 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
mbed_official 429:cc5da43e7bf6 633 {
mbed_official 429:cc5da43e7bf6 634 return 0; // FAIL
mbed_official 429:cc5da43e7bf6 635 }
mbed_official 429:cc5da43e7bf6 636
mbed_official 429:cc5da43e7bf6 637 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 429:cc5da43e7bf6 638
mbed_official 429:cc5da43e7bf6 639 //if (bypass == 0)
mbed_official 429:cc5da43e7bf6 640 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz with xtal
mbed_official 429:cc5da43e7bf6 641 //else
mbed_official 429:cc5da43e7bf6 642 // HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz with external clock
mbed_official 429:cc5da43e7bf6 643
mbed_official 429:cc5da43e7bf6 644 return 1; // OK
mbed_official 429:cc5da43e7bf6 645 }
mbed_official 429:cc5da43e7bf6 646 #endif
mbed_official 429:cc5da43e7bf6 647
mbed_official 429:cc5da43e7bf6 648 /******************************************************************************/
mbed_official 429:cc5da43e7bf6 649 /* PLL (clocked by HSI) used as System clock source */
mbed_official 429:cc5da43e7bf6 650 /******************************************************************************/
mbed_official 429:cc5da43e7bf6 651 uint8_t SetSysClock_PLL_HSI(void)
mbed_official 429:cc5da43e7bf6 652 {
mbed_official 429:cc5da43e7bf6 653 RCC_ClkInitTypeDef RCC_ClkInitStruct;
mbed_official 429:cc5da43e7bf6 654 RCC_OscInitTypeDef RCC_OscInitStruct;
mbed_official 429:cc5da43e7bf6 655
mbed_official 429:cc5da43e7bf6 656 /* The voltage scaling allows optimizing the power consumption when the device is
mbed_official 429:cc5da43e7bf6 657 clocked below the maximum system frequency, to update the voltage scaling value
mbed_official 429:cc5da43e7bf6 658 regarding system frequency refer to product datasheet. */
mbed_official 429:cc5da43e7bf6 659 __PWR_CLK_ENABLE();
mbed_official 429:cc5da43e7bf6 660 __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
mbed_official 429:cc5da43e7bf6 661
mbed_official 429:cc5da43e7bf6 662 /* Enable HSI oscillator and activate PLL with HSI as source */
mbed_official 429:cc5da43e7bf6 663 RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
mbed_official 429:cc5da43e7bf6 664 RCC_OscInitStruct.HSIState = RCC_HSI_ON;
mbed_official 429:cc5da43e7bf6 665 RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
mbed_official 429:cc5da43e7bf6 666 RCC_OscInitStruct.HSICalibrationValue = 16;
mbed_official 429:cc5da43e7bf6 667 RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
mbed_official 429:cc5da43e7bf6 668 RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
mbed_official 429:cc5da43e7bf6 669 RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
mbed_official 429:cc5da43e7bf6 670 RCC_OscInitStruct.PLL.PLLN = 192; // VCO output clock = 192 MHz (1 MHz * 192)
mbed_official 429:cc5da43e7bf6 671 RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV2; // PLLCLK = 96 MHz (192 MHz / 2)
mbed_official 429:cc5da43e7bf6 672 RCC_OscInitStruct.PLL.PLLQ = 4; // USB clock = 48 MHz (192 MHz / 4) --> Not stable for USB
mbed_official 429:cc5da43e7bf6 673 if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK)
mbed_official 429:cc5da43e7bf6 674 {
mbed_official 429:cc5da43e7bf6 675 return 0; // FAIL
mbed_official 429:cc5da43e7bf6 676 }
mbed_official 429:cc5da43e7bf6 677
mbed_official 429:cc5da43e7bf6 678 /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
mbed_official 429:cc5da43e7bf6 679 RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
mbed_official 429:cc5da43e7bf6 680 RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 96 MHz
mbed_official 429:cc5da43e7bf6 681 RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 96 MHz
mbed_official 429:cc5da43e7bf6 682 RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 48 MHz
mbed_official 429:cc5da43e7bf6 683 RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 96 MHz
mbed_official 429:cc5da43e7bf6 684 if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_3) != HAL_OK)
mbed_official 429:cc5da43e7bf6 685 {
mbed_official 429:cc5da43e7bf6 686 return 0; // FAIL
mbed_official 429:cc5da43e7bf6 687 }
mbed_official 429:cc5da43e7bf6 688
mbed_official 429:cc5da43e7bf6 689 /* Output clock on MCO1 pin(PA8) for debugging purpose */
mbed_official 429:cc5da43e7bf6 690 //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
mbed_official 429:cc5da43e7bf6 691
mbed_official 429:cc5da43e7bf6 692 return 1; // OK
mbed_official 429:cc5da43e7bf6 693 }
mbed_official 429:cc5da43e7bf6 694
mbed_official 429:cc5da43e7bf6 695 /**
mbed_official 429:cc5da43e7bf6 696 * @}
mbed_official 429:cc5da43e7bf6 697 */
mbed_official 429:cc5da43e7bf6 698
mbed_official 429:cc5da43e7bf6 699 /**
mbed_official 429:cc5da43e7bf6 700 * @}
mbed_official 429:cc5da43e7bf6 701 */
mbed_official 429:cc5da43e7bf6 702
mbed_official 429:cc5da43e7bf6 703 /**
mbed_official 429:cc5da43e7bf6 704 * @}
mbed_official 429:cc5da43e7bf6 705 */
mbed_official 429:cc5da43e7bf6 706 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/