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targets/hal/TARGET_RENESAS/TARGET_RZ_A1H/serial_api.c@445:9a3ffe6cfa19, 2015-01-14 (annotated)

Committer:
moirans2
Date:
Wed Jan 14 20:53:08 2015 +0000
Revision:
445:9a3ffe6cfa19
Parent:
441:d2c15dda23c1 
internal clock stm32L051

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 390:35c2c1cf29cd 1 /* mbed Microcontroller Library
mbed_official 390:35c2c1cf29cd 2 * Copyright (c) 2006-2013 ARM Limited
mbed_official 390:35c2c1cf29cd 3 *
mbed_official 390:35c2c1cf29cd 4 * Licensed under the Apache License, Version 2.0 (the "License");
mbed_official 390:35c2c1cf29cd 5 * you may not use this file except in compliance with the License.
mbed_official 390:35c2c1cf29cd 6 * You may obtain a copy of the License at
mbed_official 390:35c2c1cf29cd 7 *
mbed_official 390:35c2c1cf29cd 8 * http://www.apache.org/licenses/LICENSE-2.0
mbed_official 390:35c2c1cf29cd 9 *
mbed_official 390:35c2c1cf29cd 10 * Unless required by applicable law or agreed to in writing, software
mbed_official 390:35c2c1cf29cd 11 * distributed under the License is distributed on an "AS IS" BASIS,
mbed_official 390:35c2c1cf29cd 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mbed_official 390:35c2c1cf29cd 13 * See the License for the specific language governing permissions and
mbed_official 390:35c2c1cf29cd 14 * limitations under the License.
mbed_official 390:35c2c1cf29cd 15 */
mbed_official 390:35c2c1cf29cd 16 // math.h required for floating point operations for baud rate calculation
mbed_official 390:35c2c1cf29cd 17 #include "mbed_assert.h"
mbed_official 390:35c2c1cf29cd 18 #include <math.h>
mbed_official 390:35c2c1cf29cd 19 #include <string.h>
mbed_official 390:35c2c1cf29cd 20 #include <stdlib.h>
mbed_official 390:35c2c1cf29cd 21
mbed_official 390:35c2c1cf29cd 22 #include "serial_api.h"
mbed_official 390:35c2c1cf29cd 23 #include "cmsis.h"
mbed_official 390:35c2c1cf29cd 24 #include "pinmap.h"
mbed_official 390:35c2c1cf29cd 25 #include "gpio_api.h"
mbed_official 390:35c2c1cf29cd 26
mbed_official 390:35c2c1cf29cd 27 #include "scif_iodefine.h"
mbed_official 390:35c2c1cf29cd 28 #include "cpg_iodefine.h"
mbed_official 390:35c2c1cf29cd 29
mbed_official 390:35c2c1cf29cd 30 /******************************************************************************
mbed_official 390:35c2c1cf29cd 31 * INITIALIZATION
mbed_official 390:35c2c1cf29cd 32 ******************************************************************************/
mbed_official 437:0b72c0f86db6 33 #define UART_NUM 8
mbed_official 437:0b72c0f86db6 34 #define IRQ_NUM 2
mbed_official 437:0b72c0f86db6 35
mbed_official 437:0b72c0f86db6 36 static void uart0_tx_irq(void);
mbed_official 437:0b72c0f86db6 37 static void uart1_tx_irq(void);
mbed_official 437:0b72c0f86db6 38 static void uart2_tx_irq(void);
mbed_official 437:0b72c0f86db6 39 static void uart3_tx_irq(void);
mbed_official 437:0b72c0f86db6 40 static void uart4_tx_irq(void);
mbed_official 437:0b72c0f86db6 41 static void uart5_tx_irq(void);
mbed_official 437:0b72c0f86db6 42 static void uart6_tx_irq(void);
mbed_official 437:0b72c0f86db6 43 static void uart7_tx_irq(void);
mbed_official 437:0b72c0f86db6 44 static void uart0_rx_irq(void);
mbed_official 437:0b72c0f86db6 45 static void uart1_rx_irq(void);
mbed_official 437:0b72c0f86db6 46 static void uart2_rx_irq(void);
mbed_official 437:0b72c0f86db6 47 static void uart3_rx_irq(void);
mbed_official 437:0b72c0f86db6 48 static void uart4_rx_irq(void);
mbed_official 437:0b72c0f86db6 49 static void uart5_rx_irq(void);
mbed_official 437:0b72c0f86db6 50 static void uart6_rx_irq(void);
mbed_official 437:0b72c0f86db6 51 static void uart7_rx_irq(void);
mbed_official 437:0b72c0f86db6 52
mbed_official 390:35c2c1cf29cd 53
mbed_official 390:35c2c1cf29cd 54 static const PinMap PinMap_UART_TX[] = {
mbed_official 441:d2c15dda23c1 55 {P6_3 , UART2, 7},
mbed_official 441:d2c15dda23c1 56 {P2_14 , UART0, 6},
mbed_official 441:d2c15dda23c1 57 {P5_0 , UART4, 5},
mbed_official 441:d2c15dda23c1 58 {P5_3 , UART3, 5},
mbed_official 441:d2c15dda23c1 59 {P5_6 , UART6, 5},
mbed_official 441:d2c15dda23c1 60 {P2_5 , UART1, 6},
mbed_official 441:d2c15dda23c1 61 {P8_14 , UART4, 7},
mbed_official 441:d2c15dda23c1 62 {P8_13 , UART5, 5},
mbed_official 441:d2c15dda23c1 63 {P7_4 , UART7, 4},
mbed_official 441:d2c15dda23c1 64 {P11_10, UART5, 3},
mbed_official 441:d2c15dda23c1 65 {P6_6 , UART5, 5},
mbed_official 441:d2c15dda23c1 66 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 67 };
mbed_official 390:35c2c1cf29cd 68
mbed_official 390:35c2c1cf29cd 69 static const PinMap PinMap_UART_RX[] = {
mbed_official 441:d2c15dda23c1 70 {P6_2 , UART2, 7},
mbed_official 441:d2c15dda23c1 71 {P2_15 , UART0, 6},
mbed_official 441:d2c15dda23c1 72 {P5_1 , UART4, 5},
mbed_official 441:d2c15dda23c1 73 {P5_4 , UART3, 5},
mbed_official 441:d2c15dda23c1 74 {P5_7 , UART6, 5},
mbed_official 441:d2c15dda23c1 75 {P2_6 , UART1, 6},
mbed_official 441:d2c15dda23c1 76 {P8_15 , UART4, 7},
mbed_official 441:d2c15dda23c1 77 {P8_11 , UART5, 5},
mbed_official 441:d2c15dda23c1 78 {P7_5 , UART7, 4},
mbed_official 441:d2c15dda23c1 79 {P11_11, UART5, 3},
mbed_official 441:d2c15dda23c1 80 {P6_7 , UART5, 5},
mbed_official 441:d2c15dda23c1 81 {NC , NC , 0}
mbed_official 390:35c2c1cf29cd 82 };
mbed_official 390:35c2c1cf29cd 83
mbed_official 441:d2c15dda23c1 84 static const struct st_scif *SCIF[] = SCIF_ADDRESS_LIST;
mbed_official 390:35c2c1cf29cd 85 static uart_irq_handler irq_handler;
mbed_official 390:35c2c1cf29cd 86
mbed_official 390:35c2c1cf29cd 87 int stdio_uart_inited = 0;
mbed_official 390:35c2c1cf29cd 88 serial_t stdio_uart;
mbed_official 390:35c2c1cf29cd 89
mbed_official 390:35c2c1cf29cd 90 struct serial_global_data_s {
mbed_official 390:35c2c1cf29cd 91 uint32_t serial_irq_id;
mbed_official 390:35c2c1cf29cd 92 gpio_t sw_rts, sw_cts;
mbed_official 390:35c2c1cf29cd 93 uint8_t count, rx_irq_set_flow, rx_irq_set_api;
mbed_official 390:35c2c1cf29cd 94 };
mbed_official 390:35c2c1cf29cd 95
mbed_official 390:35c2c1cf29cd 96 static struct serial_global_data_s uart_data[UART_NUM];
mbed_official 390:35c2c1cf29cd 97
mbed_official 437:0b72c0f86db6 98 static const IRQn_Type irq_set_tbl[UART_NUM][IRQ_NUM] = {
mbed_official 437:0b72c0f86db6 99 {SCIFRXI0_IRQn, SCIFTXI0_IRQn},
mbed_official 437:0b72c0f86db6 100 {SCIFRXI1_IRQn, SCIFTXI1_IRQn},
mbed_official 437:0b72c0f86db6 101 {SCIFRXI2_IRQn, SCIFTXI2_IRQn},
mbed_official 437:0b72c0f86db6 102 {SCIFRXI3_IRQn, SCIFTXI3_IRQn},
mbed_official 437:0b72c0f86db6 103 {SCIFRXI4_IRQn, SCIFTXI4_IRQn},
mbed_official 437:0b72c0f86db6 104 {SCIFRXI5_IRQn, SCIFTXI5_IRQn},
mbed_official 437:0b72c0f86db6 105 {SCIFRXI6_IRQn, SCIFTXI6_IRQn},
mbed_official 437:0b72c0f86db6 106 {SCIFRXI7_IRQn, SCIFTXI7_IRQn}
mbed_official 437:0b72c0f86db6 107 };
mbed_official 437:0b72c0f86db6 108
mbed_official 437:0b72c0f86db6 109 static const IRQHandler hander_set_tbl[UART_NUM][IRQ_NUM] = {
mbed_official 437:0b72c0f86db6 110 {uart0_rx_irq, uart0_tx_irq},
mbed_official 437:0b72c0f86db6 111 {uart1_rx_irq, uart1_tx_irq},
mbed_official 437:0b72c0f86db6 112 {uart2_rx_irq, uart2_tx_irq},
mbed_official 437:0b72c0f86db6 113 {uart3_rx_irq, uart3_tx_irq},
mbed_official 437:0b72c0f86db6 114 {uart4_rx_irq, uart4_tx_irq},
mbed_official 437:0b72c0f86db6 115 {uart5_rx_irq, uart5_tx_irq},
mbed_official 437:0b72c0f86db6 116 {uart6_rx_irq, uart6_tx_irq},
mbed_official 437:0b72c0f86db6 117 {uart7_rx_irq, uart7_tx_irq}
mbed_official 437:0b72c0f86db6 118 };
mbed_official 437:0b72c0f86db6 119
mbed_official 437:0b72c0f86db6 120 static __IO uint16_t *SCSCR_MATCH[] = {
mbed_official 437:0b72c0f86db6 121 &SCSCR_0,
mbed_official 437:0b72c0f86db6 122 &SCSCR_1,
mbed_official 437:0b72c0f86db6 123 &SCSCR_2,
mbed_official 437:0b72c0f86db6 124 &SCSCR_3,
mbed_official 437:0b72c0f86db6 125 &SCSCR_4,
mbed_official 437:0b72c0f86db6 126 &SCSCR_5,
mbed_official 437:0b72c0f86db6 127 &SCSCR_6,
mbed_official 437:0b72c0f86db6 128 &SCSCR_7,
mbed_official 437:0b72c0f86db6 129 };
mbed_official 437:0b72c0f86db6 130
mbed_official 437:0b72c0f86db6 131 static __IO uint16_t *SCFSR_MATCH[] = {
mbed_official 437:0b72c0f86db6 132 &SCFSR_0,
mbed_official 437:0b72c0f86db6 133 &SCFSR_1,
mbed_official 437:0b72c0f86db6 134 &SCFSR_2,
mbed_official 437:0b72c0f86db6 135 &SCFSR_3,
mbed_official 437:0b72c0f86db6 136 &SCFSR_4,
mbed_official 437:0b72c0f86db6 137 &SCFSR_5,
mbed_official 437:0b72c0f86db6 138 &SCFSR_6,
mbed_official 437:0b72c0f86db6 139 &SCFSR_7,
mbed_official 437:0b72c0f86db6 140 };
mbed_official 437:0b72c0f86db6 141
mbed_official 437:0b72c0f86db6 142
mbed_official 390:35c2c1cf29cd 143 void serial_init(serial_t *obj, PinName tx, PinName rx) {
mbed_official 441:d2c15dda23c1 144 volatile uint8_t dummy ;
mbed_official 390:35c2c1cf29cd 145 int is_stdio_uart = 0;
mbed_official 390:35c2c1cf29cd 146 // determine the UART to use
mbed_official 390:35c2c1cf29cd 147 uint32_t uart_tx = pinmap_peripheral(tx, PinMap_UART_TX);
mbed_official 390:35c2c1cf29cd 148 uint32_t uart_rx = pinmap_peripheral(rx, PinMap_UART_RX);
mbed_official 390:35c2c1cf29cd 149 uint32_t uart = pinmap_merge(uart_tx, uart_rx);
mbed_official 441:d2c15dda23c1 150
mbed_official 390:35c2c1cf29cd 151 MBED_ASSERT((int)uart != NC);
mbed_official 390:35c2c1cf29cd 152
mbed_official 441:d2c15dda23c1 153 obj->uart = (struct st_scif *)SCIF[uart];
mbed_official 390:35c2c1cf29cd 154 // enable power
mbed_official 390:35c2c1cf29cd 155 switch (uart) {
mbed_official 441:d2c15dda23c1 156 case UART0: CPG.STBCR4 &= ~(1 << 7); break;
mbed_official 441:d2c15dda23c1 157 case UART1: CPG.STBCR4 &= ~(1 << 6); break;
mbed_official 441:d2c15dda23c1 158 case UART2: CPG.STBCR4 &= ~(1 << 5); break;
mbed_official 441:d2c15dda23c1 159 case UART3: CPG.STBCR4 &= ~(1 << 4); break;
mbed_official 441:d2c15dda23c1 160 case UART4: CPG.STBCR4 &= ~(1 << 3); break;
mbed_official 441:d2c15dda23c1 161 case UART5: CPG.STBCR4 &= ~(1 << 2); break;
mbed_official 441:d2c15dda23c1 162 case UART6: CPG.STBCR4 &= ~(1 << 1); break;
mbed_official 441:d2c15dda23c1 163 case UART7: CPG.STBCR4 &= ~(1 << 0); break;
mbed_official 390:35c2c1cf29cd 164 }
mbed_official 390:35c2c1cf29cd 165 dummy = CPG.STBCR4;
mbed_official 390:35c2c1cf29cd 166
mbed_official 390:35c2c1cf29cd 167 /* ==== SCIF initial setting ==== */
mbed_official 390:35c2c1cf29cd 168 /* ---- Serial control register (SCSCR) setting ---- */
mbed_official 390:35c2c1cf29cd 169 /* B'00 : Internal CLK */
mbed_official 390:35c2c1cf29cd 170 obj->uart->SCSCR = 0x0000u; /* SCIF transmitting and receiving operations stop */
mbed_official 390:35c2c1cf29cd 171
mbed_official 390:35c2c1cf29cd 172 /* ---- FIFO control register (SCFCR) setting ---- */
mbed_official 390:35c2c1cf29cd 173 /* Transmit FIFO reset & Receive FIFO data register reset */
mbed_official 390:35c2c1cf29cd 174 obj->uart->SCFCR = 0x0006;
mbed_official 390:35c2c1cf29cd 175
mbed_official 390:35c2c1cf29cd 176 /* ---- Serial status register (SCFSR) setting ---- */
mbed_official 437:0b72c0f86db6 177 dummy = obj->uart->SCFSR;
mbed_official 437:0b72c0f86db6 178 obj->uart->SCFSR = (dummy & 0xFF6Cu); /* ER,BRK,DR bit clear */
mbed_official 390:35c2c1cf29cd 179
mbed_official 390:35c2c1cf29cd 180 /* ---- Line status register (SCLSR) setting ---- */
mbed_official 390:35c2c1cf29cd 181 /* ORER bit clear */
mbed_official 390:35c2c1cf29cd 182 obj->uart->SCLSR = 0;
mbed_official 390:35c2c1cf29cd 183
mbed_official 390:35c2c1cf29cd 184 /* ---- Serial extension mode register (SCEMR) setting ----
mbed_official 390:35c2c1cf29cd 185 b7 BGDM - Baud rate generator double-speed mode : Normal mode
mbed_official 390:35c2c1cf29cd 186 b0 ABCS - Base clock select in asynchronous mode : Base clock is 16 times the bit rate */
mbed_official 390:35c2c1cf29cd 187 obj->uart->SCEMR = 0x0000u;
mbed_official 390:35c2c1cf29cd 188
mbed_official 390:35c2c1cf29cd 189 /* ---- Bit rate register (SCBRR) setting ---- */
mbed_official 390:35c2c1cf29cd 190 serial_baud (obj, 9600);
mbed_official 390:35c2c1cf29cd 191 serial_format(obj, 8, ParityNone, 1);
mbed_official 390:35c2c1cf29cd 192
mbed_official 390:35c2c1cf29cd 193 /* ---- FIFO control register (SCFCR) setting ---- */
mbed_official 390:35c2c1cf29cd 194 obj->uart->SCFCR = 0x0030u;
mbed_official 441:d2c15dda23c1 195
mbed_official 390:35c2c1cf29cd 196 /* ---- Serial port register (SCSPTR) setting ----
mbed_official 390:35c2c1cf29cd 197 b1 SPB2IO - Serial port break output : disabled
mbed_official 390:35c2c1cf29cd 198 b0 SPB2DT - Serial port break data : High-level */
mbed_official 390:35c2c1cf29cd 199 //obj->uart->SCSPTR |= 0x0000u;
mbed_official 390:35c2c1cf29cd 200
mbed_official 409:a95c696104d3 201 obj->uart->SCSCR = 0x00F0;
mbed_official 390:35c2c1cf29cd 202
mbed_official 390:35c2c1cf29cd 203 // pinout the chosen uart
mbed_official 390:35c2c1cf29cd 204 pinmap_pinout(tx, PinMap_UART_TX);
mbed_official 390:35c2c1cf29cd 205 pinmap_pinout(rx, PinMap_UART_RX);
mbed_official 390:35c2c1cf29cd 206
mbed_official 390:35c2c1cf29cd 207 switch (uart) {
mbed_official 441:d2c15dda23c1 208 case UART0: obj->index = 0; break;
mbed_official 441:d2c15dda23c1 209 case UART1: obj->index = 1; break;
mbed_official 441:d2c15dda23c1 210 case UART2: obj->index = 2; break;
mbed_official 441:d2c15dda23c1 211 case UART3: obj->index = 3; break;
mbed_official 441:d2c15dda23c1 212 case UART4: obj->index = 4; break;
mbed_official 441:d2c15dda23c1 213 case UART5: obj->index = 5; break;
mbed_official 441:d2c15dda23c1 214 case UART6: obj->index = 6; break;
mbed_official 441:d2c15dda23c1 215 case UART7: obj->index = 7; break;
mbed_official 390:35c2c1cf29cd 216 }
mbed_official 390:35c2c1cf29cd 217 uart_data[obj->index].sw_rts.pin = NC;
mbed_official 390:35c2c1cf29cd 218 uart_data[obj->index].sw_cts.pin = NC;
mbed_official 390:35c2c1cf29cd 219
mbed_official 390:35c2c1cf29cd 220 is_stdio_uart = (uart == STDIO_UART) ? (1) : (0);
mbed_official 390:35c2c1cf29cd 221
mbed_official 390:35c2c1cf29cd 222 if (is_stdio_uart) {
mbed_official 390:35c2c1cf29cd 223 stdio_uart_inited = 1;
mbed_official 390:35c2c1cf29cd 224 memcpy(&stdio_uart, obj, sizeof(serial_t));
mbed_official 390:35c2c1cf29cd 225 }
mbed_official 390:35c2c1cf29cd 226 }
mbed_official 390:35c2c1cf29cd 227
mbed_official 390:35c2c1cf29cd 228 void serial_free(serial_t *obj) {
mbed_official 390:35c2c1cf29cd 229 uart_data[obj->index].serial_irq_id = 0;
mbed_official 390:35c2c1cf29cd 230 }
mbed_official 390:35c2c1cf29cd 231
mbed_official 390:35c2c1cf29cd 232 // serial_baud
mbed_official 390:35c2c1cf29cd 233 // set the baud rate, taking in to account the current SystemFrequency
mbed_official 390:35c2c1cf29cd 234 void serial_baud(serial_t *obj, int baudrate) {
mbed_official 390:35c2c1cf29cd 235
mbed_official 390:35c2c1cf29cd 236 uint32_t PCLK = 66666666;
mbed_official 390:35c2c1cf29cd 237
mbed_official 390:35c2c1cf29cd 238 uint16_t DL = (PCLK / (32 * baudrate)) -1;
mbed_official 390:35c2c1cf29cd 239
mbed_official 390:35c2c1cf29cd 240 // set LCR[DLAB] to enable writing to divider registers
mbed_official 390:35c2c1cf29cd 241 obj->uart->SCBRR = DL;
mbed_official 390:35c2c1cf29cd 242 }
mbed_official 390:35c2c1cf29cd 243
mbed_official 390:35c2c1cf29cd 244 void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits) {
mbed_official 441:d2c15dda23c1 245 int parity_enable;
mbed_official 441:d2c15dda23c1 246 int parity_select;
mbed_official 441:d2c15dda23c1 247
mbed_official 390:35c2c1cf29cd 248 MBED_ASSERT((stop_bits == 1) || (stop_bits == 2)); // 0: 1 stop bits, 1: 2 stop bits
mbed_official 390:35c2c1cf29cd 249 MBED_ASSERT((data_bits > 6) && (data_bits < 9)); // 0: 5 data bits ... 3: 8 data bits
mbed_official 390:35c2c1cf29cd 250 MBED_ASSERT((parity == ParityNone) || (parity == ParityOdd) || (parity == ParityEven) ||
mbed_official 390:35c2c1cf29cd 251 (parity == ParityForced1) || (parity == ParityForced0));
mbed_official 390:35c2c1cf29cd 252
mbed_official 390:35c2c1cf29cd 253 stop_bits = (stop_bits == 1)? 0:
mbed_official 390:35c2c1cf29cd 254 (stop_bits == 2)? 1:
mbed_official 390:35c2c1cf29cd 255 0; // must not to be
mbed_official 390:35c2c1cf29cd 256
mbed_official 390:35c2c1cf29cd 257 data_bits = (data_bits == 8)? 0:
mbed_official 390:35c2c1cf29cd 258 (data_bits == 7)? 1:
mbed_official 390:35c2c1cf29cd 259 0; // must not to be
mbed_official 390:35c2c1cf29cd 260
mbed_official 390:35c2c1cf29cd 261 switch (parity) {
mbed_official 441:d2c15dda23c1 262 case ParityNone:
mbed_official 441:d2c15dda23c1 263 parity_enable = 0;
mbed_official 441:d2c15dda23c1 264 parity_select = 0;
mbed_official 441:d2c15dda23c1 265 break;
mbed_official 441:d2c15dda23c1 266 case ParityOdd:
mbed_official 441:d2c15dda23c1 267 parity_enable = 1;
mbed_official 441:d2c15dda23c1 268 parity_select = 0;
mbed_official 441:d2c15dda23c1 269 break;
mbed_official 441:d2c15dda23c1 270 case ParityEven:
mbed_official 441:d2c15dda23c1 271 parity_enable = 1;
mbed_official 441:d2c15dda23c1 272 parity_select = 1;
mbed_official 441:d2c15dda23c1 273 break;
mbed_official 390:35c2c1cf29cd 274 default:
mbed_official 441:d2c15dda23c1 275 parity_enable = 0;
mbed_official 441:d2c15dda23c1 276 parity_select = 0;
mbed_official 390:35c2c1cf29cd 277 break;
mbed_official 390:35c2c1cf29cd 278 }
mbed_official 390:35c2c1cf29cd 279
mbed_official 390:35c2c1cf29cd 280 obj->uart->SCSMR = data_bits << 6
mbed_official 390:35c2c1cf29cd 281 | parity_enable << 5
mbed_official 390:35c2c1cf29cd 282 | parity_select << 4
mbed_official 390:35c2c1cf29cd 283 | stop_bits << 3;
mbed_official 390:35c2c1cf29cd 284 }
mbed_official 390:35c2c1cf29cd 285
mbed_official 390:35c2c1cf29cd 286 /******************************************************************************
mbed_official 390:35c2c1cf29cd 287 * INTERRUPTS HANDLING
mbed_official 390:35c2c1cf29cd 288 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 289
mbed_official 409:a95c696104d3 290 static void uart_tx_irq(IRQn_Type irq_num, uint32_t index) {
mbed_official 437:0b72c0f86db6 291 __IO uint16_t *dmy_rd_scscr;
mbed_official 437:0b72c0f86db6 292 __IO uint16_t *dmy_rd_scfsr;
mbed_official 441:d2c15dda23c1 293
mbed_official 437:0b72c0f86db6 294 dmy_rd_scscr = SCSCR_MATCH[index];
mbed_official 437:0b72c0f86db6 295 *dmy_rd_scscr &= 0x007B; // Clear TIE and Write to bit15~8,2 is always 0
mbed_official 437:0b72c0f86db6 296 dmy_rd_scfsr = SCFSR_MATCH[index];
mbed_official 437:0b72c0f86db6 297 *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0020); // Clear TDFE
mbed_official 441:d2c15dda23c1 298
mbed_official 409:a95c696104d3 299 irq_handler(uart_data[index].serial_irq_id, TxIrq);
mbed_official 409:a95c696104d3 300 }
mbed_official 409:a95c696104d3 301
mbed_official 409:a95c696104d3 302 static void uart_rx_irq(IRQn_Type irq_num, uint32_t index) {
mbed_official 437:0b72c0f86db6 303 __IO uint16_t *dmy_rd_scscr;
mbed_official 437:0b72c0f86db6 304 __IO uint16_t *dmy_rd_scfsr;
mbed_official 441:d2c15dda23c1 305
mbed_official 437:0b72c0f86db6 306 dmy_rd_scscr = SCSCR_MATCH[index];
mbed_official 437:0b72c0f86db6 307 *dmy_rd_scscr &= 0x00B3; // Clear RIE,REIE and Write to bit15~8,2 is always 0
mbed_official 437:0b72c0f86db6 308 dmy_rd_scfsr = SCFSR_MATCH[index];
mbed_official 437:0b72c0f86db6 309 *dmy_rd_scfsr = (*dmy_rd_scfsr & ~0x0003); // Clear RDF,DR
mbed_official 437:0b72c0f86db6 310
mbed_official 409:a95c696104d3 311 irq_handler(uart_data[index].serial_irq_id, RxIrq);
mbed_official 409:a95c696104d3 312 }
mbed_official 437:0b72c0f86db6 313
mbed_official 409:a95c696104d3 314 /* TX handler */
mbed_official 437:0b72c0f86db6 315 static void uart0_tx_irq(void) {uart_tx_irq(SCIFTXI0_IRQn, 0);}
mbed_official 437:0b72c0f86db6 316 static void uart1_tx_irq(void) {uart_tx_irq(SCIFTXI1_IRQn, 1);}
mbed_official 437:0b72c0f86db6 317 static void uart2_tx_irq(void) {uart_tx_irq(SCIFTXI2_IRQn, 2);}
mbed_official 437:0b72c0f86db6 318 static void uart3_tx_irq(void) {uart_tx_irq(SCIFTXI3_IRQn, 3);}
mbed_official 437:0b72c0f86db6 319 static void uart4_tx_irq(void) {uart_tx_irq(SCIFTXI4_IRQn, 4);}
mbed_official 437:0b72c0f86db6 320 static void uart5_tx_irq(void) {uart_tx_irq(SCIFTXI5_IRQn, 5);}
mbed_official 437:0b72c0f86db6 321 static void uart6_tx_irq(void) {uart_tx_irq(SCIFTXI6_IRQn, 6);}
mbed_official 437:0b72c0f86db6 322 static void uart7_tx_irq(void) {uart_tx_irq(SCIFTXI7_IRQn, 7);}
mbed_official 409:a95c696104d3 323 /* RX handler */
mbed_official 437:0b72c0f86db6 324 static void uart0_rx_irq(void) {uart_rx_irq(SCIFRXI0_IRQn, 0);}
mbed_official 437:0b72c0f86db6 325 static void uart1_rx_irq(void) {uart_rx_irq(SCIFRXI1_IRQn, 1);}
mbed_official 437:0b72c0f86db6 326 static void uart2_rx_irq(void) {uart_rx_irq(SCIFRXI2_IRQn, 2);}
mbed_official 437:0b72c0f86db6 327 static void uart3_rx_irq(void) {uart_rx_irq(SCIFRXI3_IRQn, 3);}
mbed_official 437:0b72c0f86db6 328 static void uart4_rx_irq(void) {uart_rx_irq(SCIFRXI4_IRQn, 4);}
mbed_official 437:0b72c0f86db6 329 static void uart5_rx_irq(void) {uart_rx_irq(SCIFRXI5_IRQn, 5);}
mbed_official 437:0b72c0f86db6 330 static void uart6_rx_irq(void) {uart_rx_irq(SCIFRXI6_IRQn, 6);}
mbed_official 437:0b72c0f86db6 331 static void uart7_rx_irq(void) {uart_rx_irq(SCIFRXI7_IRQn, 7);}
mbed_official 390:35c2c1cf29cd 332
mbed_official 390:35c2c1cf29cd 333 void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id) {
mbed_official 390:35c2c1cf29cd 334 irq_handler = handler;
mbed_official 390:35c2c1cf29cd 335 uart_data[obj->index].serial_irq_id = id;
mbed_official 390:35c2c1cf29cd 336 }
mbed_official 390:35c2c1cf29cd 337
mbed_official 390:35c2c1cf29cd 338 static void serial_irq_set_internal(serial_t *obj, SerialIrq irq, uint32_t enable) {
mbed_official 437:0b72c0f86db6 339 IRQn_Type IRQn;
mbed_official 437:0b72c0f86db6 340 IRQHandler handler;
mbed_official 437:0b72c0f86db6 341
mbed_official 437:0b72c0f86db6 342 IRQn = irq_set_tbl[obj->index][irq];
mbed_official 437:0b72c0f86db6 343 handler = hander_set_tbl[obj->index][irq];
mbed_official 437:0b72c0f86db6 344
mbed_official 437:0b72c0f86db6 345 if ((obj->index >= 0) && (obj->index <= 7)) {
mbed_official 437:0b72c0f86db6 346 if (enable) {
mbed_official 437:0b72c0f86db6 347 InterruptHandlerRegister(IRQn, (void (*)(uint32_t))handler);
mbed_official 437:0b72c0f86db6 348 GIC_SetPriority(IRQn, 5);
mbed_official 437:0b72c0f86db6 349 GIC_EnableIRQ(IRQn);
mbed_official 437:0b72c0f86db6 350 } else {
mbed_official 437:0b72c0f86db6 351 GIC_DisableIRQ(IRQn);
mbed_official 437:0b72c0f86db6 352 }
mbed_official 390:35c2c1cf29cd 353 }
mbed_official 390:35c2c1cf29cd 354 }
mbed_official 390:35c2c1cf29cd 355
mbed_official 390:35c2c1cf29cd 356 void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable) {
mbed_official 441:d2c15dda23c1 357 if (RxIrq == irq) {
mbed_official 390:35c2c1cf29cd 358 uart_data[obj->index].rx_irq_set_api = enable;
mbed_official 441:d2c15dda23c1 359 }
mbed_official 390:35c2c1cf29cd 360 serial_irq_set_internal(obj, irq, enable);
mbed_official 390:35c2c1cf29cd 361 }
mbed_official 390:35c2c1cf29cd 362
mbed_official 390:35c2c1cf29cd 363 static void serial_flow_irq_set(serial_t *obj, uint32_t enable) {
mbed_official 390:35c2c1cf29cd 364 uart_data[obj->index].rx_irq_set_flow = enable;
mbed_official 390:35c2c1cf29cd 365 serial_irq_set_internal(obj, RxIrq, enable);
mbed_official 390:35c2c1cf29cd 366 }
mbed_official 390:35c2c1cf29cd 367
mbed_official 390:35c2c1cf29cd 368 /******************************************************************************
mbed_official 390:35c2c1cf29cd 369 * READ/WRITE
mbed_official 390:35c2c1cf29cd 370 ******************************************************************************/
mbed_official 390:35c2c1cf29cd 371 int serial_getc(serial_t *obj) {
mbed_official 437:0b72c0f86db6 372 uint16_t dummy_read;
mbed_official 441:d2c15dda23c1 373 int data;
mbed_official 441:d2c15dda23c1 374
mbed_official 437:0b72c0f86db6 375 if (obj->uart->SCFSR & 0x93) {
mbed_official 437:0b72c0f86db6 376 dummy_read = obj->uart->SCFSR;
mbed_official 437:0b72c0f86db6 377 obj->uart->SCFSR = (dummy_read & ~0x93);
mbed_official 437:0b72c0f86db6 378 }
mbed_official 437:0b72c0f86db6 379 obj->uart->SCSCR |= 0x0040; // Set RIE
mbed_official 390:35c2c1cf29cd 380 while (!serial_readable(obj));
mbed_official 441:d2c15dda23c1 381 data = obj->uart->SCFRDR & 0xff;
mbed_official 441:d2c15dda23c1 382 obj->uart->SCFSR &= 0xfffc; // Clear DR,RDF
mbed_official 390:35c2c1cf29cd 383 return data;
mbed_official 390:35c2c1cf29cd 384 }
mbed_official 390:35c2c1cf29cd 385
mbed_official 390:35c2c1cf29cd 386 void serial_putc(serial_t *obj, int c) {
mbed_official 437:0b72c0f86db6 387 uint16_t dummy_read;
mbed_official 437:0b72c0f86db6 388
mbed_official 437:0b72c0f86db6 389 obj->uart->SCSCR |= 0x0080; // Set TIE
mbed_official 390:35c2c1cf29cd 390 while (!serial_writable(obj));
mbed_official 390:35c2c1cf29cd 391 obj->uart->SCFTDR = c;
mbed_official 437:0b72c0f86db6 392 dummy_read = obj->uart->SCFSR;
mbed_official 437:0b72c0f86db6 393 obj->uart->SCFSR = (dummy_read & 0xff9f); // Clear TEND/TDFE
mbed_official 390:35c2c1cf29cd 394 uart_data[obj->index].count++;
mbed_official 390:35c2c1cf29cd 395 }
mbed_official 390:35c2c1cf29cd 396
mbed_official 390:35c2c1cf29cd 397 int serial_readable(serial_t *obj) {
mbed_official 390:35c2c1cf29cd 398 return obj->uart->SCFSR & 0x02; // RDF
mbed_official 390:35c2c1cf29cd 399 }
mbed_official 390:35c2c1cf29cd 400
mbed_official 390:35c2c1cf29cd 401 int serial_writable(serial_t *obj) {
mbed_official 390:35c2c1cf29cd 402 return obj->uart->SCFSR & 0x20; // TDFE
mbed_official 390:35c2c1cf29cd 403 }
mbed_official 390:35c2c1cf29cd 404
mbed_official 390:35c2c1cf29cd 405 void serial_clear(serial_t *obj) {
mbed_official 390:35c2c1cf29cd 406 obj->uart->SCFCR = 0x06;
mbed_official 390:35c2c1cf29cd 407 obj->uart->SCFCR = 0x06;
mbed_official 390:35c2c1cf29cd 408 }
mbed_official 390:35c2c1cf29cd 409
mbed_official 390:35c2c1cf29cd 410 void serial_pinout_tx(PinName tx) {
mbed_official 390:35c2c1cf29cd 411 pinmap_pinout(tx, PinMap_UART_TX);
mbed_official 390:35c2c1cf29cd 412 }
mbed_official 390:35c2c1cf29cd 413
mbed_official 390:35c2c1cf29cd 414 void serial_break_set(serial_t *obj) {
mbed_official 390:35c2c1cf29cd 415 }
mbed_official 390:35c2c1cf29cd 416
mbed_official 390:35c2c1cf29cd 417 void serial_break_clear(serial_t *obj) {
mbed_official 390:35c2c1cf29cd 418 }
mbed_official 390:35c2c1cf29cd 419
mbed_official 390:35c2c1cf29cd 420 void serial_set_flow_control(serial_t *obj, FlowControl type, PinName rxflow, PinName txflow) {
mbed_official 390:35c2c1cf29cd 421 serial_flow_irq_set(obj, 0);
mbed_official 390:35c2c1cf29cd 422 }
mbed_official 390:35c2c1cf29cd 423