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targets/cmsis/TARGET_STM/TARGET_STM32F0/stm32f0xx_hal.h@445:9a3ffe6cfa19, 2015-01-14 (annotated)
- Committer:
- moirans2
- Date:
- Wed Jan 14 20:53:08 2015 +0000
- Revision:
- 445:9a3ffe6cfa19
- Parent:
- 441:d2c15dda23c1
internal clock stm32L051
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| mbed_official | 340:28d1f895c6fe | 1 | /** |
| mbed_official | 340:28d1f895c6fe | 2 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 3 | * @file stm32f0xx_hal.h |
| mbed_official | 340:28d1f895c6fe | 4 | * @author MCD Application Team |
| mbed_official | 441:d2c15dda23c1 | 5 | * @version V1.2.0 |
| mbed_official | 441:d2c15dda23c1 | 6 | * @date 11-December-2014 |
| mbed_official | 340:28d1f895c6fe | 7 | * @brief This file contains all the functions prototypes for the HAL |
| mbed_official | 340:28d1f895c6fe | 8 | * module driver. |
| mbed_official | 340:28d1f895c6fe | 9 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 10 | * @attention |
| mbed_official | 340:28d1f895c6fe | 11 | * |
| mbed_official | 340:28d1f895c6fe | 12 | * <h2><center>© COPYRIGHT(c) 2014 STMicroelectronics</center></h2> |
| mbed_official | 340:28d1f895c6fe | 13 | * |
| mbed_official | 340:28d1f895c6fe | 14 | * Redistribution and use in source and binary forms, with or without modification, |
| mbed_official | 340:28d1f895c6fe | 15 | * are permitted provided that the following conditions are met: |
| mbed_official | 340:28d1f895c6fe | 16 | * 1. Redistributions of source code must retain the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 17 | * this list of conditions and the following disclaimer. |
| mbed_official | 340:28d1f895c6fe | 18 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
| mbed_official | 340:28d1f895c6fe | 19 | * this list of conditions and the following disclaimer in the documentation |
| mbed_official | 340:28d1f895c6fe | 20 | * and/or other materials provided with the distribution. |
| mbed_official | 340:28d1f895c6fe | 21 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
| mbed_official | 340:28d1f895c6fe | 22 | * may be used to endorse or promote products derived from this software |
| mbed_official | 340:28d1f895c6fe | 23 | * without specific prior written permission. |
| mbed_official | 340:28d1f895c6fe | 24 | * |
| mbed_official | 340:28d1f895c6fe | 25 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
| mbed_official | 340:28d1f895c6fe | 26 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
| mbed_official | 340:28d1f895c6fe | 27 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
| mbed_official | 340:28d1f895c6fe | 28 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
| mbed_official | 340:28d1f895c6fe | 29 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
| mbed_official | 340:28d1f895c6fe | 30 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
| mbed_official | 340:28d1f895c6fe | 31 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
| mbed_official | 340:28d1f895c6fe | 32 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
| mbed_official | 340:28d1f895c6fe | 33 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
| mbed_official | 340:28d1f895c6fe | 34 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
| mbed_official | 340:28d1f895c6fe | 35 | * |
| mbed_official | 340:28d1f895c6fe | 36 | ****************************************************************************** |
| mbed_official | 340:28d1f895c6fe | 37 | */ |
| mbed_official | 340:28d1f895c6fe | 38 | |
| mbed_official | 340:28d1f895c6fe | 39 | /* Define to prevent recursive inclusion -------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 40 | #ifndef __STM32F0xx_HAL_H |
| mbed_official | 340:28d1f895c6fe | 41 | #define __STM32F0xx_HAL_H |
| mbed_official | 340:28d1f895c6fe | 42 | |
| mbed_official | 340:28d1f895c6fe | 43 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 44 | extern "C" { |
| mbed_official | 340:28d1f895c6fe | 45 | #endif |
| mbed_official | 340:28d1f895c6fe | 46 | |
| mbed_official | 340:28d1f895c6fe | 47 | /* Includes ------------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 48 | #include "stm32f0xx_hal_conf.h" |
| mbed_official | 340:28d1f895c6fe | 49 | |
| mbed_official | 340:28d1f895c6fe | 50 | /** @addtogroup STM32F0xx_HAL_Driver |
| mbed_official | 340:28d1f895c6fe | 51 | * @{ |
| mbed_official | 340:28d1f895c6fe | 52 | */ |
| mbed_official | 340:28d1f895c6fe | 53 | |
| mbed_official | 340:28d1f895c6fe | 54 | /** @addtogroup HAL |
| mbed_official | 340:28d1f895c6fe | 55 | * @{ |
| mbed_official | 340:28d1f895c6fe | 56 | */ |
| mbed_official | 340:28d1f895c6fe | 57 | |
| mbed_official | 340:28d1f895c6fe | 58 | /* Exported types ------------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 59 | /* Exported constants --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 60 | /** @defgroup HAL_Exported_Constants HAL Exported Constants |
| mbed_official | 340:28d1f895c6fe | 61 | * @{ |
| mbed_official | 340:28d1f895c6fe | 62 | */ |
| mbed_official | 340:28d1f895c6fe | 63 | |
| mbed_official | 340:28d1f895c6fe | 64 | #if defined(SYSCFG_CFGR1_DMA_RMP) |
| mbed_official | 340:28d1f895c6fe | 65 | /** @defgroup HAL_DMA_remapping HAL DMA remapping |
| mbed_official | 340:28d1f895c6fe | 66 | * Elements values convention: 0xYYYYYYYY |
| mbed_official | 340:28d1f895c6fe | 67 | * - YYYYYYYY : Position in the SYSCFG register CFGR1 |
| mbed_official | 340:28d1f895c6fe | 68 | * @{ |
| mbed_official | 340:28d1f895c6fe | 69 | */ |
| mbed_official | 340:28d1f895c6fe | 70 | #define HAL_REMAPDMA_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap |
| mbed_official | 340:28d1f895c6fe | 71 | 0: No remap (ADC DMA requests mapped on DMA channel 1 |
| mbed_official | 340:28d1f895c6fe | 72 | 1: Remap (ADC DMA requests mapped on DMA channel 2 */ |
| mbed_official | 340:28d1f895c6fe | 73 | #define HAL_REMAPDMA_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap |
| mbed_official | 340:28d1f895c6fe | 74 | 0: No remap (USART1_TX DMA request mapped on DMA channel 2 |
| mbed_official | 340:28d1f895c6fe | 75 | 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */ |
| mbed_official | 340:28d1f895c6fe | 76 | #define HAL_REMAPDMA_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap |
| mbed_official | 340:28d1f895c6fe | 77 | 0: No remap (USART1_RX DMA request mapped on DMA channel 3 |
| mbed_official | 340:28d1f895c6fe | 78 | 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */ |
| mbed_official | 340:28d1f895c6fe | 79 | #define HAL_REMAPDMA_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap |
| mbed_official | 340:28d1f895c6fe | 80 | 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3) |
| mbed_official | 340:28d1f895c6fe | 81 | 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */ |
| mbed_official | 340:28d1f895c6fe | 82 | #define HAL_REMAPDMA_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap |
| mbed_official | 340:28d1f895c6fe | 83 | 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1 |
| mbed_official | 340:28d1f895c6fe | 84 | 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */ |
| mbed_official | 340:28d1f895c6fe | 85 | |
| mbed_official | 340:28d1f895c6fe | 86 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) |
| mbed_official | 340:28d1f895c6fe | 87 | #define HAL_REMAPDMA_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only |
| mbed_official | 340:28d1f895c6fe | 88 | 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit) |
| mbed_official | 340:28d1f895c6fe | 89 | 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */ |
| mbed_official | 340:28d1f895c6fe | 90 | #define HAL_REMAPDMA_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only |
| mbed_official | 340:28d1f895c6fe | 91 | 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit) |
| mbed_official | 340:28d1f895c6fe | 92 | 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */ |
| mbed_official | 340:28d1f895c6fe | 93 | #define HAL_REMAPDMA_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only. |
| mbed_official | 340:28d1f895c6fe | 94 | 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively) |
| mbed_official | 340:28d1f895c6fe | 95 | 1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ |
| mbed_official | 340:28d1f895c6fe | 96 | #define HAL_REMAPDMA_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only. |
| mbed_official | 340:28d1f895c6fe | 97 | 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively) |
| mbed_official | 340:28d1f895c6fe | 98 | 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */ |
| mbed_official | 340:28d1f895c6fe | 99 | #define HAL_REMAPDMA_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only. |
| mbed_official | 340:28d1f895c6fe | 100 | 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively) |
| mbed_official | 340:28d1f895c6fe | 101 | 1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */ |
| mbed_official | 340:28d1f895c6fe | 102 | #define HAL_REMAPDMA_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only. |
| mbed_official | 340:28d1f895c6fe | 103 | 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively) |
| mbed_official | 340:28d1f895c6fe | 104 | 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */ |
| mbed_official | 340:28d1f895c6fe | 105 | #define HAL_REMAPDMA_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only. |
| mbed_official | 340:28d1f895c6fe | 106 | 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively) |
| mbed_official | 340:28d1f895c6fe | 107 | 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */ |
| mbed_official | 340:28d1f895c6fe | 108 | #define HAL_REMAPDMA_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only. |
| mbed_official | 340:28d1f895c6fe | 109 | 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively) |
| mbed_official | 340:28d1f895c6fe | 110 | 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */ |
| mbed_official | 340:28d1f895c6fe | 111 | #define HAL_REMAPDMA_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only. |
| mbed_official | 340:28d1f895c6fe | 112 | 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4) |
| mbed_official | 340:28d1f895c6fe | 113 | 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */ |
| mbed_official | 340:28d1f895c6fe | 114 | #endif |
| mbed_official | 340:28d1f895c6fe | 115 | |
| mbed_official | 340:28d1f895c6fe | 116 | #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx) |
| mbed_official | 340:28d1f895c6fe | 117 | #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ |
| mbed_official | 340:28d1f895c6fe | 118 | ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ |
| mbed_official | 340:28d1f895c6fe | 119 | ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ |
| mbed_official | 340:28d1f895c6fe | 120 | ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ |
| mbed_official | 340:28d1f895c6fe | 121 | ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2) || \ |
| mbed_official | 340:28d1f895c6fe | 122 | ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6) || \ |
| mbed_official | 340:28d1f895c6fe | 123 | ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7) || \ |
| mbed_official | 340:28d1f895c6fe | 124 | ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67) || \ |
| mbed_official | 340:28d1f895c6fe | 125 | ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67) || \ |
| mbed_official | 340:28d1f895c6fe | 126 | ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32) || \ |
| mbed_official | 340:28d1f895c6fe | 127 | ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76) || \ |
| mbed_official | 340:28d1f895c6fe | 128 | ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6) || \ |
| mbed_official | 340:28d1f895c6fe | 129 | ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7) || \ |
| mbed_official | 340:28d1f895c6fe | 130 | ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6)) |
| mbed_official | 340:28d1f895c6fe | 131 | #else |
| mbed_official | 340:28d1f895c6fe | 132 | #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \ |
| mbed_official | 340:28d1f895c6fe | 133 | ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \ |
| mbed_official | 340:28d1f895c6fe | 134 | ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \ |
| mbed_official | 340:28d1f895c6fe | 135 | ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \ |
| mbed_official | 340:28d1f895c6fe | 136 | ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2)) |
| mbed_official | 340:28d1f895c6fe | 137 | #endif |
| mbed_official | 340:28d1f895c6fe | 138 | /** |
| mbed_official | 340:28d1f895c6fe | 139 | * @} |
| mbed_official | 340:28d1f895c6fe | 140 | */ |
| mbed_official | 340:28d1f895c6fe | 141 | #endif /* SYSCFG_CFGR1_DMA_RMP */ |
| mbed_official | 340:28d1f895c6fe | 142 | |
| mbed_official | 340:28d1f895c6fe | 143 | #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) |
| mbed_official | 340:28d1f895c6fe | 144 | /** @defgroup HAL_Pin_remapping HAL Pin remapping |
| mbed_official | 340:28d1f895c6fe | 145 | * @{ |
| mbed_official | 340:28d1f895c6fe | 146 | */ |
| mbed_official | 340:28d1f895c6fe | 147 | #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins). |
| mbed_official | 340:28d1f895c6fe | 148 | 0: No remap (pin pair PA9/10 mapped on the pins) |
| mbed_official | 340:28d1f895c6fe | 149 | 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */ |
| mbed_official | 340:28d1f895c6fe | 150 | |
| mbed_official | 340:28d1f895c6fe | 151 | #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12) |
| mbed_official | 340:28d1f895c6fe | 152 | /** |
| mbed_official | 340:28d1f895c6fe | 153 | * @} |
| mbed_official | 340:28d1f895c6fe | 154 | */ |
| mbed_official | 340:28d1f895c6fe | 155 | #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ |
| mbed_official | 340:28d1f895c6fe | 156 | |
| mbed_official | 441:d2c15dda23c1 | 157 | #if defined(STM32F091xC) || defined(STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 158 | /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection |
| mbed_official | 441:d2c15dda23c1 | 159 | * @note Applicable on STM32F09x |
| mbed_official | 340:28d1f895c6fe | 160 | * @{ |
| mbed_official | 340:28d1f895c6fe | 161 | */ |
| mbed_official | 340:28d1f895c6fe | 162 | #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */ |
| mbed_official | 340:28d1f895c6fe | 163 | #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */ |
| mbed_official | 340:28d1f895c6fe | 164 | #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */ |
| mbed_official | 340:28d1f895c6fe | 165 | |
| mbed_official | 340:28d1f895c6fe | 166 | #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \ |
| mbed_official | 340:28d1f895c6fe | 167 | ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \ |
| mbed_official | 340:28d1f895c6fe | 168 | ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4)) |
| mbed_official | 340:28d1f895c6fe | 169 | /** |
| mbed_official | 340:28d1f895c6fe | 170 | * @} |
| mbed_official | 340:28d1f895c6fe | 171 | */ |
| mbed_official | 441:d2c15dda23c1 | 172 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 173 | |
| mbed_official | 340:28d1f895c6fe | 174 | |
| mbed_official | 340:28d1f895c6fe | 175 | /** @defgroup HAL_FastModePlus_I2C HAL FastModePlus I2C |
| mbed_official | 340:28d1f895c6fe | 176 | * @{ |
| mbed_official | 340:28d1f895c6fe | 177 | */ |
| mbed_official | 340:28d1f895c6fe | 178 | #if defined(SYSCFG_CFGR1_I2C_FMP_PB6) |
| mbed_official | 340:28d1f895c6fe | 179 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 (SYSCFG_CFGR1_I2C_FMP_PB6) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| mbed_official | 340:28d1f895c6fe | 180 | 0: PB6 pin operates in standard mode |
| mbed_official | 340:28d1f895c6fe | 181 | 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */ |
| mbed_official | 340:28d1f895c6fe | 182 | #endif /* SYSCFG_CFGR1_I2C_FMP_PB6 */ |
| mbed_official | 340:28d1f895c6fe | 183 | |
| mbed_official | 340:28d1f895c6fe | 184 | #if defined(SYSCFG_CFGR1_I2C_FMP_PB7) |
| mbed_official | 340:28d1f895c6fe | 185 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 (SYSCFG_CFGR1_I2C_FMP_PB7) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| mbed_official | 340:28d1f895c6fe | 186 | 0: PB7 pin operates in standard mode |
| mbed_official | 340:28d1f895c6fe | 187 | 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */ |
| mbed_official | 340:28d1f895c6fe | 188 | #endif /* SYSCFG_CFGR1_I2C_FMP_PB7 */ |
| mbed_official | 340:28d1f895c6fe | 189 | |
| mbed_official | 340:28d1f895c6fe | 190 | #if defined(SYSCFG_CFGR1_I2C_FMP_PB8) |
| mbed_official | 340:28d1f895c6fe | 191 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 (SYSCFG_CFGR1_I2C_FMP_PB8) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| mbed_official | 340:28d1f895c6fe | 192 | 0: PB8 pin operates in standard mode |
| mbed_official | 340:28d1f895c6fe | 193 | 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */ |
| mbed_official | 340:28d1f895c6fe | 194 | #endif /* SYSCFG_CFGR1_I2C_FMP_PB8 */ |
| mbed_official | 340:28d1f895c6fe | 195 | |
| mbed_official | 340:28d1f895c6fe | 196 | #if defined(SYSCFG_CFGR1_I2C_FMP_PB9) |
| mbed_official | 340:28d1f895c6fe | 197 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 (SYSCFG_CFGR1_I2C_FMP_PB9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| mbed_official | 340:28d1f895c6fe | 198 | 0: PB9 pin operates in standard mode |
| mbed_official | 340:28d1f895c6fe | 199 | 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */ |
| mbed_official | 340:28d1f895c6fe | 200 | #endif /* SYSCFG_CFGR1_I2C_FMP_PB9 */ |
| mbed_official | 340:28d1f895c6fe | 201 | |
| mbed_official | 340:28d1f895c6fe | 202 | #if defined(SYSCFG_CFGR1_I2C_FMP_I2C1) |
| mbed_official | 340:28d1f895c6fe | 203 | #define HAL_SYSCFG_FASTMODEPLUS_I2C1 (SYSCFG_CFGR1_I2C_FMP_I2C1) /*!< I2C1 fast mode Plus driving capability activation |
| mbed_official | 340:28d1f895c6fe | 204 | 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits |
| mbed_official | 340:28d1f895c6fe | 205 | 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */ |
| mbed_official | 340:28d1f895c6fe | 206 | #endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */ |
| mbed_official | 340:28d1f895c6fe | 207 | |
| mbed_official | 340:28d1f895c6fe | 208 | #if defined(SYSCFG_CFGR1_I2C_FMP_I2C2) |
| mbed_official | 340:28d1f895c6fe | 209 | #define HAL_SYSCFG_FASTMODEPLUS_I2C2 (SYSCFG_CFGR1_I2C_FMP_I2C2) /*!< I2C2 fast mode Plus driving capability activation |
| mbed_official | 340:28d1f895c6fe | 210 | 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits |
| mbed_official | 340:28d1f895c6fe | 211 | 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */ |
| mbed_official | 340:28d1f895c6fe | 212 | #endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */ |
| mbed_official | 340:28d1f895c6fe | 213 | |
| mbed_official | 340:28d1f895c6fe | 214 | #if defined(SYSCFG_CFGR1_I2C_FMP_PA9) |
| mbed_official | 441:d2c15dda23c1 | 215 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 (SYSCFG_CFGR1_I2C_FMP_PA9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| mbed_official | 340:28d1f895c6fe | 216 | 0: PA9 pin operates in standard mode |
| mbed_official | 340:28d1f895c6fe | 217 | 1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */ |
| mbed_official | 340:28d1f895c6fe | 218 | #endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */ |
| mbed_official | 340:28d1f895c6fe | 219 | |
| mbed_official | 340:28d1f895c6fe | 220 | #if defined(SYSCFG_CFGR1_I2C_FMP_PA10) |
| mbed_official | 441:d2c15dda23c1 | 221 | #define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 (SYSCFG_CFGR1_I2C_FMP_PA10) /*!< Fast Mode Plus (FM+) driving capability activation on the pad |
| mbed_official | 340:28d1f895c6fe | 222 | 0: PA10 pin operates in standard mode |
| mbed_official | 340:28d1f895c6fe | 223 | 1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */ |
| mbed_official | 340:28d1f895c6fe | 224 | #endif /* SYSCFG_CFGR1_I2C_FMP_PA10 */ |
| mbed_official | 340:28d1f895c6fe | 225 | |
| mbed_official | 441:d2c15dda23c1 | 226 | #if defined(STM32F091xC) || defined(STM32F098xx) || defined(STM32F042x6) || defined(STM32F048xx) |
| mbed_official | 340:28d1f895c6fe | 227 | #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ |
| mbed_official | 340:28d1f895c6fe | 228 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ |
| mbed_official | 441:d2c15dda23c1 | 229 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \ |
| mbed_official | 441:d2c15dda23c1 | 230 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \ |
| mbed_official | 340:28d1f895c6fe | 231 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ |
| mbed_official | 340:28d1f895c6fe | 232 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ |
| mbed_official | 340:28d1f895c6fe | 233 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ |
| mbed_official | 340:28d1f895c6fe | 234 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) |
| mbed_official | 340:28d1f895c6fe | 235 | #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx) |
| mbed_official | 340:28d1f895c6fe | 236 | #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ |
| mbed_official | 340:28d1f895c6fe | 237 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \ |
| mbed_official | 340:28d1f895c6fe | 238 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ |
| mbed_official | 340:28d1f895c6fe | 239 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ |
| mbed_official | 340:28d1f895c6fe | 240 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ |
| mbed_official | 340:28d1f895c6fe | 241 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) |
| mbed_official | 441:d2c15dda23c1 | 242 | #elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx) || defined(STM32F070x6) || defined(STM32F070xB) || defined(STM32F030x6) |
| mbed_official | 340:28d1f895c6fe | 243 | #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \ |
| mbed_official | 441:d2c15dda23c1 | 244 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA9) || \ |
| mbed_official | 441:d2c15dda23c1 | 245 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PA10) || \ |
| mbed_official | 340:28d1f895c6fe | 246 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ |
| mbed_official | 340:28d1f895c6fe | 247 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ |
| mbed_official | 340:28d1f895c6fe | 248 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ |
| mbed_official | 340:28d1f895c6fe | 249 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) |
| mbed_official | 340:28d1f895c6fe | 250 | #else |
| mbed_official | 340:28d1f895c6fe | 251 | #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \ |
| mbed_official | 340:28d1f895c6fe | 252 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \ |
| mbed_official | 340:28d1f895c6fe | 253 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \ |
| mbed_official | 340:28d1f895c6fe | 254 | ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9)) |
| mbed_official | 340:28d1f895c6fe | 255 | #endif |
| mbed_official | 340:28d1f895c6fe | 256 | |
| mbed_official | 340:28d1f895c6fe | 257 | /** |
| mbed_official | 340:28d1f895c6fe | 258 | * @} |
| mbed_official | 340:28d1f895c6fe | 259 | */ |
| mbed_official | 340:28d1f895c6fe | 260 | |
| mbed_official | 340:28d1f895c6fe | 261 | #if defined(STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 262 | /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper |
| mbed_official | 441:d2c15dda23c1 | 263 | * @brief ISR Wrapper |
| mbed_official | 441:d2c15dda23c1 | 264 | * @note applicable on STM32F09x |
| mbed_official | 340:28d1f895c6fe | 265 | * @{ |
| mbed_official | 340:28d1f895c6fe | 266 | */ |
| mbed_official | 441:d2c15dda23c1 | 267 | #define HAL_SYSCFG_ITLINE0 ((uint32_t) 0x00000000) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 268 | #define HAL_SYSCFG_ITLINE1 ((uint32_t) 0x00000001) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 269 | #define HAL_SYSCFG_ITLINE2 ((uint32_t) 0x00000002) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 270 | #define HAL_SYSCFG_ITLINE3 ((uint32_t) 0x00000003) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 271 | #define HAL_SYSCFG_ITLINE4 ((uint32_t) 0x00000004) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 272 | #define HAL_SYSCFG_ITLINE5 ((uint32_t) 0x00000005) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 273 | #define HAL_SYSCFG_ITLINE6 ((uint32_t) 0x00000006) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 274 | #define HAL_SYSCFG_ITLINE7 ((uint32_t) 0x00000007) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 275 | #define HAL_SYSCFG_ITLINE8 ((uint32_t) 0x00000008) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 276 | #define HAL_SYSCFG_ITLINE9 ((uint32_t) 0x00000009) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 277 | #define HAL_SYSCFG_ITLINE10 ((uint32_t) 0x0000000A) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 278 | #define HAL_SYSCFG_ITLINE11 ((uint32_t) 0x0000000B) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 279 | #define HAL_SYSCFG_ITLINE12 ((uint32_t) 0x0000000C) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 280 | #define HAL_SYSCFG_ITLINE13 ((uint32_t) 0x0000000D) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 281 | #define HAL_SYSCFG_ITLINE14 ((uint32_t) 0x0000000E) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 282 | #define HAL_SYSCFG_ITLINE15 ((uint32_t) 0x0000000F) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 283 | #define HAL_SYSCFG_ITLINE16 ((uint32_t) 0x00000010) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 284 | #define HAL_SYSCFG_ITLINE17 ((uint32_t) 0x00000011) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 285 | #define HAL_SYSCFG_ITLINE18 ((uint32_t) 0x00000012) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 286 | #define HAL_SYSCFG_ITLINE19 ((uint32_t) 0x00000013) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 287 | #define HAL_SYSCFG_ITLINE20 ((uint32_t) 0x00000014) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 288 | #define HAL_SYSCFG_ITLINE21 ((uint32_t) 0x00000015) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 289 | #define HAL_SYSCFG_ITLINE22 ((uint32_t) 0x00000016) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 290 | #define HAL_SYSCFG_ITLINE23 ((uint32_t) 0x00000017) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 291 | #define HAL_SYSCFG_ITLINE24 ((uint32_t) 0x00000018) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 292 | #define HAL_SYSCFG_ITLINE25 ((uint32_t) 0x00000019) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 293 | #define HAL_SYSCFG_ITLINE26 ((uint32_t) 0x0000001A) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 294 | #define HAL_SYSCFG_ITLINE27 ((uint32_t) 0x0000001B) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 295 | #define HAL_SYSCFG_ITLINE28 ((uint32_t) 0x0000001C) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 296 | #define HAL_SYSCFG_ITLINE29 ((uint32_t) 0x0000001D) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 297 | #define HAL_SYSCFG_ITLINE30 ((uint32_t) 0x0000001E) /*!< Internal define for macro handling */ |
| mbed_official | 441:d2c15dda23c1 | 298 | #define HAL_SYSCFG_ITLINE31 ((uint32_t) 0x0000001F) /*!< Internal define for macro handling */ |
| mbed_official | 340:28d1f895c6fe | 299 | |
| mbed_official | 441:d2c15dda23c1 | 300 | #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /*!< EWDG has expired .... */ |
| mbed_official | 340:28d1f895c6fe | 301 | #if defined(STM32F091xC) |
| mbed_official | 441:d2c15dda23c1 | 302 | #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /*!< Power voltage detection Interrupt .... */ |
| mbed_official | 340:28d1f895c6fe | 303 | #endif |
| mbed_official | 441:d2c15dda23c1 | 304 | #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /*!< VDDIO2 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 305 | #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /*!< RTC WAKEUP -> exti[20] Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 306 | #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /*!< RTC Time Stamp -> exti[19] interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 307 | #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /*!< RTC Alarm -> exti[17] interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 308 | #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /*!< Flash ITF Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 309 | #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /*!< CRS Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 310 | #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /*!< CLK Control Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 311 | #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /*!< External Interrupt 0 */ |
| mbed_official | 441:d2c15dda23c1 | 312 | #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /*!< External Interrupt 1 */ |
| mbed_official | 441:d2c15dda23c1 | 313 | #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /*!< External Interrupt 2 */ |
| mbed_official | 441:d2c15dda23c1 | 314 | #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /*!< External Interrupt 3 */ |
| mbed_official | 441:d2c15dda23c1 | 315 | #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /*!< EXTI4 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 316 | #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /*!< EXTI5 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 317 | #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /*!< EXTI6 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 318 | #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /*!< EXTI7 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 319 | #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /*!< EXTI8 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 320 | #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /*!< EXTI9 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 321 | #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /*!< EXTI10 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 322 | #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /*!< EXTI11 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 323 | #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /*!< EXTI12 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 324 | #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /*!< EXTI13 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 325 | #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /*!< EXTI14 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 326 | #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /*!< EXTI15 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 327 | #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /*!< Touch control EOA Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 328 | #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /*!< Touch control MCE Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 329 | #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /*!< DMA1 Channel 1 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 330 | #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /*!< DMA1 Channel 2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 331 | #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /*!< DMA1 Channel 3 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 332 | #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /*!< DMA2 Channel 1 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 333 | #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /*!< DMA2 Channel 2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 334 | #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /*!< DMA1 Channel 4 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 335 | #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /*!< DMA1 Channel 5 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 336 | #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /*!< DMA1 Channel 6 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 337 | #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /*!< DMA1 Channel 7 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 338 | #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /*!< DMA2 Channel 3 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 339 | #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /*!< DMA2 Channel 4 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 340 | #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /*!< DMA2 Channel 5 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 341 | #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /*!< ADC Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 342 | #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /*!< COMP1 Interrupt -> exti[21] */ |
| mbed_official | 441:d2c15dda23c1 | 343 | #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /*!< COMP2 Interrupt -> exti[21] */ |
| mbed_official | 441:d2c15dda23c1 | 344 | #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /*!< TIM1 BRK Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 345 | #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /*!< TIM1 UPD Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 346 | #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /*!< TIM1 TRG Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 347 | #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /*!< TIM1 CCU Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 348 | #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /*!< TIM1 CC Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 349 | #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /*!< TIM2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 350 | #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /*!< TIM3 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 351 | #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /*!< DAC Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 352 | #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /*!< TIM6 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 353 | #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /*!< TIM7 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 354 | #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /*!< TIM14 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 355 | #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /*!< TIM15 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 356 | #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /*!< TIM16 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 357 | #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /*!< TIM17 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 358 | #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /*!< I2C1 Interrupt -> exti[23] */ |
| mbed_official | 441:d2c15dda23c1 | 359 | #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /*!< I2C2 Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 360 | #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /*!< I2C1 Interrupt -> exti[23] */ |
| mbed_official | 441:d2c15dda23c1 | 361 | #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /*!< SPI1 Interrupt */ |
| mbed_official | 340:28d1f895c6fe | 362 | #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */ |
| mbed_official | 340:28d1f895c6fe | 363 | #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */ |
| mbed_official | 441:d2c15dda23c1 | 364 | #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /*!< USART3 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 365 | #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /*!< USART4 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 366 | #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /*!< USART5 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 367 | #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /*!< USART6 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 368 | #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /*!< USART7 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 369 | #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /*!< USART8 Interrupt .... */ |
| mbed_official | 441:d2c15dda23c1 | 370 | #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /*!< CAN Interrupt */ |
| mbed_official | 441:d2c15dda23c1 | 371 | #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /*!< CEC Interrupt -> exti[27] */ |
| mbed_official | 340:28d1f895c6fe | 372 | /** |
| mbed_official | 340:28d1f895c6fe | 373 | * @} |
| mbed_official | 340:28d1f895c6fe | 374 | */ |
| mbed_official | 340:28d1f895c6fe | 375 | #endif /* STM32F091xC || STM32F098xx */ |
| mbed_official | 340:28d1f895c6fe | 376 | |
| mbed_official | 340:28d1f895c6fe | 377 | /** |
| mbed_official | 340:28d1f895c6fe | 378 | * @} |
| mbed_official | 340:28d1f895c6fe | 379 | */ |
| mbed_official | 340:28d1f895c6fe | 380 | |
| mbed_official | 340:28d1f895c6fe | 381 | /* Exported macros -----------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 382 | /** @defgroup HAL_Exported_Macros HAL Exported Macros |
| mbed_official | 340:28d1f895c6fe | 383 | * @{ |
| mbed_official | 340:28d1f895c6fe | 384 | */ |
| mbed_official | 340:28d1f895c6fe | 385 | |
| mbed_official | 340:28d1f895c6fe | 386 | /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals |
| mbed_official | 340:28d1f895c6fe | 387 | * @brief Freeze/Unfreeze Peripherals in Debug mode |
| mbed_official | 340:28d1f895c6fe | 388 | * @{ |
| mbed_official | 340:28d1f895c6fe | 389 | */ |
| mbed_official | 340:28d1f895c6fe | 390 | |
| mbed_official | 340:28d1f895c6fe | 391 | #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP) |
| mbed_official | 340:28d1f895c6fe | 392 | #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| mbed_official | 340:28d1f895c6fe | 393 | #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP)) |
| mbed_official | 340:28d1f895c6fe | 394 | #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */ |
| mbed_official | 340:28d1f895c6fe | 395 | |
| mbed_official | 340:28d1f895c6fe | 396 | #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP) |
| mbed_official | 340:28d1f895c6fe | 397 | #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| mbed_official | 340:28d1f895c6fe | 398 | #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP)) |
| mbed_official | 340:28d1f895c6fe | 399 | #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */ |
| mbed_official | 340:28d1f895c6fe | 400 | |
| mbed_official | 340:28d1f895c6fe | 401 | #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT) |
| mbed_official | 340:28d1f895c6fe | 402 | #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| mbed_official | 340:28d1f895c6fe | 403 | #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)) |
| mbed_official | 340:28d1f895c6fe | 404 | #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */ |
| mbed_official | 340:28d1f895c6fe | 405 | |
| mbed_official | 340:28d1f895c6fe | 406 | #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP) |
| mbed_official | 340:28d1f895c6fe | 407 | #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| mbed_official | 340:28d1f895c6fe | 408 | #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP)) |
| mbed_official | 340:28d1f895c6fe | 409 | #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */ |
| mbed_official | 340:28d1f895c6fe | 410 | |
| mbed_official | 340:28d1f895c6fe | 411 | #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP) |
| mbed_official | 340:28d1f895c6fe | 412 | #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| mbed_official | 340:28d1f895c6fe | 413 | #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP)) |
| mbed_official | 340:28d1f895c6fe | 414 | #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */ |
| mbed_official | 340:28d1f895c6fe | 415 | |
| mbed_official | 340:28d1f895c6fe | 416 | #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP) |
| mbed_official | 340:28d1f895c6fe | 417 | #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| mbed_official | 340:28d1f895c6fe | 418 | #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP)) |
| mbed_official | 340:28d1f895c6fe | 419 | #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */ |
| mbed_official | 340:28d1f895c6fe | 420 | |
| mbed_official | 340:28d1f895c6fe | 421 | #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP) |
| mbed_official | 340:28d1f895c6fe | 422 | #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| mbed_official | 340:28d1f895c6fe | 423 | #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP)) |
| mbed_official | 340:28d1f895c6fe | 424 | #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */ |
| mbed_official | 340:28d1f895c6fe | 425 | |
| mbed_official | 340:28d1f895c6fe | 426 | #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP) |
| mbed_official | 340:28d1f895c6fe | 427 | #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| mbed_official | 340:28d1f895c6fe | 428 | #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP)) |
| mbed_official | 340:28d1f895c6fe | 429 | #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */ |
| mbed_official | 340:28d1f895c6fe | 430 | |
| mbed_official | 340:28d1f895c6fe | 431 | #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP) |
| mbed_official | 340:28d1f895c6fe | 432 | #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| mbed_official | 340:28d1f895c6fe | 433 | #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP)) |
| mbed_official | 340:28d1f895c6fe | 434 | #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */ |
| mbed_official | 340:28d1f895c6fe | 435 | |
| mbed_official | 340:28d1f895c6fe | 436 | #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP) |
| mbed_official | 340:28d1f895c6fe | 437 | #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| mbed_official | 340:28d1f895c6fe | 438 | #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP)) |
| mbed_official | 340:28d1f895c6fe | 439 | #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */ |
| mbed_official | 340:28d1f895c6fe | 440 | |
| mbed_official | 340:28d1f895c6fe | 441 | #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP) |
| mbed_official | 340:28d1f895c6fe | 442 | #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| mbed_official | 340:28d1f895c6fe | 443 | #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP)) |
| mbed_official | 340:28d1f895c6fe | 444 | #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */ |
| mbed_official | 340:28d1f895c6fe | 445 | |
| mbed_official | 340:28d1f895c6fe | 446 | #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP) |
| mbed_official | 340:28d1f895c6fe | 447 | #define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| mbed_official | 340:28d1f895c6fe | 448 | #define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP)) |
| mbed_official | 340:28d1f895c6fe | 449 | #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */ |
| mbed_official | 340:28d1f895c6fe | 450 | |
| mbed_official | 340:28d1f895c6fe | 451 | #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP) |
| mbed_official | 340:28d1f895c6fe | 452 | #define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| mbed_official | 340:28d1f895c6fe | 453 | #define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP)) |
| mbed_official | 340:28d1f895c6fe | 454 | #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */ |
| mbed_official | 340:28d1f895c6fe | 455 | |
| mbed_official | 340:28d1f895c6fe | 456 | #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP) |
| mbed_official | 340:28d1f895c6fe | 457 | #define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| mbed_official | 340:28d1f895c6fe | 458 | #define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP)) |
| mbed_official | 340:28d1f895c6fe | 459 | #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */ |
| mbed_official | 340:28d1f895c6fe | 460 | |
| mbed_official | 340:28d1f895c6fe | 461 | /** |
| mbed_official | 340:28d1f895c6fe | 462 | * @} |
| mbed_official | 340:28d1f895c6fe | 463 | */ |
| mbed_official | 340:28d1f895c6fe | 464 | |
| mbed_official | 340:28d1f895c6fe | 465 | /** @defgroup Memory_Mapping_Selection Memory Mapping Selection |
| mbed_official | 340:28d1f895c6fe | 466 | * @{ |
| mbed_official | 340:28d1f895c6fe | 467 | */ |
| mbed_official | 340:28d1f895c6fe | 468 | #if defined(SYSCFG_CFGR1_MEM_MODE) |
| mbed_official | 340:28d1f895c6fe | 469 | /** @brief Main Flash memory mapped at 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 470 | */ |
| mbed_official | 340:28d1f895c6fe | 471 | #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE)) |
| mbed_official | 340:28d1f895c6fe | 472 | #endif /* SYSCFG_CFGR1_MEM_MODE */ |
| mbed_official | 340:28d1f895c6fe | 473 | |
| mbed_official | 340:28d1f895c6fe | 474 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) |
| mbed_official | 340:28d1f895c6fe | 475 | /** @brief System Flash memory mapped at 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 476 | */ |
| mbed_official | 340:28d1f895c6fe | 477 | #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| mbed_official | 340:28d1f895c6fe | 478 | SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \ |
| mbed_official | 340:28d1f895c6fe | 479 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 480 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 */ |
| mbed_official | 340:28d1f895c6fe | 481 | |
| mbed_official | 340:28d1f895c6fe | 482 | #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1) |
| mbed_official | 340:28d1f895c6fe | 483 | /** @brief Embedded SRAM mapped at 0x00000000 |
| mbed_official | 340:28d1f895c6fe | 484 | */ |
| mbed_official | 340:28d1f895c6fe | 485 | #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \ |
| mbed_official | 340:28d1f895c6fe | 486 | SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \ |
| mbed_official | 340:28d1f895c6fe | 487 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 488 | #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */ |
| mbed_official | 340:28d1f895c6fe | 489 | /** |
| mbed_official | 340:28d1f895c6fe | 490 | * @} |
| mbed_official | 340:28d1f895c6fe | 491 | */ |
| mbed_official | 340:28d1f895c6fe | 492 | |
| mbed_official | 340:28d1f895c6fe | 493 | #if defined(SYSCFG_CFGR1_DMA_RMP) |
| mbed_official | 340:28d1f895c6fe | 494 | /** @defgroup HAL_DMA_remap HAL DMA remap |
| mbed_official | 340:28d1f895c6fe | 495 | * @brief DMA remapping enable/disable macros |
| mbed_official | 340:28d1f895c6fe | 496 | * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping |
| mbed_official | 340:28d1f895c6fe | 497 | * @{ |
| mbed_official | 340:28d1f895c6fe | 498 | */ |
| mbed_official | 340:28d1f895c6fe | 499 | #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| mbed_official | 340:28d1f895c6fe | 500 | SYSCFG->CFGR1 |= (__DMA_REMAP__); \ |
| mbed_official | 340:28d1f895c6fe | 501 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 502 | #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \ |
| mbed_official | 340:28d1f895c6fe | 503 | SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \ |
| mbed_official | 340:28d1f895c6fe | 504 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 505 | /** |
| mbed_official | 340:28d1f895c6fe | 506 | * @} |
| mbed_official | 340:28d1f895c6fe | 507 | */ |
| mbed_official | 340:28d1f895c6fe | 508 | #endif /* SYSCFG_CFGR1_DMA_RMP */ |
| mbed_official | 340:28d1f895c6fe | 509 | |
| mbed_official | 340:28d1f895c6fe | 510 | #if defined(SYSCFG_CFGR1_PA11_PA12_RMP) |
| mbed_official | 340:28d1f895c6fe | 511 | /** @defgroup HAL_Pin_remap HAL Pin remap |
| mbed_official | 340:28d1f895c6fe | 512 | * @brief Pin remapping enable/disable macros |
| mbed_official | 340:28d1f895c6fe | 513 | * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping |
| mbed_official | 340:28d1f895c6fe | 514 | * @{ |
| mbed_official | 340:28d1f895c6fe | 515 | */ |
| mbed_official | 340:28d1f895c6fe | 516 | #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ |
| mbed_official | 340:28d1f895c6fe | 517 | SYSCFG->CFGR1 |= (__PIN_REMAP__); \ |
| mbed_official | 340:28d1f895c6fe | 518 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 519 | #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \ |
| mbed_official | 340:28d1f895c6fe | 520 | SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \ |
| mbed_official | 340:28d1f895c6fe | 521 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 522 | /** |
| mbed_official | 340:28d1f895c6fe | 523 | * @} |
| mbed_official | 340:28d1f895c6fe | 524 | */ |
| mbed_official | 340:28d1f895c6fe | 525 | #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */ |
| mbed_official | 340:28d1f895c6fe | 526 | |
| mbed_official | 340:28d1f895c6fe | 527 | /** @defgroup HAL_Fast_mode_plus_driving_cap HAL Fast mode plus driving cap |
| mbed_official | 340:28d1f895c6fe | 528 | * @brief Fast mode Plus driving capability enable/disable macros |
| mbed_official | 340:28d1f895c6fe | 529 | * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C |
| mbed_official | 340:28d1f895c6fe | 530 | * @{ |
| mbed_official | 340:28d1f895c6fe | 531 | */ |
| mbed_official | 340:28d1f895c6fe | 532 | #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ |
| mbed_official | 340:28d1f895c6fe | 533 | SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \ |
| mbed_official | 340:28d1f895c6fe | 534 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 535 | |
| mbed_official | 340:28d1f895c6fe | 536 | #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \ |
| mbed_official | 340:28d1f895c6fe | 537 | SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \ |
| mbed_official | 340:28d1f895c6fe | 538 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 539 | /** |
| mbed_official | 340:28d1f895c6fe | 540 | * @} |
| mbed_official | 340:28d1f895c6fe | 541 | */ |
| mbed_official | 340:28d1f895c6fe | 542 | |
| mbed_official | 340:28d1f895c6fe | 543 | #if defined(SYSCFG_CFGR2_LOCKUP_LOCK) |
| mbed_official | 340:28d1f895c6fe | 544 | /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable |
| mbed_official | 340:28d1f895c6fe | 545 | * @{ |
| mbed_official | 340:28d1f895c6fe | 546 | */ |
| mbed_official | 340:28d1f895c6fe | 547 | /** @brief SYSCFG Break Lockup lock |
| mbed_official | 340:28d1f895c6fe | 548 | * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input |
| mbed_official | 340:28d1f895c6fe | 549 | * @note The selected configuration is locked and can be unlocked by system reset |
| mbed_official | 340:28d1f895c6fe | 550 | */ |
| mbed_official | 340:28d1f895c6fe | 551 | #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \ |
| mbed_official | 340:28d1f895c6fe | 552 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \ |
| mbed_official | 340:28d1f895c6fe | 553 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 554 | /** |
| mbed_official | 340:28d1f895c6fe | 555 | * @} |
| mbed_official | 340:28d1f895c6fe | 556 | */ |
| mbed_official | 340:28d1f895c6fe | 557 | #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */ |
| mbed_official | 340:28d1f895c6fe | 558 | |
| mbed_official | 340:28d1f895c6fe | 559 | #if defined(SYSCFG_CFGR2_PVD_LOCK) |
| mbed_official | 340:28d1f895c6fe | 560 | /** @defgroup PVD_Lock_Enable PVD Lock |
| mbed_official | 340:28d1f895c6fe | 561 | * @{ |
| mbed_official | 340:28d1f895c6fe | 562 | */ |
| mbed_official | 340:28d1f895c6fe | 563 | /** @brief SYSCFG Break PVD lock |
| mbed_official | 340:28d1f895c6fe | 564 | * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register |
| mbed_official | 340:28d1f895c6fe | 565 | * @note The selected configuration is locked and can be unlocked by system reset |
| mbed_official | 340:28d1f895c6fe | 566 | */ |
| mbed_official | 340:28d1f895c6fe | 567 | #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \ |
| mbed_official | 340:28d1f895c6fe | 568 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \ |
| mbed_official | 340:28d1f895c6fe | 569 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 570 | /** |
| mbed_official | 340:28d1f895c6fe | 571 | * @} |
| mbed_official | 340:28d1f895c6fe | 572 | */ |
| mbed_official | 340:28d1f895c6fe | 573 | #endif /* SYSCFG_CFGR2_PVD_LOCK */ |
| mbed_official | 340:28d1f895c6fe | 574 | |
| mbed_official | 340:28d1f895c6fe | 575 | #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK) |
| mbed_official | 340:28d1f895c6fe | 576 | /** @defgroup SRAM_Parity_Lock SRAM Parity Lock |
| mbed_official | 340:28d1f895c6fe | 577 | * @{ |
| mbed_official | 340:28d1f895c6fe | 578 | */ |
| mbed_official | 340:28d1f895c6fe | 579 | /** @brief SYSCFG Break SRAM PARITY lock |
| mbed_official | 340:28d1f895c6fe | 580 | * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 |
| mbed_official | 340:28d1f895c6fe | 581 | * @note The selected configuration is locked and can be unlocked by system reset |
| mbed_official | 340:28d1f895c6fe | 582 | */ |
| mbed_official | 340:28d1f895c6fe | 583 | #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \ |
| mbed_official | 340:28d1f895c6fe | 584 | SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \ |
| mbed_official | 340:28d1f895c6fe | 585 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 586 | /** |
| mbed_official | 340:28d1f895c6fe | 587 | * @} |
| mbed_official | 340:28d1f895c6fe | 588 | */ |
| mbed_official | 340:28d1f895c6fe | 589 | #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */ |
| mbed_official | 340:28d1f895c6fe | 590 | |
| mbed_official | 340:28d1f895c6fe | 591 | #if defined(SYSCFG_CFGR2_SRAM_PEF) |
| mbed_official | 340:28d1f895c6fe | 592 | /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM |
| mbed_official | 340:28d1f895c6fe | 593 | * @brief Parity check on RAM disable macro |
| mbed_official | 340:28d1f895c6fe | 594 | * @note Disabling the parity check on RAM locks the configuration bit. |
| mbed_official | 340:28d1f895c6fe | 595 | * To re-enable the parity check on RAM perform a system reset. |
| mbed_official | 340:28d1f895c6fe | 596 | * @{ |
| mbed_official | 340:28d1f895c6fe | 597 | */ |
| mbed_official | 340:28d1f895c6fe | 598 | #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF) |
| mbed_official | 340:28d1f895c6fe | 599 | /** |
| mbed_official | 340:28d1f895c6fe | 600 | * @} |
| mbed_official | 340:28d1f895c6fe | 601 | */ |
| mbed_official | 340:28d1f895c6fe | 602 | #endif /* SYSCFG_CFGR2_SRAM_PEF */ |
| mbed_official | 340:28d1f895c6fe | 603 | |
| mbed_official | 340:28d1f895c6fe | 604 | |
| mbed_official | 340:28d1f895c6fe | 605 | #if defined(STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 606 | /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check |
| mbed_official | 340:28d1f895c6fe | 607 | * @brief ISR wrapper check |
| mbed_official | 441:d2c15dda23c1 | 608 | * @note This feature is applicable on STM32F09x |
| mbed_official | 441:d2c15dda23c1 | 609 | * @note Allow to determine interrupt source per line. |
| mbed_official | 340:28d1f895c6fe | 610 | * @{ |
| mbed_official | 340:28d1f895c6fe | 611 | */ |
| mbed_official | 340:28d1f895c6fe | 612 | #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18)] & ((__SOURCE__) & 0x00FFFFFF)) |
| mbed_official | 340:28d1f895c6fe | 613 | /** |
| mbed_official | 340:28d1f895c6fe | 614 | * @} |
| mbed_official | 340:28d1f895c6fe | 615 | */ |
| mbed_official | 340:28d1f895c6fe | 616 | #endif /* (STM32F091xC) || defined (STM32F098xx)*/ |
| mbed_official | 340:28d1f895c6fe | 617 | |
| mbed_official | 340:28d1f895c6fe | 618 | #if defined(STM32F091xC) || defined (STM32F098xx) |
| mbed_official | 340:28d1f895c6fe | 619 | /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection |
| mbed_official | 340:28d1f895c6fe | 620 | * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register |
| mbed_official | 441:d2c15dda23c1 | 621 | * @note This feature is applicable on STM32F09x |
| mbed_official | 340:28d1f895c6fe | 622 | * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL |
| mbed_official | 340:28d1f895c6fe | 623 | * @{ |
| mbed_official | 340:28d1f895c6fe | 624 | */ |
| mbed_official | 340:28d1f895c6fe | 625 | #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \ |
| mbed_official | 340:28d1f895c6fe | 626 | SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \ |
| mbed_official | 340:28d1f895c6fe | 627 | SYSCFG->CFGR1 |= (__SOURCE__); \ |
| mbed_official | 340:28d1f895c6fe | 628 | }while(0) |
| mbed_official | 340:28d1f895c6fe | 629 | |
| mbed_official | 340:28d1f895c6fe | 630 | #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0) |
| mbed_official | 340:28d1f895c6fe | 631 | /** |
| mbed_official | 340:28d1f895c6fe | 632 | * @} |
| mbed_official | 340:28d1f895c6fe | 633 | */ |
| mbed_official | 340:28d1f895c6fe | 634 | #endif /* (STM32F091xC) || defined (STM32F098xx)*/ |
| mbed_official | 340:28d1f895c6fe | 635 | |
| mbed_official | 340:28d1f895c6fe | 636 | /** |
| mbed_official | 340:28d1f895c6fe | 637 | * @} |
| mbed_official | 340:28d1f895c6fe | 638 | */ |
| mbed_official | 340:28d1f895c6fe | 639 | /* Exported functions --------------------------------------------------------*/ |
| mbed_official | 340:28d1f895c6fe | 640 | /** @addtogroup HAL_Exported_Functions HAL Exported Functions |
| mbed_official | 340:28d1f895c6fe | 641 | * @{ |
| mbed_official | 340:28d1f895c6fe | 642 | */ |
| mbed_official | 340:28d1f895c6fe | 643 | |
| mbed_official | 340:28d1f895c6fe | 644 | /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions |
| mbed_official | 340:28d1f895c6fe | 645 | * @brief Initialization and de-initialization functions |
| mbed_official | 340:28d1f895c6fe | 646 | * @{ |
| mbed_official | 340:28d1f895c6fe | 647 | */ |
| mbed_official | 340:28d1f895c6fe | 648 | /* Initialization and de-initialization functions ******************************/ |
| mbed_official | 340:28d1f895c6fe | 649 | HAL_StatusTypeDef HAL_Init(void); |
| mbed_official | 340:28d1f895c6fe | 650 | HAL_StatusTypeDef HAL_DeInit(void); |
| mbed_official | 340:28d1f895c6fe | 651 | void HAL_MspInit(void); |
| mbed_official | 340:28d1f895c6fe | 652 | void HAL_MspDeInit(void); |
| mbed_official | 340:28d1f895c6fe | 653 | HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority); |
| mbed_official | 340:28d1f895c6fe | 654 | /** |
| mbed_official | 340:28d1f895c6fe | 655 | * @} |
| mbed_official | 340:28d1f895c6fe | 656 | */ |
| mbed_official | 340:28d1f895c6fe | 657 | |
| mbed_official | 340:28d1f895c6fe | 658 | /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions |
| mbed_official | 340:28d1f895c6fe | 659 | * @brief HAL Control functions |
| mbed_official | 340:28d1f895c6fe | 660 | * @{ |
| mbed_official | 340:28d1f895c6fe | 661 | */ |
| mbed_official | 340:28d1f895c6fe | 662 | /* Peripheral Control functions **********************************************/ |
| mbed_official | 340:28d1f895c6fe | 663 | void HAL_IncTick(void); |
| mbed_official | 340:28d1f895c6fe | 664 | void HAL_Delay(__IO uint32_t Delay); |
| mbed_official | 340:28d1f895c6fe | 665 | uint32_t HAL_GetTick(void); |
| mbed_official | 340:28d1f895c6fe | 666 | void HAL_SuspendTick(void); |
| mbed_official | 340:28d1f895c6fe | 667 | void HAL_ResumeTick(void); |
| mbed_official | 340:28d1f895c6fe | 668 | uint32_t HAL_GetHalVersion(void); |
| mbed_official | 340:28d1f895c6fe | 669 | uint32_t HAL_GetREVID(void); |
| mbed_official | 340:28d1f895c6fe | 670 | uint32_t HAL_GetDEVID(void); |
| mbed_official | 340:28d1f895c6fe | 671 | void HAL_EnableDBGStopMode(void); |
| mbed_official | 340:28d1f895c6fe | 672 | void HAL_DisableDBGStopMode(void); |
| mbed_official | 340:28d1f895c6fe | 673 | void HAL_EnableDBGStandbyMode(void); |
| mbed_official | 340:28d1f895c6fe | 674 | void HAL_DisableDBGStandbyMode(void); |
| mbed_official | 340:28d1f895c6fe | 675 | /** |
| mbed_official | 340:28d1f895c6fe | 676 | * @} |
| mbed_official | 340:28d1f895c6fe | 677 | */ |
| mbed_official | 340:28d1f895c6fe | 678 | |
| mbed_official | 340:28d1f895c6fe | 679 | /** |
| mbed_official | 340:28d1f895c6fe | 680 | * @} |
| mbed_official | 340:28d1f895c6fe | 681 | */ |
| mbed_official | 340:28d1f895c6fe | 682 | |
| mbed_official | 340:28d1f895c6fe | 683 | /** |
| mbed_official | 340:28d1f895c6fe | 684 | * @} |
| mbed_official | 340:28d1f895c6fe | 685 | */ |
| mbed_official | 340:28d1f895c6fe | 686 | |
| mbed_official | 340:28d1f895c6fe | 687 | /** |
| mbed_official | 340:28d1f895c6fe | 688 | * @} |
| mbed_official | 340:28d1f895c6fe | 689 | */ |
| mbed_official | 340:28d1f895c6fe | 690 | |
| mbed_official | 340:28d1f895c6fe | 691 | #ifdef __cplusplus |
| mbed_official | 340:28d1f895c6fe | 692 | } |
| mbed_official | 340:28d1f895c6fe | 693 | #endif |
| mbed_official | 340:28d1f895c6fe | 694 | |
| mbed_official | 340:28d1f895c6fe | 695 | #endif /* __STM32F0xx_HAL_H */ |
| mbed_official | 340:28d1f895c6fe | 696 | |
| mbed_official | 340:28d1f895c6fe | 697 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |