mbed library sources

Fork of mbed-src by mbed official

Committer:
mbed_official
Date:
Thu Oct 09 08:15:07 2014 +0100
Revision:
340:28d1f895c6fe
Synchronized with git revision b5a4c8e80393336b2656fb29ab46d405d3068602

Full URL: https://github.com/mbedmicro/mbed/commit/b5a4c8e80393336b2656fb29ab46d405d3068602/

HAL: nrf51822 - Few fixes for PWM and Serial

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 340:28d1f895c6fe 1 /**
mbed_official 340:28d1f895c6fe 2 ******************************************************************************
mbed_official 340:28d1f895c6fe 3 * @file stm32f0xx_hal.h
mbed_official 340:28d1f895c6fe 4 * @author MCD Application Team
mbed_official 340:28d1f895c6fe 5 * @version V1.1.0
mbed_official 340:28d1f895c6fe 6 * @date 03-Oct-2014
mbed_official 340:28d1f895c6fe 7 * @brief This file contains all the functions prototypes for the HAL
mbed_official 340:28d1f895c6fe 8 * module driver.
mbed_official 340:28d1f895c6fe 9 ******************************************************************************
mbed_official 340:28d1f895c6fe 10 * @attention
mbed_official 340:28d1f895c6fe 11 *
mbed_official 340:28d1f895c6fe 12 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 340:28d1f895c6fe 13 *
mbed_official 340:28d1f895c6fe 14 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 340:28d1f895c6fe 15 * are permitted provided that the following conditions are met:
mbed_official 340:28d1f895c6fe 16 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 340:28d1f895c6fe 17 * this list of conditions and the following disclaimer.
mbed_official 340:28d1f895c6fe 18 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 340:28d1f895c6fe 19 * this list of conditions and the following disclaimer in the documentation
mbed_official 340:28d1f895c6fe 20 * and/or other materials provided with the distribution.
mbed_official 340:28d1f895c6fe 21 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 340:28d1f895c6fe 22 * may be used to endorse or promote products derived from this software
mbed_official 340:28d1f895c6fe 23 * without specific prior written permission.
mbed_official 340:28d1f895c6fe 24 *
mbed_official 340:28d1f895c6fe 25 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 340:28d1f895c6fe 26 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 340:28d1f895c6fe 27 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 340:28d1f895c6fe 28 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 340:28d1f895c6fe 29 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 340:28d1f895c6fe 30 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 340:28d1f895c6fe 31 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 340:28d1f895c6fe 32 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 340:28d1f895c6fe 33 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 340:28d1f895c6fe 34 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 340:28d1f895c6fe 35 *
mbed_official 340:28d1f895c6fe 36 ******************************************************************************
mbed_official 340:28d1f895c6fe 37 */
mbed_official 340:28d1f895c6fe 38
mbed_official 340:28d1f895c6fe 39 /* Define to prevent recursive inclusion -------------------------------------*/
mbed_official 340:28d1f895c6fe 40 #ifndef __STM32F0xx_HAL_H
mbed_official 340:28d1f895c6fe 41 #define __STM32F0xx_HAL_H
mbed_official 340:28d1f895c6fe 42
mbed_official 340:28d1f895c6fe 43 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 44 extern "C" {
mbed_official 340:28d1f895c6fe 45 #endif
mbed_official 340:28d1f895c6fe 46
mbed_official 340:28d1f895c6fe 47 /* Includes ------------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 48 #include "stm32f0xx_hal_conf.h"
mbed_official 340:28d1f895c6fe 49
mbed_official 340:28d1f895c6fe 50 /** @addtogroup STM32F0xx_HAL_Driver
mbed_official 340:28d1f895c6fe 51 * @{
mbed_official 340:28d1f895c6fe 52 */
mbed_official 340:28d1f895c6fe 53
mbed_official 340:28d1f895c6fe 54 /** @addtogroup HAL
mbed_official 340:28d1f895c6fe 55 * @{
mbed_official 340:28d1f895c6fe 56 */
mbed_official 340:28d1f895c6fe 57
mbed_official 340:28d1f895c6fe 58 /* Exported types ------------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 59 /* Exported constants --------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 60 /** @defgroup HAL_Exported_Constants HAL Exported Constants
mbed_official 340:28d1f895c6fe 61 * @{
mbed_official 340:28d1f895c6fe 62 */
mbed_official 340:28d1f895c6fe 63
mbed_official 340:28d1f895c6fe 64 #if defined(SYSCFG_CFGR1_DMA_RMP)
mbed_official 340:28d1f895c6fe 65 /** @defgroup HAL_DMA_remapping HAL DMA remapping
mbed_official 340:28d1f895c6fe 66 * Elements values convention: 0xYYYYYYYY
mbed_official 340:28d1f895c6fe 67 * - YYYYYYYY : Position in the SYSCFG register CFGR1
mbed_official 340:28d1f895c6fe 68 * @{
mbed_official 340:28d1f895c6fe 69 */
mbed_official 340:28d1f895c6fe 70 #define HAL_REMAPDMA_ADC_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_ADC_DMA_RMP) /*!< ADC DMA remap
mbed_official 340:28d1f895c6fe 71 0: No remap (ADC DMA requests mapped on DMA channel 1
mbed_official 340:28d1f895c6fe 72 1: Remap (ADC DMA requests mapped on DMA channel 2 */
mbed_official 340:28d1f895c6fe 73 #define HAL_REMAPDMA_USART1_TX_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_USART1TX_DMA_RMP) /*!< USART1 TX DMA remap
mbed_official 340:28d1f895c6fe 74 0: No remap (USART1_TX DMA request mapped on DMA channel 2
mbed_official 340:28d1f895c6fe 75 1: Remap (USART1_TX DMA request mapped on DMA channel 4 */
mbed_official 340:28d1f895c6fe 76 #define HAL_REMAPDMA_USART1_RX_DMA_CH5 ((uint32_t)SYSCFG_CFGR1_USART1RX_DMA_RMP) /*!< USART1 RX DMA remap
mbed_official 340:28d1f895c6fe 77 0: No remap (USART1_RX DMA request mapped on DMA channel 3
mbed_official 340:28d1f895c6fe 78 1: Remap (USART1_RX DMA request mapped on DMA channel 5 */
mbed_official 340:28d1f895c6fe 79 #define HAL_REMAPDMA_TIM16_DMA_CH4 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP) /*!< TIM16 DMA request remap
mbed_official 340:28d1f895c6fe 80 0: No remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 3)
mbed_official 340:28d1f895c6fe 81 1: Remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 4) */
mbed_official 340:28d1f895c6fe 82 #define HAL_REMAPDMA_TIM17_DMA_CH2 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP) /*!< TIM17 DMA request remap
mbed_official 340:28d1f895c6fe 83 0: No remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 1
mbed_official 340:28d1f895c6fe 84 1: Remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 2) */
mbed_official 340:28d1f895c6fe 85
mbed_official 340:28d1f895c6fe 86 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
mbed_official 340:28d1f895c6fe 87 #define HAL_REMAPDMA_TIM16_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM16_DMA_RMP2) /*!< TIM16 alternate DMA request remapping bit. Available on STM32F07x devices only
mbed_official 340:28d1f895c6fe 88 0: No alternate remap (TIM16 DMA requestsmapped according to TIM16_DMA_RMP bit)
mbed_official 340:28d1f895c6fe 89 1: Alternate remap (TIM16_CH1 and TIM16_UP DMA requests mapped on DMA channel 6) */
mbed_official 340:28d1f895c6fe 90 #define HAL_REMAPDMA_TIM17_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM17_DMA_RMP2) /*!< TIM17 alternate DMA request remapping bit. Available on STM32F07x devices only
mbed_official 340:28d1f895c6fe 91 0: No alternate remap (TIM17 DMA requestsmapped according to TIM17_DMA_RMP bit)
mbed_official 340:28d1f895c6fe 92 1: Alternate remap (TIM17_CH1 and TIM17_UP DMA requests mapped on DMA channel 7) */
mbed_official 340:28d1f895c6fe 93 #define HAL_REMAPDMA_SPI2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_SPI2_DMA_RMP) /*!< SPI2 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 340:28d1f895c6fe 94 0: No remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 4 and 5 respectively)
mbed_official 340:28d1f895c6fe 95 1: 1: Remap (SPI2_RX and SPI2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
mbed_official 340:28d1f895c6fe 96 #define HAL_REMAPDMA_USART2_DMA_CH67 ((uint32_t)SYSCFG_CFGR1_USART2_DMA_RMP) /*!< USART2 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 340:28d1f895c6fe 97 0: No remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 5 and 4 respectively)
mbed_official 340:28d1f895c6fe 98 1: 1: Remap (USART2_RX and USART2_TX DMA requests mapped on DMA channel 6 and 7 respectively) */
mbed_official 340:28d1f895c6fe 99 #define HAL_REMAPDMA_USART3_DMA_CH32 ((uint32_t)SYSCFG_CFGR1_USART3_DMA_RMP) /*!< USART3 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 340:28d1f895c6fe 100 0: No remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 6 and 7 respectively)
mbed_official 340:28d1f895c6fe 101 1: 1: Remap (USART3_RX and USART3_TX DMA requests mapped on DMA channel 3 and 2 respectively) */
mbed_official 340:28d1f895c6fe 102 #define HAL_REMAPDMA_I2C1_DMA_CH76 ((uint32_t)SYSCFG_CFGR1_I2C1_DMA_RMP) /*!< I2C1 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 340:28d1f895c6fe 103 0: No remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 3 and 2 respectively)
mbed_official 340:28d1f895c6fe 104 1: Remap (I2C1_RX and I2C1_TX DMA requests mapped on DMA channel 7 and 6 respectively) */
mbed_official 340:28d1f895c6fe 105 #define HAL_REMAPDMA_TIM1_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM1_DMA_RMP) /*!< TIM1 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 340:28d1f895c6fe 106 0: No remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 2, 3 and 4 respectively)
mbed_official 340:28d1f895c6fe 107 1: Remap (TIM1_CH1, TIM1_CH2 and TIM1_CH3 DMA requests mapped on DMA channel 6 */
mbed_official 340:28d1f895c6fe 108 #define HAL_REMAPDMA_TIM2_DMA_CH7 ((uint32_t)SYSCFG_CFGR1_TIM2_DMA_RMP) /*!< TIM2 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 340:28d1f895c6fe 109 0: No remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 3 and 4 respectively)
mbed_official 340:28d1f895c6fe 110 1: Remap (TIM2_CH2 and TIM2_CH4 DMA requests mapped on DMA channel 7 */
mbed_official 340:28d1f895c6fe 111 #define HAL_REMAPDMA_TIM3_DMA_CH6 ((uint32_t)SYSCFG_CFGR1_TIM3_DMA_RMP) /*!< TIM3 DMA request remapping bit. Available on STM32F07x devices only.
mbed_official 340:28d1f895c6fe 112 0: No remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 4)
mbed_official 340:28d1f895c6fe 113 1: Remap (TIM3_CH1 and TIM3_TRIG DMA requests mapped on DMA channel 6) */
mbed_official 340:28d1f895c6fe 114 #endif
mbed_official 340:28d1f895c6fe 115
mbed_official 340:28d1f895c6fe 116 #if defined (STM32F071xB) || defined (STM32F072xB) || defined (STM32F078xx)
mbed_official 340:28d1f895c6fe 117 #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \
mbed_official 340:28d1f895c6fe 118 ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
mbed_official 340:28d1f895c6fe 119 ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
mbed_official 340:28d1f895c6fe 120 ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \
mbed_official 340:28d1f895c6fe 121 ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2) || \
mbed_official 340:28d1f895c6fe 122 ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH6) || \
mbed_official 340:28d1f895c6fe 123 ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH7) || \
mbed_official 340:28d1f895c6fe 124 ((RMP) == HAL_REMAPDMA_SPI2_DMA_CH67) || \
mbed_official 340:28d1f895c6fe 125 ((RMP) == HAL_REMAPDMA_USART2_DMA_CH67) || \
mbed_official 340:28d1f895c6fe 126 ((RMP) == HAL_REMAPDMA_USART3_DMA_CH32) || \
mbed_official 340:28d1f895c6fe 127 ((RMP) == HAL_REMAPDMA_I2C1_DMA_CH76) || \
mbed_official 340:28d1f895c6fe 128 ((RMP) == HAL_REMAPDMA_TIM1_DMA_CH6) || \
mbed_official 340:28d1f895c6fe 129 ((RMP) == HAL_REMAPDMA_TIM2_DMA_CH7) || \
mbed_official 340:28d1f895c6fe 130 ((RMP) == HAL_REMAPDMA_TIM3_DMA_CH6))
mbed_official 340:28d1f895c6fe 131 #else
mbed_official 340:28d1f895c6fe 132 #define IS_HAL_REMAPDMA(RMP) (((RMP) == HAL_REMAPDMA_ADC_DMA_CH2) || \
mbed_official 340:28d1f895c6fe 133 ((RMP) == HAL_REMAPDMA_USART1_TX_DMA_CH4) || \
mbed_official 340:28d1f895c6fe 134 ((RMP) == HAL_REMAPDMA_USART1_RX_DMA_CH5) || \
mbed_official 340:28d1f895c6fe 135 ((RMP) == HAL_REMAPDMA_TIM16_DMA_CH4) || \
mbed_official 340:28d1f895c6fe 136 ((RMP) == HAL_REMAPDMA_TIM17_DMA_CH2))
mbed_official 340:28d1f895c6fe 137 #endif
mbed_official 340:28d1f895c6fe 138 /**
mbed_official 340:28d1f895c6fe 139 * @}
mbed_official 340:28d1f895c6fe 140 */
mbed_official 340:28d1f895c6fe 141 #endif /* SYSCFG_CFGR1_DMA_RMP */
mbed_official 340:28d1f895c6fe 142
mbed_official 340:28d1f895c6fe 143 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
mbed_official 340:28d1f895c6fe 144 /** @defgroup HAL_Pin_remapping HAL Pin remapping
mbed_official 340:28d1f895c6fe 145 * @{
mbed_official 340:28d1f895c6fe 146 */
mbed_official 340:28d1f895c6fe 147 #define HAL_REMAP_PA11_PA12 (SYSCFG_CFGR1_PA11_PA12_RMP) /*!< PA11 and PA12 remapping bit for small packages (28 and 20 pins).
mbed_official 340:28d1f895c6fe 148 0: No remap (pin pair PA9/10 mapped on the pins)
mbed_official 340:28d1f895c6fe 149 1: Remap (pin pair PA11/12 mapped instead of PA9/10) */
mbed_official 340:28d1f895c6fe 150
mbed_official 340:28d1f895c6fe 151 #define IS_HAL_REMAP_PIN(RMP) ((RMP) == HAL_REMAP_PA11_PA12)
mbed_official 340:28d1f895c6fe 152 /**
mbed_official 340:28d1f895c6fe 153 * @}
mbed_official 340:28d1f895c6fe 154 */
mbed_official 340:28d1f895c6fe 155 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
mbed_official 340:28d1f895c6fe 156
mbed_official 340:28d1f895c6fe 157 #if defined(STM32F091xC)
mbed_official 340:28d1f895c6fe 158 /** @defgroup HAL_IRDA_ENV_SEL HAL IRDA Enveloppe Selection
mbed_official 340:28d1f895c6fe 159 * @{
mbed_official 340:28d1f895c6fe 160 */
mbed_official 340:28d1f895c6fe 161 #define HAL_SYSCFG_IRDA_ENV_SEL_TIM16 (SYSCFG_CFGR1_IRDA_ENV_SEL_0 & SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 00: Timer16 is selected as IRDA Modulation enveloppe source */
mbed_official 340:28d1f895c6fe 162 #define HAL_SYSCFG_IRDA_ENV_SEL_USART1 (SYSCFG_CFGR1_IRDA_ENV_SEL_0) /* 01: USART1 is selected as IRDA Modulation enveloppe source */
mbed_official 340:28d1f895c6fe 163 #define HAL_SYSCFG_IRDA_ENV_SEL_USART4 (SYSCFG_CFGR1_IRDA_ENV_SEL_1) /* 10: USART4 is selected as IRDA Modulation enveloppe source */
mbed_official 340:28d1f895c6fe 164
mbed_official 340:28d1f895c6fe 165 #define IS_HAL_SYSCFG_IRDA_ENV_SEL(SEL) (((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_TIM16) || \
mbed_official 340:28d1f895c6fe 166 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART1) || \
mbed_official 340:28d1f895c6fe 167 ((SEL) == HAL_SYSCFG_IRDA_ENV_SEL_USART4))
mbed_official 340:28d1f895c6fe 168 /**
mbed_official 340:28d1f895c6fe 169 * @}
mbed_official 340:28d1f895c6fe 170 */
mbed_official 340:28d1f895c6fe 171 #endif /* STM32F091xC */
mbed_official 340:28d1f895c6fe 172
mbed_official 340:28d1f895c6fe 173
mbed_official 340:28d1f895c6fe 174 /** @defgroup HAL_FastModePlus_I2C HAL FastModePlus I2C
mbed_official 340:28d1f895c6fe 175 * @{
mbed_official 340:28d1f895c6fe 176 */
mbed_official 340:28d1f895c6fe 177 #if defined(SYSCFG_CFGR1_I2C_FMP_PB6)
mbed_official 340:28d1f895c6fe 178 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 (SYSCFG_CFGR1_I2C_FMP_PB6) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
mbed_official 340:28d1f895c6fe 179 0: PB6 pin operates in standard mode
mbed_official 340:28d1f895c6fe 180 1: I2C FM+ mode enabled on PB6 pin, and the Speed control is bypassed */
mbed_official 340:28d1f895c6fe 181 #endif /* SYSCFG_CFGR1_I2C_FMP_PB6 */
mbed_official 340:28d1f895c6fe 182
mbed_official 340:28d1f895c6fe 183 #if defined(SYSCFG_CFGR1_I2C_FMP_PB7)
mbed_official 340:28d1f895c6fe 184 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB7 (SYSCFG_CFGR1_I2C_FMP_PB7) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
mbed_official 340:28d1f895c6fe 185 0: PB7 pin operates in standard mode
mbed_official 340:28d1f895c6fe 186 1: I2C FM+ mode enabled on PB7 pin, and the Speed control is bypassed */
mbed_official 340:28d1f895c6fe 187 #endif /* SYSCFG_CFGR1_I2C_FMP_PB7 */
mbed_official 340:28d1f895c6fe 188
mbed_official 340:28d1f895c6fe 189 #if defined(SYSCFG_CFGR1_I2C_FMP_PB8)
mbed_official 340:28d1f895c6fe 190 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB8 (SYSCFG_CFGR1_I2C_FMP_PB8) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
mbed_official 340:28d1f895c6fe 191 0: PB8 pin operates in standard mode
mbed_official 340:28d1f895c6fe 192 1: I2C FM+ mode enabled on PB8 pin, and the Speed control is bypassed */
mbed_official 340:28d1f895c6fe 193 #endif /* SYSCFG_CFGR1_I2C_FMP_PB8 */
mbed_official 340:28d1f895c6fe 194
mbed_official 340:28d1f895c6fe 195 #if defined(SYSCFG_CFGR1_I2C_FMP_PB9)
mbed_official 340:28d1f895c6fe 196 #define HAL_SYSCFG_FASTMODEPLUS_I2C_PB9 (SYSCFG_CFGR1_I2C_FMP_PB9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
mbed_official 340:28d1f895c6fe 197 0: PB9 pin operates in standard mode
mbed_official 340:28d1f895c6fe 198 1: I2C FM+ mode enabled on PB9 pin, and the Speed control is bypassed */
mbed_official 340:28d1f895c6fe 199 #endif /* SYSCFG_CFGR1_I2C_FMP_PB9 */
mbed_official 340:28d1f895c6fe 200
mbed_official 340:28d1f895c6fe 201 #if defined(SYSCFG_CFGR1_I2C_FMP_I2C1)
mbed_official 340:28d1f895c6fe 202 #define HAL_SYSCFG_FASTMODEPLUS_I2C1 (SYSCFG_CFGR1_I2C_FMP_I2C1) /*!< I2C1 fast mode Plus driving capability activation
mbed_official 340:28d1f895c6fe 203 0: FM+ mode is not enabled on I2C1 pins selected through AF selection bits
mbed_official 340:28d1f895c6fe 204 1: FM+ mode is enabled on I2C1 pins selected through AF selection bits */
mbed_official 340:28d1f895c6fe 205 #endif /* SYSCFG_CFGR1_I2C_FMP_I2C1 */
mbed_official 340:28d1f895c6fe 206
mbed_official 340:28d1f895c6fe 207 #if defined(SYSCFG_CFGR1_I2C_FMP_I2C2)
mbed_official 340:28d1f895c6fe 208 #define HAL_SYSCFG_FASTMODEPLUS_I2C2 (SYSCFG_CFGR1_I2C_FMP_I2C2) /*!< I2C2 fast mode Plus driving capability activation
mbed_official 340:28d1f895c6fe 209 0: FM+ mode is not enabled on I2C2 pins selected through AF selection bits
mbed_official 340:28d1f895c6fe 210 1: FM+ mode is enabled on I2C2 pins selected through AF selection bits */
mbed_official 340:28d1f895c6fe 211 #endif /* SYSCFG_CFGR1_I2C_FMP_I2C2 */
mbed_official 340:28d1f895c6fe 212
mbed_official 340:28d1f895c6fe 213 #if defined(SYSCFG_CFGR1_I2C_FMP_PA9)
mbed_official 340:28d1f895c6fe 214 #define HAL_SYSCFG_FASTMODEPLUS_I2C2_PA9 (SYSCFG_CFGR1_I2C_FMP_PA9) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
mbed_official 340:28d1f895c6fe 215 0: PA9 pin operates in standard mode
mbed_official 340:28d1f895c6fe 216 1: FM+ mode is enabled on PA9 pin, and the Speed control is bypassed */
mbed_official 340:28d1f895c6fe 217 #endif /* SYSCFG_CFGR1_I2C_FMP_PA9 */
mbed_official 340:28d1f895c6fe 218
mbed_official 340:28d1f895c6fe 219 #if defined(SYSCFG_CFGR1_I2C_FMP_PA10)
mbed_official 340:28d1f895c6fe 220 #define HAL_SYSCFG_FASTMODEPLUS_I2C2_PA10 (SYSCFG_CFGR1_I2C_FMP_PA10) /*!< Fast Mode Plus (FM+) driving capability activation on the pad
mbed_official 340:28d1f895c6fe 221 0: PA10 pin operates in standard mode
mbed_official 340:28d1f895c6fe 222 1: FM+ mode is enabled on PA10 pin, and the Speed control is bypassed */
mbed_official 340:28d1f895c6fe 223 #endif /* SYSCFG_CFGR1_I2C_FMP_PA10 */
mbed_official 340:28d1f895c6fe 224
mbed_official 340:28d1f895c6fe 225 #if defined(STM32F091xC)|| defined(STM32F098xx)
mbed_official 340:28d1f895c6fe 226 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
mbed_official 340:28d1f895c6fe 227 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
mbed_official 340:28d1f895c6fe 228 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA9) || \
mbed_official 340:28d1f895c6fe 229 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA10) || \
mbed_official 340:28d1f895c6fe 230 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
mbed_official 340:28d1f895c6fe 231 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
mbed_official 340:28d1f895c6fe 232 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
mbed_official 340:28d1f895c6fe 233 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
mbed_official 340:28d1f895c6fe 234 #elif defined(STM32F071xB) || defined(STM32F072xB) || defined(STM32F078xx)
mbed_official 340:28d1f895c6fe 235 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
mbed_official 340:28d1f895c6fe 236 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2) || \
mbed_official 340:28d1f895c6fe 237 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
mbed_official 340:28d1f895c6fe 238 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
mbed_official 340:28d1f895c6fe 239 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
mbed_official 340:28d1f895c6fe 240 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
mbed_official 340:28d1f895c6fe 241 #elif defined(STM32F030x6) || defined(STM32F031x6) || defined(STM32F038xx)
mbed_official 340:28d1f895c6fe 242 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
mbed_official 340:28d1f895c6fe 243 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA9) || \
mbed_official 340:28d1f895c6fe 244 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C2_PA10) || \
mbed_official 340:28d1f895c6fe 245 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
mbed_official 340:28d1f895c6fe 246 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
mbed_official 340:28d1f895c6fe 247 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
mbed_official 340:28d1f895c6fe 248 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
mbed_official 340:28d1f895c6fe 249 #elif defined(STM32F042x6) || defined(STM32F048xx)
mbed_official 340:28d1f895c6fe 250 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C1) || \
mbed_official 340:28d1f895c6fe 251 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
mbed_official 340:28d1f895c6fe 252 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
mbed_official 340:28d1f895c6fe 253 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
mbed_official 340:28d1f895c6fe 254 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
mbed_official 340:28d1f895c6fe 255 #else
mbed_official 340:28d1f895c6fe 256 #define IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG(CONFIG) (((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB6) || \
mbed_official 340:28d1f895c6fe 257 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB7) || \
mbed_official 340:28d1f895c6fe 258 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB8) || \
mbed_official 340:28d1f895c6fe 259 ((CONFIG) == HAL_SYSCFG_FASTMODEPLUS_I2C_PB9))
mbed_official 340:28d1f895c6fe 260 #endif
mbed_official 340:28d1f895c6fe 261
mbed_official 340:28d1f895c6fe 262 /**
mbed_official 340:28d1f895c6fe 263 * @}
mbed_official 340:28d1f895c6fe 264 */
mbed_official 340:28d1f895c6fe 265
mbed_official 340:28d1f895c6fe 266 #if defined(STM32F091xC) || defined (STM32F098xx)
mbed_official 340:28d1f895c6fe 267 /** @defgroup HAL_ISR_Wrapper HAL ISR Wrapper
mbed_official 340:28d1f895c6fe 268 * @{
mbed_official 340:28d1f895c6fe 269 */
mbed_official 340:28d1f895c6fe 270 #define HAL_SYSCFG_ITLINE0 ((uint32_t) 0x00000000)
mbed_official 340:28d1f895c6fe 271 #define HAL_SYSCFG_ITLINE1 ((uint32_t) 0x00000001)
mbed_official 340:28d1f895c6fe 272 #define HAL_SYSCFG_ITLINE2 ((uint32_t) 0x00000002)
mbed_official 340:28d1f895c6fe 273 #define HAL_SYSCFG_ITLINE3 ((uint32_t) 0x00000003)
mbed_official 340:28d1f895c6fe 274 #define HAL_SYSCFG_ITLINE4 ((uint32_t) 0x00000004)
mbed_official 340:28d1f895c6fe 275 #define HAL_SYSCFG_ITLINE5 ((uint32_t) 0x00000005)
mbed_official 340:28d1f895c6fe 276 #define HAL_SYSCFG_ITLINE6 ((uint32_t) 0x00000006)
mbed_official 340:28d1f895c6fe 277 #define HAL_SYSCFG_ITLINE7 ((uint32_t) 0x00000007)
mbed_official 340:28d1f895c6fe 278 #define HAL_SYSCFG_ITLINE8 ((uint32_t) 0x00000008)
mbed_official 340:28d1f895c6fe 279 #define HAL_SYSCFG_ITLINE9 ((uint32_t) 0x00000009)
mbed_official 340:28d1f895c6fe 280 #define HAL_SYSCFG_ITLINE10 ((uint32_t) 0x0000000A)
mbed_official 340:28d1f895c6fe 281 #define HAL_SYSCFG_ITLINE11 ((uint32_t) 0x0000000B)
mbed_official 340:28d1f895c6fe 282 #define HAL_SYSCFG_ITLINE12 ((uint32_t) 0x0000000C)
mbed_official 340:28d1f895c6fe 283 #define HAL_SYSCFG_ITLINE13 ((uint32_t) 0x0000000D)
mbed_official 340:28d1f895c6fe 284 #define HAL_SYSCFG_ITLINE14 ((uint32_t) 0x0000000E)
mbed_official 340:28d1f895c6fe 285 #define HAL_SYSCFG_ITLINE15 ((uint32_t) 0x0000000F)
mbed_official 340:28d1f895c6fe 286 #define HAL_SYSCFG_ITLINE16 ((uint32_t) 0x00000010)
mbed_official 340:28d1f895c6fe 287 #define HAL_SYSCFG_ITLINE17 ((uint32_t) 0x00000011)
mbed_official 340:28d1f895c6fe 288 #define HAL_SYSCFG_ITLINE18 ((uint32_t) 0x00000012)
mbed_official 340:28d1f895c6fe 289 #define HAL_SYSCFG_ITLINE19 ((uint32_t) 0x00000013)
mbed_official 340:28d1f895c6fe 290 #define HAL_SYSCFG_ITLINE20 ((uint32_t) 0x00000014)
mbed_official 340:28d1f895c6fe 291 #define HAL_SYSCFG_ITLINE21 ((uint32_t) 0x00000015)
mbed_official 340:28d1f895c6fe 292 #define HAL_SYSCFG_ITLINE22 ((uint32_t) 0x00000016)
mbed_official 340:28d1f895c6fe 293 #define HAL_SYSCFG_ITLINE23 ((uint32_t) 0x00000017)
mbed_official 340:28d1f895c6fe 294 #define HAL_SYSCFG_ITLINE24 ((uint32_t) 0x00000018)
mbed_official 340:28d1f895c6fe 295 #define HAL_SYSCFG_ITLINE25 ((uint32_t) 0x00000019)
mbed_official 340:28d1f895c6fe 296 #define HAL_SYSCFG_ITLINE26 ((uint32_t) 0x0000001A)
mbed_official 340:28d1f895c6fe 297 #define HAL_SYSCFG_ITLINE27 ((uint32_t) 0x0000001B)
mbed_official 340:28d1f895c6fe 298 #define HAL_SYSCFG_ITLINE28 ((uint32_t) 0x0000001C)
mbed_official 340:28d1f895c6fe 299 #define HAL_SYSCFG_ITLINE29 ((uint32_t) 0x0000001D)
mbed_official 340:28d1f895c6fe 300 #define HAL_SYSCFG_ITLINE30 ((uint32_t) 0x0000001E)
mbed_official 340:28d1f895c6fe 301 #define HAL_SYSCFG_ITLINE31 ((uint32_t) 0x0000001F)
mbed_official 340:28d1f895c6fe 302
mbed_official 340:28d1f895c6fe 303 #define HAL_ITLINE_EWDG ((uint32_t) ((HAL_SYSCFG_ITLINE0 << 0x18) | SYSCFG_ITLINE0_SR_EWDG)) /* EWDG has expired .... */
mbed_official 340:28d1f895c6fe 304 #if defined(STM32F091xC)
mbed_official 340:28d1f895c6fe 305 #define HAL_ITLINE_PVDOUT ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_PVDOUT)) /* Power voltage detection Interrupt .... */
mbed_official 340:28d1f895c6fe 306 #endif
mbed_official 340:28d1f895c6fe 307 #define HAL_ITLINE_VDDIO2 ((uint32_t) ((HAL_SYSCFG_ITLINE1 << 0x18) | SYSCFG_ITLINE1_SR_VDDIO2)) /* VDDIO2 Interrupt .... */
mbed_official 340:28d1f895c6fe 308 #define HAL_ITLINE_RTC_WAKEUP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_WAKEUP)) /* RTC WAKEUP -> exti[20] Interrupt */
mbed_official 340:28d1f895c6fe 309 #define HAL_ITLINE_RTC_TSTAMP ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_TSTAMP)) /* RTC Time Stamp -> exti[19] interrupt */
mbed_official 340:28d1f895c6fe 310 #define HAL_ITLINE_RTC_ALRA ((uint32_t) ((HAL_SYSCFG_ITLINE2 << 0x18) | SYSCFG_ITLINE2_SR_RTC_ALRA)) /* RTC Alarm -> exti[17] interrupt .... */
mbed_official 340:28d1f895c6fe 311 #define HAL_ITLINE_FLASH_ITF ((uint32_t) ((HAL_SYSCFG_ITLINE3 << 0x18) | SYSCFG_ITLINE3_SR_FLASH_ITF)) /* Flash ITF Interrupt */
mbed_official 340:28d1f895c6fe 312 #define HAL_ITLINE_CRS ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CRS)) /* CRS Interrupt */
mbed_official 340:28d1f895c6fe 313 #define HAL_ITLINE_CLK_CTRL ((uint32_t) ((HAL_SYSCFG_ITLINE4 << 0x18) | SYSCFG_ITLINE4_SR_CLK_CTRL)) /* CLK Control Interrupt */
mbed_official 340:28d1f895c6fe 314 #define HAL_ITLINE_EXTI0 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI0)) /* External Interrupt 0 */
mbed_official 340:28d1f895c6fe 315 #define HAL_ITLINE_EXTI1 ((uint32_t) ((HAL_SYSCFG_ITLINE5 << 0x18) | SYSCFG_ITLINE5_SR_EXTI1)) /* External Interrupt 1 */
mbed_official 340:28d1f895c6fe 316 #define HAL_ITLINE_EXTI2 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI2)) /* External Interrupt 2 */
mbed_official 340:28d1f895c6fe 317 #define HAL_ITLINE_EXTI3 ((uint32_t) ((HAL_SYSCFG_ITLINE6 << 0x18) | SYSCFG_ITLINE6_SR_EXTI3)) /* External Interrupt 3 */
mbed_official 340:28d1f895c6fe 318 #define HAL_ITLINE_EXTI4 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI4)) /* EXTI4 Interrupt */
mbed_official 340:28d1f895c6fe 319 #define HAL_ITLINE_EXTI5 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI5)) /* EXTI5 Interrupt */
mbed_official 340:28d1f895c6fe 320 #define HAL_ITLINE_EXTI6 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI6)) /* EXTI6 Interrupt */
mbed_official 340:28d1f895c6fe 321 #define HAL_ITLINE_EXTI7 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI7)) /* EXTI7 Interrupt */
mbed_official 340:28d1f895c6fe 322 #define HAL_ITLINE_EXTI8 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI8)) /* EXTI8 Interrupt */
mbed_official 340:28d1f895c6fe 323 #define HAL_ITLINE_EXTI9 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI9)) /* EXTI9 Interrupt */
mbed_official 340:28d1f895c6fe 324 #define HAL_ITLINE_EXTI10 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI10)) /* EXTI10 Interrupt */
mbed_official 340:28d1f895c6fe 325 #define HAL_ITLINE_EXTI11 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI11)) /* EXTI11 Interrupt */
mbed_official 340:28d1f895c6fe 326 #define HAL_ITLINE_EXTI12 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI12)) /* EXTI12 Interrupt */
mbed_official 340:28d1f895c6fe 327 #define HAL_ITLINE_EXTI13 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI13)) /* EXTI13 Interrupt */
mbed_official 340:28d1f895c6fe 328 #define HAL_ITLINE_EXTI14 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI14)) /* EXTI14 Interrupt */
mbed_official 340:28d1f895c6fe 329 #define HAL_ITLINE_EXTI15 ((uint32_t) ((HAL_SYSCFG_ITLINE7 << 0x18) | SYSCFG_ITLINE7_SR_EXTI15)) /* EXTI15 Interrupt */
mbed_official 340:28d1f895c6fe 330 #define HAL_ITLINE_TSC_EOA ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_EOA)) /* Touch control EOA Interrupt */
mbed_official 340:28d1f895c6fe 331 #define HAL_ITLINE_TSC_MCE ((uint32_t) ((HAL_SYSCFG_ITLINE8 << 0x18) | SYSCFG_ITLINE8_SR_TSC_MCE)) /* Touch control MCE Interrupt */
mbed_official 340:28d1f895c6fe 332 #define HAL_ITLINE_DMA1_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE9 << 0x18) | SYSCFG_ITLINE9_SR_DMA1_CH1)) /* DMA1 Channel 1 Interrupt */
mbed_official 340:28d1f895c6fe 333 #define HAL_ITLINE_DMA1_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH2)) /* DMA1 Channel 2 Interrupt */
mbed_official 340:28d1f895c6fe 334 #define HAL_ITLINE_DMA1_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA1_CH3)) /* DMA1 Channel 3 Interrupt */
mbed_official 340:28d1f895c6fe 335 #define HAL_ITLINE_DMA2_CH1 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH1)) /* DMA2 Channel 1 Interrupt */
mbed_official 340:28d1f895c6fe 336 #define HAL_ITLINE_DMA2_CH2 ((uint32_t) ((HAL_SYSCFG_ITLINE10 << 0x18) | SYSCFG_ITLINE10_SR_DMA2_CH2)) /* DMA2 Channel 2 Interrupt */
mbed_official 340:28d1f895c6fe 337 #define HAL_ITLINE_DMA1_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH4)) /* DMA1 Channel 4 Interrupt */
mbed_official 340:28d1f895c6fe 338 #define HAL_ITLINE_DMA1_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH5)) /* DMA1 Channel 5 Interrupt */
mbed_official 340:28d1f895c6fe 339 #define HAL_ITLINE_DMA1_CH6 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH6)) /* DMA1 Channel 6 Interrupt */
mbed_official 340:28d1f895c6fe 340 #define HAL_ITLINE_DMA1_CH7 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA1_CH7)) /* DMA1 Channel 7 Interrupt */
mbed_official 340:28d1f895c6fe 341 #define HAL_ITLINE_DMA2_CH3 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH3)) /* DMA2 Channel 3 Interrupt */
mbed_official 340:28d1f895c6fe 342 #define HAL_ITLINE_DMA2_CH4 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH4)) /* DMA2 Channel 4 Interrupt */
mbed_official 340:28d1f895c6fe 343 #define HAL_ITLINE_DMA2_CH5 ((uint32_t) ((HAL_SYSCFG_ITLINE11 << 0x18) | SYSCFG_ITLINE11_SR_DMA2_CH5)) /* DMA2 Channel 5 Interrupt */
mbed_official 340:28d1f895c6fe 344 #define HAL_ITLINE_ADC ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_ADC)) /* ADC Interrupt */
mbed_official 340:28d1f895c6fe 345 #define HAL_ITLINE_COMP1 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP1)) /* COMP1 Interrupt -> exti[21] */
mbed_official 340:28d1f895c6fe 346 #define HAL_ITLINE_COMP2 ((uint32_t) ((HAL_SYSCFG_ITLINE12 << 0x18) | SYSCFG_ITLINE12_SR_COMP2)) /* COMP2 Interrupt -> exti[21] */
mbed_official 340:28d1f895c6fe 347 #define HAL_ITLINE_TIM1_BRK ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_BRK)) /* TIM1 BRK Interrupt */
mbed_official 340:28d1f895c6fe 348 #define HAL_ITLINE_TIM1_UPD ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_UPD)) /* TIM1 UPD Interrupt */
mbed_official 340:28d1f895c6fe 349 #define HAL_ITLINE_TIM1_TRG ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_TRG)) /* TIM1 TRG Interrupt */
mbed_official 340:28d1f895c6fe 350 #define HAL_ITLINE_TIM1_CCU ((uint32_t) ((HAL_SYSCFG_ITLINE13 << 0x18) | SYSCFG_ITLINE13_SR_TIM1_CCU)) /* TIM1 CCU Interrupt */
mbed_official 340:28d1f895c6fe 351 #define HAL_ITLINE_TIM1_CC ((uint32_t) ((HAL_SYSCFG_ITLINE14 << 0x18) | SYSCFG_ITLINE14_SR_TIM1_CC)) /* TIM1 CC Interrupt */
mbed_official 340:28d1f895c6fe 352 #define HAL_ITLINE_TIM2 ((uint32_t) ((HAL_SYSCFG_ITLINE15 << 0x18) | SYSCFG_ITLINE15_SR_TIM2_GLB)) /* TIM2 Interrupt */
mbed_official 340:28d1f895c6fe 353 #define HAL_ITLINE_TIM3 ((uint32_t) ((HAL_SYSCFG_ITLINE16 << 0x18) | SYSCFG_ITLINE16_SR_TIM3_GLB)) /* TIM3 Interrupt */
mbed_official 340:28d1f895c6fe 354 #define HAL_ITLINE_DAC ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_DAC)) /* DAC Interrupt */
mbed_official 340:28d1f895c6fe 355 #define HAL_ITLINE_TIM6 ((uint32_t) ((HAL_SYSCFG_ITLINE17 << 0x18) | SYSCFG_ITLINE17_SR_TIM6_GLB)) /* TIM6 Interrupt */
mbed_official 340:28d1f895c6fe 356 #define HAL_ITLINE_TIM7 ((uint32_t) ((HAL_SYSCFG_ITLINE18 << 0x18) | SYSCFG_ITLINE18_SR_TIM7_GLB)) /* TIM7 Interrupt */
mbed_official 340:28d1f895c6fe 357 #define HAL_ITLINE_TIM14 ((uint32_t) ((HAL_SYSCFG_ITLINE19 << 0x18) | SYSCFG_ITLINE19_SR_TIM14_GLB)) /* TIM14 Interrupt */
mbed_official 340:28d1f895c6fe 358 #define HAL_ITLINE_TIM15 ((uint32_t) ((HAL_SYSCFG_ITLINE20 << 0x18) | SYSCFG_ITLINE20_SR_TIM15_GLB)) /* TIM15 Interrupt */
mbed_official 340:28d1f895c6fe 359 #define HAL_ITLINE_TIM16 ((uint32_t) ((HAL_SYSCFG_ITLINE21 << 0x18) | SYSCFG_ITLINE21_SR_TIM16_GLB)) /* TIM16 Interrupt */
mbed_official 340:28d1f895c6fe 360 #define HAL_ITLINE_TIM17 ((uint32_t) ((HAL_SYSCFG_ITLINE22 << 0x18) | SYSCFG_ITLINE22_SR_TIM17_GLB)) /* TIM17 Interrupt */
mbed_official 340:28d1f895c6fe 361 #define HAL_ITLINE_I2C1 ((uint32_t) ((HAL_SYSCFG_ITLINE23 << 0x18) | SYSCFG_ITLINE23_SR_I2C1_GLB)) /* I2C1 Interrupt -> exti[23] */
mbed_official 340:28d1f895c6fe 362 #define HAL_ITLINE_I2C2 ((uint32_t) ((HAL_SYSCFG_ITLINE24 << 0x18) | SYSCFG_ITLINE24_SR_I2C2_GLB)) /* I2C2 Interrupt */
mbed_official 340:28d1f895c6fe 363 #define HAL_ITLINE_SPI1 ((uint32_t) ((HAL_SYSCFG_ITLINE25 << 0x18) | SYSCFG_ITLINE25_SR_SPI1)) /* I2C1 Interrupt -> exti[23] */
mbed_official 340:28d1f895c6fe 364 #define HAL_ITLINE_SPI2 ((uint32_t) ((HAL_SYSCFG_ITLINE26 << 0x18) | SYSCFG_ITLINE26_SR_SPI2)) /* SPI1 Interrupt */
mbed_official 340:28d1f895c6fe 365 #define HAL_ITLINE_USART1 ((uint32_t) ((HAL_SYSCFG_ITLINE27 << 0x18) | SYSCFG_ITLINE27_SR_USART1_GLB)) /*!< USART1 GLB Interrupt -> exti[25] */
mbed_official 340:28d1f895c6fe 366 #define HAL_ITLINE_USART2 ((uint32_t) ((HAL_SYSCFG_ITLINE28 << 0x18) | SYSCFG_ITLINE28_SR_USART2_GLB)) /*!< USART2 GLB Interrupt -> exti[26] */
mbed_official 340:28d1f895c6fe 367 #define HAL_ITLINE_USART3 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART3_GLB)) /* USART3 Interrupt .... */
mbed_official 340:28d1f895c6fe 368 #define HAL_ITLINE_USART4 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART4_GLB)) /* USART4 Interrupt .... */
mbed_official 340:28d1f895c6fe 369 #define HAL_ITLINE_USART5 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART5_GLB)) /* USART5 Interrupt .... */
mbed_official 340:28d1f895c6fe 370 #define HAL_ITLINE_USART6 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART6_GLB)) /* USART6 Interrupt .... */
mbed_official 340:28d1f895c6fe 371 #define HAL_ITLINE_USART7 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART7_GLB)) /* USART7 Interrupt .... */
mbed_official 340:28d1f895c6fe 372 #define HAL_ITLINE_USART8 ((uint32_t) ((HAL_SYSCFG_ITLINE29 << 0x18) | SYSCFG_ITLINE29_SR_USART8_GLB)) /* USART8 Interrupt .... */
mbed_official 340:28d1f895c6fe 373 #define HAL_ITLINE_CAN ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CAN)) /* CAN Interrupt */
mbed_official 340:28d1f895c6fe 374 #define HAL_ITLINE_CEC ((uint32_t) ((HAL_SYSCFG_ITLINE30 << 0x18) | SYSCFG_ITLINE30_SR_CEC)) /* CEC Interrupt -> exti[27] */
mbed_official 340:28d1f895c6fe 375 /**
mbed_official 340:28d1f895c6fe 376 * @}
mbed_official 340:28d1f895c6fe 377 */
mbed_official 340:28d1f895c6fe 378 #endif /* STM32F091xC || STM32F098xx */
mbed_official 340:28d1f895c6fe 379
mbed_official 340:28d1f895c6fe 380 /**
mbed_official 340:28d1f895c6fe 381 * @}
mbed_official 340:28d1f895c6fe 382 */
mbed_official 340:28d1f895c6fe 383
mbed_official 340:28d1f895c6fe 384 /* Exported macros -----------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 385 /** @defgroup HAL_Exported_Macros HAL Exported Macros
mbed_official 340:28d1f895c6fe 386 * @{
mbed_official 340:28d1f895c6fe 387 */
mbed_official 340:28d1f895c6fe 388
mbed_official 340:28d1f895c6fe 389 /** @defgroup HAL_Freeze_Unfreeze_Peripherals HAL Freeze Unfreeze Peripherals
mbed_official 340:28d1f895c6fe 390 * @brief Freeze/Unfreeze Peripherals in Debug mode
mbed_official 340:28d1f895c6fe 391 * @{
mbed_official 340:28d1f895c6fe 392 */
mbed_official 340:28d1f895c6fe 393
mbed_official 340:28d1f895c6fe 394 #if defined(DBGMCU_APB1_FZ_DBG_CAN_STOP)
mbed_official 340:28d1f895c6fe 395 #define __HAL_FREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_CAN_STOP))
mbed_official 340:28d1f895c6fe 396 #define __HAL_UNFREEZE_CAN_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_CAN_STOP))
mbed_official 340:28d1f895c6fe 397 #endif /* DBGMCU_APB1_FZ_DBG_CAN_STOP */
mbed_official 340:28d1f895c6fe 398
mbed_official 340:28d1f895c6fe 399 #if defined(DBGMCU_APB1_FZ_DBG_RTC_STOP)
mbed_official 340:28d1f895c6fe 400 #define __HAL_FREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_RTC_STOP))
mbed_official 340:28d1f895c6fe 401 #define __HAL_UNFREEZE_RTC_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_RTC_STOP))
mbed_official 340:28d1f895c6fe 402 #endif /* DBGMCU_APB1_FZ_DBG_RTC_STOP */
mbed_official 340:28d1f895c6fe 403
mbed_official 340:28d1f895c6fe 404 #if defined(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT)
mbed_official 340:28d1f895c6fe 405 #define __HAL_FREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
mbed_official 340:28d1f895c6fe 406 #define __HAL_UNFREEZE_I2C1_TIMEOUT_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT))
mbed_official 340:28d1f895c6fe 407 #endif /* DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT */
mbed_official 340:28d1f895c6fe 408
mbed_official 340:28d1f895c6fe 409 #if defined(DBGMCU_APB1_FZ_DBG_IWDG_STOP)
mbed_official 340:28d1f895c6fe 410 #define __HAL_FREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_IWDG_STOP))
mbed_official 340:28d1f895c6fe 411 #define __HAL_UNFREEZE_IWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_IWDG_STOP))
mbed_official 340:28d1f895c6fe 412 #endif /* DBGMCU_APB1_FZ_DBG_IWDG_STOP */
mbed_official 340:28d1f895c6fe 413
mbed_official 340:28d1f895c6fe 414 #if defined(DBGMCU_APB1_FZ_DBG_WWDG_STOP)
mbed_official 340:28d1f895c6fe 415 #define __HAL_FREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_WWDG_STOP))
mbed_official 340:28d1f895c6fe 416 #define __HAL_UNFREEZE_WWDG_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_WWDG_STOP))
mbed_official 340:28d1f895c6fe 417 #endif /* DBGMCU_APB1_FZ_DBG_WWDG_STOP */
mbed_official 340:28d1f895c6fe 418
mbed_official 340:28d1f895c6fe 419 #if defined(DBGMCU_APB1_FZ_DBG_TIM2_STOP)
mbed_official 340:28d1f895c6fe 420 #define __HAL_FREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM2_STOP))
mbed_official 340:28d1f895c6fe 421 #define __HAL_UNFREEZE_TIM2_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM2_STOP))
mbed_official 340:28d1f895c6fe 422 #endif /* DBGMCU_APB1_FZ_DBG_TIM2_STOP */
mbed_official 340:28d1f895c6fe 423
mbed_official 340:28d1f895c6fe 424 #if defined(DBGMCU_APB1_FZ_DBG_TIM3_STOP)
mbed_official 340:28d1f895c6fe 425 #define __HAL_FREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM3_STOP))
mbed_official 340:28d1f895c6fe 426 #define __HAL_UNFREEZE_TIM3_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM3_STOP))
mbed_official 340:28d1f895c6fe 427 #endif /* DBGMCU_APB1_FZ_DBG_TIM3_STOP */
mbed_official 340:28d1f895c6fe 428
mbed_official 340:28d1f895c6fe 429 #if defined(DBGMCU_APB1_FZ_DBG_TIM6_STOP)
mbed_official 340:28d1f895c6fe 430 #define __HAL_FREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM6_STOP))
mbed_official 340:28d1f895c6fe 431 #define __HAL_UNFREEZE_TIM6_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM6_STOP))
mbed_official 340:28d1f895c6fe 432 #endif /* DBGMCU_APB1_FZ_DBG_TIM6_STOP */
mbed_official 340:28d1f895c6fe 433
mbed_official 340:28d1f895c6fe 434 #if defined(DBGMCU_APB1_FZ_DBG_TIM7_STOP)
mbed_official 340:28d1f895c6fe 435 #define __HAL_FREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM7_STOP))
mbed_official 340:28d1f895c6fe 436 #define __HAL_UNFREEZE_TIM7_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM7_STOP))
mbed_official 340:28d1f895c6fe 437 #endif /* DBGMCU_APB1_FZ_DBG_TIM7_STOP */
mbed_official 340:28d1f895c6fe 438
mbed_official 340:28d1f895c6fe 439 #if defined(DBGMCU_APB1_FZ_DBG_TIM14_STOP)
mbed_official 340:28d1f895c6fe 440 #define __HAL_FREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ |= (DBGMCU_APB1_FZ_DBG_TIM14_STOP))
mbed_official 340:28d1f895c6fe 441 #define __HAL_UNFREEZE_TIM14_DBGMCU() (DBGMCU->APB1FZ &= ~(DBGMCU_APB1_FZ_DBG_TIM14_STOP))
mbed_official 340:28d1f895c6fe 442 #endif /* DBGMCU_APB1_FZ_DBG_TIM14_STOP */
mbed_official 340:28d1f895c6fe 443
mbed_official 340:28d1f895c6fe 444 #if defined(DBGMCU_APB2_FZ_DBG_TIM1_STOP)
mbed_official 340:28d1f895c6fe 445 #define __HAL_FREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM1_STOP))
mbed_official 340:28d1f895c6fe 446 #define __HAL_UNFREEZE_TIM1_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM1_STOP))
mbed_official 340:28d1f895c6fe 447 #endif /* DBGMCU_APB2_FZ_DBG_TIM1_STOP */
mbed_official 340:28d1f895c6fe 448
mbed_official 340:28d1f895c6fe 449 #if defined(DBGMCU_APB2_FZ_DBG_TIM15_STOP)
mbed_official 340:28d1f895c6fe 450 #define __HAL_FREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM15_STOP))
mbed_official 340:28d1f895c6fe 451 #define __HAL_UNFREEZE_TIM15_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM15_STOP))
mbed_official 340:28d1f895c6fe 452 #endif /* DBGMCU_APB2_FZ_DBG_TIM15_STOP */
mbed_official 340:28d1f895c6fe 453
mbed_official 340:28d1f895c6fe 454 #if defined(DBGMCU_APB2_FZ_DBG_TIM16_STOP)
mbed_official 340:28d1f895c6fe 455 #define __HAL_FREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM16_STOP))
mbed_official 340:28d1f895c6fe 456 #define __HAL_UNFREEZE_TIM16_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM16_STOP))
mbed_official 340:28d1f895c6fe 457 #endif /* DBGMCU_APB2_FZ_DBG_TIM16_STOP */
mbed_official 340:28d1f895c6fe 458
mbed_official 340:28d1f895c6fe 459 #if defined(DBGMCU_APB2_FZ_DBG_TIM17_STOP)
mbed_official 340:28d1f895c6fe 460 #define __HAL_FREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ |= (DBGMCU_APB2_FZ_DBG_TIM17_STOP))
mbed_official 340:28d1f895c6fe 461 #define __HAL_UNFREEZE_TIM17_DBGMCU() (DBGMCU->APB2FZ &= ~(DBGMCU_APB2_FZ_DBG_TIM17_STOP))
mbed_official 340:28d1f895c6fe 462 #endif /* DBGMCU_APB2_FZ_DBG_TIM17_STOP */
mbed_official 340:28d1f895c6fe 463
mbed_official 340:28d1f895c6fe 464 /**
mbed_official 340:28d1f895c6fe 465 * @}
mbed_official 340:28d1f895c6fe 466 */
mbed_official 340:28d1f895c6fe 467
mbed_official 340:28d1f895c6fe 468 /** @defgroup Memory_Mapping_Selection Memory Mapping Selection
mbed_official 340:28d1f895c6fe 469 * @{
mbed_official 340:28d1f895c6fe 470 */
mbed_official 340:28d1f895c6fe 471 #if defined(SYSCFG_CFGR1_MEM_MODE)
mbed_official 340:28d1f895c6fe 472 /** @brief Main Flash memory mapped at 0x00000000
mbed_official 340:28d1f895c6fe 473 */
mbed_official 340:28d1f895c6fe 474 #define __HAL_REMAPMEMORY_FLASH() (SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE))
mbed_official 340:28d1f895c6fe 475 #endif /* SYSCFG_CFGR1_MEM_MODE */
mbed_official 340:28d1f895c6fe 476
mbed_official 340:28d1f895c6fe 477 #if defined(SYSCFG_CFGR1_MEM_MODE_0)
mbed_official 340:28d1f895c6fe 478 /** @brief System Flash memory mapped at 0x00000000
mbed_official 340:28d1f895c6fe 479 */
mbed_official 340:28d1f895c6fe 480 #define __HAL_REMAPMEMORY_SYSTEMFLASH() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
mbed_official 340:28d1f895c6fe 481 SYSCFG->CFGR1 |= SYSCFG_CFGR1_MEM_MODE_0; \
mbed_official 340:28d1f895c6fe 482 }while(0)
mbed_official 340:28d1f895c6fe 483 #endif /* SYSCFG_CFGR1_MEM_MODE_0 */
mbed_official 340:28d1f895c6fe 484
mbed_official 340:28d1f895c6fe 485 #if defined(SYSCFG_CFGR1_MEM_MODE_0) && defined(SYSCFG_CFGR1_MEM_MODE_1)
mbed_official 340:28d1f895c6fe 486 /** @brief Embedded SRAM mapped at 0x00000000
mbed_official 340:28d1f895c6fe 487 */
mbed_official 340:28d1f895c6fe 488 #define __HAL_REMAPMEMORY_SRAM() do {SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_MEM_MODE); \
mbed_official 340:28d1f895c6fe 489 SYSCFG->CFGR1 |= (SYSCFG_CFGR1_MEM_MODE_0 | SYSCFG_CFGR1_MEM_MODE_1); \
mbed_official 340:28d1f895c6fe 490 }while(0)
mbed_official 340:28d1f895c6fe 491 #endif /* SYSCFG_CFGR1_MEM_MODE_0 && SYSCFG_CFGR1_MEM_MODE_1 */
mbed_official 340:28d1f895c6fe 492 /**
mbed_official 340:28d1f895c6fe 493 * @}
mbed_official 340:28d1f895c6fe 494 */
mbed_official 340:28d1f895c6fe 495
mbed_official 340:28d1f895c6fe 496 #if defined(SYSCFG_CFGR1_DMA_RMP)
mbed_official 340:28d1f895c6fe 497 /** @defgroup HAL_DMA_remap HAL DMA remap
mbed_official 340:28d1f895c6fe 498 * @brief DMA remapping enable/disable macros
mbed_official 340:28d1f895c6fe 499 * @param __DMA_REMAP__: This parameter can be a value of @ref HAL_DMA_remapping
mbed_official 340:28d1f895c6fe 500 * @{
mbed_official 340:28d1f895c6fe 501 */
mbed_official 340:28d1f895c6fe 502 #define __HAL_REMAPDMA_CHANNEL_ENABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
mbed_official 340:28d1f895c6fe 503 SYSCFG->CFGR1 |= (__DMA_REMAP__); \
mbed_official 340:28d1f895c6fe 504 }while(0)
mbed_official 340:28d1f895c6fe 505 #define __HAL_REMAPDMA_CHANNEL_DISABLE(__DMA_REMAP__) do {assert_param(IS_HAL_REMAPDMA((__DMA_REMAP__))); \
mbed_official 340:28d1f895c6fe 506 SYSCFG->CFGR1 &= ~(__DMA_REMAP__); \
mbed_official 340:28d1f895c6fe 507 }while(0)
mbed_official 340:28d1f895c6fe 508 /**
mbed_official 340:28d1f895c6fe 509 * @}
mbed_official 340:28d1f895c6fe 510 */
mbed_official 340:28d1f895c6fe 511 #endif /* SYSCFG_CFGR1_DMA_RMP */
mbed_official 340:28d1f895c6fe 512
mbed_official 340:28d1f895c6fe 513 #if defined(SYSCFG_CFGR1_PA11_PA12_RMP)
mbed_official 340:28d1f895c6fe 514 /** @defgroup HAL_Pin_remap HAL Pin remap
mbed_official 340:28d1f895c6fe 515 * @brief Pin remapping enable/disable macros
mbed_official 340:28d1f895c6fe 516 * @param __PIN_REMAP__: This parameter can be a value of @ref HAL_Pin_remapping
mbed_official 340:28d1f895c6fe 517 * @{
mbed_official 340:28d1f895c6fe 518 */
mbed_official 340:28d1f895c6fe 519 #define __HAL_REMAP_PIN_ENABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
mbed_official 340:28d1f895c6fe 520 SYSCFG->CFGR1 |= (__PIN_REMAP__); \
mbed_official 340:28d1f895c6fe 521 }while(0)
mbed_official 340:28d1f895c6fe 522 #define __HAL_REMAP_PIN_DISABLE(__PIN_REMAP__) do {assert_param(IS_HAL_REMAP_PIN((__PIN_REMAP__))); \
mbed_official 340:28d1f895c6fe 523 SYSCFG->CFGR1 &= ~(__PIN_REMAP__); \
mbed_official 340:28d1f895c6fe 524 }while(0)
mbed_official 340:28d1f895c6fe 525 /**
mbed_official 340:28d1f895c6fe 526 * @}
mbed_official 340:28d1f895c6fe 527 */
mbed_official 340:28d1f895c6fe 528 #endif /* SYSCFG_CFGR1_PA11_PA12_RMP */
mbed_official 340:28d1f895c6fe 529
mbed_official 340:28d1f895c6fe 530 /** @defgroup HAL_Fast_mode_plus_driving_cap HAL Fast mode plus driving cap
mbed_official 340:28d1f895c6fe 531 * @brief Fast mode Plus driving capability enable/disable macros
mbed_official 340:28d1f895c6fe 532 * @param __FASTMODEPLUS__: This parameter can be a value of @ref HAL_FastModePlus_I2C
mbed_official 340:28d1f895c6fe 533 * @{
mbed_official 340:28d1f895c6fe 534 */
mbed_official 340:28d1f895c6fe 535 #define __HAL_SYSCFG_FASTMODEPLUS_ENABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
mbed_official 340:28d1f895c6fe 536 SYSCFG->CFGR1 |= (__FASTMODEPLUS__); \
mbed_official 340:28d1f895c6fe 537 }while(0)
mbed_official 340:28d1f895c6fe 538
mbed_official 340:28d1f895c6fe 539 #define __HAL_SYSCFG_FASTMODEPLUS_DISABLE(__FASTMODEPLUS__) do {assert_param(IS_HAL_SYSCFG_FASTMODEPLUS_CONFIG((__FASTMODEPLUS__))); \
mbed_official 340:28d1f895c6fe 540 SYSCFG->CFGR1 &= ~(__FASTMODEPLUS__); \
mbed_official 340:28d1f895c6fe 541 }while(0)
mbed_official 340:28d1f895c6fe 542 /**
mbed_official 340:28d1f895c6fe 543 * @}
mbed_official 340:28d1f895c6fe 544 */
mbed_official 340:28d1f895c6fe 545
mbed_official 340:28d1f895c6fe 546 #if defined(SYSCFG_CFGR2_LOCKUP_LOCK)
mbed_official 340:28d1f895c6fe 547 /** @defgroup Cortex_Lockup_Enable Cortex Lockup Enable
mbed_official 340:28d1f895c6fe 548 * @{
mbed_official 340:28d1f895c6fe 549 */
mbed_official 340:28d1f895c6fe 550 /** @brief SYSCFG Break Lockup lock
mbed_official 340:28d1f895c6fe 551 * Enables and locks the connection of Cortex-M0 LOCKUP (Hardfault) output to TIM1/15/16/17 Break input
mbed_official 340:28d1f895c6fe 552 * @note The selected configuration is locked and can be unlocked by system reset
mbed_official 340:28d1f895c6fe 553 */
mbed_official 340:28d1f895c6fe 554 #define __HAL_SYSCFG_BREAK_LOCKUP_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_LOCKUP_LOCK); \
mbed_official 340:28d1f895c6fe 555 SYSCFG->CFGR2 |= SYSCFG_CFGR2_LOCKUP_LOCK; \
mbed_official 340:28d1f895c6fe 556 }while(0)
mbed_official 340:28d1f895c6fe 557 /**
mbed_official 340:28d1f895c6fe 558 * @}
mbed_official 340:28d1f895c6fe 559 */
mbed_official 340:28d1f895c6fe 560 #endif /* SYSCFG_CFGR2_LOCKUP_LOCK */
mbed_official 340:28d1f895c6fe 561
mbed_official 340:28d1f895c6fe 562 #if defined(SYSCFG_CFGR2_PVD_LOCK)
mbed_official 340:28d1f895c6fe 563 /** @defgroup PVD_Lock_Enable PVD Lock
mbed_official 340:28d1f895c6fe 564 * @{
mbed_official 340:28d1f895c6fe 565 */
mbed_official 340:28d1f895c6fe 566 /** @brief SYSCFG Break PVD lock
mbed_official 340:28d1f895c6fe 567 * Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input, , as well as the PVDE and PLS[2:0] in the PWR_CR register
mbed_official 340:28d1f895c6fe 568 * @note The selected configuration is locked and can be unlocked by system reset
mbed_official 340:28d1f895c6fe 569 */
mbed_official 340:28d1f895c6fe 570 #define __HAL_SYSCFG_BREAK_PVD_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_PVD_LOCK); \
mbed_official 340:28d1f895c6fe 571 SYSCFG->CFGR2 |= SYSCFG_CFGR2_PVD_LOCK; \
mbed_official 340:28d1f895c6fe 572 }while(0)
mbed_official 340:28d1f895c6fe 573 /**
mbed_official 340:28d1f895c6fe 574 * @}
mbed_official 340:28d1f895c6fe 575 */
mbed_official 340:28d1f895c6fe 576 #endif /* SYSCFG_CFGR2_PVD_LOCK */
mbed_official 340:28d1f895c6fe 577
mbed_official 340:28d1f895c6fe 578 #if defined(SYSCFG_CFGR2_SRAM_PARITY_LOCK)
mbed_official 340:28d1f895c6fe 579 /** @defgroup SRAM_Parity_Lock SRAM Parity Lock
mbed_official 340:28d1f895c6fe 580 * @{
mbed_official 340:28d1f895c6fe 581 */
mbed_official 340:28d1f895c6fe 582 /** @brief SYSCFG Break SRAM PARITY lock
mbed_official 340:28d1f895c6fe 583 * Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17
mbed_official 340:28d1f895c6fe 584 * @note The selected configuration is locked and can be unlocked by system reset
mbed_official 340:28d1f895c6fe 585 */
mbed_official 340:28d1f895c6fe 586 #define __HAL_SYSCFG_BREAK_SRAMPARITY_LOCK() do {SYSCFG->CFGR2 &= ~(SYSCFG_CFGR2_SRAM_PARITY_LOCK); \
mbed_official 340:28d1f895c6fe 587 SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PARITY_LOCK; \
mbed_official 340:28d1f895c6fe 588 }while(0)
mbed_official 340:28d1f895c6fe 589 /**
mbed_official 340:28d1f895c6fe 590 * @}
mbed_official 340:28d1f895c6fe 591 */
mbed_official 340:28d1f895c6fe 592 #endif /* SYSCFG_CFGR2_SRAM_PARITY_LOCK */
mbed_official 340:28d1f895c6fe 593
mbed_official 340:28d1f895c6fe 594 #if defined(SYSCFG_CFGR2_SRAM_PEF)
mbed_official 340:28d1f895c6fe 595 /** @defgroup HAL_SYSCFG_Parity_check_on_RAM HAL SYSCFG Parity check on RAM
mbed_official 340:28d1f895c6fe 596 * @brief Parity check on RAM disable macro
mbed_official 340:28d1f895c6fe 597 * @note Disabling the parity check on RAM locks the configuration bit.
mbed_official 340:28d1f895c6fe 598 * To re-enable the parity check on RAM perform a system reset.
mbed_official 340:28d1f895c6fe 599 * @{
mbed_official 340:28d1f895c6fe 600 */
mbed_official 340:28d1f895c6fe 601 #define __HAL_SYSCFG_RAM_PARITYCHECK_DISABLE() (SYSCFG->CFGR2 |= SYSCFG_CFGR2_SRAM_PEF)
mbed_official 340:28d1f895c6fe 602 /**
mbed_official 340:28d1f895c6fe 603 * @}
mbed_official 340:28d1f895c6fe 604 */
mbed_official 340:28d1f895c6fe 605 #endif /* SYSCFG_CFGR2_SRAM_PEF */
mbed_official 340:28d1f895c6fe 606
mbed_official 340:28d1f895c6fe 607
mbed_official 340:28d1f895c6fe 608 #if defined(STM32F091xC) || defined (STM32F098xx)
mbed_official 340:28d1f895c6fe 609 /** @defgroup HAL_ISR_wrapper_check HAL ISR wrapper check
mbed_official 340:28d1f895c6fe 610 * @brief ISR wrapper check
mbed_official 340:28d1f895c6fe 611 * @note Allow to determine interrupt source per line.
mbed_official 340:28d1f895c6fe 612 * @{
mbed_official 340:28d1f895c6fe 613 */
mbed_official 340:28d1f895c6fe 614 #define __HAL_GET_PENDING_IT(__SOURCE__) (SYSCFG->IT_LINE_SR[((__SOURCE__) >> 0x18)] & ((__SOURCE__) & 0x00FFFFFF))
mbed_official 340:28d1f895c6fe 615 /**
mbed_official 340:28d1f895c6fe 616 * @}
mbed_official 340:28d1f895c6fe 617 */
mbed_official 340:28d1f895c6fe 618 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
mbed_official 340:28d1f895c6fe 619
mbed_official 340:28d1f895c6fe 620 #if defined(STM32F091xC) || defined (STM32F098xx)
mbed_official 340:28d1f895c6fe 621 /** @defgroup HAL_SYSCFG_IRDA_modulation_envelope_selection HAL SYSCFG IRDA modulation envelope selection
mbed_official 340:28d1f895c6fe 622 * @brief selection of the modulation envelope signal macro, using bits [7:6] of SYS_CTRL(CFGR1) register
mbed_official 340:28d1f895c6fe 623 * @param __SOURCE__: This parameter can be a value of @ref HAL_IRDA_ENV_SEL
mbed_official 340:28d1f895c6fe 624 * @{
mbed_official 340:28d1f895c6fe 625 */
mbed_official 340:28d1f895c6fe 626 #define __HAL_SYSCFG_IRDA_ENV_SELECTION(__SOURCE__) do {assert_param(IS_HAL_SYSCFG_IRDA_ENV_SEL((__SOURCE__))); \
mbed_official 340:28d1f895c6fe 627 SYSCFG->CFGR1 &= ~(SYSCFG_CFGR1_IRDA_ENV_SEL); \
mbed_official 340:28d1f895c6fe 628 SYSCFG->CFGR1 |= (__SOURCE__); \
mbed_official 340:28d1f895c6fe 629 }while(0)
mbed_official 340:28d1f895c6fe 630
mbed_official 340:28d1f895c6fe 631 #define __HAL_SYSCFG_GET_IRDA_ENV_SELECTION() ((SYSCFG->CFGR1) & 0x000000C0)
mbed_official 340:28d1f895c6fe 632 /**
mbed_official 340:28d1f895c6fe 633 * @}
mbed_official 340:28d1f895c6fe 634 */
mbed_official 340:28d1f895c6fe 635 #endif /* (STM32F091xC) || defined (STM32F098xx)*/
mbed_official 340:28d1f895c6fe 636
mbed_official 340:28d1f895c6fe 637 /**
mbed_official 340:28d1f895c6fe 638 * @}
mbed_official 340:28d1f895c6fe 639 */
mbed_official 340:28d1f895c6fe 640 /* Exported functions --------------------------------------------------------*/
mbed_official 340:28d1f895c6fe 641 /** @addtogroup HAL_Exported_Functions HAL Exported Functions
mbed_official 340:28d1f895c6fe 642 * @{
mbed_official 340:28d1f895c6fe 643 */
mbed_official 340:28d1f895c6fe 644
mbed_official 340:28d1f895c6fe 645 /** @addtogroup HAL_Exported_Functions_Group1 Initialization and de-initialization Functions
mbed_official 340:28d1f895c6fe 646 * @brief Initialization and de-initialization functions
mbed_official 340:28d1f895c6fe 647 * @{
mbed_official 340:28d1f895c6fe 648 */
mbed_official 340:28d1f895c6fe 649 /* Initialization and de-initialization functions ******************************/
mbed_official 340:28d1f895c6fe 650 HAL_StatusTypeDef HAL_Init(void);
mbed_official 340:28d1f895c6fe 651 HAL_StatusTypeDef HAL_DeInit(void);
mbed_official 340:28d1f895c6fe 652 void HAL_MspInit(void);
mbed_official 340:28d1f895c6fe 653 void HAL_MspDeInit(void);
mbed_official 340:28d1f895c6fe 654 HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
mbed_official 340:28d1f895c6fe 655 /**
mbed_official 340:28d1f895c6fe 656 * @}
mbed_official 340:28d1f895c6fe 657 */
mbed_official 340:28d1f895c6fe 658
mbed_official 340:28d1f895c6fe 659 /** @addtogroup HAL_Exported_Functions_Group2 HAL Control functions
mbed_official 340:28d1f895c6fe 660 * @brief HAL Control functions
mbed_official 340:28d1f895c6fe 661 * @{
mbed_official 340:28d1f895c6fe 662 */
mbed_official 340:28d1f895c6fe 663 /* Peripheral Control functions **********************************************/
mbed_official 340:28d1f895c6fe 664 void HAL_IncTick(void);
mbed_official 340:28d1f895c6fe 665 void HAL_Delay(__IO uint32_t Delay);
mbed_official 340:28d1f895c6fe 666 uint32_t HAL_GetTick(void);
mbed_official 340:28d1f895c6fe 667 void HAL_SuspendTick(void);
mbed_official 340:28d1f895c6fe 668 void HAL_ResumeTick(void);
mbed_official 340:28d1f895c6fe 669 uint32_t HAL_GetHalVersion(void);
mbed_official 340:28d1f895c6fe 670 uint32_t HAL_GetREVID(void);
mbed_official 340:28d1f895c6fe 671 uint32_t HAL_GetDEVID(void);
mbed_official 340:28d1f895c6fe 672 void HAL_EnableDBGStopMode(void);
mbed_official 340:28d1f895c6fe 673 void HAL_DisableDBGStopMode(void);
mbed_official 340:28d1f895c6fe 674 void HAL_EnableDBGStandbyMode(void);
mbed_official 340:28d1f895c6fe 675 void HAL_DisableDBGStandbyMode(void);
mbed_official 340:28d1f895c6fe 676 /**
mbed_official 340:28d1f895c6fe 677 * @}
mbed_official 340:28d1f895c6fe 678 */
mbed_official 340:28d1f895c6fe 679
mbed_official 340:28d1f895c6fe 680 /**
mbed_official 340:28d1f895c6fe 681 * @}
mbed_official 340:28d1f895c6fe 682 */
mbed_official 340:28d1f895c6fe 683
mbed_official 340:28d1f895c6fe 684 /**
mbed_official 340:28d1f895c6fe 685 * @}
mbed_official 340:28d1f895c6fe 686 */
mbed_official 340:28d1f895c6fe 687
mbed_official 340:28d1f895c6fe 688 /**
mbed_official 340:28d1f895c6fe 689 * @}
mbed_official 340:28d1f895c6fe 690 */
mbed_official 340:28d1f895c6fe 691
mbed_official 340:28d1f895c6fe 692 #ifdef __cplusplus
mbed_official 340:28d1f895c6fe 693 }
mbed_official 340:28d1f895c6fe 694 #endif
mbed_official 340:28d1f895c6fe 695
mbed_official 340:28d1f895c6fe 696 #endif /* __STM32F0xx_HAL_H */
mbed_official 340:28d1f895c6fe 697
mbed_official 340:28d1f895c6fe 698 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/