mbed library sources

Fork of mbed-src by mbed official

Committer:
mbed_official
Date:
Wed Dec 03 09:45:08 2014 +0000
Revision:
425:91481e778ca2
Parent:
155:8435094ec241
Synchronized with git revision da233f6e5eb075b1e8d1fcc1438f74d3cb08e2ab

Full URL: https://github.com/mbedmicro/mbed/commit/da233f6e5eb075b1e8d1fcc1438f74d3cb08e2ab/

Targets: Fix GCC ARM linker script for STM32L1 (STM32L152XE)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mbed_official 155:8435094ec241 1 /**
mbed_official 155:8435094ec241 2 ******************************************************************************
mbed_official 155:8435094ec241 3 * @file stm32f30x.h
mbed_official 155:8435094ec241 4 * @author MCD Application Team
mbed_official 155:8435094ec241 5 * @version V1.1.0
mbed_official 155:8435094ec241 6 * @date 27-February-2014
mbed_official 155:8435094ec241 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer Header File.
mbed_official 155:8435094ec241 8 * This file contains all the peripheral registers definitions, bits
mbed_official 155:8435094ec241 9 * definitions and memory mapping for STM32F30x devices.
mbed_official 155:8435094ec241 10 *
mbed_official 155:8435094ec241 11 * The file is the unique include file that the application programmer
mbed_official 155:8435094ec241 12 * is using in the C source code, usually in main.c. This file contains:
mbed_official 155:8435094ec241 13 * - Configuration section that allows to select:
mbed_official 155:8435094ec241 14 * - The device used in the target application
mbed_official 155:8435094ec241 15 * - To use or not the peripheral’s drivers in application code(i.e.
mbed_official 155:8435094ec241 16 * code will be based on direct access to peripheral’s registers
mbed_official 155:8435094ec241 17 * rather than drivers API), this option is controlled by
mbed_official 155:8435094ec241 18 * "#define USE_STDPERIPH_DRIVER"
mbed_official 155:8435094ec241 19 * - To change few application-specific parameters such as the HSE
mbed_official 155:8435094ec241 20 * crystal frequency
mbed_official 155:8435094ec241 21 * - Data structures and the address mapping for all peripherals
mbed_official 155:8435094ec241 22 * - Peripheral registers declarations and bits definition
mbed_official 155:8435094ec241 23 * - Macros to access peripheral registers hardware
mbed_official 155:8435094ec241 24 *
mbed_official 155:8435094ec241 25 ******************************************************************************
mbed_official 155:8435094ec241 26 * @attention
mbed_official 155:8435094ec241 27 *
mbed_official 155:8435094ec241 28 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
mbed_official 155:8435094ec241 29 *
mbed_official 155:8435094ec241 30 * Redistribution and use in source and binary forms, with or without modification,
mbed_official 155:8435094ec241 31 * are permitted provided that the following conditions are met:
mbed_official 155:8435094ec241 32 * 1. Redistributions of source code must retain the above copyright notice,
mbed_official 155:8435094ec241 33 * this list of conditions and the following disclaimer.
mbed_official 155:8435094ec241 34 * 2. Redistributions in binary form must reproduce the above copyright notice,
mbed_official 155:8435094ec241 35 * this list of conditions and the following disclaimer in the documentation
mbed_official 155:8435094ec241 36 * and/or other materials provided with the distribution.
mbed_official 155:8435094ec241 37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
mbed_official 155:8435094ec241 38 * may be used to endorse or promote products derived from this software
mbed_official 155:8435094ec241 39 * without specific prior written permission.
mbed_official 155:8435094ec241 40 *
mbed_official 155:8435094ec241 41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mbed_official 155:8435094ec241 42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mbed_official 155:8435094ec241 43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
mbed_official 155:8435094ec241 44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
mbed_official 155:8435094ec241 45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
mbed_official 155:8435094ec241 46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
mbed_official 155:8435094ec241 47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 155:8435094ec241 48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
mbed_official 155:8435094ec241 49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
mbed_official 155:8435094ec241 50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
mbed_official 155:8435094ec241 51 *
mbed_official 155:8435094ec241 52 ******************************************************************************
mbed_official 155:8435094ec241 53 */
mbed_official 155:8435094ec241 54
mbed_official 155:8435094ec241 55 /** @addtogroup CMSIS
mbed_official 155:8435094ec241 56 * @{
mbed_official 155:8435094ec241 57 */
mbed_official 155:8435094ec241 58
mbed_official 155:8435094ec241 59 /** @addtogroup stm32f30x
mbed_official 155:8435094ec241 60 * @{
mbed_official 155:8435094ec241 61 */
mbed_official 155:8435094ec241 62
mbed_official 155:8435094ec241 63 #ifndef __STM32F30x_H
mbed_official 155:8435094ec241 64 #define __STM32F30x_H
mbed_official 155:8435094ec241 65
mbed_official 155:8435094ec241 66 #ifdef __cplusplus
mbed_official 155:8435094ec241 67 extern "C" {
mbed_official 155:8435094ec241 68 #endif /* __cplusplus */
mbed_official 155:8435094ec241 69
mbed_official 155:8435094ec241 70 /** @addtogroup Library_configuration_section
mbed_official 155:8435094ec241 71 * @{
mbed_official 155:8435094ec241 72 */
mbed_official 155:8435094ec241 73
mbed_official 155:8435094ec241 74 /* Uncomment the line below according to the target STM32 device used in your
mbed_official 155:8435094ec241 75 application
mbed_official 155:8435094ec241 76 */
mbed_official 155:8435094ec241 77
mbed_official 155:8435094ec241 78 #if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F303x8) && !defined (STM32F301x8) && !defined (STM32F302x8)
mbed_official 155:8435094ec241 79 #define STM32F303xC /*!< STM32F303CB, STM32F303CC, STM32F303RB, STM32F303RC, STM32F303VB and STM32F303VC Devices */
mbed_official 155:8435094ec241 80 /* #define STM32F334x8 */ /*!< STM32F334C4, STM32F334C6, STM32F334C8, STM32F334R4, STM32F334R6 and STM32F334R8 Devices */
mbed_official 155:8435094ec241 81 /* #define STM32F302x8 */ /*!< STM32F302K4, STM32F302K6, STM32F302K8, STM32F302C4, STM32F302C6, STM32F302C8,
mbed_official 155:8435094ec241 82 STM32F302R4, STM32F302R6 and STM32F302R8 Devices */
mbed_official 155:8435094ec241 83 #endif
mbed_official 155:8435094ec241 84
mbed_official 155:8435094ec241 85 /* Tip: To avoid modifying this file each time you need to switch between these
mbed_official 155:8435094ec241 86 devices, you can define the device in your toolchain compiler preprocessor.
mbed_official 155:8435094ec241 87 */
mbed_official 155:8435094ec241 88
mbed_official 155:8435094ec241 89 /* Old STM32F30X definition, maintained for legacy purpose */
mbed_official 155:8435094ec241 90 #if defined(STM32F30X)
mbed_official 155:8435094ec241 91 #define STM32F303xC
mbed_official 155:8435094ec241 92 #endif /* STM32F30X */
mbed_official 155:8435094ec241 93
mbed_official 155:8435094ec241 94 #if !defined (STM32F303xC) && !defined (STM32F334x8) && !defined (STM32F302x8)
mbed_official 155:8435094ec241 95 #error "Please select first the target STM32F30X device used in your application (in stm32f30x.h file)"
mbed_official 155:8435094ec241 96 #endif
mbed_official 155:8435094ec241 97
mbed_official 155:8435094ec241 98 #if !defined (USE_STDPERIPH_DRIVER)
mbed_official 155:8435094ec241 99 /**
mbed_official 155:8435094ec241 100 * @brief Comment the line below if you will not use the peripherals drivers.
mbed_official 155:8435094ec241 101 In this case, these drivers will not be included and the application code will
mbed_official 155:8435094ec241 102 be based on direct access to peripherals registers
mbed_official 155:8435094ec241 103 */
mbed_official 155:8435094ec241 104 #define USE_STDPERIPH_DRIVER
mbed_official 155:8435094ec241 105 #endif /* USE_STDPERIPH_DRIVER */
mbed_official 155:8435094ec241 106
mbed_official 155:8435094ec241 107 /**
mbed_official 155:8435094ec241 108 * @brief In the following line adjust the value of External High Speed oscillator (HSE)
mbed_official 155:8435094ec241 109 used in your application
mbed_official 155:8435094ec241 110
mbed_official 155:8435094ec241 111 Tip: To avoid modifying this file each time you need to use different HSE, you
mbed_official 155:8435094ec241 112 can define the HSE value in your toolchain compiler preprocessor.
mbed_official 155:8435094ec241 113 */
mbed_official 155:8435094ec241 114 #if !defined (HSE_VALUE)
mbed_official 155:8435094ec241 115 #define HSE_VALUE ((uint32_t)8000000) /*!< Value of the External xtal in Hz */
mbed_official 155:8435094ec241 116 #endif /* HSE_VALUE */
mbed_official 155:8435094ec241 117
mbed_official 155:8435094ec241 118 /**
mbed_official 155:8435094ec241 119 * @brief In the following line adjust the External High Speed oscillator (HSE) Startup
mbed_official 155:8435094ec241 120 Timeout value
mbed_official 155:8435094ec241 121 */
mbed_official 155:8435094ec241 122 #if !defined (HSE_STARTUP_TIMEOUT)
mbed_official 155:8435094ec241 123 #define HSE_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSE start up */
mbed_official 155:8435094ec241 124 #endif /* HSE_STARTUP_TIMEOUT */
mbed_official 155:8435094ec241 125
mbed_official 155:8435094ec241 126 /**
mbed_official 155:8435094ec241 127 * @brief In the following line adjust the Internal High Speed oscillator (HSI) Startup
mbed_official 155:8435094ec241 128 Timeout value
mbed_official 155:8435094ec241 129 */
mbed_official 155:8435094ec241 130 #if !defined (HSI_STARTUP_TIMEOUT)
mbed_official 155:8435094ec241 131 #define HSI_STARTUP_TIMEOUT ((uint16_t)0x5000) /*!< Time out for HSI start up */
mbed_official 155:8435094ec241 132 #endif /* HSI_STARTUP_TIMEOUT */
mbed_official 155:8435094ec241 133
mbed_official 155:8435094ec241 134 #if !defined (HSI_VALUE)
mbed_official 155:8435094ec241 135 #define HSI_VALUE ((uint32_t)8000000)
mbed_official 155:8435094ec241 136 #endif /* HSI_VALUE */ /*!< Value of the Internal High Speed oscillator in Hz.
mbed_official 155:8435094ec241 137 The real value may vary depending on the variations
mbed_official 155:8435094ec241 138 in voltage and temperature. */
mbed_official 155:8435094ec241 139 #if !defined (LSI_VALUE)
mbed_official 155:8435094ec241 140 #define LSI_VALUE ((uint32_t)40000)
mbed_official 155:8435094ec241 141 #endif /* LSI_VALUE */ /*!< Value of the Internal Low Speed oscillator in Hz
mbed_official 155:8435094ec241 142 The real value may vary depending on the variations
mbed_official 155:8435094ec241 143 in voltage and temperature. */
mbed_official 155:8435094ec241 144 #if !defined (LSE_VALUE)
mbed_official 155:8435094ec241 145 #define LSE_VALUE ((uint32_t)32768) /*!< Value of the External Low Speed oscillator in Hz */
mbed_official 155:8435094ec241 146 #endif /* LSE_VALUE */
mbed_official 155:8435094ec241 147
mbed_official 155:8435094ec241 148
mbed_official 155:8435094ec241 149 /**
mbed_official 155:8435094ec241 150 * @brief STM32F30x Standard Peripherals Library version number V1.1.0
mbed_official 155:8435094ec241 151 */
mbed_official 155:8435094ec241 152 #define __STM32F30X_STDPERIPH_VERSION_MAIN (0x01) /*!< [31:24] main version */
mbed_official 155:8435094ec241 153 #define __STM32F30X_STDPERIPH_VERSION_SUB1 (0x01) /*!< [23:16] sub1 version */
mbed_official 155:8435094ec241 154 #define __STM32F30X_STDPERIPH_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
mbed_official 155:8435094ec241 155 #define __STM32F30X_STDPERIPH_VERSION_RC (0x00) /*!< [7:0] release candidate */
mbed_official 155:8435094ec241 156 #define __STM32F30X_STDPERIPH_VERSION ( (__STM32F30X_STDPERIPH_VERSION_MAIN << 24)\
mbed_official 155:8435094ec241 157 |(__STM32F30X_STDPERIPH_VERSION_SUB1 << 16)\
mbed_official 155:8435094ec241 158 |(__STM32F30X_STDPERIPH_VERSION_SUB2 << 8)\
mbed_official 155:8435094ec241 159 |(__STM32F30X_STDPERIPH_VERSION_RC))
mbed_official 155:8435094ec241 160
mbed_official 155:8435094ec241 161 /**
mbed_official 155:8435094ec241 162 * @}
mbed_official 155:8435094ec241 163 */
mbed_official 155:8435094ec241 164
mbed_official 155:8435094ec241 165 /** @addtogroup Configuration_section_for_CMSIS
mbed_official 155:8435094ec241 166 * @{
mbed_official 155:8435094ec241 167 */
mbed_official 155:8435094ec241 168
mbed_official 155:8435094ec241 169 /**
mbed_official 155:8435094ec241 170 * @brief Configuration of the Cortex-M4 Processor and Core Peripherals
mbed_official 155:8435094ec241 171 */
mbed_official 155:8435094ec241 172 #define __CM4_REV 0x0001 /*!< Core revision r0p1 */
mbed_official 155:8435094ec241 173 #define __MPU_PRESENT 1 /*!< STM32F30X provide an MPU */
mbed_official 155:8435094ec241 174 #define __NVIC_PRIO_BITS 4 /*!< STM32F30X uses 4 Bits for the Priority Levels */
mbed_official 155:8435094ec241 175 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
mbed_official 155:8435094ec241 176 #define __FPU_PRESENT 1 /*!< STM32F30X provide an FPU */
mbed_official 155:8435094ec241 177
mbed_official 155:8435094ec241 178
mbed_official 155:8435094ec241 179 /**
mbed_official 155:8435094ec241 180 * @brief STM32F30X Interrupt Number Definition, according to the selected device
mbed_official 155:8435094ec241 181 * in @ref Library_configuration_section
mbed_official 155:8435094ec241 182 */
mbed_official 155:8435094ec241 183 typedef enum IRQn
mbed_official 155:8435094ec241 184 {
mbed_official 155:8435094ec241 185 /****** Cortex-M4 Processor Exceptions Numbers ****************************************************************/
mbed_official 155:8435094ec241 186 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
mbed_official 155:8435094ec241 187 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt */
mbed_official 155:8435094ec241 188 BusFault_IRQn = -11, /*!< 5 Cortex-M4 Bus Fault Interrupt */
mbed_official 155:8435094ec241 189 UsageFault_IRQn = -10, /*!< 6 Cortex-M4 Usage Fault Interrupt */
mbed_official 155:8435094ec241 190 SVCall_IRQn = -5, /*!< 11 Cortex-M4 SV Call Interrupt */
mbed_official 155:8435094ec241 191 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M4 Debug Monitor Interrupt */
mbed_official 155:8435094ec241 192 PendSV_IRQn = -2, /*!< 14 Cortex-M4 Pend SV Interrupt */
mbed_official 155:8435094ec241 193 SysTick_IRQn = -1, /*!< 15 Cortex-M4 System Tick Interrupt */
mbed_official 155:8435094ec241 194 /****** STM32 specific Interrupt Numbers **********************************************************************/
mbed_official 155:8435094ec241 195 #ifdef STM32F303xC
mbed_official 155:8435094ec241 196 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 155:8435094ec241 197 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 155:8435094ec241 198 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
mbed_official 155:8435094ec241 199 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
mbed_official 155:8435094ec241 200 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 155:8435094ec241 201 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 155:8435094ec241 202 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 155:8435094ec241 203 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 155:8435094ec241 204 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
mbed_official 155:8435094ec241 205 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 155:8435094ec241 206 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 155:8435094ec241 207 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
mbed_official 155:8435094ec241 208 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
mbed_official 155:8435094ec241 209 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
mbed_official 155:8435094ec241 210 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
mbed_official 155:8435094ec241 211 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
mbed_official 155:8435094ec241 212 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
mbed_official 155:8435094ec241 213 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
mbed_official 155:8435094ec241 214 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
mbed_official 155:8435094ec241 215 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
mbed_official 155:8435094ec241 216 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
mbed_official 155:8435094ec241 217 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 155:8435094ec241 218 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 155:8435094ec241 219 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 155:8435094ec241 220 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
mbed_official 155:8435094ec241 221 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
mbed_official 155:8435094ec241 222 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
mbed_official 155:8435094ec241 223 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 155:8435094ec241 224 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 155:8435094ec241 225 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 155:8435094ec241 226 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
mbed_official 155:8435094ec241 227 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 155:8435094ec241 228 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 155:8435094ec241 229 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 155:8435094ec241 230 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 155:8435094ec241 231 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 155:8435094ec241 232 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 155:8435094ec241 233 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 155:8435094ec241 234 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 155:8435094ec241 235 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 155:8435094ec241 236 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 155:8435094ec241 237 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 155:8435094ec241 238 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
mbed_official 155:8435094ec241 239 TIM8_BRK_IRQn = 43, /*!< TIM8 Break Interrupt */
mbed_official 155:8435094ec241 240 TIM8_UP_IRQn = 44, /*!< TIM8 Update Interrupt */
mbed_official 155:8435094ec241 241 TIM8_TRG_COM_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt */
mbed_official 155:8435094ec241 242 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
mbed_official 155:8435094ec241 243 ADC3_IRQn = 47, /*!< ADC3 global Interrupt */
mbed_official 155:8435094ec241 244 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 155:8435094ec241 245 UART4_IRQn = 52, /*!< UART4 global Interrupt */
mbed_official 155:8435094ec241 246 UART5_IRQn = 53, /*!< UART5 global Interrupt */
mbed_official 155:8435094ec241 247 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 155:8435094ec241 248 TIM7_IRQn = 55, /*!< TIM7 global Interrupt */
mbed_official 155:8435094ec241 249 DMA2_Channel1_IRQn = 56, /*!< DMA2 Channel 1 global Interrupt */
mbed_official 155:8435094ec241 250 DMA2_Channel2_IRQn = 57, /*!< DMA2 Channel 2 global Interrupt */
mbed_official 155:8435094ec241 251 DMA2_Channel3_IRQn = 58, /*!< DMA2 Channel 3 global Interrupt */
mbed_official 155:8435094ec241 252 DMA2_Channel4_IRQn = 59, /*!< DMA2 Channel 4 global Interrupt */
mbed_official 155:8435094ec241 253 DMA2_Channel5_IRQn = 60, /*!< DMA2 Channel 5 global Interrupt */
mbed_official 155:8435094ec241 254 ADC4_IRQn = 61, /*!< ADC4 global Interrupt */
mbed_official 155:8435094ec241 255 COMP1_2_3_IRQn = 64, /*!< COMP1, COMP2 and COMP3 global Interrupt */
mbed_official 155:8435094ec241 256 COMP4_5_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */
mbed_official 155:8435094ec241 257 COMP7_IRQn = 66, /*!< COMP7 global Interrupt */
mbed_official 155:8435094ec241 258 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
mbed_official 155:8435094ec241 259 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
mbed_official 155:8435094ec241 260 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
mbed_official 155:8435094ec241 261 FPU_IRQn = 81 /*!< Floating point Interrupt */
mbed_official 155:8435094ec241 262 #endif /* STM32F303xC */
mbed_official 155:8435094ec241 263 #ifdef STM32F334x8
mbed_official 155:8435094ec241 264 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 155:8435094ec241 265 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 155:8435094ec241 266 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
mbed_official 155:8435094ec241 267 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 17, 19 & 20 */
mbed_official 155:8435094ec241 268 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 155:8435094ec241 269 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 155:8435094ec241 270 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 155:8435094ec241 271 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 155:8435094ec241 272 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
mbed_official 155:8435094ec241 273 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 155:8435094ec241 274 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 155:8435094ec241 275 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
mbed_official 155:8435094ec241 276 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
mbed_official 155:8435094ec241 277 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
mbed_official 155:8435094ec241 278 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
mbed_official 155:8435094ec241 279 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
mbed_official 155:8435094ec241 280 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
mbed_official 155:8435094ec241 281 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
mbed_official 155:8435094ec241 282 ADC1_2_IRQn = 18, /*!< ADC1 & ADC2 Interrupts */
mbed_official 155:8435094ec241 283 CAN1_TX_IRQn = 19, /*!< CAN1 TX Interrupts */
mbed_official 155:8435094ec241 284 CAN1_RX0_IRQn = 20, /*!< CAN1 RX0 Interrupts */
mbed_official 155:8435094ec241 285 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 155:8435094ec241 286 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 155:8435094ec241 287 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 155:8435094ec241 288 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
mbed_official 155:8435094ec241 289 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
mbed_official 155:8435094ec241 290 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
mbed_official 155:8435094ec241 291 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 155:8435094ec241 292 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 155:8435094ec241 293 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
mbed_official 155:8435094ec241 294 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 155:8435094ec241 295 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 155:8435094ec241 296 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
mbed_official 155:8435094ec241 297 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 155:8435094ec241 298 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 155:8435094ec241 299 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 155:8435094ec241 300 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 155:8435094ec241 301 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 155:8435094ec241 302 TIM6_DAC1_IRQn = 54, /*!< TIM6 global and DAC1 underrun error interrupts */
mbed_official 155:8435094ec241 303 TIM7_DAC2_IRQn = 55, /*!< TIM7 global and DAC2 underrun error Interrupt */
mbed_official 155:8435094ec241 304 COMP2_IRQn = 64, /*!< COMP2 global Interrupt */
mbed_official 155:8435094ec241 305 COMP4_6_IRQn = 65, /*!< COMP6 and COMP4 global Interrupt */
mbed_official 155:8435094ec241 306 HRTIM1_Master_IRQn = 67, /*!< HRTIM Master Timer global Interrupts */
mbed_official 155:8435094ec241 307 HRTIM1_TIMA_IRQn = 68, /*!< HRTIM Timer A global Interrupt */
mbed_official 155:8435094ec241 308 HRTIM1_TIMB_IRQn = 69, /*!< HRTIM Timer B global Interrupt */
mbed_official 155:8435094ec241 309 HRTIM1_TIMC_IRQn = 70, /*!< HRTIM Timer C global Interrupt */
mbed_official 155:8435094ec241 310 HRTIM1_TIMD_IRQn = 71, /*!< HRTIM Timer D global Interrupt */
mbed_official 155:8435094ec241 311 HRTIM1_TIME_IRQn = 72, /*!< HRTIM Timer E global Interrupt */
mbed_official 155:8435094ec241 312 HRTIM1_FLT_IRQn = 73, /*!< HRTIM Fault global Interrupt */
mbed_official 155:8435094ec241 313 FPU_IRQn = 81 /*!< Floating point Interrupt */
mbed_official 155:8435094ec241 314 #endif /* STM32F334x8 */
mbed_official 155:8435094ec241 315 #ifdef STM32F302x8
mbed_official 155:8435094ec241 316 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
mbed_official 155:8435094ec241 317 PVD_IRQn = 1, /*!< PVD through EXTI Line detection Interrupt */
mbed_official 155:8435094ec241 318 TAMPER_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts */
mbed_official 155:8435094ec241 319 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI lines 20 */
mbed_official 155:8435094ec241 320 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
mbed_official 155:8435094ec241 321 RCC_IRQn = 5, /*!< RCC global Interrupt */
mbed_official 155:8435094ec241 322 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
mbed_official 155:8435094ec241 323 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
mbed_official 155:8435094ec241 324 EXTI2_TS_IRQn = 8, /*!< EXTI Line2 Interrupt and Touch Sense Interrupt */
mbed_official 155:8435094ec241 325 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
mbed_official 155:8435094ec241 326 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
mbed_official 155:8435094ec241 327 DMA1_Channel1_IRQn = 11, /*!< DMA1 Channel 1 Interrupt */
mbed_official 155:8435094ec241 328 DMA1_Channel2_IRQn = 12, /*!< DMA1 Channel 2 Interrupt */
mbed_official 155:8435094ec241 329 DMA1_Channel3_IRQn = 13, /*!< DMA1 Channel 3 Interrupt */
mbed_official 155:8435094ec241 330 DMA1_Channel4_IRQn = 14, /*!< DMA1 Channel 4 Interrupt */
mbed_official 155:8435094ec241 331 DMA1_Channel5_IRQn = 15, /*!< DMA1 Channel 5 Interrupt */
mbed_official 155:8435094ec241 332 DMA1_Channel6_IRQn = 16, /*!< DMA1 Channel 6 Interrupt */
mbed_official 155:8435094ec241 333 DMA1_Channel7_IRQn = 17, /*!< DMA1 Channel 7 Interrupt */
mbed_official 155:8435094ec241 334 ADC1_IRQn = 18, /*!< ADC1 Interrupts */
mbed_official 155:8435094ec241 335 USB_HP_CAN1_TX_IRQn = 19, /*!< USB Device High Priority or CAN1 TX Interrupts */
mbed_official 155:8435094ec241 336 USB_LP_CAN1_RX0_IRQn = 20, /*!< USB Device Low Priority or CAN1 RX0 Interrupts */
mbed_official 155:8435094ec241 337 CAN1_RX1_IRQn = 21, /*!< CAN1 RX1 Interrupt */
mbed_official 155:8435094ec241 338 CAN1_SCE_IRQn = 22, /*!< CAN1 SCE Interrupt */
mbed_official 155:8435094ec241 339 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
mbed_official 155:8435094ec241 340 TIM1_BRK_TIM15_IRQn = 24, /*!< TIM1 Break and TIM15 Interrupts */
mbed_official 155:8435094ec241 341 TIM1_UP_TIM16_IRQn = 25, /*!< TIM1 Update and TIM16 Interrupts */
mbed_official 155:8435094ec241 342 TIM1_TRG_COM_TIM17_IRQn = 26, /*!< TIM1 Trigger and Commutation and TIM17 Interrupt */
mbed_official 155:8435094ec241 343 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
mbed_official 155:8435094ec241 344 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
mbed_official 155:8435094ec241 345 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
mbed_official 155:8435094ec241 346 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
mbed_official 155:8435094ec241 347 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
mbed_official 155:8435094ec241 348 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
mbed_official 155:8435094ec241 349 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
mbed_official 155:8435094ec241 350 USART1_IRQn = 37, /*!< USART1 global Interrupt */
mbed_official 155:8435094ec241 351 USART2_IRQn = 38, /*!< USART2 global Interrupt */
mbed_official 155:8435094ec241 352 USART3_IRQn = 39, /*!< USART3 global Interrupt */
mbed_official 155:8435094ec241 353 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
mbed_official 155:8435094ec241 354 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
mbed_official 155:8435094ec241 355 USBWakeUp_IRQn = 42, /*!< USB Wakeup Interrupt */
mbed_official 155:8435094ec241 356 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
mbed_official 155:8435094ec241 357 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
mbed_official 155:8435094ec241 358 COMP2_IRQn = 64, /*!< COMP2 global Interrupt */
mbed_official 155:8435094ec241 359 COMP4_6_IRQn = 65, /*!< COMP5, COMP6 and COMP4 global Interrupt */
mbed_official 155:8435094ec241 360 COMP7_IRQn = 66, /*!< COMP7 global Interrupt */
mbed_official 155:8435094ec241 361 I2C3_EV_IRQn = 72, /*!< I2C3 Event Interrupt */
mbed_official 155:8435094ec241 362 I2C3_ER_IRQn = 73, /*!< I2C3 Error Interrupt */
mbed_official 155:8435094ec241 363 USB_HP_IRQn = 74, /*!< USB High Priority global Interrupt remap */
mbed_official 155:8435094ec241 364 USB_LP_IRQn = 75, /*!< USB Low Priority global Interrupt remap */
mbed_official 155:8435094ec241 365 USBWakeUp_RMP_IRQn = 76, /*!< USB Wakeup Interrupt remap */
mbed_official 155:8435094ec241 366 FPU_IRQn = 81 /*!< Floating point Interrupt */
mbed_official 155:8435094ec241 367 #endif /* STM32F302x8 */
mbed_official 155:8435094ec241 368 } IRQn_Type;
mbed_official 155:8435094ec241 369
mbed_official 155:8435094ec241 370 /**
mbed_official 155:8435094ec241 371 * @}
mbed_official 155:8435094ec241 372 */
mbed_official 155:8435094ec241 373
mbed_official 155:8435094ec241 374 #include "core_cm4.h" /* Cortex-M4 processor and core peripherals */
mbed_official 155:8435094ec241 375 #include "system_stm32f30x.h" /* STM32F30x System Header */
mbed_official 155:8435094ec241 376 #include <stdint.h>
mbed_official 155:8435094ec241 377
mbed_official 155:8435094ec241 378 /** @addtogroup Exported_types
mbed_official 155:8435094ec241 379 * @{
mbed_official 155:8435094ec241 380 */
mbed_official 155:8435094ec241 381 /*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
mbed_official 155:8435094ec241 382 typedef int32_t s32;
mbed_official 155:8435094ec241 383 typedef int16_t s16;
mbed_official 155:8435094ec241 384 typedef int8_t s8;
mbed_official 155:8435094ec241 385
mbed_official 155:8435094ec241 386 typedef const int32_t sc32; /*!< Read Only */
mbed_official 155:8435094ec241 387 typedef const int16_t sc16; /*!< Read Only */
mbed_official 155:8435094ec241 388 typedef const int8_t sc8; /*!< Read Only */
mbed_official 155:8435094ec241 389
mbed_official 155:8435094ec241 390 typedef __IO int32_t vs32;
mbed_official 155:8435094ec241 391 typedef __IO int16_t vs16;
mbed_official 155:8435094ec241 392 typedef __IO int8_t vs8;
mbed_official 155:8435094ec241 393
mbed_official 155:8435094ec241 394 typedef __I int32_t vsc32; /*!< Read Only */
mbed_official 155:8435094ec241 395 typedef __I int16_t vsc16; /*!< Read Only */
mbed_official 155:8435094ec241 396 typedef __I int8_t vsc8; /*!< Read Only */
mbed_official 155:8435094ec241 397
mbed_official 155:8435094ec241 398 typedef uint32_t u32;
mbed_official 155:8435094ec241 399 typedef uint16_t u16;
mbed_official 155:8435094ec241 400 typedef uint8_t u8;
mbed_official 155:8435094ec241 401
mbed_official 155:8435094ec241 402 typedef const uint32_t uc32; /*!< Read Only */
mbed_official 155:8435094ec241 403 typedef const uint16_t uc16; /*!< Read Only */
mbed_official 155:8435094ec241 404 typedef const uint8_t uc8; /*!< Read Only */
mbed_official 155:8435094ec241 405
mbed_official 155:8435094ec241 406 typedef __IO uint32_t vu32;
mbed_official 155:8435094ec241 407 typedef __IO uint16_t vu16;
mbed_official 155:8435094ec241 408 typedef __IO uint8_t vu8;
mbed_official 155:8435094ec241 409
mbed_official 155:8435094ec241 410 typedef __I uint32_t vuc32; /*!< Read Only */
mbed_official 155:8435094ec241 411 typedef __I uint16_t vuc16; /*!< Read Only */
mbed_official 155:8435094ec241 412 typedef __I uint8_t vuc8; /*!< Read Only */
mbed_official 155:8435094ec241 413
mbed_official 155:8435094ec241 414 typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
mbed_official 155:8435094ec241 415
mbed_official 155:8435094ec241 416 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
mbed_official 155:8435094ec241 417 #define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
mbed_official 155:8435094ec241 418
mbed_official 155:8435094ec241 419 typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
mbed_official 155:8435094ec241 420
mbed_official 155:8435094ec241 421 /**
mbed_official 155:8435094ec241 422 * @}
mbed_official 155:8435094ec241 423 */
mbed_official 155:8435094ec241 424
mbed_official 155:8435094ec241 425 /** @addtogroup Peripheral_registers_structures
mbed_official 155:8435094ec241 426 * @{
mbed_official 155:8435094ec241 427 */
mbed_official 155:8435094ec241 428
mbed_official 155:8435094ec241 429 /**
mbed_official 155:8435094ec241 430 * @brief Analog to Digital Converter
mbed_official 155:8435094ec241 431 */
mbed_official 155:8435094ec241 432
mbed_official 155:8435094ec241 433 typedef struct
mbed_official 155:8435094ec241 434 {
mbed_official 155:8435094ec241 435 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
mbed_official 155:8435094ec241 436 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
mbed_official 155:8435094ec241 437 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
mbed_official 155:8435094ec241 438 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
mbed_official 155:8435094ec241 439 uint32_t RESERVED0; /*!< Reserved, 0x010 */
mbed_official 155:8435094ec241 440 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
mbed_official 155:8435094ec241 441 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
mbed_official 155:8435094ec241 442 uint32_t RESERVED1; /*!< Reserved, 0x01C */
mbed_official 155:8435094ec241 443 __IO uint32_t TR1; /*!< ADC watchdog threshold register 1, Address offset: 0x20 */
mbed_official 155:8435094ec241 444 __IO uint32_t TR2; /*!< ADC watchdog threshold register 2, Address offset: 0x24 */
mbed_official 155:8435094ec241 445 __IO uint32_t TR3; /*!< ADC watchdog threshold register 3, Address offset: 0x28 */
mbed_official 155:8435094ec241 446 uint32_t RESERVED2; /*!< Reserved, 0x02C */
mbed_official 155:8435094ec241 447 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
mbed_official 155:8435094ec241 448 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
mbed_official 155:8435094ec241 449 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
mbed_official 155:8435094ec241 450 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
mbed_official 155:8435094ec241 451 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
mbed_official 155:8435094ec241 452 uint32_t RESERVED3; /*!< Reserved, 0x044 */
mbed_official 155:8435094ec241 453 uint32_t RESERVED4; /*!< Reserved, 0x048 */
mbed_official 155:8435094ec241 454 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
mbed_official 155:8435094ec241 455 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
mbed_official 155:8435094ec241 456 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
mbed_official 155:8435094ec241 457 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
mbed_official 155:8435094ec241 458 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
mbed_official 155:8435094ec241 459 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
mbed_official 155:8435094ec241 460 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
mbed_official 155:8435094ec241 461 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
mbed_official 155:8435094ec241 462 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
mbed_official 155:8435094ec241 463 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
mbed_official 155:8435094ec241 464 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
mbed_official 155:8435094ec241 465 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
mbed_official 155:8435094ec241 466 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
mbed_official 155:8435094ec241 467 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
mbed_official 155:8435094ec241 468 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
mbed_official 155:8435094ec241 469 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
mbed_official 155:8435094ec241 470 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xB0 */
mbed_official 155:8435094ec241 471 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xB4 */
mbed_official 155:8435094ec241 472
mbed_official 155:8435094ec241 473 } ADC_TypeDef;
mbed_official 155:8435094ec241 474
mbed_official 155:8435094ec241 475 typedef struct
mbed_official 155:8435094ec241 476 {
mbed_official 155:8435094ec241 477 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
mbed_official 155:8435094ec241 478 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
mbed_official 155:8435094ec241 479 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
mbed_official 155:8435094ec241 480 __IO uint32_t CDR; /*!< ADC common regular data register for dual
mbed_official 155:8435094ec241 481 modes, Address offset: ADC1/3 base address + 0x30A */
mbed_official 155:8435094ec241 482 } ADC_Common_TypeDef;
mbed_official 155:8435094ec241 483
mbed_official 155:8435094ec241 484
mbed_official 155:8435094ec241 485 /**
mbed_official 155:8435094ec241 486 * @brief Controller Area Network TxMailBox
mbed_official 155:8435094ec241 487 */
mbed_official 155:8435094ec241 488 typedef struct
mbed_official 155:8435094ec241 489 {
mbed_official 155:8435094ec241 490 __IO uint32_t TIR; /*!< CAN TX mailbox identifier register */
mbed_official 155:8435094ec241 491 __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
mbed_official 155:8435094ec241 492 __IO uint32_t TDLR; /*!< CAN mailbox data low register */
mbed_official 155:8435094ec241 493 __IO uint32_t TDHR; /*!< CAN mailbox data high register */
mbed_official 155:8435094ec241 494 } CAN_TxMailBox_TypeDef;
mbed_official 155:8435094ec241 495
mbed_official 155:8435094ec241 496 /**
mbed_official 155:8435094ec241 497 * @brief Controller Area Network FIFOMailBox
mbed_official 155:8435094ec241 498 */
mbed_official 155:8435094ec241 499 typedef struct
mbed_official 155:8435094ec241 500 {
mbed_official 155:8435094ec241 501 __IO uint32_t RIR; /*!< CAN receive FIFO mailbox identifier register */
mbed_official 155:8435094ec241 502 __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
mbed_official 155:8435094ec241 503 __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
mbed_official 155:8435094ec241 504 __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
mbed_official 155:8435094ec241 505 } CAN_FIFOMailBox_TypeDef;
mbed_official 155:8435094ec241 506
mbed_official 155:8435094ec241 507 /**
mbed_official 155:8435094ec241 508 * @brief Controller Area Network FilterRegister
mbed_official 155:8435094ec241 509 */
mbed_official 155:8435094ec241 510 typedef struct
mbed_official 155:8435094ec241 511 {
mbed_official 155:8435094ec241 512 __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
mbed_official 155:8435094ec241 513 __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
mbed_official 155:8435094ec241 514 } CAN_FilterRegister_TypeDef;
mbed_official 155:8435094ec241 515
mbed_official 155:8435094ec241 516 /**
mbed_official 155:8435094ec241 517 * @brief Controller Area Network
mbed_official 155:8435094ec241 518 */
mbed_official 155:8435094ec241 519 typedef struct
mbed_official 155:8435094ec241 520 {
mbed_official 155:8435094ec241 521 __IO uint32_t MCR; /*!< CAN master control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 522 __IO uint32_t MSR; /*!< CAN master status register, Address offset: 0x04 */
mbed_official 155:8435094ec241 523 __IO uint32_t TSR; /*!< CAN transmit status register, Address offset: 0x08 */
mbed_official 155:8435094ec241 524 __IO uint32_t RF0R; /*!< CAN receive FIFO 0 register, Address offset: 0x0C */
mbed_official 155:8435094ec241 525 __IO uint32_t RF1R; /*!< CAN receive FIFO 1 register, Address offset: 0x10 */
mbed_official 155:8435094ec241 526 __IO uint32_t IER; /*!< CAN interrupt enable register, Address offset: 0x14 */
mbed_official 155:8435094ec241 527 __IO uint32_t ESR; /*!< CAN error status register, Address offset: 0x18 */
mbed_official 155:8435094ec241 528 __IO uint32_t BTR; /*!< CAN bit timing register, Address offset: 0x1C */
mbed_official 155:8435094ec241 529 uint32_t RESERVED0[88]; /*!< Reserved, 0x020 - 0x17F */
mbed_official 155:8435094ec241 530 CAN_TxMailBox_TypeDef sTxMailBox[3]; /*!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC */
mbed_official 155:8435094ec241 531 CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /*!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC */
mbed_official 155:8435094ec241 532 uint32_t RESERVED1[12]; /*!< Reserved, 0x1D0 - 0x1FF */
mbed_official 155:8435094ec241 533 __IO uint32_t FMR; /*!< CAN filter master register, Address offset: 0x200 */
mbed_official 155:8435094ec241 534 __IO uint32_t FM1R; /*!< CAN filter mode register, Address offset: 0x204 */
mbed_official 155:8435094ec241 535 uint32_t RESERVED2; /*!< Reserved, 0x208 */
mbed_official 155:8435094ec241 536 __IO uint32_t FS1R; /*!< CAN filter scale register, Address offset: 0x20C */
mbed_official 155:8435094ec241 537 uint32_t RESERVED3; /*!< Reserved, 0x210 */
mbed_official 155:8435094ec241 538 __IO uint32_t FFA1R; /*!< CAN filter FIFO assignment register, Address offset: 0x214 */
mbed_official 155:8435094ec241 539 uint32_t RESERVED4; /*!< Reserved, 0x218 */
mbed_official 155:8435094ec241 540 __IO uint32_t FA1R; /*!< CAN filter activation register, Address offset: 0x21C */
mbed_official 155:8435094ec241 541 uint32_t RESERVED5[8]; /*!< Reserved, 0x220-0x23F */
mbed_official 155:8435094ec241 542 CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register, Address offset: 0x240-0x31C */
mbed_official 155:8435094ec241 543 } CAN_TypeDef;
mbed_official 155:8435094ec241 544
mbed_official 155:8435094ec241 545
mbed_official 155:8435094ec241 546 /**
mbed_official 155:8435094ec241 547 * @brief Analog Comparators
mbed_official 155:8435094ec241 548 */
mbed_official 155:8435094ec241 549
mbed_official 155:8435094ec241 550 typedef struct
mbed_official 155:8435094ec241 551 {
mbed_official 155:8435094ec241 552 __IO uint32_t CSR; /*!< Comparator control Status register, Address offset: 0x00 */
mbed_official 155:8435094ec241 553 } COMP_TypeDef;
mbed_official 155:8435094ec241 554
mbed_official 155:8435094ec241 555 /**
mbed_official 155:8435094ec241 556 * @brief CRC calculation unit
mbed_official 155:8435094ec241 557 */
mbed_official 155:8435094ec241 558
mbed_official 155:8435094ec241 559 typedef struct
mbed_official 155:8435094ec241 560 {
mbed_official 155:8435094ec241 561 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
mbed_official 155:8435094ec241 562 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
mbed_official 155:8435094ec241 563 uint8_t RESERVED0; /*!< Reserved, 0x05 */
mbed_official 155:8435094ec241 564 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 155:8435094ec241 565 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
mbed_official 155:8435094ec241 566 uint32_t RESERVED2; /*!< Reserved, 0x0C */
mbed_official 155:8435094ec241 567 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
mbed_official 155:8435094ec241 568 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
mbed_official 155:8435094ec241 569 } CRC_TypeDef;
mbed_official 155:8435094ec241 570
mbed_official 155:8435094ec241 571 /**
mbed_official 155:8435094ec241 572 * @brief Digital to Analog Converter
mbed_official 155:8435094ec241 573 */
mbed_official 155:8435094ec241 574
mbed_official 155:8435094ec241 575 typedef struct
mbed_official 155:8435094ec241 576 {
mbed_official 155:8435094ec241 577 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 578 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
mbed_official 155:8435094ec241 579 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
mbed_official 155:8435094ec241 580 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
mbed_official 155:8435094ec241 581 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
mbed_official 155:8435094ec241 582 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
mbed_official 155:8435094ec241 583 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
mbed_official 155:8435094ec241 584 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
mbed_official 155:8435094ec241 585 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
mbed_official 155:8435094ec241 586 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
mbed_official 155:8435094ec241 587 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
mbed_official 155:8435094ec241 588 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
mbed_official 155:8435094ec241 589 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
mbed_official 155:8435094ec241 590 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
mbed_official 155:8435094ec241 591 } DAC_TypeDef;
mbed_official 155:8435094ec241 592
mbed_official 155:8435094ec241 593 /**
mbed_official 155:8435094ec241 594 * @brief Debug MCU
mbed_official 155:8435094ec241 595 */
mbed_official 155:8435094ec241 596
mbed_official 155:8435094ec241 597 typedef struct
mbed_official 155:8435094ec241 598 {
mbed_official 155:8435094ec241 599 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
mbed_official 155:8435094ec241 600 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
mbed_official 155:8435094ec241 601 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
mbed_official 155:8435094ec241 602 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
mbed_official 155:8435094ec241 603 }DBGMCU_TypeDef;
mbed_official 155:8435094ec241 604
mbed_official 155:8435094ec241 605 /**
mbed_official 155:8435094ec241 606 * @brief DMA Controller
mbed_official 155:8435094ec241 607 */
mbed_official 155:8435094ec241 608
mbed_official 155:8435094ec241 609 typedef struct
mbed_official 155:8435094ec241 610 {
mbed_official 155:8435094ec241 611 __IO uint32_t CCR; /*!< DMA channel x configuration register */
mbed_official 155:8435094ec241 612 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
mbed_official 155:8435094ec241 613 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
mbed_official 155:8435094ec241 614 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
mbed_official 155:8435094ec241 615 } DMA_Channel_TypeDef;
mbed_official 155:8435094ec241 616
mbed_official 155:8435094ec241 617 typedef struct
mbed_official 155:8435094ec241 618 {
mbed_official 155:8435094ec241 619 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
mbed_official 155:8435094ec241 620 __IO uint32_t IFCR; /*!< DMA interrupt clear flag register, Address offset: 0x04 */
mbed_official 155:8435094ec241 621 } DMA_TypeDef;
mbed_official 155:8435094ec241 622
mbed_official 155:8435094ec241 623 /**
mbed_official 155:8435094ec241 624 * @brief External Interrupt/Event Controller
mbed_official 155:8435094ec241 625 */
mbed_official 155:8435094ec241 626
mbed_official 155:8435094ec241 627 typedef struct
mbed_official 155:8435094ec241 628 {
mbed_official 155:8435094ec241 629 __IO uint32_t IMR; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
mbed_official 155:8435094ec241 630 __IO uint32_t EMR; /*!< EXTI Event mask register, Address offset: 0x04 */
mbed_official 155:8435094ec241 631 __IO uint32_t RTSR; /*!< EXTI Rising trigger selection register, Address offset: 0x08 */
mbed_official 155:8435094ec241 632 __IO uint32_t FTSR; /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
mbed_official 155:8435094ec241 633 __IO uint32_t SWIER; /*!< EXTI Software interrupt event register, Address offset: 0x10 */
mbed_official 155:8435094ec241 634 __IO uint32_t PR; /*!< EXTI Pending register, Address offset: 0x14 */
mbed_official 155:8435094ec241 635 uint32_t RESERVED1; /*!< Reserved, 0x18 */
mbed_official 155:8435094ec241 636 uint32_t RESERVED2; /*!< Reserved, 0x1C */
mbed_official 155:8435094ec241 637 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
mbed_official 155:8435094ec241 638 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x24 */
mbed_official 155:8435094ec241 639 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x28 */
mbed_official 155:8435094ec241 640 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x2C */
mbed_official 155:8435094ec241 641 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x30 */
mbed_official 155:8435094ec241 642 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x34 */
mbed_official 155:8435094ec241 643 }EXTI_TypeDef;
mbed_official 155:8435094ec241 644
mbed_official 155:8435094ec241 645 /**
mbed_official 155:8435094ec241 646 * @brief FLASH Registers
mbed_official 155:8435094ec241 647 */
mbed_official 155:8435094ec241 648
mbed_official 155:8435094ec241 649 typedef struct
mbed_official 155:8435094ec241 650 {
mbed_official 155:8435094ec241 651 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 652 __IO uint32_t KEYR; /*!< FLASH key register, Address offset: 0x04 */
mbed_official 155:8435094ec241 653 __IO uint32_t OPTKEYR; /*!< FLASH option key register, Address offset: 0x08 */
mbed_official 155:8435094ec241 654 __IO uint32_t SR; /*!< FLASH status register, Address offset: 0x0C */
mbed_official 155:8435094ec241 655 __IO uint32_t CR; /*!< FLASH control register, Address offset: 0x10 */
mbed_official 155:8435094ec241 656 __IO uint32_t AR; /*!< FLASH address register, Address offset: 0x14 */
mbed_official 155:8435094ec241 657 uint32_t RESERVED; /*!< Reserved, 0x18 */
mbed_official 155:8435094ec241 658 __IO uint32_t OBR; /*!< FLASH Option byte register, Address offset: 0x1C */
mbed_official 155:8435094ec241 659 __IO uint32_t WRPR; /*!< FLASH Write register, Address offset: 0x20 */
mbed_official 155:8435094ec241 660
mbed_official 155:8435094ec241 661 } FLASH_TypeDef;
mbed_official 155:8435094ec241 662
mbed_official 155:8435094ec241 663 /**
mbed_official 155:8435094ec241 664 * @brief Option Bytes Registers
mbed_official 155:8435094ec241 665 */
mbed_official 155:8435094ec241 666 typedef struct
mbed_official 155:8435094ec241 667 {
mbed_official 155:8435094ec241 668 __IO uint16_t RDP; /*!<FLASH option byte Read protection, Address offset: 0x00 */
mbed_official 155:8435094ec241 669 __IO uint16_t USER; /*!<FLASH option byte user options, Address offset: 0x02 */
mbed_official 155:8435094ec241 670 uint16_t RESERVED0; /*!< Reserved, 0x04 */
mbed_official 155:8435094ec241 671 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 155:8435094ec241 672 __IO uint16_t WRP0; /*!<FLASH option byte write protection 0, Address offset: 0x08 */
mbed_official 155:8435094ec241 673 __IO uint16_t WRP1; /*!<FLASH option byte write protection 1, Address offset: 0x0C */
mbed_official 155:8435094ec241 674 __IO uint16_t WRP2; /*!<FLASH option byte write protection 2, Address offset: 0x10 */
mbed_official 155:8435094ec241 675 __IO uint16_t WRP3; /*!<FLASH option byte write protection 3, Address offset: 0x12 */
mbed_official 155:8435094ec241 676 } OB_TypeDef;
mbed_official 155:8435094ec241 677
mbed_official 155:8435094ec241 678 /**
mbed_official 155:8435094ec241 679 * @brief General Purpose I/O
mbed_official 155:8435094ec241 680 */
mbed_official 155:8435094ec241 681
mbed_official 155:8435094ec241 682 typedef struct
mbed_official 155:8435094ec241 683 {
mbed_official 155:8435094ec241 684 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
mbed_official 155:8435094ec241 685 __IO uint16_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
mbed_official 155:8435094ec241 686 uint16_t RESERVED0; /*!< Reserved, 0x06 */
mbed_official 155:8435094ec241 687 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
mbed_official 155:8435094ec241 688 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
mbed_official 155:8435094ec241 689 __IO uint16_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
mbed_official 155:8435094ec241 690 uint16_t RESERVED1; /*!< Reserved, 0x12 */
mbed_official 155:8435094ec241 691 __IO uint16_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
mbed_official 155:8435094ec241 692 uint16_t RESERVED2; /*!< Reserved, 0x16 */
mbed_official 155:8435094ec241 693 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
mbed_official 155:8435094ec241 694 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
mbed_official 155:8435094ec241 695 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
mbed_official 155:8435094ec241 696 __IO uint16_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
mbed_official 155:8435094ec241 697 uint16_t RESERVED3; /*!< Reserved, 0x2A */
mbed_official 155:8435094ec241 698 }GPIO_TypeDef;
mbed_official 155:8435094ec241 699
mbed_official 155:8435094ec241 700 /**
mbed_official 155:8435094ec241 701 * @brief High resolution Timer (HRTIM)
mbed_official 155:8435094ec241 702 */
mbed_official 155:8435094ec241 703 /* HRTIM master definition */
mbed_official 155:8435094ec241 704 typedef struct
mbed_official 155:8435094ec241 705 {
mbed_official 155:8435094ec241 706 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 707 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
mbed_official 155:8435094ec241 708 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
mbed_official 155:8435094ec241 709 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
mbed_official 155:8435094ec241 710 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
mbed_official 155:8435094ec241 711 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
mbed_official 155:8435094ec241 712 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
mbed_official 155:8435094ec241 713 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
mbed_official 155:8435094ec241 714 uint32_t RESERVED0; /*!< Reserved, 0x20 */
mbed_official 155:8435094ec241 715 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
mbed_official 155:8435094ec241 716 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
mbed_official 155:8435094ec241 717 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
mbed_official 155:8435094ec241 718 }HRTIM_Master_TypeDef;
mbed_official 155:8435094ec241 719
mbed_official 155:8435094ec241 720 /* HRTIM slave definition */
mbed_official 155:8435094ec241 721 typedef struct
mbed_official 155:8435094ec241 722 {
mbed_official 155:8435094ec241 723 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 724 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
mbed_official 155:8435094ec241 725 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
mbed_official 155:8435094ec241 726 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 155:8435094ec241 727 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
mbed_official 155:8435094ec241 728 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
mbed_official 155:8435094ec241 729 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
mbed_official 155:8435094ec241 730 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
mbed_official 155:8435094ec241 731 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
mbed_official 155:8435094ec241 732 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
mbed_official 155:8435094ec241 733 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
mbed_official 155:8435094ec241 734 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
mbed_official 155:8435094ec241 735 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
mbed_official 155:8435094ec241 736 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
mbed_official 155:8435094ec241 737 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
mbed_official 155:8435094ec241 738 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
mbed_official 155:8435094ec241 739 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
mbed_official 155:8435094ec241 740 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
mbed_official 155:8435094ec241 741 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
mbed_official 155:8435094ec241 742 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
mbed_official 155:8435094ec241 743 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
mbed_official 155:8435094ec241 744 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
mbed_official 155:8435094ec241 745 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
mbed_official 155:8435094ec241 746 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
mbed_official 155:8435094ec241 747 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
mbed_official 155:8435094ec241 748 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
mbed_official 155:8435094ec241 749 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
mbed_official 155:8435094ec241 750 uint32_t RESERVED0[5];/*!< Reserved, */
mbed_official 155:8435094ec241 751 }HRTIM_Timerx_TypeDef;
mbed_official 155:8435094ec241 752
mbed_official 155:8435094ec241 753 /* HRTIM common register definition */
mbed_official 155:8435094ec241 754 typedef struct
mbed_official 155:8435094ec241 755 {
mbed_official 155:8435094ec241 756 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
mbed_official 155:8435094ec241 757 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
mbed_official 155:8435094ec241 758 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
mbed_official 155:8435094ec241 759 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
mbed_official 155:8435094ec241 760 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
mbed_official 155:8435094ec241 761 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
mbed_official 155:8435094ec241 762 __IO uint32_t DISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
mbed_official 155:8435094ec241 763 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
mbed_official 155:8435094ec241 764 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
mbed_official 155:8435094ec241 765 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
mbed_official 155:8435094ec241 766 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
mbed_official 155:8435094ec241 767 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
mbed_official 155:8435094ec241 768 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
mbed_official 155:8435094ec241 769 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
mbed_official 155:8435094ec241 770 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
mbed_official 155:8435094ec241 771 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
mbed_official 155:8435094ec241 772 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
mbed_official 155:8435094ec241 773 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
mbed_official 155:8435094ec241 774 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
mbed_official 155:8435094ec241 775 __IO uint32_t DLLCR; /*!< HRTIM DLL control register, Address offset: 0x4C */
mbed_official 155:8435094ec241 776 __IO uint32_t FLTINxR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
mbed_official 155:8435094ec241 777 __IO uint32_t FLTINxR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
mbed_official 155:8435094ec241 778 __IO uint32_t BDMUPDR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
mbed_official 155:8435094ec241 779 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
mbed_official 155:8435094ec241 780 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
mbed_official 155:8435094ec241 781 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
mbed_official 155:8435094ec241 782 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
mbed_official 155:8435094ec241 783 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
mbed_official 155:8435094ec241 784 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
mbed_official 155:8435094ec241 785 }HRTIM_Common_TypeDef;
mbed_official 155:8435094ec241 786
mbed_official 155:8435094ec241 787 /* HRTIM register definition */
mbed_official 155:8435094ec241 788 typedef struct {
mbed_official 155:8435094ec241 789 HRTIM_Master_TypeDef HRTIM_MASTER;
mbed_official 155:8435094ec241 790 uint32_t RESERVED0[20];
mbed_official 155:8435094ec241 791 HRTIM_Timerx_TypeDef HRTIM_TIMERx[5];
mbed_official 155:8435094ec241 792 uint32_t RESERVED1[32];
mbed_official 155:8435094ec241 793 HRTIM_Common_TypeDef HRTIM_COMMON;
mbed_official 155:8435094ec241 794 }HRTIM_TypeDef;
mbed_official 155:8435094ec241 795
mbed_official 155:8435094ec241 796 /**
mbed_official 155:8435094ec241 797 * @brief Operational Amplifier (OPAMP)
mbed_official 155:8435094ec241 798 */
mbed_official 155:8435094ec241 799
mbed_official 155:8435094ec241 800 typedef struct
mbed_official 155:8435094ec241 801 {
mbed_official 155:8435094ec241 802 __IO uint32_t CSR; /*!< OPAMP control and status register, Address offset: 0x00 */
mbed_official 155:8435094ec241 803 } OPAMP_TypeDef;
mbed_official 155:8435094ec241 804
mbed_official 155:8435094ec241 805
mbed_official 155:8435094ec241 806 /**
mbed_official 155:8435094ec241 807 * @brief System configuration controller
mbed_official 155:8435094ec241 808 */
mbed_official 155:8435094ec241 809
mbed_official 155:8435094ec241 810 typedef struct
mbed_official 155:8435094ec241 811 {
mbed_official 155:8435094ec241 812 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
mbed_official 155:8435094ec241 813 __IO uint32_t RCR; /*!< SYSCFG CCM SRAM protection register, Address offset: 0x04 */
mbed_official 155:8435094ec241 814 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x14-0x08 */
mbed_official 155:8435094ec241 815 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
mbed_official 155:8435094ec241 816 __IO uint32_t RESERVED0; /*!< Reserved, 0x1C */
mbed_official 155:8435094ec241 817 __IO uint32_t RESERVED1; /*!< Reserved, 0x20 */
mbed_official 155:8435094ec241 818 __IO uint32_t RESERVED2; /*!< Reserved, 0x24 */
mbed_official 155:8435094ec241 819 __IO uint32_t RESERVED4; /*!< Reserved, 0x28 */
mbed_official 155:8435094ec241 820 __IO uint32_t RESERVED5; /*!< Reserved, 0x2C */
mbed_official 155:8435094ec241 821 __IO uint32_t RESERVED6; /*!< Reserved, 0x30 */
mbed_official 155:8435094ec241 822 __IO uint32_t RESERVED7; /*!< Reserved, 0x34 */
mbed_official 155:8435094ec241 823 __IO uint32_t RESERVED8; /*!< Reserved, 0x38 */
mbed_official 155:8435094ec241 824 __IO uint32_t RESERVED9; /*!< Reserved, 0x3C */
mbed_official 155:8435094ec241 825 __IO uint32_t RESERVED10; /*!< Reserved, 0x40 */
mbed_official 155:8435094ec241 826 __IO uint32_t RESERVED11; /*!< Reserved, 0x44 */
mbed_official 155:8435094ec241 827 __IO uint32_t RESERVED12; /*!< Reserved, 0x48 */
mbed_official 155:8435094ec241 828 __IO uint32_t RESERVED13; /*!< Reserved, 0x4C */
mbed_official 155:8435094ec241 829 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x50 */
mbed_official 155:8435094ec241 830 } SYSCFG_TypeDef;
mbed_official 155:8435094ec241 831
mbed_official 155:8435094ec241 832 /**
mbed_official 155:8435094ec241 833 * @brief Inter-integrated Circuit Interface
mbed_official 155:8435094ec241 834 */
mbed_official 155:8435094ec241 835
mbed_official 155:8435094ec241 836 typedef struct
mbed_official 155:8435094ec241 837 {
mbed_official 155:8435094ec241 838 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
mbed_official 155:8435094ec241 839 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
mbed_official 155:8435094ec241 840 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
mbed_official 155:8435094ec241 841 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
mbed_official 155:8435094ec241 842 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
mbed_official 155:8435094ec241 843 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
mbed_official 155:8435094ec241 844 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
mbed_official 155:8435094ec241 845 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
mbed_official 155:8435094ec241 846 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
mbed_official 155:8435094ec241 847 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
mbed_official 155:8435094ec241 848 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
mbed_official 155:8435094ec241 849 }I2C_TypeDef;
mbed_official 155:8435094ec241 850
mbed_official 155:8435094ec241 851 /**
mbed_official 155:8435094ec241 852 * @brief Independent WATCHDOG
mbed_official 155:8435094ec241 853 */
mbed_official 155:8435094ec241 854
mbed_official 155:8435094ec241 855 typedef struct
mbed_official 155:8435094ec241 856 {
mbed_official 155:8435094ec241 857 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
mbed_official 155:8435094ec241 858 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
mbed_official 155:8435094ec241 859 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
mbed_official 155:8435094ec241 860 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
mbed_official 155:8435094ec241 861 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
mbed_official 155:8435094ec241 862 } IWDG_TypeDef;
mbed_official 155:8435094ec241 863
mbed_official 155:8435094ec241 864 /**
mbed_official 155:8435094ec241 865 * @brief Power Control
mbed_official 155:8435094ec241 866 */
mbed_official 155:8435094ec241 867
mbed_official 155:8435094ec241 868 typedef struct
mbed_official 155:8435094ec241 869 {
mbed_official 155:8435094ec241 870 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 871 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
mbed_official 155:8435094ec241 872 } PWR_TypeDef;
mbed_official 155:8435094ec241 873
mbed_official 155:8435094ec241 874 /**
mbed_official 155:8435094ec241 875 * @brief Reset and Clock Control
mbed_official 155:8435094ec241 876 */
mbed_official 155:8435094ec241 877 typedef struct
mbed_official 155:8435094ec241 878 {
mbed_official 155:8435094ec241 879 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 880 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
mbed_official 155:8435094ec241 881 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
mbed_official 155:8435094ec241 882 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
mbed_official 155:8435094ec241 883 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
mbed_official 155:8435094ec241 884 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
mbed_official 155:8435094ec241 885 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
mbed_official 155:8435094ec241 886 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
mbed_official 155:8435094ec241 887 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
mbed_official 155:8435094ec241 888 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
mbed_official 155:8435094ec241 889 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
mbed_official 155:8435094ec241 890 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
mbed_official 155:8435094ec241 891 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
mbed_official 155:8435094ec241 892 } RCC_TypeDef;
mbed_official 155:8435094ec241 893
mbed_official 155:8435094ec241 894 /**
mbed_official 155:8435094ec241 895 * @brief Real-Time Clock
mbed_official 155:8435094ec241 896 */
mbed_official 155:8435094ec241 897
mbed_official 155:8435094ec241 898 typedef struct
mbed_official 155:8435094ec241 899 {
mbed_official 155:8435094ec241 900 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
mbed_official 155:8435094ec241 901 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
mbed_official 155:8435094ec241 902 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
mbed_official 155:8435094ec241 903 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
mbed_official 155:8435094ec241 904 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
mbed_official 155:8435094ec241 905 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
mbed_official 155:8435094ec241 906 uint32_t RESERVED0; /*!< Reserved, 0x18 */
mbed_official 155:8435094ec241 907 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
mbed_official 155:8435094ec241 908 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
mbed_official 155:8435094ec241 909 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
mbed_official 155:8435094ec241 910 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
mbed_official 155:8435094ec241 911 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
mbed_official 155:8435094ec241 912 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
mbed_official 155:8435094ec241 913 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
mbed_official 155:8435094ec241 914 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
mbed_official 155:8435094ec241 915 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
mbed_official 155:8435094ec241 916 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
mbed_official 155:8435094ec241 917 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
mbed_official 155:8435094ec241 918 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
mbed_official 155:8435094ec241 919 uint32_t RESERVED7; /*!< Reserved, 0x4C */
mbed_official 155:8435094ec241 920 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
mbed_official 155:8435094ec241 921 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
mbed_official 155:8435094ec241 922 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
mbed_official 155:8435094ec241 923 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
mbed_official 155:8435094ec241 924 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
mbed_official 155:8435094ec241 925 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
mbed_official 155:8435094ec241 926 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
mbed_official 155:8435094ec241 927 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
mbed_official 155:8435094ec241 928 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
mbed_official 155:8435094ec241 929 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
mbed_official 155:8435094ec241 930 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
mbed_official 155:8435094ec241 931 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
mbed_official 155:8435094ec241 932 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
mbed_official 155:8435094ec241 933 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
mbed_official 155:8435094ec241 934 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
mbed_official 155:8435094ec241 935 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
mbed_official 155:8435094ec241 936 } RTC_TypeDef;
mbed_official 155:8435094ec241 937
mbed_official 155:8435094ec241 938
mbed_official 155:8435094ec241 939 /**
mbed_official 155:8435094ec241 940 * @brief Serial Peripheral Interface
mbed_official 155:8435094ec241 941 */
mbed_official 155:8435094ec241 942
mbed_official 155:8435094ec241 943 typedef struct
mbed_official 155:8435094ec241 944 {
mbed_official 155:8435094ec241 945 __IO uint16_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
mbed_official 155:8435094ec241 946 uint16_t RESERVED0; /*!< Reserved, 0x02 */
mbed_official 155:8435094ec241 947 __IO uint16_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
mbed_official 155:8435094ec241 948 uint16_t RESERVED1; /*!< Reserved, 0x06 */
mbed_official 155:8435094ec241 949 __IO uint16_t SR; /*!< SPI Status register, Address offset: 0x08 */
mbed_official 155:8435094ec241 950 uint16_t RESERVED2; /*!< Reserved, 0x0A */
mbed_official 155:8435094ec241 951 __IO uint16_t DR; /*!< SPI data register, Address offset: 0x0C */
mbed_official 155:8435094ec241 952 uint16_t RESERVED3; /*!< Reserved, 0x0E */
mbed_official 155:8435094ec241 953 __IO uint16_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
mbed_official 155:8435094ec241 954 uint16_t RESERVED4; /*!< Reserved, 0x12 */
mbed_official 155:8435094ec241 955 __IO uint16_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
mbed_official 155:8435094ec241 956 uint16_t RESERVED5; /*!< Reserved, 0x16 */
mbed_official 155:8435094ec241 957 __IO uint16_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
mbed_official 155:8435094ec241 958 uint16_t RESERVED6; /*!< Reserved, 0x1A */
mbed_official 155:8435094ec241 959 __IO uint16_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
mbed_official 155:8435094ec241 960 uint16_t RESERVED7; /*!< Reserved, 0x1E */
mbed_official 155:8435094ec241 961 __IO uint16_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
mbed_official 155:8435094ec241 962 uint16_t RESERVED8; /*!< Reserved, 0x22 */
mbed_official 155:8435094ec241 963 } SPI_TypeDef;
mbed_official 155:8435094ec241 964
mbed_official 155:8435094ec241 965 /**
mbed_official 155:8435094ec241 966 * @brief TIM
mbed_official 155:8435094ec241 967 */
mbed_official 155:8435094ec241 968 typedef struct
mbed_official 155:8435094ec241 969 {
mbed_official 155:8435094ec241 970 __IO uint16_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
mbed_official 155:8435094ec241 971 uint16_t RESERVED0; /*!< Reserved, 0x02 */
mbed_official 155:8435094ec241 972 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
mbed_official 155:8435094ec241 973 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
mbed_official 155:8435094ec241 974 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
mbed_official 155:8435094ec241 975 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
mbed_official 155:8435094ec241 976 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
mbed_official 155:8435094ec241 977 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
mbed_official 155:8435094ec241 978 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
mbed_official 155:8435094ec241 979 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
mbed_official 155:8435094ec241 980 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
mbed_official 155:8435094ec241 981 __IO uint16_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
mbed_official 155:8435094ec241 982 uint16_t RESERVED9; /*!< Reserved, 0x2A */
mbed_official 155:8435094ec241 983 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
mbed_official 155:8435094ec241 984 __IO uint16_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
mbed_official 155:8435094ec241 985 uint16_t RESERVED10; /*!< Reserved, 0x32 */
mbed_official 155:8435094ec241 986 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
mbed_official 155:8435094ec241 987 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
mbed_official 155:8435094ec241 988 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
mbed_official 155:8435094ec241 989 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
mbed_official 155:8435094ec241 990 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
mbed_official 155:8435094ec241 991 __IO uint16_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
mbed_official 155:8435094ec241 992 uint16_t RESERVED12; /*!< Reserved, 0x4A */
mbed_official 155:8435094ec241 993 __IO uint16_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
mbed_official 155:8435094ec241 994 uint16_t RESERVED13; /*!< Reserved, 0x4E */
mbed_official 155:8435094ec241 995 __IO uint16_t OR; /*!< TIM option register, Address offset: 0x50 */
mbed_official 155:8435094ec241 996 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
mbed_official 155:8435094ec241 997 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
mbed_official 155:8435094ec241 998 __IO uint32_t CCR6; /*!< TIM capture/compare register 4, Address offset: 0x5C */
mbed_official 155:8435094ec241 999 } TIM_TypeDef;
mbed_official 155:8435094ec241 1000
mbed_official 155:8435094ec241 1001
mbed_official 155:8435094ec241 1002 /**
mbed_official 155:8435094ec241 1003 * @brief Touch Sensing Controller (TSC)
mbed_official 155:8435094ec241 1004 */
mbed_official 155:8435094ec241 1005 typedef struct
mbed_official 155:8435094ec241 1006 {
mbed_official 155:8435094ec241 1007 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 1008 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
mbed_official 155:8435094ec241 1009 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
mbed_official 155:8435094ec241 1010 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
mbed_official 155:8435094ec241 1011 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
mbed_official 155:8435094ec241 1012 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
mbed_official 155:8435094ec241 1013 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
mbed_official 155:8435094ec241 1014 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
mbed_official 155:8435094ec241 1015 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
mbed_official 155:8435094ec241 1016 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
mbed_official 155:8435094ec241 1017 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
mbed_official 155:8435094ec241 1018 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
mbed_official 155:8435094ec241 1019 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
mbed_official 155:8435094ec241 1020 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
mbed_official 155:8435094ec241 1021 } TSC_TypeDef;
mbed_official 155:8435094ec241 1022
mbed_official 155:8435094ec241 1023 /**
mbed_official 155:8435094ec241 1024 * @brief Universal Synchronous Asynchronous Receiver Transmitter
mbed_official 155:8435094ec241 1025 */
mbed_official 155:8435094ec241 1026
mbed_official 155:8435094ec241 1027 typedef struct
mbed_official 155:8435094ec241 1028 {
mbed_official 155:8435094ec241 1029 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
mbed_official 155:8435094ec241 1030 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
mbed_official 155:8435094ec241 1031 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
mbed_official 155:8435094ec241 1032 __IO uint16_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
mbed_official 155:8435094ec241 1033 uint16_t RESERVED1; /*!< Reserved, 0x0E */
mbed_official 155:8435094ec241 1034 __IO uint16_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
mbed_official 155:8435094ec241 1035 uint16_t RESERVED2; /*!< Reserved, 0x12 */
mbed_official 155:8435094ec241 1036 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
mbed_official 155:8435094ec241 1037 __IO uint16_t RQR; /*!< USART Request register, Address offset: 0x18 */
mbed_official 155:8435094ec241 1038 uint16_t RESERVED3; /*!< Reserved, 0x1A */
mbed_official 155:8435094ec241 1039 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
mbed_official 155:8435094ec241 1040 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
mbed_official 155:8435094ec241 1041 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
mbed_official 155:8435094ec241 1042 uint16_t RESERVED4; /*!< Reserved, 0x26 */
mbed_official 155:8435094ec241 1043 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
mbed_official 155:8435094ec241 1044 uint16_t RESERVED5; /*!< Reserved, 0x2A */
mbed_official 155:8435094ec241 1045 } USART_TypeDef;
mbed_official 155:8435094ec241 1046
mbed_official 155:8435094ec241 1047 /**
mbed_official 155:8435094ec241 1048 * @brief Window WATCHDOG
mbed_official 155:8435094ec241 1049 */
mbed_official 155:8435094ec241 1050 typedef struct
mbed_official 155:8435094ec241 1051 {
mbed_official 155:8435094ec241 1052 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
mbed_official 155:8435094ec241 1053 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
mbed_official 155:8435094ec241 1054 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
mbed_official 155:8435094ec241 1055 } WWDG_TypeDef;
mbed_official 155:8435094ec241 1056
mbed_official 155:8435094ec241 1057
mbed_official 155:8435094ec241 1058 /** @addtogroup Peripheral_memory_map
mbed_official 155:8435094ec241 1059 * @{
mbed_official 155:8435094ec241 1060 */
mbed_official 155:8435094ec241 1061
mbed_official 155:8435094ec241 1062 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
mbed_official 155:8435094ec241 1063 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
mbed_official 155:8435094ec241 1064 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
mbed_official 155:8435094ec241 1065
mbed_official 155:8435094ec241 1066 #define SRAM_BB_BASE ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
mbed_official 155:8435094ec241 1067 #define PERIPH_BB_BASE ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
mbed_official 155:8435094ec241 1068
mbed_official 155:8435094ec241 1069
mbed_official 155:8435094ec241 1070 /*!< Peripheral memory map */
mbed_official 155:8435094ec241 1071 #define APB1PERIPH_BASE PERIPH_BASE
mbed_official 155:8435094ec241 1072 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000)
mbed_official 155:8435094ec241 1073 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000)
mbed_official 155:8435094ec241 1074 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
mbed_official 155:8435094ec241 1075 #define AHB3PERIPH_BASE (PERIPH_BASE + 0x10000000)
mbed_official 155:8435094ec241 1076
mbed_official 155:8435094ec241 1077 /*!< APB1 peripherals */
mbed_official 155:8435094ec241 1078 #define TIM2_BASE (APB1PERIPH_BASE + 0x00000000)
mbed_official 155:8435094ec241 1079 #define TIM3_BASE (APB1PERIPH_BASE + 0x00000400)
mbed_official 155:8435094ec241 1080 #define TIM4_BASE (APB1PERIPH_BASE + 0x00000800)
mbed_official 155:8435094ec241 1081 #define TIM6_BASE (APB1PERIPH_BASE + 0x00001000)
mbed_official 155:8435094ec241 1082 #define TIM7_BASE (APB1PERIPH_BASE + 0x00001400)
mbed_official 155:8435094ec241 1083 #define RTC_BASE (APB1PERIPH_BASE + 0x00002800)
mbed_official 155:8435094ec241 1084 #define WWDG_BASE (APB1PERIPH_BASE + 0x00002C00)
mbed_official 155:8435094ec241 1085 #define IWDG_BASE (APB1PERIPH_BASE + 0x00003000)
mbed_official 155:8435094ec241 1086 #define I2S2ext_BASE (APB1PERIPH_BASE + 0x00003400)
mbed_official 155:8435094ec241 1087 #define SPI2_BASE (APB1PERIPH_BASE + 0x00003800)
mbed_official 155:8435094ec241 1088 #define SPI3_BASE (APB1PERIPH_BASE + 0x00003C00)
mbed_official 155:8435094ec241 1089 #define I2S3ext_BASE (APB1PERIPH_BASE + 0x00004000)
mbed_official 155:8435094ec241 1090 #define USART2_BASE (APB1PERIPH_BASE + 0x00004400)
mbed_official 155:8435094ec241 1091 #define USART3_BASE (APB1PERIPH_BASE + 0x00004800)
mbed_official 155:8435094ec241 1092 #define UART4_BASE (APB1PERIPH_BASE + 0x00004C00)
mbed_official 155:8435094ec241 1093 #define UART5_BASE (APB1PERIPH_BASE + 0x00005000)
mbed_official 155:8435094ec241 1094 #define I2C1_BASE (APB1PERIPH_BASE + 0x00005400)
mbed_official 155:8435094ec241 1095 #define I2C2_BASE (APB1PERIPH_BASE + 0x00005800)
mbed_official 155:8435094ec241 1096 #define CAN1_BASE (APB1PERIPH_BASE + 0x00006400)
mbed_official 155:8435094ec241 1097 #define PWR_BASE (APB1PERIPH_BASE + 0x00007000)
mbed_official 155:8435094ec241 1098 #define DAC1_BASE (APB1PERIPH_BASE + 0x00007400)
mbed_official 155:8435094ec241 1099 #define I2C3_BASE (APB1PERIPH_BASE + 0x00007800)
mbed_official 155:8435094ec241 1100 #define DAC2_BASE (APB1PERIPH_BASE + 0x00009800)
mbed_official 155:8435094ec241 1101 #define DAC_BASE DAC1_BASE
mbed_official 155:8435094ec241 1102
mbed_official 155:8435094ec241 1103 /*!< APB2 peripherals */
mbed_official 155:8435094ec241 1104 #define SYSCFG_BASE (APB2PERIPH_BASE + 0x00000000)
mbed_official 155:8435094ec241 1105 #define COMP_BASE (APB2PERIPH_BASE + 0x0000001C)
mbed_official 155:8435094ec241 1106 #define COMP1_BASE (APB2PERIPH_BASE + 0x0000001C)
mbed_official 155:8435094ec241 1107 #define COMP2_BASE (APB2PERIPH_BASE + 0x00000020)
mbed_official 155:8435094ec241 1108 #define COMP3_BASE (APB2PERIPH_BASE + 0x00000024)
mbed_official 155:8435094ec241 1109 #define COMP4_BASE (APB2PERIPH_BASE + 0x00000028)
mbed_official 155:8435094ec241 1110 #define COMP5_BASE (APB2PERIPH_BASE + 0x0000002C)
mbed_official 155:8435094ec241 1111 #define COMP6_BASE (APB2PERIPH_BASE + 0x00000030)
mbed_official 155:8435094ec241 1112 #define COMP7_BASE (APB2PERIPH_BASE + 0x00000034)
mbed_official 155:8435094ec241 1113 #define OPAMP_BASE (APB2PERIPH_BASE + 0x00000038)
mbed_official 155:8435094ec241 1114 #define OPAMP1_BASE (APB2PERIPH_BASE + 0x00000038)
mbed_official 155:8435094ec241 1115 #define OPAMP2_BASE (APB2PERIPH_BASE + 0x0000003C)
mbed_official 155:8435094ec241 1116 #define OPAMP3_BASE (APB2PERIPH_BASE + 0x00000040)
mbed_official 155:8435094ec241 1117 #define OPAMP4_BASE (APB2PERIPH_BASE + 0x00000044)
mbed_official 155:8435094ec241 1118 #define EXTI_BASE (APB2PERIPH_BASE + 0x00000400)
mbed_official 155:8435094ec241 1119 #define TIM1_BASE (APB2PERIPH_BASE + 0x00002C00)
mbed_official 155:8435094ec241 1120 #define SPI1_BASE (APB2PERIPH_BASE + 0x00003000)
mbed_official 155:8435094ec241 1121 #define TIM8_BASE (APB2PERIPH_BASE + 0x00003400)
mbed_official 155:8435094ec241 1122 #define USART1_BASE (APB2PERIPH_BASE + 0x00003800)
mbed_official 155:8435094ec241 1123 #define TIM15_BASE (APB2PERIPH_BASE + 0x00004000)
mbed_official 155:8435094ec241 1124 #define TIM16_BASE (APB2PERIPH_BASE + 0x00004400)
mbed_official 155:8435094ec241 1125 #define TIM17_BASE (APB2PERIPH_BASE + 0x00004800)
mbed_official 155:8435094ec241 1126 #define HRTIM1_BASE (APB2PERIPH_BASE + 0x00007400)
mbed_official 155:8435094ec241 1127 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080)
mbed_official 155:8435094ec241 1128 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100)
mbed_official 155:8435094ec241 1129 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180)
mbed_official 155:8435094ec241 1130 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200)
mbed_official 155:8435094ec241 1131 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280)
mbed_official 155:8435094ec241 1132 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380)
mbed_official 155:8435094ec241 1133
mbed_official 155:8435094ec241 1134 /*!< AHB1 peripherals */
mbed_official 155:8435094ec241 1135 #define DMA1_BASE (AHB1PERIPH_BASE + 0x00000000)
mbed_official 155:8435094ec241 1136 #define DMA1_Channel1_BASE (AHB1PERIPH_BASE + 0x00000008)
mbed_official 155:8435094ec241 1137 #define DMA1_Channel2_BASE (AHB1PERIPH_BASE + 0x0000001C)
mbed_official 155:8435094ec241 1138 #define DMA1_Channel3_BASE (AHB1PERIPH_BASE + 0x00000030)
mbed_official 155:8435094ec241 1139 #define DMA1_Channel4_BASE (AHB1PERIPH_BASE + 0x00000044)
mbed_official 155:8435094ec241 1140 #define DMA1_Channel5_BASE (AHB1PERIPH_BASE + 0x00000058)
mbed_official 155:8435094ec241 1141 #define DMA1_Channel6_BASE (AHB1PERIPH_BASE + 0x0000006C)
mbed_official 155:8435094ec241 1142 #define DMA1_Channel7_BASE (AHB1PERIPH_BASE + 0x00000080)
mbed_official 155:8435094ec241 1143 #define DMA2_BASE (AHB1PERIPH_BASE + 0x00000400)
mbed_official 155:8435094ec241 1144 #define DMA2_Channel1_BASE (AHB1PERIPH_BASE + 0x00000408)
mbed_official 155:8435094ec241 1145 #define DMA2_Channel2_BASE (AHB1PERIPH_BASE + 0x0000041C)
mbed_official 155:8435094ec241 1146 #define DMA2_Channel3_BASE (AHB1PERIPH_BASE + 0x00000430)
mbed_official 155:8435094ec241 1147 #define DMA2_Channel4_BASE (AHB1PERIPH_BASE + 0x00000444)
mbed_official 155:8435094ec241 1148 #define DMA2_Channel5_BASE (AHB1PERIPH_BASE + 0x00000458)
mbed_official 155:8435094ec241 1149 #define RCC_BASE (AHB1PERIPH_BASE + 0x00001000)
mbed_official 155:8435094ec241 1150 #define FLASH_R_BASE (AHB1PERIPH_BASE + 0x00002000) /*!< Flash registers base address */
mbed_official 155:8435094ec241 1151 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< Flash Option Bytes base address */
mbed_official 155:8435094ec241 1152 #define CRC_BASE (AHB1PERIPH_BASE + 0x00003000)
mbed_official 155:8435094ec241 1153 #define TSC_BASE (AHB1PERIPH_BASE + 0x00004000)
mbed_official 155:8435094ec241 1154
mbed_official 155:8435094ec241 1155 /*!< AHB2 peripherals */
mbed_official 155:8435094ec241 1156 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x0000)
mbed_official 155:8435094ec241 1157 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x0400)
mbed_official 155:8435094ec241 1158 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x0800)
mbed_official 155:8435094ec241 1159 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x0C00)
mbed_official 155:8435094ec241 1160 #define GPIOE_BASE (AHB2PERIPH_BASE + 0x1000)
mbed_official 155:8435094ec241 1161 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x1400)
mbed_official 155:8435094ec241 1162
mbed_official 155:8435094ec241 1163 /*!< AHB3 peripherals */
mbed_official 155:8435094ec241 1164 #define ADC1_BASE (AHB3PERIPH_BASE + 0x0000)
mbed_official 155:8435094ec241 1165 #define ADC2_BASE (AHB3PERIPH_BASE + 0x0100)
mbed_official 155:8435094ec241 1166 #define ADC1_2_BASE (AHB3PERIPH_BASE + 0x0300)
mbed_official 155:8435094ec241 1167 #define ADC3_BASE (AHB3PERIPH_BASE + 0x0400)
mbed_official 155:8435094ec241 1168 #define ADC4_BASE (AHB3PERIPH_BASE + 0x0500)
mbed_official 155:8435094ec241 1169 #define ADC3_4_BASE (AHB3PERIPH_BASE + 0x0700)
mbed_official 155:8435094ec241 1170
mbed_official 155:8435094ec241 1171 #define DBGMCU_BASE ((uint32_t)0xE0042000) /*!< Debug MCU registers base address */
mbed_official 155:8435094ec241 1172 /**
mbed_official 155:8435094ec241 1173 * @}
mbed_official 155:8435094ec241 1174 */
mbed_official 155:8435094ec241 1175
mbed_official 155:8435094ec241 1176 /** @addtogroup Peripheral_declaration
mbed_official 155:8435094ec241 1177 * @{
mbed_official 155:8435094ec241 1178 */
mbed_official 155:8435094ec241 1179 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
mbed_official 155:8435094ec241 1180 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
mbed_official 155:8435094ec241 1181 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
mbed_official 155:8435094ec241 1182 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
mbed_official 155:8435094ec241 1183 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
mbed_official 155:8435094ec241 1184 #define RTC ((RTC_TypeDef *) RTC_BASE)
mbed_official 155:8435094ec241 1185 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
mbed_official 155:8435094ec241 1186 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
mbed_official 155:8435094ec241 1187 #define I2S2ext ((SPI_TypeDef *) I2S2ext_BASE)
mbed_official 155:8435094ec241 1188 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
mbed_official 155:8435094ec241 1189 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
mbed_official 155:8435094ec241 1190 #define I2S3ext ((SPI_TypeDef *) I2S3ext_BASE)
mbed_official 155:8435094ec241 1191 #define USART2 ((USART_TypeDef *) USART2_BASE)
mbed_official 155:8435094ec241 1192 #define USART3 ((USART_TypeDef *) USART3_BASE)
mbed_official 155:8435094ec241 1193 #define UART4 ((USART_TypeDef *) UART4_BASE)
mbed_official 155:8435094ec241 1194 #define UART5 ((USART_TypeDef *) UART5_BASE)
mbed_official 155:8435094ec241 1195 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
mbed_official 155:8435094ec241 1196 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
mbed_official 155:8435094ec241 1197 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
mbed_official 155:8435094ec241 1198 #define CAN1 ((CAN_TypeDef *) CAN1_BASE)
mbed_official 155:8435094ec241 1199 #define PWR ((PWR_TypeDef *) PWR_BASE)
mbed_official 155:8435094ec241 1200 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
mbed_official 155:8435094ec241 1201 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
mbed_official 155:8435094ec241 1202 #define DAC DAC1
mbed_official 155:8435094ec241 1203 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
mbed_official 155:8435094ec241 1204 #define COMP ((COMP_TypeDef *) COMP_BASE)
mbed_official 155:8435094ec241 1205 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
mbed_official 155:8435094ec241 1206 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
mbed_official 155:8435094ec241 1207 #define COMP3 ((COMP_TypeDef *) COMP3_BASE)
mbed_official 155:8435094ec241 1208 #define COMP4 ((COMP_TypeDef *) COMP4_BASE)
mbed_official 155:8435094ec241 1209 #define COMP5 ((COMP_TypeDef *) COMP5_BASE)
mbed_official 155:8435094ec241 1210 #define COMP6 ((COMP_TypeDef *) COMP6_BASE)
mbed_official 155:8435094ec241 1211 #define COMP7 ((COMP_TypeDef *) COMP7_BASE)
mbed_official 155:8435094ec241 1212 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
mbed_official 155:8435094ec241 1213 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
mbed_official 155:8435094ec241 1214 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
mbed_official 155:8435094ec241 1215 #define OPAMP3 ((OPAMP_TypeDef *) OPAMP3_BASE)
mbed_official 155:8435094ec241 1216 #define OPAMP4 ((OPAMP_TypeDef *) OPAMP4_BASE)
mbed_official 155:8435094ec241 1217 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
mbed_official 155:8435094ec241 1218 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
mbed_official 155:8435094ec241 1219 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
mbed_official 155:8435094ec241 1220 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
mbed_official 155:8435094ec241 1221 #define USART1 ((USART_TypeDef *) USART1_BASE)
mbed_official 155:8435094ec241 1222 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
mbed_official 155:8435094ec241 1223 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
mbed_official 155:8435094ec241 1224 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
mbed_official 155:8435094ec241 1225 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
mbed_official 155:8435094ec241 1226 #define HRTIM1_TIMA ((HRTIM_TIM_TypeDef *) HRTIM1_TIMA_BASE)
mbed_official 155:8435094ec241 1227 #define HRTIM1_TIMB ((HRTIM_TIM_TypeDef *) HRTIM1_TIMB_BASE)
mbed_official 155:8435094ec241 1228 #define HRTIM1_TIMC ((HRTIM_TIM_TypeDef *) HRTIM1_TIMC_BASE)
mbed_official 155:8435094ec241 1229 #define HRTIM1_TIMD ((HRTIM_TIM_TypeDef *) HRTIM1_TIMD_BASE)
mbed_official 155:8435094ec241 1230 #define HRTIM1_TIME ((HRTIM_TIM_TypeDef *) HRTIM1_TIME_BASE)
mbed_official 155:8435094ec241 1231 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
mbed_official 155:8435094ec241 1232 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
mbed_official 155:8435094ec241 1233 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
mbed_official 155:8435094ec241 1234 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
mbed_official 155:8435094ec241 1235 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
mbed_official 155:8435094ec241 1236 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
mbed_official 155:8435094ec241 1237 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
mbed_official 155:8435094ec241 1238 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
mbed_official 155:8435094ec241 1239 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
mbed_official 155:8435094ec241 1240 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
mbed_official 155:8435094ec241 1241 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
mbed_official 155:8435094ec241 1242 #define DMA2_Channel1 ((DMA_Channel_TypeDef *) DMA2_Channel1_BASE)
mbed_official 155:8435094ec241 1243 #define DMA2_Channel2 ((DMA_Channel_TypeDef *) DMA2_Channel2_BASE)
mbed_official 155:8435094ec241 1244 #define DMA2_Channel3 ((DMA_Channel_TypeDef *) DMA2_Channel3_BASE)
mbed_official 155:8435094ec241 1245 #define DMA2_Channel4 ((DMA_Channel_TypeDef *) DMA2_Channel4_BASE)
mbed_official 155:8435094ec241 1246 #define DMA2_Channel5 ((DMA_Channel_TypeDef *) DMA2_Channel5_BASE)
mbed_official 155:8435094ec241 1247 #define RCC ((RCC_TypeDef *) RCC_BASE)
mbed_official 155:8435094ec241 1248 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
mbed_official 155:8435094ec241 1249 #define OB ((OB_TypeDef *) OB_BASE)
mbed_official 155:8435094ec241 1250 #define CRC ((CRC_TypeDef *) CRC_BASE)
mbed_official 155:8435094ec241 1251 #define TSC ((TSC_TypeDef *) TSC_BASE)
mbed_official 155:8435094ec241 1252 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
mbed_official 155:8435094ec241 1253 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
mbed_official 155:8435094ec241 1254 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
mbed_official 155:8435094ec241 1255 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
mbed_official 155:8435094ec241 1256 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
mbed_official 155:8435094ec241 1257 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
mbed_official 155:8435094ec241 1258 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
mbed_official 155:8435094ec241 1259 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
mbed_official 155:8435094ec241 1260 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
mbed_official 155:8435094ec241 1261 #define ADC4 ((ADC_TypeDef *) ADC4_BASE)
mbed_official 155:8435094ec241 1262 #define ADC1_2 ((ADC_Common_TypeDef *) ADC1_2_BASE)
mbed_official 155:8435094ec241 1263 #define ADC3_4 ((ADC_Common_TypeDef *) ADC3_4_BASE)
mbed_official 155:8435094ec241 1264 /**
mbed_official 155:8435094ec241 1265 * @}
mbed_official 155:8435094ec241 1266 */
mbed_official 155:8435094ec241 1267
mbed_official 155:8435094ec241 1268 /** @addtogroup Exported_constants
mbed_official 155:8435094ec241 1269 * @{
mbed_official 155:8435094ec241 1270 */
mbed_official 155:8435094ec241 1271
mbed_official 155:8435094ec241 1272 /** @addtogroup Peripheral_Registers_Bits_Definition
mbed_official 155:8435094ec241 1273 * @{
mbed_official 155:8435094ec241 1274 */
mbed_official 155:8435094ec241 1275
mbed_official 155:8435094ec241 1276 /******************************************************************************/
mbed_official 155:8435094ec241 1277 /* Peripheral Registers_Bits_Definition */
mbed_official 155:8435094ec241 1278 /******************************************************************************/
mbed_official 155:8435094ec241 1279 /******************************************************************************/
mbed_official 155:8435094ec241 1280 /* */
mbed_official 155:8435094ec241 1281 /* High Resolution Timer (HRTIM) */
mbed_official 155:8435094ec241 1282 /* */
mbed_official 155:8435094ec241 1283 /******************************************************************************/
mbed_official 155:8435094ec241 1284 /******************** Master Timer control register ***************************/
mbed_official 155:8435094ec241 1285 #define HRTIM_MCR_CK_PSC ((uint32_t)0x00000007) /*!< Prescaler mask */
mbed_official 155:8435094ec241 1286 #define HRTIM_MCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< Prescaler bit 0 */
mbed_official 155:8435094ec241 1287 #define HRTIM_MCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< Prescaler bit 1 */
mbed_official 155:8435094ec241 1288 #define HRTIM_MCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< Prescaler bit 2 */
mbed_official 155:8435094ec241 1289
mbed_official 155:8435094ec241 1290 #define HRTIM_MCR_CONT ((uint32_t)0x00000008) /*!< Continuous mode */
mbed_official 155:8435094ec241 1291 #define HRTIM_MCR_RETRIG ((uint32_t)0x00000010) /*!< Rettrigreable mode */
mbed_official 155:8435094ec241 1292 #define HRTIM_MCR_HALF ((uint32_t)0x00000020) /*!< Half mode */
mbed_official 155:8435094ec241 1293
mbed_official 155:8435094ec241 1294 #define HRTIM_MCR_SYNC_IN ((uint32_t)0x00000300) /*!< Synchronization input master */
mbed_official 155:8435094ec241 1295 #define HRTIM_MCR_SYNC_IN_0 ((uint32_t)0x00000100) /*!< Synchronization input bit 0 */
mbed_official 155:8435094ec241 1296 #define HRTIM_MCR_SYNC_IN_1 ((uint32_t)0x00000200) /*!< Synchronization input bit 1 */
mbed_official 155:8435094ec241 1297 #define HRTIM_MCR_SYNCRSTM ((uint32_t)0x00000400) /*!< Synchronization reset master */
mbed_official 155:8435094ec241 1298 #define HRTIM_MCR_SYNCSTRTM ((uint32_t)0x00000800) /*!< Synchronization start master */
mbed_official 155:8435094ec241 1299 #define HRTIM_MCR_SYNC_OUT ((uint32_t)0x00003000) /*!< Synchronization output master */
mbed_official 155:8435094ec241 1300 #define HRTIM_MCR_SYNC_OUT_0 ((uint32_t)0x00001000) /*!< Synchronization output bit 0 */
mbed_official 155:8435094ec241 1301 #define HRTIM_MCR_SYNC_OUT_1 ((uint32_t)0x00002000) /*!< Synchronization output bit 1 */
mbed_official 155:8435094ec241 1302 #define HRTIM_MCR_SYNC_SRC ((uint32_t)0x0000C000) /*!< Synchronization source */
mbed_official 155:8435094ec241 1303 #define HRTIM_MCR_SYNC_SRC_0 ((uint32_t)0x00004000) /*!< Synchronization source bit 0 */
mbed_official 155:8435094ec241 1304 #define HRTIM_MCR_SYNC_SRC_1 ((uint32_t)0x00008000) /*!< Synchronization source bit 1 */
mbed_official 155:8435094ec241 1305
mbed_official 155:8435094ec241 1306 #define HRTIM_MCR_MCEN ((uint32_t)0x00010000) /*!< Master counter enable */
mbed_official 155:8435094ec241 1307 #define HRTIM_MCR_TACEN ((uint32_t)0x00020000) /*!< Timer A counter enable */
mbed_official 155:8435094ec241 1308 #define HRTIM_MCR_TBCEN ((uint32_t)0x00040000) /*!< Timer B counter enable */
mbed_official 155:8435094ec241 1309 #define HRTIM_MCR_TCCEN ((uint32_t)0x00080000) /*!< Timer C counter enable */
mbed_official 155:8435094ec241 1310 #define HRTIM_MCR_TDCEN ((uint32_t)0x00100000) /*!< Timer D counter enable */
mbed_official 155:8435094ec241 1311 #define HRTIM_MCR_TECEN ((uint32_t)0x00200000) /*!< Timer E counter enable */
mbed_official 155:8435094ec241 1312
mbed_official 155:8435094ec241 1313 #define HRTIM_MCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */
mbed_official 155:8435094ec241 1314 #define HRTIM_MCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */
mbed_official 155:8435094ec241 1315 #define HRTIM_MCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */
mbed_official 155:8435094ec241 1316
mbed_official 155:8435094ec241 1317 #define HRTIM_MCR_PREEN ((uint32_t)0x08000000) /*!< Master preload enable */
mbed_official 155:8435094ec241 1318 #define HRTIM_MCR_MREPU ((uint32_t)0x20000000) /*!< Master repetition update */
mbed_official 155:8435094ec241 1319
mbed_official 155:8435094ec241 1320 #define HRTIM_MCR_BRSTDMA ((uint32_t)0xC0000000) /*!< Burst DMA update */
mbed_official 155:8435094ec241 1321 #define HRTIM_MCR_BRSTDMA_0 ((uint32_t)0x40000000) /*!< Burst DMA update bit 0*/
mbed_official 155:8435094ec241 1322 #define HRTIM_MCR_BRSTDMA_1 ((uint32_t)0x80000000) /*!< Burst DMA update bit 1 */
mbed_official 155:8435094ec241 1323
mbed_official 155:8435094ec241 1324 /******************** Master Timer Interrupt status register ******************/
mbed_official 155:8435094ec241 1325 #define HRTIM_MISR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag */
mbed_official 155:8435094ec241 1326 #define HRTIM_MISR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag */
mbed_official 155:8435094ec241 1327 #define HRTIM_MISR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag */
mbed_official 155:8435094ec241 1328 #define HRTIM_MISR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag */
mbed_official 155:8435094ec241 1329 #define HRTIM_MISR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag */
mbed_official 155:8435094ec241 1330 #define HRTIM_MISR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag */
mbed_official 155:8435094ec241 1331 #define HRTIM_MISR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag */
mbed_official 155:8435094ec241 1332
mbed_official 155:8435094ec241 1333 /******************** Master Timer Interrupt clear register *******************/
mbed_official 155:8435094ec241 1334 #define HRTIM_MICR_MCMP1 ((uint32_t)0x00000001) /*!< Master compare 1 interrupt flag clear */
mbed_official 155:8435094ec241 1335 #define HRTIM_MICR_MCMP2 ((uint32_t)0x00000002) /*!< Master compare 2 interrupt flag clear */
mbed_official 155:8435094ec241 1336 #define HRTIM_MICR_MCMP3 ((uint32_t)0x00000004) /*!< Master compare 3 interrupt flag clear */
mbed_official 155:8435094ec241 1337 #define HRTIM_MICR_MCMP4 ((uint32_t)0x00000008) /*!< Master compare 4 interrupt flag clear */
mbed_official 155:8435094ec241 1338 #define HRTIM_MICR_MREP ((uint32_t)0x00000010) /*!< Master Repetition interrupt flag clear */
mbed_official 155:8435094ec241 1339 #define HRTIM_MICR_SYNC ((uint32_t)0x00000020) /*!< Synchronization input interrupt flag clear */
mbed_official 155:8435094ec241 1340 #define HRTIM_MICR_MUPD ((uint32_t)0x00000040) /*!< Master update interrupt flag clear */
mbed_official 155:8435094ec241 1341
mbed_official 155:8435094ec241 1342 /******************** Master Timer DMA/Interrupt enable register **************/
mbed_official 155:8435094ec241 1343 #define HRTIM_MDIER_MCMP1IE ((uint32_t)0x00000001) /*!< Master compare 1 interrupt enable */
mbed_official 155:8435094ec241 1344 #define HRTIM_MDIER_MCMP2IE ((uint32_t)0x00000002) /*!< Master compare 2 interrupt enable */
mbed_official 155:8435094ec241 1345 #define HRTIM_MDIER_MCMP3IE ((uint32_t)0x00000004) /*!< Master compare 3 interrupt enable */
mbed_official 155:8435094ec241 1346 #define HRTIM_MDIER_MCMP4IE ((uint32_t)0x00000008) /*!< Master compare 4 interrupt enable */
mbed_official 155:8435094ec241 1347 #define HRTIM_MDIER_MREPIE ((uint32_t)0x00000010) /*!< Master Repetition interrupt enable */
mbed_official 155:8435094ec241 1348 #define HRTIM_MDIER_SYNCIE ((uint32_t)0x00000020) /*!< Synchronization input interrupt enable */
mbed_official 155:8435094ec241 1349 #define HRTIM_MDIER_MUPDIE ((uint32_t)0x00000040) /*!< Master update interrupt enable */
mbed_official 155:8435094ec241 1350
mbed_official 155:8435094ec241 1351 #define HRTIM_MDIER_MCMP1DE ((uint32_t)0x00010000) /*!< Master compare 1 DMA enable */
mbed_official 155:8435094ec241 1352 #define HRTIM_MDIER_MCMP2DE ((uint32_t)0x00020000) /*!< Master compare 2 DMA enable */
mbed_official 155:8435094ec241 1353 #define HRTIM_MDIER_MCMP3DE ((uint32_t)0x00040000) /*!< Master compare 3 DMA enable */
mbed_official 155:8435094ec241 1354 #define HRTIM_MDIER_MCMP4DE ((uint32_t)0x00080000) /*!< Master compare 4 DMA enable */
mbed_official 155:8435094ec241 1355 #define HRTIM_MDIER_MREPDE ((uint32_t)0x00100000) /*!< Master Repetition DMA enable */
mbed_official 155:8435094ec241 1356 #define HRTIM_MDIER_SYNCDE ((uint32_t)0x00200000) /*!< Synchronization input DMA enable */
mbed_official 155:8435094ec241 1357 #define HRTIM_MDIER_MUPDDE ((uint32_t)0x00400000) /*!< Master update DMA enable */
mbed_official 155:8435094ec241 1358
mbed_official 155:8435094ec241 1359 /******************* Bit definition for HRTIM_MCNTR register ****************/
mbed_official 155:8435094ec241 1360 #define HRTIM_MCNTR_MCNTR ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 155:8435094ec241 1361
mbed_official 155:8435094ec241 1362 /******************* Bit definition for HRTIM_MPER register *****************/
mbed_official 155:8435094ec241 1363 #define HRTIM_MPER_MPER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
mbed_official 155:8435094ec241 1364
mbed_official 155:8435094ec241 1365 /******************* Bit definition for HRTIM_MREP register *****************/
mbed_official 155:8435094ec241 1366 #define HRTIM_MREP_MREP ((uint32_t)0xFFFFFFFF) /*!<Repetition Value */
mbed_official 155:8435094ec241 1367
mbed_official 155:8435094ec241 1368 /******************* Bit definition for HRTIM_MCMP1R register *****************/
mbed_official 155:8435094ec241 1369 #define HRTIM_MCMP1R_MCMP1R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
mbed_official 155:8435094ec241 1370
mbed_official 155:8435094ec241 1371 /******************* Bit definition for HRTIM_MCMP2R register *****************/
mbed_official 155:8435094ec241 1372 #define HRTIM_MCMP1R_MCMP2R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
mbed_official 155:8435094ec241 1373
mbed_official 155:8435094ec241 1374 /******************* Bit definition for HRTIM_MCMP3R register *****************/
mbed_official 155:8435094ec241 1375 #define HRTIM_MCMP1R_MCMP3R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
mbed_official 155:8435094ec241 1376
mbed_official 155:8435094ec241 1377 /******************* Bit definition for HRTIM_MCMP4R register *****************/
mbed_official 155:8435094ec241 1378 #define HRTIM_MCMP1R_MCMP4R ((uint32_t)0xFFFFFFFF) /*!<Compare Value */
mbed_official 155:8435094ec241 1379
mbed_official 155:8435094ec241 1380 /******************** Slave control register **********************************/
mbed_official 155:8435094ec241 1381 #define HRTIM_TIMCR_CK_PSC ((uint32_t)0x00000007) /*!< Slave prescaler mask*/
mbed_official 155:8435094ec241 1382 #define HRTIM_TIMCR_CK_PSC_0 ((uint32_t)0x00000001) /*!< prescaler bit 0 */
mbed_official 155:8435094ec241 1383 #define HRTIM_TIMCR_CK_PSC_1 ((uint32_t)0x00000002) /*!< prescaler bit 1 */
mbed_official 155:8435094ec241 1384 #define HRTIM_TIMCR_CK_PSC_2 ((uint32_t)0x00000004) /*!< prescaler bit 2 */
mbed_official 155:8435094ec241 1385
mbed_official 155:8435094ec241 1386 #define HRTIM_TIMCR_CONT ((uint32_t)0x00000008) /*!< Slave continuous mode */
mbed_official 155:8435094ec241 1387 #define HRTIM_TIMCR_RETRIG ((uint32_t)0x00000010) /*!< Slave Retrigreable mode */
mbed_official 155:8435094ec241 1388 #define HRTIM_TIMCR_HALF ((uint32_t)0x00000020) /*!< Slave Half mode */
mbed_official 155:8435094ec241 1389 #define HRTIM_TIMCR_PSHPLL ((uint32_t)0x00000040) /*!< Slave push-pull mode */
mbed_official 155:8435094ec241 1390
mbed_official 155:8435094ec241 1391 #define HRTIM_TIMCR_SYNCRST ((uint32_t)0x00000400) /*!< Slave synchronization resets */
mbed_official 155:8435094ec241 1392 #define HRTIM_TIMCR_SYNCSTRT ((uint32_t)0x00000800) /*!< Slave synchronization starts */
mbed_official 155:8435094ec241 1393
mbed_official 155:8435094ec241 1394 #define HRTIM_TIMCR_DELCMP2 ((uint32_t)0x00003000) /*!< Slave delayed comparator 2 mode mask */
mbed_official 155:8435094ec241 1395 #define HRTIM_TIMCR_DELCMP2_0 ((uint32_t)0x00001000) /*!< Slave delayed comparator 2 bit 0 */
mbed_official 155:8435094ec241 1396 #define HRTIM_TIMCR_DELCMP2_1 ((uint32_t)0x00002000) /*!< Slave delayed comparator 2 bit 1 */
mbed_official 155:8435094ec241 1397 #define HRTIM_TIMCR_DELCMP4 ((uint32_t)0x0000C000) /*!< Slave delayed comparator 4 mode mask */
mbed_official 155:8435094ec241 1398 #define HRTIM_TIMCR_DELCMP4_0 ((uint32_t)0x00004000) /*!< Slave delayed comparator 4 bit 0 */
mbed_official 155:8435094ec241 1399 #define HRTIM_TIMCR_DELCMP4_1 ((uint32_t)0x00008000) /*!< Slave delayed comparator 4 bit 1 */
mbed_official 155:8435094ec241 1400
mbed_official 155:8435094ec241 1401 #define HRTIM_TIMCR_TREPU ((uint32_t)0x00020000) /*!< Slave repetition update */
mbed_official 155:8435094ec241 1402 #define HRTIM_TIMCR_TRSTU ((uint32_t)0x00040000) /*!< Slave reset update */
mbed_official 155:8435094ec241 1403 #define HRTIM_TIMCR_TAU ((uint32_t)0x00080000) /*!< Slave Timer A update reserved for TIM A */
mbed_official 155:8435094ec241 1404 #define HRTIM_TIMCR_TBU ((uint32_t)0x00100000) /*!< Slave Timer B update reserved for TIM B */
mbed_official 155:8435094ec241 1405 #define HRTIM_TIMCR_TCU ((uint32_t)0x00200000) /*!< Slave Timer C update reserved for TIM C */
mbed_official 155:8435094ec241 1406 #define HRTIM_TIMCR_TDU ((uint32_t)0x00400000) /*!< Slave Timer D update reserved for TIM D */
mbed_official 155:8435094ec241 1407 #define HRTIM_TIMCR_TEU ((uint32_t)0x00800000) /*!< Slave Timer E update reserved for TIM E */
mbed_official 155:8435094ec241 1408 #define HRTIM_TIMCR_MSTU ((uint32_t)0x01000000) /*!< Master Update */
mbed_official 155:8435094ec241 1409
mbed_official 155:8435094ec241 1410 #define HRTIM_TIMCR_DACSYNC ((uint32_t)0x06000000) /*!< DAC synchronization mask */
mbed_official 155:8435094ec241 1411 #define HRTIM_TIMCR_DACSYNC_0 ((uint32_t)0x02000000) /*!< DAC synchronization bit 0 */
mbed_official 155:8435094ec241 1412 #define HRTIM_TIMCR_DACSYNC_1 ((uint32_t)0x04000000) /*!< DAC synchronization bit 1 */
mbed_official 155:8435094ec241 1413 #define HRTIM_TIMCR_PREEN ((uint32_t)0x08000000) /*!< Slave preload enable */
mbed_official 155:8435094ec241 1414
mbed_official 155:8435094ec241 1415 #define HRTIM_TIMCR_UPDGAT ((uint32_t)0xF0000000) /*!< Slave update gating mask */
mbed_official 155:8435094ec241 1416 #define HRTIM_TIMCR_UPDGAT_0 ((uint32_t)0x10000000) /*!< Update gating bit 0 */
mbed_official 155:8435094ec241 1417 #define HRTIM_TIMCR_UPDGAT_1 ((uint32_t)0x20000000) /*!< Update gating bit 1 */
mbed_official 155:8435094ec241 1418 #define HRTIM_TIMCR_UPDGAT_2 ((uint32_t)0x40000000) /*!< Update gating bit 2 */
mbed_official 155:8435094ec241 1419 #define HRTIM_TIMCR_UPDGAT_3 ((uint32_t)0x80000000) /*!< Update gating bit 3 */
mbed_official 155:8435094ec241 1420
mbed_official 155:8435094ec241 1421 /******************** Slave Interrupt status register **************************/
mbed_official 155:8435094ec241 1422 #define HRTIM_TIMISR_CMP1 ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt flag */
mbed_official 155:8435094ec241 1423 #define HRTIM_TIMISR_CMP2 ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt flag */
mbed_official 155:8435094ec241 1424 #define HRTIM_TIMISR_CMP3 ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt flag */
mbed_official 155:8435094ec241 1425 #define HRTIM_TIMISR_CMP4 ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt flag */
mbed_official 155:8435094ec241 1426 #define HRTIM_TIMISR_REP ((uint32_t)0x00000010) /*!< Slave repetition interrupt flag */
mbed_official 155:8435094ec241 1427 #define HRTIM_TIMISR_UPD ((uint32_t)0x00000040) /*!< Slave update interrupt flag */
mbed_official 155:8435094ec241 1428 #define HRTIM_TIMISR_CPT1 ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt flag */
mbed_official 155:8435094ec241 1429 #define HRTIM_TIMISR_CPT2 ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt flag */
mbed_official 155:8435094ec241 1430 #define HRTIM_TIMISR_SET1 ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt flag */
mbed_official 155:8435094ec241 1431 #define HRTIM_TIMISR_RST1 ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt flag */
mbed_official 155:8435094ec241 1432 #define HRTIM_TIMISR_SET2 ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt flag */
mbed_official 155:8435094ec241 1433 #define HRTIM_TIMISR_RST2 ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt flag */
mbed_official 155:8435094ec241 1434 #define HRTIM_TIMISR_RST ((uint32_t)0x00002000) /*!< Slave reset interrupt flag */
mbed_official 155:8435094ec241 1435 #define HRTIM_TIMISR_DLYPRT ((uint32_t)0x00004000) /*!< Slave output 1 delay protection interrupt flag */
mbed_official 155:8435094ec241 1436 #define HRTIM_TIMISR_CPPSTAT ((uint32_t)0x00010000) /*!< Slave current push-pull flag */
mbed_official 155:8435094ec241 1437 #define HRTIM_TIMISR_IPPSTAT ((uint32_t)0x00020000) /*!< Slave idle push-pull flag */
mbed_official 155:8435094ec241 1438 #define HRTIM_TIMISR_O1STAT ((uint32_t)0x00040000) /*!< Slave output 1 state flag */
mbed_official 155:8435094ec241 1439 #define HRTIM_TIMISR_O2STAT ((uint32_t)0x00080000) /*!< Slave output 2 state flag */
mbed_official 155:8435094ec241 1440 #define HRTIM_TIMISR_O1CPY ((uint32_t)0x00100000) /*!< Slave output 1 copy flag */
mbed_official 155:8435094ec241 1441 #define HRTIM_TIMISR_O2CPY ((uint32_t)0x00200000) /*!< Slave output 2 copy flag */
mbed_official 155:8435094ec241 1442
mbed_official 155:8435094ec241 1443 /******************** Slave Interrupt clear register **************************/
mbed_official 155:8435094ec241 1444 #define HRTIM_TIMICR_CMP1C ((uint32_t)0x00000001) /*!< Slave compare 1 clear flag */
mbed_official 155:8435094ec241 1445 #define HRTIM_TIMICR_CMP2C ((uint32_t)0x00000002) /*!< Slave compare 2 clear flag */
mbed_official 155:8435094ec241 1446 #define HRTIM_TIMICR_CMP3C ((uint32_t)0x00000004) /*!< Slave compare 3 clear flag */
mbed_official 155:8435094ec241 1447 #define HRTIM_TIMICR_CMP4C ((uint32_t)0x00000008) /*!< Slave compare 4 clear flag */
mbed_official 155:8435094ec241 1448 #define HRTIM_TIMICR_REPC ((uint32_t)0x00000010) /*!< Slave repetition clear flag */
mbed_official 155:8435094ec241 1449 #define HRTIM_TIMICR_UPDC ((uint32_t)0x00000040) /*!< Slave update clear flag */
mbed_official 155:8435094ec241 1450 #define HRTIM_TIMICR_CPT1C ((uint32_t)0x00000080) /*!< Slave capture 1 clear flag */
mbed_official 155:8435094ec241 1451 #define HRTIM_TIMICR_CPT2C ((uint32_t)0x00000100) /*!< Slave capture 2 clear flag */
mbed_official 155:8435094ec241 1452 #define HRTIM_TIMICR_SET1C ((uint32_t)0x00000200) /*!< Slave output 1 set clear flag */
mbed_official 155:8435094ec241 1453 #define HRTIM_TIMICR_RST1C ((uint32_t)0x00000400) /*!< Slave output 1 reset clear flag */
mbed_official 155:8435094ec241 1454 #define HRTIM_TIMICR_SET2C ((uint32_t)0x00000800) /*!< Slave output 2 set clear flag */
mbed_official 155:8435094ec241 1455 #define HRTIM_TIMICR_RST2C ((uint32_t)0x00001000) /*!< Slave output 2 reset clear flag */
mbed_official 155:8435094ec241 1456 #define HRTIM_TIMICR_RSTC ((uint32_t)0x00002000) /*!< Slave reset clear flag */
mbed_official 155:8435094ec241 1457 #define HRTIM_TIMICR_DLYPRT1C ((uint32_t)0x00004000) /*!< Slave output 1 delay protection clear flag */
mbed_official 155:8435094ec241 1458 #define HRTIM_TIMICR_DLYPRT2C ((uint32_t)0x00008000) /*!< Slave output 2 delay protection clear flag */
mbed_official 155:8435094ec241 1459
mbed_official 155:8435094ec241 1460 /******************** Slave DMA/Interrupt enable register *********************/
mbed_official 155:8435094ec241 1461 #define HRTIM_TIMDIER_CMP1IE ((uint32_t)0x00000001) /*!< Slave compare 1 interrupt enable */
mbed_official 155:8435094ec241 1462 #define HRTIM_TIMDIER_CMP2IE ((uint32_t)0x00000002) /*!< Slave compare 2 interrupt enable */
mbed_official 155:8435094ec241 1463 #define HRTIM_TIMDIER_CMP3IE ((uint32_t)0x00000004) /*!< Slave compare 3 interrupt enable */
mbed_official 155:8435094ec241 1464 #define HRTIM_TIMDIER_CMP4IE ((uint32_t)0x00000008) /*!< Slave compare 4 interrupt enable */
mbed_official 155:8435094ec241 1465 #define HRTIM_TIMDIER_REPIE ((uint32_t)0x00000010) /*!< Slave repetition interrupt enable */
mbed_official 155:8435094ec241 1466 #define HRTIM_TIMDIER_UPDIE ((uint32_t)0x00000040) /*!< Slave update interrupt enable */
mbed_official 155:8435094ec241 1467 #define HRTIM_TIMDIER_CPT1IE ((uint32_t)0x00000080) /*!< Slave capture 1 interrupt enable */
mbed_official 155:8435094ec241 1468 #define HRTIM_TIMDIER_CPT2IE ((uint32_t)0x00000100) /*!< Slave capture 2 interrupt enable */
mbed_official 155:8435094ec241 1469 #define HRTIM_TIMDIER_SET1IE ((uint32_t)0x00000200) /*!< Slave output 1 set interrupt enable */
mbed_official 155:8435094ec241 1470 #define HRTIM_TIMDIER_RST1IE ((uint32_t)0x00000400) /*!< Slave output 1 reset interrupt enable */
mbed_official 155:8435094ec241 1471 #define HRTIM_TIMDIER_SET2IE ((uint32_t)0x00000800) /*!< Slave output 2 set interrupt enable */
mbed_official 155:8435094ec241 1472 #define HRTIM_TIMDIER_RST2IE ((uint32_t)0x00001000) /*!< Slave output 2 reset interrupt enable */
mbed_official 155:8435094ec241 1473 #define HRTIM_TIMDIER_RSTIE ((uint32_t)0x00002000) /*!< Slave reset interrupt enable */
mbed_official 155:8435094ec241 1474 #define HRTIM_TIMDIER_DLYPRTIE ((uint32_t)0x00004000) /*!< Slave delay protection interrupt enable */
mbed_official 155:8435094ec241 1475
mbed_official 155:8435094ec241 1476 #define HRTIM_TIMDIER_CMP1DE ((uint32_t)0x00010000) /*!< Slave compare 1 request enable */
mbed_official 155:8435094ec241 1477 #define HRTIM_TIMDIER_CMP2DE ((uint32_t)0x00020000) /*!< Slave compare 2 request enable */
mbed_official 155:8435094ec241 1478 #define HRTIM_TIMDIER_CMP3DE ((uint32_t)0x00040000) /*!< Slave compare 3 request enable */
mbed_official 155:8435094ec241 1479 #define HRTIM_TIMDIER_CMP4DE ((uint32_t)0x00080000) /*!< Slave compare 4 request enable */
mbed_official 155:8435094ec241 1480 #define HRTIM_TIMDIER_REPDE ((uint32_t)0x00100000) /*!< Slave repetition request enable */
mbed_official 155:8435094ec241 1481 #define HRTIM_TIMDIER_UPDDE ((uint32_t)0x00400000) /*!< Slave update request enable */
mbed_official 155:8435094ec241 1482 #define HRTIM_TIMDIER_CPT1DE ((uint32_t)0x00800000) /*!< Slave capture 1 request enable */
mbed_official 155:8435094ec241 1483 #define HRTIM_TIMDIER_CPT2DE ((uint32_t)0x01000000) /*!< Slave capture 2 request enable */
mbed_official 155:8435094ec241 1484 #define HRTIM_TIMDIER_SET1DE ((uint32_t)0x02000000) /*!< Slave output 1 set request enable */
mbed_official 155:8435094ec241 1485 #define HRTIM_TIMDIER_RST1DE ((uint32_t)0x04000000) /*!< Slave output 1 reset request enable */
mbed_official 155:8435094ec241 1486 #define HRTIM_TIMDIER_SET2DE ((uint32_t)0x08000000) /*!< Slave output 2 set request enable */
mbed_official 155:8435094ec241 1487 #define HRTIM_TIMDIER_RST2DE ((uint32_t)0x10000000) /*!< Slave output 2 reset request enable */
mbed_official 155:8435094ec241 1488 #define HRTIM_TIMDIER_RSTDE ((uint32_t)0x20000000) /*!< Slave reset request enable */
mbed_official 155:8435094ec241 1489 #define HRTIM_TIMDIER_DLYPRTDE ((uint32_t)0x40000000) /*!< Slave delay protection request enable */
mbed_official 155:8435094ec241 1490
mbed_official 155:8435094ec241 1491 /****************** Bit definition for HRTIM_CNTR register ****************/
mbed_official 155:8435094ec241 1492 #define HRTIM_CNTR_CNTR ((uint32_t)0xFFFFFFFF) /*!< Counter Value */
mbed_official 155:8435094ec241 1493
mbed_official 155:8435094ec241 1494 /******************* Bit definition for HRTIM_PER register *****************/
mbed_official 155:8435094ec241 1495 #define HRTIM_PER_PER ((uint32_t)0xFFFFFFFF) /*!< Period Value */
mbed_official 155:8435094ec241 1496
mbed_official 155:8435094ec241 1497 /******************* Bit definition for HRTIM_REP register *****************/
mbed_official 155:8435094ec241 1498 #define HRTIM_REP_REP ((uint32_t)0xFFFFFFFF) /*!< Repetition Value */
mbed_official 155:8435094ec241 1499
mbed_official 155:8435094ec241 1500 /******************* Bit definition for HRTIM_CMP1R register *****************/
mbed_official 155:8435094ec241 1501 #define HRTIM_CMP1R_CMP1R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
mbed_official 155:8435094ec241 1502
mbed_official 155:8435094ec241 1503 /******************* Bit definition for HRTIM_CMP1CR register *****************/
mbed_official 155:8435094ec241 1504 #define HRTIM_CMP1CR_CMP1CR ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
mbed_official 155:8435094ec241 1505
mbed_official 155:8435094ec241 1506 /******************* Bit definition for HRTIM_CMP2R register *****************/
mbed_official 155:8435094ec241 1507 #define HRTIM_CMP2R_CMP2R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
mbed_official 155:8435094ec241 1508
mbed_official 155:8435094ec241 1509 /******************* Bit definition for HRTIM_CMP3R register *****************/
mbed_official 155:8435094ec241 1510 #define HRTIM_CMP3R_CMP3R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
mbed_official 155:8435094ec241 1511
mbed_official 155:8435094ec241 1512 /******************* Bit definition for HRTIM_CMP4R register *****************/
mbed_official 155:8435094ec241 1513 #define HRTIM_CMP4R_CMP4R ((uint32_t)0xFFFFFFFF) /*!< Compare Value */
mbed_official 155:8435094ec241 1514
mbed_official 155:8435094ec241 1515 /******************* Bit definition for HRTIM_CPT1R register ****************/
mbed_official 155:8435094ec241 1516 #define HRTIM_CPT1R_CPT1R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
mbed_official 155:8435094ec241 1517
mbed_official 155:8435094ec241 1518 /******************* Bit definition for HRTIM_CPT2R register ****************/
mbed_official 155:8435094ec241 1519 #define HRTIM_CPT2R_CPT2R ((uint32_t)0xFFFFFFFF) /*!< Capture Value */
mbed_official 155:8435094ec241 1520
mbed_official 155:8435094ec241 1521 /******************** Bit definition for Slave Deadtime register **************/
mbed_official 155:8435094ec241 1522 #define HRTIM_DTR_DTR ((uint32_t)0x000001FF) /*!< Dead time rising value */
mbed_official 155:8435094ec241 1523 #define HRTIM_DTR_DTR_0 ((uint32_t)0x00000001) /*!< Dead time rising bit 0 */
mbed_official 155:8435094ec241 1524 #define HRTIM_DTR_DTR_1 ((uint32_t)0x00000002) /*!< Dead time rising bit 1 */
mbed_official 155:8435094ec241 1525 #define HRTIM_DTR_DTR_2 ((uint32_t)0x00000004) /*!< Dead time rising bit 2 */
mbed_official 155:8435094ec241 1526 #define HRTIM_DTR_DTR_3 ((uint32_t)0x00000008) /*!< Dead time rising bit 3 */
mbed_official 155:8435094ec241 1527 #define HRTIM_DTR_DTR_4 ((uint32_t)0x00000010) /*!< Dead time rising bit 4 */
mbed_official 155:8435094ec241 1528 #define HRTIM_DTR_DTR_5 ((uint32_t)0x00000020) /*!< Dead time rising bit 5 */
mbed_official 155:8435094ec241 1529 #define HRTIM_DTR_DTR_6 ((uint32_t)0x00000040) /*!< Dead time rising bit 6 */
mbed_official 155:8435094ec241 1530 #define HRTIM_DTR_DTR_7 ((uint32_t)0x00000080) /*!< Dead time rising bit 7 */
mbed_official 155:8435094ec241 1531 #define HRTIM_DTR_DTR_8 ((uint32_t)0x00000100) /*!< Dead time rising bit 8 */
mbed_official 155:8435094ec241 1532 #define HRTIM_DTR_SDTR ((uint32_t)0x00000200) /*!< Sign dead time rising value */
mbed_official 155:8435094ec241 1533 #define HRTIM_DTR_DTPRSC ((uint32_t)0x00001C00) /*!< Dead time prescaler */
mbed_official 155:8435094ec241 1534 #define HRTIM_DTR_DTPRSC_0 ((uint32_t)0x00000400) /*!< Dead time prescaler bit 0 */
mbed_official 155:8435094ec241 1535 #define HRTIM_DTR_DTPRSC_1 ((uint32_t)0x00000800) /*!< Dead time prescaler bit 1 */
mbed_official 155:8435094ec241 1536 #define HRTIM_DTR_DTPRSC_2 ((uint32_t)0x00001000) /*!< Dead time prescaler bit 2 */
mbed_official 155:8435094ec241 1537 #define HRTIM_DTR_DTRSLK ((uint32_t)0x00004000) /*!< Dead time rising sign lock */
mbed_official 155:8435094ec241 1538 #define HRTIM_DTR_DTRLK ((uint32_t)0x00008000) /*!< Dead time rising lock */
mbed_official 155:8435094ec241 1539 #define HRTIM_DTR_DTF ((uint32_t)0x01FF0000) /*!< Dead time falling value */
mbed_official 155:8435094ec241 1540 #define HRTIM_DTR_DTF_0 ((uint32_t)0x00010000) /*!< Dead time falling bit 0 */
mbed_official 155:8435094ec241 1541 #define HRTIM_DTR_DTF_1 ((uint32_t)0x00020000) /*!< Dead time falling bit 1 */
mbed_official 155:8435094ec241 1542 #define HRTIM_DTR_DTF_2 ((uint32_t)0x00040000) /*!< Dead time falling bit 2 */
mbed_official 155:8435094ec241 1543 #define HRTIM_DTR_DTF_3 ((uint32_t)0x00080000) /*!< Dead time falling bit 3 */
mbed_official 155:8435094ec241 1544 #define HRTIM_DTR_DTF_4 ((uint32_t)0x00100000) /*!< Dead time falling bit 4 */
mbed_official 155:8435094ec241 1545 #define HRTIM_DTR_DTF_5 ((uint32_t)0x00200000) /*!< Dead time falling bit 5 */
mbed_official 155:8435094ec241 1546 #define HRTIM_DTR_DTF_6 ((uint32_t)0x00400000) /*!< Dead time falling bit 6 */
mbed_official 155:8435094ec241 1547 #define HRTIM_DTR_DTF_7 ((uint32_t)0x00800000) /*!< Dead time falling bit 7 */
mbed_official 155:8435094ec241 1548 #define HRTIM_DTR_DTF_8 ((uint32_t)0x01000000) /*!< Dead time falling bit 8 */
mbed_official 155:8435094ec241 1549 #define HRTIM_DTR_SDTF ((uint32_t)0x02000000) /*!< Sign dead time falling value */
mbed_official 155:8435094ec241 1550 #define HRTIM_DTR_DTFSLK ((uint32_t)0x40000000) /*!< Dead time falling sign lock */
mbed_official 155:8435094ec241 1551 #define HRTIM_DTR_DTFLK ((uint32_t)0x80000000) /*!< Dead time falling lock */
mbed_official 155:8435094ec241 1552
mbed_official 155:8435094ec241 1553 /**** Bit definition for Slave Output 1 set register **************************/
mbed_official 155:8435094ec241 1554 #define HRTIM_SET1R_SST ((uint32_t)0x00000001) /*!< software set trigger */
mbed_official 155:8435094ec241 1555 #define HRTIM_SET1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
mbed_official 155:8435094ec241 1556 #define HRTIM_SET1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
mbed_official 155:8435094ec241 1557 #define HRTIM_SET1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
mbed_official 155:8435094ec241 1558 #define HRTIM_SET1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
mbed_official 155:8435094ec241 1559 #define HRTIM_SET1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
mbed_official 155:8435094ec241 1560 #define HRTIM_SET1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
mbed_official 155:8435094ec241 1561
mbed_official 155:8435094ec241 1562 #define HRTIM_SET1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
mbed_official 155:8435094ec241 1563 #define HRTIM_SET1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
mbed_official 155:8435094ec241 1564 #define HRTIM_SET1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
mbed_official 155:8435094ec241 1565 #define HRTIM_SET1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
mbed_official 155:8435094ec241 1566 #define HRTIM_SET1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
mbed_official 155:8435094ec241 1567
mbed_official 155:8435094ec241 1568 #define HRTIM_SET1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
mbed_official 155:8435094ec241 1569 #define HRTIM_SET1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
mbed_official 155:8435094ec241 1570 #define HRTIM_SET1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
mbed_official 155:8435094ec241 1571 #define HRTIM_SET1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
mbed_official 155:8435094ec241 1572 #define HRTIM_SET1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
mbed_official 155:8435094ec241 1573 #define HRTIM_SET1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
mbed_official 155:8435094ec241 1574 #define HRTIM_SET1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
mbed_official 155:8435094ec241 1575 #define HRTIM_SET1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
mbed_official 155:8435094ec241 1576 #define HRTIM_SET1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
mbed_official 155:8435094ec241 1577
mbed_official 155:8435094ec241 1578 #define HRTIM_SET1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
mbed_official 155:8435094ec241 1579 #define HRTIM_SET1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
mbed_official 155:8435094ec241 1580 #define HRTIM_SET1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
mbed_official 155:8435094ec241 1581 #define HRTIM_SET1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
mbed_official 155:8435094ec241 1582 #define HRTIM_SET1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
mbed_official 155:8435094ec241 1583 #define HRTIM_SET1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
mbed_official 155:8435094ec241 1584 #define HRTIM_SET1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
mbed_official 155:8435094ec241 1585 #define HRTIM_SET1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
mbed_official 155:8435094ec241 1586 #define HRTIM_SET1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
mbed_official 155:8435094ec241 1587 #define HRTIM_SET1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
mbed_official 155:8435094ec241 1588
mbed_official 155:8435094ec241 1589 #define HRTIM_SET1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
mbed_official 155:8435094ec241 1590
mbed_official 155:8435094ec241 1591 /**** Bit definition for Slave Output 1 reset register ************************/
mbed_official 155:8435094ec241 1592 #define HRTIM_RST1R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
mbed_official 155:8435094ec241 1593 #define HRTIM_RST1R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
mbed_official 155:8435094ec241 1594 #define HRTIM_RST1R_PER ((uint32_t)0x00000004) /*!< Timer A period */
mbed_official 155:8435094ec241 1595 #define HRTIM_RST1R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
mbed_official 155:8435094ec241 1596 #define HRTIM_RST1R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
mbed_official 155:8435094ec241 1597 #define HRTIM_RST1R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
mbed_official 155:8435094ec241 1598 #define HRTIM_RST1R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
mbed_official 155:8435094ec241 1599
mbed_official 155:8435094ec241 1600 #define HRTIM_RST1R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
mbed_official 155:8435094ec241 1601 #define HRTIM_RST1R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
mbed_official 155:8435094ec241 1602 #define HRTIM_RST1R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
mbed_official 155:8435094ec241 1603 #define HRTIM_RST1R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
mbed_official 155:8435094ec241 1604 #define HRTIM_RST1R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
mbed_official 155:8435094ec241 1605
mbed_official 155:8435094ec241 1606 #define HRTIM_RST1R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
mbed_official 155:8435094ec241 1607 #define HRTIM_RST1R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
mbed_official 155:8435094ec241 1608 #define HRTIM_RST1R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
mbed_official 155:8435094ec241 1609 #define HRTIM_RST1R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
mbed_official 155:8435094ec241 1610 #define HRTIM_RST1R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
mbed_official 155:8435094ec241 1611 #define HRTIM_RST1R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
mbed_official 155:8435094ec241 1612 #define HRTIM_RST1R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
mbed_official 155:8435094ec241 1613 #define HRTIM_RST1R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
mbed_official 155:8435094ec241 1614 #define HRTIM_RST1R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
mbed_official 155:8435094ec241 1615
mbed_official 155:8435094ec241 1616 #define HRTIM_RST1R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
mbed_official 155:8435094ec241 1617 #define HRTIM_RST1R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
mbed_official 155:8435094ec241 1618 #define HRTIM_RST1R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
mbed_official 155:8435094ec241 1619 #define HRTIM_RST1R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
mbed_official 155:8435094ec241 1620 #define HRTIM_RST1R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
mbed_official 155:8435094ec241 1621 #define HRTIM_RST1R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
mbed_official 155:8435094ec241 1622 #define HRTIM_RST1R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
mbed_official 155:8435094ec241 1623 #define HRTIM_RST1R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
mbed_official 155:8435094ec241 1624 #define HRTIM_RST1R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
mbed_official 155:8435094ec241 1625 #define HRTIM_RST1R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
mbed_official 155:8435094ec241 1626
mbed_official 155:8435094ec241 1627 #define HRTIM_RST1R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
mbed_official 155:8435094ec241 1628
mbed_official 155:8435094ec241 1629
mbed_official 155:8435094ec241 1630 /**** Bit definition for Slave Output 2 set register **************************/
mbed_official 155:8435094ec241 1631 #define HRTIM_SET2R_SST ((uint32_t)0x00000001) /*!< software set trigger */
mbed_official 155:8435094ec241 1632 #define HRTIM_SET2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
mbed_official 155:8435094ec241 1633 #define HRTIM_SET2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
mbed_official 155:8435094ec241 1634 #define HRTIM_SET2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
mbed_official 155:8435094ec241 1635 #define HRTIM_SET2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
mbed_official 155:8435094ec241 1636 #define HRTIM_SET2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
mbed_official 155:8435094ec241 1637 #define HRTIM_SET2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
mbed_official 155:8435094ec241 1638
mbed_official 155:8435094ec241 1639 #define HRTIM_SET2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
mbed_official 155:8435094ec241 1640 #define HRTIM_SET2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
mbed_official 155:8435094ec241 1641 #define HRTIM_SET2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
mbed_official 155:8435094ec241 1642 #define HRTIM_SET2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
mbed_official 155:8435094ec241 1643 #define HRTIM_SET2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
mbed_official 155:8435094ec241 1644
mbed_official 155:8435094ec241 1645 #define HRTIM_SET2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
mbed_official 155:8435094ec241 1646 #define HRTIM_SET2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
mbed_official 155:8435094ec241 1647 #define HRTIM_SET2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
mbed_official 155:8435094ec241 1648 #define HRTIM_SET2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
mbed_official 155:8435094ec241 1649 #define HRTIM_SET2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
mbed_official 155:8435094ec241 1650 #define HRTIM_SET2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
mbed_official 155:8435094ec241 1651 #define HRTIM_SET2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
mbed_official 155:8435094ec241 1652 #define HRTIM_SET2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
mbed_official 155:8435094ec241 1653 #define HRTIM_SET2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
mbed_official 155:8435094ec241 1654
mbed_official 155:8435094ec241 1655 #define HRTIM_SET2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
mbed_official 155:8435094ec241 1656 #define HRTIM_SET2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
mbed_official 155:8435094ec241 1657 #define HRTIM_SET2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
mbed_official 155:8435094ec241 1658 #define HRTIM_SET2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
mbed_official 155:8435094ec241 1659 #define HRTIM_SET2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
mbed_official 155:8435094ec241 1660 #define HRTIM_SET2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
mbed_official 155:8435094ec241 1661 #define HRTIM_SET2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
mbed_official 155:8435094ec241 1662 #define HRTIM_SET2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
mbed_official 155:8435094ec241 1663 #define HRTIM_SET2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
mbed_official 155:8435094ec241 1664 #define HRTIM_SET2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
mbed_official 155:8435094ec241 1665
mbed_official 155:8435094ec241 1666 #define HRTIM_SET2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
mbed_official 155:8435094ec241 1667
mbed_official 155:8435094ec241 1668 /**** Bit definition for Slave Output 2 reset register ************************/
mbed_official 155:8435094ec241 1669 #define HRTIM_RST2R_SRT ((uint32_t)0x00000001) /*!< software reset trigger */
mbed_official 155:8435094ec241 1670 #define HRTIM_RST2R_RESYNC ((uint32_t)0x00000002) /*!< Timer A resynchronization */
mbed_official 155:8435094ec241 1671 #define HRTIM_RST2R_PER ((uint32_t)0x00000004) /*!< Timer A period */
mbed_official 155:8435094ec241 1672 #define HRTIM_RST2R_CMP1 ((uint32_t)0x00000008) /*!< Timer A compare 1 */
mbed_official 155:8435094ec241 1673 #define HRTIM_RST2R_CMP2 ((uint32_t)0x00000010) /*!< Timer A compare 2 */
mbed_official 155:8435094ec241 1674 #define HRTIM_RST2R_CMP3 ((uint32_t)0x00000020) /*!< Timer A compare 3 */
mbed_official 155:8435094ec241 1675 #define HRTIM_RST2R_CMP4 ((uint32_t)0x00000040) /*!< Timer A compare 4 */
mbed_official 155:8435094ec241 1676
mbed_official 155:8435094ec241 1677 #define HRTIM_RST2R_MSTPER ((uint32_t)0x00000080) /*!< Master period */
mbed_official 155:8435094ec241 1678 #define HRTIM_RST2R_MSTCMP1 ((uint32_t)0x00000100) /*!< Master compare 1 */
mbed_official 155:8435094ec241 1679 #define HRTIM_RST2R_MSTCMP2 ((uint32_t)0x00000200) /*!< Master compare 2 */
mbed_official 155:8435094ec241 1680 #define HRTIM_RST2R_MSTCMP3 ((uint32_t)0x00000400) /*!< Master compare 3 */
mbed_official 155:8435094ec241 1681 #define HRTIM_RST2R_MSTCMP4 ((uint32_t)0x00000800) /*!< Master compare 4 */
mbed_official 155:8435094ec241 1682
mbed_official 155:8435094ec241 1683 #define HRTIM_RST2R_TIMEVNT1 ((uint32_t)0x00001000) /*!< Timer event 1 */
mbed_official 155:8435094ec241 1684 #define HRTIM_RST2R_TIMEVNT2 ((uint32_t)0x00002000) /*!< Timer event 2 */
mbed_official 155:8435094ec241 1685 #define HRTIM_RST2R_TIMEVNT3 ((uint32_t)0x00004000) /*!< Timer event 3 */
mbed_official 155:8435094ec241 1686 #define HRTIM_RST2R_TIMEVNT4 ((uint32_t)0x00008000) /*!< Timer event 4 */
mbed_official 155:8435094ec241 1687 #define HRTIM_RST2R_TIMEVNT5 ((uint32_t)0x00010000) /*!< Timer event 5 */
mbed_official 155:8435094ec241 1688 #define HRTIM_RST2R_TIMEVNT6 ((uint32_t)0x00020000) /*!< Timer event 6 */
mbed_official 155:8435094ec241 1689 #define HRTIM_RST2R_TIMEVNT7 ((uint32_t)0x00040000) /*!< Timer event 7 */
mbed_official 155:8435094ec241 1690 #define HRTIM_RST2R_TIMEVNT8 ((uint32_t)0x00080000) /*!< Timer event 8 */
mbed_official 155:8435094ec241 1691 #define HRTIM_RST2R_TIMEVNT9 ((uint32_t)0x00100000) /*!< Timer event 9 */
mbed_official 155:8435094ec241 1692
mbed_official 155:8435094ec241 1693 #define HRTIM_RST2R_EXTVNT1 ((uint32_t)0x00200000) /*!< External event 1 */
mbed_official 155:8435094ec241 1694 #define HRTIM_RST2R_EXTVNT2 ((uint32_t)0x00400000) /*!< External event 2 */
mbed_official 155:8435094ec241 1695 #define HRTIM_RST2R_EXTVNT3 ((uint32_t)0x00800000) /*!< External event 3 */
mbed_official 155:8435094ec241 1696 #define HRTIM_RST2R_EXTVNT4 ((uint32_t)0x01000000) /*!< External event 4 */
mbed_official 155:8435094ec241 1697 #define HRTIM_RST2R_EXTVNT5 ((uint32_t)0x02000000) /*!< External event 5 */
mbed_official 155:8435094ec241 1698 #define HRTIM_RST2R_EXTVNT6 ((uint32_t)0x04000000) /*!< External event 6 */
mbed_official 155:8435094ec241 1699 #define HRTIM_RST2R_EXTVNT7 ((uint32_t)0x08000000) /*!< External event 7 */
mbed_official 155:8435094ec241 1700 #define HRTIM_RST2R_EXTVNT8 ((uint32_t)0x10000000) /*!< External event 8 */
mbed_official 155:8435094ec241 1701 #define HRTIM_RST2R_EXTVNT9 ((uint32_t)0x20000000) /*!< External event 9 */
mbed_official 155:8435094ec241 1702 #define HRTIM_RST2R_EXTVNT10 ((uint32_t)0x40000000) /*!< External event 10 */
mbed_official 155:8435094ec241 1703
mbed_official 155:8435094ec241 1704 #define HRTIM_RST2R_UPDATE ((uint32_t)0x80000000) /*!< Register update (transfer preload to active) */
mbed_official 155:8435094ec241 1705
mbed_official 155:8435094ec241 1706 /**** Bit definition for Slave external event filtering register 1 ***********/
mbed_official 155:8435094ec241 1707 #define HRTIM_EEFR1_EE1LTCH ((uint32_t)0x00000001) /*!< External Event 1 latch */
mbed_official 155:8435094ec241 1708 #define HRTIM_EEFR1_EE1FLTR ((uint32_t)0x0000001E) /*!< External Event 1 filter mask */
mbed_official 155:8435094ec241 1709 #define HRTIM_EEFR1_EE1FLTR_0 ((uint32_t)0x00000002) /*!< External Event 1 bit 0 */
mbed_official 155:8435094ec241 1710 #define HRTIM_EEFR1_EE1FLTR_1 ((uint32_t)0x00000004) /*!< External Event 1 bit 1*/
mbed_official 155:8435094ec241 1711 #define HRTIM_EEFR1_EE1FLTR_2 ((uint32_t)0x00000008) /*!< External Event 1 bit 2 */
mbed_official 155:8435094ec241 1712 #define HRTIM_EEFR1_EE1FLTR_3 ((uint32_t)0x00000010) /*!< External Event 1 bit 3 */
mbed_official 155:8435094ec241 1713
mbed_official 155:8435094ec241 1714 #define HRTIM_EEFR1_EE2LTCH ((uint32_t)0x00000040) /*!< External Event 2 latch */
mbed_official 155:8435094ec241 1715 #define HRTIM_EEFR1_EE2FLTR ((uint32_t)0x00000780) /*!< External Event 2 filter mask */
mbed_official 155:8435094ec241 1716 #define HRTIM_EEFR1_EE2FLTR_0 ((uint32_t)0x00000080) /*!< External Event 2 bit 0 */
mbed_official 155:8435094ec241 1717 #define HRTIM_EEFR1_EE2FLTR_1 ((uint32_t)0x00000100) /*!< External Event 2 bit 1*/
mbed_official 155:8435094ec241 1718 #define HRTIM_EEFR1_EE2FLTR_2 ((uint32_t)0x00000200) /*!< External Event 2 bit 2 */
mbed_official 155:8435094ec241 1719 #define HRTIM_EEFR1_EE2FLTR_3 ((uint32_t)0x00000400) /*!< External Event 2 bit 3 */
mbed_official 155:8435094ec241 1720
mbed_official 155:8435094ec241 1721 #define HRTIM_EEFR1_EE3LTCH ((uint32_t)0x00001000) /*!< External Event 3 latch */
mbed_official 155:8435094ec241 1722 #define HRTIM_EEFR1_EE3FLTR ((uint32_t)0x0001E000) /*!< External Event 3 filter mask */
mbed_official 155:8435094ec241 1723 #define HRTIM_EEFR1_EE3FLTR_0 ((uint32_t)0x00002000) /*!< External Event 3 bit 0 */
mbed_official 155:8435094ec241 1724 #define HRTIM_EEFR1_EE3FLTR_1 ((uint32_t)0x00004000) /*!< External Event 3 bit 1*/
mbed_official 155:8435094ec241 1725 #define HRTIM_EEFR1_EE3FLTR_2 ((uint32_t)0x00008000) /*!< External Event 3 bit 2 */
mbed_official 155:8435094ec241 1726 #define HRTIM_EEFR1_EE3FLTR_3 ((uint32_t)0x00010000) /*!< External Event 3 bit 3 */
mbed_official 155:8435094ec241 1727
mbed_official 155:8435094ec241 1728 #define HRTIM_EEFR1_EE4LTCH ((uint32_t)0x00040000) /*!< External Event 4 latch */
mbed_official 155:8435094ec241 1729 #define HRTIM_EEFR1_EE4FLTR ((uint32_t)0x00780000) /*!< External Event 4 filter mask */
mbed_official 155:8435094ec241 1730 #define HRTIM_EEFR1_EE4FLTR_0 ((uint32_t)0x00080000) /*!< External Event 4 bit 0 */
mbed_official 155:8435094ec241 1731 #define HRTIM_EEFR1_EE4FLTR_1 ((uint32_t)0x00100000) /*!< External Event 4 bit 1*/
mbed_official 155:8435094ec241 1732 #define HRTIM_EEFR1_EE4FLTR_2 ((uint32_t)0x00200000) /*!< External Event 4 bit 2 */
mbed_official 155:8435094ec241 1733 #define HRTIM_EEFR1_EE4FLTR_3 ((uint32_t)0x00400000) /*!< External Event 4 bit 3 */
mbed_official 155:8435094ec241 1734
mbed_official 155:8435094ec241 1735 #define HRTIM_EEFR1_EE5LTCH ((uint32_t)0x01000000) /*!< External Event 5 latch */
mbed_official 155:8435094ec241 1736 #define HRTIM_EEFR1_EE5FLTR ((uint32_t)0x1E000000) /*!< External Event 5 filter mask */
mbed_official 155:8435094ec241 1737 #define HRTIM_EEFR1_EE5FLTR_0 ((uint32_t)0x02000000) /*!< External Event 5 bit 0 */
mbed_official 155:8435094ec241 1738 #define HRTIM_EEFR1_EE5FLTR_1 ((uint32_t)0x04000000) /*!< External Event 5 bit 1*/
mbed_official 155:8435094ec241 1739 #define HRTIM_EEFR1_EE5FLTR_2 ((uint32_t)0x08000000) /*!< External Event 5 bit 2 */
mbed_official 155:8435094ec241 1740 #define HRTIM_EEFR1_EE5FLTR_3 ((uint32_t)0x10000000) /*!< External Event 5 bit 3 */
mbed_official 155:8435094ec241 1741
mbed_official 155:8435094ec241 1742 /**** Bit definition for Slave external event filtering register 2 ***********/
mbed_official 155:8435094ec241 1743 #define HRTIM_EEFR2_EE6LTCH ((uint32_t)0x00000001) /*!< External Event 6 latch */
mbed_official 155:8435094ec241 1744 #define HRTIM_EEFR2_EE6FLTR ((uint32_t)0x0000001E) /*!< External Event 6 filter mask */
mbed_official 155:8435094ec241 1745 #define HRTIM_EEFR2_EE6FLTR_0 ((uint32_t)0x00000002) /*!< External Event 6 bit 0 */
mbed_official 155:8435094ec241 1746 #define HRTIM_EEFR2_EE6FLTR_1 ((uint32_t)0x00000004) /*!< External Event 6 bit 1*/
mbed_official 155:8435094ec241 1747 #define HRTIM_EEFR2_EE6FLTR_2 ((uint32_t)0x00000008) /*!< External Event 6 bit 2 */
mbed_official 155:8435094ec241 1748 #define HRTIM_EEFR2_EE6FLTR_3 ((uint32_t)0x00000010) /*!< External Event 6 bit 3 */
mbed_official 155:8435094ec241 1749
mbed_official 155:8435094ec241 1750 #define HRTIM_EEFR2_EE7LTCH ((uint32_t)0x00000040) /*!< External Event 7 latch */
mbed_official 155:8435094ec241 1751 #define HRTIM_EEFR2_EE7FLTR ((uint32_t)0x00000780) /*!< External Event 7 filter mask */
mbed_official 155:8435094ec241 1752 #define HRTIM_EEFR2_EE7FLTR_0 ((uint32_t)0x00000080) /*!< External Event 7 bit 0 */
mbed_official 155:8435094ec241 1753 #define HRTIM_EEFR2_EE7FLTR_1 ((uint32_t)0x00000100) /*!< External Event 7 bit 1*/
mbed_official 155:8435094ec241 1754 #define HRTIM_EEFR2_EE7FLTR_2 ((uint32_t)0x00000200) /*!< External Event 7 bit 2 */
mbed_official 155:8435094ec241 1755 #define HRTIM_EEFR2_EE7FLTR_3 ((uint32_t)0x00000400) /*!< External Event 7 bit 3 */
mbed_official 155:8435094ec241 1756
mbed_official 155:8435094ec241 1757 #define HRTIM_EEFR2_EE8LTCH ((uint32_t)0x00001000) /*!< External Event 8 latch */
mbed_official 155:8435094ec241 1758 #define HRTIM_EEFR2_EE8FLTR ((uint32_t)0x0001E000) /*!< External Event 8 filter mask */
mbed_official 155:8435094ec241 1759 #define HRTIM_EEFR2_EE8FLTR_0 ((uint32_t)0x00002000) /*!< External Event 8 bit 0 */
mbed_official 155:8435094ec241 1760 #define HRTIM_EEFR2_EE8FLTR_1 ((uint32_t)0x00004000) /*!< External Event 8 bit 1*/
mbed_official 155:8435094ec241 1761 #define HRTIM_EEFR2_EE8FLTR_2 ((uint32_t)0x00008000) /*!< External Event 8 bit 2 */
mbed_official 155:8435094ec241 1762 #define HRTIM_EEFR2_EE8FLTR_3 ((uint32_t)0x00010000) /*!< External Event 8 bit 3 */
mbed_official 155:8435094ec241 1763
mbed_official 155:8435094ec241 1764 #define HRTIM_EEFR2_EE9LTCH ((uint32_t)0x00040000) /*!< External Event 9 latch */
mbed_official 155:8435094ec241 1765 #define HRTIM_EEFR2_EE9FLTR ((uint32_t)0x00780000) /*!< External Event 9 filter mask */
mbed_official 155:8435094ec241 1766 #define HRTIM_EEFR2_EE9FLTR_0 ((uint32_t)0x00080000) /*!< External Event 9 bit 0 */
mbed_official 155:8435094ec241 1767 #define HRTIM_EEFR2_EE9FLTR_1 ((uint32_t)0x00100000) /*!< External Event 9 bit 1*/
mbed_official 155:8435094ec241 1768 #define HRTIM_EEFR2_EE9FLTR_2 ((uint32_t)0x00200000) /*!< External Event 9 bit 2 */
mbed_official 155:8435094ec241 1769 #define HRTIM_EEFR2_EE9FLTR_3 ((uint32_t)0x00400000) /*!< External Event 9 bit 3 */
mbed_official 155:8435094ec241 1770
mbed_official 155:8435094ec241 1771 #define HRTIM_EEFR2_EE10LTCH ((uint32_t)0x01000000) /*!< External Event 10 latch */
mbed_official 155:8435094ec241 1772 #define HRTIM_EEFR2_EE10FLTR ((uint32_t)0x1E000000) /*!< External Event 10 filter mask */
mbed_official 155:8435094ec241 1773 #define HRTIM_EEFR2_EE10FLTR_0 ((uint32_t)0x02000000) /*!< External Event 10 bit 0 */
mbed_official 155:8435094ec241 1774 #define HRTIM_EEFR2_EE10FLTR_1 ((uint32_t)0x04000000) /*!< External Event 10 bit 1*/
mbed_official 155:8435094ec241 1775 #define HRTIM_EEFR2_EE10FLTR_2 ((uint32_t)0x08000000) /*!< External Event 10 bit 2 */
mbed_official 155:8435094ec241 1776 #define HRTIM_EEFR2_EE10FLTR_3 ((uint32_t)0x10000000) /*!< External Event 10 bit 3 */
mbed_official 155:8435094ec241 1777
mbed_official 155:8435094ec241 1778 /**** Bit definition for Slave Timer reset register ***************************/
mbed_official 155:8435094ec241 1779 #define HRTIM_RSTR_UPDATE ((uint32_t)0x00000002) /*!< Timer update */
mbed_official 155:8435094ec241 1780 #define HRTIM_RSTR_CMP2 ((uint32_t)0x00000004) /*!< Timer compare2 */
mbed_official 155:8435094ec241 1781 #define HRTIM_RSTR_CMP4 ((uint32_t)0x00000008) /*!< Timer compare4 */
mbed_official 155:8435094ec241 1782
mbed_official 155:8435094ec241 1783 #define HRTIM_RSTR_MSTPER ((uint32_t)0x00000010) /*!< Master period */
mbed_official 155:8435094ec241 1784 #define HRTIM_RSTR_MSTCMP1 ((uint32_t)0x00000020) /*!< Master compare1 */
mbed_official 155:8435094ec241 1785 #define HRTIM_RSTR_MSTCMP2 ((uint32_t)0x00000040) /*!< Master compare2 */
mbed_official 155:8435094ec241 1786 #define HRTIM_RSTR_MSTCMP3 ((uint32_t)0x00000080) /*!< Master compare3 */
mbed_official 155:8435094ec241 1787 #define HRTIM_RSTR_MSTCMP4 ((uint32_t)0x00000100) /*!< Master compare4 */
mbed_official 155:8435094ec241 1788
mbed_official 155:8435094ec241 1789 #define HRTIM_RSTR_EXTEVNT1 ((uint32_t)0x00000200) /*!< External event 1 */
mbed_official 155:8435094ec241 1790 #define HRTIM_RSTR_EXTEVNT2 ((uint32_t)0x00000400) /*!< External event 2 */
mbed_official 155:8435094ec241 1791 #define HRTIM_RSTR_EXTEVNT3 ((uint32_t)0x00000800) /*!< External event 3 */
mbed_official 155:8435094ec241 1792 #define HRTIM_RSTR_EXTEVNT4 ((uint32_t)0x00001000) /*!< External event 4 */
mbed_official 155:8435094ec241 1793 #define HRTIM_RSTR_EXTEVNT5 ((uint32_t)0x00002000) /*!< External event 5 */
mbed_official 155:8435094ec241 1794 #define HRTIM_RSTR_EXTEVNT6 ((uint32_t)0x00004000) /*!< External event 6 */
mbed_official 155:8435094ec241 1795 #define HRTIM_RSTR_EXTEVNT7 ((uint32_t)0x00008000) /*!< External event 7 */
mbed_official 155:8435094ec241 1796 #define HRTIM_RSTR_EXTEVNT8 ((uint32_t)0x00010000) /*!< External event 8 */
mbed_official 155:8435094ec241 1797 #define HRTIM_RSTR_EXTEVNT9 ((uint32_t)0x00020000) /*!< External event 9 */
mbed_official 155:8435094ec241 1798 #define HRTIM_RSTR_EXTEVNT10 ((uint32_t)0x00040000) /*!< External event 10 */
mbed_official 155:8435094ec241 1799
mbed_official 155:8435094ec241 1800 #define HRTIM_RSTR_TIMBCMP1 ((uint32_t)0x00080000) /*!< Timer B compare 1 */
mbed_official 155:8435094ec241 1801 #define HRTIM_RSTR_TIMBCMP2 ((uint32_t)0x00100000) /*!< Timer B compare 2 */
mbed_official 155:8435094ec241 1802 #define HRTIM_RSTR_TIMBCMP4 ((uint32_t)0x00200000) /*!< Timer B compare 4 */
mbed_official 155:8435094ec241 1803
mbed_official 155:8435094ec241 1804 #define HRTIM_RSTR_TIMCCMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
mbed_official 155:8435094ec241 1805 #define HRTIM_RSTR_TIMCCMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
mbed_official 155:8435094ec241 1806 #define HRTIM_RSTR_TIMCCMP4 ((uint32_t)0x01000000) /*!< Timer C compare 4 */
mbed_official 155:8435094ec241 1807
mbed_official 155:8435094ec241 1808 #define HRTIM_RSTR_TIMDCMP1 ((uint32_t)0x02000000) /*!< Timer D compare 1 */
mbed_official 155:8435094ec241 1809 #define HRTIM_RSTR_TIMDCMP2 ((uint32_t)0x04000000) /*!< Timer D compare 2 */
mbed_official 155:8435094ec241 1810 #define HRTIM_RSTR_TIMDCMP4 ((uint32_t)0x08000000) /*!< Timer D compare 4 */
mbed_official 155:8435094ec241 1811
mbed_official 155:8435094ec241 1812 #define HRTIM_RSTR_TIMECMP1 ((uint32_t)0x10000000) /*!< Timer E compare 1 */
mbed_official 155:8435094ec241 1813 #define HRTIM_RSTR_TIMECMP2 ((uint32_t)0x20000000) /*!< Timer E compare 2 */
mbed_official 155:8435094ec241 1814 #define HRTIM_RSTR_TIMECMP4 ((uint32_t)0x40000000) /*!< Timer E compare 4 */
mbed_official 155:8435094ec241 1815
mbed_official 155:8435094ec241 1816 /**** Bit definition for Slave Timer Chopper register *************************/
mbed_official 155:8435094ec241 1817 #define HRTIM_CHPR_CARFRQ ((uint32_t)0x0000000F) /*!< Timer carrier frequency value */
mbed_official 155:8435094ec241 1818 #define HRTIM_CHPR_CARFRQ_0 ((uint32_t)0x00000001) /*!< Timer carrier frequency value bit 0 */
mbed_official 155:8435094ec241 1819 #define HRTIM_CHPR_CARFRQ_1 ((uint32_t)0x00000002) /*!< Timer carrier frequency value bit 1 */
mbed_official 155:8435094ec241 1820 #define HRTIM_CHPR_CARFRQ_2 ((uint32_t)0x00000004) /*!< Timer carrier frequency value bit 2 */
mbed_official 155:8435094ec241 1821 #define HRTIM_CHPR_CARFRQ_3 ((uint32_t)0x00000008) /*!< Timer carrier frequency value bit 3 */
mbed_official 155:8435094ec241 1822
mbed_official 155:8435094ec241 1823 #define HRTIM_CHPR_CARDTY ((uint32_t)0x00000070) /*!< Timer chopper duty cycle value */
mbed_official 155:8435094ec241 1824 #define HRTIM_CHPR_CARDTY_0 ((uint32_t)0x00000010) /*!< Timer chopper duty cycle value bit 0 */
mbed_official 155:8435094ec241 1825 #define HRTIM_CHPR_CARDTY_1 ((uint32_t)0x00000020) /*!< Timer chopper duty cycle value bit 1 */
mbed_official 155:8435094ec241 1826 #define HRTIM_CHPR_CARDTY_2 ((uint32_t)0x00000040) /*!< Timer chopper duty cycle value bit 2 */
mbed_official 155:8435094ec241 1827
mbed_official 155:8435094ec241 1828 #define HRTIM_CHPR_STRPW ((uint32_t)0x00000780) /*!< Timer start pulse width value */
mbed_official 155:8435094ec241 1829 #define HRTIM_CHPR_STRPW_0 ((uint32_t)0x00000080) /*!< Timer start pulse width value bit 0 */
mbed_official 155:8435094ec241 1830 #define HRTIM_CHPR_STRPW_1 ((uint32_t)0x00000100) /*!< Timer start pulse width value bit 1 */
mbed_official 155:8435094ec241 1831 #define HRTIM_CHPR_STRPW_2 ((uint32_t)0x00000200) /*!< Timer start pulse width value bit 2 */
mbed_official 155:8435094ec241 1832 #define HRTIM_CHPR_STRPW_3 ((uint32_t)0x00000400) /*!< Timer start pulse width value bit 3 */
mbed_official 155:8435094ec241 1833
mbed_official 155:8435094ec241 1834 /**** Bit definition for Slave Timer Capture 1 control register ***************/
mbed_official 155:8435094ec241 1835 #define HRTIM_CPT1CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
mbed_official 155:8435094ec241 1836 #define HRTIM_CPT1CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
mbed_official 155:8435094ec241 1837 #define HRTIM_CPT1CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
mbed_official 155:8435094ec241 1838 #define HRTIM_CPT1CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
mbed_official 155:8435094ec241 1839 #define HRTIM_CPT1CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
mbed_official 155:8435094ec241 1840 #define HRTIM_CPT1CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
mbed_official 155:8435094ec241 1841 #define HRTIM_CPT1CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
mbed_official 155:8435094ec241 1842 #define HRTIM_CPT1CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
mbed_official 155:8435094ec241 1843 #define HRTIM_CPT1CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
mbed_official 155:8435094ec241 1844 #define HRTIM_CPT1CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
mbed_official 155:8435094ec241 1845 #define HRTIM_CPT1CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
mbed_official 155:8435094ec241 1846 #define HRTIM_CPT1CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
mbed_official 155:8435094ec241 1847
mbed_official 155:8435094ec241 1848 #define HRTIM_CPT1CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
mbed_official 155:8435094ec241 1849 #define HRTIM_CPT1CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
mbed_official 155:8435094ec241 1850 #define HRTIM_CPT1CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
mbed_official 155:8435094ec241 1851 #define HRTIM_CPT1CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
mbed_official 155:8435094ec241 1852
mbed_official 155:8435094ec241 1853 #define HRTIM_CPT1CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
mbed_official 155:8435094ec241 1854 #define HRTIM_CPT1CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
mbed_official 155:8435094ec241 1855 #define HRTIM_CPT1CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
mbed_official 155:8435094ec241 1856 #define HRTIM_CPT1CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
mbed_official 155:8435094ec241 1857
mbed_official 155:8435094ec241 1858 #define HRTIM_CPT1CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
mbed_official 155:8435094ec241 1859 #define HRTIM_CPT1CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
mbed_official 155:8435094ec241 1860 #define HRTIM_CPT1CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
mbed_official 155:8435094ec241 1861 #define HRTIM_CPT1CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
mbed_official 155:8435094ec241 1862
mbed_official 155:8435094ec241 1863 #define HRTIM_CPT1CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
mbed_official 155:8435094ec241 1864 #define HRTIM_CPT1CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
mbed_official 155:8435094ec241 1865 #define HRTIM_CPT1CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
mbed_official 155:8435094ec241 1866 #define HRTIM_CPT1CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
mbed_official 155:8435094ec241 1867
mbed_official 155:8435094ec241 1868 #define HRTIM_CPT1CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
mbed_official 155:8435094ec241 1869 #define HRTIM_CPT1CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
mbed_official 155:8435094ec241 1870 #define HRTIM_CPT1CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
mbed_official 155:8435094ec241 1871 #define HRTIM_CPT1CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
mbed_official 155:8435094ec241 1872
mbed_official 155:8435094ec241 1873 /**** Bit definition for Slave Timer Capture 2 control register ***************/
mbed_official 155:8435094ec241 1874 #define HRTIM_CPT2CR_SWCPT ((uint32_t)0x00000001) /*!< Software capture */
mbed_official 155:8435094ec241 1875 #define HRTIM_CPT2CR_UPDCPT ((uint32_t)0x00000002) /*!< Update capture */
mbed_official 155:8435094ec241 1876 #define HRTIM_CPT2CR_EXEV1CPT ((uint32_t)0x00000004) /*!< External event 1 capture */
mbed_official 155:8435094ec241 1877 #define HRTIM_CPT2CR_EXEV2CPT ((uint32_t)0x00000008) /*!< External event 2 capture */
mbed_official 155:8435094ec241 1878 #define HRTIM_CPT2CR_EXEV3CPT ((uint32_t)0x00000010) /*!< External event 3 capture */
mbed_official 155:8435094ec241 1879 #define HRTIM_CPT2CR_EXEV4CPT ((uint32_t)0x00000020) /*!< External event 4 capture */
mbed_official 155:8435094ec241 1880 #define HRTIM_CPT2CR_EXEV5CPT ((uint32_t)0x00000040) /*!< External event 5 capture */
mbed_official 155:8435094ec241 1881 #define HRTIM_CPT2CR_EXEV6CPT ((uint32_t)0x00000080) /*!< External event 6 capture */
mbed_official 155:8435094ec241 1882 #define HRTIM_CPT2CR_EXEV7CPT ((uint32_t)0x00000100) /*!< External event 7 capture */
mbed_official 155:8435094ec241 1883 #define HRTIM_CPT2CR_EXEV8CPT ((uint32_t)0x00000200) /*!< External event 8 capture */
mbed_official 155:8435094ec241 1884 #define HRTIM_CPT2CR_EXEV9CPT ((uint32_t)0x00000400) /*!< External event 9 capture */
mbed_official 155:8435094ec241 1885 #define HRTIM_CPT2CR_EXEV10CPT ((uint32_t)0x00000800) /*!< External event 10 capture */
mbed_official 155:8435094ec241 1886
mbed_official 155:8435094ec241 1887 #define HRTIM_CPT2CR_TA1SET ((uint32_t)0x00001000) /*!< Timer A output 1 set */
mbed_official 155:8435094ec241 1888 #define HRTIM_CPT2CR_TA1RST ((uint32_t)0x00002000) /*!< Timer A output 1 reset */
mbed_official 155:8435094ec241 1889 #define HRTIM_CPT2CR_TA1CMP1 ((uint32_t)0x00004000) /*!< Timer A compare 1 */
mbed_official 155:8435094ec241 1890 #define HRTIM_CPT2CR_TA1CMP2 ((uint32_t)0x00008000) /*!< Timer A compare 2 */
mbed_official 155:8435094ec241 1891
mbed_official 155:8435094ec241 1892 #define HRTIM_CPT2CR_TB1SET ((uint32_t)0x00010000) /*!< Timer B output 1 set */
mbed_official 155:8435094ec241 1893 #define HRTIM_CPT2CR_TB1RST ((uint32_t)0x00020000) /*!< Timer B output 1 reset */
mbed_official 155:8435094ec241 1894 #define HRTIM_CPT2CR_TB1CMP1 ((uint32_t)0x00040000) /*!< Timer B compare 1 */
mbed_official 155:8435094ec241 1895 #define HRTIM_CPT2CR_TB1CMP2 ((uint32_t)0x00080000) /*!< Timer B compare 2 */
mbed_official 155:8435094ec241 1896
mbed_official 155:8435094ec241 1897 #define HRTIM_CPT2CR_TC1SET ((uint32_t)0x00100000) /*!< Timer C output 1 set */
mbed_official 155:8435094ec241 1898 #define HRTIM_CPT2CR_TC1RST ((uint32_t)0x00200000) /*!< Timer C output 1 reset */
mbed_official 155:8435094ec241 1899 #define HRTIM_CPT2CR_TC1CMP1 ((uint32_t)0x00400000) /*!< Timer C compare 1 */
mbed_official 155:8435094ec241 1900 #define HRTIM_CPT2CR_TC1CMP2 ((uint32_t)0x00800000) /*!< Timer C compare 2 */
mbed_official 155:8435094ec241 1901
mbed_official 155:8435094ec241 1902 #define HRTIM_CPT2CR_TD1SET ((uint32_t)0x01000000) /*!< Timer D output 1 set */
mbed_official 155:8435094ec241 1903 #define HRTIM_CPT2CR_TD1RST ((uint32_t)0x02000000) /*!< Timer D output 1 reset */
mbed_official 155:8435094ec241 1904 #define HRTIM_CPT2CR_TD1CMP1 ((uint32_t)0x04000000) /*!< Timer D compare 1 */
mbed_official 155:8435094ec241 1905 #define HRTIM_CPT2CR_TD1CMP2 ((uint32_t)0x08000000) /*!< Timer D compare 2 */
mbed_official 155:8435094ec241 1906
mbed_official 155:8435094ec241 1907 #define HRTIM_CPT2CR_TE1SET ((uint32_t)0x10000000) /*!< Timer E output 1 set */
mbed_official 155:8435094ec241 1908 #define HRTIM_CPT2CR_TE1RST ((uint32_t)0x20000000) /*!< Timer E output 1 reset */
mbed_official 155:8435094ec241 1909 #define HRTIM_CPT2CR_TE1CMP1 ((uint32_t)0x40000000) /*!< Timer E compare 1 */
mbed_official 155:8435094ec241 1910 #define HRTIM_CPT2CR_TE1CMP2 ((uint32_t)0x80000000) /*!< Timer E compare 2 */
mbed_official 155:8435094ec241 1911
mbed_official 155:8435094ec241 1912 /**** Bit definition for Slave Timer Output register **************************/
mbed_official 155:8435094ec241 1913 #define HRTIM_OUTR_POL1 ((uint32_t)0x00000002) /*!< Slave output 1 polarity */
mbed_official 155:8435094ec241 1914 #define HRTIM_OUTR_IDLM1 ((uint32_t)0x00000004) /*!< Slave output 1 idle mode */
mbed_official 155:8435094ec241 1915 #define HRTIM_OUTR_IDLES1 ((uint32_t)0x00000008) /*!< Slave output 1 idle state */
mbed_official 155:8435094ec241 1916 #define HRTIM_OUTR_FAULT1 ((uint32_t)0x00000030) /*!< Slave output 1 fault state */
mbed_official 155:8435094ec241 1917 #define HRTIM_OUTR_FAULT1_0 ((uint32_t)0x00000010) /*!< Slave output 1 fault state bit 0 */
mbed_official 155:8435094ec241 1918 #define HRTIM_OUTR_FAULT1_1 ((uint32_t)0x00000020) /*!< Slave output 1 fault state bit 1 */
mbed_official 155:8435094ec241 1919 #define HRTIM_OUTR_CHP1 ((uint32_t)0x00000040) /*!< Slave output 1 chopper enable */
mbed_official 155:8435094ec241 1920 #define HRTIM_OUTR_DIDL1 ((uint32_t)0x00000080) /*!< Slave output 1 dead time idle */
mbed_official 155:8435094ec241 1921
mbed_official 155:8435094ec241 1922 #define HRTIM_OUTR_DTEN ((uint32_t)0x00000100) /*!< Slave output deadtime enable */
mbed_official 155:8435094ec241 1923 #define HRTIM_OUTR_DLYPRTEN ((uint32_t)0x00000200) /*!< Slave output delay protection enable */
mbed_official 155:8435094ec241 1924 #define HRTIM_OUTR_DLYPRT ((uint32_t)0x00001C00) /*!< Slave output delay protection */
mbed_official 155:8435094ec241 1925 #define HRTIM_OUTR_DLYPRT_0 ((uint32_t)0x00000400) /*!< Slave output delay protection bit 0 */
mbed_official 155:8435094ec241 1926 #define HRTIM_OUTR_DLYPRT_1 ((uint32_t)0x00000800) /*!< Slave output delay protection bit 1 */
mbed_official 155:8435094ec241 1927 #define HRTIM_OUTR_DLYPRT_2 ((uint32_t)0x00001000) /*!< Slave output delay protection bit 2 */
mbed_official 155:8435094ec241 1928
mbed_official 155:8435094ec241 1929 #define HRTIM_OUTR_POL2 ((uint32_t)0x00020000) /*!< Slave output 2 polarity */
mbed_official 155:8435094ec241 1930 #define HRTIM_OUTR_IDLM2 ((uint32_t)0x00040000) /*!< Slave output 2 idle mode */
mbed_official 155:8435094ec241 1931 #define HRTIM_OUTR_IDLES2 ((uint32_t)0x00080000) /*!< Slave output 2 idle state */
mbed_official 155:8435094ec241 1932 #define HRTIM_OUTR_FAULT2 ((uint32_t)0x00300000) /*!< Slave output 2 fault state */
mbed_official 155:8435094ec241 1933 #define HRTIM_OUTR_FAULT2_0 ((uint32_t)0x00100000) /*!< Slave output 2 fault state bit 0 */
mbed_official 155:8435094ec241 1934 #define HRTIM_OUTR_FAULT2_1 ((uint32_t)0x00200000) /*!< Slave output 2 fault state bit 1 */
mbed_official 155:8435094ec241 1935 #define HRTIM_OUTR_CHP2 ((uint32_t)0x00400000) /*!< Slave output 2 chopper enable */
mbed_official 155:8435094ec241 1936 #define HRTIM_OUTR_DIDL2 ((uint32_t)0x00800000) /*!< Slave output 2 dead time idle */
mbed_official 155:8435094ec241 1937
mbed_official 155:8435094ec241 1938 /**** Bit definition for Slave Timer Fault register ***************************/
mbed_official 155:8435094ec241 1939 #define HRTIM_FLTR_FLT1EN ((uint32_t)0x00000001) /*!< Fault 1 enable */
mbed_official 155:8435094ec241 1940 #define HRTIM_FLTR_FLT2EN ((uint32_t)0x00000002) /*!< Fault 2 enable */
mbed_official 155:8435094ec241 1941 #define HRTIM_FLTR_FLT3EN ((uint32_t)0x00000004) /*!< Fault 3 enable */
mbed_official 155:8435094ec241 1942 #define HRTIM_FLTR_FLT4EN ((uint32_t)0x00000008) /*!< Fault 4 enable */
mbed_official 155:8435094ec241 1943 #define HRTIM_FLTR_FLT5EN ((uint32_t)0x00000010) /*!< Fault 5 enable */
mbed_official 155:8435094ec241 1944 #define HRTIM_FLTR_FLTCLK ((uint32_t)0x80000000) /*!< Fault sources lock */
mbed_official 155:8435094ec241 1945
mbed_official 155:8435094ec241 1946 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
mbed_official 155:8435094ec241 1947 #define HRTIM_CR1_MUDIS ((uint32_t)0x00000001) /*!< Master update disable*/
mbed_official 155:8435094ec241 1948 #define HRTIM_CR1_TAUDIS ((uint32_t)0x00000002) /*!< Timer A update disable*/
mbed_official 155:8435094ec241 1949 #define HRTIM_CR1_TBUDIS ((uint32_t)0x00000004) /*!< Timer B update disable*/
mbed_official 155:8435094ec241 1950 #define HRTIM_CR1_TCUDIS ((uint32_t)0x00000008) /*!< Timer C update disable*/
mbed_official 155:8435094ec241 1951 #define HRTIM_CR1_TDUDIS ((uint32_t)0x00000010) /*!< Timer D update disable*/
mbed_official 155:8435094ec241 1952 #define HRTIM_CR1_TEUDIS ((uint32_t)0x00000020) /*!< Timer E update disable*/
mbed_official 155:8435094ec241 1953 #define HRTIM_CR1_ADC1USRC ((uint32_t)0x00070000) /*!< ADC Trigger 1 update source */
mbed_official 155:8435094ec241 1954 #define HRTIM_CR1_ADC1USRC_0 ((uint32_t)0x00010000) /*!< ADC Trigger 1 update source bit 0 */
mbed_official 155:8435094ec241 1955 #define HRTIM_CR1_ADC1USRC_1 ((uint32_t)0x00020000) /*!< ADC Trigger 1 update source bit 1 */
mbed_official 155:8435094ec241 1956 #define HRTIM_CR1_ADC1USRC_2 ((uint32_t)0x00040000) /*!< ADC Trigger 1 update source bit 2 */
mbed_official 155:8435094ec241 1957 #define HRTIM_CR1_ADC2USRC ((uint32_t)0x00380000) /*!< ADC Trigger 2 update source */
mbed_official 155:8435094ec241 1958 #define HRTIM_CR1_ADC2USRC_0 ((uint32_t)0x00080000) /*!< ADC Trigger 2 update source bit 0 */
mbed_official 155:8435094ec241 1959 #define HRTIM_CR1_ADC2USRC_1 ((uint32_t)0x00100000) /*!< ADC Trigger 2 update source bit 1 */
mbed_official 155:8435094ec241 1960 #define HRTIM_CR1_ADC2USRC_2 ((uint32_t)0x00200000) /*!< ADC Trigger 2 update source bit 2 */
mbed_official 155:8435094ec241 1961 #define HRTIM_CR1_ADC3USRC ((uint32_t)0x01C00000) /*!< ADC Trigger 3 update source */
mbed_official 155:8435094ec241 1962 #define HRTIM_CR1_ADC3USRC_0 ((uint32_t)0x00400000) /*!< ADC Trigger 3 update source bit 0 */
mbed_official 155:8435094ec241 1963 #define HRTIM_CR1_ADC3USRC_1 ((uint32_t)0x00800000) /*!< ADC Trigger 3 update source bit 1 */
mbed_official 155:8435094ec241 1964 #define HRTIM_CR1_ADC3USRC_2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 update source bit 2 */
mbed_official 155:8435094ec241 1965 #define HRTIM_CR1_ADC4USRC ((uint32_t)0x0E000000) /*!< ADC Trigger 4 update source */
mbed_official 155:8435094ec241 1966 #define HRTIM_CR1_ADC4USRC_0 ((uint32_t)0x02000000) /*!< ADC Trigger 4 update source bit 0 */
mbed_official 155:8435094ec241 1967 #define HRTIM_CR1_ADC4USRC_1 ((uint32_t)0x04000000) /*!< ADC Trigger 4 update source bit 1 */
mbed_official 155:8435094ec241 1968 #define HRTIM_CR1_ADC4USRC_2 ((uint32_t)0x0800000) /*!< ADC Trigger 4 update source bit 2 */
mbed_official 155:8435094ec241 1969
mbed_official 155:8435094ec241 1970 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
mbed_official 155:8435094ec241 1971 #define HRTIM_CR2_MSWU ((uint32_t)0x00000001) /*!< Master software update */
mbed_official 155:8435094ec241 1972 #define HRTIM_CR2_TASWU ((uint32_t)0x00000002) /*!< Timer A software update */
mbed_official 155:8435094ec241 1973 #define HRTIM_CR2_TBSWU ((uint32_t)0x00000004) /*!< Timer B software update */
mbed_official 155:8435094ec241 1974 #define HRTIM_CR2_TCSWU ((uint32_t)0x00000008) /*!< Timer C software update */
mbed_official 155:8435094ec241 1975 #define HRTIM_CR2_TDSWU ((uint32_t)0x00000010) /*!< Timer D software update */
mbed_official 155:8435094ec241 1976 #define HRTIM_CR2_TESWU ((uint32_t)0x00000020) /*!< Timer E software update */
mbed_official 155:8435094ec241 1977 #define HRTIM_CR2_MRST ((uint32_t)0x00000100) /*!< Master count software reset */
mbed_official 155:8435094ec241 1978 #define HRTIM_CR2_TARST ((uint32_t)0x00000200) /*!< Timer A count software reset */
mbed_official 155:8435094ec241 1979 #define HRTIM_CR2_TBRST ((uint32_t)0x00000400) /*!< Timer B count software reset */
mbed_official 155:8435094ec241 1980 #define HRTIM_CR2_TCRST ((uint32_t)0x00000800) /*!< Timer C count software reset */
mbed_official 155:8435094ec241 1981 #define HRTIM_CR2_TDRST ((uint32_t)0x00001000) /*!< Timer D count software reset */
mbed_official 155:8435094ec241 1982 #define HRTIM_CR2_TERST ((uint32_t)0x00002000) /*!< Timer E count software reset */
mbed_official 155:8435094ec241 1983
mbed_official 155:8435094ec241 1984 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
mbed_official 155:8435094ec241 1985 #define HRTIM_ISR_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag */
mbed_official 155:8435094ec241 1986 #define HRTIM_ISR_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag */
mbed_official 155:8435094ec241 1987 #define HRTIM_ISR_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag */
mbed_official 155:8435094ec241 1988 #define HRTIM_ISR_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag */
mbed_official 155:8435094ec241 1989 #define HRTIM_ISR_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag */
mbed_official 155:8435094ec241 1990 #define HRTIM_ISR_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt flag */
mbed_official 155:8435094ec241 1991 #define HRTIM_ISR_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt flag */
mbed_official 155:8435094ec241 1992 #define HRTIM_ISR_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag */
mbed_official 155:8435094ec241 1993
mbed_official 155:8435094ec241 1994 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
mbed_official 155:8435094ec241 1995 #define HRTIM_ICR_FLT1C ((uint32_t)0x00000001) /*!< Fault 1 interrupt flag clear */
mbed_official 155:8435094ec241 1996 #define HRTIM_ICR_FLT2C ((uint32_t)0x00000002) /*!< Fault 2 interrupt flag clear */
mbed_official 155:8435094ec241 1997 #define HRTIM_ICR_FLT3C ((uint32_t)0x00000004) /*!< Fault 3 interrupt flag clear */
mbed_official 155:8435094ec241 1998 #define HRTIM_ICR_FLT4C ((uint32_t)0x00000008) /*!< Fault 4 interrupt flag clear */
mbed_official 155:8435094ec241 1999 #define HRTIM_ICR_FLT5C ((uint32_t)0x00000010) /*!< Fault 5 interrupt flag clear */
mbed_official 155:8435094ec241 2000 #define HRTIM_ICR_SYSFLTC ((uint32_t)0x00000020) /*!< System Fault interrupt flag clear */
mbed_official 155:8435094ec241 2001 #define HRTIM_ICR_DLLRDYC ((uint32_t)0x00010000) /*!< DLL ready interrupt flag clear */
mbed_official 155:8435094ec241 2002 #define HRTIM_ICR_BMPERC ((uint32_t)0x00020000) /*!< Burst mode period interrupt flag clear */
mbed_official 155:8435094ec241 2003
mbed_official 155:8435094ec241 2004 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
mbed_official 155:8435094ec241 2005 #define HRTIM_IER_FLT1 ((uint32_t)0x00000001) /*!< Fault 1 interrupt enable */
mbed_official 155:8435094ec241 2006 #define HRTIM_IER_FLT2 ((uint32_t)0x00000002) /*!< Fault 2 interrupt enable */
mbed_official 155:8435094ec241 2007 #define HRTIM_IER_FLT3 ((uint32_t)0x00000004) /*!< Fault 3 interrupt enable */
mbed_official 155:8435094ec241 2008 #define HRTIM_IER_FLT4 ((uint32_t)0x00000008) /*!< Fault 4 interrupt enable */
mbed_official 155:8435094ec241 2009 #define HRTIM_IER_FLT5 ((uint32_t)0x00000010) /*!< Fault 5 interrupt enable */
mbed_official 155:8435094ec241 2010 #define HRTIM_IER_SYSFLT ((uint32_t)0x00000020) /*!< System Fault interrupt enable */
mbed_official 155:8435094ec241 2011 #define HRTIM_IER_DLLRDY ((uint32_t)0x00010000) /*!< DLL ready interrupt enable */
mbed_official 155:8435094ec241 2012 #define HRTIM_IER_BMPER ((uint32_t)0x00020000) /*!< Burst mode period interrupt enable */
mbed_official 155:8435094ec241 2013
mbed_official 155:8435094ec241 2014 /**** Bit definition for Common HRTIM Timer output enable register ************/
mbed_official 155:8435094ec241 2015 #define HRTIM_OENR_TA1OEN ((uint32_t)0x00000001) /*!< Timer A Output 1 enable */
mbed_official 155:8435094ec241 2016 #define HRTIM_OENR_TA2OEN ((uint32_t)0x00000002) /*!< Timer A Output 2 enable */
mbed_official 155:8435094ec241 2017 #define HRTIM_OENR_TB1OEN ((uint32_t)0x00000004) /*!< Timer B Output 1 enable */
mbed_official 155:8435094ec241 2018 #define HRTIM_OENR_TB2OEN ((uint32_t)0x00000008) /*!< Timer B Output 2 enable */
mbed_official 155:8435094ec241 2019 #define HRTIM_OENR_TC1OEN ((uint32_t)0x00000010) /*!< Timer C Output 1 enable */
mbed_official 155:8435094ec241 2020 #define HRTIM_OENR_TC2OEN ((uint32_t)0x00000020) /*!< Timer C Output 2 enable */
mbed_official 155:8435094ec241 2021 #define HRTIM_OENR_TD1OEN ((uint32_t)0x00000040) /*!< Timer D Output 1 enable */
mbed_official 155:8435094ec241 2022 #define HRTIM_OENR_TD2OEN ((uint32_t)0x00000080) /*!< Timer D Output 2 enable */
mbed_official 155:8435094ec241 2023 #define HRTIM_OENR_TE1OEN ((uint32_t)0x00000100) /*!< Timer E Output 1 enable */
mbed_official 155:8435094ec241 2024 #define HRTIM_OENR_TE2OEN ((uint32_t)0x00000200) /*!< Timer E Output 2 enable */
mbed_official 155:8435094ec241 2025
mbed_official 155:8435094ec241 2026 /**** Bit definition for Common HRTIM Timer output disable register ***********/
mbed_official 155:8435094ec241 2027 #define HRTIM_ODISR_TA1ODIS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable */
mbed_official 155:8435094ec241 2028 #define HRTIM_ODISR_TA2ODIS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable */
mbed_official 155:8435094ec241 2029 #define HRTIM_ODISR_TB1ODIS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable */
mbed_official 155:8435094ec241 2030 #define HRTIM_ODISR_TB2ODIS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable */
mbed_official 155:8435094ec241 2031 #define HRTIM_ODISR_TC1ODIS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable */
mbed_official 155:8435094ec241 2032 #define HRTIM_ODISR_TC2ODIS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable */
mbed_official 155:8435094ec241 2033 #define HRTIM_ODISR_TD1ODIS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable */
mbed_official 155:8435094ec241 2034 #define HRTIM_ODISR_TD2ODIS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable */
mbed_official 155:8435094ec241 2035 #define HRTIM_ODISR_TE1ODIS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable */
mbed_official 155:8435094ec241 2036 #define HRTIM_ODISR_TE2ODIS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable */
mbed_official 155:8435094ec241 2037
mbed_official 155:8435094ec241 2038 /**** Bit definition for Common HRTIM Timer output disable status register *****/
mbed_official 155:8435094ec241 2039 #define HRTIM_ODSR_TA1ODS ((uint32_t)0x00000001) /*!< Timer A Output 1 disable status */
mbed_official 155:8435094ec241 2040 #define HRTIM_ODSR_TA2ODS ((uint32_t)0x00000002) /*!< Timer A Output 2 disable status */
mbed_official 155:8435094ec241 2041 #define HRTIM_ODSR_TB1ODS ((uint32_t)0x00000004) /*!< Timer B Output 1 disable status */
mbed_official 155:8435094ec241 2042 #define HRTIM_ODSR_TB2ODS ((uint32_t)0x00000008) /*!< Timer B Output 2 disable status */
mbed_official 155:8435094ec241 2043 #define HRTIM_ODSR_TC1ODS ((uint32_t)0x00000010) /*!< Timer C Output 1 disable status */
mbed_official 155:8435094ec241 2044 #define HRTIM_ODSR_TC2ODS ((uint32_t)0x00000020) /*!< Timer C Output 2 disable status */
mbed_official 155:8435094ec241 2045 #define HRTIM_ODSR_TD1ODS ((uint32_t)0x00000040) /*!< Timer D Output 1 disable status */
mbed_official 155:8435094ec241 2046 #define HRTIM_ODSR_TD2ODS ((uint32_t)0x00000080) /*!< Timer D Output 2 disable status */
mbed_official 155:8435094ec241 2047 #define HRTIM_ODSR_TE1ODS ((uint32_t)0x00000100) /*!< Timer E Output 1 disable status */
mbed_official 155:8435094ec241 2048 #define HRTIM_ODSR_TE2ODS ((uint32_t)0x00000200) /*!< Timer E Output 2 disable status */
mbed_official 155:8435094ec241 2049
mbed_official 155:8435094ec241 2050 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
mbed_official 155:8435094ec241 2051 #define HRTIM_BMCR_BME ((uint32_t)0x00000001) /*!< Burst mode enable */
mbed_official 155:8435094ec241 2052 #define HRTIM_BMCR_BMOM ((uint32_t)0x00000002) /*!< Burst mode operating mode */
mbed_official 155:8435094ec241 2053 #define HRTIM_BMCR_BMCLK ((uint32_t)0x0000003C) /*!< Burst mode clock source */
mbed_official 155:8435094ec241 2054 #define HRTIM_BMCR_BMCLK_0 ((uint32_t)0x00000004) /*!< Burst mode clock source bit 0 */
mbed_official 155:8435094ec241 2055 #define HRTIM_BMCR_BMCLK_1 ((uint32_t)0x00000008) /*!< Burst mode clock source bit 1 */
mbed_official 155:8435094ec241 2056 #define HRTIM_BMCR_BMCLK_2 ((uint32_t)0x00000010) /*!< Burst mode clock source bit 2 */
mbed_official 155:8435094ec241 2057 #define HRTIM_BMCR_BMCLK_3 ((uint32_t)0x00000020) /*!< Burst mode clock source bit 3 */
mbed_official 155:8435094ec241 2058 #define HRTIM_BMCR_BMPSC ((uint32_t)0x000003C0) /*!< Burst mode prescaler */
mbed_official 155:8435094ec241 2059 #define HRTIM_BMCR_BMPSC_0 ((uint32_t)0x00000040) /*!< Burst mode prescaler bit 0 */
mbed_official 155:8435094ec241 2060 #define HRTIM_BMCR_BMPSC_1 ((uint32_t)0x00000080) /*!< Burst mode prescaler bit 1 */
mbed_official 155:8435094ec241 2061 #define HRTIM_BMCR_BMPSC_2 ((uint32_t)0x00000100) /*!< Burst mode prescaler bit 2 */
mbed_official 155:8435094ec241 2062 #define HRTIM_BMCR_BMPSC_3 ((uint32_t)0x00000200) /*!< Burst mode prescaler bit 3 */
mbed_official 155:8435094ec241 2063 #define HRTIM_BMCR_BMPREN ((uint32_t)0x00000400) /*!< Burst mode Preload bit */
mbed_official 155:8435094ec241 2064 #define HRTIM_BMCR_MTBM ((uint32_t)0x00010000) /*!< Master Timer Burst mode */
mbed_official 155:8435094ec241 2065 #define HRTIM_BMCR_TABM ((uint32_t)0x00020000) /*!< Timer A Burst mode */
mbed_official 155:8435094ec241 2066 #define HRTIM_BMCR_TBBM ((uint32_t)0x00040000) /*!< Timer B Burst mode */
mbed_official 155:8435094ec241 2067 #define HRTIM_BMCR_TCBM ((uint32_t)0x00080000) /*!< Timer C Burst mode */
mbed_official 155:8435094ec241 2068 #define HRTIM_BMCR_TDBM ((uint32_t)0x00100000) /*!< Timer D Burst mode */
mbed_official 155:8435094ec241 2069 #define HRTIM_BMCR_TEBM ((uint32_t)0x00200000) /*!< Timer E Burst mode */
mbed_official 155:8435094ec241 2070 #define HRTIM_BMCR_BMSTAT ((uint32_t)0x80000000) /*!< Burst mode status */
mbed_official 155:8435094ec241 2071
mbed_official 155:8435094ec241 2072 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
mbed_official 155:8435094ec241 2073 #define HRTIM_BMTRGR_SW ((uint32_t)0x00000001) /*!< Software start */
mbed_official 155:8435094ec241 2074 #define HRTIM_BMTRGR_MSTRST ((uint32_t)0x00000002) /*!< Master reset */
mbed_official 155:8435094ec241 2075 #define HRTIM_BMTRGR_MSTREP ((uint32_t)0x00000004) /*!< Master repetition */
mbed_official 155:8435094ec241 2076 #define HRTIM_BMTRGR_MSTCMP1 ((uint32_t)0x00000008) /*!< Master compare 1 */
mbed_official 155:8435094ec241 2077 #define HRTIM_BMTRGR_MSTCMP2 ((uint32_t)0x00000010) /*!< Master compare 2 */
mbed_official 155:8435094ec241 2078 #define HRTIM_BMTRGR_MSTCMP3 ((uint32_t)0x00000020) /*!< Master compare 3 */
mbed_official 155:8435094ec241 2079 #define HRTIM_BMTRGR_MSTCMP4 ((uint32_t)0x00000040) /*!< Master compare 4 */
mbed_official 155:8435094ec241 2080 #define HRTIM_BMTRGR_TARST ((uint32_t)0x00000080) /*!< Timer A reset */
mbed_official 155:8435094ec241 2081 #define HRTIM_BMTRGR_TAREP ((uint32_t)0x00000100) /*!< Timer A repetition */
mbed_official 155:8435094ec241 2082 #define HRTIM_BMTRGR_TACMP1 ((uint32_t)0x00000200) /*!< Timer A compare 1 */
mbed_official 155:8435094ec241 2083 #define HRTIM_BMTRGR_TACMP2 ((uint32_t)0x00000400) /*!< Timer A compare 2 */
mbed_official 155:8435094ec241 2084 #define HRTIM_BMTRGR_TBRST ((uint32_t)0x00000800) /*!< Timer B reset */
mbed_official 155:8435094ec241 2085 #define HRTIM_BMTRGR_TBREP ((uint32_t)0x00001000) /*!< Timer B repetition */
mbed_official 155:8435094ec241 2086 #define HRTIM_BMTRGR_TBCMP1 ((uint32_t)0x00002000) /*!< Timer B compare 1 */
mbed_official 155:8435094ec241 2087 #define HRTIM_BMTRGR_TBCMP2 ((uint32_t)0x00004000) /*!< Timer B compare 2 */
mbed_official 155:8435094ec241 2088 #define HRTIM_BMTRGR_TCRST ((uint32_t)0x00008000) /*!< Timer C reset */
mbed_official 155:8435094ec241 2089 #define HRTIM_BMTRGR_TCREP ((uint32_t)0x00010000) /*!< Timer C repetition */
mbed_official 155:8435094ec241 2090 #define HRTIM_BMTRGR_TCCMP1 ((uint32_t)0x00020000) /*!< Timer C compare 1 */
mbed_official 155:8435094ec241 2091 #define HRTIM_BMTRGR_TCCMP2 ((uint32_t)0x00040000) /*!< Timer C compare 2 */
mbed_official 155:8435094ec241 2092 #define HRTIM_BMTRGR_TDRST ((uint32_t)0x00080000) /*!< Timer D reset */
mbed_official 155:8435094ec241 2093 #define HRTIM_BMTRGR_TDREP ((uint32_t)0x00100000) /*!< Timer D repetition */
mbed_official 155:8435094ec241 2094 #define HRTIM_BMTRGR_TDCMP1 ((uint32_t)0x00200000) /*!< Timer D compare 1 */
mbed_official 155:8435094ec241 2095 #define HRTIM_BMTRGR_TDCMP2 ((uint32_t)0x00400000) /*!< Timer D compare 2 */
mbed_official 155:8435094ec241 2096 #define HRTIM_BMTRGR_TERST ((uint32_t)0x00800000) /*!< Timer E reset */
mbed_official 155:8435094ec241 2097 #define HRTIM_BMTRGR_TEREP ((uint32_t)0x01000000) /*!< Timer E repetition */
mbed_official 155:8435094ec241 2098 #define HRTIM_BMTRGR_TECMP1 ((uint32_t)0x02000000) /*!< Timer E compare 1 */
mbed_official 155:8435094ec241 2099 #define HRTIM_BMTRGR_TECMP2 ((uint32_t)0x04000000) /*!< Timer E compare 2 */
mbed_official 155:8435094ec241 2100 #define HRTIM_BMTRGR_TAEEV7 ((uint32_t)0x08000000) /*!< Timer A period following External Event7 */
mbed_official 155:8435094ec241 2101 #define HRTIM_BMTRGR_TDEEV8 ((uint32_t)0x10000000) /*!< Timer D period following External Event8 */
mbed_official 155:8435094ec241 2102 #define HRTIM_BMTRGR_EEV7 ((uint32_t)0x20000000) /*!< External Event 7 */
mbed_official 155:8435094ec241 2103 #define HRTIM_BMTRGR_EEV8 ((uint32_t)0x40000000) /*!< External Event 8 */
mbed_official 155:8435094ec241 2104 #define HRTIM_BMTRGR_OCHPEV ((uint32_t)0x80000000) /*!< on-chip Event */
mbed_official 155:8435094ec241 2105
mbed_official 155:8435094ec241 2106 /******************* Bit definition for HRTIM_BMCMPR register ***************/
mbed_official 155:8435094ec241 2107 #define HRTIM_BMCMPR_BMCMPR ((uint32_t)0x0000FFFF) /*!<!<Burst Compare Value */
mbed_official 155:8435094ec241 2108
mbed_official 155:8435094ec241 2109 /******************* Bit definition for HRTIM_BMPER register ****************/
mbed_official 155:8435094ec241 2110 #define HRTIM_BMPER_BMPER ((uint32_t)0x0000FFFF) /*!<!<Burst period Value */
mbed_official 155:8435094ec241 2111
mbed_official 155:8435094ec241 2112 /******************* Bit definition for HRTIM_EECR1 register ****************/
mbed_official 155:8435094ec241 2113 #define HRTIM_EECR1_EE1SRC ((uint32_t)0x00000003) /*!< External event 1 source */
mbed_official 155:8435094ec241 2114 #define HRTIM_EECR1_EE1SRC_0 ((uint32_t)0x00000001) /*!< External event 1 source bit 0 */
mbed_official 155:8435094ec241 2115 #define HRTIM_EECR1_EE1SRC_1 ((uint32_t)0x00000002) /*!< External event 1 source bit 1 */
mbed_official 155:8435094ec241 2116 #define HRTIM_EECR1_EE1POL ((uint32_t)0x00000004) /*!< External event 1 Polarity */
mbed_official 155:8435094ec241 2117 #define HRTIM_EECR1_EE1SNS ((uint32_t)0x00000018) /*!< External event 1 sensitivity */
mbed_official 155:8435094ec241 2118 #define HRTIM_EECR1_EE1SNS_0 ((uint32_t)0x00000008) /*!< External event 1 sensitivity bit 0 */
mbed_official 155:8435094ec241 2119 #define HRTIM_EECR1_EE1SNS_1 ((uint32_t)0x00000010) /*!< External event 1 sensitivity bit 1 */
mbed_official 155:8435094ec241 2120 #define HRTIM_EECR1_EE1FAST ((uint32_t)0x00000020) /*!< External event 1 Fast mode */
mbed_official 155:8435094ec241 2121
mbed_official 155:8435094ec241 2122 #define HRTIM_EECR1_EE2SRC ((uint32_t)0x000000C0) /*!< External event 2 source */
mbed_official 155:8435094ec241 2123 #define HRTIM_EECR1_EE2SRC_0 ((uint32_t)0x00000040) /*!< External event 2 source bit 0 */
mbed_official 155:8435094ec241 2124 #define HRTIM_EECR1_EE2SRC_1 ((uint32_t)0x00000080) /*!< External event 2 source bit 1 */
mbed_official 155:8435094ec241 2125 #define HRTIM_EECR1_EE2POL ((uint32_t)0x00000100) /*!< External event 2 Polarity */
mbed_official 155:8435094ec241 2126 #define HRTIM_EECR1_EE2SNS ((uint32_t)0x00000600) /*!< External event 2 sensitivity */
mbed_official 155:8435094ec241 2127 #define HRTIM_EECR1_EE2SNS_0 ((uint32_t)0x00000200) /*!< External event 2 sensitivity bit 0 */
mbed_official 155:8435094ec241 2128 #define HRTIM_EECR1_EE2SNS_1 ((uint32_t)0x00000400) /*!< External event 2 sensitivity bit 1 */
mbed_official 155:8435094ec241 2129 #define HRTIM_EECR1_EE2FAST ((uint32_t)0x00000800) /*!< External event 2 Fast mode */
mbed_official 155:8435094ec241 2130
mbed_official 155:8435094ec241 2131 #define HRTIM_EECR1_EE3SRC ((uint32_t)0x00003000) /*!< External event 3 source */
mbed_official 155:8435094ec241 2132 #define HRTIM_EECR1_EE3SRC_0 ((uint32_t)0x00001000) /*!< External event 3 source bit 0 */
mbed_official 155:8435094ec241 2133 #define HRTIM_EECR1_EE3SRC_1 ((uint32_t)0x00002000) /*!< External event 3 source bit 1 */
mbed_official 155:8435094ec241 2134 #define HRTIM_EECR1_EE3POL ((uint32_t)0x00004000) /*!< External event 3 Polarity */
mbed_official 155:8435094ec241 2135 #define HRTIM_EECR1_EE3SNS ((uint32_t)0x00018000) /*!< External event 3 sensitivity */
mbed_official 155:8435094ec241 2136 #define HRTIM_EECR1_EE3SNS_0 ((uint32_t)0x00008000) /*!< External event 3 sensitivity bit 0 */
mbed_official 155:8435094ec241 2137 #define HRTIM_EECR1_EE3SNS_1 ((uint32_t)0x00010000) /*!< External event 3 sensitivity bit 1 */
mbed_official 155:8435094ec241 2138 #define HRTIM_EECR1_EE3FAST ((uint32_t)0x00020000) /*!< External event 3 Fast mode */
mbed_official 155:8435094ec241 2139
mbed_official 155:8435094ec241 2140 #define HRTIM_EECR1_EE4SRC ((uint32_t)0x000C0000) /*!< External event 4 source */
mbed_official 155:8435094ec241 2141 #define HRTIM_EECR1_EE4SRC_0 ((uint32_t)0x00040000) /*!< External event 4 source bit 0 */
mbed_official 155:8435094ec241 2142 #define HRTIM_EECR1_EE4SRC_1 ((uint32_t)0x00080000) /*!< External event 4 source bit 1 */
mbed_official 155:8435094ec241 2143 #define HRTIM_EECR1_EE4POL ((uint32_t)0x00100000) /*!< External event 4 Polarity */
mbed_official 155:8435094ec241 2144 #define HRTIM_EECR1_EE4SNS ((uint32_t)0x00600000) /*!< External event 4 sensitivity */
mbed_official 155:8435094ec241 2145 #define HRTIM_EECR1_EE4SNS_0 ((uint32_t)0x00200000) /*!< External event 4 sensitivity bit 0 */
mbed_official 155:8435094ec241 2146 #define HRTIM_EECR1_EE4SNS_1 ((uint32_t)0x00400000) /*!< External event 4 sensitivity bit 1 */
mbed_official 155:8435094ec241 2147 #define HRTIM_EECR1_EE4FAST ((uint32_t)0x00800000) /*!< External event 4 Fast mode */
mbed_official 155:8435094ec241 2148
mbed_official 155:8435094ec241 2149 #define HRTIM_EECR1_EE5SRC ((uint32_t)0x03000000) /*!< External event 5 source */
mbed_official 155:8435094ec241 2150 #define HRTIM_EECR1_EE5SRC_0 ((uint32_t)0x01000000) /*!< External event 5 source bit 0 */
mbed_official 155:8435094ec241 2151 #define HRTIM_EECR1_EE5SRC_1 ((uint32_t)0x02000000) /*!< External event 5 source bit 1 */
mbed_official 155:8435094ec241 2152 #define HRTIM_EECR1_EE5POL ((uint32_t)0x04000000) /*!< External event 5 Polarity */
mbed_official 155:8435094ec241 2153 #define HRTIM_EECR1_EE5SNS ((uint32_t)0x18000000) /*!< External event 5 sensitivity */
mbed_official 155:8435094ec241 2154 #define HRTIM_EECR1_EE5SNS_0 ((uint32_t)0x08000000) /*!< External event 5 sensitivity bit 0 */
mbed_official 155:8435094ec241 2155 #define HRTIM_EECR1_EE5SNS_1 ((uint32_t)0x10000000) /*!< External event 5 sensitivity bit 1 */
mbed_official 155:8435094ec241 2156 #define HRTIM_EECR1_EE5FAST ((uint32_t)0x20000000) /*!< External event 5 Fast mode */
mbed_official 155:8435094ec241 2157
mbed_official 155:8435094ec241 2158 /******************* Bit definition for HRTIM_EECR2 register ****************/
mbed_official 155:8435094ec241 2159 #define HRTIM_EECR2_EE6SRC ((uint32_t)0x00000003) /*!< External event 6 source */
mbed_official 155:8435094ec241 2160 #define HRTIM_EECR2_EE6SRC_0 ((uint32_t)0x00000001) /*!< External event 6 source bit 0 */
mbed_official 155:8435094ec241 2161 #define HRTIM_EECR2_EE6SRC_1 ((uint32_t)0x00000002) /*!< External event 6 source bit 1 */
mbed_official 155:8435094ec241 2162 #define HRTIM_EECR2_EE6POL ((uint32_t)0x00000004) /*!< External event 6 Polarity */
mbed_official 155:8435094ec241 2163 #define HRTIM_EECR2_EE6SNS ((uint32_t)0x00000018) /*!< External event 6 sensitivity */
mbed_official 155:8435094ec241 2164 #define HRTIM_EECR2_EE6SNS_0 ((uint32_t)0x00000008) /*!< External event 6 sensitivity bit 0 */
mbed_official 155:8435094ec241 2165 #define HRTIM_EECR2_EE6SNS_1 ((uint32_t)0x00000010) /*!< External event 6 sensitivity bit 1 */
mbed_official 155:8435094ec241 2166
mbed_official 155:8435094ec241 2167 #define HRTIM_EECR2_EE7SRC ((uint32_t)0x000000C0) /*!< External event 7 source */
mbed_official 155:8435094ec241 2168 #define HRTIM_EECR2_EE7SRC_0 ((uint32_t)0x00000040) /*!< External event 7 source bit 0 */
mbed_official 155:8435094ec241 2169 #define HRTIM_EECR2_EE7SRC_1 ((uint32_t)0x00000080) /*!< External event 7 source bit 1 */
mbed_official 155:8435094ec241 2170 #define HRTIM_EECR2_EE7POL ((uint32_t)0x00000100) /*!< External event 7 Polarity */
mbed_official 155:8435094ec241 2171 #define HRTIM_EECR2_EE7SNS ((uint32_t)0x00000600) /*!< External event 7 sensitivity */
mbed_official 155:8435094ec241 2172 #define HRTIM_EECR2_EE7SNS_0 ((uint32_t)0x00000200) /*!< External event 7 sensitivity bit 0 */
mbed_official 155:8435094ec241 2173 #define HRTIM_EECR2_EE7SNS_1 ((uint32_t)0x00000400) /*!< External event 7 sensitivity bit 1 */
mbed_official 155:8435094ec241 2174
mbed_official 155:8435094ec241 2175 #define HRTIM_EECR2_EE8SRC ((uint32_t)0x00003000) /*!< External event 8 source */
mbed_official 155:8435094ec241 2176 #define HRTIM_EECR2_EE8SRC_0 ((uint32_t)0x00001000) /*!< External event 8 source bit 0 */
mbed_official 155:8435094ec241 2177 #define HRTIM_EECR2_EE8SRC_1 ((uint32_t)0x00002000) /*!< External event 8 source bit 1 */
mbed_official 155:8435094ec241 2178 #define HRTIM_EECR2_EE8POL ((uint32_t)0x00004000) /*!< External event 8 Polarity */
mbed_official 155:8435094ec241 2179 #define HRTIM_EECR2_EE8SNS ((uint32_t)0x00018000) /*!< External event 8 sensitivity */
mbed_official 155:8435094ec241 2180 #define HRTIM_EECR2_EE8SNS_0 ((uint32_t)0x00008000) /*!< External event 8 sensitivity bit 0 */
mbed_official 155:8435094ec241 2181 #define HRTIM_EECR2_EE8SNS_1 ((uint32_t)0x00010000) /*!< External event 8 sensitivity bit 1 */
mbed_official 155:8435094ec241 2182
mbed_official 155:8435094ec241 2183 #define HRTIM_EECR2_EE9SRC ((uint32_t)0x000C0000) /*!< External event 9 source */
mbed_official 155:8435094ec241 2184 #define HRTIM_EECR2_EE9SRC_0 ((uint32_t)0x00040000) /*!< External event 9 source bit 0 */
mbed_official 155:8435094ec241 2185 #define HRTIM_EECR2_EE9SRC_1 ((uint32_t)0x00080000) /*!< External event 9 source bit 1 */
mbed_official 155:8435094ec241 2186 #define HRTIM_EECR2_EE9POL ((uint32_t)0x00100000) /*!< External event 9 Polarity */
mbed_official 155:8435094ec241 2187 #define HRTIM_EECR2_EE9SNS ((uint32_t)0x00600000) /*!< External event 9 sensitivity */
mbed_official 155:8435094ec241 2188 #define HRTIM_EECR2_EE9SNS_0 ((uint32_t)0x00200000) /*!< External event 9 sensitivity bit 0 */
mbed_official 155:8435094ec241 2189 #define HRTIM_EECR2_EE9SNS_1 ((uint32_t)0x00400000) /*!< External event 9 sensitivity bit 1 */
mbed_official 155:8435094ec241 2190
mbed_official 155:8435094ec241 2191 #define HRTIM_EECR2_EE10SRC ((uint32_t)0x03000000) /*!< External event 10 source */
mbed_official 155:8435094ec241 2192 #define HRTIM_EECR2_EE10SRC_0 ((uint32_t)0x01000000) /*!< External event 10 source bit 0 */
mbed_official 155:8435094ec241 2193 #define HRTIM_EECR2_EE10SRC_1 ((uint32_t)0x02000000) /*!< External event 10 source bit 1 */
mbed_official 155:8435094ec241 2194 #define HRTIM_EECR2_EE10POL ((uint32_t)0x04000000) /*!< External event 10 Polarity */
mbed_official 155:8435094ec241 2195 #define HRTIM_EECR2_EE10SNS ((uint32_t)0x18000000) /*!< External event 10 sensitivity */
mbed_official 155:8435094ec241 2196 #define HRTIM_EECR2_EE10SNS_0 ((uint32_t)0x08000000) /*!< External event 10 sensitivity bit 0 */
mbed_official 155:8435094ec241 2197 #define HRTIM_EECR2_EE10SNS_1 ((uint32_t)0x10000000) /*!< External event 10 sensitivity bit 1 */
mbed_official 155:8435094ec241 2198
mbed_official 155:8435094ec241 2199 /******************* Bit definition for HRTIM_EECR3 register ****************/
mbed_official 155:8435094ec241 2200 #define HRTIM_EECR3_EE6F ((uint32_t)0x0000000F) /*!< External event 6 filter */
mbed_official 155:8435094ec241 2201 #define HRTIM_EECR3_EE6F_0 ((uint32_t)0x00000001) /*!< External event 6 filter bit 0 */
mbed_official 155:8435094ec241 2202 #define HRTIM_EECR3_EE6F_1 ((uint32_t)0x00000002) /*!< External event 6 filter bit 1 */
mbed_official 155:8435094ec241 2203 #define HRTIM_EECR3_EE6F_2 ((uint32_t)0x00000004) /*!< External event 6 filter bit 2 */
mbed_official 155:8435094ec241 2204 #define HRTIM_EECR3_EE6F_3 ((uint32_t)0x00000008) /*!< External event 6 filter bit 3 */
mbed_official 155:8435094ec241 2205 #define HRTIM_EECR3_EE7F ((uint32_t)0x000003C0) /*!< External event 7 filter */
mbed_official 155:8435094ec241 2206 #define HRTIM_EECR3_EE7F_0 ((uint32_t)0x00000040) /*!< External event 7 filter bit 0 */
mbed_official 155:8435094ec241 2207 #define HRTIM_EECR3_EE7F_1 ((uint32_t)0x00000080) /*!< External event 7 filter bit 1 */
mbed_official 155:8435094ec241 2208 #define HRTIM_EECR3_EE7F_2 ((uint32_t)0x00000100) /*!< External event 7 filter bit 2 */
mbed_official 155:8435094ec241 2209 #define HRTIM_EECR3_EE7F_3 ((uint32_t)0x00000200) /*!< External event 7 filter bit 3 */
mbed_official 155:8435094ec241 2210 #define HRTIM_EECR3_EE8F ((uint32_t)0x0000F000) /*!< External event 8 filter */
mbed_official 155:8435094ec241 2211 #define HRTIM_EECR3_EE8F_0 ((uint32_t)0x00001000) /*!< External event 8 filter bit 0 */
mbed_official 155:8435094ec241 2212 #define HRTIM_EECR3_EE8F_1 ((uint32_t)0x00002000) /*!< External event 8 filter bit 1 */
mbed_official 155:8435094ec241 2213 #define HRTIM_EECR3_EE8F_2 ((uint32_t)0x00004000) /*!< External event 8 filter bit 2 */
mbed_official 155:8435094ec241 2214 #define HRTIM_EECR3_EE8F_3 ((uint32_t)0x00008000) /*!< External event 8 filter bit 3 */
mbed_official 155:8435094ec241 2215 #define HRTIM_EECR3_EE9F ((uint32_t)0x003C0000) /*!< External event 9 filter */
mbed_official 155:8435094ec241 2216 #define HRTIM_EECR3_EE9F_0 ((uint32_t)0x00040000) /*!< External event 9 filter bit 0 */
mbed_official 155:8435094ec241 2217 #define HRTIM_EECR3_EE9F_1 ((uint32_t)0x00080000) /*!< External event 9 filter bit 1 */
mbed_official 155:8435094ec241 2218 #define HRTIM_EECR3_EE9F_2 ((uint32_t)0x00100000) /*!< External event 9 filter bit 2 */
mbed_official 155:8435094ec241 2219 #define HRTIM_EECR3_EE9F_3 ((uint32_t)0x00200000) /*!< External event 9 filter bit 3 */
mbed_official 155:8435094ec241 2220 #define HRTIM_EECR3_EE10F ((uint32_t)0x0F000000) /*!< External event 10 filter */
mbed_official 155:8435094ec241 2221 #define HRTIM_EECR3_EE10F_0 ((uint32_t)0x01000000) /*!< External event 10 filter bit 0 */
mbed_official 155:8435094ec241 2222 #define HRTIM_EECR3_EE10F_1 ((uint32_t)0x02000000) /*!< External event 10 filter bit 1 */
mbed_official 155:8435094ec241 2223 #define HRTIM_EECR3_EE10F_2 ((uint32_t)0x04000000) /*!< External event 10 filter bit 2 */
mbed_official 155:8435094ec241 2224 #define HRTIM_EECR3_EE10F_3 ((uint32_t)0x08000000) /*!< External event 10 filter bit 3 */
mbed_official 155:8435094ec241 2225 #define HRTIM_EECR3_EEVSD ((uint32_t)0xC0000000) /*!< External event sampling clock division */
mbed_official 155:8435094ec241 2226 #define HRTIM_EECR3_EEVSD_0 ((uint32_t)0x40000000) /*!< External event sampling clock division bit 0 */
mbed_official 155:8435094ec241 2227 #define HRTIM_EECR3_EEVSD_1 ((uint32_t)0x80000000) /*!< External event sampling clock division bit 1 */
mbed_official 155:8435094ec241 2228
mbed_official 155:8435094ec241 2229 /******************* Bit definition for HRTIM_ADC1R register ****************/
mbed_official 155:8435094ec241 2230 #define HRTIM_ADC1R_AD1MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 1 on master compare 1 */
mbed_official 155:8435094ec241 2231 #define HRTIM_ADC1R_AD1MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 1 on master compare 2 */
mbed_official 155:8435094ec241 2232 #define HRTIM_ADC1R_AD1MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 1 on master compare 3 */
mbed_official 155:8435094ec241 2233 #define HRTIM_ADC1R_AD1MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 1 on master compare 4 */
mbed_official 155:8435094ec241 2234 #define HRTIM_ADC1R_AD1MPER ((uint32_t)0x00000010) /*!< ADC Trigger 1 on master period */
mbed_official 155:8435094ec241 2235 #define HRTIM_ADC1R_AD1EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 1 on external event 1 */
mbed_official 155:8435094ec241 2236 #define HRTIM_ADC1R_AD1EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 1 on external event 2 */
mbed_official 155:8435094ec241 2237 #define HRTIM_ADC1R_AD1EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 1 on external event 3 */
mbed_official 155:8435094ec241 2238 #define HRTIM_ADC1R_AD1EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 1 on external event 4 */
mbed_official 155:8435094ec241 2239 #define HRTIM_ADC1R_AD1EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 1 on external event 5 */
mbed_official 155:8435094ec241 2240 #define HRTIM_ADC1R_AD1TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 1 on Timer A compare 2 */
mbed_official 155:8435094ec241 2241 #define HRTIM_ADC1R_AD1TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 1 on Timer A compare 3 */
mbed_official 155:8435094ec241 2242 #define HRTIM_ADC1R_AD1TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 1 on Timer A compare 4 */
mbed_official 155:8435094ec241 2243 #define HRTIM_ADC1R_AD1TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 1 on Timer A period */
mbed_official 155:8435094ec241 2244 #define HRTIM_ADC1R_AD1TARST ((uint32_t)0x00004000) /*!< ADC Trigger 1 on Timer A reset */
mbed_official 155:8435094ec241 2245 #define HRTIM_ADC1R_AD1TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 1 on Timer B compare 2 */
mbed_official 155:8435094ec241 2246 #define HRTIM_ADC1R_AD1TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 1 on Timer B compare 3 */
mbed_official 155:8435094ec241 2247 #define HRTIM_ADC1R_AD1TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 1 on Timer B compare 4 */
mbed_official 155:8435094ec241 2248 #define HRTIM_ADC1R_AD1TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 1 on Timer B period */
mbed_official 155:8435094ec241 2249 #define HRTIM_ADC1R_AD1TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 1 on Timer B reset */
mbed_official 155:8435094ec241 2250 #define HRTIM_ADC1R_AD1TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 1 on Timer C compare 2 */
mbed_official 155:8435094ec241 2251 #define HRTIM_ADC1R_AD1TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 1 on Timer C compare 3 */
mbed_official 155:8435094ec241 2252 #define HRTIM_ADC1R_AD1TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 1 on Timer C compare 4 */
mbed_official 155:8435094ec241 2253 #define HRTIM_ADC1R_AD1TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 1 on Timer C period */
mbed_official 155:8435094ec241 2254 #define HRTIM_ADC1R_AD1TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 1 on Timer D compare 2 */
mbed_official 155:8435094ec241 2255 #define HRTIM_ADC1R_AD1TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 1 on Timer D compare 3 */
mbed_official 155:8435094ec241 2256 #define HRTIM_ADC1R_AD1TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 1 on Timer D compare 4 */
mbed_official 155:8435094ec241 2257 #define HRTIM_ADC1R_AD1TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 1 on Timer D period */
mbed_official 155:8435094ec241 2258 #define HRTIM_ADC1R_AD1TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 1 on Timer E compare 2 */
mbed_official 155:8435094ec241 2259 #define HRTIM_ADC1R_AD1TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 1 on Timer E compare 3 */
mbed_official 155:8435094ec241 2260 #define HRTIM_ADC1R_AD1TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 1 on Timer E compare 4 */
mbed_official 155:8435094ec241 2261 #define HRTIM_ADC1R_AD1TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 1 on Timer E period */
mbed_official 155:8435094ec241 2262
mbed_official 155:8435094ec241 2263 /******************* Bit definition for HRTIM_ADC2R register ****************/
mbed_official 155:8435094ec241 2264 #define HRTIM_ADC2R_AD2MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 2 on master compare 1 */
mbed_official 155:8435094ec241 2265 #define HRTIM_ADC2R_AD2MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 2 on master compare 2 */
mbed_official 155:8435094ec241 2266 #define HRTIM_ADC2R_AD2MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 2 on master compare 3 */
mbed_official 155:8435094ec241 2267 #define HRTIM_ADC2R_AD2MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 2 on master compare 4 */
mbed_official 155:8435094ec241 2268 #define HRTIM_ADC2R_AD2MPER ((uint32_t)0x00000010) /*!< ADC Trigger 2 on master period */
mbed_official 155:8435094ec241 2269 #define HRTIM_ADC2R_AD2EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 2 on external event 6 */
mbed_official 155:8435094ec241 2270 #define HRTIM_ADC2R_AD2EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 2 on external event 7 */
mbed_official 155:8435094ec241 2271 #define HRTIM_ADC2R_AD2EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 2 on external event 8 */
mbed_official 155:8435094ec241 2272 #define HRTIM_ADC2R_AD2EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 2 on external event 9 */
mbed_official 155:8435094ec241 2273 #define HRTIM_ADC2R_AD2EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 2 on external event 10 */
mbed_official 155:8435094ec241 2274 #define HRTIM_ADC2R_AD2TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 2 on Timer A compare 2 */
mbed_official 155:8435094ec241 2275 #define HRTIM_ADC2R_AD2TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 2 on Timer A compare 3 */
mbed_official 155:8435094ec241 2276 #define HRTIM_ADC2R_AD2TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 2 on Timer A compare 4*/
mbed_official 155:8435094ec241 2277 #define HRTIM_ADC2R_AD2TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 2 on Timer A period */
mbed_official 155:8435094ec241 2278 #define HRTIM_ADC2R_AD2TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 2 on Timer B compare 2 */
mbed_official 155:8435094ec241 2279 #define HRTIM_ADC2R_AD2TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 2 on Timer B compare 3 */
mbed_official 155:8435094ec241 2280 #define HRTIM_ADC2R_AD2TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 2 on Timer B compare 4 */
mbed_official 155:8435094ec241 2281 #define HRTIM_ADC2R_AD2TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 2 on Timer B period */
mbed_official 155:8435094ec241 2282 #define HRTIM_ADC2R_AD2TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 2 on Timer C compare 2 */
mbed_official 155:8435094ec241 2283 #define HRTIM_ADC2R_AD2TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 2 on Timer C compare 3 */
mbed_official 155:8435094ec241 2284 #define HRTIM_ADC2R_AD2TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 2 on Timer C compare 4 */
mbed_official 155:8435094ec241 2285 #define HRTIM_ADC2R_AD2TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 2 on Timer C period */
mbed_official 155:8435094ec241 2286 #define HRTIM_ADC2R_AD2TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 2 on Timer C reset */
mbed_official 155:8435094ec241 2287 #define HRTIM_ADC2R_AD2TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 2 on Timer D compare 2 */
mbed_official 155:8435094ec241 2288 #define HRTIM_ADC2R_AD2TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 2 on Timer D compare 3 */
mbed_official 155:8435094ec241 2289 #define HRTIM_ADC2R_AD2TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 2 on Timer D compare 4*/
mbed_official 155:8435094ec241 2290 #define HRTIM_ADC2R_AD2TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 2 on Timer D period */
mbed_official 155:8435094ec241 2291 #define HRTIM_ADC2R_AD2TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 2 on Timer D reset */
mbed_official 155:8435094ec241 2292 #define HRTIM_ADC2R_AD2TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 2 on Timer E compare 2 */
mbed_official 155:8435094ec241 2293 #define HRTIM_ADC2R_AD2TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 2 on Timer E compare 3 */
mbed_official 155:8435094ec241 2294 #define HRTIM_ADC2R_AD2TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 2 on Timer E compare 4 */
mbed_official 155:8435094ec241 2295 #define HRTIM_ADC2R_AD2TERST ((uint32_t)0x80000000) /*!< ADC Trigger 2 on Timer E reset */
mbed_official 155:8435094ec241 2296
mbed_official 155:8435094ec241 2297 /******************* Bit definition for HRTIM_ADC3R register ****************/
mbed_official 155:8435094ec241 2298 #define HRTIM_ADC3R_AD3MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 3 on master compare 1 */
mbed_official 155:8435094ec241 2299 #define HRTIM_ADC3R_AD3MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 3 on master compare 2 */
mbed_official 155:8435094ec241 2300 #define HRTIM_ADC3R_AD3MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 3 on master compare 3 */
mbed_official 155:8435094ec241 2301 #define HRTIM_ADC3R_AD3MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 3 on master compare 4 */
mbed_official 155:8435094ec241 2302 #define HRTIM_ADC3R_AD3MPER ((uint32_t)0x00000010) /*!< ADC Trigger 3 on master period */
mbed_official 155:8435094ec241 2303 #define HRTIM_ADC3R_AD3EEV1 ((uint32_t)0x00000020) /*!< ADC Trigger 3 on external event 1 */
mbed_official 155:8435094ec241 2304 #define HRTIM_ADC3R_AD3EEV2 ((uint32_t)0x00000040) /*!< ADC Trigger 3 on external event 2 */
mbed_official 155:8435094ec241 2305 #define HRTIM_ADC3R_AD3EEV3 ((uint32_t)0x00000080) /*!< ADC Trigger 3 on external event 3 */
mbed_official 155:8435094ec241 2306 #define HRTIM_ADC3R_AD3EEV4 ((uint32_t)0x00000100) /*!< ADC Trigger 3 on external event 4 */
mbed_official 155:8435094ec241 2307 #define HRTIM_ADC3R_AD3EEV5 ((uint32_t)0x00000200) /*!< ADC Trigger 3 on external event 5 */
mbed_official 155:8435094ec241 2308 #define HRTIM_ADC3R_AD3TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 3 on Timer A compare 2 */
mbed_official 155:8435094ec241 2309 #define HRTIM_ADC3R_AD3TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 3 on Timer A compare 3 */
mbed_official 155:8435094ec241 2310 #define HRTIM_ADC3R_AD3TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 3 on Timer A compare 4 */
mbed_official 155:8435094ec241 2311 #define HRTIM_ADC3R_AD3TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 3 on Timer A period */
mbed_official 155:8435094ec241 2312 #define HRTIM_ADC3R_AD3TARST ((uint32_t)0x00004000) /*!< ADC Trigger 3 on Timer A reset */
mbed_official 155:8435094ec241 2313 #define HRTIM_ADC3R_AD3TBC2 ((uint32_t)0x00008000) /*!< ADC Trigger 3 on Timer B compare 2 */
mbed_official 155:8435094ec241 2314 #define HRTIM_ADC3R_AD3TBC3 ((uint32_t)0x00010000) /*!< ADC Trigger 3 on Timer B compare 3 */
mbed_official 155:8435094ec241 2315 #define HRTIM_ADC3R_AD3TBC4 ((uint32_t)0x00020000) /*!< ADC Trigger 3 on Timer B compare 4 */
mbed_official 155:8435094ec241 2316 #define HRTIM_ADC3R_AD3TBPER ((uint32_t)0x00040000) /*!< ADC Trigger 3 on Timer B period */
mbed_official 155:8435094ec241 2317 #define HRTIM_ADC3R_AD3TBRST ((uint32_t)0x00080000) /*!< ADC Trigger 3 on Timer B reset */
mbed_official 155:8435094ec241 2318 #define HRTIM_ADC3R_AD3TCC2 ((uint32_t)0x00100000) /*!< ADC Trigger 3 on Timer C compare 2 */
mbed_official 155:8435094ec241 2319 #define HRTIM_ADC3R_AD3TCC3 ((uint32_t)0x00200000) /*!< ADC Trigger 3 on Timer C compare 3 */
mbed_official 155:8435094ec241 2320 #define HRTIM_ADC3R_AD3TCC4 ((uint32_t)0x00400000) /*!< ADC Trigger 3 on Timer C compare 4 */
mbed_official 155:8435094ec241 2321 #define HRTIM_ADC3R_AD3TCPER ((uint32_t)0x00800000) /*!< ADC Trigger 3 on Timer C period */
mbed_official 155:8435094ec241 2322 #define HRTIM_ADC3R_AD3TDC2 ((uint32_t)0x01000000) /*!< ADC Trigger 3 on Timer D compare 2 */
mbed_official 155:8435094ec241 2323 #define HRTIM_ADC3R_AD3TDC3 ((uint32_t)0x02000000) /*!< ADC Trigger 3 on Timer D compare 3 */
mbed_official 155:8435094ec241 2324 #define HRTIM_ADC3R_AD3TDC4 ((uint32_t)0x04000000) /*!< ADC Trigger 3 on Timer D compare 4 */
mbed_official 155:8435094ec241 2325 #define HRTIM_ADC3R_AD3TDPER ((uint32_t)0x08000000) /*!< ADC Trigger 3 on Timer D period */
mbed_official 155:8435094ec241 2326 #define HRTIM_ADC3R_AD3TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 3 on Timer E compare 2 */
mbed_official 155:8435094ec241 2327 #define HRTIM_ADC3R_AD3TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 3 on Timer E compare 3 */
mbed_official 155:8435094ec241 2328 #define HRTIM_ADC3R_AD3TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 3 on Timer E compare 4 */
mbed_official 155:8435094ec241 2329 #define HRTIM_ADC3R_AD3TEPER ((uint32_t)0x80000000) /*!< ADC Trigger 3 on Timer E period */
mbed_official 155:8435094ec241 2330
mbed_official 155:8435094ec241 2331 /******************* Bit definition for HRTIM_ADC4R register ****************/
mbed_official 155:8435094ec241 2332 #define HRTIM_ADC4R_AD4MC1 ((uint32_t)0x00000001) /*!< ADC Trigger 4 on master compare 1 */
mbed_official 155:8435094ec241 2333 #define HRTIM_ADC4R_AD4MC2 ((uint32_t)0x00000002) /*!< ADC Trigger 4 on master compare 2 */
mbed_official 155:8435094ec241 2334 #define HRTIM_ADC4R_AD4MC3 ((uint32_t)0x00000004) /*!< ADC Trigger 4 on master compare 3 */
mbed_official 155:8435094ec241 2335 #define HRTIM_ADC4R_AD4MC4 ((uint32_t)0x00000008) /*!< ADC Trigger 4 on master compare 4 */
mbed_official 155:8435094ec241 2336 #define HRTIM_ADC4R_AD4MPER ((uint32_t)0x00000010) /*!< ADC Trigger 4 on master period */
mbed_official 155:8435094ec241 2337 #define HRTIM_ADC4R_AD4EEV6 ((uint32_t)0x00000020) /*!< ADC Trigger 4 on external event 6 */
mbed_official 155:8435094ec241 2338 #define HRTIM_ADC4R_AD4EEV7 ((uint32_t)0x00000040) /*!< ADC Trigger 4 on external event 7 */
mbed_official 155:8435094ec241 2339 #define HRTIM_ADC4R_AD4EEV8 ((uint32_t)0x00000080) /*!< ADC Trigger 4 on external event 8 */
mbed_official 155:8435094ec241 2340 #define HRTIM_ADC4R_AD4EEV9 ((uint32_t)0x00000100) /*!< ADC Trigger 4 on external event 9 */
mbed_official 155:8435094ec241 2341 #define HRTIM_ADC4R_AD4EEV10 ((uint32_t)0x00000200) /*!< ADC Trigger 4 on external event 10 */
mbed_official 155:8435094ec241 2342 #define HRTIM_ADC4R_AD4TAC2 ((uint32_t)0x00000400) /*!< ADC Trigger 4 on Timer A compare 2 */
mbed_official 155:8435094ec241 2343 #define HRTIM_ADC4R_AD4TAC3 ((uint32_t)0x00000800) /*!< ADC Trigger 4 on Timer A compare 3 */
mbed_official 155:8435094ec241 2344 #define HRTIM_ADC4R_AD4TAC4 ((uint32_t)0x00001000) /*!< ADC Trigger 4 on Timer A compare 4*/
mbed_official 155:8435094ec241 2345 #define HRTIM_ADC4R_AD4TAPER ((uint32_t)0x00002000) /*!< ADC Trigger 4 on Timer A period */
mbed_official 155:8435094ec241 2346 #define HRTIM_ADC4R_AD4TBC2 ((uint32_t)0x00004000) /*!< ADC Trigger 4 on Timer B compare 2 */
mbed_official 155:8435094ec241 2347 #define HRTIM_ADC4R_AD4TBC3 ((uint32_t)0x00008000) /*!< ADC Trigger 4 on Timer B compare 3 */
mbed_official 155:8435094ec241 2348 #define HRTIM_ADC4R_AD4TBC4 ((uint32_t)0x00010000) /*!< ADC Trigger 4 on Timer B compare 4 */
mbed_official 155:8435094ec241 2349 #define HRTIM_ADC4R_AD4TBPER ((uint32_t)0x00020000) /*!< ADC Trigger 4 on Timer B period */
mbed_official 155:8435094ec241 2350 #define HRTIM_ADC4R_AD4TCC2 ((uint32_t)0x00040000) /*!< ADC Trigger 4 on Timer C compare 2 */
mbed_official 155:8435094ec241 2351 #define HRTIM_ADC4R_AD4TCC3 ((uint32_t)0x00080000) /*!< ADC Trigger 4 on Timer C compare 3 */
mbed_official 155:8435094ec241 2352 #define HRTIM_ADC4R_AD4TCC4 ((uint32_t)0x00100000) /*!< ADC Trigger 4 on Timer C compare 4 */
mbed_official 155:8435094ec241 2353 #define HRTIM_ADC4R_AD4TCPER ((uint32_t)0x00200000) /*!< ADC Trigger 4 on Timer C period */
mbed_official 155:8435094ec241 2354 #define HRTIM_ADC4R_AD4TCRST ((uint32_t)0x00400000) /*!< ADC Trigger 4 on Timer C reset */
mbed_official 155:8435094ec241 2355 #define HRTIM_ADC4R_AD4TDC2 ((uint32_t)0x00800000) /*!< ADC Trigger 4 on Timer D compare 2 */
mbed_official 155:8435094ec241 2356 #define HRTIM_ADC4R_AD4TDC3 ((uint32_t)0x01000000) /*!< ADC Trigger 4 on Timer D compare 3 */
mbed_official 155:8435094ec241 2357 #define HRTIM_ADC4R_AD4TDC4 ((uint32_t)0x02000000) /*!< ADC Trigger 4 on Timer D compare 4*/
mbed_official 155:8435094ec241 2358 #define HRTIM_ADC4R_AD4TDPER ((uint32_t)0x04000000) /*!< ADC Trigger 4 on Timer D period */
mbed_official 155:8435094ec241 2359 #define HRTIM_ADC4R_AD4TDRST ((uint32_t)0x08000000) /*!< ADC Trigger 4 on Timer D reset */
mbed_official 155:8435094ec241 2360 #define HRTIM_ADC4R_AD4TEC2 ((uint32_t)0x10000000) /*!< ADC Trigger 4 on Timer E compare 2 */
mbed_official 155:8435094ec241 2361 #define HRTIM_ADC4R_AD4TEC3 ((uint32_t)0x20000000) /*!< ADC Trigger 4 on Timer E compare 3 */
mbed_official 155:8435094ec241 2362 #define HRTIM_ADC4R_AD4TEC4 ((uint32_t)0x40000000) /*!< ADC Trigger 4 on Timer E compare 4 */
mbed_official 155:8435094ec241 2363 #define HRTIM_ADC4R_AD4TERST ((uint32_t)0x80000000) /*!< ADC Trigger 4 on Timer E reset */
mbed_official 155:8435094ec241 2364
mbed_official 155:8435094ec241 2365 /******************* Bit definition for HRTIM_DLLCR register ****************/
mbed_official 155:8435094ec241 2366 #define HRTIM_DLLCR_CAL ((uint32_t)0x00000001) /*!< DLL calibration start */
mbed_official 155:8435094ec241 2367 #define HRTIM_DLLCR_CALEN ((uint32_t)0x00000002) /*!< DLL calibration enable */
mbed_official 155:8435094ec241 2368 #define HRTIM_DLLCR_CALRTE ((uint32_t)0x0000000C) /*!< DLL calibration rate */
mbed_official 155:8435094ec241 2369 #define HRTIM_DLLCR_CALRTE_0 ((uint32_t)0x00000004) /*!< DLL calibration rate bit 0 */
mbed_official 155:8435094ec241 2370 #define HRTIM_DLLCR_CALRTE_1 ((uint32_t)0x00000008) /*!< DLL calibration rate bit 1 */
mbed_official 155:8435094ec241 2371
mbed_official 155:8435094ec241 2372 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
mbed_official 155:8435094ec241 2373 #define HRTIM_FLTINR1_FLT1E ((uint32_t)0x00000001) /*!< Fault 1 enable */
mbed_official 155:8435094ec241 2374 #define HRTIM_FLTINR1_FLT1P ((uint32_t)0x00000002) /*!< Fault 1 polarity */
mbed_official 155:8435094ec241 2375 #define HRTIM_FLTINR1_FLT1SRC ((uint32_t)0x00000004) /*!< Fault 1 source */
mbed_official 155:8435094ec241 2376 #define HRTIM_FLTINR1_FLT1F ((uint32_t)0x00000078) /*!< Fault 1 filter */
mbed_official 155:8435094ec241 2377 #define HRTIM_FLTINR1_FLT1F_0 ((uint32_t)0x00000008) /*!< Fault 1 filter bit 0 */
mbed_official 155:8435094ec241 2378 #define HRTIM_FLTINR1_FLT1F_1 ((uint32_t)0x00000010) /*!< Fault 1 filter bit 1 */
mbed_official 155:8435094ec241 2379 #define HRTIM_FLTINR1_FLT1F_2 ((uint32_t)0x00000020) /*!< Fault 1 filter bit 2 */
mbed_official 155:8435094ec241 2380 #define HRTIM_FLTINR1_FLT1F_3 ((uint32_t)0x00000040) /*!< Fault 1 filter bit 3 */
mbed_official 155:8435094ec241 2381 #define HRTIM_FLTINR1_FLT1LCK ((uint32_t)0x00000080) /*!< Fault 1 lock */
mbed_official 155:8435094ec241 2382
mbed_official 155:8435094ec241 2383 #define HRTIM_FLTINR1_FLT2E ((uint32_t)0x00000100) /*!< Fault 2 enable */
mbed_official 155:8435094ec241 2384 #define HRTIM_FLTINR1_FLT2P ((uint32_t)0x00000200) /*!< Fault 2 polarity */
mbed_official 155:8435094ec241 2385 #define HRTIM_FLTINR1_FLT2SRC ((uint32_t)0x00000400) /*!< Fault 2 source */
mbed_official 155:8435094ec241 2386 #define HRTIM_FLTINR1_FLT2F ((uint32_t)0x00007800) /*!< Fault 2 filter */
mbed_official 155:8435094ec241 2387 #define HRTIM_FLTINR1_FLT2F_0 ((uint32_t)0x00000800) /*!< Fault 2 filter bit 0 */
mbed_official 155:8435094ec241 2388 #define HRTIM_FLTINR1_FLT2F_1 ((uint32_t)0x00001000) /*!< Fault 2 filter bit 1 */
mbed_official 155:8435094ec241 2389 #define HRTIM_FLTINR1_FLT2F_2 ((uint32_t)0x00002000) /*!< Fault 2 filter bit 2 */
mbed_official 155:8435094ec241 2390 #define HRTIM_FLTINR1_FLT2F_3 ((uint32_t)0x00004000) /*!< Fault 2 filter bit 3 */
mbed_official 155:8435094ec241 2391 #define HRTIM_FLTINR1_FLT2LCK ((uint32_t)0x00008000) /*!< Fault 2 lock */
mbed_official 155:8435094ec241 2392
mbed_official 155:8435094ec241 2393 #define HRTIM_FLTINR1_FLT3E ((uint32_t)0x00010000) /*!< Fault 3 enable */
mbed_official 155:8435094ec241 2394 #define HRTIM_FLTINR1_FLT3P ((uint32_t)0x00020000) /*!< Fault 3 polarity */
mbed_official 155:8435094ec241 2395 #define HRTIM_FLTINR1_FLT3SRC ((uint32_t)0x00040000) /*!< Fault 3 source */
mbed_official 155:8435094ec241 2396 #define HRTIM_FLTINR1_FLT3F ((uint32_t)0x00780000) /*!< Fault 3 filter */
mbed_official 155:8435094ec241 2397 #define HRTIM_FLTINR1_FLT3F_0 ((uint32_t)0x00080000) /*!< Fault 3 filter bit 0 */
mbed_official 155:8435094ec241 2398 #define HRTIM_FLTINR1_FLT3F_1 ((uint32_t)0x00100000) /*!< Fault 3 filter bit 1 */
mbed_official 155:8435094ec241 2399 #define HRTIM_FLTINR1_FLT3F_2 ((uint32_t)0x00200000) /*!< Fault 3 filter bit 2 */
mbed_official 155:8435094ec241 2400 #define HRTIM_FLTINR1_FLT3F_3 ((uint32_t)0x00400000) /*!< Fault 3 filter bit 3 */
mbed_official 155:8435094ec241 2401 #define HRTIM_FLTINR1_FLT3LCK ((uint32_t)0x00800000) /*!< Fault 3 lock */
mbed_official 155:8435094ec241 2402
mbed_official 155:8435094ec241 2403 #define HRTIM_FLTINR1_FLT4E ((uint32_t)0x01000000) /*!< Fault 4 enable */
mbed_official 155:8435094ec241 2404 #define HRTIM_FLTINR1_FLT4P ((uint32_t)0x02000000) /*!< Fault 4 polarity */
mbed_official 155:8435094ec241 2405 #define HRTIM_FLTINR1_FLT4SRC ((uint32_t)0x04000000) /*!< Fault 4 source */
mbed_official 155:8435094ec241 2406 #define HRTIM_FLTINR1_FLT4F ((uint32_t)0x78000000) /*!< Fault 4 filter */
mbed_official 155:8435094ec241 2407 #define HRTIM_FLTINR1_FLT4F_0 ((uint32_t)0x08000000) /*!< Fault 4 filter bit 0 */
mbed_official 155:8435094ec241 2408 #define HRTIM_FLTINR1_FLT4F_1 ((uint32_t)0x10000000) /*!< Fault 4 filter bit 1 */
mbed_official 155:8435094ec241 2409 #define HRTIM_FLTINR1_FLT4F_2 ((uint32_t)0x20000000) /*!< Fault 4 filter bit 2 */
mbed_official 155:8435094ec241 2410 #define HRTIM_FLTINR1_FLT4F_3 ((uint32_t)0x40000000) /*!< Fault 4 filter bit 3 */
mbed_official 155:8435094ec241 2411 #define HRTIM_FLTINR1_FLT4LCK ((uint32_t)0x80000000) /*!< Fault 4 lock */
mbed_official 155:8435094ec241 2412
mbed_official 155:8435094ec241 2413 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
mbed_official 155:8435094ec241 2414 #define HRTIM_FLTINR2_FLT5E ((uint32_t)0x00000001) /*!< Fault 5 enable */
mbed_official 155:8435094ec241 2415 #define HRTIM_FLTINR2_FLT5P ((uint32_t)0x00000002) /*!< Fault 5 polarity */
mbed_official 155:8435094ec241 2416 #define HRTIM_FLTINR2_FLT5SRC ((uint32_t)0x00000004) /*!< Fault 5 source */
mbed_official 155:8435094ec241 2417 #define HRTIM_FLTINR2_FLT5F ((uint32_t)0x00000078) /*!< Fault 5 filter */
mbed_official 155:8435094ec241 2418 #define HRTIM_FLTINR2_FLT5F_0 ((uint32_t)0x00000008) /*!< Fault 5 filter bit 0 */
mbed_official 155:8435094ec241 2419 #define HRTIM_FLTINR2_FLT5F_1 ((uint32_t)0x00000010) /*!< Fault 5 filter bit 1 */
mbed_official 155:8435094ec241 2420 #define HRTIM_FLTINR2_FLT5F_2 ((uint32_t)0x00000020) /*!< Fault 5 filter bit 2 */
mbed_official 155:8435094ec241 2421 #define HRTIM_FLTINR2_FLT5F_3 ((uint32_t)0x00000040) /*!< Fault 5 filter bit 3 */
mbed_official 155:8435094ec241 2422 #define HRTIM_FLTINR2_FLT5LCK ((uint32_t)0x00000080) /*!< Fault 5 lock */
mbed_official 155:8435094ec241 2423 #define HRTIM_FLTINR2_FLTSD ((uint32_t)0x03000000) /*!< Fault sampling clock division */
mbed_official 155:8435094ec241 2424 #define HRTIM_FLTINR2_FLTSD_0 ((uint32_t)0x01000000) /*!< Fault sampling clock division bit 0 */
mbed_official 155:8435094ec241 2425 #define HRTIM_FLTINR2_FLTSD_1 ((uint32_t)0x02000000) /*!< Fault sampling clock division bit 1 */
mbed_official 155:8435094ec241 2426
mbed_official 155:8435094ec241 2427 /******************* Bit definition for HRTIM_BDMUPR register ***************/
mbed_official 155:8435094ec241 2428 #define HRTIM_BDMUPR_MCR ((uint32_t)0x00000001) /*!< MCR register update enable */
mbed_official 155:8435094ec241 2429 #define HRTIM_BDMUPR_MICR ((uint32_t)0x00000002) /*!< MICR register update enable */
mbed_official 155:8435094ec241 2430 #define HRTIM_BDMUPR_MDIER ((uint32_t)0x00000004) /*!< MDIER register update enable */
mbed_official 155:8435094ec241 2431 #define HRTIM_BDMUPR_MCNT ((uint32_t)0x00000008) /*!< MCNT register update enable */
mbed_official 155:8435094ec241 2432 #define HRTIM_BDMUPR_MPER ((uint32_t)0x00000010) /*!< MPER register update enable */
mbed_official 155:8435094ec241 2433 #define HRTIM_BDMUPR_MREP ((uint32_t)0x00000020) /*!< MREP register update enable */
mbed_official 155:8435094ec241 2434 #define HRTIM_BDMUPR_MCMP1 ((uint32_t)0x00000040) /*!< MCMP1 register update enable */
mbed_official 155:8435094ec241 2435 #define HRTIM_BDMUPR_MCMP2 ((uint32_t)0x00000080) /*!< MCMP2 register update enable */
mbed_official 155:8435094ec241 2436 #define HRTIM_BDMUPR_MCMP3 ((uint32_t)0x00000100) /*!< MCMP3 register update enable */
mbed_official 155:8435094ec241 2437 #define HRTIM_BDMUPR_MCMP4 ((uint32_t)0x00000200) /*!< MPCMP4 register update enable */
mbed_official 155:8435094ec241 2438
mbed_official 155:8435094ec241 2439 /******************* Bit definition for HRTIM_BDTUPR register ***************/
mbed_official 155:8435094ec241 2440 #define HRTIM_BDTUPR_TIMCR ((uint32_t)0x00000001) /*!< TIMCR register update enable */
mbed_official 155:8435094ec241 2441 #define HRTIM_BDTUPR_TIMICR ((uint32_t)0x00000002) /*!< TIMICR register update enable */
mbed_official 155:8435094ec241 2442 #define HRTIM_BDTUPR_TIMDIER ((uint32_t)0x00000004) /*!< TIMDIER register update enable */
mbed_official 155:8435094ec241 2443 #define HRTIM_BDTUPR_TIMCNT ((uint32_t)0x00000008) /*!< TIMCNT register update enable */
mbed_official 155:8435094ec241 2444 #define HRTIM_BDTUPR_TIMPER ((uint32_t)0x00000010) /*!< TIMPER register update enable */
mbed_official 155:8435094ec241 2445 #define HRTIM_BDTUPR_TIMREP ((uint32_t)0x00000020) /*!< TIMREP register update enable */
mbed_official 155:8435094ec241 2446 #define HRTIM_BDTUPR_TIMCMP1 ((uint32_t)0x00000040) /*!< TIMCMP1 register update enable */
mbed_official 155:8435094ec241 2447 #define HRTIM_BDTUPR_TIMCMP2 ((uint32_t)0x00000080) /*!< TIMCMP2 register update enable */
mbed_official 155:8435094ec241 2448 #define HRTIM_BDTUPR_TIMCMP3 ((uint32_t)0x00000100) /*!< TIMCMP3 register update enable */
mbed_official 155:8435094ec241 2449 #define HRTIM_BDTUPR_TIMCMP4 ((uint32_t)0x00000200) /*!< TIMCMP4 register update enable */
mbed_official 155:8435094ec241 2450 #define HRTIM_BDTUPR_TIMDTR ((uint32_t)0x00000400) /*!< TIMDTR register update enable */
mbed_official 155:8435094ec241 2451 #define HRTIM_BDTUPR_TIMSET1R ((uint32_t)0x00000800) /*!< TIMSET1R register update enable */
mbed_official 155:8435094ec241 2452 #define HRTIM_BDTUPR_TIMRST1R ((uint32_t)0x00001000) /*!< TIMRST1R register update enable */
mbed_official 155:8435094ec241 2453 #define HRTIM_BDTUPR_TIMSET2R ((uint32_t)0x00002000) /*!< TIMSET2R register update enable */
mbed_official 155:8435094ec241 2454 #define HRTIM_BDTUPR_TIMRST2R ((uint32_t)0x00004000) /*!< TIMRST2R register update enable */
mbed_official 155:8435094ec241 2455 #define HRTIM_BDTUPR_TIMEEFR1 ((uint32_t)0x00008000) /*!< TIMEEFR1 register update enable */
mbed_official 155:8435094ec241 2456 #define HRTIM_BDTUPR_TIMEEFR2 ((uint32_t)0x00010000) /*!< TIMEEFR2 register update enable */
mbed_official 155:8435094ec241 2457 #define HRTIM_BDTUPR_TIMRSTR ((uint32_t)0x00020000) /*!< TIMRSTR register update enable */
mbed_official 155:8435094ec241 2458 #define HRTIM_BDTUPR_TIMCHPR ((uint32_t)0x00040000) /*!< TIMCHPR register update enable */
mbed_official 155:8435094ec241 2459 #define HRTIM_BDTUPR_TIMOUTR ((uint32_t)0x00080000) /*!< TIMOUTR register update enable */
mbed_official 155:8435094ec241 2460 #define HRTIM_BDTUPR_TIMFLTR ((uint32_t)0x00100000) /*!< TIMFLTR register update enable */
mbed_official 155:8435094ec241 2461
mbed_official 155:8435094ec241 2462 /******************* Bit definition for HRTIM_BDMADR register ***************/
mbed_official 155:8435094ec241 2463 #define HRTIM_BDMADR_BDMADR ((uint32_t)0xFFFFFFFF) /*!< Burst DMA Data register */
mbed_official 155:8435094ec241 2464
mbed_official 155:8435094ec241 2465 /******************************************************************************/
mbed_official 155:8435094ec241 2466 /* */
mbed_official 155:8435094ec241 2467 /* Analog to Digital Converter SAR (ADC) */
mbed_official 155:8435094ec241 2468 /* */
mbed_official 155:8435094ec241 2469 /******************************************************************************/
mbed_official 155:8435094ec241 2470 /******************** Bit definition for ADC_ISR register ********************/
mbed_official 155:8435094ec241 2471 #define ADC_ISR_ADRD ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) flag */
mbed_official 155:8435094ec241 2472 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling flag */
mbed_official 155:8435094ec241 2473 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion flag */
mbed_official 155:8435094ec241 2474 #define ADC_ISR_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions flag */
mbed_official 155:8435094ec241 2475 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< ADC overrun flag */
mbed_official 155:8435094ec241 2476 #define ADC_ISR_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion flag */
mbed_official 155:8435094ec241 2477 #define ADC_ISR_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions flag */
mbed_official 155:8435094ec241 2478 #define ADC_ISR_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 flag */
mbed_official 155:8435094ec241 2479 #define ADC_ISR_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 flag */
mbed_official 155:8435094ec241 2480 #define ADC_ISR_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 flag */
mbed_official 155:8435094ec241 2481 #define ADC_ISR_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow flag */
mbed_official 155:8435094ec241 2482
mbed_official 155:8435094ec241 2483 /******************** Bit definition for ADC_IER register ********************/
mbed_official 155:8435094ec241 2484 #define ADC_IER_RDY ((uint32_t)0x00000001) /*!< ADC Ready (ADRDY) interrupt source */
mbed_official 155:8435094ec241 2485 #define ADC_IER_EOSMP ((uint32_t)0x00000002) /*!< ADC End of Sampling interrupt source */
mbed_official 155:8435094ec241 2486 #define ADC_IER_EOC ((uint32_t)0x00000004) /*!< ADC End of Regular Conversion interrupt source */
mbed_official 155:8435094ec241 2487 #define ADC_IER_EOS ((uint32_t)0x00000008) /*!< ADC End of Regular sequence of Conversions interrupt source */
mbed_official 155:8435094ec241 2488 #define ADC_IER_OVR ((uint32_t)0x00000010) /*!< ADC overrun interrupt source */
mbed_official 155:8435094ec241 2489 #define ADC_IER_JEOC ((uint32_t)0x00000020) /*!< ADC End of Injected Conversion interrupt source */
mbed_official 155:8435094ec241 2490 #define ADC_IER_JEOS ((uint32_t)0x00000040) /*!< ADC End of Injected sequence of Conversions interrupt source */
mbed_official 155:8435094ec241 2491 #define ADC_IER_AWD1 ((uint32_t)0x00000080) /*!< ADC Analog watchdog 1 interrupt source */
mbed_official 155:8435094ec241 2492 #define ADC_IER_AWD2 ((uint32_t)0x00000100) /*!< ADC Analog watchdog 2 interrupt source */
mbed_official 155:8435094ec241 2493 #define ADC_IER_AWD3 ((uint32_t)0x00000200) /*!< ADC Analog watchdog 3 interrupt source */
mbed_official 155:8435094ec241 2494 #define ADC_IER_JQOVF ((uint32_t)0x00000400) /*!< ADC Injected Context Queue Overflow interrupt source */
mbed_official 155:8435094ec241 2495
mbed_official 155:8435094ec241 2496 /******************** Bit definition for ADC_CR register ********************/
mbed_official 155:8435094ec241 2497 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC Enable control */
mbed_official 155:8435094ec241 2498 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC Disable command */
mbed_official 155:8435094ec241 2499 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC Start of Regular conversion */
mbed_official 155:8435094ec241 2500 #define ADC_CR_JADSTART ((uint32_t)0x00000008) /*!< ADC Start of injected conversion */
mbed_official 155:8435094ec241 2501 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC Stop of Regular conversion */
mbed_official 155:8435094ec241 2502 #define ADC_CR_JADSTP ((uint32_t)0x00000020) /*!< ADC Stop of injected conversion */
mbed_official 155:8435094ec241 2503 #define ADC_CR_ADVREGEN ((uint32_t)0x30000000) /*!< ADC Voltage regulator Enable */
mbed_official 155:8435094ec241 2504 #define ADC_CR_ADVREGEN_0 ((uint32_t)0x10000000) /*!< ADC ADVREGEN bit 0 */
mbed_official 155:8435094ec241 2505 #define ADC_CR_ADVREGEN_1 ((uint32_t)0x20000000) /*!< ADC ADVREGEN bit 1 */
mbed_official 155:8435094ec241 2506 #define ADC_CR_ADCALDIF ((uint32_t)0x40000000) /*!< ADC Differential Mode for calibration */
mbed_official 155:8435094ec241 2507 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC Calibration */
mbed_official 155:8435094ec241 2508
mbed_official 155:8435094ec241 2509 /******************** Bit definition for ADC_CFGR register ********************/
mbed_official 155:8435094ec241 2510 #define ADC_CFGR_DMAEN ((uint32_t)0x00000001) /*!< ADC DMA Enable */
mbed_official 155:8435094ec241 2511 #define ADC_CFGR_DMACFG ((uint32_t)0x00000002) /*!< ADC DMA configuration */
mbed_official 155:8435094ec241 2512
mbed_official 155:8435094ec241 2513 #define ADC_CFGR_RES ((uint32_t)0x00000018) /*!< ADC Data resolution */
mbed_official 155:8435094ec241 2514 #define ADC_CFGR_RES_0 ((uint32_t)0x00000008) /*!< ADC RES bit 0 */
mbed_official 155:8435094ec241 2515 #define ADC_CFGR_RES_1 ((uint32_t)0x00000010) /*!< ADC RES bit 1 */
mbed_official 155:8435094ec241 2516
mbed_official 155:8435094ec241 2517 #define ADC_CFGR_ALIGN ((uint32_t)0x00000020) /*!< ADC Data Alignment */
mbed_official 155:8435094ec241 2518
mbed_official 155:8435094ec241 2519 #define ADC_CFGR_EXTSEL ((uint32_t)0x000003C0) /*!< ADC External trigger selection for regular group */
mbed_official 155:8435094ec241 2520 #define ADC_CFGR_EXTSEL_0 ((uint32_t)0x00000040) /*!< ADC EXTSEL bit 0 */
mbed_official 155:8435094ec241 2521 #define ADC_CFGR_EXTSEL_1 ((uint32_t)0x00000080) /*!< ADC EXTSEL bit 1 */
mbed_official 155:8435094ec241 2522 #define ADC_CFGR_EXTSEL_2 ((uint32_t)0x00000100) /*!< ADC EXTSEL bit 2 */
mbed_official 155:8435094ec241 2523 #define ADC_CFGR_EXTSEL_3 ((uint32_t)0x00000200) /*!< ADC EXTSEL bit 3 */
mbed_official 155:8435094ec241 2524
mbed_official 155:8435094ec241 2525 #define ADC_CFGR_EXTEN ((uint32_t)0x00000C00) /*!< ADC External trigger enable and polarity selection for regular channels */
mbed_official 155:8435094ec241 2526 #define ADC_CFGR_EXTEN_0 ((uint32_t)0x00000400) /*!< ADC EXTEN bit 0 */
mbed_official 155:8435094ec241 2527 #define ADC_CFGR_EXTEN_1 ((uint32_t)0x00000800) /*!< ADC EXTEN bit 1 */
mbed_official 155:8435094ec241 2528
mbed_official 155:8435094ec241 2529 #define ADC_CFGR_OVRMOD ((uint32_t)0x00001000) /*!< ADC overrun mode */
mbed_official 155:8435094ec241 2530 #define ADC_CFGR_CONT ((uint32_t)0x00002000) /*!< ADC Single/continuous conversion mode for regular conversion */
mbed_official 155:8435094ec241 2531 #define ADC_CFGR_AUTDLY ((uint32_t)0x00004000) /*!< ADC Delayed conversion mode */
mbed_official 155:8435094ec241 2532 #define ADC_CFGR_DISCEN ((uint32_t)0x00010000) /*!< ADC Discontinuous mode for regular channels */
mbed_official 155:8435094ec241 2533
mbed_official 155:8435094ec241 2534 #define ADC_CFGR_DISCNUM ((uint32_t)0x000E0000) /*!< ADC Discontinuous mode channel count */
mbed_official 155:8435094ec241 2535 #define ADC_CFGR_DISCNUM_0 ((uint32_t)0x00020000) /*!< ADC DISCNUM bit 0 */
mbed_official 155:8435094ec241 2536 #define ADC_CFGR_DISCNUM_1 ((uint32_t)0x00040000) /*!< ADC DISCNUM bit 1 */
mbed_official 155:8435094ec241 2537 #define ADC_CFGR_DISCNUM_2 ((uint32_t)0x00080000) /*!< ADC DISCNUM bit 2 */
mbed_official 155:8435094ec241 2538
mbed_official 155:8435094ec241 2539 #define ADC_CFGR_JDISCEN ((uint32_t)0x00100000) /*!< ADC Discontinuous mode on injected channels */
mbed_official 155:8435094ec241 2540 #define ADC_CFGR_JQM ((uint32_t)0x00200000) /*!< ADC JSQR Queue mode */
mbed_official 155:8435094ec241 2541 #define ADC_CFGR_AWD1SGL ((uint32_t)0x00400000) /*!< Enable the watchdog 1 on a single channel or on all channels */
mbed_official 155:8435094ec241 2542 #define ADC_CFGR_AWD1EN ((uint32_t)0x00800000) /*!< ADC Analog watchdog 1 enable on regular Channels */
mbed_official 155:8435094ec241 2543 #define ADC_CFGR_JAWD1EN ((uint32_t)0x01000000) /*!< ADC Analog watchdog 1 enable on injected Channels */
mbed_official 155:8435094ec241 2544 #define ADC_CFGR_JAUTO ((uint32_t)0x02000000) /*!< ADC Automatic injected group conversion */
mbed_official 155:8435094ec241 2545
mbed_official 155:8435094ec241 2546 #define ADC_CFGR_AWD1CH ((uint32_t)0x7C000000) /*!< ADC Analog watchdog 1 Channel selection */
mbed_official 155:8435094ec241 2547 #define ADC_CFGR_AWD1CH_0 ((uint32_t)0x04000000) /*!< ADC AWD1CH bit 0 */
mbed_official 155:8435094ec241 2548 #define ADC_CFGR_AWD1CH_1 ((uint32_t)0x08000000) /*!< ADC AWD1CH bit 1 */
mbed_official 155:8435094ec241 2549 #define ADC_CFGR_AWD1CH_2 ((uint32_t)0x10000000) /*!< ADC AWD1CH bit 2 */
mbed_official 155:8435094ec241 2550 #define ADC_CFGR_AWD1CH_3 ((uint32_t)0x20000000) /*!< ADC AWD1CH bit 3 */
mbed_official 155:8435094ec241 2551 #define ADC_CFGR_AWD1CH_4 ((uint32_t)0x40000000) /*!< ADC AWD1CH bit 4 */
mbed_official 155:8435094ec241 2552
mbed_official 155:8435094ec241 2553 /******************** Bit definition for ADC_SMPR1 register ********************/
mbed_official 155:8435094ec241 2554 #define ADC_SMPR1_SMP0 ((uint32_t)0x00000007) /*!< ADC Channel 0 Sampling time selection */
mbed_official 155:8435094ec241 2555 #define ADC_SMPR1_SMP0_0 ((uint32_t)0x00000001) /*!< ADC SMP0 bit 0 */
mbed_official 155:8435094ec241 2556 #define ADC_SMPR1_SMP0_1 ((uint32_t)0x00000002) /*!< ADC SMP0 bit 1 */
mbed_official 155:8435094ec241 2557 #define ADC_SMPR1_SMP0_2 ((uint32_t)0x00000004) /*!< ADC SMP0 bit 2 */
mbed_official 155:8435094ec241 2558
mbed_official 155:8435094ec241 2559 #define ADC_SMPR1_SMP1 ((uint32_t)0x00000038) /*!< ADC Channel 1 Sampling time selection */
mbed_official 155:8435094ec241 2560 #define ADC_SMPR1_SMP1_0 ((uint32_t)0x00000008) /*!< ADC SMP1 bit 0 */
mbed_official 155:8435094ec241 2561 #define ADC_SMPR1_SMP1_1 ((uint32_t)0x00000010) /*!< ADC SMP1 bit 1 */
mbed_official 155:8435094ec241 2562 #define ADC_SMPR1_SMP1_2 ((uint32_t)0x00000020) /*!< ADC SMP1 bit 2 */
mbed_official 155:8435094ec241 2563
mbed_official 155:8435094ec241 2564 #define ADC_SMPR1_SMP2 ((uint32_t)0x000001C0) /*!< ADC Channel 2 Sampling time selection */
mbed_official 155:8435094ec241 2565 #define ADC_SMPR1_SMP2_0 ((uint32_t)0x00000040) /*!< ADC SMP2 bit 0 */
mbed_official 155:8435094ec241 2566 #define ADC_SMPR1_SMP2_1 ((uint32_t)0x00000080) /*!< ADC SMP2 bit 1 */
mbed_official 155:8435094ec241 2567 #define ADC_SMPR1_SMP2_2 ((uint32_t)0x00000100) /*!< ADC SMP2 bit 2 */
mbed_official 155:8435094ec241 2568
mbed_official 155:8435094ec241 2569 #define ADC_SMPR1_SMP3 ((uint32_t)0x00000E00) /*!< ADC Channel 3 Sampling time selection */
mbed_official 155:8435094ec241 2570 #define ADC_SMPR1_SMP3_0 ((uint32_t)0x00000200) /*!< ADC SMP3 bit 0 */
mbed_official 155:8435094ec241 2571 #define ADC_SMPR1_SMP3_1 ((uint32_t)0x00000400) /*!< ADC SMP3 bit 1 */
mbed_official 155:8435094ec241 2572 #define ADC_SMPR1_SMP3_2 ((uint32_t)0x00000800) /*!< ADC SMP3 bit 2 */
mbed_official 155:8435094ec241 2573
mbed_official 155:8435094ec241 2574 #define ADC_SMPR1_SMP4 ((uint32_t)0x00007000) /*!< ADC Channel 4 Sampling time selection */
mbed_official 155:8435094ec241 2575 #define ADC_SMPR1_SMP4_0 ((uint32_t)0x00001000) /*!< ADC SMP4 bit 0 */
mbed_official 155:8435094ec241 2576 #define ADC_SMPR1_SMP4_1 ((uint32_t)0x00002000) /*!< ADC SMP4 bit 1 */
mbed_official 155:8435094ec241 2577 #define ADC_SMPR1_SMP4_2 ((uint32_t)0x00004000) /*!< ADC SMP4 bit 2 */
mbed_official 155:8435094ec241 2578
mbed_official 155:8435094ec241 2579 #define ADC_SMPR1_SMP5 ((uint32_t)0x00038000) /*!< ADC Channel 5 Sampling time selection */
mbed_official 155:8435094ec241 2580 #define ADC_SMPR1_SMP5_0 ((uint32_t)0x00008000) /*!< ADC SMP5 bit 0 */
mbed_official 155:8435094ec241 2581 #define ADC_SMPR1_SMP5_1 ((uint32_t)0x00010000) /*!< ADC SMP5 bit 1 */
mbed_official 155:8435094ec241 2582 #define ADC_SMPR1_SMP5_2 ((uint32_t)0x00020000) /*!< ADC SMP5 bit 2 */
mbed_official 155:8435094ec241 2583
mbed_official 155:8435094ec241 2584 #define ADC_SMPR1_SMP6 ((uint32_t)0x001C0000) /*!< ADC Channel 6 Sampling time selection */
mbed_official 155:8435094ec241 2585 #define ADC_SMPR1_SMP6_0 ((uint32_t)0x00040000) /*!< ADC SMP6 bit 0 */
mbed_official 155:8435094ec241 2586 #define ADC_SMPR1_SMP6_1 ((uint32_t)0x00080000) /*!< ADC SMP6 bit 1 */
mbed_official 155:8435094ec241 2587 #define ADC_SMPR1_SMP6_2 ((uint32_t)0x00100000) /*!< ADC SMP6 bit 2 */
mbed_official 155:8435094ec241 2588
mbed_official 155:8435094ec241 2589 #define ADC_SMPR1_SMP7 ((uint32_t)0x00E00000) /*!< ADC Channel 7 Sampling time selection */
mbed_official 155:8435094ec241 2590 #define ADC_SMPR1_SMP7_0 ((uint32_t)0x00200000) /*!< ADC SMP7 bit 0 */
mbed_official 155:8435094ec241 2591 #define ADC_SMPR1_SMP7_1 ((uint32_t)0x00400000) /*!< ADC SMP7 bit 1 */
mbed_official 155:8435094ec241 2592 #define ADC_SMPR1_SMP7_2 ((uint32_t)0x00800000) /*!< ADC SMP7 bit 2 */
mbed_official 155:8435094ec241 2593
mbed_official 155:8435094ec241 2594 #define ADC_SMPR1_SMP8 ((uint32_t)0x07000000) /*!< ADC Channel 8 Sampling time selection */
mbed_official 155:8435094ec241 2595 #define ADC_SMPR1_SMP8_0 ((uint32_t)0x01000000) /*!< ADC SMP8 bit 0 */
mbed_official 155:8435094ec241 2596 #define ADC_SMPR1_SMP8_1 ((uint32_t)0x02000000) /*!< ADC SMP8 bit 1 */
mbed_official 155:8435094ec241 2597 #define ADC_SMPR1_SMP8_2 ((uint32_t)0x04000000) /*!< ADC SMP8 bit 2 */
mbed_official 155:8435094ec241 2598
mbed_official 155:8435094ec241 2599 #define ADC_SMPR1_SMP9 ((uint32_t)0x38000000) /*!< ADC Channel 9 Sampling time selection */
mbed_official 155:8435094ec241 2600 #define ADC_SMPR1_SMP9_0 ((uint32_t)0x08000000) /*!< ADC SMP9 bit 0 */
mbed_official 155:8435094ec241 2601 #define ADC_SMPR1_SMP9_1 ((uint32_t)0x10000000) /*!< ADC SMP9 bit 1 */
mbed_official 155:8435094ec241 2602 #define ADC_SMPR1_SMP9_2 ((uint32_t)0x20000000) /*!< ADC SMP9 bit 2 */
mbed_official 155:8435094ec241 2603
mbed_official 155:8435094ec241 2604 /******************** Bit definition for ADC_SMPR2 register ********************/
mbed_official 155:8435094ec241 2605 #define ADC_SMPR2_SMP10 ((uint32_t)0x00000007) /*!< ADC Channel 10 Sampling time selection */
mbed_official 155:8435094ec241 2606 #define ADC_SMPR2_SMP10_0 ((uint32_t)0x00000001) /*!< ADC SMP10 bit 0 */
mbed_official 155:8435094ec241 2607 #define ADC_SMPR2_SMP10_1 ((uint32_t)0x00000002) /*!< ADC SMP10 bit 1 */
mbed_official 155:8435094ec241 2608 #define ADC_SMPR2_SMP10_2 ((uint32_t)0x00000004) /*!< ADC SMP10 bit 2 */
mbed_official 155:8435094ec241 2609
mbed_official 155:8435094ec241 2610 #define ADC_SMPR2_SMP11 ((uint32_t)0x00000038) /*!< ADC Channel 11 Sampling time selection */
mbed_official 155:8435094ec241 2611 #define ADC_SMPR2_SMP11_0 ((uint32_t)0x00000008) /*!< ADC SMP11 bit 0 */
mbed_official 155:8435094ec241 2612 #define ADC_SMPR2_SMP11_1 ((uint32_t)0x00000010) /*!< ADC SMP11 bit 1 */
mbed_official 155:8435094ec241 2613 #define ADC_SMPR2_SMP11_2 ((uint32_t)0x00000020) /*!< ADC SMP11 bit 2 */
mbed_official 155:8435094ec241 2614
mbed_official 155:8435094ec241 2615 #define ADC_SMPR2_SMP12 ((uint32_t)0x000001C0) /*!< ADC Channel 12 Sampling time selection */
mbed_official 155:8435094ec241 2616 #define ADC_SMPR2_SMP12_0 ((uint32_t)0x00000040) /*!< ADC SMP12 bit 0 */
mbed_official 155:8435094ec241 2617 #define ADC_SMPR2_SMP12_1 ((uint32_t)0x00000080) /*!< ADC SMP12 bit 1 */
mbed_official 155:8435094ec241 2618 #define ADC_SMPR2_SMP12_2 ((uint32_t)0x00000100) /*!< ADC SMP12 bit 2 */
mbed_official 155:8435094ec241 2619
mbed_official 155:8435094ec241 2620 #define ADC_SMPR2_SMP13 ((uint32_t)0x00000E00) /*!< ADC Channel 13 Sampling time selection */
mbed_official 155:8435094ec241 2621 #define ADC_SMPR2_SMP13_0 ((uint32_t)0x00000200) /*!< ADC SMP13 bit 0 */
mbed_official 155:8435094ec241 2622 #define ADC_SMPR2_SMP13_1 ((uint32_t)0x00000400) /*!< ADC SMP13 bit 1 */
mbed_official 155:8435094ec241 2623 #define ADC_SMPR2_SMP13_2 ((uint32_t)0x00000800) /*!< ADC SMP13 bit 2 */
mbed_official 155:8435094ec241 2624
mbed_official 155:8435094ec241 2625 #define ADC_SMPR2_SMP14 ((uint32_t)0x00007000) /*!< ADC Channel 14 Sampling time selection */
mbed_official 155:8435094ec241 2626 #define ADC_SMPR2_SMP14_0 ((uint32_t)0x00001000) /*!< ADC SMP14 bit 0 */
mbed_official 155:8435094ec241 2627 #define ADC_SMPR2_SMP14_1 ((uint32_t)0x00002000) /*!< ADC SMP14 bit 1 */
mbed_official 155:8435094ec241 2628 #define ADC_SMPR2_SMP14_2 ((uint32_t)0x00004000) /*!< ADC SMP14 bit 2 */
mbed_official 155:8435094ec241 2629
mbed_official 155:8435094ec241 2630 #define ADC_SMPR2_SMP15 ((uint32_t)0x00038000) /*!< ADC Channel 15 Sampling time selection */
mbed_official 155:8435094ec241 2631 #define ADC_SMPR2_SMP15_0 ((uint32_t)0x00008000) /*!< ADC SMP15 bit 0 */
mbed_official 155:8435094ec241 2632 #define ADC_SMPR2_SMP15_1 ((uint32_t)0x00010000) /*!< ADC SMP15 bit 1 */
mbed_official 155:8435094ec241 2633 #define ADC_SMPR2_SMP15_2 ((uint32_t)0x00020000) /*!< ADC SMP15 bit 2 */
mbed_official 155:8435094ec241 2634
mbed_official 155:8435094ec241 2635 #define ADC_SMPR2_SMP16 ((uint32_t)0x001C0000) /*!< ADC Channel 16 Sampling time selection */
mbed_official 155:8435094ec241 2636 #define ADC_SMPR2_SMP16_0 ((uint32_t)0x00040000) /*!< ADC SMP16 bit 0 */
mbed_official 155:8435094ec241 2637 #define ADC_SMPR2_SMP16_1 ((uint32_t)0x00080000) /*!< ADC SMP16 bit 1 */
mbed_official 155:8435094ec241 2638 #define ADC_SMPR2_SMP16_2 ((uint32_t)0x00100000) /*!< ADC SMP16 bit 2 */
mbed_official 155:8435094ec241 2639
mbed_official 155:8435094ec241 2640 #define ADC_SMPR2_SMP17 ((uint32_t)0x00E00000) /*!< ADC Channel 17 Sampling time selection */
mbed_official 155:8435094ec241 2641 #define ADC_SMPR2_SMP17_0 ((uint32_t)0x00200000) /*!< ADC SMP17 bit 0 */
mbed_official 155:8435094ec241 2642 #define ADC_SMPR2_SMP17_1 ((uint32_t)0x00400000) /*!< ADC SMP17 bit 1 */
mbed_official 155:8435094ec241 2643 #define ADC_SMPR2_SMP17_2 ((uint32_t)0x00800000) /*!< ADC SMP17 bit 2 */
mbed_official 155:8435094ec241 2644
mbed_official 155:8435094ec241 2645 #define ADC_SMPR2_SMP18 ((uint32_t)0x07000000) /*!< ADC Channel 18 Sampling time selection */
mbed_official 155:8435094ec241 2646 #define ADC_SMPR2_SMP18_0 ((uint32_t)0x01000000) /*!< ADC SMP18 bit 0 */
mbed_official 155:8435094ec241 2647 #define ADC_SMPR2_SMP18_1 ((uint32_t)0x02000000) /*!< ADC SMP18 bit 1 */
mbed_official 155:8435094ec241 2648 #define ADC_SMPR2_SMP18_2 ((uint32_t)0x04000000) /*!< ADC SMP18 bit 2 */
mbed_official 155:8435094ec241 2649
mbed_official 155:8435094ec241 2650 /******************** Bit definition for ADC_TR1 register ********************/
mbed_official 155:8435094ec241 2651 #define ADC_TR1_LT1 ((uint32_t)0x00000FFF) /*!< ADC Analog watchdog 1 lower threshold */
mbed_official 155:8435094ec241 2652 #define ADC_TR1_LT1_0 ((uint32_t)0x00000001) /*!< ADC LT1 bit 0 */
mbed_official 155:8435094ec241 2653 #define ADC_TR1_LT1_1 ((uint32_t)0x00000002) /*!< ADC LT1 bit 1 */
mbed_official 155:8435094ec241 2654 #define ADC_TR1_LT1_2 ((uint32_t)0x00000004) /*!< ADC LT1 bit 2 */
mbed_official 155:8435094ec241 2655 #define ADC_TR1_LT1_3 ((uint32_t)0x00000008) /*!< ADC LT1 bit 3 */
mbed_official 155:8435094ec241 2656 #define ADC_TR1_LT1_4 ((uint32_t)0x00000010) /*!< ADC LT1 bit 4 */
mbed_official 155:8435094ec241 2657 #define ADC_TR1_LT1_5 ((uint32_t)0x00000020) /*!< ADC LT1 bit 5 */
mbed_official 155:8435094ec241 2658 #define ADC_TR1_LT1_6 ((uint32_t)0x00000040) /*!< ADC LT1 bit 6 */
mbed_official 155:8435094ec241 2659 #define ADC_TR1_LT1_7 ((uint32_t)0x00000080) /*!< ADC LT1 bit 7 */
mbed_official 155:8435094ec241 2660 #define ADC_TR1_LT1_8 ((uint32_t)0x00000100) /*!< ADC LT1 bit 8 */
mbed_official 155:8435094ec241 2661 #define ADC_TR1_LT1_9 ((uint32_t)0x00000200) /*!< ADC LT1 bit 9 */
mbed_official 155:8435094ec241 2662 #define ADC_TR1_LT1_10 ((uint32_t)0x00000400) /*!< ADC LT1 bit 10 */
mbed_official 155:8435094ec241 2663 #define ADC_TR1_LT1_11 ((uint32_t)0x00000800) /*!< ADC LT1 bit 11 */
mbed_official 155:8435094ec241 2664
mbed_official 155:8435094ec241 2665 #define ADC_TR1_HT1 ((uint32_t)0x0FFF0000) /*!< ADC Analog watchdog 1 higher threshold */
mbed_official 155:8435094ec241 2666 #define ADC_TR1_HT1_0 ((uint32_t)0x00010000) /*!< ADC HT1 bit 0 */
mbed_official 155:8435094ec241 2667 #define ADC_TR1_HT1_1 ((uint32_t)0x00020000) /*!< ADC HT1 bit 1 */
mbed_official 155:8435094ec241 2668 #define ADC_TR1_HT1_2 ((uint32_t)0x00040000) /*!< ADC HT1 bit 2 */
mbed_official 155:8435094ec241 2669 #define ADC_TR1_HT1_3 ((uint32_t)0x00080000) /*!< ADC HT1 bit 3 */
mbed_official 155:8435094ec241 2670 #define ADC_TR1_HT1_4 ((uint32_t)0x00100000) /*!< ADC HT1 bit 4 */
mbed_official 155:8435094ec241 2671 #define ADC_TR1_HT1_5 ((uint32_t)0x00200000) /*!< ADC HT1 bit 5 */
mbed_official 155:8435094ec241 2672 #define ADC_TR1_HT1_6 ((uint32_t)0x00400000) /*!< ADC HT1 bit 6 */
mbed_official 155:8435094ec241 2673 #define ADC_TR1_HT1_7 ((uint32_t)0x00800000) /*!< ADC HT1 bit 7 */
mbed_official 155:8435094ec241 2674 #define ADC_TR1_HT1_8 ((uint32_t)0x01000000) /*!< ADC HT1 bit 8 */
mbed_official 155:8435094ec241 2675 #define ADC_TR1_HT1_9 ((uint32_t)0x02000000) /*!< ADC HT1 bit 9 */
mbed_official 155:8435094ec241 2676 #define ADC_TR1_HT1_10 ((uint32_t)0x04000000) /*!< ADC HT1 bit 10 */
mbed_official 155:8435094ec241 2677 #define ADC_TR1_HT1_11 ((uint32_t)0x08000000) /*!< ADC HT1 bit 11 */
mbed_official 155:8435094ec241 2678
mbed_official 155:8435094ec241 2679 /******************** Bit definition for ADC_TR2 register ********************/
mbed_official 155:8435094ec241 2680 #define ADC_TR2_LT2 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 2 lower threshold */
mbed_official 155:8435094ec241 2681 #define ADC_TR2_LT2_0 ((uint32_t)0x00000001) /*!< ADC LT2 bit 0 */
mbed_official 155:8435094ec241 2682 #define ADC_TR2_LT2_1 ((uint32_t)0x00000002) /*!< ADC LT2 bit 1 */
mbed_official 155:8435094ec241 2683 #define ADC_TR2_LT2_2 ((uint32_t)0x00000004) /*!< ADC LT2 bit 2 */
mbed_official 155:8435094ec241 2684 #define ADC_TR2_LT2_3 ((uint32_t)0x00000008) /*!< ADC LT2 bit 3 */
mbed_official 155:8435094ec241 2685 #define ADC_TR2_LT2_4 ((uint32_t)0x00000010) /*!< ADC LT2 bit 4 */
mbed_official 155:8435094ec241 2686 #define ADC_TR2_LT2_5 ((uint32_t)0x00000020) /*!< ADC LT2 bit 5 */
mbed_official 155:8435094ec241 2687 #define ADC_TR2_LT2_6 ((uint32_t)0x00000040) /*!< ADC LT2 bit 6 */
mbed_official 155:8435094ec241 2688 #define ADC_TR2_LT2_7 ((uint32_t)0x00000080) /*!< ADC LT2 bit 7 */
mbed_official 155:8435094ec241 2689
mbed_official 155:8435094ec241 2690 #define ADC_TR2_HT2 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 2 higher threshold */
mbed_official 155:8435094ec241 2691 #define ADC_TR2_HT2_0 ((uint32_t)0x00010000) /*!< ADC HT2 bit 0 */
mbed_official 155:8435094ec241 2692 #define ADC_TR2_HT2_1 ((uint32_t)0x00020000) /*!< ADC HT2 bit 1 */
mbed_official 155:8435094ec241 2693 #define ADC_TR2_HT2_2 ((uint32_t)0x00040000) /*!< ADC HT2 bit 2 */
mbed_official 155:8435094ec241 2694 #define ADC_TR2_HT2_3 ((uint32_t)0x00080000) /*!< ADC HT2 bit 3 */
mbed_official 155:8435094ec241 2695 #define ADC_TR2_HT2_4 ((uint32_t)0x00100000) /*!< ADC HT2 bit 4 */
mbed_official 155:8435094ec241 2696 #define ADC_TR2_HT2_5 ((uint32_t)0x00200000) /*!< ADC HT2 bit 5 */
mbed_official 155:8435094ec241 2697 #define ADC_TR2_HT2_6 ((uint32_t)0x00400000) /*!< ADC HT2 bit 6 */
mbed_official 155:8435094ec241 2698 #define ADC_TR2_HT2_7 ((uint32_t)0x00800000) /*!< ADC HT2 bit 7 */
mbed_official 155:8435094ec241 2699
mbed_official 155:8435094ec241 2700 /******************** Bit definition for ADC_TR3 register ********************/
mbed_official 155:8435094ec241 2701 #define ADC_TR3_LT3 ((uint32_t)0x000000FF) /*!< ADC Analog watchdog 3 lower threshold */
mbed_official 155:8435094ec241 2702 #define ADC_TR3_LT3_0 ((uint32_t)0x00000001) /*!< ADC LT3 bit 0 */
mbed_official 155:8435094ec241 2703 #define ADC_TR3_LT3_1 ((uint32_t)0x00000002) /*!< ADC LT3 bit 1 */
mbed_official 155:8435094ec241 2704 #define ADC_TR3_LT3_2 ((uint32_t)0x00000004) /*!< ADC LT3 bit 2 */
mbed_official 155:8435094ec241 2705 #define ADC_TR3_LT3_3 ((uint32_t)0x00000008) /*!< ADC LT3 bit 3 */
mbed_official 155:8435094ec241 2706 #define ADC_TR3_LT3_4 ((uint32_t)0x00000010) /*!< ADC LT3 bit 4 */
mbed_official 155:8435094ec241 2707 #define ADC_TR3_LT3_5 ((uint32_t)0x00000020) /*!< ADC LT3 bit 5 */
mbed_official 155:8435094ec241 2708 #define ADC_TR3_LT3_6 ((uint32_t)0x00000040) /*!< ADC LT3 bit 6 */
mbed_official 155:8435094ec241 2709 #define ADC_TR3_LT3_7 ((uint32_t)0x00000080) /*!< ADC LT3 bit 7 */
mbed_official 155:8435094ec241 2710
mbed_official 155:8435094ec241 2711 #define ADC_TR3_HT3 ((uint32_t)0x00FF0000) /*!< ADC Analog watchdog 3 higher threshold */
mbed_official 155:8435094ec241 2712 #define ADC_TR3_HT3_0 ((uint32_t)0x00010000) /*!< ADC HT3 bit 0 */
mbed_official 155:8435094ec241 2713 #define ADC_TR3_HT3_1 ((uint32_t)0x00020000) /*!< ADC HT3 bit 1 */
mbed_official 155:8435094ec241 2714 #define ADC_TR3_HT3_2 ((uint32_t)0x00040000) /*!< ADC HT3 bit 2 */
mbed_official 155:8435094ec241 2715 #define ADC_TR3_HT3_3 ((uint32_t)0x00080000) /*!< ADC HT3 bit 3 */
mbed_official 155:8435094ec241 2716 #define ADC_TR3_HT3_4 ((uint32_t)0x00100000) /*!< ADC HT3 bit 4 */
mbed_official 155:8435094ec241 2717 #define ADC_TR3_HT3_5 ((uint32_t)0x00200000) /*!< ADC HT3 bit 5 */
mbed_official 155:8435094ec241 2718 #define ADC_TR3_HT3_6 ((uint32_t)0x00400000) /*!< ADC HT3 bit 6 */
mbed_official 155:8435094ec241 2719 #define ADC_TR3_HT3_7 ((uint32_t)0x00800000) /*!< ADC HT3 bit 7 */
mbed_official 155:8435094ec241 2720
mbed_official 155:8435094ec241 2721 /******************** Bit definition for ADC_SQR1 register ********************/
mbed_official 155:8435094ec241 2722 #define ADC_SQR1_L ((uint32_t)0x0000000F) /*!< ADC regular channel sequence length */
mbed_official 155:8435094ec241 2723 #define ADC_SQR1_L_0 ((uint32_t)0x00000001) /*!< ADC L bit 0 */
mbed_official 155:8435094ec241 2724 #define ADC_SQR1_L_1 ((uint32_t)0x00000002) /*!< ADC L bit 1 */
mbed_official 155:8435094ec241 2725 #define ADC_SQR1_L_2 ((uint32_t)0x00000004) /*!< ADC L bit 2 */
mbed_official 155:8435094ec241 2726 #define ADC_SQR1_L_3 ((uint32_t)0x00000008) /*!< ADC L bit 3 */
mbed_official 155:8435094ec241 2727
mbed_official 155:8435094ec241 2728 #define ADC_SQR1_SQ1 ((uint32_t)0x000007C0) /*!< ADC 1st conversion in regular sequence */
mbed_official 155:8435094ec241 2729 #define ADC_SQR1_SQ1_0 ((uint32_t)0x00000040) /*!< ADC SQ1 bit 0 */
mbed_official 155:8435094ec241 2730 #define ADC_SQR1_SQ1_1 ((uint32_t)0x00000080) /*!< ADC SQ1 bit 1 */
mbed_official 155:8435094ec241 2731 #define ADC_SQR1_SQ1_2 ((uint32_t)0x00000100) /*!< ADC SQ1 bit 2 */
mbed_official 155:8435094ec241 2732 #define ADC_SQR1_SQ1_3 ((uint32_t)0x00000200) /*!< ADC SQ1 bit 3 */
mbed_official 155:8435094ec241 2733 #define ADC_SQR1_SQ1_4 ((uint32_t)0x00000400) /*!< ADC SQ1 bit 4 */
mbed_official 155:8435094ec241 2734
mbed_official 155:8435094ec241 2735 #define ADC_SQR1_SQ2 ((uint32_t)0x0001F000) /*!< ADC 2nd conversion in regular sequence */
mbed_official 155:8435094ec241 2736 #define ADC_SQR1_SQ2_0 ((uint32_t)0x00001000) /*!< ADC SQ2 bit 0 */
mbed_official 155:8435094ec241 2737 #define ADC_SQR1_SQ2_1 ((uint32_t)0x00002000) /*!< ADC SQ2 bit 1 */
mbed_official 155:8435094ec241 2738 #define ADC_SQR1_SQ2_2 ((uint32_t)0x00004000) /*!< ADC SQ2 bit 2 */
mbed_official 155:8435094ec241 2739 #define ADC_SQR1_SQ2_3 ((uint32_t)0x00008000) /*!< ADC SQ2 bit 3 */
mbed_official 155:8435094ec241 2740 #define ADC_SQR1_SQ2_4 ((uint32_t)0x00010000) /*!< ADC SQ2 bit 4 */
mbed_official 155:8435094ec241 2741
mbed_official 155:8435094ec241 2742 #define ADC_SQR1_SQ3 ((uint32_t)0x007C0000) /*!< ADC 3rd conversion in regular sequence */
mbed_official 155:8435094ec241 2743 #define ADC_SQR1_SQ3_0 ((uint32_t)0x00040000) /*!< ADC SQ3 bit 0 */
mbed_official 155:8435094ec241 2744 #define ADC_SQR1_SQ3_1 ((uint32_t)0x00080000) /*!< ADC SQ3 bit 1 */
mbed_official 155:8435094ec241 2745 #define ADC_SQR1_SQ3_2 ((uint32_t)0x00100000) /*!< ADC SQ3 bit 2 */
mbed_official 155:8435094ec241 2746 #define ADC_SQR1_SQ3_3 ((uint32_t)0x00200000) /*!< ADC SQ3 bit 3 */
mbed_official 155:8435094ec241 2747 #define ADC_SQR1_SQ3_4 ((uint32_t)0x00400000) /*!< ADC SQ3 bit 4 */
mbed_official 155:8435094ec241 2748
mbed_official 155:8435094ec241 2749 #define ADC_SQR1_SQ4 ((uint32_t)0x1F000000) /*!< ADC 4th conversion in regular sequence */
mbed_official 155:8435094ec241 2750 #define ADC_SQR1_SQ4_0 ((uint32_t)0x01000000) /*!< ADC SQ4 bit 0 */
mbed_official 155:8435094ec241 2751 #define ADC_SQR1_SQ4_1 ((uint32_t)0x02000000) /*!< ADC SQ4 bit 1 */
mbed_official 155:8435094ec241 2752 #define ADC_SQR1_SQ4_2 ((uint32_t)0x04000000) /*!< ADC SQ4 bit 2 */
mbed_official 155:8435094ec241 2753 #define ADC_SQR1_SQ4_3 ((uint32_t)0x08000000) /*!< ADC SQ4 bit 3 */
mbed_official 155:8435094ec241 2754 #define ADC_SQR1_SQ4_4 ((uint32_t)0x10000000) /*!< ADC SQ4 bit 4 */
mbed_official 155:8435094ec241 2755
mbed_official 155:8435094ec241 2756 /******************** Bit definition for ADC_SQR2 register ********************/
mbed_official 155:8435094ec241 2757 #define ADC_SQR2_SQ5 ((uint32_t)0x0000001F) /*!< ADC 5th conversion in regular sequence */
mbed_official 155:8435094ec241 2758 #define ADC_SQR2_SQ5_0 ((uint32_t)0x00000001) /*!< ADC SQ5 bit 0 */
mbed_official 155:8435094ec241 2759 #define ADC_SQR2_SQ5_1 ((uint32_t)0x00000002) /*!< ADC SQ5 bit 1 */
mbed_official 155:8435094ec241 2760 #define ADC_SQR2_SQ5_2 ((uint32_t)0x00000004) /*!< ADC SQ5 bit 2 */
mbed_official 155:8435094ec241 2761 #define ADC_SQR2_SQ5_3 ((uint32_t)0x00000008) /*!< ADC SQ5 bit 3 */
mbed_official 155:8435094ec241 2762 #define ADC_SQR2_SQ5_4 ((uint32_t)0x00000010) /*!< ADC SQ5 bit 4 */
mbed_official 155:8435094ec241 2763
mbed_official 155:8435094ec241 2764 #define ADC_SQR2_SQ6 ((uint32_t)0x000007C0) /*!< ADC 6th conversion in regular sequence */
mbed_official 155:8435094ec241 2765 #define ADC_SQR2_SQ6_0 ((uint32_t)0x00000040) /*!< ADC SQ6 bit 0 */
mbed_official 155:8435094ec241 2766 #define ADC_SQR2_SQ6_1 ((uint32_t)0x00000080) /*!< ADC SQ6 bit 1 */
mbed_official 155:8435094ec241 2767 #define ADC_SQR2_SQ6_2 ((uint32_t)0x00000100) /*!< ADC SQ6 bit 2 */
mbed_official 155:8435094ec241 2768 #define ADC_SQR2_SQ6_3 ((uint32_t)0x00000200) /*!< ADC SQ6 bit 3 */
mbed_official 155:8435094ec241 2769 #define ADC_SQR2_SQ6_4 ((uint32_t)0x00000400) /*!< ADC SQ6 bit 4 */
mbed_official 155:8435094ec241 2770
mbed_official 155:8435094ec241 2771 #define ADC_SQR2_SQ7 ((uint32_t)0x0001F000) /*!< ADC 7th conversion in regular sequence */
mbed_official 155:8435094ec241 2772 #define ADC_SQR2_SQ7_0 ((uint32_t)0x00001000) /*!< ADC SQ7 bit 0 */
mbed_official 155:8435094ec241 2773 #define ADC_SQR2_SQ7_1 ((uint32_t)0x00002000) /*!< ADC SQ7 bit 1 */
mbed_official 155:8435094ec241 2774 #define ADC_SQR2_SQ7_2 ((uint32_t)0x00004000) /*!< ADC SQ7 bit 2 */
mbed_official 155:8435094ec241 2775 #define ADC_SQR2_SQ7_3 ((uint32_t)0x00008000) /*!< ADC SQ7 bit 3 */
mbed_official 155:8435094ec241 2776 #define ADC_SQR2_SQ7_4 ((uint32_t)0x00010000) /*!< ADC SQ7 bit 4 */
mbed_official 155:8435094ec241 2777
mbed_official 155:8435094ec241 2778 #define ADC_SQR2_SQ8 ((uint32_t)0x007C0000) /*!< ADC 8th conversion in regular sequence */
mbed_official 155:8435094ec241 2779 #define ADC_SQR2_SQ8_0 ((uint32_t)0x00040000) /*!< ADC SQ8 bit 0 */
mbed_official 155:8435094ec241 2780 #define ADC_SQR2_SQ8_1 ((uint32_t)0x00080000) /*!< ADC SQ8 bit 1 */
mbed_official 155:8435094ec241 2781 #define ADC_SQR2_SQ8_2 ((uint32_t)0x00100000) /*!< ADC SQ8 bit 2 */
mbed_official 155:8435094ec241 2782 #define ADC_SQR2_SQ8_3 ((uint32_t)0x00200000) /*!< ADC SQ8 bit 3 */
mbed_official 155:8435094ec241 2783 #define ADC_SQR2_SQ8_4 ((uint32_t)0x00400000) /*!< ADC SQ8 bit 4 */
mbed_official 155:8435094ec241 2784
mbed_official 155:8435094ec241 2785 #define ADC_SQR2_SQ9 ((uint32_t)0x1F000000) /*!< ADC 9th conversion in regular sequence */
mbed_official 155:8435094ec241 2786 #define ADC_SQR2_SQ9_0 ((uint32_t)0x01000000) /*!< ADC SQ9 bit 0 */
mbed_official 155:8435094ec241 2787 #define ADC_SQR2_SQ9_1 ((uint32_t)0x02000000) /*!< ADC SQ9 bit 1 */
mbed_official 155:8435094ec241 2788 #define ADC_SQR2_SQ9_2 ((uint32_t)0x04000000) /*!< ADC SQ9 bit 2 */
mbed_official 155:8435094ec241 2789 #define ADC_SQR2_SQ9_3 ((uint32_t)0x08000000) /*!< ADC SQ9 bit 3 */
mbed_official 155:8435094ec241 2790 #define ADC_SQR2_SQ9_4 ((uint32_t)0x10000000) /*!< ADC SQ9 bit 4 */
mbed_official 155:8435094ec241 2791
mbed_official 155:8435094ec241 2792 /******************** Bit definition for ADC_SQR3 register ********************/
mbed_official 155:8435094ec241 2793 #define ADC_SQR3_SQ10 ((uint32_t)0x0000001F) /*!< ADC 10th conversion in regular sequence */
mbed_official 155:8435094ec241 2794 #define ADC_SQR3_SQ10_0 ((uint32_t)0x00000001) /*!< ADC SQ10 bit 0 */
mbed_official 155:8435094ec241 2795 #define ADC_SQR3_SQ10_1 ((uint32_t)0x00000002) /*!< ADC SQ10 bit 1 */
mbed_official 155:8435094ec241 2796 #define ADC_SQR3_SQ10_2 ((uint32_t)0x00000004) /*!< ADC SQ10 bit 2 */
mbed_official 155:8435094ec241 2797 #define ADC_SQR3_SQ10_3 ((uint32_t)0x00000008) /*!< ADC SQ10 bit 3 */
mbed_official 155:8435094ec241 2798 #define ADC_SQR3_SQ10_4 ((uint32_t)0x00000010) /*!< ADC SQ10 bit 4 */
mbed_official 155:8435094ec241 2799
mbed_official 155:8435094ec241 2800 #define ADC_SQR3_SQ11 ((uint32_t)0x000007C0) /*!< ADC 11th conversion in regular sequence */
mbed_official 155:8435094ec241 2801 #define ADC_SQR3_SQ11_0 ((uint32_t)0x00000040) /*!< ADC SQ11 bit 0 */
mbed_official 155:8435094ec241 2802 #define ADC_SQR3_SQ11_1 ((uint32_t)0x00000080) /*!< ADC SQ11 bit 1 */
mbed_official 155:8435094ec241 2803 #define ADC_SQR3_SQ11_2 ((uint32_t)0x00000100) /*!< ADC SQ11 bit 2 */
mbed_official 155:8435094ec241 2804 #define ADC_SQR3_SQ11_3 ((uint32_t)0x00000200) /*!< ADC SQ11 bit 3 */
mbed_official 155:8435094ec241 2805 #define ADC_SQR3_SQ11_4 ((uint32_t)0x00000400) /*!< ADC SQ11 bit 4 */
mbed_official 155:8435094ec241 2806
mbed_official 155:8435094ec241 2807 #define ADC_SQR3_SQ12 ((uint32_t)0x0001F000) /*!< ADC 12th conversion in regular sequence */
mbed_official 155:8435094ec241 2808 #define ADC_SQR3_SQ12_0 ((uint32_t)0x00001000) /*!< ADC SQ12 bit 0 */
mbed_official 155:8435094ec241 2809 #define ADC_SQR3_SQ12_1 ((uint32_t)0x00002000) /*!< ADC SQ12 bit 1 */
mbed_official 155:8435094ec241 2810 #define ADC_SQR3_SQ12_2 ((uint32_t)0x00004000) /*!< ADC SQ12 bit 2 */
mbed_official 155:8435094ec241 2811 #define ADC_SQR3_SQ12_3 ((uint32_t)0x00008000) /*!< ADC SQ12 bit 3 */
mbed_official 155:8435094ec241 2812 #define ADC_SQR3_SQ12_4 ((uint32_t)0x00010000) /*!< ADC SQ12 bit 4 */
mbed_official 155:8435094ec241 2813
mbed_official 155:8435094ec241 2814 #define ADC_SQR3_SQ13 ((uint32_t)0x007C0000) /*!< ADC 13th conversion in regular sequence */
mbed_official 155:8435094ec241 2815 #define ADC_SQR3_SQ13_0 ((uint32_t)0x00040000) /*!< ADC SQ13 bit 0 */
mbed_official 155:8435094ec241 2816 #define ADC_SQR3_SQ13_1 ((uint32_t)0x00080000) /*!< ADC SQ13 bit 1 */
mbed_official 155:8435094ec241 2817 #define ADC_SQR3_SQ13_2 ((uint32_t)0x00100000) /*!< ADC SQ13 bit 2 */
mbed_official 155:8435094ec241 2818 #define ADC_SQR3_SQ13_3 ((uint32_t)0x00200000) /*!< ADC SQ13 bit 3 */
mbed_official 155:8435094ec241 2819 #define ADC_SQR3_SQ13_4 ((uint32_t)0x00400000) /*!< ADC SQ13 bit 4 */
mbed_official 155:8435094ec241 2820
mbed_official 155:8435094ec241 2821 #define ADC_SQR3_SQ14 ((uint32_t)0x1F000000) /*!< ADC 14th conversion in regular sequence */
mbed_official 155:8435094ec241 2822 #define ADC_SQR3_SQ14_0 ((uint32_t)0x01000000) /*!< ADC SQ14 bit 0 */
mbed_official 155:8435094ec241 2823 #define ADC_SQR3_SQ14_1 ((uint32_t)0x02000000) /*!< ADC SQ14 bit 1 */
mbed_official 155:8435094ec241 2824 #define ADC_SQR3_SQ14_2 ((uint32_t)0x04000000) /*!< ADC SQ14 bit 2 */
mbed_official 155:8435094ec241 2825 #define ADC_SQR3_SQ14_3 ((uint32_t)0x08000000) /*!< ADC SQ14 bit 3 */
mbed_official 155:8435094ec241 2826 #define ADC_SQR3_SQ14_4 ((uint32_t)0x10000000) /*!< ADC SQ14 bit 4 */
mbed_official 155:8435094ec241 2827
mbed_official 155:8435094ec241 2828 /******************** Bit definition for ADC_SQR4 register ********************/
mbed_official 155:8435094ec241 2829 #define ADC_SQR4_SQ15 ((uint32_t)0x0000001F) /*!< ADC 15th conversion in regular sequence */
mbed_official 155:8435094ec241 2830 #define ADC_SQR4_SQ15_0 ((uint32_t)0x00000001) /*!< ADC SQ15 bit 0 */
mbed_official 155:8435094ec241 2831 #define ADC_SQR4_SQ15_1 ((uint32_t)0x00000002) /*!< ADC SQ15 bit 1 */
mbed_official 155:8435094ec241 2832 #define ADC_SQR4_SQ15_2 ((uint32_t)0x00000004) /*!< ADC SQ15 bit 2 */
mbed_official 155:8435094ec241 2833 #define ADC_SQR4_SQ15_3 ((uint32_t)0x00000008) /*!< ADC SQ15 bit 3 */
mbed_official 155:8435094ec241 2834 #define ADC_SQR4_SQ15_4 ((uint32_t)0x00000010) /*!< ADC SQ105 bit 4 */
mbed_official 155:8435094ec241 2835
mbed_official 155:8435094ec241 2836 #define ADC_SQR4_SQ16 ((uint32_t)0x000007C0) /*!< ADC 16th conversion in regular sequence */
mbed_official 155:8435094ec241 2837 #define ADC_SQR4_SQ16_0 ((uint32_t)0x00000040) /*!< ADC SQ16 bit 0 */
mbed_official 155:8435094ec241 2838 #define ADC_SQR4_SQ16_1 ((uint32_t)0x00000080) /*!< ADC SQ16 bit 1 */
mbed_official 155:8435094ec241 2839 #define ADC_SQR4_SQ16_2 ((uint32_t)0x00000100) /*!< ADC SQ16 bit 2 */
mbed_official 155:8435094ec241 2840 #define ADC_SQR4_SQ16_3 ((uint32_t)0x00000200) /*!< ADC SQ16 bit 3 */
mbed_official 155:8435094ec241 2841 #define ADC_SQR4_SQ16_4 ((uint32_t)0x00000400) /*!< ADC SQ16 bit 4 */
mbed_official 155:8435094ec241 2842
mbed_official 155:8435094ec241 2843 /* these defines are maintained for legacy purpose */
mbed_official 155:8435094ec241 2844 #define ADC_SQR3_SQ15 ADC_SQR4_SQ15 /*!< ADC 15th conversion in regular sequence */
mbed_official 155:8435094ec241 2845 #define ADC_SQR3_SQ15_0 ADC_SQR4_SQ15_0 /*!< ADC SQ15 bit 0 */
mbed_official 155:8435094ec241 2846 #define ADC_SQR3_SQ15_1 ADC_SQR4_SQ15_1 /*!< ADC SQ15 bit 1 */
mbed_official 155:8435094ec241 2847 #define ADC_SQR3_SQ15_2 ADC_SQR4_SQ15_2 /*!< ADC SQ15 bit 2 */
mbed_official 155:8435094ec241 2848 #define ADC_SQR3_SQ15_3 ADC_SQR4_SQ15_3 /*!< ADC SQ15 bit 3 */
mbed_official 155:8435094ec241 2849 #define ADC_SQR3_SQ15_4 ADC_SQR4_SQ15_4 /*!< ADC SQ105 bit 4 */
mbed_official 155:8435094ec241 2850
mbed_official 155:8435094ec241 2851 #define ADC_SQR3_SQ16 ADC_SQR4_SQ16 /*!< ADC 16th conversion in regular sequence */
mbed_official 155:8435094ec241 2852 #define ADC_SQR3_SQ16_0 ADC_SQR4_SQ16_0 /*!< ADC SQ16 bit 0 */
mbed_official 155:8435094ec241 2853 #define ADC_SQR3_SQ16_1 ADC_SQR4_SQ16_1 /*!< ADC SQ16 bit 1 */
mbed_official 155:8435094ec241 2854 #define ADC_SQR3_SQ16_2 ADC_SQR4_SQ16_2 /*!< ADC SQ16 bit 2 */
mbed_official 155:8435094ec241 2855 #define ADC_SQR3_SQ16_3 ADC_SQR4_SQ16_3 /*!< ADC SQ16 bit 3 */
mbed_official 155:8435094ec241 2856 #define ADC_SQR3_SQ16_4 ADC_SQR4_SQ16_4 /*!< ADC SQ16 bit 4 */
mbed_official 155:8435094ec241 2857 /******************** Bit definition for ADC_DR register ********************/
mbed_official 155:8435094ec241 2858 #define ADC_DR_RDATA ((uint32_t)0x0000FFFF) /*!< ADC regular Data converted */
mbed_official 155:8435094ec241 2859 #define ADC_DR_RDATA_0 ((uint32_t)0x00000001) /*!< ADC RDATA bit 0 */
mbed_official 155:8435094ec241 2860 #define ADC_DR_RDATA_1 ((uint32_t)0x00000002) /*!< ADC RDATA bit 1 */
mbed_official 155:8435094ec241 2861 #define ADC_DR_RDATA_2 ((uint32_t)0x00000004) /*!< ADC RDATA bit 2 */
mbed_official 155:8435094ec241 2862 #define ADC_DR_RDATA_3 ((uint32_t)0x00000008) /*!< ADC RDATA bit 3 */
mbed_official 155:8435094ec241 2863 #define ADC_DR_RDATA_4 ((uint32_t)0x00000010) /*!< ADC RDATA bit 4 */
mbed_official 155:8435094ec241 2864 #define ADC_DR_RDATA_5 ((uint32_t)0x00000020) /*!< ADC RDATA bit 5 */
mbed_official 155:8435094ec241 2865 #define ADC_DR_RDATA_6 ((uint32_t)0x00000040) /*!< ADC RDATA bit 6 */
mbed_official 155:8435094ec241 2866 #define ADC_DR_RDATA_7 ((uint32_t)0x00000080) /*!< ADC RDATA bit 7 */
mbed_official 155:8435094ec241 2867 #define ADC_DR_RDATA_8 ((uint32_t)0x00000100) /*!< ADC RDATA bit 8 */
mbed_official 155:8435094ec241 2868 #define ADC_DR_RDATA_9 ((uint32_t)0x00000200) /*!< ADC RDATA bit 9 */
mbed_official 155:8435094ec241 2869 #define ADC_DR_RDATA_10 ((uint32_t)0x00000400) /*!< ADC RDATA bit 10 */
mbed_official 155:8435094ec241 2870 #define ADC_DR_RDATA_11 ((uint32_t)0x00000800) /*!< ADC RDATA bit 11 */
mbed_official 155:8435094ec241 2871 #define ADC_DR_RDATA_12 ((uint32_t)0x00001000) /*!< ADC RDATA bit 12 */
mbed_official 155:8435094ec241 2872 #define ADC_DR_RDATA_13 ((uint32_t)0x00002000) /*!< ADC RDATA bit 13 */
mbed_official 155:8435094ec241 2873 #define ADC_DR_RDATA_14 ((uint32_t)0x00004000) /*!< ADC RDATA bit 14 */
mbed_official 155:8435094ec241 2874 #define ADC_DR_RDATA_15 ((uint32_t)0x00008000) /*!< ADC RDATA bit 15 */
mbed_official 155:8435094ec241 2875
mbed_official 155:8435094ec241 2876 /******************** Bit definition for ADC_JSQR register ********************/
mbed_official 155:8435094ec241 2877 #define ADC_JSQR_JL ((uint32_t)0x00000003) /*!< ADC injected channel sequence length */
mbed_official 155:8435094ec241 2878 #define ADC_JSQR_JL_0 ((uint32_t)0x00000001) /*!< ADC JL bit 0 */
mbed_official 155:8435094ec241 2879 #define ADC_JSQR_JL_1 ((uint32_t)0x00000002) /*!< ADC JL bit 1 */
mbed_official 155:8435094ec241 2880
mbed_official 155:8435094ec241 2881 #define ADC_JSQR_JEXTSEL ((uint32_t)0x0000003C) /*!< ADC external trigger selection for injected group */
mbed_official 155:8435094ec241 2882 #define ADC_JSQR_JEXTSEL_0 ((uint32_t)0x00000004) /*!< ADC JEXTSEL bit 0 */
mbed_official 155:8435094ec241 2883 #define ADC_JSQR_JEXTSEL_1 ((uint32_t)0x00000008) /*!< ADC JEXTSEL bit 1 */
mbed_official 155:8435094ec241 2884 #define ADC_JSQR_JEXTSEL_2 ((uint32_t)0x00000010) /*!< ADC JEXTSEL bit 2 */
mbed_official 155:8435094ec241 2885 #define ADC_JSQR_JEXTSEL_3 ((uint32_t)0x00000020) /*!< ADC JEXTSEL bit 3 */
mbed_official 155:8435094ec241 2886
mbed_official 155:8435094ec241 2887 #define ADC_JSQR_JEXTEN ((uint32_t)0x000000C0) /*!< ADC external trigger enable and polarity selection for injected channels */
mbed_official 155:8435094ec241 2888 #define ADC_JSQR_JEXTEN_0 ((uint32_t)0x00000040) /*!< ADC JEXTEN bit 0 */
mbed_official 155:8435094ec241 2889 #define ADC_JSQR_JEXTEN_1 ((uint32_t)0x00000080) /*!< ADC JEXTEN bit 1 */
mbed_official 155:8435094ec241 2890
mbed_official 155:8435094ec241 2891 #define ADC_JSQR_JSQ1 ((uint32_t)0x00001F00) /*!< ADC 1st conversion in injected sequence */
mbed_official 155:8435094ec241 2892 #define ADC_JSQR_JSQ1_0 ((uint32_t)0x00000100) /*!< ADC JSQ1 bit 0 */
mbed_official 155:8435094ec241 2893 #define ADC_JSQR_JSQ1_1 ((uint32_t)0x00000200) /*!< ADC JSQ1 bit 1 */
mbed_official 155:8435094ec241 2894 #define ADC_JSQR_JSQ1_2 ((uint32_t)0x00000400) /*!< ADC JSQ1 bit 2 */
mbed_official 155:8435094ec241 2895 #define ADC_JSQR_JSQ1_3 ((uint32_t)0x00000800) /*!< ADC JSQ1 bit 3 */
mbed_official 155:8435094ec241 2896 #define ADC_JSQR_JSQ1_4 ((uint32_t)0x00001000) /*!< ADC JSQ1 bit 4 */
mbed_official 155:8435094ec241 2897
mbed_official 155:8435094ec241 2898 #define ADC_JSQR_JSQ2 ((uint32_t)0x0007C000) /*!< ADC 2nd conversion in injected sequence */
mbed_official 155:8435094ec241 2899 #define ADC_JSQR_JSQ2_0 ((uint32_t)0x00004000) /*!< ADC JSQ2 bit 0 */
mbed_official 155:8435094ec241 2900 #define ADC_JSQR_JSQ2_1 ((uint32_t)0x00008000) /*!< ADC JSQ2 bit 1 */
mbed_official 155:8435094ec241 2901 #define ADC_JSQR_JSQ2_2 ((uint32_t)0x00010000) /*!< ADC JSQ2 bit 2 */
mbed_official 155:8435094ec241 2902 #define ADC_JSQR_JSQ2_3 ((uint32_t)0x00020000) /*!< ADC JSQ2 bit 3 */
mbed_official 155:8435094ec241 2903 #define ADC_JSQR_JSQ2_4 ((uint32_t)0x00040000) /*!< ADC JSQ2 bit 4 */
mbed_official 155:8435094ec241 2904
mbed_official 155:8435094ec241 2905 #define ADC_JSQR_JSQ3 ((uint32_t)0x01F00000) /*!< ADC 3rd conversion in injected sequence */
mbed_official 155:8435094ec241 2906 #define ADC_JSQR_JSQ3_0 ((uint32_t)0x00100000) /*!< ADC JSQ3 bit 0 */
mbed_official 155:8435094ec241 2907 #define ADC_JSQR_JSQ3_1 ((uint32_t)0x00200000) /*!< ADC JSQ3 bit 1 */
mbed_official 155:8435094ec241 2908 #define ADC_JSQR_JSQ3_2 ((uint32_t)0x00400000) /*!< ADC JSQ3 bit 2 */
mbed_official 155:8435094ec241 2909 #define ADC_JSQR_JSQ3_3 ((uint32_t)0x00800000) /*!< ADC JSQ3 bit 3 */
mbed_official 155:8435094ec241 2910 #define ADC_JSQR_JSQ3_4 ((uint32_t)0x01000000) /*!< ADC JSQ3 bit 4 */
mbed_official 155:8435094ec241 2911
mbed_official 155:8435094ec241 2912 #define ADC_JSQR_JSQ4 ((uint32_t)0x7C000000) /*!< ADC 4th conversion in injected sequence */
mbed_official 155:8435094ec241 2913 #define ADC_JSQR_JSQ4_0 ((uint32_t)0x04000000) /*!< ADC JSQ4 bit 0 */
mbed_official 155:8435094ec241 2914 #define ADC_JSQR_JSQ4_1 ((uint32_t)0x08000000) /*!< ADC JSQ4 bit 1 */
mbed_official 155:8435094ec241 2915 #define ADC_JSQR_JSQ4_2 ((uint32_t)0x10000000) /*!< ADC JSQ4 bit 2 */
mbed_official 155:8435094ec241 2916 #define ADC_JSQR_JSQ4_3 ((uint32_t)0x20000000) /*!< ADC JSQ4 bit 3 */
mbed_official 155:8435094ec241 2917 #define ADC_JSQR_JSQ4_4 ((uint32_t)0x40000000) /*!< ADC JSQ4 bit 4 */
mbed_official 155:8435094ec241 2918
mbed_official 155:8435094ec241 2919 /******************** Bit definition for ADC_OFR1 register ********************/
mbed_official 155:8435094ec241 2920 #define ADC_OFR1_OFFSET1 ((uint32_t)0x00000FFF) /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
mbed_official 155:8435094ec241 2921 #define ADC_OFR1_OFFSET1_0 ((uint32_t)0x00000001) /*!< ADC OFFSET1 bit 0 */
mbed_official 155:8435094ec241 2922 #define ADC_OFR1_OFFSET1_1 ((uint32_t)0x00000002) /*!< ADC OFFSET1 bit 1 */
mbed_official 155:8435094ec241 2923 #define ADC_OFR1_OFFSET1_2 ((uint32_t)0x00000004) /*!< ADC OFFSET1 bit 2 */
mbed_official 155:8435094ec241 2924 #define ADC_OFR1_OFFSET1_3 ((uint32_t)0x00000008) /*!< ADC OFFSET1 bit 3 */
mbed_official 155:8435094ec241 2925 #define ADC_OFR1_OFFSET1_4 ((uint32_t)0x00000010) /*!< ADC OFFSET1 bit 4 */
mbed_official 155:8435094ec241 2926 #define ADC_OFR1_OFFSET1_5 ((uint32_t)0x00000020) /*!< ADC OFFSET1 bit 5 */
mbed_official 155:8435094ec241 2927 #define ADC_OFR1_OFFSET1_6 ((uint32_t)0x00000040) /*!< ADC OFFSET1 bit 6 */
mbed_official 155:8435094ec241 2928 #define ADC_OFR1_OFFSET1_7 ((uint32_t)0x00000080) /*!< ADC OFFSET1 bit 7 */
mbed_official 155:8435094ec241 2929 #define ADC_OFR1_OFFSET1_8 ((uint32_t)0x00000100) /*!< ADC OFFSET1 bit 8 */
mbed_official 155:8435094ec241 2930 #define ADC_OFR1_OFFSET1_9 ((uint32_t)0x00000200) /*!< ADC OFFSET1 bit 9 */
mbed_official 155:8435094ec241 2931 #define ADC_OFR1_OFFSET1_10 ((uint32_t)0x00000400) /*!< ADC OFFSET1 bit 10 */
mbed_official 155:8435094ec241 2932 #define ADC_OFR1_OFFSET1_11 ((uint32_t)0x00000800) /*!< ADC OFFSET1 bit 11 */
mbed_official 155:8435094ec241 2933
mbed_official 155:8435094ec241 2934 #define ADC_OFR1_OFFSET1_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 1 */
mbed_official 155:8435094ec241 2935 #define ADC_OFR1_OFFSET1_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET1_CH bit 0 */
mbed_official 155:8435094ec241 2936 #define ADC_OFR1_OFFSET1_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET1_CH bit 1 */
mbed_official 155:8435094ec241 2937 #define ADC_OFR1_OFFSET1_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET1_CH bit 2 */
mbed_official 155:8435094ec241 2938 #define ADC_OFR1_OFFSET1_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET1_CH bit 3 */
mbed_official 155:8435094ec241 2939 #define ADC_OFR1_OFFSET1_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET1_CH bit 4 */
mbed_official 155:8435094ec241 2940
mbed_official 155:8435094ec241 2941 #define ADC_OFR1_OFFSET1_EN ((uint32_t)0x80000000) /*!< ADC offset 1 enable */
mbed_official 155:8435094ec241 2942
mbed_official 155:8435094ec241 2943 /******************** Bit definition for ADC_OFR2 register ********************/
mbed_official 155:8435094ec241 2944 #define ADC_OFR2_OFFSET2 ((uint32_t)0x00000FFF) /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
mbed_official 155:8435094ec241 2945 #define ADC_OFR2_OFFSET2_0 ((uint32_t)0x00000001) /*!< ADC OFFSET2 bit 0 */
mbed_official 155:8435094ec241 2946 #define ADC_OFR2_OFFSET2_1 ((uint32_t)0x00000002) /*!< ADC OFFSET2 bit 1 */
mbed_official 155:8435094ec241 2947 #define ADC_OFR2_OFFSET2_2 ((uint32_t)0x00000004) /*!< ADC OFFSET2 bit 2 */
mbed_official 155:8435094ec241 2948 #define ADC_OFR2_OFFSET2_3 ((uint32_t)0x00000008) /*!< ADC OFFSET2 bit 3 */
mbed_official 155:8435094ec241 2949 #define ADC_OFR2_OFFSET2_4 ((uint32_t)0x00000010) /*!< ADC OFFSET2 bit 4 */
mbed_official 155:8435094ec241 2950 #define ADC_OFR2_OFFSET2_5 ((uint32_t)0x00000020) /*!< ADC OFFSET2 bit 5 */
mbed_official 155:8435094ec241 2951 #define ADC_OFR2_OFFSET2_6 ((uint32_t)0x00000040) /*!< ADC OFFSET2 bit 6 */
mbed_official 155:8435094ec241 2952 #define ADC_OFR2_OFFSET2_7 ((uint32_t)0x00000080) /*!< ADC OFFSET2 bit 7 */
mbed_official 155:8435094ec241 2953 #define ADC_OFR2_OFFSET2_8 ((uint32_t)0x00000100) /*!< ADC OFFSET2 bit 8 */
mbed_official 155:8435094ec241 2954 #define ADC_OFR2_OFFSET2_9 ((uint32_t)0x00000200) /*!< ADC OFFSET2 bit 9 */
mbed_official 155:8435094ec241 2955 #define ADC_OFR2_OFFSET2_10 ((uint32_t)0x00000400) /*!< ADC OFFSET2 bit 10 */
mbed_official 155:8435094ec241 2956 #define ADC_OFR2_OFFSET2_11 ((uint32_t)0x00000800) /*!< ADC OFFSET2 bit 11 */
mbed_official 155:8435094ec241 2957
mbed_official 155:8435094ec241 2958 #define ADC_OFR2_OFFSET2_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 2 */
mbed_official 155:8435094ec241 2959 #define ADC_OFR2_OFFSET2_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET2_CH bit 0 */
mbed_official 155:8435094ec241 2960 #define ADC_OFR2_OFFSET2_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET2_CH bit 1 */
mbed_official 155:8435094ec241 2961 #define ADC_OFR2_OFFSET2_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET2_CH bit 2 */
mbed_official 155:8435094ec241 2962 #define ADC_OFR2_OFFSET2_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET2_CH bit 3 */
mbed_official 155:8435094ec241 2963 #define ADC_OFR2_OFFSET2_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET2_CH bit 4 */
mbed_official 155:8435094ec241 2964
mbed_official 155:8435094ec241 2965 #define ADC_OFR2_OFFSET2_EN ((uint32_t)0x80000000) /*!< ADC offset 2 enable */
mbed_official 155:8435094ec241 2966
mbed_official 155:8435094ec241 2967 /******************** Bit definition for ADC_OFR3 register ********************/
mbed_official 155:8435094ec241 2968 #define ADC_OFR3_OFFSET3 ((uint32_t)0x00000FFF) /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
mbed_official 155:8435094ec241 2969 #define ADC_OFR3_OFFSET3_0 ((uint32_t)0x00000001) /*!< ADC OFFSET3 bit 0 */
mbed_official 155:8435094ec241 2970 #define ADC_OFR3_OFFSET3_1 ((uint32_t)0x00000002) /*!< ADC OFFSET3 bit 1 */
mbed_official 155:8435094ec241 2971 #define ADC_OFR3_OFFSET3_2 ((uint32_t)0x00000004) /*!< ADC OFFSET3 bit 2 */
mbed_official 155:8435094ec241 2972 #define ADC_OFR3_OFFSET3_3 ((uint32_t)0x00000008) /*!< ADC OFFSET3 bit 3 */
mbed_official 155:8435094ec241 2973 #define ADC_OFR3_OFFSET3_4 ((uint32_t)0x00000010) /*!< ADC OFFSET3 bit 4 */
mbed_official 155:8435094ec241 2974 #define ADC_OFR3_OFFSET3_5 ((uint32_t)0x00000020) /*!< ADC OFFSET3 bit 5 */
mbed_official 155:8435094ec241 2975 #define ADC_OFR3_OFFSET3_6 ((uint32_t)0x00000040) /*!< ADC OFFSET3 bit 6 */
mbed_official 155:8435094ec241 2976 #define ADC_OFR3_OFFSET3_7 ((uint32_t)0x00000080) /*!< ADC OFFSET3 bit 7 */
mbed_official 155:8435094ec241 2977 #define ADC_OFR3_OFFSET3_8 ((uint32_t)0x00000100) /*!< ADC OFFSET3 bit 8 */
mbed_official 155:8435094ec241 2978 #define ADC_OFR3_OFFSET3_9 ((uint32_t)0x00000200) /*!< ADC OFFSET3 bit 9 */
mbed_official 155:8435094ec241 2979 #define ADC_OFR3_OFFSET3_10 ((uint32_t)0x00000400) /*!< ADC OFFSET3 bit 10 */
mbed_official 155:8435094ec241 2980 #define ADC_OFR3_OFFSET3_11 ((uint32_t)0x00000800) /*!< ADC OFFSET3 bit 11 */
mbed_official 155:8435094ec241 2981
mbed_official 155:8435094ec241 2982 #define ADC_OFR3_OFFSET3_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 3 */
mbed_official 155:8435094ec241 2983 #define ADC_OFR3_OFFSET3_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET3_CH bit 0 */
mbed_official 155:8435094ec241 2984 #define ADC_OFR3_OFFSET3_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET3_CH bit 1 */
mbed_official 155:8435094ec241 2985 #define ADC_OFR3_OFFSET3_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET3_CH bit 2 */
mbed_official 155:8435094ec241 2986 #define ADC_OFR3_OFFSET3_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET3_CH bit 3 */
mbed_official 155:8435094ec241 2987 #define ADC_OFR3_OFFSET3_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET3_CH bit 4 */
mbed_official 155:8435094ec241 2988
mbed_official 155:8435094ec241 2989 #define ADC_OFR3_OFFSET3_EN ((uint32_t)0x80000000) /*!< ADC offset 3 enable */
mbed_official 155:8435094ec241 2990
mbed_official 155:8435094ec241 2991 /******************** Bit definition for ADC_OFR4 register ********************/
mbed_official 155:8435094ec241 2992 #define ADC_OFR4_OFFSET4 ((uint32_t)0x00000FFF) /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
mbed_official 155:8435094ec241 2993 #define ADC_OFR4_OFFSET4_0 ((uint32_t)0x00000001) /*!< ADC OFFSET4 bit 0 */
mbed_official 155:8435094ec241 2994 #define ADC_OFR4_OFFSET4_1 ((uint32_t)0x00000002) /*!< ADC OFFSET4 bit 1 */
mbed_official 155:8435094ec241 2995 #define ADC_OFR4_OFFSET4_2 ((uint32_t)0x00000004) /*!< ADC OFFSET4 bit 2 */
mbed_official 155:8435094ec241 2996 #define ADC_OFR4_OFFSET4_3 ((uint32_t)0x00000008) /*!< ADC OFFSET4 bit 3 */
mbed_official 155:8435094ec241 2997 #define ADC_OFR4_OFFSET4_4 ((uint32_t)0x00000010) /*!< ADC OFFSET4 bit 4 */
mbed_official 155:8435094ec241 2998 #define ADC_OFR4_OFFSET4_5 ((uint32_t)0x00000020) /*!< ADC OFFSET4 bit 5 */
mbed_official 155:8435094ec241 2999 #define ADC_OFR4_OFFSET4_6 ((uint32_t)0x00000040) /*!< ADC OFFSET4 bit 6 */
mbed_official 155:8435094ec241 3000 #define ADC_OFR4_OFFSET4_7 ((uint32_t)0x00000080) /*!< ADC OFFSET4 bit 7 */
mbed_official 155:8435094ec241 3001 #define ADC_OFR4_OFFSET4_8 ((uint32_t)0x00000100) /*!< ADC OFFSET4 bit 8 */
mbed_official 155:8435094ec241 3002 #define ADC_OFR4_OFFSET4_9 ((uint32_t)0x00000200) /*!< ADC OFFSET4 bit 9 */
mbed_official 155:8435094ec241 3003 #define ADC_OFR4_OFFSET4_10 ((uint32_t)0x00000400) /*!< ADC OFFSET4 bit 10 */
mbed_official 155:8435094ec241 3004 #define ADC_OFR4_OFFSET4_11 ((uint32_t)0x00000800) /*!< ADC OFFSET4 bit 11 */
mbed_official 155:8435094ec241 3005
mbed_official 155:8435094ec241 3006 #define ADC_OFR4_OFFSET4_CH ((uint32_t)0x7C000000) /*!< ADC Channel selection for the data offset 4 */
mbed_official 155:8435094ec241 3007 #define ADC_OFR4_OFFSET4_CH_0 ((uint32_t)0x04000000) /*!< ADC OFFSET4_CH bit 0 */
mbed_official 155:8435094ec241 3008 #define ADC_OFR4_OFFSET4_CH_1 ((uint32_t)0x08000000) /*!< ADC OFFSET4_CH bit 1 */
mbed_official 155:8435094ec241 3009 #define ADC_OFR4_OFFSET4_CH_2 ((uint32_t)0x10000000) /*!< ADC OFFSET4_CH bit 2 */
mbed_official 155:8435094ec241 3010 #define ADC_OFR4_OFFSET4_CH_3 ((uint32_t)0x20000000) /*!< ADC OFFSET4_CH bit 3 */
mbed_official 155:8435094ec241 3011 #define ADC_OFR4_OFFSET4_CH_4 ((uint32_t)0x40000000) /*!< ADC OFFSET4_CH bit 4 */
mbed_official 155:8435094ec241 3012
mbed_official 155:8435094ec241 3013 #define ADC_OFR4_OFFSET4_EN ((uint32_t)0x80000000) /*!< ADC offset 4 enable */
mbed_official 155:8435094ec241 3014
mbed_official 155:8435094ec241 3015 /******************** Bit definition for ADC_JDR1 register ********************/
mbed_official 155:8435094ec241 3016 #define ADC_JDR1_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 155:8435094ec241 3017 #define ADC_JDR1_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 155:8435094ec241 3018 #define ADC_JDR1_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 155:8435094ec241 3019 #define ADC_JDR1_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 155:8435094ec241 3020 #define ADC_JDR1_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 155:8435094ec241 3021 #define ADC_JDR1_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 155:8435094ec241 3022 #define ADC_JDR1_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 155:8435094ec241 3023 #define ADC_JDR1_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 155:8435094ec241 3024 #define ADC_JDR1_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 155:8435094ec241 3025 #define ADC_JDR1_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 155:8435094ec241 3026 #define ADC_JDR1_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 155:8435094ec241 3027 #define ADC_JDR1_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 155:8435094ec241 3028 #define ADC_JDR1_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 155:8435094ec241 3029 #define ADC_JDR1_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 155:8435094ec241 3030 #define ADC_JDR1_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 155:8435094ec241 3031 #define ADC_JDR1_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 155:8435094ec241 3032 #define ADC_JDR1_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 155:8435094ec241 3033
mbed_official 155:8435094ec241 3034 /******************** Bit definition for ADC_JDR2 register ********************/
mbed_official 155:8435094ec241 3035 #define ADC_JDR2_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 155:8435094ec241 3036 #define ADC_JDR2_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 155:8435094ec241 3037 #define ADC_JDR2_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 155:8435094ec241 3038 #define ADC_JDR2_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 155:8435094ec241 3039 #define ADC_JDR2_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 155:8435094ec241 3040 #define ADC_JDR2_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 155:8435094ec241 3041 #define ADC_JDR2_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 155:8435094ec241 3042 #define ADC_JDR2_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 155:8435094ec241 3043 #define ADC_JDR2_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 155:8435094ec241 3044 #define ADC_JDR2_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 155:8435094ec241 3045 #define ADC_JDR2_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 155:8435094ec241 3046 #define ADC_JDR2_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 155:8435094ec241 3047 #define ADC_JDR2_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 155:8435094ec241 3048 #define ADC_JDR2_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 155:8435094ec241 3049 #define ADC_JDR2_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 155:8435094ec241 3050 #define ADC_JDR2_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 155:8435094ec241 3051 #define ADC_JDR2_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 155:8435094ec241 3052
mbed_official 155:8435094ec241 3053 /******************** Bit definition for ADC_JDR3 register ********************/
mbed_official 155:8435094ec241 3054 #define ADC_JDR3_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 155:8435094ec241 3055 #define ADC_JDR3_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 155:8435094ec241 3056 #define ADC_JDR3_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 155:8435094ec241 3057 #define ADC_JDR3_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 155:8435094ec241 3058 #define ADC_JDR3_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 155:8435094ec241 3059 #define ADC_JDR3_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 155:8435094ec241 3060 #define ADC_JDR3_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 155:8435094ec241 3061 #define ADC_JDR3_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 155:8435094ec241 3062 #define ADC_JDR3_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 155:8435094ec241 3063 #define ADC_JDR3_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 155:8435094ec241 3064 #define ADC_JDR3_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 155:8435094ec241 3065 #define ADC_JDR3_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 155:8435094ec241 3066 #define ADC_JDR3_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 155:8435094ec241 3067 #define ADC_JDR3_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 155:8435094ec241 3068 #define ADC_JDR3_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 155:8435094ec241 3069 #define ADC_JDR3_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 155:8435094ec241 3070 #define ADC_JDR3_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 155:8435094ec241 3071
mbed_official 155:8435094ec241 3072 /******************** Bit definition for ADC_JDR4 register ********************/
mbed_official 155:8435094ec241 3073 #define ADC_JDR4_JDATA ((uint32_t)0x0000FFFF) /*!< ADC Injected DATA */
mbed_official 155:8435094ec241 3074 #define ADC_JDR4_JDATA_0 ((uint32_t)0x00000001) /*!< ADC JDATA bit 0 */
mbed_official 155:8435094ec241 3075 #define ADC_JDR4_JDATA_1 ((uint32_t)0x00000002) /*!< ADC JDATA bit 1 */
mbed_official 155:8435094ec241 3076 #define ADC_JDR4_JDATA_2 ((uint32_t)0x00000004) /*!< ADC JDATA bit 2 */
mbed_official 155:8435094ec241 3077 #define ADC_JDR4_JDATA_3 ((uint32_t)0x00000008) /*!< ADC JDATA bit 3 */
mbed_official 155:8435094ec241 3078 #define ADC_JDR4_JDATA_4 ((uint32_t)0x00000010) /*!< ADC JDATA bit 4 */
mbed_official 155:8435094ec241 3079 #define ADC_JDR4_JDATA_5 ((uint32_t)0x00000020) /*!< ADC JDATA bit 5 */
mbed_official 155:8435094ec241 3080 #define ADC_JDR4_JDATA_6 ((uint32_t)0x00000040) /*!< ADC JDATA bit 6 */
mbed_official 155:8435094ec241 3081 #define ADC_JDR4_JDATA_7 ((uint32_t)0x00000080) /*!< ADC JDATA bit 7 */
mbed_official 155:8435094ec241 3082 #define ADC_JDR4_JDATA_8 ((uint32_t)0x00000100) /*!< ADC JDATA bit 8 */
mbed_official 155:8435094ec241 3083 #define ADC_JDR4_JDATA_9 ((uint32_t)0x00000200) /*!< ADC JDATA bit 9 */
mbed_official 155:8435094ec241 3084 #define ADC_JDR4_JDATA_10 ((uint32_t)0x00000400) /*!< ADC JDATA bit 10 */
mbed_official 155:8435094ec241 3085 #define ADC_JDR4_JDATA_11 ((uint32_t)0x00000800) /*!< ADC JDATA bit 11 */
mbed_official 155:8435094ec241 3086 #define ADC_JDR4_JDATA_12 ((uint32_t)0x00001000) /*!< ADC JDATA bit 12 */
mbed_official 155:8435094ec241 3087 #define ADC_JDR4_JDATA_13 ((uint32_t)0x00002000) /*!< ADC JDATA bit 13 */
mbed_official 155:8435094ec241 3088 #define ADC_JDR4_JDATA_14 ((uint32_t)0x00004000) /*!< ADC JDATA bit 14 */
mbed_official 155:8435094ec241 3089 #define ADC_JDR4_JDATA_15 ((uint32_t)0x00008000) /*!< ADC JDATA bit 15 */
mbed_official 155:8435094ec241 3090
mbed_official 155:8435094ec241 3091 /******************** Bit definition for ADC_AWD2CR register ********************/
mbed_official 155:8435094ec241 3092 #define ADC_AWD2CR_AWD2CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 155:8435094ec241 3093 #define ADC_AWD2CR_AWD2CH_0 ((uint32_t)0x00000002) /*!< ADC AWD2CH bit 0 */
mbed_official 155:8435094ec241 3094 #define ADC_AWD2CR_AWD2CH_1 ((uint32_t)0x00000004) /*!< ADC AWD2CH bit 1 */
mbed_official 155:8435094ec241 3095 #define ADC_AWD2CR_AWD2CH_2 ((uint32_t)0x00000008) /*!< ADC AWD2CH bit 2 */
mbed_official 155:8435094ec241 3096 #define ADC_AWD2CR_AWD2CH_3 ((uint32_t)0x00000010) /*!< ADC AWD2CH bit 3 */
mbed_official 155:8435094ec241 3097 #define ADC_AWD2CR_AWD2CH_4 ((uint32_t)0x00000020) /*!< ADC AWD2CH bit 4 */
mbed_official 155:8435094ec241 3098 #define ADC_AWD2CR_AWD2CH_5 ((uint32_t)0x00000040) /*!< ADC AWD2CH bit 5 */
mbed_official 155:8435094ec241 3099 #define ADC_AWD2CR_AWD2CH_6 ((uint32_t)0x00000080) /*!< ADC AWD2CH bit 6 */
mbed_official 155:8435094ec241 3100 #define ADC_AWD2CR_AWD2CH_7 ((uint32_t)0x00000100) /*!< ADC AWD2CH bit 7 */
mbed_official 155:8435094ec241 3101 #define ADC_AWD2CR_AWD2CH_8 ((uint32_t)0x00000200) /*!< ADC AWD2CH bit 8 */
mbed_official 155:8435094ec241 3102 #define ADC_AWD2CR_AWD2CH_9 ((uint32_t)0x00000400) /*!< ADC AWD2CH bit 9 */
mbed_official 155:8435094ec241 3103 #define ADC_AWD2CR_AWD2CH_10 ((uint32_t)0x00000800) /*!< ADC AWD2CH bit 10 */
mbed_official 155:8435094ec241 3104 #define ADC_AWD2CR_AWD2CH_11 ((uint32_t)0x00001000) /*!< ADC AWD2CH bit 11 */
mbed_official 155:8435094ec241 3105 #define ADC_AWD2CR_AWD2CH_12 ((uint32_t)0x00002000) /*!< ADC AWD2CH bit 12 */
mbed_official 155:8435094ec241 3106 #define ADC_AWD2CR_AWD2CH_13 ((uint32_t)0x00004000) /*!< ADC AWD2CH bit 13 */
mbed_official 155:8435094ec241 3107 #define ADC_AWD2CR_AWD2CH_14 ((uint32_t)0x00008000) /*!< ADC AWD2CH bit 14 */
mbed_official 155:8435094ec241 3108 #define ADC_AWD2CR_AWD2CH_15 ((uint32_t)0x00010000) /*!< ADC AWD2CH bit 15 */
mbed_official 155:8435094ec241 3109 #define ADC_AWD2CR_AWD2CH_16 ((uint32_t)0x00020000) /*!< ADC AWD2CH bit 16 */
mbed_official 155:8435094ec241 3110 #define ADC_AWD2CR_AWD2CH_17 ((uint32_t)0x00030000) /*!< ADC AWD2CH bit 17 */
mbed_official 155:8435094ec241 3111
mbed_official 155:8435094ec241 3112 /******************** Bit definition for ADC_AWD3CR register ********************/
mbed_official 155:8435094ec241 3113 #define ADC_AWD3CR_AWD3CH ((uint32_t)0x0007FFFE) /*!< ADC Analog watchdog 2 channel selection */
mbed_official 155:8435094ec241 3114 #define ADC_AWD3CR_AWD3CH_0 ((uint32_t)0x00000002) /*!< ADC AWD3CH bit 0 */
mbed_official 155:8435094ec241 3115 #define ADC_AWD3CR_AWD3CH_1 ((uint32_t)0x00000004) /*!< ADC AWD3CH bit 1 */
mbed_official 155:8435094ec241 3116 #define ADC_AWD3CR_AWD3CH_2 ((uint32_t)0x00000008) /*!< ADC AWD3CH bit 2 */
mbed_official 155:8435094ec241 3117 #define ADC_AWD3CR_AWD3CH_3 ((uint32_t)0x00000010) /*!< ADC AWD3CH bit 3 */
mbed_official 155:8435094ec241 3118 #define ADC_AWD3CR_AWD3CH_4 ((uint32_t)0x00000020) /*!< ADC AWD3CH bit 4 */
mbed_official 155:8435094ec241 3119 #define ADC_AWD3CR_AWD3CH_5 ((uint32_t)0x00000040) /*!< ADC AWD3CH bit 5 */
mbed_official 155:8435094ec241 3120 #define ADC_AWD3CR_AWD3CH_6 ((uint32_t)0x00000080) /*!< ADC AWD3CH bit 6 */
mbed_official 155:8435094ec241 3121 #define ADC_AWD3CR_AWD3CH_7 ((uint32_t)0x00000100) /*!< ADC AWD3CH bit 7 */
mbed_official 155:8435094ec241 3122 #define ADC_AWD3CR_AWD3CH_8 ((uint32_t)0x00000200) /*!< ADC AWD3CH bit 8 */
mbed_official 155:8435094ec241 3123 #define ADC_AWD3CR_AWD3CH_9 ((uint32_t)0x00000400) /*!< ADC AWD3CH bit 9 */
mbed_official 155:8435094ec241 3124 #define ADC_AWD3CR_AWD3CH_10 ((uint32_t)0x00000800) /*!< ADC AWD3CH bit 10 */
mbed_official 155:8435094ec241 3125 #define ADC_AWD3CR_AWD3CH_11 ((uint32_t)0x00001000) /*!< ADC AWD3CH bit 11 */
mbed_official 155:8435094ec241 3126 #define ADC_AWD3CR_AWD3CH_12 ((uint32_t)0x00002000) /*!< ADC AWD3CH bit 12 */
mbed_official 155:8435094ec241 3127 #define ADC_AWD3CR_AWD3CH_13 ((uint32_t)0x00004000) /*!< ADC AWD3CH bit 13 */
mbed_official 155:8435094ec241 3128 #define ADC_AWD3CR_AWD3CH_14 ((uint32_t)0x00008000) /*!< ADC AWD3CH bit 14 */
mbed_official 155:8435094ec241 3129 #define ADC_AWD3CR_AWD3CH_15 ((uint32_t)0x00010000) /*!< ADC AWD3CH bit 15 */
mbed_official 155:8435094ec241 3130 #define ADC_AWD3CR_AWD3CH_16 ((uint32_t)0x00020000) /*!< ADC AWD3CH bit 16 */
mbed_official 155:8435094ec241 3131 #define ADC_AWD3CR_AWD3CH_17 ((uint32_t)0x00030000) /*!< ADC AWD3CH bit 17 */
mbed_official 155:8435094ec241 3132
mbed_official 155:8435094ec241 3133 /******************** Bit definition for ADC_DIFSEL register ********************/
mbed_official 155:8435094ec241 3134 #define ADC_DIFSEL_DIFSEL ((uint32_t)0x0007FFFE) /*!< ADC differential modes for channels 1 to 18 */
mbed_official 155:8435094ec241 3135 #define ADC_DIFSEL_DIFSEL_0 ((uint32_t)0x00000002) /*!< ADC DIFSEL bit 0 */
mbed_official 155:8435094ec241 3136 #define ADC_DIFSEL_DIFSEL_1 ((uint32_t)0x00000004) /*!< ADC DIFSEL bit 1 */
mbed_official 155:8435094ec241 3137 #define ADC_DIFSEL_DIFSEL_2 ((uint32_t)0x00000008) /*!< ADC DIFSEL bit 2 */
mbed_official 155:8435094ec241 3138 #define ADC_DIFSEL_DIFSEL_3 ((uint32_t)0x00000010) /*!< ADC DIFSEL bit 3 */
mbed_official 155:8435094ec241 3139 #define ADC_DIFSEL_DIFSEL_4 ((uint32_t)0x00000020) /*!< ADC DIFSEL bit 4 */
mbed_official 155:8435094ec241 3140 #define ADC_DIFSEL_DIFSEL_5 ((uint32_t)0x00000040) /*!< ADC DIFSEL bit 5 */
mbed_official 155:8435094ec241 3141 #define ADC_DIFSEL_DIFSEL_6 ((uint32_t)0x00000080) /*!< ADC DIFSEL bit 6 */
mbed_official 155:8435094ec241 3142 #define ADC_DIFSEL_DIFSEL_7 ((uint32_t)0x00000100) /*!< ADC DIFSEL bit 7 */
mbed_official 155:8435094ec241 3143 #define ADC_DIFSEL_DIFSEL_8 ((uint32_t)0x00000200) /*!< ADC DIFSEL bit 8 */
mbed_official 155:8435094ec241 3144 #define ADC_DIFSEL_DIFSEL_9 ((uint32_t)0x00000400) /*!< ADC DIFSEL bit 9 */
mbed_official 155:8435094ec241 3145 #define ADC_DIFSEL_DIFSEL_10 ((uint32_t)0x00000800) /*!< ADC DIFSEL bit 10 */
mbed_official 155:8435094ec241 3146 #define ADC_DIFSEL_DIFSEL_11 ((uint32_t)0x00001000) /*!< ADC DIFSEL bit 11 */
mbed_official 155:8435094ec241 3147 #define ADC_DIFSEL_DIFSEL_12 ((uint32_t)0x00002000) /*!< ADC DIFSEL bit 12 */
mbed_official 155:8435094ec241 3148 #define ADC_DIFSEL_DIFSEL_13 ((uint32_t)0x00004000) /*!< ADC DIFSEL bit 13 */
mbed_official 155:8435094ec241 3149 #define ADC_DIFSEL_DIFSEL_14 ((uint32_t)0x00008000) /*!< ADC DIFSEL bit 14 */
mbed_official 155:8435094ec241 3150 #define ADC_DIFSEL_DIFSEL_15 ((uint32_t)0x00010000) /*!< ADC DIFSEL bit 15 */
mbed_official 155:8435094ec241 3151 #define ADC_DIFSEL_DIFSEL_16 ((uint32_t)0x00020000) /*!< ADC DIFSEL bit 16 */
mbed_official 155:8435094ec241 3152 #define ADC_DIFSEL_DIFSEL_17 ((uint32_t)0x00030000) /*!< ADC DIFSEL bit 17 */
mbed_official 155:8435094ec241 3153
mbed_official 155:8435094ec241 3154 /******************** Bit definition for ADC_CALFACT register ********************/
mbed_official 155:8435094ec241 3155 #define ADC_CALFACT_CALFACT_S ((uint32_t)0x0000007F) /*!< ADC calibration factors in single-ended mode */
mbed_official 155:8435094ec241 3156 #define ADC_CALFACT_CALFACT_S_0 ((uint32_t)0x00000001) /*!< ADC CALFACT_S bit 0 */
mbed_official 155:8435094ec241 3157 #define ADC_CALFACT_CALFACT_S_1 ((uint32_t)0x00000002) /*!< ADC CALFACT_S bit 1 */
mbed_official 155:8435094ec241 3158 #define ADC_CALFACT_CALFACT_S_2 ((uint32_t)0x00000004) /*!< ADC CALFACT_S bit 2 */
mbed_official 155:8435094ec241 3159 #define ADC_CALFACT_CALFACT_S_3 ((uint32_t)0x00000008) /*!< ADC CALFACT_S bit 3 */
mbed_official 155:8435094ec241 3160 #define ADC_CALFACT_CALFACT_S_4 ((uint32_t)0x00000010) /*!< ADC CALFACT_S bit 4 */
mbed_official 155:8435094ec241 3161 #define ADC_CALFACT_CALFACT_S_5 ((uint32_t)0x00000020) /*!< ADC CALFACT_S bit 5 */
mbed_official 155:8435094ec241 3162 #define ADC_CALFACT_CALFACT_S_6 ((uint32_t)0x00000040) /*!< ADC CALFACT_S bit 6 */
mbed_official 155:8435094ec241 3163 #define ADC_CALFACT_CALFACT_D ((uint32_t)0x007F0000) /*!< ADC calibration factors in differential mode */
mbed_official 155:8435094ec241 3164 #define ADC_CALFACT_CALFACT_D_0 ((uint32_t)0x00010000) /*!< ADC CALFACT_D bit 0 */
mbed_official 155:8435094ec241 3165 #define ADC_CALFACT_CALFACT_D_1 ((uint32_t)0x00020000) /*!< ADC CALFACT_D bit 1 */
mbed_official 155:8435094ec241 3166 #define ADC_CALFACT_CALFACT_D_2 ((uint32_t)0x00040000) /*!< ADC CALFACT_D bit 2 */
mbed_official 155:8435094ec241 3167 #define ADC_CALFACT_CALFACT_D_3 ((uint32_t)0x00080000) /*!< ADC CALFACT_D bit 3 */
mbed_official 155:8435094ec241 3168 #define ADC_CALFACT_CALFACT_D_4 ((uint32_t)0x00100000) /*!< ADC CALFACT_D bit 4 */
mbed_official 155:8435094ec241 3169 #define ADC_CALFACT_CALFACT_D_5 ((uint32_t)0x00200000) /*!< ADC CALFACT_D bit 5 */
mbed_official 155:8435094ec241 3170 #define ADC_CALFACT_CALFACT_D_6 ((uint32_t)0x00400000) /*!< ADC CALFACT_D bit 6 */
mbed_official 155:8435094ec241 3171
mbed_official 155:8435094ec241 3172 /************************* ADC Common registers *****************************/
mbed_official 155:8435094ec241 3173 /******************** Bit definition for ADC12_CSR register ********************/
mbed_official 155:8435094ec241 3174 #define ADC12_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
mbed_official 155:8435094ec241 3175 #define ADC12_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
mbed_official 155:8435094ec241 3176 #define ADC12_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
mbed_official 155:8435094ec241 3177 #define ADC12_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
mbed_official 155:8435094ec241 3178 #define ADC12_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
mbed_official 155:8435094ec241 3179 #define ADC12_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
mbed_official 155:8435094ec241 3180 #define ADC12_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
mbed_official 155:8435094ec241 3181 #define ADC12_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
mbed_official 155:8435094ec241 3182 #define ADC12_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
mbed_official 155:8435094ec241 3183 #define ADC12_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
mbed_official 155:8435094ec241 3184 #define ADC12_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
mbed_official 155:8435094ec241 3185 #define ADC12_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
mbed_official 155:8435094ec241 3186 #define ADC12_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
mbed_official 155:8435094ec241 3187 #define ADC12_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
mbed_official 155:8435094ec241 3188 #define ADC12_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
mbed_official 155:8435094ec241 3189 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
mbed_official 155:8435094ec241 3190 #define ADC12_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
mbed_official 155:8435094ec241 3191 #define ADC12_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
mbed_official 155:8435094ec241 3192 #define ADC12_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
mbed_official 155:8435094ec241 3193 #define ADC12_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
mbed_official 155:8435094ec241 3194 #define ADC12_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
mbed_official 155:8435094ec241 3195 #define ADC12_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
mbed_official 155:8435094ec241 3196
mbed_official 155:8435094ec241 3197 /******************** Bit definition for ADC34_CSR register ********************/
mbed_official 155:8435094ec241 3198 #define ADC34_CSR_ADRDY_MST ((uint32_t)0x00000001) /*!< Master ADC ready */
mbed_official 155:8435094ec241 3199 #define ADC34_CSR_ADRDY_EOSMP_MST ((uint32_t)0x00000002) /*!< End of sampling phase flag of the master ADC */
mbed_official 155:8435094ec241 3200 #define ADC34_CSR_ADRDY_EOC_MST ((uint32_t)0x00000004) /*!< End of regular conversion of the master ADC */
mbed_official 155:8435094ec241 3201 #define ADC34_CSR_ADRDY_EOS_MST ((uint32_t)0x00000008) /*!< End of regular sequence flag of the master ADC */
mbed_official 155:8435094ec241 3202 #define ADC34_CSR_ADRDY_OVR_MST ((uint32_t)0x00000010) /*!< Overrun flag of the master ADC */
mbed_official 155:8435094ec241 3203 #define ADC34_CSR_ADRDY_JEOC_MST ((uint32_t)0x00000020) /*!< End of injected conversion of the master ADC */
mbed_official 155:8435094ec241 3204 #define ADC34_CSR_ADRDY_JEOS_MST ((uint32_t)0x00000040) /*!< End of injected sequence flag of the master ADC */
mbed_official 155:8435094ec241 3205 #define ADC34_CSR_AWD1_MST ((uint32_t)0x00000080) /*!< Analog watchdog 1 flag of the master ADC */
mbed_official 155:8435094ec241 3206 #define ADC34_CSR_AWD2_MST ((uint32_t)0x00000100) /*!< Analog watchdog 2 flag of the master ADC */
mbed_official 155:8435094ec241 3207 #define ADC34_CSR_AWD3_MST ((uint32_t)0x00000200) /*!< Analog watchdog 3 flag of the master ADC */
mbed_official 155:8435094ec241 3208 #define ADC34_CSR_JQOVF_MST ((uint32_t)0x00000400) /*!< Injected context queue overflow flag of the master ADC */
mbed_official 155:8435094ec241 3209 #define ADC34_CSR_ADRDY_SLV ((uint32_t)0x00010000) /*!< Slave ADC ready */
mbed_official 155:8435094ec241 3210 #define ADC34_CSR_ADRDY_EOSMP_SLV ((uint32_t)0x00020000) /*!< End of sampling phase flag of the slave ADC */
mbed_official 155:8435094ec241 3211 #define ADC34_CSR_ADRDY_EOC_SLV ((uint32_t)0x00040000) /*!< End of regular conversion of the slave ADC */
mbed_official 155:8435094ec241 3212 #define ADC34_CSR_ADRDY_EOS_SLV ((uint32_t)0x00080000) /*!< End of regular sequence flag of the slave ADC */
mbed_official 155:8435094ec241 3213 #define ADC12_CSR_ADRDY_OVR_SLV ((uint32_t)0x00100000) /*!< Overrun flag of the slave ADC */
mbed_official 155:8435094ec241 3214 #define ADC34_CSR_ADRDY_JEOC_SLV ((uint32_t)0x00200000) /*!< End of injected conversion of the slave ADC */
mbed_official 155:8435094ec241 3215 #define ADC34_CSR_ADRDY_JEOS_SLV ((uint32_t)0x00400000) /*!< End of injected sequence flag of the slave ADC */
mbed_official 155:8435094ec241 3216 #define ADC34_CSR_AWD1_SLV ((uint32_t)0x00800000) /*!< Analog watchdog 1 flag of the slave ADC */
mbed_official 155:8435094ec241 3217 #define ADC34_CSR_AWD2_SLV ((uint32_t)0x01000000) /*!< Analog watchdog 2 flag of the slave ADC */
mbed_official 155:8435094ec241 3218 #define ADC34_CSR_AWD3_SLV ((uint32_t)0x02000000) /*!< Analog watchdog 3 flag of the slave ADC */
mbed_official 155:8435094ec241 3219 #define ADC34_CSR_JQOVF_SLV ((uint32_t)0x04000000) /*!< Injected context queue overflow flag of the slave ADC */
mbed_official 155:8435094ec241 3220
mbed_official 155:8435094ec241 3221 /******************** Bit definition for ADC_CCR register ********************/
mbed_official 155:8435094ec241 3222 #define ADC12_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
mbed_official 155:8435094ec241 3223 #define ADC12_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
mbed_official 155:8435094ec241 3224 #define ADC12_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
mbed_official 155:8435094ec241 3225 #define ADC12_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
mbed_official 155:8435094ec241 3226 #define ADC12_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
mbed_official 155:8435094ec241 3227 #define ADC12_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
mbed_official 155:8435094ec241 3228 #define ADC12_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
mbed_official 155:8435094ec241 3229 #define ADC12_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
mbed_official 155:8435094ec241 3230 #define ADC12_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
mbed_official 155:8435094ec241 3231 #define ADC12_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
mbed_official 155:8435094ec241 3232 #define ADC12_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
mbed_official 155:8435094ec241 3233 #define ADC12_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
mbed_official 155:8435094ec241 3234 #define ADC12_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
mbed_official 155:8435094ec241 3235 #define ADC12_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
mbed_official 155:8435094ec241 3236 #define ADC12_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
mbed_official 155:8435094ec241 3237 #define ADC12_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
mbed_official 155:8435094ec241 3238 #define ADC12_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
mbed_official 155:8435094ec241 3239 #define ADC12_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
mbed_official 155:8435094ec241 3240 #define ADC12_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
mbed_official 155:8435094ec241 3241 #define ADC12_CCR_TSEN ((uint32_t)0x00800000) /*!< Temperature sensor enable */
mbed_official 155:8435094ec241 3242 #define ADC12_CCR_VBATEN ((uint32_t)0x01000000) /*!< VBAT enable */
mbed_official 155:8435094ec241 3243
mbed_official 155:8435094ec241 3244 /******************** Bit definition for ADC_CCR register ********************/
mbed_official 155:8435094ec241 3245 #define ADC34_CCR_MULTI ((uint32_t)0x0000001F) /*!< Multi ADC mode selection */
mbed_official 155:8435094ec241 3246 #define ADC34_CCR_MULTI_0 ((uint32_t)0x00000001) /*!< MULTI bit 0 */
mbed_official 155:8435094ec241 3247 #define ADC34_CCR_MULTI_1 ((uint32_t)0x00000002) /*!< MULTI bit 1 */
mbed_official 155:8435094ec241 3248 #define ADC34_CCR_MULTI_2 ((uint32_t)0x00000004) /*!< MULTI bit 2 */
mbed_official 155:8435094ec241 3249 #define ADC34_CCR_MULTI_3 ((uint32_t)0x00000008) /*!< MULTI bit 3 */
mbed_official 155:8435094ec241 3250 #define ADC34_CCR_MULTI_4 ((uint32_t)0x00000010) /*!< MULTI bit 4 */
mbed_official 155:8435094ec241 3251
mbed_official 155:8435094ec241 3252 #define ADC34_CCR_DELAY ((uint32_t)0x00000F00) /*!< Delay between 2 sampling phases */
mbed_official 155:8435094ec241 3253 #define ADC34_CCR_DELAY_0 ((uint32_t)0x00000100) /*!< DELAY bit 0 */
mbed_official 155:8435094ec241 3254 #define ADC34_CCR_DELAY_1 ((uint32_t)0x00000200) /*!< DELAY bit 1 */
mbed_official 155:8435094ec241 3255 #define ADC34_CCR_DELAY_2 ((uint32_t)0x00000400) /*!< DELAY bit 2 */
mbed_official 155:8435094ec241 3256 #define ADC34_CCR_DELAY_3 ((uint32_t)0x00000800) /*!< DELAY bit 3 */
mbed_official 155:8435094ec241 3257
mbed_official 155:8435094ec241 3258 #define ADC34_CCR_DMACFG ((uint32_t)0x00002000) /*!< DMA configuration for multi-ADC mode */
mbed_official 155:8435094ec241 3259 #define ADC34_CCR_MDMA ((uint32_t)0x0000C000) /*!< DMA mode for multi-ADC mode */
mbed_official 155:8435094ec241 3260 #define ADC34_CCR_MDMA_0 ((uint32_t)0x00004000) /*!< MDMA bit 0 */
mbed_official 155:8435094ec241 3261 #define ADC34_CCR_MDMA_1 ((uint32_t)0x00008000) /*!< MDMA bit 1 */
mbed_official 155:8435094ec241 3262
mbed_official 155:8435094ec241 3263 #define ADC34_CCR_CKMODE ((uint32_t)0x00030000) /*!< ADC clock mode */
mbed_official 155:8435094ec241 3264 #define ADC34_CCR_CKMODE_0 ((uint32_t)0x00010000) /*!< CKMODE bit 0 */
mbed_official 155:8435094ec241 3265 #define ADC34_CCR_CKMODE_1 ((uint32_t)0x00020000) /*!< CKMODE bit 1 */
mbed_official 155:8435094ec241 3266
mbed_official 155:8435094ec241 3267 #define ADC34_CCR_VREFEN ((uint32_t)0x00400000) /*!< VREFINT enable */
mbed_official 155:8435094ec241 3268
mbed_official 155:8435094ec241 3269 /******************** Bit definition for ADC_CDR register ********************/
mbed_official 155:8435094ec241 3270 #define ADC12_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
mbed_official 155:8435094ec241 3271 #define ADC12_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
mbed_official 155:8435094ec241 3272 #define ADC12_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
mbed_official 155:8435094ec241 3273 #define ADC12_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
mbed_official 155:8435094ec241 3274 #define ADC12_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
mbed_official 155:8435094ec241 3275 #define ADC12_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
mbed_official 155:8435094ec241 3276 #define ADC12_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
mbed_official 155:8435094ec241 3277 #define ADC12_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
mbed_official 155:8435094ec241 3278 #define ADC12_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
mbed_official 155:8435094ec241 3279 #define ADC12_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
mbed_official 155:8435094ec241 3280 #define ADC12_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
mbed_official 155:8435094ec241 3281 #define ADC12_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
mbed_official 155:8435094ec241 3282 #define ADC12_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
mbed_official 155:8435094ec241 3283 #define ADC12_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
mbed_official 155:8435094ec241 3284 #define ADC12_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
mbed_official 155:8435094ec241 3285 #define ADC12_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
mbed_official 155:8435094ec241 3286 #define ADC12_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
mbed_official 155:8435094ec241 3287
mbed_official 155:8435094ec241 3288 #define ADC12_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
mbed_official 155:8435094ec241 3289 #define ADC12_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
mbed_official 155:8435094ec241 3290 #define ADC12_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
mbed_official 155:8435094ec241 3291 #define ADC12_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
mbed_official 155:8435094ec241 3292 #define ADC12_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
mbed_official 155:8435094ec241 3293 #define ADC12_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
mbed_official 155:8435094ec241 3294 #define ADC12_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
mbed_official 155:8435094ec241 3295 #define ADC12_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
mbed_official 155:8435094ec241 3296 #define ADC12_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
mbed_official 155:8435094ec241 3297 #define ADC12_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
mbed_official 155:8435094ec241 3298 #define ADC12_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
mbed_official 155:8435094ec241 3299 #define ADC12_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
mbed_official 155:8435094ec241 3300 #define ADC12_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
mbed_official 155:8435094ec241 3301 #define ADC12_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
mbed_official 155:8435094ec241 3302 #define ADC12_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
mbed_official 155:8435094ec241 3303 #define ADC12_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
mbed_official 155:8435094ec241 3304 #define ADC12_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
mbed_official 155:8435094ec241 3305
mbed_official 155:8435094ec241 3306 /******************** Bit definition for ADC_CDR register ********************/
mbed_official 155:8435094ec241 3307 #define ADC34_CDR_RDATA_MST ((uint32_t)0x0000FFFF) /*!< Regular Data of the master ADC */
mbed_official 155:8435094ec241 3308 #define ADC34_CDR_RDATA_MST_0 ((uint32_t)0x00000001) /*!< RDATA_MST bit 0 */
mbed_official 155:8435094ec241 3309 #define ADC34_CDR_RDATA_MST_1 ((uint32_t)0x00000002) /*!< RDATA_MST bit 1 */
mbed_official 155:8435094ec241 3310 #define ADC34_CDR_RDATA_MST_2 ((uint32_t)0x00000004) /*!< RDATA_MST bit 2 */
mbed_official 155:8435094ec241 3311 #define ADC34_CDR_RDATA_MST_3 ((uint32_t)0x00000008) /*!< RDATA_MST bit 3 */
mbed_official 155:8435094ec241 3312 #define ADC34_CDR_RDATA_MST_4 ((uint32_t)0x00000010) /*!< RDATA_MST bit 4 */
mbed_official 155:8435094ec241 3313 #define ADC34_CDR_RDATA_MST_5 ((uint32_t)0x00000020) /*!< RDATA_MST bit 5 */
mbed_official 155:8435094ec241 3314 #define ADC34_CDR_RDATA_MST_6 ((uint32_t)0x00000040) /*!< RDATA_MST bit 6 */
mbed_official 155:8435094ec241 3315 #define ADC34_CDR_RDATA_MST_7 ((uint32_t)0x00000080) /*!< RDATA_MST bit 7 */
mbed_official 155:8435094ec241 3316 #define ADC34_CDR_RDATA_MST_8 ((uint32_t)0x00000100) /*!< RDATA_MST bit 8 */
mbed_official 155:8435094ec241 3317 #define ADC34_CDR_RDATA_MST_9 ((uint32_t)0x00000200) /*!< RDATA_MST bit 9 */
mbed_official 155:8435094ec241 3318 #define ADC34_CDR_RDATA_MST_10 ((uint32_t)0x00000400) /*!< RDATA_MST bit 10 */
mbed_official 155:8435094ec241 3319 #define ADC34_CDR_RDATA_MST_11 ((uint32_t)0x00000800) /*!< RDATA_MST bit 11 */
mbed_official 155:8435094ec241 3320 #define ADC34_CDR_RDATA_MST_12 ((uint32_t)0x00001000) /*!< RDATA_MST bit 12 */
mbed_official 155:8435094ec241 3321 #define ADC34_CDR_RDATA_MST_13 ((uint32_t)0x00002000) /*!< RDATA_MST bit 13 */
mbed_official 155:8435094ec241 3322 #define ADC34_CDR_RDATA_MST_14 ((uint32_t)0x00004000) /*!< RDATA_MST bit 14 */
mbed_official 155:8435094ec241 3323 #define ADC34_CDR_RDATA_MST_15 ((uint32_t)0x00008000) /*!< RDATA_MST bit 15 */
mbed_official 155:8435094ec241 3324
mbed_official 155:8435094ec241 3325 #define ADC34_CDR_RDATA_SLV ((uint32_t)0xFFFF0000) /*!< Regular Data of the master ADC */
mbed_official 155:8435094ec241 3326 #define ADC34_CDR_RDATA_SLV_0 ((uint32_t)0x00010000) /*!< RDATA_SLV bit 0 */
mbed_official 155:8435094ec241 3327 #define ADC34_CDR_RDATA_SLV_1 ((uint32_t)0x00020000) /*!< RDATA_SLV bit 1 */
mbed_official 155:8435094ec241 3328 #define ADC34_CDR_RDATA_SLV_2 ((uint32_t)0x00040000) /*!< RDATA_SLV bit 2 */
mbed_official 155:8435094ec241 3329 #define ADC34_CDR_RDATA_SLV_3 ((uint32_t)0x00080000) /*!< RDATA_SLV bit 3 */
mbed_official 155:8435094ec241 3330 #define ADC34_CDR_RDATA_SLV_4 ((uint32_t)0x00100000) /*!< RDATA_SLV bit 4 */
mbed_official 155:8435094ec241 3331 #define ADC34_CDR_RDATA_SLV_5 ((uint32_t)0x00200000) /*!< RDATA_SLV bit 5 */
mbed_official 155:8435094ec241 3332 #define ADC34_CDR_RDATA_SLV_6 ((uint32_t)0x00400000) /*!< RDATA_SLV bit 6 */
mbed_official 155:8435094ec241 3333 #define ADC34_CDR_RDATA_SLV_7 ((uint32_t)0x00800000) /*!< RDATA_SLV bit 7 */
mbed_official 155:8435094ec241 3334 #define ADC34_CDR_RDATA_SLV_8 ((uint32_t)0x01000000) /*!< RDATA_SLV bit 8 */
mbed_official 155:8435094ec241 3335 #define ADC34_CDR_RDATA_SLV_9 ((uint32_t)0x02000000) /*!< RDATA_SLV bit 9 */
mbed_official 155:8435094ec241 3336 #define ADC34_CDR_RDATA_SLV_10 ((uint32_t)0x04000000) /*!< RDATA_SLV bit 10 */
mbed_official 155:8435094ec241 3337 #define ADC34_CDR_RDATA_SLV_11 ((uint32_t)0x08000000) /*!< RDATA_SLV bit 11 */
mbed_official 155:8435094ec241 3338 #define ADC34_CDR_RDATA_SLV_12 ((uint32_t)0x10000000) /*!< RDATA_SLV bit 12 */
mbed_official 155:8435094ec241 3339 #define ADC34_CDR_RDATA_SLV_13 ((uint32_t)0x20000000) /*!< RDATA_SLV bit 13 */
mbed_official 155:8435094ec241 3340 #define ADC34_CDR_RDATA_SLV_14 ((uint32_t)0x40000000) /*!< RDATA_SLV bit 14 */
mbed_official 155:8435094ec241 3341 #define ADC34_CDR_RDATA_SLV_15 ((uint32_t)0x80000000) /*!< RDATA_SLV bit 15 */
mbed_official 155:8435094ec241 3342
mbed_official 155:8435094ec241 3343 /******************************************************************************/
mbed_official 155:8435094ec241 3344 /* */
mbed_official 155:8435094ec241 3345 /* Analog Comparators (COMP) */
mbed_official 155:8435094ec241 3346 /* */
mbed_official 155:8435094ec241 3347 /******************************************************************************/
mbed_official 155:8435094ec241 3348 /********************** Bit definition for COMP1_CSR register ***************/
mbed_official 155:8435094ec241 3349 #define COMP1_CSR_COMP1EN ((uint32_t)0x00000001) /*!< COMP1 enable */
mbed_official 155:8435094ec241 3350 #define COMP1_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
mbed_official 155:8435094ec241 3351 #define COMP1_CSR_COMP1MODE ((uint32_t)0x0000000C) /*!< COMP1 power mode */
mbed_official 155:8435094ec241 3352 #define COMP1_CSR_COMP1MODE_0 ((uint32_t)0x00000004) /*!< COMP1 power mode bit 0 */
mbed_official 155:8435094ec241 3353 #define COMP1_CSR_COMP1MODE_1 ((uint32_t)0x00000008) /*!< COMP1 power mode bit 1 */
mbed_official 155:8435094ec241 3354 #define COMP1_CSR_COMP1INSEL ((uint32_t)0x00000070) /*!< COMP1 inverting input select */
mbed_official 155:8435094ec241 3355 #define COMP1_CSR_COMP1INSEL_0 ((uint32_t)0x00000010) /*!< COMP1 inverting input select bit 0 */
mbed_official 155:8435094ec241 3356 #define COMP1_CSR_COMP1INSEL_1 ((uint32_t)0x00000020) /*!< COMP1 inverting input select bit 1 */
mbed_official 155:8435094ec241 3357 #define COMP1_CSR_COMP1INSEL_2 ((uint32_t)0x00000040) /*!< COMP1 inverting input select bit 2 */
mbed_official 155:8435094ec241 3358 #define COMP1_CSR_COMP1NONINSEL ((uint32_t)0x00000080) /*!< COMP1 non inverting input select */
mbed_official 155:8435094ec241 3359 #define COMP1_CSR_COMP1OUTSEL ((uint32_t)0x00003C00) /*!< COMP1 output select */
mbed_official 155:8435094ec241 3360 #define COMP1_CSR_COMP1OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP1 output select bit 0 */
mbed_official 155:8435094ec241 3361 #define COMP1_CSR_COMP1OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP1 output select bit 1 */
mbed_official 155:8435094ec241 3362 #define COMP1_CSR_COMP1OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP1 output select bit 2 */
mbed_official 155:8435094ec241 3363 #define COMP1_CSR_COMP1OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP1 output select bit 3 */
mbed_official 155:8435094ec241 3364 #define COMP1_CSR_COMP1POL ((uint32_t)0x00008000) /*!< COMP1 output polarity */
mbed_official 155:8435094ec241 3365 #define COMP1_CSR_COMP1HYST ((uint32_t)0x00030000) /*!< COMP1 hysteresis */
mbed_official 155:8435094ec241 3366 #define COMP1_CSR_COMP1HYST_0 ((uint32_t)0x00010000) /*!< COMP1 hysteresis bit 0 */
mbed_official 155:8435094ec241 3367 #define COMP1_CSR_COMP1HYST_1 ((uint32_t)0x00020000) /*!< COMP1 hysteresis bit 1 */
mbed_official 155:8435094ec241 3368 #define COMP1_CSR_COMP1BLANKING ((uint32_t)0x000C0000) /*!< COMP1 blanking */
mbed_official 155:8435094ec241 3369 #define COMP1_CSR_COMP1BLANKING_0 ((uint32_t)0x00040000) /*!< COMP1 blanking bit 0 */
mbed_official 155:8435094ec241 3370 #define COMP1_CSR_COMP1BLANKING_1 ((uint32_t)0x00080000) /*!< COMP1 blanking bit 1 */
mbed_official 155:8435094ec241 3371 #define COMP1_CSR_COMP1BLANKING_2 ((uint32_t)0x00100000) /*!< COMP1 blanking bit 2 */
mbed_official 155:8435094ec241 3372 #define COMP1_CSR_COMP1OUT ((uint32_t)0x40000000) /*!< COMP1 output level */
mbed_official 155:8435094ec241 3373 #define COMP1_CSR_COMP1LOCK ((uint32_t)0x80000000) /*!< COMP1 lock */
mbed_official 155:8435094ec241 3374
mbed_official 155:8435094ec241 3375 /********************** Bit definition for COMP2_CSR register ***************/
mbed_official 155:8435094ec241 3376 #define COMP2_CSR_COMP2EN ((uint32_t)0x00000001) /*!< COMP2 enable */
mbed_official 155:8435094ec241 3377 #define COMP2_CSR_COMP2MODE ((uint32_t)0x0000000C) /*!< COMP2 power mode */
mbed_official 155:8435094ec241 3378 #define COMP2_CSR_COMP2MODE_0 ((uint32_t)0x00000004) /*!< COMP2 power mode bit 0 */
mbed_official 155:8435094ec241 3379 #define COMP2_CSR_COMP2MODE_1 ((uint32_t)0x00000008) /*!< COMP2 power mode bit 1 */
mbed_official 155:8435094ec241 3380 #define COMP2_CSR_COMP2INSEL ((uint32_t)0x00000070) /*!< COMP2 inverting input select */
mbed_official 155:8435094ec241 3381 #define COMP2_CSR_COMP2INSEL_0 ((uint32_t)0x00000010) /*!< COMP2 inverting input select bit 0 */
mbed_official 155:8435094ec241 3382 #define COMP2_CSR_COMP2INSEL_1 ((uint32_t)0x00000020) /*!< COMP2 inverting input select bit 1 */
mbed_official 155:8435094ec241 3383 #define COMP2_CSR_COMP2INSEL_2 ((uint32_t)0x00000040) /*!< COMP2 inverting input select bit 2 */
mbed_official 155:8435094ec241 3384 #define COMP2_CSR_COMP2NONINSEL ((uint32_t)0x00000080) /*!< COMP2 non inverting input select */
mbed_official 155:8435094ec241 3385 #define COMP2_CSR_COMP2WNDWEN ((uint32_t)0x00000200) /*!< COMP2 window mode enable */
mbed_official 155:8435094ec241 3386 #define COMP2_CSR_COMP2OUTSEL ((uint32_t)0x00003C00) /*!< COMP2 output select */
mbed_official 155:8435094ec241 3387 #define COMP2_CSR_COMP2OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP2 output select bit 0 */
mbed_official 155:8435094ec241 3388 #define COMP2_CSR_COMP2OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP2 output select bit 1 */
mbed_official 155:8435094ec241 3389 #define COMP2_CSR_COMP2OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP2 output select bit 2 */
mbed_official 155:8435094ec241 3390 #define COMP2_CSR_COMP2OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP2 output select bit 3 */
mbed_official 155:8435094ec241 3391 #define COMP2_CSR_COMP2POL ((uint32_t)0x00008000) /*!< COMP2 output polarity */
mbed_official 155:8435094ec241 3392 #define COMP2_CSR_COMP2HYST ((uint32_t)0x00030000) /*!< COMP2 hysteresis */
mbed_official 155:8435094ec241 3393 #define COMP2_CSR_COMP2HYST_0 ((uint32_t)0x00010000) /*!< COMP2 hysteresis bit 0 */
mbed_official 155:8435094ec241 3394 #define COMP2_CSR_COMP2HYST_1 ((uint32_t)0x00020000) /*!< COMP2 hysteresis bit 1 */
mbed_official 155:8435094ec241 3395 #define COMP2_CSR_COMP2BLANKING ((uint32_t)0x000C0000) /*!< COMP2 blanking */
mbed_official 155:8435094ec241 3396 #define COMP2_CSR_COMP2BLANKING_0 ((uint32_t)0x00040000) /*!< COMP2 blanking bit 0 */
mbed_official 155:8435094ec241 3397 #define COMP2_CSR_COMP2BLANKING_1 ((uint32_t)0x00080000) /*!< COMP2 blanking bit 1 */
mbed_official 155:8435094ec241 3398 #define COMP2_CSR_COMP2BLANKING_2 ((uint32_t)0x00100000) /*!< COMP2 blanking bit 2 */
mbed_official 155:8435094ec241 3399 #define COMP2_CSR_COMP2OUT ((uint32_t)0x40000000) /*!< COMP2 output level */
mbed_official 155:8435094ec241 3400 #define COMP2_CSR_COMP2LOCK ((uint32_t)0x80000000) /*!< COMP2 lock */
mbed_official 155:8435094ec241 3401
mbed_official 155:8435094ec241 3402 /********************** Bit definition for COMP3_CSR register ***************/
mbed_official 155:8435094ec241 3403 #define COMP3_CSR_COMP3EN ((uint32_t)0x00000001) /*!< COMP3 enable */
mbed_official 155:8435094ec241 3404 #define COMP3_CSR_COMP3MODE ((uint32_t)0x0000000C) /*!< COMP3 power mode */
mbed_official 155:8435094ec241 3405 #define COMP3_CSR_COMP3MODE_0 ((uint32_t)0x00000004) /*!< COMP3 power mode bit 0 */
mbed_official 155:8435094ec241 3406 #define COMP3_CSR_COMP3MODE_1 ((uint32_t)0x00000008) /*!< COMP3 power mode bit 1 */
mbed_official 155:8435094ec241 3407 #define COMP3_CSR_COMP3INSEL ((uint32_t)0x00000070) /*!< COMP3 inverting input select */
mbed_official 155:8435094ec241 3408 #define COMP3_CSR_COMP3INSEL_0 ((uint32_t)0x00000010) /*!< COMP3 inverting input select bit 0 */
mbed_official 155:8435094ec241 3409 #define COMP3_CSR_COMP3INSEL_1 ((uint32_t)0x00000020) /*!< COMP3 inverting input select bit 1 */
mbed_official 155:8435094ec241 3410 #define COMP3_CSR_COMP3INSEL_2 ((uint32_t)0x00000040) /*!< COMP3 inverting input select bit 2 */
mbed_official 155:8435094ec241 3411 #define COMP3_CSR_COMP3NONINSEL ((uint32_t)0x00000080) /*!< COMP3 non inverting input select */
mbed_official 155:8435094ec241 3412 #define COMP3_CSR_COMP3OUTSEL ((uint32_t)0x00003C00) /*!< COMP3 output select */
mbed_official 155:8435094ec241 3413 #define COMP3_CSR_COMP3OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP3 output select bit 0 */
mbed_official 155:8435094ec241 3414 #define COMP3_CSR_COMP3OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP3 output select bit 1 */
mbed_official 155:8435094ec241 3415 #define COMP3_CSR_COMP3OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP3 output select bit 2 */
mbed_official 155:8435094ec241 3416 #define COMP3_CSR_COMP3OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP3 output select bit 3 */
mbed_official 155:8435094ec241 3417 #define COMP3_CSR_COMP3POL ((uint32_t)0x00008000) /*!< COMP3 output polarity */
mbed_official 155:8435094ec241 3418 #define COMP3_CSR_COMP3HYST ((uint32_t)0x00030000) /*!< COMP3 hysteresis */
mbed_official 155:8435094ec241 3419 #define COMP3_CSR_COMP3HYST_0 ((uint32_t)0x00010000) /*!< COMP3 hysteresis bit 0 */
mbed_official 155:8435094ec241 3420 #define COMP3_CSR_COMP3HYST_1 ((uint32_t)0x00020000) /*!< COMP3 hysteresis bit 1 */
mbed_official 155:8435094ec241 3421 #define COMP3_CSR_COMP3BLANKING ((uint32_t)0x000C0000) /*!< COMP3 blanking */
mbed_official 155:8435094ec241 3422 #define COMP3_CSR_COMP3BLANKING_0 ((uint32_t)0x00040000) /*!< COMP3 blanking bit 0 */
mbed_official 155:8435094ec241 3423 #define COMP3_CSR_COMP3BLANKING_1 ((uint32_t)0x00080000) /*!< COMP3 blanking bit 1 */
mbed_official 155:8435094ec241 3424 #define COMP3_CSR_COMP3BLANKING_2 ((uint32_t)0x00100000) /*!< COMP3 blanking bit 2 */
mbed_official 155:8435094ec241 3425 #define COMP3_CSR_COMP3OUT ((uint32_t)0x40000000) /*!< COMP3 output level */
mbed_official 155:8435094ec241 3426 #define COMP3_CSR_COMP3LOCK ((uint32_t)0x80000000) /*!< COMP3 lock */
mbed_official 155:8435094ec241 3427
mbed_official 155:8435094ec241 3428 /********************** Bit definition for COMP4_CSR register ***************/
mbed_official 155:8435094ec241 3429 #define COMP4_CSR_COMP4EN ((uint32_t)0x00000001) /*!< COMP4 enable */
mbed_official 155:8435094ec241 3430 #define COMP4_CSR_COMP4MODE ((uint32_t)0x0000000C) /*!< COMP4 power mode */
mbed_official 155:8435094ec241 3431 #define COMP4_CSR_COMP4MODE_0 ((uint32_t)0x00000004) /*!< COMP4 power mode bit 0 */
mbed_official 155:8435094ec241 3432 #define COMP4_CSR_COMP4MODE_1 ((uint32_t)0x00000008) /*!< COMP4 power mode bit 1 */
mbed_official 155:8435094ec241 3433 #define COMP4_CSR_COMP4INSEL ((uint32_t)0x00000070) /*!< COMP4 inverting input select */
mbed_official 155:8435094ec241 3434 #define COMP4_CSR_COMP4INSEL_0 ((uint32_t)0x00000010) /*!< COMP4 inverting input select bit 0 */
mbed_official 155:8435094ec241 3435 #define COMP4_CSR_COMP4INSEL_1 ((uint32_t)0x00000020) /*!< COMP4 inverting input select bit 1 */
mbed_official 155:8435094ec241 3436 #define COMP4_CSR_COMP4INSEL_2 ((uint32_t)0x00000040) /*!< COMP4 inverting input select bit 2 */
mbed_official 155:8435094ec241 3437 #define COMP4_CSR_COMP4NONINSEL ((uint32_t)0x00000080) /*!< COMP4 non inverting input select */
mbed_official 155:8435094ec241 3438 #define COMP4_CSR_COMP4WNDWEN ((uint32_t)0x00000200) /*!< COMP4 window mode enable */
mbed_official 155:8435094ec241 3439 #define COMP4_CSR_COMP4OUTSEL ((uint32_t)0x00003C00) /*!< COMP4 output select */
mbed_official 155:8435094ec241 3440 #define COMP4_CSR_COMP4OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP4 output select bit 0 */
mbed_official 155:8435094ec241 3441 #define COMP4_CSR_COMP4OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP4 output select bit 1 */
mbed_official 155:8435094ec241 3442 #define COMP4_CSR_COMP4OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP4 output select bit 2 */
mbed_official 155:8435094ec241 3443 #define COMP4_CSR_COMP4OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP4 output select bit 3 */
mbed_official 155:8435094ec241 3444 #define COMP4_CSR_COMP4POL ((uint32_t)0x00008000) /*!< COMP4 output polarity */
mbed_official 155:8435094ec241 3445 #define COMP4_CSR_COMP4HYST ((uint32_t)0x00030000) /*!< COMP4 hysteresis */
mbed_official 155:8435094ec241 3446 #define COMP4_CSR_COMP4HYST_0 ((uint32_t)0x00010000) /*!< COMP4 hysteresis bit 0 */
mbed_official 155:8435094ec241 3447 #define COMP4_CSR_COMP4HYST_1 ((uint32_t)0x00020000) /*!< COMP4 hysteresis bit 1 */
mbed_official 155:8435094ec241 3448 #define COMP4_CSR_COMP4BLANKING ((uint32_t)0x000C0000) /*!< COMP4 blanking */
mbed_official 155:8435094ec241 3449 #define COMP4_CSR_COMP4BLANKING_0 ((uint32_t)0x00040000) /*!< COMP4 blanking bit 0 */
mbed_official 155:8435094ec241 3450 #define COMP4_CSR_COMP4BLANKING_1 ((uint32_t)0x00080000) /*!< COMP4 blanking bit 1 */
mbed_official 155:8435094ec241 3451 #define COMP4_CSR_COMP4BLANKING_2 ((uint32_t)0x00100000) /*!< COMP4 blanking bit 2 */
mbed_official 155:8435094ec241 3452 #define COMP4_CSR_COMP4OUT ((uint32_t)0x40000000) /*!< COMP4 output level */
mbed_official 155:8435094ec241 3453 #define COMP4_CSR_COMP4LOCK ((uint32_t)0x80000000) /*!< COMP4 lock */
mbed_official 155:8435094ec241 3454
mbed_official 155:8435094ec241 3455 /********************** Bit definition for COMP5_CSR register ***************/
mbed_official 155:8435094ec241 3456 #define COMP5_CSR_COMP5EN ((uint32_t)0x00000001) /*!< COMP5 enable */
mbed_official 155:8435094ec241 3457 #define COMP5_CSR_COMP5MODE ((uint32_t)0x0000000C) /*!< COMP5 power mode */
mbed_official 155:8435094ec241 3458 #define COMP5_CSR_COMP5MODE_0 ((uint32_t)0x00000004) /*!< COMP5 power mode bit 0 */
mbed_official 155:8435094ec241 3459 #define COMP5_CSR_COMP5MODE_1 ((uint32_t)0x00000008) /*!< COMP5 power mode bit 1 */
mbed_official 155:8435094ec241 3460 #define COMP5_CSR_COMP5INSEL ((uint32_t)0x00000070) /*!< COMP5 inverting input select */
mbed_official 155:8435094ec241 3461 #define COMP5_CSR_COMP5INSEL_0 ((uint32_t)0x00000010) /*!< COMP5 inverting input select bit 0 */
mbed_official 155:8435094ec241 3462 #define COMP5_CSR_COMP5INSEL_1 ((uint32_t)0x00000020) /*!< COMP5 inverting input select bit 1 */
mbed_official 155:8435094ec241 3463 #define COMP5_CSR_COMP5INSEL_2 ((uint32_t)0x00000040) /*!< COMP5 inverting input select bit 2 */
mbed_official 155:8435094ec241 3464 #define COMP5_CSR_COMP5NONINSEL ((uint32_t)0x00000080) /*!< COMP5 non inverting input select */
mbed_official 155:8435094ec241 3465 #define COMP5_CSR_COMP5OUTSEL ((uint32_t)0x00003C00) /*!< COMP5 output select */
mbed_official 155:8435094ec241 3466 #define COMP5_CSR_COMP5OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP5 output select bit 0 */
mbed_official 155:8435094ec241 3467 #define COMP5_CSR_COMP5OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP5 output select bit 1 */
mbed_official 155:8435094ec241 3468 #define COMP5_CSR_COMP5OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP5 output select bit 2 */
mbed_official 155:8435094ec241 3469 #define COMP5_CSR_COMP5OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP5 output select bit 3 */
mbed_official 155:8435094ec241 3470 #define COMP5_CSR_COMP5POL ((uint32_t)0x00008000) /*!< COMP5 output polarity */
mbed_official 155:8435094ec241 3471 #define COMP5_CSR_COMP5HYST ((uint32_t)0x00030000) /*!< COMP5 hysteresis */
mbed_official 155:8435094ec241 3472 #define COMP5_CSR_COMP5HYST_0 ((uint32_t)0x00010000) /*!< COMP5 hysteresis bit 0 */
mbed_official 155:8435094ec241 3473 #define COMP5_CSR_COMP5HYST_1 ((uint32_t)0x00020000) /*!< COMP5 hysteresis bit 1 */
mbed_official 155:8435094ec241 3474 #define COMP5_CSR_COMP5BLANKING ((uint32_t)0x000C0000) /*!< COMP5 blanking */
mbed_official 155:8435094ec241 3475 #define COMP5_CSR_COMP5BLANKING_0 ((uint32_t)0x00040000) /*!< COMP5 blanking bit 0 */
mbed_official 155:8435094ec241 3476 #define COMP5_CSR_COMP5BLANKING_1 ((uint32_t)0x00080000) /*!< COMP5 blanking bit 1 */
mbed_official 155:8435094ec241 3477 #define COMP5_CSR_COMP5BLANKING_2 ((uint32_t)0x00100000) /*!< COMP5 blanking bit 2 */
mbed_official 155:8435094ec241 3478 #define COMP5_CSR_COMP5OUT ((uint32_t)0x40000000) /*!< COMP5 output level */
mbed_official 155:8435094ec241 3479 #define COMP5_CSR_COMP5LOCK ((uint32_t)0x80000000) /*!< COMP5 lock */
mbed_official 155:8435094ec241 3480
mbed_official 155:8435094ec241 3481 /********************** Bit definition for COMP6_CSR register ***************/
mbed_official 155:8435094ec241 3482 #define COMP6_CSR_COMP6EN ((uint32_t)0x00000001) /*!< COMP6 enable */
mbed_official 155:8435094ec241 3483 #define COMP6_CSR_COMP6MODE ((uint32_t)0x0000000C) /*!< COMP6 power mode */
mbed_official 155:8435094ec241 3484 #define COMP6_CSR_COMP6MODE_0 ((uint32_t)0x00000004) /*!< COMP6 power mode bit 0 */
mbed_official 155:8435094ec241 3485 #define COMP6_CSR_COMP6MODE_1 ((uint32_t)0x00000008) /*!< COMP6 power mode bit 1 */
mbed_official 155:8435094ec241 3486 #define COMP6_CSR_COMP6INSEL ((uint32_t)0x00000070) /*!< COMP6 inverting input select */
mbed_official 155:8435094ec241 3487 #define COMP6_CSR_COMP6INSEL_0 ((uint32_t)0x00000010) /*!< COMP6 inverting input select bit 0 */
mbed_official 155:8435094ec241 3488 #define COMP6_CSR_COMP6INSEL_1 ((uint32_t)0x00000020) /*!< COMP6 inverting input select bit 1 */
mbed_official 155:8435094ec241 3489 #define COMP6_CSR_COMP6INSEL_2 ((uint32_t)0x00000040) /*!< COMP6 inverting input select bit 2 */
mbed_official 155:8435094ec241 3490 #define COMP6_CSR_COMP6NONINSEL ((uint32_t)0x00000080) /*!< COMP6 non inverting input select */
mbed_official 155:8435094ec241 3491 #define COMP6_CSR_COMP6WNDWEN ((uint32_t)0x00000200) /*!< COMP6 window mode enable */
mbed_official 155:8435094ec241 3492 #define COMP6_CSR_COMP6OUTSEL ((uint32_t)0x00003C00) /*!< COMP6 output select */
mbed_official 155:8435094ec241 3493 #define COMP6_CSR_COMP6OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP6 output select bit 0 */
mbed_official 155:8435094ec241 3494 #define COMP6_CSR_COMP6OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP6 output select bit 1 */
mbed_official 155:8435094ec241 3495 #define COMP6_CSR_COMP6OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP6 output select bit 2 */
mbed_official 155:8435094ec241 3496 #define COMP6_CSR_COMP6OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP6 output select bit 3 */
mbed_official 155:8435094ec241 3497 #define COMP6_CSR_COMP6POL ((uint32_t)0x00008000) /*!< COMP6 output polarity */
mbed_official 155:8435094ec241 3498 #define COMP6_CSR_COMP6HYST ((uint32_t)0x00030000) /*!< COMP6 hysteresis */
mbed_official 155:8435094ec241 3499 #define COMP6_CSR_COMP6HYST_0 ((uint32_t)0x00010000) /*!< COMP6 hysteresis bit 0 */
mbed_official 155:8435094ec241 3500 #define COMP6_CSR_COMP6HYST_1 ((uint32_t)0x00020000) /*!< COMP6 hysteresis bit 1 */
mbed_official 155:8435094ec241 3501 #define COMP6_CSR_COMP6BLANKING ((uint32_t)0x000C0000) /*!< COMP6 blanking */
mbed_official 155:8435094ec241 3502 #define COMP6_CSR_COMP6BLANKING_0 ((uint32_t)0x00040000) /*!< COMP6 blanking bit 0 */
mbed_official 155:8435094ec241 3503 #define COMP6_CSR_COMP6BLANKING_1 ((uint32_t)0x00080000) /*!< COMP6 blanking bit 1 */
mbed_official 155:8435094ec241 3504 #define COMP6_CSR_COMP6BLANKING_2 ((uint32_t)0x00100000) /*!< COMP6 blanking bit 2 */
mbed_official 155:8435094ec241 3505 #define COMP6_CSR_COMP6OUT ((uint32_t)0x40000000) /*!< COMP6 output level */
mbed_official 155:8435094ec241 3506 #define COMP6_CSR_COMP6LOCK ((uint32_t)0x80000000) /*!< COMP6 lock */
mbed_official 155:8435094ec241 3507
mbed_official 155:8435094ec241 3508 /********************** Bit definition for COMP7_CSR register ***************/
mbed_official 155:8435094ec241 3509 #define COMP7_CSR_COMP7EN ((uint32_t)0x00000001) /*!< COMP7 enable */
mbed_official 155:8435094ec241 3510 #define COMP7_CSR_COMP7MODE ((uint32_t)0x0000000C) /*!< COMP7 power mode */
mbed_official 155:8435094ec241 3511 #define COMP7_CSR_COMP7MODE_0 ((uint32_t)0x00000004) /*!< COMP7 power mode bit 0 */
mbed_official 155:8435094ec241 3512 #define COMP7_CSR_COMP7MODE_1 ((uint32_t)0x00000008) /*!< COMP7 power mode bit 1 */
mbed_official 155:8435094ec241 3513 #define COMP7_CSR_COMP7INSEL ((uint32_t)0x00000070) /*!< COMP7 inverting input select */
mbed_official 155:8435094ec241 3514 #define COMP7_CSR_COMP7INSEL_0 ((uint32_t)0x00000010) /*!< COMP7 inverting input select bit 0 */
mbed_official 155:8435094ec241 3515 #define COMP7_CSR_COMP7INSEL_1 ((uint32_t)0x00000020) /*!< COMP7 inverting input select bit 1 */
mbed_official 155:8435094ec241 3516 #define COMP7_CSR_COMP7INSEL_2 ((uint32_t)0x00000040) /*!< COMP7 inverting input select bit 2 */
mbed_official 155:8435094ec241 3517 #define COMP7_CSR_COMP7NONINSEL ((uint32_t)0x00000080) /*!< COMP7 non inverting input select */
mbed_official 155:8435094ec241 3518 #define COMP7_CSR_COMP7OUTSEL ((uint32_t)0x00003C00) /*!< COMP7 output select */
mbed_official 155:8435094ec241 3519 #define COMP7_CSR_COMP7OUTSEL_0 ((uint32_t)0x00000400) /*!< COMP7 output select bit 0 */
mbed_official 155:8435094ec241 3520 #define COMP7_CSR_COMP7OUTSEL_1 ((uint32_t)0x00000800) /*!< COMP7 output select bit 1 */
mbed_official 155:8435094ec241 3521 #define COMP7_CSR_COMP7OUTSEL_2 ((uint32_t)0x00001000) /*!< COMP7 output select bit 2 */
mbed_official 155:8435094ec241 3522 #define COMP7_CSR_COMP7OUTSEL_3 ((uint32_t)0x00002000) /*!< COMP7 output select bit 3 */
mbed_official 155:8435094ec241 3523 #define COMP7_CSR_COMP7POL ((uint32_t)0x00008000) /*!< COMP7 output polarity */
mbed_official 155:8435094ec241 3524 #define COMP7_CSR_COMP7HYST ((uint32_t)0x00030000) /*!< COMP7 hysteresis */
mbed_official 155:8435094ec241 3525 #define COMP7_CSR_COMP7HYST_0 ((uint32_t)0x00010000) /*!< COMP7 hysteresis bit 0 */
mbed_official 155:8435094ec241 3526 #define COMP7_CSR_COMP7HYST_1 ((uint32_t)0x00020000) /*!< COMP7 hysteresis bit 1 */
mbed_official 155:8435094ec241 3527 #define COMP7_CSR_COMP7BLANKING ((uint32_t)0x000C0000) /*!< COMP7 blanking */
mbed_official 155:8435094ec241 3528 #define COMP7_CSR_COMP7BLANKING_0 ((uint32_t)0x00040000) /*!< COMP7 blanking bit 0 */
mbed_official 155:8435094ec241 3529 #define COMP7_CSR_COMP7BLANKING_1 ((uint32_t)0x00080000) /*!< COMP7 blanking bit 1 */
mbed_official 155:8435094ec241 3530 #define COMP7_CSR_COMP7BLANKING_2 ((uint32_t)0x00100000) /*!< COMP7 blanking bit 2 */
mbed_official 155:8435094ec241 3531 #define COMP7_CSR_COMP7OUT ((uint32_t)0x40000000) /*!< COMP7 output level */
mbed_official 155:8435094ec241 3532 #define COMP7_CSR_COMP7LOCK ((uint32_t)0x80000000) /*!< COMP7 lock */
mbed_official 155:8435094ec241 3533
mbed_official 155:8435094ec241 3534 /********************** Bit definition for COMP_CSR register ****************/
mbed_official 155:8435094ec241 3535 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001) /*!< COMPx enable */
mbed_official 155:8435094ec241 3536 #define COMP_CSR_COMP1SW1 ((uint32_t)0x00000002) /*!< COMP1 SW1 switch control */
mbed_official 155:8435094ec241 3537 #define COMP_CSR_COMPxMODE ((uint32_t)0x0000000C) /*!< COMPx power mode */
mbed_official 155:8435094ec241 3538 #define COMP_CSR_COMPxMODE_0 ((uint32_t)0x00000004) /*!< COMPx power mode bit 0 */
mbed_official 155:8435094ec241 3539 #define COMP_CSR_COMPxMODE_1 ((uint32_t)0x00000008) /*!< COMPx power mode bit 1 */
mbed_official 155:8435094ec241 3540 #define COMP_CSR_COMPxINSEL ((uint32_t)0x00000070) /*!< COMPx inverting input select */
mbed_official 155:8435094ec241 3541 #define COMP_CSR_COMPxINSEL_0 ((uint32_t)0x00000010) /*!< COMPx inverting input select bit 0 */
mbed_official 155:8435094ec241 3542 #define COMP_CSR_COMPxINSEL_1 ((uint32_t)0x00000020) /*!< COMPx inverting input select bit 1 */
mbed_official 155:8435094ec241 3543 #define COMP_CSR_COMPxINSEL_2 ((uint32_t)0x00000040) /*!< COMPx inverting input select bit 2 */
mbed_official 155:8435094ec241 3544 #define COMP_CSR_COMPxNONINSEL ((uint32_t)0x00000080) /*!< COMPx non inverting input select */
mbed_official 155:8435094ec241 3545 #define COMP_CSR_COMPxWNDWEN ((uint32_t)0x00000200) /*!< COMPx window mode enable */
mbed_official 155:8435094ec241 3546 #define COMP_CSR_COMPxOUTSEL ((uint32_t)0x00003C00) /*!< COMPx output select */
mbed_official 155:8435094ec241 3547 #define COMP_CSR_COMPxOUTSEL_0 ((uint32_t)0x00000400) /*!< COMPx output select bit 0 */
mbed_official 155:8435094ec241 3548 #define COMP_CSR_COMPxOUTSEL_1 ((uint32_t)0x00000800) /*!< COMPx output select bit 1 */
mbed_official 155:8435094ec241 3549 #define COMP_CSR_COMPxOUTSEL_2 ((uint32_t)0x00001000) /*!< COMPx output select bit 2 */
mbed_official 155:8435094ec241 3550 #define COMP_CSR_COMPxOUTSEL_3 ((uint32_t)0x00002000) /*!< COMPx output select bit 3 */
mbed_official 155:8435094ec241 3551 #define COMP_CSR_COMPxPOL ((uint32_t)0x00008000) /*!< COMPx output polarity */
mbed_official 155:8435094ec241 3552 #define COMP_CSR_COMPxHYST ((uint32_t)0x00030000) /*!< COMPx hysteresis */
mbed_official 155:8435094ec241 3553 #define COMP_CSR_COMPxHYST_0 ((uint32_t)0x00010000) /*!< COMPx hysteresis bit 0 */
mbed_official 155:8435094ec241 3554 #define COMP_CSR_COMPxHYST_1 ((uint32_t)0x00020000) /*!< COMPx hysteresis bit 1 */
mbed_official 155:8435094ec241 3555 #define COMP_CSR_COMPxBLANKING ((uint32_t)0x000C0000) /*!< COMPx blanking */
mbed_official 155:8435094ec241 3556 #define COMP_CSR_COMPxBLANKING_0 ((uint32_t)0x00040000) /*!< COMPx blanking bit 0 */
mbed_official 155:8435094ec241 3557 #define COMP_CSR_COMPxBLANKING_1 ((uint32_t)0x00080000) /*!< COMPx blanking bit 1 */
mbed_official 155:8435094ec241 3558 #define COMP_CSR_COMPxBLANKING_2 ((uint32_t)0x00100000) /*!< COMPx blanking bit 2 */
mbed_official 155:8435094ec241 3559 #define COMP_CSR_COMPxINSEL_3 ((uint32_t)0x00400000) /*!< COMPx inverting input select bit 3 */
mbed_official 155:8435094ec241 3560 #define COMP_CSR_COMPxOUT ((uint32_t)0x40000000) /*!< COMPx output level */
mbed_official 155:8435094ec241 3561 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000) /*!< COMPx lock */
mbed_official 155:8435094ec241 3562
mbed_official 155:8435094ec241 3563 /******************************************************************************/
mbed_official 155:8435094ec241 3564 /* */
mbed_official 155:8435094ec241 3565 /* Operational Amplifier (OPAMP) */
mbed_official 155:8435094ec241 3566 /* */
mbed_official 155:8435094ec241 3567 /******************************************************************************/
mbed_official 155:8435094ec241 3568 /********************* Bit definition for OPAMP1_CSR register ***************/
mbed_official 155:8435094ec241 3569 #define OPAMP1_CSR_OPAMP1EN ((uint32_t)0x00000001) /*!< OPAMP1 enable */
mbed_official 155:8435094ec241 3570 #define OPAMP1_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 155:8435094ec241 3571 #define OPAMP1_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 155:8435094ec241 3572 #define OPAMP1_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 155:8435094ec241 3573 #define OPAMP1_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 155:8435094ec241 3574 #define OPAMP1_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 155:8435094ec241 3575 #define OPAMP1_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 155:8435094ec241 3576 #define OPAMP1_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 155:8435094ec241 3577 #define OPAMP1_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 155:8435094ec241 3578 #define OPAMP1_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 155:8435094ec241 3579 #define OPAMP1_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 155:8435094ec241 3580 #define OPAMP1_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 155:8435094ec241 3581 #define OPAMP1_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 155:8435094ec241 3582 #define OPAMP1_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 155:8435094ec241 3583 #define OPAMP1_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 155:8435094ec241 3584 #define OPAMP1_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3585 #define OPAMP1_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3586 #define OPAMP1_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 155:8435094ec241 3587 #define OPAMP1_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3588 #define OPAMP1_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3589 #define OPAMP1_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 155:8435094ec241 3590 #define OPAMP1_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 155:8435094ec241 3591 #define OPAMP1_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 155:8435094ec241 3592 #define OPAMP1_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 155:8435094ec241 3593 #define OPAMP1_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 155:8435094ec241 3594 #define OPAMP1_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 155:8435094ec241 3595 #define OPAMP1_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
mbed_official 155:8435094ec241 3596 #define OPAMP1_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 155:8435094ec241 3597
mbed_official 155:8435094ec241 3598 /********************* Bit definition for OPAMP2_CSR register ***************/
mbed_official 155:8435094ec241 3599 #define OPAMP2_CSR_OPAMP2EN ((uint32_t)0x00000001) /*!< OPAMP2 enable */
mbed_official 155:8435094ec241 3600 #define OPAMP2_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 155:8435094ec241 3601 #define OPAMP2_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 155:8435094ec241 3602 #define OPAMP2_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 155:8435094ec241 3603 #define OPAMP2_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 155:8435094ec241 3604 #define OPAMP2_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 155:8435094ec241 3605 #define OPAMP2_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 155:8435094ec241 3606 #define OPAMP2_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 155:8435094ec241 3607 #define OPAMP2_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 155:8435094ec241 3608 #define OPAMP2_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 155:8435094ec241 3609 #define OPAMP2_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 155:8435094ec241 3610 #define OPAMP2_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 155:8435094ec241 3611 #define OPAMP2_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 155:8435094ec241 3612 #define OPAMP2_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 155:8435094ec241 3613 #define OPAMP2_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 155:8435094ec241 3614 #define OPAMP2_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3615 #define OPAMP2_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3616 #define OPAMP2_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 155:8435094ec241 3617 #define OPAMP2_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3618 #define OPAMP2_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3619 #define OPAMP2_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 155:8435094ec241 3620 #define OPAMP2_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 155:8435094ec241 3621 #define OPAMP2_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 155:8435094ec241 3622 #define OPAMP2_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 155:8435094ec241 3623 #define OPAMP2_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 155:8435094ec241 3624 #define OPAMP2_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 155:8435094ec241 3625 #define OPAMP2_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
mbed_official 155:8435094ec241 3626 #define OPAMP2_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 155:8435094ec241 3627
mbed_official 155:8435094ec241 3628 /********************* Bit definition for OPAMP3_CSR register ***************/
mbed_official 155:8435094ec241 3629 #define OPAMP3_CSR_OPAMP3EN ((uint32_t)0x00000001) /*!< OPAMP3 enable */
mbed_official 155:8435094ec241 3630 #define OPAMP3_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 155:8435094ec241 3631 #define OPAMP3_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 155:8435094ec241 3632 #define OPAMP3_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 155:8435094ec241 3633 #define OPAMP3_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 155:8435094ec241 3634 #define OPAMP3_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 155:8435094ec241 3635 #define OPAMP3_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 155:8435094ec241 3636 #define OPAMP3_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 155:8435094ec241 3637 #define OPAMP3_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 155:8435094ec241 3638 #define OPAMP3_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 155:8435094ec241 3639 #define OPAMP3_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 155:8435094ec241 3640 #define OPAMP3_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 155:8435094ec241 3641 #define OPAMP3_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 155:8435094ec241 3642 #define OPAMP3_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 155:8435094ec241 3643 #define OPAMP3_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 155:8435094ec241 3644 #define OPAMP3_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3645 #define OPAMP3_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3646 #define OPAMP3_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 155:8435094ec241 3647 #define OPAMP3_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3648 #define OPAMP3_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3649 #define OPAMP3_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 155:8435094ec241 3650 #define OPAMP3_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 155:8435094ec241 3651 #define OPAMP3_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 155:8435094ec241 3652 #define OPAMP3_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 155:8435094ec241 3653 #define OPAMP3_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 155:8435094ec241 3654 #define OPAMP3_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 155:8435094ec241 3655 #define OPAMP3_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
mbed_official 155:8435094ec241 3656 #define OPAMP3_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 155:8435094ec241 3657
mbed_official 155:8435094ec241 3658 /********************* Bit definition for OPAMP4_CSR register ***************/
mbed_official 155:8435094ec241 3659 #define OPAMP4_CSR_OPAMP4EN ((uint32_t)0x00000001) /*!< OPAMP4 enable */
mbed_official 155:8435094ec241 3660 #define OPAMP4_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 155:8435094ec241 3661 #define OPAMP4_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 155:8435094ec241 3662 #define OPAMP4_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 155:8435094ec241 3663 #define OPAMP4_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 155:8435094ec241 3664 #define OPAMP4_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 155:8435094ec241 3665 #define OPAMP4_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 155:8435094ec241 3666 #define OPAMP4_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 155:8435094ec241 3667 #define OPAMP4_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 155:8435094ec241 3668 #define OPAMP4_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 155:8435094ec241 3669 #define OPAMP4_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 155:8435094ec241 3670 #define OPAMP4_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 155:8435094ec241 3671 #define OPAMP4_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 155:8435094ec241 3672 #define OPAMP4_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 155:8435094ec241 3673 #define OPAMP4_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 155:8435094ec241 3674 #define OPAMP4_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3675 #define OPAMP4_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3676 #define OPAMP4_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 155:8435094ec241 3677 #define OPAMP4_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3678 #define OPAMP4_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3679 #define OPAMP4_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 155:8435094ec241 3680 #define OPAMP4_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 155:8435094ec241 3681 #define OPAMP4_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 155:8435094ec241 3682 #define OPAMP4_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 155:8435094ec241 3683 #define OPAMP4_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 155:8435094ec241 3684 #define OPAMP4_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 155:8435094ec241 3685 #define OPAMP4_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
mbed_official 155:8435094ec241 3686 #define OPAMP4_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 155:8435094ec241 3687
mbed_official 155:8435094ec241 3688 /********************* Bit definition for OPAMPx_CSR register ***************/
mbed_official 155:8435094ec241 3689 #define OPAMP_CSR_OPAMPxEN ((uint32_t)0x00000001) /*!< OPAMP enable */
mbed_official 155:8435094ec241 3690 #define OPAMP_CSR_FORCEVP ((uint32_t)0x00000002) /*!< Connect the internal references to the plus input of the OPAMPX */
mbed_official 155:8435094ec241 3691 #define OPAMP_CSR_VPSEL ((uint32_t)0x0000000C) /*!< Non inverting input selection */
mbed_official 155:8435094ec241 3692 #define OPAMP_CSR_VPSEL_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 155:8435094ec241 3693 #define OPAMP_CSR_VPSEL_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 155:8435094ec241 3694 #define OPAMP_CSR_VMSEL ((uint32_t)0x00000060) /*!< Inverting input selection */
mbed_official 155:8435094ec241 3695 #define OPAMP_CSR_VMSEL_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 155:8435094ec241 3696 #define OPAMP_CSR_VMSEL_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 155:8435094ec241 3697 #define OPAMP_CSR_TCMEN ((uint32_t)0x00000080) /*!< Timer-Controlled Mux mode enable */
mbed_official 155:8435094ec241 3698 #define OPAMP_CSR_VMSSEL ((uint32_t)0x00000100) /*!< Inverting input secondary selection */
mbed_official 155:8435094ec241 3699 #define OPAMP_CSR_VPSSEL ((uint32_t)0x00000600) /*!< Non inverting input secondary selection */
mbed_official 155:8435094ec241 3700 #define OPAMP_CSR_VPSSEL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 155:8435094ec241 3701 #define OPAMP_CSR_VPSSEL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 155:8435094ec241 3702 #define OPAMP_CSR_CALON ((uint32_t)0x00000800) /*!< Calibration mode enable */
mbed_official 155:8435094ec241 3703 #define OPAMP_CSR_CALSEL ((uint32_t)0x00003000) /*!< Calibration selection */
mbed_official 155:8435094ec241 3704 #define OPAMP_CSR_CALSEL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3705 #define OPAMP_CSR_CALSEL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3706 #define OPAMP_CSR_PGGAIN ((uint32_t)0x0003C000) /*!< Gain in PGA mode */
mbed_official 155:8435094ec241 3707 #define OPAMP_CSR_PGGAIN_0 ((uint32_t)0x00004000) /*!< Bit 0 */
mbed_official 155:8435094ec241 3708 #define OPAMP_CSR_PGGAIN_1 ((uint32_t)0x00008000) /*!< Bit 1 */
mbed_official 155:8435094ec241 3709 #define OPAMP_CSR_PGGAIN_2 ((uint32_t)0x00010000) /*!< Bit 2 */
mbed_official 155:8435094ec241 3710 #define OPAMP_CSR_PGGAIN_3 ((uint32_t)0x00020000) /*!< Bit 3 */
mbed_official 155:8435094ec241 3711 #define OPAMP_CSR_USERTRIM ((uint32_t)0x00040000) /*!< User trimming enable */
mbed_official 155:8435094ec241 3712 #define OPAMP_CSR_TRIMOFFSETP ((uint32_t)0x00F80000) /*!< Offset trimming value (PMOS) */
mbed_official 155:8435094ec241 3713 #define OPAMP_CSR_TRIMOFFSETN ((uint32_t)0x1F000000) /*!< Offset trimming value (NMOS) */
mbed_official 155:8435094ec241 3714 #define OPAMP_CSR_TSTREF ((uint32_t)0x20000000) /*!< It enables the switch to put out the internal reference */
mbed_official 155:8435094ec241 3715 #define OPAMP_CSR_OUTCAL ((uint32_t)0x40000000) /*!< OPAMP output status flag */
mbed_official 155:8435094ec241 3716 #define OPAMP_CSR_LOCK ((uint32_t)0x80000000) /*!< OPAMP lock */
mbed_official 155:8435094ec241 3717
mbed_official 155:8435094ec241 3718
mbed_official 155:8435094ec241 3719 /******************************************************************************/
mbed_official 155:8435094ec241 3720 /* */
mbed_official 155:8435094ec241 3721 /* Controller Area Network (CAN ) */
mbed_official 155:8435094ec241 3722 /* */
mbed_official 155:8435094ec241 3723 /******************************************************************************/
mbed_official 155:8435094ec241 3724 /*!<CAN control and status registers */
mbed_official 155:8435094ec241 3725 /******************* Bit definition for CAN_MCR register ********************/
mbed_official 155:8435094ec241 3726 #define CAN_MCR_INRQ ((uint16_t)0x0001) /*!<Initialization Request */
mbed_official 155:8435094ec241 3727 #define CAN_MCR_SLEEP ((uint16_t)0x0002) /*!<Sleep Mode Request */
mbed_official 155:8435094ec241 3728 #define CAN_MCR_TXFP ((uint16_t)0x0004) /*!<Transmit FIFO Priority */
mbed_official 155:8435094ec241 3729 #define CAN_MCR_RFLM ((uint16_t)0x0008) /*!<Receive FIFO Locked Mode */
mbed_official 155:8435094ec241 3730 #define CAN_MCR_NART ((uint16_t)0x0010) /*!<No Automatic Retransmission */
mbed_official 155:8435094ec241 3731 #define CAN_MCR_AWUM ((uint16_t)0x0020) /*!<Automatic Wakeup Mode */
mbed_official 155:8435094ec241 3732 #define CAN_MCR_ABOM ((uint16_t)0x0040) /*!<Automatic Bus-Off Management */
mbed_official 155:8435094ec241 3733 #define CAN_MCR_TTCM ((uint16_t)0x0080) /*!<Time Triggered Communication Mode */
mbed_official 155:8435094ec241 3734 #define CAN_MCR_RESET ((uint16_t)0x8000) /*!<bxCAN software master reset */
mbed_official 155:8435094ec241 3735
mbed_official 155:8435094ec241 3736 /******************* Bit definition for CAN_MSR register ********************/
mbed_official 155:8435094ec241 3737 #define CAN_MSR_INAK ((uint16_t)0x0001) /*!<Initialization Acknowledge */
mbed_official 155:8435094ec241 3738 #define CAN_MSR_SLAK ((uint16_t)0x0002) /*!<Sleep Acknowledge */
mbed_official 155:8435094ec241 3739 #define CAN_MSR_ERRI ((uint16_t)0x0004) /*!<Error Interrupt */
mbed_official 155:8435094ec241 3740 #define CAN_MSR_WKUI ((uint16_t)0x0008) /*!<Wakeup Interrupt */
mbed_official 155:8435094ec241 3741 #define CAN_MSR_SLAKI ((uint16_t)0x0010) /*!<Sleep Acknowledge Interrupt */
mbed_official 155:8435094ec241 3742 #define CAN_MSR_TXM ((uint16_t)0x0100) /*!<Transmit Mode */
mbed_official 155:8435094ec241 3743 #define CAN_MSR_RXM ((uint16_t)0x0200) /*!<Receive Mode */
mbed_official 155:8435094ec241 3744 #define CAN_MSR_SAMP ((uint16_t)0x0400) /*!<Last Sample Point */
mbed_official 155:8435094ec241 3745 #define CAN_MSR_RX ((uint16_t)0x0800) /*!<CAN Rx Signal */
mbed_official 155:8435094ec241 3746
mbed_official 155:8435094ec241 3747 /******************* Bit definition for CAN_TSR register ********************/
mbed_official 155:8435094ec241 3748 #define CAN_TSR_RQCP0 ((uint32_t)0x00000001) /*!<Request Completed Mailbox0 */
mbed_official 155:8435094ec241 3749 #define CAN_TSR_TXOK0 ((uint32_t)0x00000002) /*!<Transmission OK of Mailbox0 */
mbed_official 155:8435094ec241 3750 #define CAN_TSR_ALST0 ((uint32_t)0x00000004) /*!<Arbitration Lost for Mailbox0 */
mbed_official 155:8435094ec241 3751 #define CAN_TSR_TERR0 ((uint32_t)0x00000008) /*!<Transmission Error of Mailbox0 */
mbed_official 155:8435094ec241 3752 #define CAN_TSR_ABRQ0 ((uint32_t)0x00000080) /*!<Abort Request for Mailbox0 */
mbed_official 155:8435094ec241 3753 #define CAN_TSR_RQCP1 ((uint32_t)0x00000100) /*!<Request Completed Mailbox1 */
mbed_official 155:8435094ec241 3754 #define CAN_TSR_TXOK1 ((uint32_t)0x00000200) /*!<Transmission OK of Mailbox1 */
mbed_official 155:8435094ec241 3755 #define CAN_TSR_ALST1 ((uint32_t)0x00000400) /*!<Arbitration Lost for Mailbox1 */
mbed_official 155:8435094ec241 3756 #define CAN_TSR_TERR1 ((uint32_t)0x00000800) /*!<Transmission Error of Mailbox1 */
mbed_official 155:8435094ec241 3757 #define CAN_TSR_ABRQ1 ((uint32_t)0x00008000) /*!<Abort Request for Mailbox 1 */
mbed_official 155:8435094ec241 3758 #define CAN_TSR_RQCP2 ((uint32_t)0x00010000) /*!<Request Completed Mailbox2 */
mbed_official 155:8435094ec241 3759 #define CAN_TSR_TXOK2 ((uint32_t)0x00020000) /*!<Transmission OK of Mailbox 2 */
mbed_official 155:8435094ec241 3760 #define CAN_TSR_ALST2 ((uint32_t)0x00040000) /*!<Arbitration Lost for mailbox 2 */
mbed_official 155:8435094ec241 3761 #define CAN_TSR_TERR2 ((uint32_t)0x00080000) /*!<Transmission Error of Mailbox 2 */
mbed_official 155:8435094ec241 3762 #define CAN_TSR_ABRQ2 ((uint32_t)0x00800000) /*!<Abort Request for Mailbox 2 */
mbed_official 155:8435094ec241 3763 #define CAN_TSR_CODE ((uint32_t)0x03000000) /*!<Mailbox Code */
mbed_official 155:8435094ec241 3764
mbed_official 155:8435094ec241 3765 #define CAN_TSR_TME ((uint32_t)0x1C000000) /*!<TME[2:0] bits */
mbed_official 155:8435094ec241 3766 #define CAN_TSR_TME0 ((uint32_t)0x04000000) /*!<Transmit Mailbox 0 Empty */
mbed_official 155:8435094ec241 3767 #define CAN_TSR_TME1 ((uint32_t)0x08000000) /*!<Transmit Mailbox 1 Empty */
mbed_official 155:8435094ec241 3768 #define CAN_TSR_TME2 ((uint32_t)0x10000000) /*!<Transmit Mailbox 2 Empty */
mbed_official 155:8435094ec241 3769
mbed_official 155:8435094ec241 3770 #define CAN_TSR_LOW ((uint32_t)0xE0000000) /*!<LOW[2:0] bits */
mbed_official 155:8435094ec241 3771 #define CAN_TSR_LOW0 ((uint32_t)0x20000000) /*!<Lowest Priority Flag for Mailbox 0 */
mbed_official 155:8435094ec241 3772 #define CAN_TSR_LOW1 ((uint32_t)0x40000000) /*!<Lowest Priority Flag for Mailbox 1 */
mbed_official 155:8435094ec241 3773 #define CAN_TSR_LOW2 ((uint32_t)0x80000000) /*!<Lowest Priority Flag for Mailbox 2 */
mbed_official 155:8435094ec241 3774
mbed_official 155:8435094ec241 3775 /******************* Bit definition for CAN_RF0R register *******************/
mbed_official 155:8435094ec241 3776 #define CAN_RF0R_FMP0 ((uint8_t)0x03) /*!<FIFO 0 Message Pending */
mbed_official 155:8435094ec241 3777 #define CAN_RF0R_FULL0 ((uint8_t)0x08) /*!<FIFO 0 Full */
mbed_official 155:8435094ec241 3778 #define CAN_RF0R_FOVR0 ((uint8_t)0x10) /*!<FIFO 0 Overrun */
mbed_official 155:8435094ec241 3779 #define CAN_RF0R_RFOM0 ((uint8_t)0x20) /*!<Release FIFO 0 Output Mailbox */
mbed_official 155:8435094ec241 3780
mbed_official 155:8435094ec241 3781 /******************* Bit definition for CAN_RF1R register *******************/
mbed_official 155:8435094ec241 3782 #define CAN_RF1R_FMP1 ((uint8_t)0x03) /*!<FIFO 1 Message Pending */
mbed_official 155:8435094ec241 3783 #define CAN_RF1R_FULL1 ((uint8_t)0x08) /*!<FIFO 1 Full */
mbed_official 155:8435094ec241 3784 #define CAN_RF1R_FOVR1 ((uint8_t)0x10) /*!<FIFO 1 Overrun */
mbed_official 155:8435094ec241 3785 #define CAN_RF1R_RFOM1 ((uint8_t)0x20) /*!<Release FIFO 1 Output Mailbox */
mbed_official 155:8435094ec241 3786
mbed_official 155:8435094ec241 3787 /******************** Bit definition for CAN_IER register *******************/
mbed_official 155:8435094ec241 3788 #define CAN_IER_TMEIE ((uint32_t)0x00000001) /*!<Transmit Mailbox Empty Interrupt Enable */
mbed_official 155:8435094ec241 3789 #define CAN_IER_FMPIE0 ((uint32_t)0x00000002) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 155:8435094ec241 3790 #define CAN_IER_FFIE0 ((uint32_t)0x00000004) /*!<FIFO Full Interrupt Enable */
mbed_official 155:8435094ec241 3791 #define CAN_IER_FOVIE0 ((uint32_t)0x00000008) /*!<FIFO Overrun Interrupt Enable */
mbed_official 155:8435094ec241 3792 #define CAN_IER_FMPIE1 ((uint32_t)0x00000010) /*!<FIFO Message Pending Interrupt Enable */
mbed_official 155:8435094ec241 3793 #define CAN_IER_FFIE1 ((uint32_t)0x00000020) /*!<FIFO Full Interrupt Enable */
mbed_official 155:8435094ec241 3794 #define CAN_IER_FOVIE1 ((uint32_t)0x00000040) /*!<FIFO Overrun Interrupt Enable */
mbed_official 155:8435094ec241 3795 #define CAN_IER_EWGIE ((uint32_t)0x00000100) /*!<Error Warning Interrupt Enable */
mbed_official 155:8435094ec241 3796 #define CAN_IER_EPVIE ((uint32_t)0x00000200) /*!<Error Passive Interrupt Enable */
mbed_official 155:8435094ec241 3797 #define CAN_IER_BOFIE ((uint32_t)0x00000400) /*!<Bus-Off Interrupt Enable */
mbed_official 155:8435094ec241 3798 #define CAN_IER_LECIE ((uint32_t)0x00000800) /*!<Last Error Code Interrupt Enable */
mbed_official 155:8435094ec241 3799 #define CAN_IER_ERRIE ((uint32_t)0x00008000) /*!<Error Interrupt Enable */
mbed_official 155:8435094ec241 3800 #define CAN_IER_WKUIE ((uint32_t)0x00010000) /*!<Wakeup Interrupt Enable */
mbed_official 155:8435094ec241 3801 #define CAN_IER_SLKIE ((uint32_t)0x00020000) /*!<Sleep Interrupt Enable */
mbed_official 155:8435094ec241 3802
mbed_official 155:8435094ec241 3803 /******************** Bit definition for CAN_ESR register *******************/
mbed_official 155:8435094ec241 3804 #define CAN_ESR_EWGF ((uint32_t)0x00000001) /*!<Error Warning Flag */
mbed_official 155:8435094ec241 3805 #define CAN_ESR_EPVF ((uint32_t)0x00000002) /*!<Error Passive Flag */
mbed_official 155:8435094ec241 3806 #define CAN_ESR_BOFF ((uint32_t)0x00000004) /*!<Bus-Off Flag */
mbed_official 155:8435094ec241 3807
mbed_official 155:8435094ec241 3808 #define CAN_ESR_LEC ((uint32_t)0x00000070) /*!<LEC[2:0] bits (Last Error Code) */
mbed_official 155:8435094ec241 3809 #define CAN_ESR_LEC_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 3810 #define CAN_ESR_LEC_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 3811 #define CAN_ESR_LEC_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 3812
mbed_official 155:8435094ec241 3813 #define CAN_ESR_TEC ((uint32_t)0x00FF0000) /*!<Least significant byte of the 9-bit Transmit Error Counter */
mbed_official 155:8435094ec241 3814 #define CAN_ESR_REC ((uint32_t)0xFF000000) /*!<Receive Error Counter */
mbed_official 155:8435094ec241 3815
mbed_official 155:8435094ec241 3816 /******************* Bit definition for CAN_BTR register ********************/
mbed_official 155:8435094ec241 3817 #define CAN_BTR_BRP ((uint32_t)0x000003FF) /*!<Baud Rate Prescaler */
mbed_official 155:8435094ec241 3818 #define CAN_BTR_TS1 ((uint32_t)0x000F0000) /*!<Time Segment 1 */
mbed_official 155:8435094ec241 3819 #define CAN_BTR_TS2 ((uint32_t)0x00700000) /*!<Time Segment 2 */
mbed_official 155:8435094ec241 3820 #define CAN_BTR_SJW ((uint32_t)0x03000000) /*!<Resynchronization Jump Width */
mbed_official 155:8435094ec241 3821 #define CAN_BTR_LBKM ((uint32_t)0x40000000) /*!<Loop Back Mode (Debug) */
mbed_official 155:8435094ec241 3822 #define CAN_BTR_SILM ((uint32_t)0x80000000) /*!<Silent Mode */
mbed_official 155:8435094ec241 3823
mbed_official 155:8435094ec241 3824 /*!<Mailbox registers */
mbed_official 155:8435094ec241 3825 /****************** Bit definition for CAN_TI0R register ********************/
mbed_official 155:8435094ec241 3826 #define CAN_TI0R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 155:8435094ec241 3827 #define CAN_TI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 155:8435094ec241 3828 #define CAN_TI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 155:8435094ec241 3829 #define CAN_TI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 155:8435094ec241 3830 #define CAN_TI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 155:8435094ec241 3831
mbed_official 155:8435094ec241 3832 /****************** Bit definition for CAN_TDT0R register *******************/
mbed_official 155:8435094ec241 3833 #define CAN_TDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 155:8435094ec241 3834 #define CAN_TDT0R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 155:8435094ec241 3835 #define CAN_TDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 155:8435094ec241 3836
mbed_official 155:8435094ec241 3837 /****************** Bit definition for CAN_TDL0R register *******************/
mbed_official 155:8435094ec241 3838 #define CAN_TDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 155:8435094ec241 3839 #define CAN_TDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 155:8435094ec241 3840 #define CAN_TDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 155:8435094ec241 3841 #define CAN_TDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 155:8435094ec241 3842
mbed_official 155:8435094ec241 3843 /****************** Bit definition for CAN_TDH0R register *******************/
mbed_official 155:8435094ec241 3844 #define CAN_TDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 155:8435094ec241 3845 #define CAN_TDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 155:8435094ec241 3846 #define CAN_TDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 155:8435094ec241 3847 #define CAN_TDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 155:8435094ec241 3848
mbed_official 155:8435094ec241 3849 /******************* Bit definition for CAN_TI1R register *******************/
mbed_official 155:8435094ec241 3850 #define CAN_TI1R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 155:8435094ec241 3851 #define CAN_TI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 155:8435094ec241 3852 #define CAN_TI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 155:8435094ec241 3853 #define CAN_TI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 155:8435094ec241 3854 #define CAN_TI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 155:8435094ec241 3855
mbed_official 155:8435094ec241 3856 /******************* Bit definition for CAN_TDT1R register ******************/
mbed_official 155:8435094ec241 3857 #define CAN_TDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 155:8435094ec241 3858 #define CAN_TDT1R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 155:8435094ec241 3859 #define CAN_TDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 155:8435094ec241 3860
mbed_official 155:8435094ec241 3861 /******************* Bit definition for CAN_TDL1R register ******************/
mbed_official 155:8435094ec241 3862 #define CAN_TDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 155:8435094ec241 3863 #define CAN_TDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 155:8435094ec241 3864 #define CAN_TDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 155:8435094ec241 3865 #define CAN_TDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 155:8435094ec241 3866
mbed_official 155:8435094ec241 3867 /******************* Bit definition for CAN_TDH1R register ******************/
mbed_official 155:8435094ec241 3868 #define CAN_TDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 155:8435094ec241 3869 #define CAN_TDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 155:8435094ec241 3870 #define CAN_TDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 155:8435094ec241 3871 #define CAN_TDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 155:8435094ec241 3872
mbed_official 155:8435094ec241 3873 /******************* Bit definition for CAN_TI2R register *******************/
mbed_official 155:8435094ec241 3874 #define CAN_TI2R_TXRQ ((uint32_t)0x00000001) /*!<Transmit Mailbox Request */
mbed_official 155:8435094ec241 3875 #define CAN_TI2R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 155:8435094ec241 3876 #define CAN_TI2R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 155:8435094ec241 3877 #define CAN_TI2R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 155:8435094ec241 3878 #define CAN_TI2R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 155:8435094ec241 3879
mbed_official 155:8435094ec241 3880 /******************* Bit definition for CAN_TDT2R register ******************/
mbed_official 155:8435094ec241 3881 #define CAN_TDT2R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 155:8435094ec241 3882 #define CAN_TDT2R_TGT ((uint32_t)0x00000100) /*!<Transmit Global Time */
mbed_official 155:8435094ec241 3883 #define CAN_TDT2R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 155:8435094ec241 3884
mbed_official 155:8435094ec241 3885 /******************* Bit definition for CAN_TDL2R register ******************/
mbed_official 155:8435094ec241 3886 #define CAN_TDL2R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 155:8435094ec241 3887 #define CAN_TDL2R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 155:8435094ec241 3888 #define CAN_TDL2R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 155:8435094ec241 3889 #define CAN_TDL2R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 155:8435094ec241 3890
mbed_official 155:8435094ec241 3891 /******************* Bit definition for CAN_TDH2R register ******************/
mbed_official 155:8435094ec241 3892 #define CAN_TDH2R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 155:8435094ec241 3893 #define CAN_TDH2R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 155:8435094ec241 3894 #define CAN_TDH2R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 155:8435094ec241 3895 #define CAN_TDH2R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 155:8435094ec241 3896
mbed_official 155:8435094ec241 3897 /******************* Bit definition for CAN_RI0R register *******************/
mbed_official 155:8435094ec241 3898 #define CAN_RI0R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 155:8435094ec241 3899 #define CAN_RI0R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 155:8435094ec241 3900 #define CAN_RI0R_EXID ((uint32_t)0x001FFFF8) /*!<Extended Identifier */
mbed_official 155:8435094ec241 3901 #define CAN_RI0R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 155:8435094ec241 3902
mbed_official 155:8435094ec241 3903 /******************* Bit definition for CAN_RDT0R register ******************/
mbed_official 155:8435094ec241 3904 #define CAN_RDT0R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 155:8435094ec241 3905 #define CAN_RDT0R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 155:8435094ec241 3906 #define CAN_RDT0R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 155:8435094ec241 3907
mbed_official 155:8435094ec241 3908 /******************* Bit definition for CAN_RDL0R register ******************/
mbed_official 155:8435094ec241 3909 #define CAN_RDL0R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 155:8435094ec241 3910 #define CAN_RDL0R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 155:8435094ec241 3911 #define CAN_RDL0R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 155:8435094ec241 3912 #define CAN_RDL0R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 155:8435094ec241 3913
mbed_official 155:8435094ec241 3914 /******************* Bit definition for CAN_RDH0R register ******************/
mbed_official 155:8435094ec241 3915 #define CAN_RDH0R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 155:8435094ec241 3916 #define CAN_RDH0R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 155:8435094ec241 3917 #define CAN_RDH0R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 155:8435094ec241 3918 #define CAN_RDH0R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 155:8435094ec241 3919
mbed_official 155:8435094ec241 3920 /******************* Bit definition for CAN_RI1R register *******************/
mbed_official 155:8435094ec241 3921 #define CAN_RI1R_RTR ((uint32_t)0x00000002) /*!<Remote Transmission Request */
mbed_official 155:8435094ec241 3922 #define CAN_RI1R_IDE ((uint32_t)0x00000004) /*!<Identifier Extension */
mbed_official 155:8435094ec241 3923 #define CAN_RI1R_EXID ((uint32_t)0x001FFFF8) /*!<Extended identifier */
mbed_official 155:8435094ec241 3924 #define CAN_RI1R_STID ((uint32_t)0xFFE00000) /*!<Standard Identifier or Extended Identifier */
mbed_official 155:8435094ec241 3925
mbed_official 155:8435094ec241 3926 /******************* Bit definition for CAN_RDT1R register ******************/
mbed_official 155:8435094ec241 3927 #define CAN_RDT1R_DLC ((uint32_t)0x0000000F) /*!<Data Length Code */
mbed_official 155:8435094ec241 3928 #define CAN_RDT1R_FMI ((uint32_t)0x0000FF00) /*!<Filter Match Index */
mbed_official 155:8435094ec241 3929 #define CAN_RDT1R_TIME ((uint32_t)0xFFFF0000) /*!<Message Time Stamp */
mbed_official 155:8435094ec241 3930
mbed_official 155:8435094ec241 3931 /******************* Bit definition for CAN_RDL1R register ******************/
mbed_official 155:8435094ec241 3932 #define CAN_RDL1R_DATA0 ((uint32_t)0x000000FF) /*!<Data byte 0 */
mbed_official 155:8435094ec241 3933 #define CAN_RDL1R_DATA1 ((uint32_t)0x0000FF00) /*!<Data byte 1 */
mbed_official 155:8435094ec241 3934 #define CAN_RDL1R_DATA2 ((uint32_t)0x00FF0000) /*!<Data byte 2 */
mbed_official 155:8435094ec241 3935 #define CAN_RDL1R_DATA3 ((uint32_t)0xFF000000) /*!<Data byte 3 */
mbed_official 155:8435094ec241 3936
mbed_official 155:8435094ec241 3937 /******************* Bit definition for CAN_RDH1R register ******************/
mbed_official 155:8435094ec241 3938 #define CAN_RDH1R_DATA4 ((uint32_t)0x000000FF) /*!<Data byte 4 */
mbed_official 155:8435094ec241 3939 #define CAN_RDH1R_DATA5 ((uint32_t)0x0000FF00) /*!<Data byte 5 */
mbed_official 155:8435094ec241 3940 #define CAN_RDH1R_DATA6 ((uint32_t)0x00FF0000) /*!<Data byte 6 */
mbed_official 155:8435094ec241 3941 #define CAN_RDH1R_DATA7 ((uint32_t)0xFF000000) /*!<Data byte 7 */
mbed_official 155:8435094ec241 3942
mbed_official 155:8435094ec241 3943 /*!<CAN filter registers */
mbed_official 155:8435094ec241 3944 /******************* Bit definition for CAN_FMR register ********************/
mbed_official 155:8435094ec241 3945 #define CAN_FMR_FINIT ((uint8_t)0x01) /*!<Filter Init Mode */
mbed_official 155:8435094ec241 3946
mbed_official 155:8435094ec241 3947 /******************* Bit definition for CAN_FM1R register *******************/
mbed_official 155:8435094ec241 3948 #define CAN_FM1R_FBM ((uint16_t)0x3FFF) /*!<Filter Mode */
mbed_official 155:8435094ec241 3949 #define CAN_FM1R_FBM0 ((uint16_t)0x0001) /*!<Filter Init Mode bit 0 */
mbed_official 155:8435094ec241 3950 #define CAN_FM1R_FBM1 ((uint16_t)0x0002) /*!<Filter Init Mode bit 1 */
mbed_official 155:8435094ec241 3951 #define CAN_FM1R_FBM2 ((uint16_t)0x0004) /*!<Filter Init Mode bit 2 */
mbed_official 155:8435094ec241 3952 #define CAN_FM1R_FBM3 ((uint16_t)0x0008) /*!<Filter Init Mode bit 3 */
mbed_official 155:8435094ec241 3953 #define CAN_FM1R_FBM4 ((uint16_t)0x0010) /*!<Filter Init Mode bit 4 */
mbed_official 155:8435094ec241 3954 #define CAN_FM1R_FBM5 ((uint16_t)0x0020) /*!<Filter Init Mode bit 5 */
mbed_official 155:8435094ec241 3955 #define CAN_FM1R_FBM6 ((uint16_t)0x0040) /*!<Filter Init Mode bit 6 */
mbed_official 155:8435094ec241 3956 #define CAN_FM1R_FBM7 ((uint16_t)0x0080) /*!<Filter Init Mode bit 7 */
mbed_official 155:8435094ec241 3957 #define CAN_FM1R_FBM8 ((uint16_t)0x0100) /*!<Filter Init Mode bit 8 */
mbed_official 155:8435094ec241 3958 #define CAN_FM1R_FBM9 ((uint16_t)0x0200) /*!<Filter Init Mode bit 9 */
mbed_official 155:8435094ec241 3959 #define CAN_FM1R_FBM10 ((uint16_t)0x0400) /*!<Filter Init Mode bit 10 */
mbed_official 155:8435094ec241 3960 #define CAN_FM1R_FBM11 ((uint16_t)0x0800) /*!<Filter Init Mode bit 11 */
mbed_official 155:8435094ec241 3961 #define CAN_FM1R_FBM12 ((uint16_t)0x1000) /*!<Filter Init Mode bit 12 */
mbed_official 155:8435094ec241 3962 #define CAN_FM1R_FBM13 ((uint16_t)0x2000) /*!<Filter Init Mode bit 13 */
mbed_official 155:8435094ec241 3963
mbed_official 155:8435094ec241 3964 /******************* Bit definition for CAN_FS1R register *******************/
mbed_official 155:8435094ec241 3965 #define CAN_FS1R_FSC ((uint16_t)0x3FFF) /*!<Filter Scale Configuration */
mbed_official 155:8435094ec241 3966 #define CAN_FS1R_FSC0 ((uint16_t)0x0001) /*!<Filter Scale Configuration bit 0 */
mbed_official 155:8435094ec241 3967 #define CAN_FS1R_FSC1 ((uint16_t)0x0002) /*!<Filter Scale Configuration bit 1 */
mbed_official 155:8435094ec241 3968 #define CAN_FS1R_FSC2 ((uint16_t)0x0004) /*!<Filter Scale Configuration bit 2 */
mbed_official 155:8435094ec241 3969 #define CAN_FS1R_FSC3 ((uint16_t)0x0008) /*!<Filter Scale Configuration bit 3 */
mbed_official 155:8435094ec241 3970 #define CAN_FS1R_FSC4 ((uint16_t)0x0010) /*!<Filter Scale Configuration bit 4 */
mbed_official 155:8435094ec241 3971 #define CAN_FS1R_FSC5 ((uint16_t)0x0020) /*!<Filter Scale Configuration bit 5 */
mbed_official 155:8435094ec241 3972 #define CAN_FS1R_FSC6 ((uint16_t)0x0040) /*!<Filter Scale Configuration bit 6 */
mbed_official 155:8435094ec241 3973 #define CAN_FS1R_FSC7 ((uint16_t)0x0080) /*!<Filter Scale Configuration bit 7 */
mbed_official 155:8435094ec241 3974 #define CAN_FS1R_FSC8 ((uint16_t)0x0100) /*!<Filter Scale Configuration bit 8 */
mbed_official 155:8435094ec241 3975 #define CAN_FS1R_FSC9 ((uint16_t)0x0200) /*!<Filter Scale Configuration bit 9 */
mbed_official 155:8435094ec241 3976 #define CAN_FS1R_FSC10 ((uint16_t)0x0400) /*!<Filter Scale Configuration bit 10 */
mbed_official 155:8435094ec241 3977 #define CAN_FS1R_FSC11 ((uint16_t)0x0800) /*!<Filter Scale Configuration bit 11 */
mbed_official 155:8435094ec241 3978 #define CAN_FS1R_FSC12 ((uint16_t)0x1000) /*!<Filter Scale Configuration bit 12 */
mbed_official 155:8435094ec241 3979 #define CAN_FS1R_FSC13 ((uint16_t)0x2000) /*!<Filter Scale Configuration bit 13 */
mbed_official 155:8435094ec241 3980
mbed_official 155:8435094ec241 3981 /****************** Bit definition for CAN_FFA1R register *******************/
mbed_official 155:8435094ec241 3982 #define CAN_FFA1R_FFA ((uint16_t)0x3FFF) /*!<Filter FIFO Assignment */
mbed_official 155:8435094ec241 3983 #define CAN_FFA1R_FFA0 ((uint16_t)0x0001) /*!<Filter FIFO Assignment for Filter 0 */
mbed_official 155:8435094ec241 3984 #define CAN_FFA1R_FFA1 ((uint16_t)0x0002) /*!<Filter FIFO Assignment for Filter 1 */
mbed_official 155:8435094ec241 3985 #define CAN_FFA1R_FFA2 ((uint16_t)0x0004) /*!<Filter FIFO Assignment for Filter 2 */
mbed_official 155:8435094ec241 3986 #define CAN_FFA1R_FFA3 ((uint16_t)0x0008) /*!<Filter FIFO Assignment for Filter 3 */
mbed_official 155:8435094ec241 3987 #define CAN_FFA1R_FFA4 ((uint16_t)0x0010) /*!<Filter FIFO Assignment for Filter 4 */
mbed_official 155:8435094ec241 3988 #define CAN_FFA1R_FFA5 ((uint16_t)0x0020) /*!<Filter FIFO Assignment for Filter 5 */
mbed_official 155:8435094ec241 3989 #define CAN_FFA1R_FFA6 ((uint16_t)0x0040) /*!<Filter FIFO Assignment for Filter 6 */
mbed_official 155:8435094ec241 3990 #define CAN_FFA1R_FFA7 ((uint16_t)0x0080) /*!<Filter FIFO Assignment for Filter 7 */
mbed_official 155:8435094ec241 3991 #define CAN_FFA1R_FFA8 ((uint16_t)0x0100) /*!<Filter FIFO Assignment for Filter 8 */
mbed_official 155:8435094ec241 3992 #define CAN_FFA1R_FFA9 ((uint16_t)0x0200) /*!<Filter FIFO Assignment for Filter 9 */
mbed_official 155:8435094ec241 3993 #define CAN_FFA1R_FFA10 ((uint16_t)0x0400) /*!<Filter FIFO Assignment for Filter 10 */
mbed_official 155:8435094ec241 3994 #define CAN_FFA1R_FFA11 ((uint16_t)0x0800) /*!<Filter FIFO Assignment for Filter 11 */
mbed_official 155:8435094ec241 3995 #define CAN_FFA1R_FFA12 ((uint16_t)0x1000) /*!<Filter FIFO Assignment for Filter 12 */
mbed_official 155:8435094ec241 3996 #define CAN_FFA1R_FFA13 ((uint16_t)0x2000) /*!<Filter FIFO Assignment for Filter 13 */
mbed_official 155:8435094ec241 3997
mbed_official 155:8435094ec241 3998 /******************* Bit definition for CAN_FA1R register *******************/
mbed_official 155:8435094ec241 3999 #define CAN_FA1R_FACT ((uint16_t)0x3FFF) /*!<Filter Active */
mbed_official 155:8435094ec241 4000 #define CAN_FA1R_FACT0 ((uint16_t)0x0001) /*!<Filter 0 Active */
mbed_official 155:8435094ec241 4001 #define CAN_FA1R_FACT1 ((uint16_t)0x0002) /*!<Filter 1 Active */
mbed_official 155:8435094ec241 4002 #define CAN_FA1R_FACT2 ((uint16_t)0x0004) /*!<Filter 2 Active */
mbed_official 155:8435094ec241 4003 #define CAN_FA1R_FACT3 ((uint16_t)0x0008) /*!<Filter 3 Active */
mbed_official 155:8435094ec241 4004 #define CAN_FA1R_FACT4 ((uint16_t)0x0010) /*!<Filter 4 Active */
mbed_official 155:8435094ec241 4005 #define CAN_FA1R_FACT5 ((uint16_t)0x0020) /*!<Filter 5 Active */
mbed_official 155:8435094ec241 4006 #define CAN_FA1R_FACT6 ((uint16_t)0x0040) /*!<Filter 6 Active */
mbed_official 155:8435094ec241 4007 #define CAN_FA1R_FACT7 ((uint16_t)0x0080) /*!<Filter 7 Active */
mbed_official 155:8435094ec241 4008 #define CAN_FA1R_FACT8 ((uint16_t)0x0100) /*!<Filter 8 Active */
mbed_official 155:8435094ec241 4009 #define CAN_FA1R_FACT9 ((uint16_t)0x0200) /*!<Filter 9 Active */
mbed_official 155:8435094ec241 4010 #define CAN_FA1R_FACT10 ((uint16_t)0x0400) /*!<Filter 10 Active */
mbed_official 155:8435094ec241 4011 #define CAN_FA1R_FACT11 ((uint16_t)0x0800) /*!<Filter 11 Active */
mbed_official 155:8435094ec241 4012 #define CAN_FA1R_FACT12 ((uint16_t)0x1000) /*!<Filter 12 Active */
mbed_official 155:8435094ec241 4013 #define CAN_FA1R_FACT13 ((uint16_t)0x2000) /*!<Filter 13 Active */
mbed_official 155:8435094ec241 4014
mbed_official 155:8435094ec241 4015 /******************* Bit definition for CAN_F0R1 register *******************/
mbed_official 155:8435094ec241 4016 #define CAN_F0R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4017 #define CAN_F0R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4018 #define CAN_F0R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4019 #define CAN_F0R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4020 #define CAN_F0R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4021 #define CAN_F0R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4022 #define CAN_F0R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4023 #define CAN_F0R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4024 #define CAN_F0R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4025 #define CAN_F0R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4026 #define CAN_F0R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4027 #define CAN_F0R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4028 #define CAN_F0R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4029 #define CAN_F0R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4030 #define CAN_F0R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4031 #define CAN_F0R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4032 #define CAN_F0R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4033 #define CAN_F0R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4034 #define CAN_F0R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4035 #define CAN_F0R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4036 #define CAN_F0R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4037 #define CAN_F0R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4038 #define CAN_F0R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4039 #define CAN_F0R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4040 #define CAN_F0R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4041 #define CAN_F0R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4042 #define CAN_F0R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4043 #define CAN_F0R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4044 #define CAN_F0R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4045 #define CAN_F0R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4046 #define CAN_F0R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4047 #define CAN_F0R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4048
mbed_official 155:8435094ec241 4049 /******************* Bit definition for CAN_F1R1 register *******************/
mbed_official 155:8435094ec241 4050 #define CAN_F1R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4051 #define CAN_F1R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4052 #define CAN_F1R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4053 #define CAN_F1R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4054 #define CAN_F1R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4055 #define CAN_F1R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4056 #define CAN_F1R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4057 #define CAN_F1R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4058 #define CAN_F1R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4059 #define CAN_F1R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4060 #define CAN_F1R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4061 #define CAN_F1R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4062 #define CAN_F1R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4063 #define CAN_F1R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4064 #define CAN_F1R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4065 #define CAN_F1R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4066 #define CAN_F1R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4067 #define CAN_F1R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4068 #define CAN_F1R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4069 #define CAN_F1R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4070 #define CAN_F1R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4071 #define CAN_F1R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4072 #define CAN_F1R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4073 #define CAN_F1R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4074 #define CAN_F1R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4075 #define CAN_F1R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4076 #define CAN_F1R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4077 #define CAN_F1R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4078 #define CAN_F1R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4079 #define CAN_F1R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4080 #define CAN_F1R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4081 #define CAN_F1R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4082
mbed_official 155:8435094ec241 4083 /******************* Bit definition for CAN_F2R1 register *******************/
mbed_official 155:8435094ec241 4084 #define CAN_F2R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4085 #define CAN_F2R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4086 #define CAN_F2R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4087 #define CAN_F2R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4088 #define CAN_F2R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4089 #define CAN_F2R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4090 #define CAN_F2R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4091 #define CAN_F2R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4092 #define CAN_F2R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4093 #define CAN_F2R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4094 #define CAN_F2R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4095 #define CAN_F2R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4096 #define CAN_F2R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4097 #define CAN_F2R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4098 #define CAN_F2R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4099 #define CAN_F2R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4100 #define CAN_F2R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4101 #define CAN_F2R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4102 #define CAN_F2R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4103 #define CAN_F2R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4104 #define CAN_F2R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4105 #define CAN_F2R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4106 #define CAN_F2R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4107 #define CAN_F2R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4108 #define CAN_F2R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4109 #define CAN_F2R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4110 #define CAN_F2R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4111 #define CAN_F2R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4112 #define CAN_F2R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4113 #define CAN_F2R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4114 #define CAN_F2R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4115 #define CAN_F2R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4116
mbed_official 155:8435094ec241 4117 /******************* Bit definition for CAN_F3R1 register *******************/
mbed_official 155:8435094ec241 4118 #define CAN_F3R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4119 #define CAN_F3R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4120 #define CAN_F3R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4121 #define CAN_F3R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4122 #define CAN_F3R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4123 #define CAN_F3R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4124 #define CAN_F3R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4125 #define CAN_F3R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4126 #define CAN_F3R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4127 #define CAN_F3R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4128 #define CAN_F3R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4129 #define CAN_F3R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4130 #define CAN_F3R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4131 #define CAN_F3R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4132 #define CAN_F3R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4133 #define CAN_F3R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4134 #define CAN_F3R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4135 #define CAN_F3R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4136 #define CAN_F3R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4137 #define CAN_F3R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4138 #define CAN_F3R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4139 #define CAN_F3R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4140 #define CAN_F3R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4141 #define CAN_F3R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4142 #define CAN_F3R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4143 #define CAN_F3R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4144 #define CAN_F3R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4145 #define CAN_F3R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4146 #define CAN_F3R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4147 #define CAN_F3R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4148 #define CAN_F3R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4149 #define CAN_F3R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4150
mbed_official 155:8435094ec241 4151 /******************* Bit definition for CAN_F4R1 register *******************/
mbed_official 155:8435094ec241 4152 #define CAN_F4R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4153 #define CAN_F4R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4154 #define CAN_F4R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4155 #define CAN_F4R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4156 #define CAN_F4R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4157 #define CAN_F4R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4158 #define CAN_F4R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4159 #define CAN_F4R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4160 #define CAN_F4R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4161 #define CAN_F4R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4162 #define CAN_F4R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4163 #define CAN_F4R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4164 #define CAN_F4R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4165 #define CAN_F4R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4166 #define CAN_F4R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4167 #define CAN_F4R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4168 #define CAN_F4R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4169 #define CAN_F4R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4170 #define CAN_F4R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4171 #define CAN_F4R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4172 #define CAN_F4R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4173 #define CAN_F4R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4174 #define CAN_F4R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4175 #define CAN_F4R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4176 #define CAN_F4R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4177 #define CAN_F4R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4178 #define CAN_F4R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4179 #define CAN_F4R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4180 #define CAN_F4R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4181 #define CAN_F4R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4182 #define CAN_F4R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4183 #define CAN_F4R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4184
mbed_official 155:8435094ec241 4185 /******************* Bit definition for CAN_F5R1 register *******************/
mbed_official 155:8435094ec241 4186 #define CAN_F5R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4187 #define CAN_F5R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4188 #define CAN_F5R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4189 #define CAN_F5R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4190 #define CAN_F5R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4191 #define CAN_F5R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4192 #define CAN_F5R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4193 #define CAN_F5R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4194 #define CAN_F5R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4195 #define CAN_F5R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4196 #define CAN_F5R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4197 #define CAN_F5R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4198 #define CAN_F5R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4199 #define CAN_F5R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4200 #define CAN_F5R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4201 #define CAN_F5R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4202 #define CAN_F5R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4203 #define CAN_F5R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4204 #define CAN_F5R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4205 #define CAN_F5R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4206 #define CAN_F5R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4207 #define CAN_F5R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4208 #define CAN_F5R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4209 #define CAN_F5R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4210 #define CAN_F5R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4211 #define CAN_F5R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4212 #define CAN_F5R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4213 #define CAN_F5R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4214 #define CAN_F5R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4215 #define CAN_F5R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4216 #define CAN_F5R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4217 #define CAN_F5R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4218
mbed_official 155:8435094ec241 4219 /******************* Bit definition for CAN_F6R1 register *******************/
mbed_official 155:8435094ec241 4220 #define CAN_F6R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4221 #define CAN_F6R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4222 #define CAN_F6R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4223 #define CAN_F6R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4224 #define CAN_F6R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4225 #define CAN_F6R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4226 #define CAN_F6R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4227 #define CAN_F6R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4228 #define CAN_F6R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4229 #define CAN_F6R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4230 #define CAN_F6R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4231 #define CAN_F6R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4232 #define CAN_F6R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4233 #define CAN_F6R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4234 #define CAN_F6R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4235 #define CAN_F6R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4236 #define CAN_F6R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4237 #define CAN_F6R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4238 #define CAN_F6R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4239 #define CAN_F6R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4240 #define CAN_F6R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4241 #define CAN_F6R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4242 #define CAN_F6R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4243 #define CAN_F6R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4244 #define CAN_F6R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4245 #define CAN_F6R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4246 #define CAN_F6R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4247 #define CAN_F6R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4248 #define CAN_F6R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4249 #define CAN_F6R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4250 #define CAN_F6R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4251 #define CAN_F6R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4252
mbed_official 155:8435094ec241 4253 /******************* Bit definition for CAN_F7R1 register *******************/
mbed_official 155:8435094ec241 4254 #define CAN_F7R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4255 #define CAN_F7R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4256 #define CAN_F7R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4257 #define CAN_F7R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4258 #define CAN_F7R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4259 #define CAN_F7R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4260 #define CAN_F7R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4261 #define CAN_F7R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4262 #define CAN_F7R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4263 #define CAN_F7R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4264 #define CAN_F7R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4265 #define CAN_F7R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4266 #define CAN_F7R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4267 #define CAN_F7R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4268 #define CAN_F7R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4269 #define CAN_F7R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4270 #define CAN_F7R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4271 #define CAN_F7R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4272 #define CAN_F7R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4273 #define CAN_F7R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4274 #define CAN_F7R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4275 #define CAN_F7R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4276 #define CAN_F7R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4277 #define CAN_F7R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4278 #define CAN_F7R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4279 #define CAN_F7R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4280 #define CAN_F7R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4281 #define CAN_F7R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4282 #define CAN_F7R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4283 #define CAN_F7R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4284 #define CAN_F7R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4285 #define CAN_F7R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4286
mbed_official 155:8435094ec241 4287 /******************* Bit definition for CAN_F8R1 register *******************/
mbed_official 155:8435094ec241 4288 #define CAN_F8R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4289 #define CAN_F8R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4290 #define CAN_F8R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4291 #define CAN_F8R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4292 #define CAN_F8R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4293 #define CAN_F8R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4294 #define CAN_F8R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4295 #define CAN_F8R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4296 #define CAN_F8R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4297 #define CAN_F8R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4298 #define CAN_F8R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4299 #define CAN_F8R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4300 #define CAN_F8R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4301 #define CAN_F8R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4302 #define CAN_F8R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4303 #define CAN_F8R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4304 #define CAN_F8R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4305 #define CAN_F8R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4306 #define CAN_F8R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4307 #define CAN_F8R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4308 #define CAN_F8R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4309 #define CAN_F8R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4310 #define CAN_F8R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4311 #define CAN_F8R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4312 #define CAN_F8R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4313 #define CAN_F8R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4314 #define CAN_F8R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4315 #define CAN_F8R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4316 #define CAN_F8R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4317 #define CAN_F8R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4318 #define CAN_F8R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4319 #define CAN_F8R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4320
mbed_official 155:8435094ec241 4321 /******************* Bit definition for CAN_F9R1 register *******************/
mbed_official 155:8435094ec241 4322 #define CAN_F9R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4323 #define CAN_F9R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4324 #define CAN_F9R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4325 #define CAN_F9R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4326 #define CAN_F9R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4327 #define CAN_F9R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4328 #define CAN_F9R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4329 #define CAN_F9R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4330 #define CAN_F9R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4331 #define CAN_F9R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4332 #define CAN_F9R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4333 #define CAN_F9R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4334 #define CAN_F9R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4335 #define CAN_F9R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4336 #define CAN_F9R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4337 #define CAN_F9R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4338 #define CAN_F9R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4339 #define CAN_F9R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4340 #define CAN_F9R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4341 #define CAN_F9R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4342 #define CAN_F9R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4343 #define CAN_F9R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4344 #define CAN_F9R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4345 #define CAN_F9R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4346 #define CAN_F9R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4347 #define CAN_F9R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4348 #define CAN_F9R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4349 #define CAN_F9R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4350 #define CAN_F9R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4351 #define CAN_F9R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4352 #define CAN_F9R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4353 #define CAN_F9R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4354
mbed_official 155:8435094ec241 4355 /******************* Bit definition for CAN_F10R1 register ******************/
mbed_official 155:8435094ec241 4356 #define CAN_F10R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4357 #define CAN_F10R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4358 #define CAN_F10R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4359 #define CAN_F10R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4360 #define CAN_F10R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4361 #define CAN_F10R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4362 #define CAN_F10R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4363 #define CAN_F10R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4364 #define CAN_F10R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4365 #define CAN_F10R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4366 #define CAN_F10R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4367 #define CAN_F10R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4368 #define CAN_F10R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4369 #define CAN_F10R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4370 #define CAN_F10R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4371 #define CAN_F10R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4372 #define CAN_F10R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4373 #define CAN_F10R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4374 #define CAN_F10R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4375 #define CAN_F10R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4376 #define CAN_F10R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4377 #define CAN_F10R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4378 #define CAN_F10R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4379 #define CAN_F10R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4380 #define CAN_F10R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4381 #define CAN_F10R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4382 #define CAN_F10R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4383 #define CAN_F10R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4384 #define CAN_F10R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4385 #define CAN_F10R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4386 #define CAN_F10R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4387 #define CAN_F10R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4388
mbed_official 155:8435094ec241 4389 /******************* Bit definition for CAN_F11R1 register ******************/
mbed_official 155:8435094ec241 4390 #define CAN_F11R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4391 #define CAN_F11R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4392 #define CAN_F11R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4393 #define CAN_F11R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4394 #define CAN_F11R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4395 #define CAN_F11R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4396 #define CAN_F11R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4397 #define CAN_F11R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4398 #define CAN_F11R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4399 #define CAN_F11R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4400 #define CAN_F11R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4401 #define CAN_F11R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4402 #define CAN_F11R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4403 #define CAN_F11R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4404 #define CAN_F11R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4405 #define CAN_F11R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4406 #define CAN_F11R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4407 #define CAN_F11R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4408 #define CAN_F11R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4409 #define CAN_F11R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4410 #define CAN_F11R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4411 #define CAN_F11R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4412 #define CAN_F11R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4413 #define CAN_F11R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4414 #define CAN_F11R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4415 #define CAN_F11R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4416 #define CAN_F11R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4417 #define CAN_F11R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4418 #define CAN_F11R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4419 #define CAN_F11R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4420 #define CAN_F11R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4421 #define CAN_F11R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4422
mbed_official 155:8435094ec241 4423 /******************* Bit definition for CAN_F12R1 register ******************/
mbed_official 155:8435094ec241 4424 #define CAN_F12R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4425 #define CAN_F12R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4426 #define CAN_F12R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4427 #define CAN_F12R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4428 #define CAN_F12R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4429 #define CAN_F12R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4430 #define CAN_F12R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4431 #define CAN_F12R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4432 #define CAN_F12R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4433 #define CAN_F12R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4434 #define CAN_F12R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4435 #define CAN_F12R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4436 #define CAN_F12R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4437 #define CAN_F12R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4438 #define CAN_F12R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4439 #define CAN_F12R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4440 #define CAN_F12R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4441 #define CAN_F12R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4442 #define CAN_F12R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4443 #define CAN_F12R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4444 #define CAN_F12R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4445 #define CAN_F12R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4446 #define CAN_F12R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4447 #define CAN_F12R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4448 #define CAN_F12R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4449 #define CAN_F12R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4450 #define CAN_F12R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4451 #define CAN_F12R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4452 #define CAN_F12R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4453 #define CAN_F12R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4454 #define CAN_F12R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4455 #define CAN_F12R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4456
mbed_official 155:8435094ec241 4457 /******************* Bit definition for CAN_F13R1 register ******************/
mbed_official 155:8435094ec241 4458 #define CAN_F13R1_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4459 #define CAN_F13R1_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4460 #define CAN_F13R1_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4461 #define CAN_F13R1_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4462 #define CAN_F13R1_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4463 #define CAN_F13R1_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4464 #define CAN_F13R1_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4465 #define CAN_F13R1_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4466 #define CAN_F13R1_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4467 #define CAN_F13R1_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4468 #define CAN_F13R1_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4469 #define CAN_F13R1_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4470 #define CAN_F13R1_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4471 #define CAN_F13R1_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4472 #define CAN_F13R1_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4473 #define CAN_F13R1_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4474 #define CAN_F13R1_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4475 #define CAN_F13R1_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4476 #define CAN_F13R1_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4477 #define CAN_F13R1_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4478 #define CAN_F13R1_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4479 #define CAN_F13R1_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4480 #define CAN_F13R1_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4481 #define CAN_F13R1_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4482 #define CAN_F13R1_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4483 #define CAN_F13R1_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4484 #define CAN_F13R1_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4485 #define CAN_F13R1_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4486 #define CAN_F13R1_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4487 #define CAN_F13R1_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4488 #define CAN_F13R1_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4489 #define CAN_F13R1_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4490
mbed_official 155:8435094ec241 4491 /******************* Bit definition for CAN_F0R2 register *******************/
mbed_official 155:8435094ec241 4492 #define CAN_F0R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4493 #define CAN_F0R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4494 #define CAN_F0R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4495 #define CAN_F0R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4496 #define CAN_F0R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4497 #define CAN_F0R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4498 #define CAN_F0R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4499 #define CAN_F0R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4500 #define CAN_F0R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4501 #define CAN_F0R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4502 #define CAN_F0R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4503 #define CAN_F0R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4504 #define CAN_F0R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4505 #define CAN_F0R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4506 #define CAN_F0R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4507 #define CAN_F0R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4508 #define CAN_F0R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4509 #define CAN_F0R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4510 #define CAN_F0R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4511 #define CAN_F0R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4512 #define CAN_F0R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4513 #define CAN_F0R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4514 #define CAN_F0R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4515 #define CAN_F0R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4516 #define CAN_F0R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4517 #define CAN_F0R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4518 #define CAN_F0R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4519 #define CAN_F0R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4520 #define CAN_F0R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4521 #define CAN_F0R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4522 #define CAN_F0R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4523 #define CAN_F0R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4524
mbed_official 155:8435094ec241 4525 /******************* Bit definition for CAN_F1R2 register *******************/
mbed_official 155:8435094ec241 4526 #define CAN_F1R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4527 #define CAN_F1R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4528 #define CAN_F1R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4529 #define CAN_F1R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4530 #define CAN_F1R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4531 #define CAN_F1R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4532 #define CAN_F1R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4533 #define CAN_F1R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4534 #define CAN_F1R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4535 #define CAN_F1R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4536 #define CAN_F1R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4537 #define CAN_F1R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4538 #define CAN_F1R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4539 #define CAN_F1R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4540 #define CAN_F1R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4541 #define CAN_F1R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4542 #define CAN_F1R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4543 #define CAN_F1R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4544 #define CAN_F1R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4545 #define CAN_F1R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4546 #define CAN_F1R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4547 #define CAN_F1R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4548 #define CAN_F1R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4549 #define CAN_F1R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4550 #define CAN_F1R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4551 #define CAN_F1R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4552 #define CAN_F1R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4553 #define CAN_F1R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4554 #define CAN_F1R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4555 #define CAN_F1R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4556 #define CAN_F1R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4557 #define CAN_F1R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4558
mbed_official 155:8435094ec241 4559 /******************* Bit definition for CAN_F2R2 register *******************/
mbed_official 155:8435094ec241 4560 #define CAN_F2R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4561 #define CAN_F2R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4562 #define CAN_F2R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4563 #define CAN_F2R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4564 #define CAN_F2R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4565 #define CAN_F2R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4566 #define CAN_F2R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4567 #define CAN_F2R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4568 #define CAN_F2R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4569 #define CAN_F2R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4570 #define CAN_F2R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4571 #define CAN_F2R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4572 #define CAN_F2R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4573 #define CAN_F2R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4574 #define CAN_F2R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4575 #define CAN_F2R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4576 #define CAN_F2R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4577 #define CAN_F2R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4578 #define CAN_F2R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4579 #define CAN_F2R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4580 #define CAN_F2R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4581 #define CAN_F2R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4582 #define CAN_F2R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4583 #define CAN_F2R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4584 #define CAN_F2R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4585 #define CAN_F2R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4586 #define CAN_F2R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4587 #define CAN_F2R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4588 #define CAN_F2R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4589 #define CAN_F2R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4590 #define CAN_F2R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4591 #define CAN_F2R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4592
mbed_official 155:8435094ec241 4593 /******************* Bit definition for CAN_F3R2 register *******************/
mbed_official 155:8435094ec241 4594 #define CAN_F3R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4595 #define CAN_F3R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4596 #define CAN_F3R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4597 #define CAN_F3R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4598 #define CAN_F3R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4599 #define CAN_F3R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4600 #define CAN_F3R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4601 #define CAN_F3R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4602 #define CAN_F3R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4603 #define CAN_F3R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4604 #define CAN_F3R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4605 #define CAN_F3R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4606 #define CAN_F3R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4607 #define CAN_F3R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4608 #define CAN_F3R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4609 #define CAN_F3R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4610 #define CAN_F3R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4611 #define CAN_F3R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4612 #define CAN_F3R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4613 #define CAN_F3R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4614 #define CAN_F3R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4615 #define CAN_F3R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4616 #define CAN_F3R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4617 #define CAN_F3R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4618 #define CAN_F3R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4619 #define CAN_F3R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4620 #define CAN_F3R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4621 #define CAN_F3R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4622 #define CAN_F3R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4623 #define CAN_F3R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4624 #define CAN_F3R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4625 #define CAN_F3R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4626
mbed_official 155:8435094ec241 4627 /******************* Bit definition for CAN_F4R2 register *******************/
mbed_official 155:8435094ec241 4628 #define CAN_F4R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4629 #define CAN_F4R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4630 #define CAN_F4R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4631 #define CAN_F4R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4632 #define CAN_F4R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4633 #define CAN_F4R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4634 #define CAN_F4R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4635 #define CAN_F4R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4636 #define CAN_F4R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4637 #define CAN_F4R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4638 #define CAN_F4R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4639 #define CAN_F4R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4640 #define CAN_F4R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4641 #define CAN_F4R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4642 #define CAN_F4R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4643 #define CAN_F4R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4644 #define CAN_F4R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4645 #define CAN_F4R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4646 #define CAN_F4R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4647 #define CAN_F4R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4648 #define CAN_F4R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4649 #define CAN_F4R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4650 #define CAN_F4R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4651 #define CAN_F4R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4652 #define CAN_F4R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4653 #define CAN_F4R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4654 #define CAN_F4R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4655 #define CAN_F4R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4656 #define CAN_F4R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4657 #define CAN_F4R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4658 #define CAN_F4R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4659 #define CAN_F4R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4660
mbed_official 155:8435094ec241 4661 /******************* Bit definition for CAN_F5R2 register *******************/
mbed_official 155:8435094ec241 4662 #define CAN_F5R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4663 #define CAN_F5R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4664 #define CAN_F5R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4665 #define CAN_F5R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4666 #define CAN_F5R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4667 #define CAN_F5R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4668 #define CAN_F5R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4669 #define CAN_F5R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4670 #define CAN_F5R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4671 #define CAN_F5R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4672 #define CAN_F5R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4673 #define CAN_F5R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4674 #define CAN_F5R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4675 #define CAN_F5R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4676 #define CAN_F5R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4677 #define CAN_F5R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4678 #define CAN_F5R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4679 #define CAN_F5R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4680 #define CAN_F5R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4681 #define CAN_F5R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4682 #define CAN_F5R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4683 #define CAN_F5R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4684 #define CAN_F5R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4685 #define CAN_F5R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4686 #define CAN_F5R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4687 #define CAN_F5R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4688 #define CAN_F5R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4689 #define CAN_F5R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4690 #define CAN_F5R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4691 #define CAN_F5R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4692 #define CAN_F5R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4693 #define CAN_F5R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4694
mbed_official 155:8435094ec241 4695 /******************* Bit definition for CAN_F6R2 register *******************/
mbed_official 155:8435094ec241 4696 #define CAN_F6R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4697 #define CAN_F6R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4698 #define CAN_F6R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4699 #define CAN_F6R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4700 #define CAN_F6R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4701 #define CAN_F6R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4702 #define CAN_F6R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4703 #define CAN_F6R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4704 #define CAN_F6R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4705 #define CAN_F6R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4706 #define CAN_F6R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4707 #define CAN_F6R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4708 #define CAN_F6R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4709 #define CAN_F6R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4710 #define CAN_F6R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4711 #define CAN_F6R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4712 #define CAN_F6R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4713 #define CAN_F6R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4714 #define CAN_F6R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4715 #define CAN_F6R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4716 #define CAN_F6R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4717 #define CAN_F6R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4718 #define CAN_F6R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4719 #define CAN_F6R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4720 #define CAN_F6R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4721 #define CAN_F6R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4722 #define CAN_F6R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4723 #define CAN_F6R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4724 #define CAN_F6R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4725 #define CAN_F6R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4726 #define CAN_F6R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4727 #define CAN_F6R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4728
mbed_official 155:8435094ec241 4729 /******************* Bit definition for CAN_F7R2 register *******************/
mbed_official 155:8435094ec241 4730 #define CAN_F7R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4731 #define CAN_F7R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4732 #define CAN_F7R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4733 #define CAN_F7R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4734 #define CAN_F7R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4735 #define CAN_F7R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4736 #define CAN_F7R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4737 #define CAN_F7R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4738 #define CAN_F7R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4739 #define CAN_F7R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4740 #define CAN_F7R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4741 #define CAN_F7R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4742 #define CAN_F7R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4743 #define CAN_F7R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4744 #define CAN_F7R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4745 #define CAN_F7R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4746 #define CAN_F7R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4747 #define CAN_F7R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4748 #define CAN_F7R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4749 #define CAN_F7R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4750 #define CAN_F7R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4751 #define CAN_F7R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4752 #define CAN_F7R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4753 #define CAN_F7R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4754 #define CAN_F7R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4755 #define CAN_F7R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4756 #define CAN_F7R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4757 #define CAN_F7R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4758 #define CAN_F7R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4759 #define CAN_F7R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4760 #define CAN_F7R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4761 #define CAN_F7R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4762
mbed_official 155:8435094ec241 4763 /******************* Bit definition for CAN_F8R2 register *******************/
mbed_official 155:8435094ec241 4764 #define CAN_F8R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4765 #define CAN_F8R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4766 #define CAN_F8R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4767 #define CAN_F8R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4768 #define CAN_F8R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4769 #define CAN_F8R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4770 #define CAN_F8R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4771 #define CAN_F8R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4772 #define CAN_F8R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4773 #define CAN_F8R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4774 #define CAN_F8R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4775 #define CAN_F8R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4776 #define CAN_F8R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4777 #define CAN_F8R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4778 #define CAN_F8R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4779 #define CAN_F8R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4780 #define CAN_F8R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4781 #define CAN_F8R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4782 #define CAN_F8R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4783 #define CAN_F8R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4784 #define CAN_F8R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4785 #define CAN_F8R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4786 #define CAN_F8R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4787 #define CAN_F8R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4788 #define CAN_F8R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4789 #define CAN_F8R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4790 #define CAN_F8R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4791 #define CAN_F8R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4792 #define CAN_F8R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4793 #define CAN_F8R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4794 #define CAN_F8R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4795 #define CAN_F8R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4796
mbed_official 155:8435094ec241 4797 /******************* Bit definition for CAN_F9R2 register *******************/
mbed_official 155:8435094ec241 4798 #define CAN_F9R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4799 #define CAN_F9R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4800 #define CAN_F9R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4801 #define CAN_F9R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4802 #define CAN_F9R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4803 #define CAN_F9R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4804 #define CAN_F9R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4805 #define CAN_F9R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4806 #define CAN_F9R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4807 #define CAN_F9R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4808 #define CAN_F9R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4809 #define CAN_F9R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4810 #define CAN_F9R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4811 #define CAN_F9R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4812 #define CAN_F9R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4813 #define CAN_F9R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4814 #define CAN_F9R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4815 #define CAN_F9R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4816 #define CAN_F9R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4817 #define CAN_F9R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4818 #define CAN_F9R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4819 #define CAN_F9R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4820 #define CAN_F9R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4821 #define CAN_F9R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4822 #define CAN_F9R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4823 #define CAN_F9R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4824 #define CAN_F9R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4825 #define CAN_F9R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4826 #define CAN_F9R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4827 #define CAN_F9R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4828 #define CAN_F9R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4829 #define CAN_F9R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4830
mbed_official 155:8435094ec241 4831 /******************* Bit definition for CAN_F10R2 register ******************/
mbed_official 155:8435094ec241 4832 #define CAN_F10R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4833 #define CAN_F10R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4834 #define CAN_F10R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4835 #define CAN_F10R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4836 #define CAN_F10R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4837 #define CAN_F10R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4838 #define CAN_F10R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4839 #define CAN_F10R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4840 #define CAN_F10R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4841 #define CAN_F10R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4842 #define CAN_F10R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4843 #define CAN_F10R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4844 #define CAN_F10R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4845 #define CAN_F10R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4846 #define CAN_F10R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4847 #define CAN_F10R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4848 #define CAN_F10R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4849 #define CAN_F10R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4850 #define CAN_F10R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4851 #define CAN_F10R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4852 #define CAN_F10R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4853 #define CAN_F10R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4854 #define CAN_F10R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4855 #define CAN_F10R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4856 #define CAN_F10R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4857 #define CAN_F10R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4858 #define CAN_F10R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4859 #define CAN_F10R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4860 #define CAN_F10R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4861 #define CAN_F10R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4862 #define CAN_F10R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4863 #define CAN_F10R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4864
mbed_official 155:8435094ec241 4865 /******************* Bit definition for CAN_F11R2 register ******************/
mbed_official 155:8435094ec241 4866 #define CAN_F11R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4867 #define CAN_F11R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4868 #define CAN_F11R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4869 #define CAN_F11R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4870 #define CAN_F11R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4871 #define CAN_F11R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4872 #define CAN_F11R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4873 #define CAN_F11R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4874 #define CAN_F11R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4875 #define CAN_F11R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4876 #define CAN_F11R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4877 #define CAN_F11R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4878 #define CAN_F11R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4879 #define CAN_F11R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4880 #define CAN_F11R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4881 #define CAN_F11R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4882 #define CAN_F11R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4883 #define CAN_F11R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4884 #define CAN_F11R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4885 #define CAN_F11R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4886 #define CAN_F11R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4887 #define CAN_F11R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4888 #define CAN_F11R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4889 #define CAN_F11R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4890 #define CAN_F11R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4891 #define CAN_F11R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4892 #define CAN_F11R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4893 #define CAN_F11R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4894 #define CAN_F11R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4895 #define CAN_F11R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4896 #define CAN_F11R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4897 #define CAN_F11R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4898
mbed_official 155:8435094ec241 4899 /******************* Bit definition for CAN_F12R2 register ******************/
mbed_official 155:8435094ec241 4900 #define CAN_F12R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4901 #define CAN_F12R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4902 #define CAN_F12R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4903 #define CAN_F12R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4904 #define CAN_F12R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4905 #define CAN_F12R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4906 #define CAN_F12R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4907 #define CAN_F12R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4908 #define CAN_F12R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4909 #define CAN_F12R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4910 #define CAN_F12R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4911 #define CAN_F12R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4912 #define CAN_F12R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4913 #define CAN_F12R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4914 #define CAN_F12R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4915 #define CAN_F12R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4916 #define CAN_F12R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4917 #define CAN_F12R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4918 #define CAN_F12R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4919 #define CAN_F12R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4920 #define CAN_F12R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4921 #define CAN_F12R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4922 #define CAN_F12R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4923 #define CAN_F12R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4924 #define CAN_F12R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4925 #define CAN_F12R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4926 #define CAN_F12R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4927 #define CAN_F12R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4928 #define CAN_F12R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4929 #define CAN_F12R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4930 #define CAN_F12R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4931 #define CAN_F12R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4932
mbed_official 155:8435094ec241 4933 /******************* Bit definition for CAN_F13R2 register ******************/
mbed_official 155:8435094ec241 4934 #define CAN_F13R2_FB0 ((uint32_t)0x00000001) /*!<Filter bit 0 */
mbed_official 155:8435094ec241 4935 #define CAN_F13R2_FB1 ((uint32_t)0x00000002) /*!<Filter bit 1 */
mbed_official 155:8435094ec241 4936 #define CAN_F13R2_FB2 ((uint32_t)0x00000004) /*!<Filter bit 2 */
mbed_official 155:8435094ec241 4937 #define CAN_F13R2_FB3 ((uint32_t)0x00000008) /*!<Filter bit 3 */
mbed_official 155:8435094ec241 4938 #define CAN_F13R2_FB4 ((uint32_t)0x00000010) /*!<Filter bit 4 */
mbed_official 155:8435094ec241 4939 #define CAN_F13R2_FB5 ((uint32_t)0x00000020) /*!<Filter bit 5 */
mbed_official 155:8435094ec241 4940 #define CAN_F13R2_FB6 ((uint32_t)0x00000040) /*!<Filter bit 6 */
mbed_official 155:8435094ec241 4941 #define CAN_F13R2_FB7 ((uint32_t)0x00000080) /*!<Filter bit 7 */
mbed_official 155:8435094ec241 4942 #define CAN_F13R2_FB8 ((uint32_t)0x00000100) /*!<Filter bit 8 */
mbed_official 155:8435094ec241 4943 #define CAN_F13R2_FB9 ((uint32_t)0x00000200) /*!<Filter bit 9 */
mbed_official 155:8435094ec241 4944 #define CAN_F13R2_FB10 ((uint32_t)0x00000400) /*!<Filter bit 10 */
mbed_official 155:8435094ec241 4945 #define CAN_F13R2_FB11 ((uint32_t)0x00000800) /*!<Filter bit 11 */
mbed_official 155:8435094ec241 4946 #define CAN_F13R2_FB12 ((uint32_t)0x00001000) /*!<Filter bit 12 */
mbed_official 155:8435094ec241 4947 #define CAN_F13R2_FB13 ((uint32_t)0x00002000) /*!<Filter bit 13 */
mbed_official 155:8435094ec241 4948 #define CAN_F13R2_FB14 ((uint32_t)0x00004000) /*!<Filter bit 14 */
mbed_official 155:8435094ec241 4949 #define CAN_F13R2_FB15 ((uint32_t)0x00008000) /*!<Filter bit 15 */
mbed_official 155:8435094ec241 4950 #define CAN_F13R2_FB16 ((uint32_t)0x00010000) /*!<Filter bit 16 */
mbed_official 155:8435094ec241 4951 #define CAN_F13R2_FB17 ((uint32_t)0x00020000) /*!<Filter bit 17 */
mbed_official 155:8435094ec241 4952 #define CAN_F13R2_FB18 ((uint32_t)0x00040000) /*!<Filter bit 18 */
mbed_official 155:8435094ec241 4953 #define CAN_F13R2_FB19 ((uint32_t)0x00080000) /*!<Filter bit 19 */
mbed_official 155:8435094ec241 4954 #define CAN_F13R2_FB20 ((uint32_t)0x00100000) /*!<Filter bit 20 */
mbed_official 155:8435094ec241 4955 #define CAN_F13R2_FB21 ((uint32_t)0x00200000) /*!<Filter bit 21 */
mbed_official 155:8435094ec241 4956 #define CAN_F13R2_FB22 ((uint32_t)0x00400000) /*!<Filter bit 22 */
mbed_official 155:8435094ec241 4957 #define CAN_F13R2_FB23 ((uint32_t)0x00800000) /*!<Filter bit 23 */
mbed_official 155:8435094ec241 4958 #define CAN_F13R2_FB24 ((uint32_t)0x01000000) /*!<Filter bit 24 */
mbed_official 155:8435094ec241 4959 #define CAN_F13R2_FB25 ((uint32_t)0x02000000) /*!<Filter bit 25 */
mbed_official 155:8435094ec241 4960 #define CAN_F13R2_FB26 ((uint32_t)0x04000000) /*!<Filter bit 26 */
mbed_official 155:8435094ec241 4961 #define CAN_F13R2_FB27 ((uint32_t)0x08000000) /*!<Filter bit 27 */
mbed_official 155:8435094ec241 4962 #define CAN_F13R2_FB28 ((uint32_t)0x10000000) /*!<Filter bit 28 */
mbed_official 155:8435094ec241 4963 #define CAN_F13R2_FB29 ((uint32_t)0x20000000) /*!<Filter bit 29 */
mbed_official 155:8435094ec241 4964 #define CAN_F13R2_FB30 ((uint32_t)0x40000000) /*!<Filter bit 30 */
mbed_official 155:8435094ec241 4965 #define CAN_F13R2_FB31 ((uint32_t)0x80000000) /*!<Filter bit 31 */
mbed_official 155:8435094ec241 4966
mbed_official 155:8435094ec241 4967 /******************************************************************************/
mbed_official 155:8435094ec241 4968 /* */
mbed_official 155:8435094ec241 4969 /* CRC calculation unit (CRC) */
mbed_official 155:8435094ec241 4970 /* */
mbed_official 155:8435094ec241 4971 /******************************************************************************/
mbed_official 155:8435094ec241 4972 /******************* Bit definition for CRC_DR register *********************/
mbed_official 155:8435094ec241 4973 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
mbed_official 155:8435094ec241 4974
mbed_official 155:8435094ec241 4975 /******************* Bit definition for CRC_IDR register ********************/
mbed_official 155:8435094ec241 4976 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
mbed_official 155:8435094ec241 4977
mbed_official 155:8435094ec241 4978 /******************** Bit definition for CRC_CR register ********************/
mbed_official 155:8435094ec241 4979 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
mbed_official 155:8435094ec241 4980 #define CRC_CR_POLSIZE ((uint32_t)0x00000018) /*!< Polynomial size bits */
mbed_official 155:8435094ec241 4981 #define CRC_CR_POLSIZE_0 ((uint32_t)0x00000008) /*!< Polynomial size bit 0 */
mbed_official 155:8435094ec241 4982 #define CRC_CR_POLSIZE_1 ((uint32_t)0x00000010) /*!< Polynomial size bit 1 */
mbed_official 155:8435094ec241 4983 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
mbed_official 155:8435094ec241 4984 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< Bit 0 */
mbed_official 155:8435094ec241 4985 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< Bit 1 */
mbed_official 155:8435094ec241 4986 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
mbed_official 155:8435094ec241 4987
mbed_official 155:8435094ec241 4988 /******************* Bit definition for CRC_INIT register *******************/
mbed_official 155:8435094ec241 4989 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
mbed_official 155:8435094ec241 4990
mbed_official 155:8435094ec241 4991 /******************* Bit definition for CRC_POL register ********************/
mbed_official 155:8435094ec241 4992 #define CRC_POL_POL ((uint32_t)0xFFFFFFFF) /*!< Coefficients of the polynomial */
mbed_official 155:8435094ec241 4993 /******************************************************************************/
mbed_official 155:8435094ec241 4994 /* */
mbed_official 155:8435094ec241 4995 /* Digital to Analog Converter (DAC) */
mbed_official 155:8435094ec241 4996 /* */
mbed_official 155:8435094ec241 4997 /******************************************************************************/
mbed_official 155:8435094ec241 4998 /******************** Bit definition for DAC_CR register ********************/
mbed_official 155:8435094ec241 4999 #define DAC_CR_EN1 ((uint32_t)0x00000001) /*!< DAC channel1 enable */
mbed_official 155:8435094ec241 5000 #define DAC_CR_BOFF1 ((uint32_t)0x00000002) /*!< DAC channel1 output buffer disable */
mbed_official 155:8435094ec241 5001 #define DAC_CR_TEN1 ((uint32_t)0x00000004) /*!< DAC channel1 Trigger enable */
mbed_official 155:8435094ec241 5002
mbed_official 155:8435094ec241 5003 #define DAC_CR_TSEL1 ((uint32_t)0x00000038) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
mbed_official 155:8435094ec241 5004 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 155:8435094ec241 5005 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 155:8435094ec241 5006 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020) /*!< Bit 2 */
mbed_official 155:8435094ec241 5007
mbed_official 155:8435094ec241 5008 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
mbed_official 155:8435094ec241 5009 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040) /*!< Bit 0 */
mbed_official 155:8435094ec241 5010 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080) /*!< Bit 1 */
mbed_official 155:8435094ec241 5011
mbed_official 155:8435094ec241 5012 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
mbed_official 155:8435094ec241 5013 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 155:8435094ec241 5014 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 155:8435094ec241 5015 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 155:8435094ec241 5016 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800) /*!< Bit 3 */
mbed_official 155:8435094ec241 5017
mbed_official 155:8435094ec241 5018 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000) /*!< DAC channel1 DMA enable */
mbed_official 155:8435094ec241 5019 #define DAC_CR_EN2 ((uint32_t)0x00010000) /*!< DAC channel2 enable */
mbed_official 155:8435094ec241 5020 #define DAC_CR_BOFF2 ((uint32_t)0x00020000) /*!< DAC channel2 output buffer disable */
mbed_official 155:8435094ec241 5021 #define DAC_CR_TEN2 ((uint32_t)0x00040000) /*!< DAC channel2 Trigger enable */
mbed_official 155:8435094ec241 5022
mbed_official 155:8435094ec241 5023 #define DAC_CR_TSEL2 ((uint32_t)0x00380000) /*!< TSEL2[2:0] (DAC channel2 Trigger selection) */
mbed_official 155:8435094ec241 5024 #define DAC_CR_TSEL2_0 ((uint32_t)0x00080000) /*!< Bit 0 */
mbed_official 155:8435094ec241 5025 #define DAC_CR_TSEL2_1 ((uint32_t)0x00100000) /*!< Bit 1 */
mbed_official 155:8435094ec241 5026 #define DAC_CR_TSEL2_2 ((uint32_t)0x00200000) /*!< Bit 2 */
mbed_official 155:8435094ec241 5027
mbed_official 155:8435094ec241 5028 #define DAC_CR_WAVE2 ((uint32_t)0x00C00000) /*!< WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
mbed_official 155:8435094ec241 5029 #define DAC_CR_WAVE2_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 155:8435094ec241 5030 #define DAC_CR_WAVE2_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 155:8435094ec241 5031
mbed_official 155:8435094ec241 5032 #define DAC_CR_MAMP2 ((uint32_t)0x0F000000) /*!< MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
mbed_official 155:8435094ec241 5033 #define DAC_CR_MAMP2_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 155:8435094ec241 5034 #define DAC_CR_MAMP2_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 155:8435094ec241 5035 #define DAC_CR_MAMP2_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 155:8435094ec241 5036 #define DAC_CR_MAMP2_3 ((uint32_t)0x08000000) /*!< Bit 3 */
mbed_official 155:8435094ec241 5037
mbed_official 155:8435094ec241 5038 #define DAC_CR_DMAEN2 ((uint32_t)0x10000000) /*!< DAC channel2 DMA enabled */
mbed_official 155:8435094ec241 5039
mbed_official 155:8435094ec241 5040 /***************** Bit definition for DAC_SWTRIGR register ******************/
mbed_official 155:8435094ec241 5041 #define DAC_SWTRIGR_SWTRIG1 ((uint8_t)0x01) /*!< DAC channel1 software trigger */
mbed_official 155:8435094ec241 5042 #define DAC_SWTRIGR_SWTRIG2 ((uint8_t)0x02) /*!< DAC channel2 software trigger */
mbed_official 155:8435094ec241 5043
mbed_official 155:8435094ec241 5044 /***************** Bit definition for DAC_DHR12R1 register ******************/
mbed_official 155:8435094ec241 5045 #define DAC_DHR12R1_DACC1DHR ((uint16_t)0x0FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 155:8435094ec241 5046
mbed_official 155:8435094ec241 5047 /***************** Bit definition for DAC_DHR12L1 register ******************/
mbed_official 155:8435094ec241 5048 #define DAC_DHR12L1_DACC1DHR ((uint16_t)0xFFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 155:8435094ec241 5049
mbed_official 155:8435094ec241 5050 /****************** Bit definition for DAC_DHR8R1 register ******************/
mbed_official 155:8435094ec241 5051 #define DAC_DHR8R1_DACC1DHR ((uint8_t)0xFF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 155:8435094ec241 5052
mbed_official 155:8435094ec241 5053 /***************** Bit definition for DAC_DHR12R2 register ******************/
mbed_official 155:8435094ec241 5054 #define DAC_DHR12R2_DACC2DHR ((uint16_t)0x0FFF) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 155:8435094ec241 5055
mbed_official 155:8435094ec241 5056 /***************** Bit definition for DAC_DHR12L2 register ******************/
mbed_official 155:8435094ec241 5057 #define DAC_DHR12L2_DACC2DHR ((uint16_t)0xFFF0) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 155:8435094ec241 5058
mbed_official 155:8435094ec241 5059 /****************** Bit definition for DAC_DHR8R2 register ******************/
mbed_official 155:8435094ec241 5060 #define DAC_DHR8R2_DACC2DHR ((uint8_t)0xFF) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 155:8435094ec241 5061
mbed_official 155:8435094ec241 5062 /***************** Bit definition for DAC_DHR12RD register ******************/
mbed_official 155:8435094ec241 5063 #define DAC_DHR12RD_DACC1DHR ((uint32_t)0x00000FFF) /*!< DAC channel1 12-bit Right aligned data */
mbed_official 155:8435094ec241 5064 #define DAC_DHR12RD_DACC2DHR ((uint32_t)0x0FFF0000) /*!< DAC channel2 12-bit Right aligned data */
mbed_official 155:8435094ec241 5065
mbed_official 155:8435094ec241 5066 /***************** Bit definition for DAC_DHR12LD register ******************/
mbed_official 155:8435094ec241 5067 #define DAC_DHR12LD_DACC1DHR ((uint32_t)0x0000FFF0) /*!< DAC channel1 12-bit Left aligned data */
mbed_official 155:8435094ec241 5068 #define DAC_DHR12LD_DACC2DHR ((uint32_t)0xFFF00000) /*!< DAC channel2 12-bit Left aligned data */
mbed_official 155:8435094ec241 5069
mbed_official 155:8435094ec241 5070 /****************** Bit definition for DAC_DHR8RD register ******************/
mbed_official 155:8435094ec241 5071 #define DAC_DHR8RD_DACC1DHR ((uint16_t)0x00FF) /*!< DAC channel1 8-bit Right aligned data */
mbed_official 155:8435094ec241 5072 #define DAC_DHR8RD_DACC2DHR ((uint16_t)0xFF00) /*!< DAC channel2 8-bit Right aligned data */
mbed_official 155:8435094ec241 5073
mbed_official 155:8435094ec241 5074 /******************* Bit definition for DAC_DOR1 register *******************/
mbed_official 155:8435094ec241 5075 #define DAC_DOR1_DACC1DOR ((uint16_t)0x0FFF) /*!< DAC channel1 data output */
mbed_official 155:8435094ec241 5076
mbed_official 155:8435094ec241 5077 /******************* Bit definition for DAC_DOR2 register *******************/
mbed_official 155:8435094ec241 5078 #define DAC_DOR2_DACC2DOR ((uint16_t)0x0FFF) /*!< DAC channel2 data output */
mbed_official 155:8435094ec241 5079
mbed_official 155:8435094ec241 5080 /******************** Bit definition for DAC_SR register ********************/
mbed_official 155:8435094ec241 5081 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000) /*!< DAC channel1 DMA underrun flag */
mbed_official 155:8435094ec241 5082 #define DAC_SR_DMAUDR2 ((uint32_t)0x20000000) /*!< DAC channel2 DMA underrun flag */
mbed_official 155:8435094ec241 5083
mbed_official 155:8435094ec241 5084 /******************************************************************************/
mbed_official 155:8435094ec241 5085 /* */
mbed_official 155:8435094ec241 5086 /* Debug MCU (DBGMCU) */
mbed_official 155:8435094ec241 5087 /* */
mbed_official 155:8435094ec241 5088 /******************************************************************************/
mbed_official 155:8435094ec241 5089 /******************** Bit definition for DBGMCU_IDCODE register *************/
mbed_official 155:8435094ec241 5090 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF)
mbed_official 155:8435094ec241 5091 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000)
mbed_official 155:8435094ec241 5092
mbed_official 155:8435094ec241 5093 /******************** Bit definition for DBGMCU_CR register *****************/
mbed_official 155:8435094ec241 5094 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5095 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5096 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5097 #define DBGMCU_CR_TRACE_IOEN ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5098
mbed_official 155:8435094ec241 5099 #define DBGMCU_CR_TRACE_MODE ((uint32_t)0x000000C0)
mbed_official 155:8435094ec241 5100 #define DBGMCU_CR_TRACE_MODE_0 ((uint32_t)0x00000040)/*!<Bit 0 */
mbed_official 155:8435094ec241 5101 #define DBGMCU_CR_TRACE_MODE_1 ((uint32_t)0x00000080)/*!<Bit 1 */
mbed_official 155:8435094ec241 5102
mbed_official 155:8435094ec241 5103 /******************** Bit definition for DBGMCU_APB1_FZ register ************/
mbed_official 155:8435094ec241 5104 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5105 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5106 #define DBGMCU_APB1_FZ_DBG_TIM4_STOP ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5107 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5108 #define DBGMCU_APB1_FZ_DBG_TIM7_STOP ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5109 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5110 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5111 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5112 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 5113 #define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 5114 #define DBGMCU_APB1_FZ_DBG_CAN1_STOP ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 5115
mbed_official 155:8435094ec241 5116 /******************** Bit definition for DBGMCU_APB2_FZ register ************/
mbed_official 155:8435094ec241 5117 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5118 #define DBGMCU_APB2_FZ_DBG_TIM8_STOP ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5119 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5120 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5121 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5122
mbed_official 155:8435094ec241 5123 /******************************************************************************/
mbed_official 155:8435094ec241 5124 /* */
mbed_official 155:8435094ec241 5125 /* DMA Controller (DMA) */
mbed_official 155:8435094ec241 5126 /* */
mbed_official 155:8435094ec241 5127 /******************************************************************************/
mbed_official 155:8435094ec241 5128 /******************* Bit definition for DMA_ISR register ********************/
mbed_official 155:8435094ec241 5129 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
mbed_official 155:8435094ec241 5130 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
mbed_official 155:8435094ec241 5131 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
mbed_official 155:8435094ec241 5132 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
mbed_official 155:8435094ec241 5133 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
mbed_official 155:8435094ec241 5134 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
mbed_official 155:8435094ec241 5135 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
mbed_official 155:8435094ec241 5136 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
mbed_official 155:8435094ec241 5137 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
mbed_official 155:8435094ec241 5138 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
mbed_official 155:8435094ec241 5139 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
mbed_official 155:8435094ec241 5140 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
mbed_official 155:8435094ec241 5141 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
mbed_official 155:8435094ec241 5142 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
mbed_official 155:8435094ec241 5143 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
mbed_official 155:8435094ec241 5144 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
mbed_official 155:8435094ec241 5145 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
mbed_official 155:8435094ec241 5146 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
mbed_official 155:8435094ec241 5147 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
mbed_official 155:8435094ec241 5148 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
mbed_official 155:8435094ec241 5149 #define DMA_ISR_GIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt flag */
mbed_official 155:8435094ec241 5150 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete flag */
mbed_official 155:8435094ec241 5151 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer flag */
mbed_official 155:8435094ec241 5152 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error flag */
mbed_official 155:8435094ec241 5153 #define DMA_ISR_GIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt flag */
mbed_official 155:8435094ec241 5154 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete flag */
mbed_official 155:8435094ec241 5155 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer flag */
mbed_official 155:8435094ec241 5156 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error flag */
mbed_official 155:8435094ec241 5157
mbed_official 155:8435094ec241 5158 /******************* Bit definition for DMA_IFCR register *******************/
mbed_official 155:8435094ec241 5159 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
mbed_official 155:8435094ec241 5160 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
mbed_official 155:8435094ec241 5161 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
mbed_official 155:8435094ec241 5162 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
mbed_official 155:8435094ec241 5163 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
mbed_official 155:8435094ec241 5164 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
mbed_official 155:8435094ec241 5165 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
mbed_official 155:8435094ec241 5166 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
mbed_official 155:8435094ec241 5167 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
mbed_official 155:8435094ec241 5168 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
mbed_official 155:8435094ec241 5169 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
mbed_official 155:8435094ec241 5170 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
mbed_official 155:8435094ec241 5171 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
mbed_official 155:8435094ec241 5172 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
mbed_official 155:8435094ec241 5173 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
mbed_official 155:8435094ec241 5174 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
mbed_official 155:8435094ec241 5175 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
mbed_official 155:8435094ec241 5176 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
mbed_official 155:8435094ec241 5177 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
mbed_official 155:8435094ec241 5178 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
mbed_official 155:8435094ec241 5179 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000) /*!< Channel 6 Global interrupt clear */
mbed_official 155:8435094ec241 5180 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000) /*!< Channel 6 Transfer Complete clear */
mbed_official 155:8435094ec241 5181 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000) /*!< Channel 6 Half Transfer clear */
mbed_official 155:8435094ec241 5182 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000) /*!< Channel 6 Transfer Error clear */
mbed_official 155:8435094ec241 5183 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000) /*!< Channel 7 Global interrupt clear */
mbed_official 155:8435094ec241 5184 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000) /*!< Channel 7 Transfer Complete clear */
mbed_official 155:8435094ec241 5185 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000) /*!< Channel 7 Half Transfer clear */
mbed_official 155:8435094ec241 5186 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000) /*!< Channel 7 Transfer Error clear */
mbed_official 155:8435094ec241 5187
mbed_official 155:8435094ec241 5188 /******************* Bit definition for DMA_CCR register ********************/
mbed_official 155:8435094ec241 5189 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
mbed_official 155:8435094ec241 5190 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
mbed_official 155:8435094ec241 5191 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
mbed_official 155:8435094ec241 5192 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
mbed_official 155:8435094ec241 5193 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
mbed_official 155:8435094ec241 5194 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
mbed_official 155:8435094ec241 5195 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
mbed_official 155:8435094ec241 5196 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
mbed_official 155:8435094ec241 5197
mbed_official 155:8435094ec241 5198 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
mbed_official 155:8435094ec241 5199 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 155:8435094ec241 5200 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 155:8435094ec241 5201
mbed_official 155:8435094ec241 5202 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
mbed_official 155:8435094ec241 5203 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
mbed_official 155:8435094ec241 5204 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
mbed_official 155:8435094ec241 5205
mbed_official 155:8435094ec241 5206 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
mbed_official 155:8435094ec241 5207 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 155:8435094ec241 5208 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 155:8435094ec241 5209
mbed_official 155:8435094ec241 5210 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
mbed_official 155:8435094ec241 5211
mbed_official 155:8435094ec241 5212 /****************** Bit definition for DMA_CNDTR register *******************/
mbed_official 155:8435094ec241 5213 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
mbed_official 155:8435094ec241 5214
mbed_official 155:8435094ec241 5215 /****************** Bit definition for DMA_CPAR register ********************/
mbed_official 155:8435094ec241 5216 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
mbed_official 155:8435094ec241 5217
mbed_official 155:8435094ec241 5218 /****************** Bit definition for DMA_CMAR register ********************/
mbed_official 155:8435094ec241 5219 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
mbed_official 155:8435094ec241 5220
mbed_official 155:8435094ec241 5221 /******************************************************************************/
mbed_official 155:8435094ec241 5222 /* */
mbed_official 155:8435094ec241 5223 /* External Interrupt/Event Controller (EXTI) */
mbed_official 155:8435094ec241 5224 /* */
mbed_official 155:8435094ec241 5225 /******************************************************************************/
mbed_official 155:8435094ec241 5226 /******************* Bit definition for EXTI_IMR register *******************/
mbed_official 155:8435094ec241 5227 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
mbed_official 155:8435094ec241 5228 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
mbed_official 155:8435094ec241 5229 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
mbed_official 155:8435094ec241 5230 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
mbed_official 155:8435094ec241 5231 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
mbed_official 155:8435094ec241 5232 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
mbed_official 155:8435094ec241 5233 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
mbed_official 155:8435094ec241 5234 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
mbed_official 155:8435094ec241 5235 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
mbed_official 155:8435094ec241 5236 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
mbed_official 155:8435094ec241 5237 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
mbed_official 155:8435094ec241 5238 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
mbed_official 155:8435094ec241 5239 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
mbed_official 155:8435094ec241 5240 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
mbed_official 155:8435094ec241 5241 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
mbed_official 155:8435094ec241 5242 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
mbed_official 155:8435094ec241 5243 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
mbed_official 155:8435094ec241 5244 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
mbed_official 155:8435094ec241 5245 #define EXTI_IMR_MR18 ((uint32_t)0x00040000) /*!< Interrupt Mask on line 18 */
mbed_official 155:8435094ec241 5246 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
mbed_official 155:8435094ec241 5247 #define EXTI_IMR_MR20 ((uint32_t)0x00100000) /*!< Interrupt Mask on line 20 */
mbed_official 155:8435094ec241 5248 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
mbed_official 155:8435094ec241 5249 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
mbed_official 155:8435094ec241 5250 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
mbed_official 155:8435094ec241 5251 #define EXTI_IMR_MR24 ((uint32_t)0x01000000) /*!< Interrupt Mask on line 24 */
mbed_official 155:8435094ec241 5252 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
mbed_official 155:8435094ec241 5253 #define EXTI_IMR_MR26 ((uint32_t)0x04000000) /*!< Interrupt Mask on line 26 */
mbed_official 155:8435094ec241 5254 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
mbed_official 155:8435094ec241 5255 #define EXTI_IMR_MR28 ((uint32_t)0x10000000) /*!< Interrupt Mask on line 28 */
mbed_official 155:8435094ec241 5256
mbed_official 155:8435094ec241 5257 /******************* Bit definition for EXTI_EMR register *******************/
mbed_official 155:8435094ec241 5258 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
mbed_official 155:8435094ec241 5259 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
mbed_official 155:8435094ec241 5260 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
mbed_official 155:8435094ec241 5261 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
mbed_official 155:8435094ec241 5262 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
mbed_official 155:8435094ec241 5263 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
mbed_official 155:8435094ec241 5264 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
mbed_official 155:8435094ec241 5265 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
mbed_official 155:8435094ec241 5266 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
mbed_official 155:8435094ec241 5267 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
mbed_official 155:8435094ec241 5268 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
mbed_official 155:8435094ec241 5269 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
mbed_official 155:8435094ec241 5270 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
mbed_official 155:8435094ec241 5271 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
mbed_official 155:8435094ec241 5272 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
mbed_official 155:8435094ec241 5273 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
mbed_official 155:8435094ec241 5274 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
mbed_official 155:8435094ec241 5275 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
mbed_official 155:8435094ec241 5276 #define EXTI_EMR_MR18 ((uint32_t)0x00040000) /*!< Event Mask on line 18 */
mbed_official 155:8435094ec241 5277 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
mbed_official 155:8435094ec241 5278 #define EXTI_EMR_MR20 ((uint32_t)0x00100000) /*!< Event Mask on line 20 */
mbed_official 155:8435094ec241 5279 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
mbed_official 155:8435094ec241 5280 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
mbed_official 155:8435094ec241 5281 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
mbed_official 155:8435094ec241 5282 #define EXTI_EMR_MR24 ((uint32_t)0x01000000) /*!< Event Mask on line 24 */
mbed_official 155:8435094ec241 5283 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
mbed_official 155:8435094ec241 5284 #define EXTI_EMR_MR26 ((uint32_t)0x04000000) /*!< Event Mask on line 26 */
mbed_official 155:8435094ec241 5285 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
mbed_official 155:8435094ec241 5286 #define EXTI_EMR_MR28 ((uint32_t)0x10000000) /*!< Event Mask on line 28 */
mbed_official 155:8435094ec241 5287
mbed_official 155:8435094ec241 5288 /****************** Bit definition for EXTI_RTSR register *******************/
mbed_official 155:8435094ec241 5289 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
mbed_official 155:8435094ec241 5290 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
mbed_official 155:8435094ec241 5291 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
mbed_official 155:8435094ec241 5292 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
mbed_official 155:8435094ec241 5293 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
mbed_official 155:8435094ec241 5294 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
mbed_official 155:8435094ec241 5295 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
mbed_official 155:8435094ec241 5296 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
mbed_official 155:8435094ec241 5297 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
mbed_official 155:8435094ec241 5298 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
mbed_official 155:8435094ec241 5299 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
mbed_official 155:8435094ec241 5300 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
mbed_official 155:8435094ec241 5301 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
mbed_official 155:8435094ec241 5302 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
mbed_official 155:8435094ec241 5303 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
mbed_official 155:8435094ec241 5304 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
mbed_official 155:8435094ec241 5305 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
mbed_official 155:8435094ec241 5306 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
mbed_official 155:8435094ec241 5307 #define EXTI_RTSR_TR18 ((uint32_t)0x00040000) /*!< Rising trigger event configuration bit of line 18 */
mbed_official 155:8435094ec241 5308 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
mbed_official 155:8435094ec241 5309 #define EXTI_RTSR_TR20 ((uint32_t)0x00100000) /*!< Rising trigger event configuration bit of line 20 */
mbed_official 155:8435094ec241 5310 #define EXTI_RTSR_TR21 ((uint32_t)0x00200000) /*!< Rising trigger event configuration bit of line 21 */
mbed_official 155:8435094ec241 5311 #define EXTI_RTSR_TR22 ((uint32_t)0x00400000) /*!< Rising trigger event configuration bit of line 22 */
mbed_official 155:8435094ec241 5312 #define EXTI_RTSR_TR23 ((uint32_t)0x00800000) /*!< Rising trigger event configuration bit of line 23 */
mbed_official 155:8435094ec241 5313 #define EXTI_RTSR_TR24 ((uint32_t)0x01000000) /*!< Rising trigger event configuration bit of line 24 */
mbed_official 155:8435094ec241 5314 #define EXTI_RTSR_TR25 ((uint32_t)0x02000000) /*!< Rising trigger event configuration bit of line 25 */
mbed_official 155:8435094ec241 5315 #define EXTI_RTSR_TR26 ((uint32_t)0x04000000) /*!< Rising trigger event configuration bit of line 26 */
mbed_official 155:8435094ec241 5316 #define EXTI_RTSR_TR27 ((uint32_t)0x08000000) /*!< Rising trigger event configuration bit of line 27 */
mbed_official 155:8435094ec241 5317 #define EXTI_RTSR_TR28 ((uint32_t)0x10000000) /*!< Rising trigger event configuration bit of line 28 */
mbed_official 155:8435094ec241 5318
mbed_official 155:8435094ec241 5319 /****************** Bit definition for EXTI_FTSR register *******************/
mbed_official 155:8435094ec241 5320 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
mbed_official 155:8435094ec241 5321 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
mbed_official 155:8435094ec241 5322 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
mbed_official 155:8435094ec241 5323 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
mbed_official 155:8435094ec241 5324 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
mbed_official 155:8435094ec241 5325 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
mbed_official 155:8435094ec241 5326 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
mbed_official 155:8435094ec241 5327 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
mbed_official 155:8435094ec241 5328 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
mbed_official 155:8435094ec241 5329 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
mbed_official 155:8435094ec241 5330 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
mbed_official 155:8435094ec241 5331 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
mbed_official 155:8435094ec241 5332 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
mbed_official 155:8435094ec241 5333 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
mbed_official 155:8435094ec241 5334 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
mbed_official 155:8435094ec241 5335 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
mbed_official 155:8435094ec241 5336 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
mbed_official 155:8435094ec241 5337 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
mbed_official 155:8435094ec241 5338 #define EXTI_FTSR_TR18 ((uint32_t)0x00040000) /*!< Falling trigger event configuration bit of line 18 */
mbed_official 155:8435094ec241 5339 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
mbed_official 155:8435094ec241 5340 #define EXTI_FTSR_TR20 ((uint32_t)0x00100000) /*!< Falling trigger event configuration bit of line 20 */
mbed_official 155:8435094ec241 5341 #define EXTI_FTSR_TR21 ((uint32_t)0x00200000) /*!< Falling trigger event configuration bit of line 21 */
mbed_official 155:8435094ec241 5342 #define EXTI_FTSR_TR22 ((uint32_t)0x00400000) /*!< Falling trigger event configuration bit of line 22 */
mbed_official 155:8435094ec241 5343 #define EXTI_FTSR_TR23 ((uint32_t)0x00800000) /*!< Falling trigger event configuration bit of line 23 */
mbed_official 155:8435094ec241 5344 #define EXTI_FTSR_TR24 ((uint32_t)0x01000000) /*!< Falling trigger event configuration bit of line 24 */
mbed_official 155:8435094ec241 5345 #define EXTI_FTSR_TR25 ((uint32_t)0x02000000) /*!< Falling trigger event configuration bit of line 25 */
mbed_official 155:8435094ec241 5346 #define EXTI_FTSR_TR26 ((uint32_t)0x04000000) /*!< Falling trigger event configuration bit of line 26 */
mbed_official 155:8435094ec241 5347 #define EXTI_FTSR_TR27 ((uint32_t)0x08000000) /*!< Falling trigger event configuration bit of line 27 */
mbed_official 155:8435094ec241 5348 #define EXTI_FTSR_TR28 ((uint32_t)0x10000000) /*!< Falling trigger event configuration bit of line 28 */
mbed_official 155:8435094ec241 5349
mbed_official 155:8435094ec241 5350 /****************** Bit definition for EXTI_SWIER register ******************/
mbed_official 155:8435094ec241 5351 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
mbed_official 155:8435094ec241 5352 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
mbed_official 155:8435094ec241 5353 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
mbed_official 155:8435094ec241 5354 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
mbed_official 155:8435094ec241 5355 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
mbed_official 155:8435094ec241 5356 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
mbed_official 155:8435094ec241 5357 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
mbed_official 155:8435094ec241 5358 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
mbed_official 155:8435094ec241 5359 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
mbed_official 155:8435094ec241 5360 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
mbed_official 155:8435094ec241 5361 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
mbed_official 155:8435094ec241 5362 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
mbed_official 155:8435094ec241 5363 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
mbed_official 155:8435094ec241 5364 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
mbed_official 155:8435094ec241 5365 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
mbed_official 155:8435094ec241 5366 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
mbed_official 155:8435094ec241 5367 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
mbed_official 155:8435094ec241 5368 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
mbed_official 155:8435094ec241 5369 #define EXTI_SWIER_SWIER18 ((uint32_t)0x00040000) /*!< Software Interrupt on line 18 */
mbed_official 155:8435094ec241 5370 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
mbed_official 155:8435094ec241 5371 #define EXTI_SWIER_SWIER20 ((uint32_t)0x00100000) /*!< Software Interrupt on line 20 */
mbed_official 155:8435094ec241 5372 #define EXTI_SWIER_SWIER21 ((uint32_t)0x00200000) /*!< Software Interrupt on line 21 */
mbed_official 155:8435094ec241 5373 #define EXTI_SWIER_SWIER22 ((uint32_t)0x00400000) /*!< Software Interrupt on line 22 */
mbed_official 155:8435094ec241 5374 #define EXTI_SWIER_SWIER23 ((uint32_t)0x00800000) /*!< Software Interrupt on line 23 */
mbed_official 155:8435094ec241 5375 #define EXTI_SWIER_SWIER24 ((uint32_t)0x01000000) /*!< Software Interrupt on line 24 */
mbed_official 155:8435094ec241 5376 #define EXTI_SWIER_SWIER25 ((uint32_t)0x02000000) /*!< Software Interrupt on line 25 */
mbed_official 155:8435094ec241 5377 #define EXTI_SWIER_SWIER26 ((uint32_t)0x04000000) /*!< Software Interrupt on line 26 */
mbed_official 155:8435094ec241 5378 #define EXTI_SWIER_SWIER27 ((uint32_t)0x08000000) /*!< Software Interrupt on line 27 */
mbed_official 155:8435094ec241 5379 #define EXTI_SWIER_SWIER28 ((uint32_t)0x10000000) /*!< Software Interrupt on line 28 */
mbed_official 155:8435094ec241 5380
mbed_official 155:8435094ec241 5381 /******************* Bit definition for EXTI_PR register ********************/
mbed_official 155:8435094ec241 5382 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit for line 0 */
mbed_official 155:8435094ec241 5383 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit for line 1 */
mbed_official 155:8435094ec241 5384 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit for line 2 */
mbed_official 155:8435094ec241 5385 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit for line 3 */
mbed_official 155:8435094ec241 5386 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit for line 4 */
mbed_official 155:8435094ec241 5387 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit for line 5 */
mbed_official 155:8435094ec241 5388 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit for line 6 */
mbed_official 155:8435094ec241 5389 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit for line 7 */
mbed_official 155:8435094ec241 5390 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit for line 8 */
mbed_official 155:8435094ec241 5391 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit for line 9 */
mbed_official 155:8435094ec241 5392 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit for line 10 */
mbed_official 155:8435094ec241 5393 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit for line 11 */
mbed_official 155:8435094ec241 5394 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit for line 12 */
mbed_official 155:8435094ec241 5395 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit for line 13 */
mbed_official 155:8435094ec241 5396 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit for line 14 */
mbed_official 155:8435094ec241 5397 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit for line 15 */
mbed_official 155:8435094ec241 5398 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit for line 16 */
mbed_official 155:8435094ec241 5399 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit for line 17 */
mbed_official 155:8435094ec241 5400 #define EXTI_PR_PR18 ((uint32_t)0x00040000) /*!< Pending bit for line 18 */
mbed_official 155:8435094ec241 5401 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit for line 19 */
mbed_official 155:8435094ec241 5402 #define EXTI_PR_PR20 ((uint32_t)0x00100000) /*!< Pending bit for line 20 */
mbed_official 155:8435094ec241 5403 #define EXTI_PR_PR21 ((uint32_t)0x00200000) /*!< Pending bit for line 21 */
mbed_official 155:8435094ec241 5404 #define EXTI_PR_PR22 ((uint32_t)0x00400000) /*!< Pending bit for line 22 */
mbed_official 155:8435094ec241 5405 #define EXTI_PR_PR23 ((uint32_t)0x00800000) /*!< Pending bit for line 23 */
mbed_official 155:8435094ec241 5406 #define EXTI_PR_PR24 ((uint32_t)0x01000000) /*!< Pending bit for line 24 */
mbed_official 155:8435094ec241 5407 #define EXTI_PR_PR25 ((uint32_t)0x02000000) /*!< Pending bit for line 25 */
mbed_official 155:8435094ec241 5408 #define EXTI_PR_PR26 ((uint32_t)0x04000000) /*!< Pending bit for line 26 */
mbed_official 155:8435094ec241 5409 #define EXTI_PR_PR27 ((uint32_t)0x08000000) /*!< Pending bit for line 27 */
mbed_official 155:8435094ec241 5410 #define EXTI_PR_PR28 ((uint32_t)0x10000000) /*!< Pending bit for line 28 */
mbed_official 155:8435094ec241 5411
mbed_official 155:8435094ec241 5412 /******************************************************************************/
mbed_official 155:8435094ec241 5413 /* */
mbed_official 155:8435094ec241 5414 /* FLASH */
mbed_official 155:8435094ec241 5415 /* */
mbed_official 155:8435094ec241 5416 /******************************************************************************/
mbed_official 155:8435094ec241 5417 /******************* Bit definition for FLASH_ACR register ******************/
mbed_official 155:8435094ec241 5418 #define FLASH_ACR_LATENCY ((uint8_t)0x03) /*!< LATENCY[2:0] bits (Latency) */
mbed_official 155:8435094ec241 5419 #define FLASH_ACR_LATENCY_0 ((uint8_t)0x01) /*!< Bit 0 */
mbed_official 155:8435094ec241 5420 #define FLASH_ACR_LATENCY_1 ((uint8_t)0x02) /*!< Bit 1 */
mbed_official 155:8435094ec241 5421
mbed_official 155:8435094ec241 5422 #define FLASH_ACR_HLFCYA ((uint8_t)0x08) /*!< Flash Half Cycle Access Enable */
mbed_official 155:8435094ec241 5423 #define FLASH_ACR_PRFTBE ((uint8_t)0x10) /*!< Prefetch Buffer Enable */
mbed_official 155:8435094ec241 5424 #define FLASH_ACR_PRFTBS ((uint8_t)0x20)
mbed_official 155:8435094ec241 5425
mbed_official 155:8435094ec241 5426 /****************** Bit definition for FLASH_KEYR register ******************/
mbed_official 155:8435094ec241 5427 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
mbed_official 155:8435094ec241 5428
mbed_official 155:8435094ec241 5429 #define RDP_KEY ((uint16_t)0x00A5) /*!< RDP Key */
mbed_official 155:8435094ec241 5430 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< FPEC Key1 */
mbed_official 155:8435094ec241 5431 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< FPEC Key2 */
mbed_official 155:8435094ec241 5432
mbed_official 155:8435094ec241 5433 /***************** Bit definition for FLASH_OPTKEYR register ****************/
mbed_official 155:8435094ec241 5434 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
mbed_official 155:8435094ec241 5435
mbed_official 155:8435094ec241 5436 #define FLASH_OPTKEY1 FLASH_KEY1 /*!< Option Byte Key1 */
mbed_official 155:8435094ec241 5437 #define FLASH_OPTKEY2 FLASH_KEY2 /*!< Option Byte Key2 */
mbed_official 155:8435094ec241 5438
mbed_official 155:8435094ec241 5439 /****************** Bit definition for FLASH_SR register *******************/
mbed_official 155:8435094ec241 5440 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
mbed_official 155:8435094ec241 5441 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
mbed_official 155:8435094ec241 5442 #define FLASH_SR_WRPERR ((uint32_t)0x00000010) /*!< Write Protection Error */
mbed_official 155:8435094ec241 5443 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
mbed_official 155:8435094ec241 5444
mbed_official 155:8435094ec241 5445 /******************* Bit definition for FLASH_CR register *******************/
mbed_official 155:8435094ec241 5446 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
mbed_official 155:8435094ec241 5447 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
mbed_official 155:8435094ec241 5448 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
mbed_official 155:8435094ec241 5449 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
mbed_official 155:8435094ec241 5450 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
mbed_official 155:8435094ec241 5451 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
mbed_official 155:8435094ec241 5452 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
mbed_official 155:8435094ec241 5453 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
mbed_official 155:8435094ec241 5454 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
mbed_official 155:8435094ec241 5455 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
mbed_official 155:8435094ec241 5456 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< OptionBytes Loader Launch */
mbed_official 155:8435094ec241 5457
mbed_official 155:8435094ec241 5458 /******************* Bit definition for FLASH_AR register *******************/
mbed_official 155:8435094ec241 5459 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
mbed_official 155:8435094ec241 5460
mbed_official 155:8435094ec241 5461 /****************** Bit definition for FLASH_OBR register *******************/
mbed_official 155:8435094ec241 5462 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
mbed_official 155:8435094ec241 5463 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
mbed_official 155:8435094ec241 5464 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
mbed_official 155:8435094ec241 5465
mbed_official 155:8435094ec241 5466 #define FLASH_OBR_USER ((uint32_t)0x00003700) /*!< User Option Bytes */
mbed_official 155:8435094ec241 5467 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
mbed_official 155:8435094ec241 5468 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
mbed_official 155:8435094ec241 5469 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
mbed_official 155:8435094ec241 5470
mbed_official 155:8435094ec241 5471 /****************** Bit definition for FLASH_WRPR register ******************/
mbed_official 155:8435094ec241 5472 #define FLASH_WRPR_WRP ((uint32_t)0xFFFFFFFF) /*!< Write Protect */
mbed_official 155:8435094ec241 5473
mbed_official 155:8435094ec241 5474 /*----------------------------------------------------------------------------*/
mbed_official 155:8435094ec241 5475
mbed_official 155:8435094ec241 5476 /****************** Bit definition for OB_RDP register **********************/
mbed_official 155:8435094ec241 5477 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
mbed_official 155:8435094ec241 5478 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
mbed_official 155:8435094ec241 5479
mbed_official 155:8435094ec241 5480 /****************** Bit definition for OB_USER register *********************/
mbed_official 155:8435094ec241 5481 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
mbed_official 155:8435094ec241 5482 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
mbed_official 155:8435094ec241 5483
mbed_official 155:8435094ec241 5484 /****************** Bit definition for FLASH_WRP0 register ******************/
mbed_official 155:8435094ec241 5485 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 155:8435094ec241 5486 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 155:8435094ec241 5487
mbed_official 155:8435094ec241 5488 /****************** Bit definition for FLASH_WRP1 register ******************/
mbed_official 155:8435094ec241 5489 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 155:8435094ec241 5490 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 155:8435094ec241 5491
mbed_official 155:8435094ec241 5492 /****************** Bit definition for FLASH_WRP2 register ******************/
mbed_official 155:8435094ec241 5493 #define OB_WRP2_WRP2 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
mbed_official 155:8435094ec241 5494 #define OB_WRP2_nWRP2 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
mbed_official 155:8435094ec241 5495
mbed_official 155:8435094ec241 5496 /****************** Bit definition for FLASH_WRP3 register ******************/
mbed_official 155:8435094ec241 5497 #define OB_WRP3_WRP3 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
mbed_official 155:8435094ec241 5498 #define OB_WRP3_nWRP3 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
mbed_official 155:8435094ec241 5499 /******************************************************************************/
mbed_official 155:8435094ec241 5500 /* */
mbed_official 155:8435094ec241 5501 /* General Purpose I/O (GPIO) */
mbed_official 155:8435094ec241 5502 /* */
mbed_official 155:8435094ec241 5503 /******************************************************************************/
mbed_official 155:8435094ec241 5504 /******************* Bit definition for GPIO_MODER register *****************/
mbed_official 155:8435094ec241 5505 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
mbed_official 155:8435094ec241 5506 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5507 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5508 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
mbed_official 155:8435094ec241 5509 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5510 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5511 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
mbed_official 155:8435094ec241 5512 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5513 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5514 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
mbed_official 155:8435094ec241 5515 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5516 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5517 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
mbed_official 155:8435094ec241 5518 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5519 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5520 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
mbed_official 155:8435094ec241 5521 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5522 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5523 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
mbed_official 155:8435094ec241 5524 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5525 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5526 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
mbed_official 155:8435094ec241 5527 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5528 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5529 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
mbed_official 155:8435094ec241 5530 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 5531 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 5532 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
mbed_official 155:8435094ec241 5533 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 5534 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 5535 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
mbed_official 155:8435094ec241 5536 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 5537 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 5538 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
mbed_official 155:8435094ec241 5539 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 5540 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 5541 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
mbed_official 155:8435094ec241 5542 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 5543 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 5544 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
mbed_official 155:8435094ec241 5545 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 5546 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 5547 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
mbed_official 155:8435094ec241 5548 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
mbed_official 155:8435094ec241 5549 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
mbed_official 155:8435094ec241 5550 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
mbed_official 155:8435094ec241 5551 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
mbed_official 155:8435094ec241 5552 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
mbed_official 155:8435094ec241 5553
mbed_official 155:8435094ec241 5554
mbed_official 155:8435094ec241 5555 /****************** Bit definition for GPIO_OTYPER register *****************/
mbed_official 155:8435094ec241 5556 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5557 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5558 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5559 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5560 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5561 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5562 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5563 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5564 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5565 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5566 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5567 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5568 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5569 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5570 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5571 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5572
mbed_official 155:8435094ec241 5573
mbed_official 155:8435094ec241 5574 /**************** Bit definition for GPIO_OSPEEDR register ******************/
mbed_official 155:8435094ec241 5575 #define GPIO_OSPEEDER_OSPEEDR0 ((uint32_t)0x00000003)
mbed_official 155:8435094ec241 5576 #define GPIO_OSPEEDER_OSPEEDR0_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5577 #define GPIO_OSPEEDER_OSPEEDR0_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5578 #define GPIO_OSPEEDER_OSPEEDR1 ((uint32_t)0x0000000C)
mbed_official 155:8435094ec241 5579 #define GPIO_OSPEEDER_OSPEEDR1_0 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5580 #define GPIO_OSPEEDER_OSPEEDR1_1 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5581 #define GPIO_OSPEEDER_OSPEEDR2 ((uint32_t)0x00000030)
mbed_official 155:8435094ec241 5582 #define GPIO_OSPEEDER_OSPEEDR2_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5583 #define GPIO_OSPEEDER_OSPEEDR2_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5584 #define GPIO_OSPEEDER_OSPEEDR3 ((uint32_t)0x000000C0)
mbed_official 155:8435094ec241 5585 #define GPIO_OSPEEDER_OSPEEDR3_0 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5586 #define GPIO_OSPEEDER_OSPEEDR3_1 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5587 #define GPIO_OSPEEDER_OSPEEDR4 ((uint32_t)0x00000300)
mbed_official 155:8435094ec241 5588 #define GPIO_OSPEEDER_OSPEEDR4_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5589 #define GPIO_OSPEEDER_OSPEEDR4_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5590 #define GPIO_OSPEEDER_OSPEEDR5 ((uint32_t)0x00000C00)
mbed_official 155:8435094ec241 5591 #define GPIO_OSPEEDER_OSPEEDR5_0 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5592 #define GPIO_OSPEEDER_OSPEEDR5_1 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5593 #define GPIO_OSPEEDER_OSPEEDR6 ((uint32_t)0x00003000)
mbed_official 155:8435094ec241 5594 #define GPIO_OSPEEDER_OSPEEDR6_0 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5595 #define GPIO_OSPEEDER_OSPEEDR6_1 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5596 #define GPIO_OSPEEDER_OSPEEDR7 ((uint32_t)0x0000C000)
mbed_official 155:8435094ec241 5597 #define GPIO_OSPEEDER_OSPEEDR7_0 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5598 #define GPIO_OSPEEDER_OSPEEDR7_1 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5599 #define GPIO_OSPEEDER_OSPEEDR8 ((uint32_t)0x00030000)
mbed_official 155:8435094ec241 5600 #define GPIO_OSPEEDER_OSPEEDR8_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 5601 #define GPIO_OSPEEDER_OSPEEDR8_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 5602 #define GPIO_OSPEEDER_OSPEEDR9 ((uint32_t)0x000C0000)
mbed_official 155:8435094ec241 5603 #define GPIO_OSPEEDER_OSPEEDR9_0 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 5604 #define GPIO_OSPEEDER_OSPEEDR9_1 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 5605 #define GPIO_OSPEEDER_OSPEEDR10 ((uint32_t)0x00300000)
mbed_official 155:8435094ec241 5606 #define GPIO_OSPEEDER_OSPEEDR10_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 5607 #define GPIO_OSPEEDER_OSPEEDR10_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 5608 #define GPIO_OSPEEDER_OSPEEDR11 ((uint32_t)0x00C00000)
mbed_official 155:8435094ec241 5609 #define GPIO_OSPEEDER_OSPEEDR11_0 ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 5610 #define GPIO_OSPEEDER_OSPEEDR11_1 ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 5611 #define GPIO_OSPEEDER_OSPEEDR12 ((uint32_t)0x03000000)
mbed_official 155:8435094ec241 5612 #define GPIO_OSPEEDER_OSPEEDR12_0 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 5613 #define GPIO_OSPEEDER_OSPEEDR12_1 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 5614 #define GPIO_OSPEEDER_OSPEEDR13 ((uint32_t)0x0C000000)
mbed_official 155:8435094ec241 5615 #define GPIO_OSPEEDER_OSPEEDR13_0 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 5616 #define GPIO_OSPEEDER_OSPEEDR13_1 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 5617 #define GPIO_OSPEEDER_OSPEEDR14 ((uint32_t)0x30000000)
mbed_official 155:8435094ec241 5618 #define GPIO_OSPEEDER_OSPEEDR14_0 ((uint32_t)0x10000000)
mbed_official 155:8435094ec241 5619 #define GPIO_OSPEEDER_OSPEEDR14_1 ((uint32_t)0x20000000)
mbed_official 155:8435094ec241 5620 #define GPIO_OSPEEDER_OSPEEDR15 ((uint32_t)0xC0000000)
mbed_official 155:8435094ec241 5621 #define GPIO_OSPEEDER_OSPEEDR15_0 ((uint32_t)0x40000000)
mbed_official 155:8435094ec241 5622 #define GPIO_OSPEEDER_OSPEEDR15_1 ((uint32_t)0x80000000)
mbed_official 155:8435094ec241 5623
mbed_official 155:8435094ec241 5624 /******************* Bit definition for GPIO_PUPDR register ******************/
mbed_official 155:8435094ec241 5625 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
mbed_official 155:8435094ec241 5626 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5627 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5628 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
mbed_official 155:8435094ec241 5629 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5630 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5631 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
mbed_official 155:8435094ec241 5632 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5633 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5634 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
mbed_official 155:8435094ec241 5635 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5636 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5637 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
mbed_official 155:8435094ec241 5638 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5639 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5640 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
mbed_official 155:8435094ec241 5641 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5642 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5643 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
mbed_official 155:8435094ec241 5644 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5645 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5646 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
mbed_official 155:8435094ec241 5647 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5648 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5649 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
mbed_official 155:8435094ec241 5650 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 5651 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 5652 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
mbed_official 155:8435094ec241 5653 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 5654 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 5655 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
mbed_official 155:8435094ec241 5656 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 5657 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 5658 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
mbed_official 155:8435094ec241 5659 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 5660 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 5661 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
mbed_official 155:8435094ec241 5662 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 5663 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 5664 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
mbed_official 155:8435094ec241 5665 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 5666 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 5667 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
mbed_official 155:8435094ec241 5668 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
mbed_official 155:8435094ec241 5669 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
mbed_official 155:8435094ec241 5670 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
mbed_official 155:8435094ec241 5671 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
mbed_official 155:8435094ec241 5672 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
mbed_official 155:8435094ec241 5673
mbed_official 155:8435094ec241 5674 /******************* Bit definition for GPIO_IDR register *******************/
mbed_official 155:8435094ec241 5675 #define GPIO_IDR_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5676 #define GPIO_IDR_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5677 #define GPIO_IDR_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5678 #define GPIO_IDR_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5679 #define GPIO_IDR_4 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5680 #define GPIO_IDR_5 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5681 #define GPIO_IDR_6 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5682 #define GPIO_IDR_7 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5683 #define GPIO_IDR_8 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5684 #define GPIO_IDR_9 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5685 #define GPIO_IDR_10 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5686 #define GPIO_IDR_11 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5687 #define GPIO_IDR_12 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5688 #define GPIO_IDR_13 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5689 #define GPIO_IDR_14 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5690 #define GPIO_IDR_15 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5691
mbed_official 155:8435094ec241 5692 /****************** Bit definition for GPIO_ODR register ********************/
mbed_official 155:8435094ec241 5693 #define GPIO_ODR_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5694 #define GPIO_ODR_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5695 #define GPIO_ODR_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5696 #define GPIO_ODR_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5697 #define GPIO_ODR_4 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5698 #define GPIO_ODR_5 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5699 #define GPIO_ODR_6 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5700 #define GPIO_ODR_7 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5701 #define GPIO_ODR_8 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5702 #define GPIO_ODR_9 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5703 #define GPIO_ODR_10 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5704 #define GPIO_ODR_11 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5705 #define GPIO_ODR_12 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5706 #define GPIO_ODR_13 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5707 #define GPIO_ODR_14 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5708 #define GPIO_ODR_15 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5709
mbed_official 155:8435094ec241 5710 /****************** Bit definition for GPIO_BSRR register ********************/
mbed_official 155:8435094ec241 5711 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5712 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5713 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5714 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5715 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5716 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5717 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5718 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5719 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5720 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5721 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5722 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5723 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5724 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5725 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5726 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5727 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 5728 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 5729 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 5730 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 5731 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 5732 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 5733 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 5734 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 5735 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 5736 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 5737 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 5738 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 5739 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
mbed_official 155:8435094ec241 5740 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
mbed_official 155:8435094ec241 5741 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
mbed_official 155:8435094ec241 5742 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
mbed_official 155:8435094ec241 5743
mbed_official 155:8435094ec241 5744 /****************** Bit definition for GPIO_LCKR register ********************/
mbed_official 155:8435094ec241 5745 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5746 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5747 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5748 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5749 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5750 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5751 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5752 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5753 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5754 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5755 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5756 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5757 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5758 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5759 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5760 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5761 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 5762
mbed_official 155:8435094ec241 5763 /****************** Bit definition for GPIO_AFRL register ********************/
mbed_official 155:8435094ec241 5764 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 5765 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
mbed_official 155:8435094ec241 5766 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 5767 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
mbed_official 155:8435094ec241 5768 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
mbed_official 155:8435094ec241 5769 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
mbed_official 155:8435094ec241 5770 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
mbed_official 155:8435094ec241 5771 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
mbed_official 155:8435094ec241 5772
mbed_official 155:8435094ec241 5773 /****************** Bit definition for GPIO_AFRH register ********************/
mbed_official 155:8435094ec241 5774 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 5775 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
mbed_official 155:8435094ec241 5776 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 5777 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
mbed_official 155:8435094ec241 5778 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
mbed_official 155:8435094ec241 5779 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
mbed_official 155:8435094ec241 5780 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
mbed_official 155:8435094ec241 5781 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
mbed_official 155:8435094ec241 5782
mbed_official 155:8435094ec241 5783 /****************** Bit definition for GPIO_BRR register *********************/
mbed_official 155:8435094ec241 5784 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5785 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5786 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 5787 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 5788 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 5789 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 5790 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 5791 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 5792 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 5793 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 5794 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 5795 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 5796 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 5797 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 5798 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 5799 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 5800
mbed_official 155:8435094ec241 5801 /******************************************************************************/
mbed_official 155:8435094ec241 5802 /* */
mbed_official 155:8435094ec241 5803 /* Inter-integrated Circuit Interface (I2C) */
mbed_official 155:8435094ec241 5804 /* */
mbed_official 155:8435094ec241 5805 /******************************************************************************/
mbed_official 155:8435094ec241 5806 /******************* Bit definition for I2C_CR1 register *******************/
mbed_official 155:8435094ec241 5807 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
mbed_official 155:8435094ec241 5808 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
mbed_official 155:8435094ec241 5809 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
mbed_official 155:8435094ec241 5810 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
mbed_official 155:8435094ec241 5811 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
mbed_official 155:8435094ec241 5812 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
mbed_official 155:8435094ec241 5813 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
mbed_official 155:8435094ec241 5814 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
mbed_official 155:8435094ec241 5815 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
mbed_official 155:8435094ec241 5816 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
mbed_official 155:8435094ec241 5817 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
mbed_official 155:8435094ec241 5818 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
mbed_official 155:8435094ec241 5819 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
mbed_official 155:8435094ec241 5820 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
mbed_official 155:8435094ec241 5821 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
mbed_official 155:8435094ec241 5822 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
mbed_official 155:8435094ec241 5823 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
mbed_official 155:8435094ec241 5824 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
mbed_official 155:8435094ec241 5825 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
mbed_official 155:8435094ec241 5826 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
mbed_official 155:8435094ec241 5827 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
mbed_official 155:8435094ec241 5828
mbed_official 155:8435094ec241 5829 /****************** Bit definition for I2C_CR2 register ********************/
mbed_official 155:8435094ec241 5830 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
mbed_official 155:8435094ec241 5831 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
mbed_official 155:8435094ec241 5832 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
mbed_official 155:8435094ec241 5833 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
mbed_official 155:8435094ec241 5834 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
mbed_official 155:8435094ec241 5835 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
mbed_official 155:8435094ec241 5836 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
mbed_official 155:8435094ec241 5837 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
mbed_official 155:8435094ec241 5838 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
mbed_official 155:8435094ec241 5839 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
mbed_official 155:8435094ec241 5840 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
mbed_official 155:8435094ec241 5841
mbed_official 155:8435094ec241 5842 /******************* Bit definition for I2C_OAR1 register ******************/
mbed_official 155:8435094ec241 5843 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
mbed_official 155:8435094ec241 5844 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
mbed_official 155:8435094ec241 5845 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
mbed_official 155:8435094ec241 5846
mbed_official 155:8435094ec241 5847 /******************* Bit definition for I2C_OAR2 register *******************/
mbed_official 155:8435094ec241 5848 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
mbed_official 155:8435094ec241 5849 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
mbed_official 155:8435094ec241 5850 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
mbed_official 155:8435094ec241 5851
mbed_official 155:8435094ec241 5852 /******************* Bit definition for I2C_TIMINGR register *****************/
mbed_official 155:8435094ec241 5853 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
mbed_official 155:8435094ec241 5854 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
mbed_official 155:8435094ec241 5855 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
mbed_official 155:8435094ec241 5856 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
mbed_official 155:8435094ec241 5857 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
mbed_official 155:8435094ec241 5858
mbed_official 155:8435094ec241 5859 /******************* Bit definition for I2C_TIMEOUTR register *****************/
mbed_official 155:8435094ec241 5860 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
mbed_official 155:8435094ec241 5861 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
mbed_official 155:8435094ec241 5862 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
mbed_official 155:8435094ec241 5863 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
mbed_official 155:8435094ec241 5864 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
mbed_official 155:8435094ec241 5865
mbed_official 155:8435094ec241 5866 /****************** Bit definition for I2C_ISR register *********************/
mbed_official 155:8435094ec241 5867 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
mbed_official 155:8435094ec241 5868 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
mbed_official 155:8435094ec241 5869 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
mbed_official 155:8435094ec241 5870 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
mbed_official 155:8435094ec241 5871 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
mbed_official 155:8435094ec241 5872 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
mbed_official 155:8435094ec241 5873 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
mbed_official 155:8435094ec241 5874 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
mbed_official 155:8435094ec241 5875 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
mbed_official 155:8435094ec241 5876 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
mbed_official 155:8435094ec241 5877 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
mbed_official 155:8435094ec241 5878 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
mbed_official 155:8435094ec241 5879 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
mbed_official 155:8435094ec241 5880 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
mbed_official 155:8435094ec241 5881 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
mbed_official 155:8435094ec241 5882 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
mbed_official 155:8435094ec241 5883 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
mbed_official 155:8435094ec241 5884
mbed_official 155:8435094ec241 5885 /****************** Bit definition for I2C_ICR register *********************/
mbed_official 155:8435094ec241 5886 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
mbed_official 155:8435094ec241 5887 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
mbed_official 155:8435094ec241 5888 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
mbed_official 155:8435094ec241 5889 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
mbed_official 155:8435094ec241 5890 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
mbed_official 155:8435094ec241 5891 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
mbed_official 155:8435094ec241 5892 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
mbed_official 155:8435094ec241 5893 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
mbed_official 155:8435094ec241 5894 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
mbed_official 155:8435094ec241 5895
mbed_official 155:8435094ec241 5896 /****************** Bit definition for I2C_PECR register ********************/
mbed_official 155:8435094ec241 5897 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
mbed_official 155:8435094ec241 5898
mbed_official 155:8435094ec241 5899 /****************** Bit definition for I2C_RXDR register *********************/
mbed_official 155:8435094ec241 5900 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
mbed_official 155:8435094ec241 5901
mbed_official 155:8435094ec241 5902 /****************** Bit definition for I2C_TXDR register *********************/
mbed_official 155:8435094ec241 5903 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
mbed_official 155:8435094ec241 5904
mbed_official 155:8435094ec241 5905
mbed_official 155:8435094ec241 5906 /******************************************************************************/
mbed_official 155:8435094ec241 5907 /* */
mbed_official 155:8435094ec241 5908 /* Independent WATCHDOG (IWDG) */
mbed_official 155:8435094ec241 5909 /* */
mbed_official 155:8435094ec241 5910 /******************************************************************************/
mbed_official 155:8435094ec241 5911 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 155:8435094ec241 5912 #define IWDG_KR_KEY ((uint16_t)0xFFFF) /*!< Key value (write only, read 0000h) */
mbed_official 155:8435094ec241 5913
mbed_official 155:8435094ec241 5914 /******************* Bit definition for IWDG_PR register ********************/
mbed_official 155:8435094ec241 5915 #define IWDG_PR_PR ((uint8_t)0x07) /*!< PR[2:0] (Prescaler divider) */
mbed_official 155:8435094ec241 5916 #define IWDG_PR_PR_0 ((uint8_t)0x01) /*!< Bit 0 */
mbed_official 155:8435094ec241 5917 #define IWDG_PR_PR_1 ((uint8_t)0x02) /*!< Bit 1 */
mbed_official 155:8435094ec241 5918 #define IWDG_PR_PR_2 ((uint8_t)0x04) /*!< Bit 2 */
mbed_official 155:8435094ec241 5919
mbed_official 155:8435094ec241 5920 /******************* Bit definition for IWDG_RLR register *******************/
mbed_official 155:8435094ec241 5921 #define IWDG_RLR_RL ((uint16_t)0x0FFF) /*!< Watchdog counter reload value */
mbed_official 155:8435094ec241 5922
mbed_official 155:8435094ec241 5923 /******************* Bit definition for IWDG_SR register ********************/
mbed_official 155:8435094ec241 5924 #define IWDG_SR_PVU ((uint8_t)0x01) /*!< Watchdog prescaler value update */
mbed_official 155:8435094ec241 5925 #define IWDG_SR_RVU ((uint8_t)0x02) /*!< Watchdog counter reload value update */
mbed_official 155:8435094ec241 5926 #define IWDG_SR_WVU ((uint8_t)0x04) /*!< Watchdog counter window value update */
mbed_official 155:8435094ec241 5927
mbed_official 155:8435094ec241 5928 /******************* Bit definition for IWDG_KR register ********************/
mbed_official 155:8435094ec241 5929 #define IWDG_WINR_WIN ((uint16_t)0x0FFF) /*!< Watchdog counter window value */
mbed_official 155:8435094ec241 5930
mbed_official 155:8435094ec241 5931 /******************************************************************************/
mbed_official 155:8435094ec241 5932 /* */
mbed_official 155:8435094ec241 5933 /* Power Control */
mbed_official 155:8435094ec241 5934 /* */
mbed_official 155:8435094ec241 5935 /******************************************************************************/
mbed_official 155:8435094ec241 5936 /******************** Bit definition for PWR_CR register ********************/
mbed_official 155:8435094ec241 5937 #define PWR_CR_LPSDSR ((uint16_t)0x0001) /*!< Low-power deepsleep/sleep/low power run */
mbed_official 155:8435094ec241 5938 #define PWR_CR_PDDS ((uint16_t)0x0002) /*!< Power Down Deepsleep */
mbed_official 155:8435094ec241 5939 #define PWR_CR_CWUF ((uint16_t)0x0004) /*!< Clear Wakeup Flag */
mbed_official 155:8435094ec241 5940 #define PWR_CR_CSBF ((uint16_t)0x0008) /*!< Clear Standby Flag */
mbed_official 155:8435094ec241 5941 #define PWR_CR_PVDE ((uint16_t)0x0010) /*!< Power Voltage Detector Enable */
mbed_official 155:8435094ec241 5942
mbed_official 155:8435094ec241 5943 #define PWR_CR_PLS ((uint16_t)0x00E0) /*!< PLS[2:0] bits (PVD Level Selection) */
mbed_official 155:8435094ec241 5944 #define PWR_CR_PLS_0 ((uint16_t)0x0020) /*!< Bit 0 */
mbed_official 155:8435094ec241 5945 #define PWR_CR_PLS_1 ((uint16_t)0x0040) /*!< Bit 1 */
mbed_official 155:8435094ec241 5946 #define PWR_CR_PLS_2 ((uint16_t)0x0080) /*!< Bit 2 */
mbed_official 155:8435094ec241 5947
mbed_official 155:8435094ec241 5948 /*!< PVD level configuration */
mbed_official 155:8435094ec241 5949 #define PWR_CR_PLS_LEV0 ((uint16_t)0x0000) /*!< PVD level 0 */
mbed_official 155:8435094ec241 5950 #define PWR_CR_PLS_LEV1 ((uint16_t)0x0020) /*!< PVD level 1 */
mbed_official 155:8435094ec241 5951 #define PWR_CR_PLS_LEV2 ((uint16_t)0x0040) /*!< PVD level 2 */
mbed_official 155:8435094ec241 5952 #define PWR_CR_PLS_LEV3 ((uint16_t)0x0060) /*!< PVD level 3 */
mbed_official 155:8435094ec241 5953 #define PWR_CR_PLS_LEV4 ((uint16_t)0x0080) /*!< PVD level 4 */
mbed_official 155:8435094ec241 5954 #define PWR_CR_PLS_LEV5 ((uint16_t)0x00A0) /*!< PVD level 5 */
mbed_official 155:8435094ec241 5955 #define PWR_CR_PLS_LEV6 ((uint16_t)0x00C0) /*!< PVD level 6 */
mbed_official 155:8435094ec241 5956 #define PWR_CR_PLS_LEV7 ((uint16_t)0x00E0) /*!< PVD level 7 */
mbed_official 155:8435094ec241 5957
mbed_official 155:8435094ec241 5958 #define PWR_CR_DBP ((uint16_t)0x0100) /*!< Disable Backup Domain write protection */
mbed_official 155:8435094ec241 5959
mbed_official 155:8435094ec241 5960 /******************* Bit definition for PWR_CSR register ********************/
mbed_official 155:8435094ec241 5961 #define PWR_CSR_WUF ((uint16_t)0x0001) /*!< Wakeup Flag */
mbed_official 155:8435094ec241 5962 #define PWR_CSR_SBF ((uint16_t)0x0002) /*!< Standby Flag */
mbed_official 155:8435094ec241 5963 #define PWR_CSR_PVDO ((uint16_t)0x0004) /*!< PVD Output */
mbed_official 155:8435094ec241 5964 #define PWR_CSR_VREFINTRDYF ((uint16_t)0x0008) /*!< Internal voltage reference (VREFINT) ready flag */
mbed_official 155:8435094ec241 5965
mbed_official 155:8435094ec241 5966 #define PWR_CSR_EWUP1 ((uint16_t)0x0100) /*!< Enable WKUP pin 1 */
mbed_official 155:8435094ec241 5967 #define PWR_CSR_EWUP2 ((uint16_t)0x0200) /*!< Enable WKUP pin 2 */
mbed_official 155:8435094ec241 5968 #define PWR_CSR_EWUP3 ((uint16_t)0x0400) /*!< Enable WKUP pin 3 */
mbed_official 155:8435094ec241 5969
mbed_official 155:8435094ec241 5970 /******************************************************************************/
mbed_official 155:8435094ec241 5971 /* */
mbed_official 155:8435094ec241 5972 /* Reset and Clock Control */
mbed_official 155:8435094ec241 5973 /* */
mbed_official 155:8435094ec241 5974 /******************************************************************************/
mbed_official 155:8435094ec241 5975 /******************** Bit definition for RCC_CR register ********************/
mbed_official 155:8435094ec241 5976 #define RCC_CR_HSION ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 5977 #define RCC_CR_HSIRDY ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 5978
mbed_official 155:8435094ec241 5979 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8)
mbed_official 155:8435094ec241 5980 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008)/*!<Bit 0 */
mbed_official 155:8435094ec241 5981 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010)/*!<Bit 1 */
mbed_official 155:8435094ec241 5982 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020)/*!<Bit 2 */
mbed_official 155:8435094ec241 5983 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040)/*!<Bit 3 */
mbed_official 155:8435094ec241 5984 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080)/*!<Bit 4 */
mbed_official 155:8435094ec241 5985
mbed_official 155:8435094ec241 5986 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00)
mbed_official 155:8435094ec241 5987 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100)/*!<Bit 0 */
mbed_official 155:8435094ec241 5988 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200)/*!<Bit 1 */
mbed_official 155:8435094ec241 5989 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400)/*!<Bit 2 */
mbed_official 155:8435094ec241 5990 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800)/*!<Bit 3 */
mbed_official 155:8435094ec241 5991 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000)/*!<Bit 4 */
mbed_official 155:8435094ec241 5992 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000)/*!<Bit 5 */
mbed_official 155:8435094ec241 5993 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000)/*!<Bit 6 */
mbed_official 155:8435094ec241 5994 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000)/*!<Bit 7 */
mbed_official 155:8435094ec241 5995
mbed_official 155:8435094ec241 5996 #define RCC_CR_HSEON ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 5997 #define RCC_CR_HSERDY ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 5998 #define RCC_CR_HSEBYP ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 5999 #define RCC_CR_CSSON ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 6000
mbed_official 155:8435094ec241 6001 #define RCC_CR_PLLON ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 6002 #define RCC_CR_PLLRDY ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 6003
mbed_official 155:8435094ec241 6004 /******************** Bit definition for RCC_CFGR register ******************/
mbed_official 155:8435094ec241 6005 /*!< SW configuration */
mbed_official 155:8435094ec241 6006 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
mbed_official 155:8435094ec241 6007 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 155:8435094ec241 6008 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 155:8435094ec241 6009
mbed_official 155:8435094ec241 6010 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
mbed_official 155:8435094ec241 6011 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
mbed_official 155:8435094ec241 6012 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
mbed_official 155:8435094ec241 6013
mbed_official 155:8435094ec241 6014 /*!< SWS configuration */
mbed_official 155:8435094ec241 6015 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
mbed_official 155:8435094ec241 6016 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
mbed_official 155:8435094ec241 6017 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
mbed_official 155:8435094ec241 6018
mbed_official 155:8435094ec241 6019 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
mbed_official 155:8435094ec241 6020 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
mbed_official 155:8435094ec241 6021 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
mbed_official 155:8435094ec241 6022
mbed_official 155:8435094ec241 6023 /*!< HPRE configuration */
mbed_official 155:8435094ec241 6024 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
mbed_official 155:8435094ec241 6025 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 155:8435094ec241 6026 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 155:8435094ec241 6027 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 155:8435094ec241 6028 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 155:8435094ec241 6029
mbed_official 155:8435094ec241 6030 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
mbed_official 155:8435094ec241 6031 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
mbed_official 155:8435094ec241 6032 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
mbed_official 155:8435094ec241 6033 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
mbed_official 155:8435094ec241 6034 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
mbed_official 155:8435094ec241 6035 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
mbed_official 155:8435094ec241 6036 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
mbed_official 155:8435094ec241 6037 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
mbed_official 155:8435094ec241 6038 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
mbed_official 155:8435094ec241 6039
mbed_official 155:8435094ec241 6040 /*!< PPRE1 configuration */
mbed_official 155:8435094ec241 6041 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700) /*!< PRE1[2:0] bits (APB1 prescaler) */
mbed_official 155:8435094ec241 6042 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 155:8435094ec241 6043 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 155:8435094ec241 6044 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400) /*!< Bit 2 */
mbed_official 155:8435094ec241 6045
mbed_official 155:8435094ec241 6046 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 155:8435094ec241 6047 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
mbed_official 155:8435094ec241 6048 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
mbed_official 155:8435094ec241 6049 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
mbed_official 155:8435094ec241 6050 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
mbed_official 155:8435094ec241 6051
mbed_official 155:8435094ec241 6052 /*!< PPRE2 configuration */
mbed_official 155:8435094ec241 6053 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800) /*!< PRE2[2:0] bits (APB2 prescaler) */
mbed_official 155:8435094ec241 6054 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800) /*!< Bit 0 */
mbed_official 155:8435094ec241 6055 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6056 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000) /*!< Bit 2 */
mbed_official 155:8435094ec241 6057
mbed_official 155:8435094ec241 6058 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
mbed_official 155:8435094ec241 6059 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000) /*!< HCLK divided by 2 */
mbed_official 155:8435094ec241 6060 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800) /*!< HCLK divided by 4 */
mbed_official 155:8435094ec241 6061 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000) /*!< HCLK divided by 8 */
mbed_official 155:8435094ec241 6062 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800) /*!< HCLK divided by 16 */
mbed_official 155:8435094ec241 6063
mbed_official 155:8435094ec241 6064 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
mbed_official 155:8435094ec241 6065
mbed_official 155:8435094ec241 6066 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
mbed_official 155:8435094ec241 6067
mbed_official 155:8435094ec241 6068 /*!< PLLMUL configuration */
mbed_official 155:8435094ec241 6069 #define RCC_CFGR_PLLMULL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
mbed_official 155:8435094ec241 6070 #define RCC_CFGR_PLLMULL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 155:8435094ec241 6071 #define RCC_CFGR_PLLMULL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6072 #define RCC_CFGR_PLLMULL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
mbed_official 155:8435094ec241 6073 #define RCC_CFGR_PLLMULL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
mbed_official 155:8435094ec241 6074
mbed_official 155:8435094ec241 6075 #define RCC_CFGR_PLLSRC_HSI_Div2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
mbed_official 155:8435094ec241 6076 #define RCC_CFGR_PLLSRC_PREDIV1 ((uint32_t)0x00010000) /*!< PREDIV1 clock selected as PLL entry clock source */
mbed_official 155:8435094ec241 6077
mbed_official 155:8435094ec241 6078 #define RCC_CFGR_PLLXTPRE_PREDIV1 ((uint32_t)0x00000000) /*!< PREDIV1 clock not divided for PLL entry */
mbed_official 155:8435094ec241 6079 #define RCC_CFGR_PLLXTPRE_PREDIV1_Div2 ((uint32_t)0x00020000) /*!< PREDIV1 clock divided by 2 for PLL entry */
mbed_official 155:8435094ec241 6080
mbed_official 155:8435094ec241 6081 #define RCC_CFGR_PLLMULL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
mbed_official 155:8435094ec241 6082 #define RCC_CFGR_PLLMULL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
mbed_official 155:8435094ec241 6083 #define RCC_CFGR_PLLMULL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
mbed_official 155:8435094ec241 6084 #define RCC_CFGR_PLLMULL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
mbed_official 155:8435094ec241 6085 #define RCC_CFGR_PLLMULL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
mbed_official 155:8435094ec241 6086 #define RCC_CFGR_PLLMULL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
mbed_official 155:8435094ec241 6087 #define RCC_CFGR_PLLMULL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
mbed_official 155:8435094ec241 6088 #define RCC_CFGR_PLLMULL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
mbed_official 155:8435094ec241 6089 #define RCC_CFGR_PLLMULL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
mbed_official 155:8435094ec241 6090 #define RCC_CFGR_PLLMULL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
mbed_official 155:8435094ec241 6091 #define RCC_CFGR_PLLMULL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
mbed_official 155:8435094ec241 6092 #define RCC_CFGR_PLLMULL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
mbed_official 155:8435094ec241 6093 #define RCC_CFGR_PLLMULL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
mbed_official 155:8435094ec241 6094 #define RCC_CFGR_PLLMULL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
mbed_official 155:8435094ec241 6095 #define RCC_CFGR_PLLMULL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
mbed_official 155:8435094ec241 6096
mbed_official 155:8435094ec241 6097 /*!< USB configuration */
mbed_official 155:8435094ec241 6098 #define RCC_CFGR_USBPRE ((uint32_t)0x00400000) /*!< USB prescaler */
mbed_official 155:8435094ec241 6099
mbed_official 155:8435094ec241 6100 /*!< I2S configuration */
mbed_official 155:8435094ec241 6101 #define RCC_CFGR_I2SSRC ((uint32_t)0x00800000) /*!< I2S external clock source selection */
mbed_official 155:8435094ec241 6102
mbed_official 155:8435094ec241 6103 /*!< MCO configuration */
mbed_official 155:8435094ec241 6104 #define RCC_CFGR_MCO ((uint32_t)0x07000000) /*!< MCO[2:0] bits (Microcontroller Clock Output) */
mbed_official 155:8435094ec241 6105 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
mbed_official 155:8435094ec241 6106 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6107 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
mbed_official 155:8435094ec241 6108
mbed_official 155:8435094ec241 6109 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 155:8435094ec241 6110 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
mbed_official 155:8435094ec241 6111 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
mbed_official 155:8435094ec241 6112 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
mbed_official 155:8435094ec241 6113 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
mbed_official 155:8435094ec241 6114 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
mbed_official 155:8435094ec241 6115 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
mbed_official 155:8435094ec241 6116
mbed_official 155:8435094ec241 6117 #define RCC_CFGR_MCOF ((uint32_t)0x10000000) /*!< Microcontroller Clock Output Flag */
mbed_official 155:8435094ec241 6118
mbed_official 155:8435094ec241 6119 #define RCC_CFGR_MCO_PRE ((uint32_t)0x70000000) /*!< MCO prescaler */
mbed_official 155:8435094ec241 6120 #define RCC_CFGR_MCO_PRE_1 ((uint32_t)0x00000000) /*!< MCO is divided by 1 */
mbed_official 155:8435094ec241 6121 #define RCC_CFGR_MCO_PRE_2 ((uint32_t)0x10000000) /*!< MCO is divided by 2 */
mbed_official 155:8435094ec241 6122 #define RCC_CFGR_MCO_PRE_4 ((uint32_t)0x20000000) /*!< MCO is divided by 4 */
mbed_official 155:8435094ec241 6123 #define RCC_CFGR_MCO_PRE_8 ((uint32_t)0x30000000) /*!< MCO is divided by 8 */
mbed_official 155:8435094ec241 6124 #define RCC_CFGR_MCO_PRE_16 ((uint32_t)0x40000000) /*!< MCO is divided by 16 */
mbed_official 155:8435094ec241 6125 #define RCC_CFGR_MCO_PRE_32 ((uint32_t)0x50000000) /*!< MCO is divided by 32 */
mbed_official 155:8435094ec241 6126 #define RCC_CFGR_MCO_PRE_64 ((uint32_t)0x60000000) /*!< MCO is divided by 64 */
mbed_official 155:8435094ec241 6127 #define RCC_CFGR_MCO_PRE_128 ((uint32_t)0x70000000) /*!< MCO is divided by 128 */
mbed_official 155:8435094ec241 6128
mbed_official 155:8435094ec241 6129 #define RCC_CFGR_PLLNODIV ((uint32_t)0x80000000) /*!< PLL is not divided to MCO */
mbed_official 155:8435094ec241 6130
mbed_official 155:8435094ec241 6131 /********************* Bit definition for RCC_CIR register ********************/
mbed_official 155:8435094ec241 6132 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
mbed_official 155:8435094ec241 6133 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
mbed_official 155:8435094ec241 6134 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
mbed_official 155:8435094ec241 6135 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
mbed_official 155:8435094ec241 6136 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
mbed_official 155:8435094ec241 6137 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
mbed_official 155:8435094ec241 6138 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
mbed_official 155:8435094ec241 6139 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
mbed_official 155:8435094ec241 6140 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
mbed_official 155:8435094ec241 6141 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
mbed_official 155:8435094ec241 6142 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
mbed_official 155:8435094ec241 6143 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
mbed_official 155:8435094ec241 6144 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
mbed_official 155:8435094ec241 6145 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
mbed_official 155:8435094ec241 6146 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
mbed_official 155:8435094ec241 6147 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
mbed_official 155:8435094ec241 6148 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
mbed_official 155:8435094ec241 6149
mbed_official 155:8435094ec241 6150 /****************** Bit definition for RCC_APB2RSTR register *****************/
mbed_official 155:8435094ec241 6151 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG reset */
mbed_official 155:8435094ec241 6152 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000200) /*!< TIM1 reset */
mbed_official 155:8435094ec241 6153 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 reset */
mbed_official 155:8435094ec241 6154 #define RCC_APB2RSTR_TIM8RST ((uint32_t)0x00000200) /*!< TIM8 reset */
mbed_official 155:8435094ec241 6155 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 reset */
mbed_official 155:8435094ec241 6156 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 reset */
mbed_official 155:8435094ec241 6157 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 reset */
mbed_official 155:8435094ec241 6158 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 reset */
mbed_official 155:8435094ec241 6159 #define RCC_APB2RSTR_HRTIM1RST ((uint32_t)0x20000000) /*!< HRTIM1 reset */
mbed_official 155:8435094ec241 6160
mbed_official 155:8435094ec241 6161 /****************** Bit definition for RCC_APB1RSTR register ******************/
mbed_official 155:8435094ec241 6162 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001) /*!< Timer 2 reset */
mbed_official 155:8435094ec241 6163 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 reset */
mbed_official 155:8435094ec241 6164 #define RCC_APB1RSTR_TIM4RST ((uint32_t)0x00000004) /*!< Timer 4 reset */
mbed_official 155:8435094ec241 6165 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 reset */
mbed_official 155:8435094ec241 6166 #define RCC_APB1RSTR_TIM7RST ((uint32_t)0x00000020) /*!< Timer 7 reset */
mbed_official 155:8435094ec241 6167 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog reset */
mbed_official 155:8435094ec241 6168 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 reset */
mbed_official 155:8435094ec241 6169 #define RCC_APB1RSTR_SPI3RST ((uint32_t)0x00008000) /*!< SPI3 reset */
mbed_official 155:8435094ec241 6170 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 reset */
mbed_official 155:8435094ec241 6171 #define RCC_APB1RSTR_USART3RST ((uint32_t)0x00040000) /*!< USART 3 reset */
mbed_official 155:8435094ec241 6172 #define RCC_APB1RSTR_UART4RST ((uint32_t)0x00080000) /*!< UART 4 reset */
mbed_official 155:8435094ec241 6173 #define RCC_APB1RSTR_UART5RST ((uint32_t)0x00100000) /*!< UART 5 reset */
mbed_official 155:8435094ec241 6174 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 reset */
mbed_official 155:8435094ec241 6175 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 reset */
mbed_official 155:8435094ec241 6176 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000) /*!< USB reset */
mbed_official 155:8435094ec241 6177 #define RCC_APB1RSTR_CAN1RST ((uint32_t)0x02000000) /*!< CAN reset */
mbed_official 155:8435094ec241 6178 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR reset */
mbed_official 155:8435094ec241 6179 #define RCC_APB1RSTR_DAC1RST ((uint32_t)0x20000000) /*!< DAC 1 reset */
mbed_official 155:8435094ec241 6180 #define RCC_APB1RSTR_I2C3RST ((uint32_t)0x40000000) /*!< I2C 3 reset */
mbed_official 155:8435094ec241 6181 #define RCC_APB1RSTR_DAC2RST ((uint32_t)0x04000000) /*!< DAC 2 reset */
mbed_official 155:8435094ec241 6182 #define RCC_APB1RSTR_DACRST RCC_APB1RSTR_DAC1RST /*!< DAC reset */
mbed_official 155:8435094ec241 6183
mbed_official 155:8435094ec241 6184 /****************** Bit definition for RCC_AHBENR register ******************/
mbed_official 155:8435094ec241 6185 #define RCC_AHBENR_DMA1EN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
mbed_official 155:8435094ec241 6186 #define RCC_AHBENR_DMA2EN ((uint32_t)0x00000002) /*!< DMA2 clock enable */
mbed_official 155:8435094ec241 6187 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
mbed_official 155:8435094ec241 6188 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
mbed_official 155:8435094ec241 6189 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
mbed_official 155:8435094ec241 6190 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
mbed_official 155:8435094ec241 6191 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
mbed_official 155:8435094ec241 6192 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
mbed_official 155:8435094ec241 6193 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
mbed_official 155:8435094ec241 6194 #define RCC_AHBENR_GPIOEEN ((uint32_t)0x00200000) /*!< GPIOE clock enable */
mbed_official 155:8435094ec241 6195 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
mbed_official 155:8435094ec241 6196 #define RCC_AHBENR_TSEN ((uint32_t)0x01000000) /*!< TS clock enable */
mbed_official 155:8435094ec241 6197 #define RCC_AHBENR_ADC12EN ((uint32_t)0x10000000) /*!< ADC1/ ADC2 clock enable */
mbed_official 155:8435094ec241 6198 #define RCC_AHBENR_ADC34EN ((uint32_t)0x20000000) /*!< ADC1/ ADC2 clock enable */
mbed_official 155:8435094ec241 6199
mbed_official 155:8435094ec241 6200 /***************** Bit definition for RCC_APB2ENR register ******************/
mbed_official 155:8435094ec241 6201 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001) /*!< SYSCFG clock enable */
mbed_official 155:8435094ec241 6202 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
mbed_official 155:8435094ec241 6203 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
mbed_official 155:8435094ec241 6204 #define RCC_APB2ENR_TIM8EN ((uint32_t)0x00002000) /*!< TIM8 clock enable */
mbed_official 155:8435094ec241 6205 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
mbed_official 155:8435094ec241 6206 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
mbed_official 155:8435094ec241 6207 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
mbed_official 155:8435094ec241 6208 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
mbed_official 155:8435094ec241 6209 #define RCC_APB2ENR_HRTIM1 ((uint32_t)0x20000000) /*!< HRTIM1 clock enable */
mbed_official 155:8435094ec241 6210
mbed_official 155:8435094ec241 6211 /****************** Bit definition for RCC_APB1ENR register ******************/
mbed_official 155:8435094ec241 6212 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001) /*!< Timer 2 clock enable */
mbed_official 155:8435094ec241 6213 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
mbed_official 155:8435094ec241 6214 #define RCC_APB1ENR_TIM4EN ((uint32_t)0x00000004) /*!< Timer 4 clock enable */
mbed_official 155:8435094ec241 6215 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
mbed_official 155:8435094ec241 6216 #define RCC_APB1ENR_TIM7EN ((uint32_t)0x00000020) /*!< Timer 7 clock enable */
mbed_official 155:8435094ec241 6217 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
mbed_official 155:8435094ec241 6218 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
mbed_official 155:8435094ec241 6219 #define RCC_APB1ENR_SPI3EN ((uint32_t)0x00008000) /*!< SPI3 clock enable */
mbed_official 155:8435094ec241 6220 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART 2 clock enable */
mbed_official 155:8435094ec241 6221 #define RCC_APB1ENR_USART3EN ((uint32_t)0x00040000) /*!< USART 3 clock enable */
mbed_official 155:8435094ec241 6222 #define RCC_APB1ENR_UART4EN ((uint32_t)0x00080000) /*!< UART 4 clock enable */
mbed_official 155:8435094ec241 6223 #define RCC_APB1ENR_UART5EN ((uint32_t)0x00100000) /*!< UART 5 clock enable */
mbed_official 155:8435094ec241 6224 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C 1 clock enable */
mbed_official 155:8435094ec241 6225 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C 2 clock enable */
mbed_official 155:8435094ec241 6226 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000) /*!< USB clock enable */
mbed_official 155:8435094ec241 6227 #define RCC_APB1ENR_CAN1EN ((uint32_t)0x02000000) /*!< CAN clock enable */
mbed_official 155:8435094ec241 6228 #define RCC_APB1ENR_DAC2EN ((uint32_t)0x04000000) /*!< DAC 2 clock enable */
mbed_official 155:8435094ec241 6229 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
mbed_official 155:8435094ec241 6230 #define RCC_APB1ENR_DAC1EN ((uint32_t)0x20000000) /*!< DAC clock enable */
mbed_official 155:8435094ec241 6231 #define RCC_APB1ENR_I2C3EN ((uint32_t)0x40000000) /*!< I2C 3 clock enable */
mbed_official 155:8435094ec241 6232 #define RCC_APB1ENR_DACEN RCC_APB1ENR_DAC1EN
mbed_official 155:8435094ec241 6233
mbed_official 155:8435094ec241 6234 /******************** Bit definition for RCC_BDCR register ******************/
mbed_official 155:8435094ec241 6235 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
mbed_official 155:8435094ec241 6236 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
mbed_official 155:8435094ec241 6237 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
mbed_official 155:8435094ec241 6238
mbed_official 155:8435094ec241 6239 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
mbed_official 155:8435094ec241 6240 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
mbed_official 155:8435094ec241 6241 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
mbed_official 155:8435094ec241 6242
mbed_official 155:8435094ec241 6243
mbed_official 155:8435094ec241 6244 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
mbed_official 155:8435094ec241 6245 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
mbed_official 155:8435094ec241 6246 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
mbed_official 155:8435094ec241 6247
mbed_official 155:8435094ec241 6248 /*!< RTC configuration */
mbed_official 155:8435094ec241 6249 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
mbed_official 155:8435094ec241 6250 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
mbed_official 155:8435094ec241 6251 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
mbed_official 155:8435094ec241 6252 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 32 used as RTC clock */
mbed_official 155:8435094ec241 6253
mbed_official 155:8435094ec241 6254 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
mbed_official 155:8435094ec241 6255 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
mbed_official 155:8435094ec241 6256
mbed_official 155:8435094ec241 6257 /******************** Bit definition for RCC_CSR register *******************/
mbed_official 155:8435094ec241 6258 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
mbed_official 155:8435094ec241 6259 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
mbed_official 155:8435094ec241 6260 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
mbed_official 155:8435094ec241 6261 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
mbed_official 155:8435094ec241 6262 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
mbed_official 155:8435094ec241 6263 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
mbed_official 155:8435094ec241 6264 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
mbed_official 155:8435094ec241 6265 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
mbed_official 155:8435094ec241 6266 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
mbed_official 155:8435094ec241 6267 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
mbed_official 155:8435094ec241 6268
mbed_official 155:8435094ec241 6269 /******************* Bit definition for RCC_AHBRSTR register ****************/
mbed_official 155:8435094ec241 6270 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA reset */
mbed_official 155:8435094ec241 6271 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB reset */
mbed_official 155:8435094ec241 6272 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC reset */
mbed_official 155:8435094ec241 6273 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00010000) /*!< GPIOD reset */
mbed_official 155:8435094ec241 6274 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00040000) /*!< GPIOF reset */
mbed_official 155:8435094ec241 6275 #define RCC_AHBRSTR_TSRST ((uint32_t)0x00100000) /*!< TS reset */
mbed_official 155:8435094ec241 6276 #define RCC_AHBRSTR_ADC12RST ((uint32_t)0x01000000) /*!< ADC1 & ADC2 reset */
mbed_official 155:8435094ec241 6277 #define RCC_AHBRSTR_ADC34RST ((uint32_t)0x02000000) /*!< ADC3 & ADC4 reset */
mbed_official 155:8435094ec241 6278
mbed_official 155:8435094ec241 6279 /******************* Bit definition for RCC_CFGR2 register ******************/
mbed_official 155:8435094ec241 6280 /*!< PREDIV1 configuration */
mbed_official 155:8435094ec241 6281 #define RCC_CFGR2_PREDIV1 ((uint32_t)0x0000000F) /*!< PREDIV1[3:0] bits */
mbed_official 155:8435094ec241 6282 #define RCC_CFGR2_PREDIV1_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 155:8435094ec241 6283 #define RCC_CFGR2_PREDIV1_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 155:8435094ec241 6284 #define RCC_CFGR2_PREDIV1_2 ((uint32_t)0x00000004) /*!< Bit 2 */
mbed_official 155:8435094ec241 6285 #define RCC_CFGR2_PREDIV1_3 ((uint32_t)0x00000008) /*!< Bit 3 */
mbed_official 155:8435094ec241 6286
mbed_official 155:8435094ec241 6287 #define RCC_CFGR2_PREDIV1_DIV1 ((uint32_t)0x00000000) /*!< PREDIV1 input clock not divided */
mbed_official 155:8435094ec241 6288 #define RCC_CFGR2_PREDIV1_DIV2 ((uint32_t)0x00000001) /*!< PREDIV1 input clock divided by 2 */
mbed_official 155:8435094ec241 6289 #define RCC_CFGR2_PREDIV1_DIV3 ((uint32_t)0x00000002) /*!< PREDIV1 input clock divided by 3 */
mbed_official 155:8435094ec241 6290 #define RCC_CFGR2_PREDIV1_DIV4 ((uint32_t)0x00000003) /*!< PREDIV1 input clock divided by 4 */
mbed_official 155:8435094ec241 6291 #define RCC_CFGR2_PREDIV1_DIV5 ((uint32_t)0x00000004) /*!< PREDIV1 input clock divided by 5 */
mbed_official 155:8435094ec241 6292 #define RCC_CFGR2_PREDIV1_DIV6 ((uint32_t)0x00000005) /*!< PREDIV1 input clock divided by 6 */
mbed_official 155:8435094ec241 6293 #define RCC_CFGR2_PREDIV1_DIV7 ((uint32_t)0x00000006) /*!< PREDIV1 input clock divided by 7 */
mbed_official 155:8435094ec241 6294 #define RCC_CFGR2_PREDIV1_DIV8 ((uint32_t)0x00000007) /*!< PREDIV1 input clock divided by 8 */
mbed_official 155:8435094ec241 6295 #define RCC_CFGR2_PREDIV1_DIV9 ((uint32_t)0x00000008) /*!< PREDIV1 input clock divided by 9 */
mbed_official 155:8435094ec241 6296 #define RCC_CFGR2_PREDIV1_DIV10 ((uint32_t)0x00000009) /*!< PREDIV1 input clock divided by 10 */
mbed_official 155:8435094ec241 6297 #define RCC_CFGR2_PREDIV1_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV1 input clock divided by 11 */
mbed_official 155:8435094ec241 6298 #define RCC_CFGR2_PREDIV1_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV1 input clock divided by 12 */
mbed_official 155:8435094ec241 6299 #define RCC_CFGR2_PREDIV1_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV1 input clock divided by 13 */
mbed_official 155:8435094ec241 6300 #define RCC_CFGR2_PREDIV1_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV1 input clock divided by 14 */
mbed_official 155:8435094ec241 6301 #define RCC_CFGR2_PREDIV1_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV1 input clock divided by 15 */
mbed_official 155:8435094ec241 6302 #define RCC_CFGR2_PREDIV1_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV1 input clock divided by 16 */
mbed_official 155:8435094ec241 6303
mbed_official 155:8435094ec241 6304 /*!< ADCPRE12 configuration */
mbed_official 155:8435094ec241 6305 #define RCC_CFGR2_ADCPRE12 ((uint32_t)0x000001F0) /*!< ADCPRE12[8:4] bits */
mbed_official 155:8435094ec241 6306 #define RCC_CFGR2_ADCPRE12_0 ((uint32_t)0x00000010) /*!< Bit 0 */
mbed_official 155:8435094ec241 6307 #define RCC_CFGR2_ADCPRE12_1 ((uint32_t)0x00000020) /*!< Bit 1 */
mbed_official 155:8435094ec241 6308 #define RCC_CFGR2_ADCPRE12_2 ((uint32_t)0x00000040) /*!< Bit 2 */
mbed_official 155:8435094ec241 6309 #define RCC_CFGR2_ADCPRE12_3 ((uint32_t)0x00000080) /*!< Bit 3 */
mbed_official 155:8435094ec241 6310 #define RCC_CFGR2_ADCPRE12_4 ((uint32_t)0x00000100) /*!< Bit 4 */
mbed_official 155:8435094ec241 6311
mbed_official 155:8435094ec241 6312 #define RCC_CFGR2_ADCPRE12_NO ((uint32_t)0x00000000) /*!< ADC12 clock disabled, ADC12 can use AHB clock */
mbed_official 155:8435094ec241 6313 #define RCC_CFGR2_ADCPRE12_DIV1 ((uint32_t)0x00000100) /*!< ADC12 PLL clock divided by 1 */
mbed_official 155:8435094ec241 6314 #define RCC_CFGR2_ADCPRE12_DIV2 ((uint32_t)0x00000110) /*!< ADC12 PLL clock divided by 2 */
mbed_official 155:8435094ec241 6315 #define RCC_CFGR2_ADCPRE12_DIV4 ((uint32_t)0x00000120) /*!< ADC12 PLL clock divided by 4 */
mbed_official 155:8435094ec241 6316 #define RCC_CFGR2_ADCPRE12_DIV6 ((uint32_t)0x00000130) /*!< ADC12 PLL clock divided by 6 */
mbed_official 155:8435094ec241 6317 #define RCC_CFGR2_ADCPRE12_DIV8 ((uint32_t)0x00000140) /*!< ADC12 PLL clock divided by 8 */
mbed_official 155:8435094ec241 6318 #define RCC_CFGR2_ADCPRE12_DIV10 ((uint32_t)0x00000150) /*!< ADC12 PLL clock divided by 10 */
mbed_official 155:8435094ec241 6319 #define RCC_CFGR2_ADCPRE12_DIV12 ((uint32_t)0x00000160) /*!< ADC12 PLL clock divided by 12 */
mbed_official 155:8435094ec241 6320 #define RCC_CFGR2_ADCPRE12_DIV16 ((uint32_t)0x00000170) /*!< ADC12 PLL clock divided by 16 */
mbed_official 155:8435094ec241 6321 #define RCC_CFGR2_ADCPRE12_DIV32 ((uint32_t)0x00000180) /*!< ADC12 PLL clock divided by 32 */
mbed_official 155:8435094ec241 6322 #define RCC_CFGR2_ADCPRE12_DIV64 ((uint32_t)0x00000190) /*!< ADC12 PLL clock divided by 64 */
mbed_official 155:8435094ec241 6323 #define RCC_CFGR2_ADCPRE12_DIV128 ((uint32_t)0x000001A0) /*!< ADC12 PLL clock divided by 128 */
mbed_official 155:8435094ec241 6324 #define RCC_CFGR2_ADCPRE12_DIV256 ((uint32_t)0x000001B0) /*!< ADC12 PLL clock divided by 256 */
mbed_official 155:8435094ec241 6325
mbed_official 155:8435094ec241 6326 /*!< ADCPRE34 configuration */
mbed_official 155:8435094ec241 6327 #define RCC_CFGR2_ADCPRE34 ((uint32_t)0x00003E00) /*!< ADCPRE34[13:5] bits */
mbed_official 155:8435094ec241 6328 #define RCC_CFGR2_ADCPRE34_0 ((uint32_t)0x00000200) /*!< Bit 0 */
mbed_official 155:8435094ec241 6329 #define RCC_CFGR2_ADCPRE34_1 ((uint32_t)0x00000400) /*!< Bit 1 */
mbed_official 155:8435094ec241 6330 #define RCC_CFGR2_ADCPRE34_2 ((uint32_t)0x00000800) /*!< Bit 2 */
mbed_official 155:8435094ec241 6331 #define RCC_CFGR2_ADCPRE34_3 ((uint32_t)0x00001000) /*!< Bit 3 */
mbed_official 155:8435094ec241 6332 #define RCC_CFGR2_ADCPRE34_4 ((uint32_t)0x00002000) /*!< Bit 4 */
mbed_official 155:8435094ec241 6333
mbed_official 155:8435094ec241 6334 #define RCC_CFGR2_ADCPRE34_NO ((uint32_t)0x00000000) /*!< ADC34 clock disabled, ADC34 can use AHB clock */
mbed_official 155:8435094ec241 6335 #define RCC_CFGR2_ADCPRE34_DIV1 ((uint32_t)0x00002000) /*!< ADC34 PLL clock divided by 1 */
mbed_official 155:8435094ec241 6336 #define RCC_CFGR2_ADCPRE34_DIV2 ((uint32_t)0x00002200) /*!< ADC34 PLL clock divided by 2 */
mbed_official 155:8435094ec241 6337 #define RCC_CFGR2_ADCPRE34_DIV4 ((uint32_t)0x00002400) /*!< ADC34 PLL clock divided by 4 */
mbed_official 155:8435094ec241 6338 #define RCC_CFGR2_ADCPRE34_DIV6 ((uint32_t)0x00002600) /*!< ADC34 PLL clock divided by 6 */
mbed_official 155:8435094ec241 6339 #define RCC_CFGR2_ADCPRE34_DIV8 ((uint32_t)0x00002800) /*!< ADC34 PLL clock divided by 8 */
mbed_official 155:8435094ec241 6340 #define RCC_CFGR2_ADCPRE34_DIV10 ((uint32_t)0x00002A00) /*!< ADC34 PLL clock divided by 10 */
mbed_official 155:8435094ec241 6341 #define RCC_CFGR2_ADCPRE34_DIV12 ((uint32_t)0x00002C00) /*!< ADC34 PLL clock divided by 12 */
mbed_official 155:8435094ec241 6342 #define RCC_CFGR2_ADCPRE34_DIV16 ((uint32_t)0x00002E00) /*!< ADC34 PLL clock divided by 16 */
mbed_official 155:8435094ec241 6343 #define RCC_CFGR2_ADCPRE34_DIV32 ((uint32_t)0x00003000) /*!< ADC34 PLL clock divided by 32 */
mbed_official 155:8435094ec241 6344 #define RCC_CFGR2_ADCPRE34_DIV64 ((uint32_t)0x00003200) /*!< ADC34 PLL clock divided by 64 */
mbed_official 155:8435094ec241 6345 #define RCC_CFGR2_ADCPRE34_DIV128 ((uint32_t)0x00003400) /*!< ADC34 PLL clock divided by 128 */
mbed_official 155:8435094ec241 6346 #define RCC_CFGR2_ADCPRE34_DIV256 ((uint32_t)0x00003600) /*!< ADC34 PLL clock divided by 256 */
mbed_official 155:8435094ec241 6347
mbed_official 155:8435094ec241 6348 /******************* Bit definition for RCC_CFGR3 register ******************/
mbed_official 155:8435094ec241 6349 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
mbed_official 155:8435094ec241 6350 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 155:8435094ec241 6351 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 155:8435094ec241 6352
mbed_official 155:8435094ec241 6353 #define RCC_CFGR3_I2CSW ((uint32_t)0x00000070) /*!< I2CSW bits */
mbed_official 155:8435094ec241 6354 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
mbed_official 155:8435094ec241 6355 #define RCC_CFGR3_I2C2SW ((uint32_t)0x00000020) /*!< I2C2SW bits */
mbed_official 155:8435094ec241 6356 #define RCC_CFGR3_I2C3SW ((uint32_t)0x00000040) /*!< I2C3SW bits */
mbed_official 155:8435094ec241 6357
mbed_official 155:8435094ec241 6358 #define RCC_CFGR3_TIMSW ((uint32_t)0x00002F00) /*!< TIMSW bits */
mbed_official 155:8435094ec241 6359 #define RCC_CFGR3_TIM1SW ((uint32_t)0x00000100) /*!< TIM1SW bits */
mbed_official 155:8435094ec241 6360 #define RCC_CFGR3_TIM8SW ((uint32_t)0x00000200) /*!< TIM8SW bits */
mbed_official 155:8435094ec241 6361 #define RCC_CFGR3_TIM15SW ((uint32_t)0x00000400) /*!< TIM15SW bits */
mbed_official 155:8435094ec241 6362 #define RCC_CFGR3_TIM16SW ((uint32_t)0x00000800) /*!< TIM16SW bits */
mbed_official 155:8435094ec241 6363 #define RCC_CFGR3_TIM17SW ((uint32_t)0x00002000) /*!< TIM17SW bits */
mbed_official 155:8435094ec241 6364
mbed_official 155:8435094ec241 6365 #define RCC_CFGR3_HRTIM1SW ((uint32_t)0x00001000) /*!< HRTIM1SW bits */
mbed_official 155:8435094ec241 6366
mbed_official 155:8435094ec241 6367 #define RCC_CFGR3_USART2SW ((uint32_t)0x00030000) /*!< USART2SW[1:0] bits */
mbed_official 155:8435094ec241 6368 #define RCC_CFGR3_USART2SW_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 155:8435094ec241 6369 #define RCC_CFGR3_USART2SW_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6370
mbed_official 155:8435094ec241 6371 #define RCC_CFGR3_USART3SW ((uint32_t)0x000C0000) /*!< USART3SW[1:0] bits */
mbed_official 155:8435094ec241 6372 #define RCC_CFGR3_USART3SW_0 ((uint32_t)0x00040000) /*!< Bit 0 */
mbed_official 155:8435094ec241 6373 #define RCC_CFGR3_USART3SW_1 ((uint32_t)0x00080000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6374
mbed_official 155:8435094ec241 6375 #define RCC_CFGR3_UART4SW ((uint32_t)0x00300000) /*!< UART4SW[1:0] bits */
mbed_official 155:8435094ec241 6376 #define RCC_CFGR3_UART4SW_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 155:8435094ec241 6377 #define RCC_CFGR3_UART4SW_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6378
mbed_official 155:8435094ec241 6379 #define RCC_CFGR3_UART5SW ((uint32_t)0x00C00000) /*!< UART5SW[1:0] bits */
mbed_official 155:8435094ec241 6380 #define RCC_CFGR3_UART5SW_0 ((uint32_t)0x00400000) /*!< Bit 0 */
mbed_official 155:8435094ec241 6381 #define RCC_CFGR3_UART5SW_1 ((uint32_t)0x00800000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6382
mbed_official 155:8435094ec241 6383 /******************************************************************************/
mbed_official 155:8435094ec241 6384 /* */
mbed_official 155:8435094ec241 6385 /* Real-Time Clock (RTC) */
mbed_official 155:8435094ec241 6386 /* */
mbed_official 155:8435094ec241 6387 /******************************************************************************/
mbed_official 155:8435094ec241 6388 /******************** Bits definition for RTC_TR register *******************/
mbed_official 155:8435094ec241 6389 #define RTC_TR_PM ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 6390 #define RTC_TR_HT ((uint32_t)0x00300000)
mbed_official 155:8435094ec241 6391 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 6392 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 6393 #define RTC_TR_HU ((uint32_t)0x000F0000)
mbed_official 155:8435094ec241 6394 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 6395 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 6396 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 6397 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 6398 #define RTC_TR_MNT ((uint32_t)0x00007000)
mbed_official 155:8435094ec241 6399 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6400 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6401 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6402 #define RTC_TR_MNU ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 6403 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6404 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6405 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6406 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6407 #define RTC_TR_ST ((uint32_t)0x00000070)
mbed_official 155:8435094ec241 6408 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6409 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6410 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6411 #define RTC_TR_SU ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 6412 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6413 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6414 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6415 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6416
mbed_official 155:8435094ec241 6417 /******************** Bits definition for RTC_DR register *******************/
mbed_official 155:8435094ec241 6418 #define RTC_DR_YT ((uint32_t)0x00F00000)
mbed_official 155:8435094ec241 6419 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 6420 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 6421 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 6422 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 6423 #define RTC_DR_YU ((uint32_t)0x000F0000)
mbed_official 155:8435094ec241 6424 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 6425 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 6426 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 6427 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 6428 #define RTC_DR_WDU ((uint32_t)0x0000E000)
mbed_official 155:8435094ec241 6429 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6430 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6431 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6432 #define RTC_DR_MT ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6433 #define RTC_DR_MU ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 6434 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6435 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6436 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6437 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6438 #define RTC_DR_DT ((uint32_t)0x00000030)
mbed_official 155:8435094ec241 6439 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6440 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6441 #define RTC_DR_DU ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 6442 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6443 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6444 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6445 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6446
mbed_official 155:8435094ec241 6447 /******************** Bits definition for RTC_CR register *******************/
mbed_official 155:8435094ec241 6448 #define RTC_CR_COE ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 6449 #define RTC_CR_OSEL ((uint32_t)0x00600000)
mbed_official 155:8435094ec241 6450 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 6451 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 6452 #define RTC_CR_POL ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 6453 #define RTC_CR_COSEL ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 6454 #define RTC_CR_BCK ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 6455 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 6456 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 6457 #define RTC_CR_TSIE ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6458 #define RTC_CR_WUTIE ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6459 #define RTC_CR_ALRBIE ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6460 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6461 #define RTC_CR_TSE ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6462 #define RTC_CR_WUTE ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6463 #define RTC_CR_ALRBE ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6464 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6465 #define RTC_CR_FMT ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6466 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6467 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6468 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6469 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007)
mbed_official 155:8435094ec241 6470 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6471 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6472 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6473
mbed_official 155:8435094ec241 6474 /******************** Bits definition for RTC_ISR register ******************/
mbed_official 155:8435094ec241 6475 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 6476 #define RTC_ISR_TAMP3F ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6477 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6478 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6479 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6480 #define RTC_ISR_TSF ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6481 #define RTC_ISR_WUTF ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6482 #define RTC_ISR_ALRBF ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6483 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6484 #define RTC_ISR_INIT ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 6485 #define RTC_ISR_INITF ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6486 #define RTC_ISR_RSF ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6487 #define RTC_ISR_INITS ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6488 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6489 #define RTC_ISR_WUTWF ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6490 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6491 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6492
mbed_official 155:8435094ec241 6493 /******************** Bits definition for RTC_PRER register *****************/
mbed_official 155:8435094ec241 6494 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
mbed_official 155:8435094ec241 6495 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
mbed_official 155:8435094ec241 6496
mbed_official 155:8435094ec241 6497 /******************** Bits definition for RTC_WUTR register *****************/
mbed_official 155:8435094ec241 6498 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFF)
mbed_official 155:8435094ec241 6499
mbed_official 155:8435094ec241 6500 /******************** Bits definition for RTC_ALRMAR register ***************/
mbed_official 155:8435094ec241 6501 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
mbed_official 155:8435094ec241 6502 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
mbed_official 155:8435094ec241 6503 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
mbed_official 155:8435094ec241 6504 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
mbed_official 155:8435094ec241 6505 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
mbed_official 155:8435094ec241 6506 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
mbed_official 155:8435094ec241 6507 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 6508 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 6509 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 6510 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 6511 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 6512 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 6513 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
mbed_official 155:8435094ec241 6514 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 6515 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 6516 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
mbed_official 155:8435094ec241 6517 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 6518 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 6519 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 6520 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 6521 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6522 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
mbed_official 155:8435094ec241 6523 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6524 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6525 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6526 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 6527 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6528 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6529 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6530 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6531 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 6532 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
mbed_official 155:8435094ec241 6533 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6534 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6535 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6536 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 6537 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6538 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6539 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6540 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6541
mbed_official 155:8435094ec241 6542 /******************** Bits definition for RTC_ALRMBR register ***************/
mbed_official 155:8435094ec241 6543 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000)
mbed_official 155:8435094ec241 6544 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000)
mbed_official 155:8435094ec241 6545 #define RTC_ALRMBR_DT ((uint32_t)0x30000000)
mbed_official 155:8435094ec241 6546 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000)
mbed_official 155:8435094ec241 6547 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000)
mbed_official 155:8435094ec241 6548 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000)
mbed_official 155:8435094ec241 6549 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 6550 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 6551 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 6552 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 6553 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000)
mbed_official 155:8435094ec241 6554 #define RTC_ALRMBR_PM ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 6555 #define RTC_ALRMBR_HT ((uint32_t)0x00300000)
mbed_official 155:8435094ec241 6556 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 6557 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 6558 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000)
mbed_official 155:8435094ec241 6559 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 6560 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 6561 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 6562 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 6563 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6564 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000)
mbed_official 155:8435094ec241 6565 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6566 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6567 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6568 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 6569 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6570 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6571 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6572 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6573 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 6574 #define RTC_ALRMBR_ST ((uint32_t)0x00000070)
mbed_official 155:8435094ec241 6575 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6576 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6577 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6578 #define RTC_ALRMBR_SU ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 6579 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6580 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6581 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6582 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6583
mbed_official 155:8435094ec241 6584 /******************** Bits definition for RTC_WPR register ******************/
mbed_official 155:8435094ec241 6585 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
mbed_official 155:8435094ec241 6586
mbed_official 155:8435094ec241 6587 /******************** Bits definition for RTC_SSR register ******************/
mbed_official 155:8435094ec241 6588 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
mbed_official 155:8435094ec241 6589
mbed_official 155:8435094ec241 6590 /******************** Bits definition for RTC_SHIFTR register ***************/
mbed_official 155:8435094ec241 6591 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
mbed_official 155:8435094ec241 6592 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
mbed_official 155:8435094ec241 6593
mbed_official 155:8435094ec241 6594 /******************** Bits definition for RTC_TSTR register *****************/
mbed_official 155:8435094ec241 6595 #define RTC_TSTR_PM ((uint32_t)0x00400000)
mbed_official 155:8435094ec241 6596 #define RTC_TSTR_HT ((uint32_t)0x00300000)
mbed_official 155:8435094ec241 6597 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
mbed_official 155:8435094ec241 6598 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
mbed_official 155:8435094ec241 6599 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
mbed_official 155:8435094ec241 6600 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
mbed_official 155:8435094ec241 6601 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
mbed_official 155:8435094ec241 6602 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 6603 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
mbed_official 155:8435094ec241 6604 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
mbed_official 155:8435094ec241 6605 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6606 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6607 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6608 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 6609 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6610 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6611 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6612 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6613 #define RTC_TSTR_ST ((uint32_t)0x00000070)
mbed_official 155:8435094ec241 6614 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6615 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6616 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6617 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 6618 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6619 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6620 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6621 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6622
mbed_official 155:8435094ec241 6623 /******************** Bits definition for RTC_TSDR register *****************/
mbed_official 155:8435094ec241 6624 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
mbed_official 155:8435094ec241 6625 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6626 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6627 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6628 #define RTC_TSDR_MT ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6629 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
mbed_official 155:8435094ec241 6630 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6631 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6632 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6633 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6634 #define RTC_TSDR_DT ((uint32_t)0x00000030)
mbed_official 155:8435094ec241 6635 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6636 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6637 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
mbed_official 155:8435094ec241 6638 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6639 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6640 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6641 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6642
mbed_official 155:8435094ec241 6643 /******************** Bits definition for RTC_TSSSR register ****************/
mbed_official 155:8435094ec241 6644 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
mbed_official 155:8435094ec241 6645
mbed_official 155:8435094ec241 6646 /******************** Bits definition for RTC_CAL register *****************/
mbed_official 155:8435094ec241 6647 #define RTC_CALR_CALP ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6648 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6649 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6650 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
mbed_official 155:8435094ec241 6651 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6652 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6653 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6654 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6655 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6656 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6657 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6658 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 6659 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6660
mbed_official 155:8435094ec241 6661 /******************** Bits definition for RTC_TAFCR register ****************/
mbed_official 155:8435094ec241 6662 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
mbed_official 155:8435094ec241 6663 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
mbed_official 155:8435094ec241 6664 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
mbed_official 155:8435094ec241 6665 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
mbed_official 155:8435094ec241 6666 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
mbed_official 155:8435094ec241 6667 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
mbed_official 155:8435094ec241 6668 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
mbed_official 155:8435094ec241 6669 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
mbed_official 155:8435094ec241 6670 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
mbed_official 155:8435094ec241 6671 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
mbed_official 155:8435094ec241 6672 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
mbed_official 155:8435094ec241 6673 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
mbed_official 155:8435094ec241 6674 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
mbed_official 155:8435094ec241 6675 #define RTC_TAFCR_TAMP3TRG ((uint32_t)0x00000040)
mbed_official 155:8435094ec241 6676 #define RTC_TAFCR_TAMP3E ((uint32_t)0x00000020)
mbed_official 155:8435094ec241 6677 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
mbed_official 155:8435094ec241 6678 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
mbed_official 155:8435094ec241 6679 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
mbed_official 155:8435094ec241 6680 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
mbed_official 155:8435094ec241 6681 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
mbed_official 155:8435094ec241 6682
mbed_official 155:8435094ec241 6683 /******************** Bits definition for RTC_ALRMASSR register *************/
mbed_official 155:8435094ec241 6684 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 155:8435094ec241 6685 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 6686 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 6687 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 6688 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 6689 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
mbed_official 155:8435094ec241 6690
mbed_official 155:8435094ec241 6691 /******************** Bits definition for RTC_ALRMBSSR register *************/
mbed_official 155:8435094ec241 6692 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000)
mbed_official 155:8435094ec241 6693 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000)
mbed_official 155:8435094ec241 6694 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000)
mbed_official 155:8435094ec241 6695 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000)
mbed_official 155:8435094ec241 6696 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000)
mbed_official 155:8435094ec241 6697 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFF)
mbed_official 155:8435094ec241 6698
mbed_official 155:8435094ec241 6699 /******************** Bits definition for RTC_BKP0R register ****************/
mbed_official 155:8435094ec241 6700 #define RTC_BKP0R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6701
mbed_official 155:8435094ec241 6702 /******************** Bits definition for RTC_BKP1R register ****************/
mbed_official 155:8435094ec241 6703 #define RTC_BKP1R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6704
mbed_official 155:8435094ec241 6705 /******************** Bits definition for RTC_BKP2R register ****************/
mbed_official 155:8435094ec241 6706 #define RTC_BKP2R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6707
mbed_official 155:8435094ec241 6708 /******************** Bits definition for RTC_BKP3R register ****************/
mbed_official 155:8435094ec241 6709 #define RTC_BKP3R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6710
mbed_official 155:8435094ec241 6711 /******************** Bits definition for RTC_BKP4R register ****************/
mbed_official 155:8435094ec241 6712 #define RTC_BKP4R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6713
mbed_official 155:8435094ec241 6714 /******************** Bits definition for RTC_BKP5R register ****************/
mbed_official 155:8435094ec241 6715 #define RTC_BKP5R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6716
mbed_official 155:8435094ec241 6717 /******************** Bits definition for RTC_BKP6R register ****************/
mbed_official 155:8435094ec241 6718 #define RTC_BKP6R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6719
mbed_official 155:8435094ec241 6720 /******************** Bits definition for RTC_BKP7R register ****************/
mbed_official 155:8435094ec241 6721 #define RTC_BKP7R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6722
mbed_official 155:8435094ec241 6723 /******************** Bits definition for RTC_BKP8R register ****************/
mbed_official 155:8435094ec241 6724 #define RTC_BKP8R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6725
mbed_official 155:8435094ec241 6726 /******************** Bits definition for RTC_BKP9R register ****************/
mbed_official 155:8435094ec241 6727 #define RTC_BKP9R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6728
mbed_official 155:8435094ec241 6729 /******************** Bits definition for RTC_BKP10R register ***************/
mbed_official 155:8435094ec241 6730 #define RTC_BKP10R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6731
mbed_official 155:8435094ec241 6732 /******************** Bits definition for RTC_BKP11R register ***************/
mbed_official 155:8435094ec241 6733 #define RTC_BKP11R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6734
mbed_official 155:8435094ec241 6735 /******************** Bits definition for RTC_BKP12R register ***************/
mbed_official 155:8435094ec241 6736 #define RTC_BKP12R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6737
mbed_official 155:8435094ec241 6738 /******************** Bits definition for RTC_BKP13R register ***************/
mbed_official 155:8435094ec241 6739 #define RTC_BKP13R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6740
mbed_official 155:8435094ec241 6741 /******************** Bits definition for RTC_BKP14R register ***************/
mbed_official 155:8435094ec241 6742 #define RTC_BKP14R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6743
mbed_official 155:8435094ec241 6744 /******************** Bits definition for RTC_BKP15R register ***************/
mbed_official 155:8435094ec241 6745 #define RTC_BKP15R ((uint32_t)0xFFFFFFFF)
mbed_official 155:8435094ec241 6746
mbed_official 155:8435094ec241 6747 /******************************************************************************/
mbed_official 155:8435094ec241 6748 /* */
mbed_official 155:8435094ec241 6749 /* Serial Peripheral Interface (SPI) */
mbed_official 155:8435094ec241 6750 /* */
mbed_official 155:8435094ec241 6751 /******************************************************************************/
mbed_official 155:8435094ec241 6752 /******************* Bit definition for SPI_CR1 register ********************/
mbed_official 155:8435094ec241 6753 #define SPI_CR1_CPHA ((uint16_t)0x0001) /*!< Clock Phase */
mbed_official 155:8435094ec241 6754 #define SPI_CR1_CPOL ((uint16_t)0x0002) /*!< Clock Polarity */
mbed_official 155:8435094ec241 6755 #define SPI_CR1_MSTR ((uint16_t)0x0004) /*!< Master Selection */
mbed_official 155:8435094ec241 6756
mbed_official 155:8435094ec241 6757 #define SPI_CR1_BR ((uint16_t)0x0038) /*!< BR[2:0] bits (Baud Rate Control) */
mbed_official 155:8435094ec241 6758 #define SPI_CR1_BR_0 ((uint16_t)0x0008) /*!< Bit 0 */
mbed_official 155:8435094ec241 6759 #define SPI_CR1_BR_1 ((uint16_t)0x0010) /*!< Bit 1 */
mbed_official 155:8435094ec241 6760 #define SPI_CR1_BR_2 ((uint16_t)0x0020) /*!< Bit 2 */
mbed_official 155:8435094ec241 6761
mbed_official 155:8435094ec241 6762 #define SPI_CR1_SPE ((uint16_t)0x0040) /*!< SPI Enable */
mbed_official 155:8435094ec241 6763 #define SPI_CR1_LSBFIRST ((uint16_t)0x0080) /*!< Frame Format */
mbed_official 155:8435094ec241 6764 #define SPI_CR1_SSI ((uint16_t)0x0100) /*!< Internal slave select */
mbed_official 155:8435094ec241 6765 #define SPI_CR1_SSM ((uint16_t)0x0200) /*!< Software slave management */
mbed_official 155:8435094ec241 6766 #define SPI_CR1_RXONLY ((uint16_t)0x0400) /*!< Receive only */
mbed_official 155:8435094ec241 6767 #define SPI_CR1_CRCL ((uint16_t)0x0800) /*!< CRC Length */
mbed_official 155:8435094ec241 6768 #define SPI_CR1_CRCNEXT ((uint16_t)0x1000) /*!< Transmit CRC next */
mbed_official 155:8435094ec241 6769 #define SPI_CR1_CRCEN ((uint16_t)0x2000) /*!< Hardware CRC calculation enable */
mbed_official 155:8435094ec241 6770 #define SPI_CR1_BIDIOE ((uint16_t)0x4000) /*!< Output enable in bidirectional mode */
mbed_official 155:8435094ec241 6771 #define SPI_CR1_BIDIMODE ((uint16_t)0x8000) /*!< Bidirectional data mode enable */
mbed_official 155:8435094ec241 6772
mbed_official 155:8435094ec241 6773 /******************* Bit definition for SPI_CR2 register ********************/
mbed_official 155:8435094ec241 6774 #define SPI_CR2_RXDMAEN ((uint16_t)0x0001) /*!< Rx Buffer DMA Enable */
mbed_official 155:8435094ec241 6775 #define SPI_CR2_TXDMAEN ((uint16_t)0x0002) /*!< Tx Buffer DMA Enable */
mbed_official 155:8435094ec241 6776 #define SPI_CR2_SSOE ((uint16_t)0x0004) /*!< SS Output Enable */
mbed_official 155:8435094ec241 6777 #define SPI_CR2_NSSP ((uint16_t)0x0008) /*!< NSS pulse management Enable */
mbed_official 155:8435094ec241 6778 #define SPI_CR2_FRF ((uint16_t)0x0010) /*!< Frame Format Enable */
mbed_official 155:8435094ec241 6779 #define SPI_CR2_ERRIE ((uint16_t)0x0020) /*!< Error Interrupt Enable */
mbed_official 155:8435094ec241 6780 #define SPI_CR2_RXNEIE ((uint16_t)0x0040) /*!< RX buffer Not Empty Interrupt Enable */
mbed_official 155:8435094ec241 6781 #define SPI_CR2_TXEIE ((uint16_t)0x0080) /*!< Tx buffer Empty Interrupt Enable */
mbed_official 155:8435094ec241 6782
mbed_official 155:8435094ec241 6783 #define SPI_CR2_DS ((uint16_t)0x0F00) /*!< DS[3:0] Data Size */
mbed_official 155:8435094ec241 6784 #define SPI_CR2_DS_0 ((uint16_t)0x0100) /*!< Bit 0 */
mbed_official 155:8435094ec241 6785 #define SPI_CR2_DS_1 ((uint16_t)0x0200) /*!< Bit 1 */
mbed_official 155:8435094ec241 6786 #define SPI_CR2_DS_2 ((uint16_t)0x0400) /*!< Bit 2 */
mbed_official 155:8435094ec241 6787 #define SPI_CR2_DS_3 ((uint16_t)0x0800) /*!< Bit 3 */
mbed_official 155:8435094ec241 6788
mbed_official 155:8435094ec241 6789 #define SPI_CR2_FRXTH ((uint16_t)0x1000) /*!< FIFO reception Threshold */
mbed_official 155:8435094ec241 6790 #define SPI_CR2_LDMARX ((uint16_t)0x2000) /*!< Last DMA transfer for reception */
mbed_official 155:8435094ec241 6791 #define SPI_CR2_LDMATX ((uint16_t)0x4000) /*!< Last DMA transfer for transmission */
mbed_official 155:8435094ec241 6792
mbed_official 155:8435094ec241 6793 /******************** Bit definition for SPI_SR register ********************/
mbed_official 155:8435094ec241 6794 #define SPI_SR_RXNE ((uint16_t)0x0001) /*!< Receive buffer Not Empty */
mbed_official 155:8435094ec241 6795 #define SPI_SR_TXE ((uint16_t)0x0002) /*!< Transmit buffer Empty */
mbed_official 155:8435094ec241 6796 #define SPI_SR_CRCERR ((uint16_t)0x0010) /*!< CRC Error flag */
mbed_official 155:8435094ec241 6797 #define SPI_SR_MODF ((uint16_t)0x0020) /*!< Mode fault */
mbed_official 155:8435094ec241 6798 #define SPI_SR_OVR ((uint16_t)0x0040) /*!< Overrun flag */
mbed_official 155:8435094ec241 6799 #define SPI_SR_BSY ((uint16_t)0x0080) /*!< Busy flag */
mbed_official 155:8435094ec241 6800 #define SPI_SR_FRE ((uint16_t)0x0100) /*!< TI frame format error */
mbed_official 155:8435094ec241 6801 #define SPI_SR_FRLVL ((uint16_t)0x0600) /*!< FIFO Reception Level */
mbed_official 155:8435094ec241 6802 #define SPI_SR_FRLVL_0 ((uint16_t)0x0200) /*!< Bit 0 */
mbed_official 155:8435094ec241 6803 #define SPI_SR_FRLVL_1 ((uint16_t)0x0400) /*!< Bit 1 */
mbed_official 155:8435094ec241 6804 #define SPI_SR_FTLVL ((uint16_t)0x1800) /*!< FIFO Transmission Level */
mbed_official 155:8435094ec241 6805 #define SPI_SR_FTLVL_0 ((uint16_t)0x0800) /*!< Bit 0 */
mbed_official 155:8435094ec241 6806 #define SPI_SR_FTLVL_1 ((uint16_t)0x1000) /*!< Bit 1 */
mbed_official 155:8435094ec241 6807
mbed_official 155:8435094ec241 6808 /******************** Bit definition for SPI_DR register ********************/
mbed_official 155:8435094ec241 6809 #define SPI_DR_DR ((uint16_t)0xFFFF) /*!< Data Register */
mbed_official 155:8435094ec241 6810
mbed_official 155:8435094ec241 6811 /******************* Bit definition for SPI_CRCPR register ******************/
mbed_official 155:8435094ec241 6812 #define SPI_CRCPR_CRCPOLY ((uint16_t)0xFFFF) /*!< CRC polynomial register */
mbed_official 155:8435094ec241 6813
mbed_official 155:8435094ec241 6814 /****************** Bit definition for SPI_RXCRCR register ******************/
mbed_official 155:8435094ec241 6815 #define SPI_RXCRCR_RXCRC ((uint16_t)0xFFFF) /*!< Rx CRC Register */
mbed_official 155:8435094ec241 6816
mbed_official 155:8435094ec241 6817 /****************** Bit definition for SPI_TXCRCR register ******************/
mbed_official 155:8435094ec241 6818 #define SPI_TXCRCR_TXCRC ((uint16_t)0xFFFF) /*!< Tx CRC Register */
mbed_official 155:8435094ec241 6819
mbed_official 155:8435094ec241 6820 /****************** Bit definition for SPI_I2SCFGR register *****************/
mbed_official 155:8435094ec241 6821 #define SPI_I2SCFGR_CHLEN ((uint16_t)0x0001) /*!<Channel length (number of bits per audio channel) */
mbed_official 155:8435094ec241 6822
mbed_official 155:8435094ec241 6823 #define SPI_I2SCFGR_DATLEN ((uint16_t)0x0006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
mbed_official 155:8435094ec241 6824 #define SPI_I2SCFGR_DATLEN_0 ((uint16_t)0x0002) /*!<Bit 0 */
mbed_official 155:8435094ec241 6825 #define SPI_I2SCFGR_DATLEN_1 ((uint16_t)0x0004) /*!<Bit 1 */
mbed_official 155:8435094ec241 6826
mbed_official 155:8435094ec241 6827 #define SPI_I2SCFGR_CKPOL ((uint16_t)0x0008) /*!<steady state clock polarity */
mbed_official 155:8435094ec241 6828
mbed_official 155:8435094ec241 6829 #define SPI_I2SCFGR_I2SSTD ((uint16_t)0x0030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
mbed_official 155:8435094ec241 6830 #define SPI_I2SCFGR_I2SSTD_0 ((uint16_t)0x0010) /*!<Bit 0 */
mbed_official 155:8435094ec241 6831 #define SPI_I2SCFGR_I2SSTD_1 ((uint16_t)0x0020) /*!<Bit 1 */
mbed_official 155:8435094ec241 6832
mbed_official 155:8435094ec241 6833 #define SPI_I2SCFGR_PCMSYNC ((uint16_t)0x0080) /*!<PCM frame synchronization */
mbed_official 155:8435094ec241 6834
mbed_official 155:8435094ec241 6835 #define SPI_I2SCFGR_I2SCFG ((uint16_t)0x0300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
mbed_official 155:8435094ec241 6836 #define SPI_I2SCFGR_I2SCFG_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 155:8435094ec241 6837 #define SPI_I2SCFGR_I2SCFG_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 155:8435094ec241 6838
mbed_official 155:8435094ec241 6839 #define SPI_I2SCFGR_I2SE ((uint16_t)0x0400) /*!<I2S Enable */
mbed_official 155:8435094ec241 6840 #define SPI_I2SCFGR_I2SMOD ((uint16_t)0x0800) /*!<I2S mode selection */
mbed_official 155:8435094ec241 6841
mbed_official 155:8435094ec241 6842 /****************** Bit definition for SPI_I2SPR register *******************/
mbed_official 155:8435094ec241 6843 #define SPI_I2SPR_I2SDIV ((uint16_t)0x00FF) /*!<I2S Linear prescaler */
mbed_official 155:8435094ec241 6844 #define SPI_I2SPR_ODD ((uint16_t)0x0100) /*!<Odd factor for the prescaler */
mbed_official 155:8435094ec241 6845 #define SPI_I2SPR_MCKOE ((uint16_t)0x0200) /*!<Master Clock Output Enable */
mbed_official 155:8435094ec241 6846
mbed_official 155:8435094ec241 6847 /******************************************************************************/
mbed_official 155:8435094ec241 6848 /* */
mbed_official 155:8435094ec241 6849 /* System Configuration(SYSCFG) */
mbed_official 155:8435094ec241 6850 /* */
mbed_official 155:8435094ec241 6851 /******************************************************************************/
mbed_official 155:8435094ec241 6852 /***************** Bit definition for SYSCFG_CFGR1 register *****************/
mbed_official 155:8435094ec241 6853 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
mbed_official 155:8435094ec241 6854 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< Bit 0 */
mbed_official 155:8435094ec241 6855 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< Bit 1 */
mbed_official 155:8435094ec241 6856 #define SYSCFG_CFGR1_USB_IT_RMP ((uint32_t)0x00000020) /*!< USB interrupt remap */
mbed_official 155:8435094ec241 6857 #define SYSCFG_CFGR1_TIM1_ITR3_RMP ((uint32_t)0x00000040) /*!< Timer 1 ITR3 selection */
mbed_official 155:8435094ec241 6858 #define SYSCFG_CFGR1_DAC1_TRIG1_RMP ((uint32_t)0x00000080) /*!< DAC1 Trigger1 remap */
mbed_official 155:8435094ec241 6859 #define SYSCFG_CFGR1_ADC24_DMA_RMP ((uint32_t)0x00000100) /*!< ADC2 and ADC4 DMA remap */
mbed_official 155:8435094ec241 6860 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
mbed_official 155:8435094ec241 6861 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
mbed_official 155:8435094ec241 6862 #define SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP ((uint32_t)0x00002000) /*!< Timer 6 / DAC1 CH1 DMA remap */
mbed_official 155:8435094ec241 6863 #define SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP ((uint32_t)0x00004000) /*!< Timer 7 / DAC1 CH2 DMA remap */
mbed_official 155:8435094ec241 6864 #define SYSCFG_CFGR1_DAC2Ch1_DMA_RMP ((uint32_t)0x00008000) /*!< DAC2 CH1 DMA remap */
mbed_official 155:8435094ec241 6865 #define SYSCFG_CFGR1_I2C_PB6_FMP ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
mbed_official 155:8435094ec241 6866 #define SYSCFG_CFGR1_I2C_PB7_FMP ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
mbed_official 155:8435094ec241 6867 #define SYSCFG_CFGR1_I2C_PB8_FMP ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
mbed_official 155:8435094ec241 6868 #define SYSCFG_CFGR1_I2C_PB9_FMP ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
mbed_official 155:8435094ec241 6869 #define SYSCFG_CFGR1_I2C1_FMP ((uint32_t)0x00100000) /*!< I2C1 Fast mode plus */
mbed_official 155:8435094ec241 6870 #define SYSCFG_CFGR1_I2C2_FMP ((uint32_t)0x00200000) /*!< I2C2 Fast mode plus */
mbed_official 155:8435094ec241 6871 #define SYSCFG_CFGR1_ENCODER_MODE ((uint32_t)0x00C00000) /*!< Encoder Mode */
mbed_official 155:8435094ec241 6872 #define SYSCFG_CFGR1_ENCODER_MODE_0 ((uint32_t)0x00400000) /*!< Encoder Mode 0 */
mbed_official 155:8435094ec241 6873 #define SYSCFG_CFGR1_ENCODER_MODE_1 ((uint32_t)0x00800000) /*!< Encoder Mode 1 */
mbed_official 155:8435094ec241 6874 #define SYSCFG_CFGR1_FPU_IE ((uint32_t)0xFC000000) /*!< Floating Point Unit Interrupt Enable */
mbed_official 155:8435094ec241 6875 #define SYSCFG_CFGR1_FPU_IE_0 ((uint32_t)0x04000000) /*!< Floating Point Unit Interrupt Enable 0 */
mbed_official 155:8435094ec241 6876 #define SYSCFG_CFGR1_FPU_IE_1 ((uint32_t)0x08000000) /*!< Floating Point Unit Interrupt Enable 1 */
mbed_official 155:8435094ec241 6877 #define SYSCFG_CFGR1_FPU_IE_2 ((uint32_t)0x10000000) /*!< Floating Point Unit Interrupt Enable 2 */
mbed_official 155:8435094ec241 6878 #define SYSCFG_CFGR1_FPU_IE_3 ((uint32_t)0x20000000) /*!< Floating Point Unit Interrupt Enable 3 */
mbed_official 155:8435094ec241 6879 #define SYSCFG_CFGR1_FPU_IE_4 ((uint32_t)0x40000000) /*!< Floating Point Unit Interrupt Enable 4 */
mbed_official 155:8435094ec241 6880 #define SYSCFG_CFGR1_FPU_IE_5 ((uint32_t)0x80000000) /*!< Floating Point Unit Interrupt Enable 5 */
mbed_official 155:8435094ec241 6881 #define SYSCFG_CFGR1_DAC_TRIG_RMP SYSCFG_CFGR1_DAC1_TRIG1_RMP /*!< Old define maintained for legacy purpose */
mbed_official 155:8435094ec241 6882 #define SYSCFG_CFGR1_TIM6DAC1 SYSCFG_CFGR1_TIM6DAC1Ch1_DMA_RMP /*!< Old define maintained for legacy purpose */
mbed_official 155:8435094ec241 6883 #define SYSCFG_CFGR1_TIM7DAC2 SYSCFG_CFGR1_TIM7DAC1Ch2_DMA_RMP /*!< Old define maintained for legacy purpose */
mbed_official 155:8435094ec241 6884 /***************** Bit definition for SYSCFG_RCR register *******************/
mbed_official 155:8435094ec241 6885 #define SYSCFG_RCR_PAGE0 ((uint32_t)0x00000001) /*!< ICODE SRAM Write protection page 0 */
mbed_official 155:8435094ec241 6886 #define SYSCFG_RCR_PAGE1 ((uint32_t)0x00000002) /*!< ICODE SRAM Write protection page 1 */
mbed_official 155:8435094ec241 6887 #define SYSCFG_RCR_PAGE2 ((uint32_t)0x00000004) /*!< ICODE SRAM Write protection page 2 */
mbed_official 155:8435094ec241 6888 #define SYSCFG_RCR_PAGE3 ((uint32_t)0x00000008) /*!< ICODE SRAM Write protection page 3 */
mbed_official 155:8435094ec241 6889 #define SYSCFG_RCR_PAGE4 ((uint32_t)0x00000010) /*!< ICODE SRAM Write protection page 4 */
mbed_official 155:8435094ec241 6890 #define SYSCFG_RCR_PAGE5 ((uint32_t)0x00000020) /*!< ICODE SRAM Write protection page 5 */
mbed_official 155:8435094ec241 6891 #define SYSCFG_RCR_PAGE6 ((uint32_t)0x00000040) /*!< ICODE SRAM Write protection page 6 */
mbed_official 155:8435094ec241 6892 #define SYSCFG_RCR_PAGE7 ((uint32_t)0x00000080) /*!< ICODE SRAM Write protection page 7 */
mbed_official 155:8435094ec241 6893
mbed_official 155:8435094ec241 6894 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
mbed_official 155:8435094ec241 6895 #define SYSCFG_EXTICR1_EXTI0 ((uint16_t)0x000F) /*!< EXTI 0 configuration */
mbed_official 155:8435094ec241 6896 #define SYSCFG_EXTICR1_EXTI1 ((uint16_t)0x00F0) /*!< EXTI 1 configuration */
mbed_official 155:8435094ec241 6897 #define SYSCFG_EXTICR1_EXTI2 ((uint16_t)0x0F00) /*!< EXTI 2 configuration */
mbed_official 155:8435094ec241 6898 #define SYSCFG_EXTICR1_EXTI3 ((uint16_t)0xF000) /*!< EXTI 3 configuration */
mbed_official 155:8435094ec241 6899
mbed_official 155:8435094ec241 6900 /**
mbed_official 155:8435094ec241 6901 * @brief EXTI0 configuration
mbed_official 155:8435094ec241 6902 */
mbed_official 155:8435094ec241 6903 #define SYSCFG_EXTICR1_EXTI0_PA ((uint16_t)0x0000) /*!< PA[0] pin */
mbed_official 155:8435094ec241 6904 #define SYSCFG_EXTICR1_EXTI0_PB ((uint16_t)0x0001) /*!< PB[0] pin */
mbed_official 155:8435094ec241 6905 #define SYSCFG_EXTICR1_EXTI0_PC ((uint16_t)0x0002) /*!< PC[0] pin */
mbed_official 155:8435094ec241 6906 #define SYSCFG_EXTICR1_EXTI0_PD ((uint16_t)0x0003) /*!< PD[0] pin */
mbed_official 155:8435094ec241 6907 #define SYSCFG_EXTICR1_EXTI0_PE ((uint16_t)0x0004) /*!< PE[0] pin */
mbed_official 155:8435094ec241 6908 #define SYSCFG_EXTICR1_EXTI0_PF ((uint16_t)0x0005) /*!< PF[0] pin */
mbed_official 155:8435094ec241 6909
mbed_official 155:8435094ec241 6910 /**
mbed_official 155:8435094ec241 6911 * @brief EXTI1 configuration
mbed_official 155:8435094ec241 6912 */
mbed_official 155:8435094ec241 6913 #define SYSCFG_EXTICR1_EXTI1_PA ((uint16_t)0x0000) /*!< PA[1] pin */
mbed_official 155:8435094ec241 6914 #define SYSCFG_EXTICR1_EXTI1_PB ((uint16_t)0x0010) /*!< PB[1] pin */
mbed_official 155:8435094ec241 6915 #define SYSCFG_EXTICR1_EXTI1_PC ((uint16_t)0x0020) /*!< PC[1] pin */
mbed_official 155:8435094ec241 6916 #define SYSCFG_EXTICR1_EXTI1_PD ((uint16_t)0x0030) /*!< PD[1] pin */
mbed_official 155:8435094ec241 6917 #define SYSCFG_EXTICR1_EXTI1_PE ((uint16_t)0x0040) /*!< PE[1] pin */
mbed_official 155:8435094ec241 6918 #define SYSCFG_EXTICR1_EXTI1_PF ((uint16_t)0x0050) /*!< PF[1] pin */
mbed_official 155:8435094ec241 6919
mbed_official 155:8435094ec241 6920 /**
mbed_official 155:8435094ec241 6921 * @brief EXTI2 configuration
mbed_official 155:8435094ec241 6922 */
mbed_official 155:8435094ec241 6923 #define SYSCFG_EXTICR1_EXTI2_PA ((uint16_t)0x0000) /*!< PA[2] pin */
mbed_official 155:8435094ec241 6924 #define SYSCFG_EXTICR1_EXTI2_PB ((uint16_t)0x0100) /*!< PB[2] pin */
mbed_official 155:8435094ec241 6925 #define SYSCFG_EXTICR1_EXTI2_PC ((uint16_t)0x0200) /*!< PC[2] pin */
mbed_official 155:8435094ec241 6926 #define SYSCFG_EXTICR1_EXTI2_PD ((uint16_t)0x0300) /*!< PD[2] pin */
mbed_official 155:8435094ec241 6927 #define SYSCFG_EXTICR1_EXTI2_PE ((uint16_t)0x0400) /*!< PE[2] pin */
mbed_official 155:8435094ec241 6928 #define SYSCFG_EXTICR1_EXTI2_PF ((uint16_t)0x0500) /*!< PF[2] pin */
mbed_official 155:8435094ec241 6929
mbed_official 155:8435094ec241 6930 /**
mbed_official 155:8435094ec241 6931 * @brief EXTI3 configuration
mbed_official 155:8435094ec241 6932 */
mbed_official 155:8435094ec241 6933 #define SYSCFG_EXTICR1_EXTI3_PA ((uint16_t)0x0000) /*!< PA[3] pin */
mbed_official 155:8435094ec241 6934 #define SYSCFG_EXTICR1_EXTI3_PB ((uint16_t)0x1000) /*!< PB[3] pin */
mbed_official 155:8435094ec241 6935 #define SYSCFG_EXTICR1_EXTI3_PC ((uint16_t)0x2000) /*!< PC[3] pin */
mbed_official 155:8435094ec241 6936 #define SYSCFG_EXTICR1_EXTI3_PD ((uint16_t)0x3000) /*!< PD[3] pin */
mbed_official 155:8435094ec241 6937 #define SYSCFG_EXTICR1_EXTI3_PE ((uint16_t)0x4000) /*!< PE[3] pin */
mbed_official 155:8435094ec241 6938
mbed_official 155:8435094ec241 6939 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
mbed_official 155:8435094ec241 6940 #define SYSCFG_EXTIRCR_EXTI4 ((uint16_t)0x000F) /*!< EXTI 4 configuration */
mbed_official 155:8435094ec241 6941 #define SYSCFG_EXTIRCR_EXTI5 ((uint16_t)0x00F0) /*!< EXTI 5 configuration */
mbed_official 155:8435094ec241 6942 #define SYSCFG_EXTIRCR_EXTI6 ((uint16_t)0x0F00) /*!< EXTI 6 configuration */
mbed_official 155:8435094ec241 6943 #define SYSCFG_EXTIRCR_EXTI7 ((uint16_t)0xF000) /*!< EXTI 7 configuration */
mbed_official 155:8435094ec241 6944
mbed_official 155:8435094ec241 6945 /**
mbed_official 155:8435094ec241 6946 * @brief EXTI4 configuration
mbed_official 155:8435094ec241 6947 */
mbed_official 155:8435094ec241 6948 #define SYSCFG_EXTIRCR_EXTI4_PA ((uint16_t)0x0000) /*!< PA[4] pin */
mbed_official 155:8435094ec241 6949 #define SYSCFG_EXTIRCR_EXTI4_PB ((uint16_t)0x0001) /*!< PB[4] pin */
mbed_official 155:8435094ec241 6950 #define SYSCFG_EXTIRCR_EXTI4_PC ((uint16_t)0x0002) /*!< PC[4] pin */
mbed_official 155:8435094ec241 6951 #define SYSCFG_EXTIRCR_EXTI4_PD ((uint16_t)0x0003) /*!< PD[4] pin */
mbed_official 155:8435094ec241 6952 #define SYSCFG_EXTIRCR_EXTI4_PE ((uint16_t)0x0004) /*!< PE[4] pin */
mbed_official 155:8435094ec241 6953 #define SYSCFG_EXTIRCR_EXTI4_PF ((uint16_t)0x0005) /*!< PF[4] pin */
mbed_official 155:8435094ec241 6954
mbed_official 155:8435094ec241 6955 /**
mbed_official 155:8435094ec241 6956 * @brief EXTI5 configuration
mbed_official 155:8435094ec241 6957 */
mbed_official 155:8435094ec241 6958 #define SYSCFG_EXTIRCR_EXTI5_PA ((uint16_t)0x0000) /*!< PA[5] pin */
mbed_official 155:8435094ec241 6959 #define SYSCFG_EXTIRCR_EXTI5_PB ((uint16_t)0x0010) /*!< PB[5] pin */
mbed_official 155:8435094ec241 6960 #define SYSCFG_EXTIRCR_EXTI5_PC ((uint16_t)0x0020) /*!< PC[5] pin */
mbed_official 155:8435094ec241 6961 #define SYSCFG_EXTIRCR_EXTI5_PD ((uint16_t)0x0030) /*!< PD[5] pin */
mbed_official 155:8435094ec241 6962 #define SYSCFG_EXTIRCR_EXTI5_PE ((uint16_t)0x0040) /*!< PE[5] pin */
mbed_official 155:8435094ec241 6963 #define SYSCFG_EXTIRCR_EXTI5_PF ((uint16_t)0x0050) /*!< PF[5] pin */
mbed_official 155:8435094ec241 6964
mbed_official 155:8435094ec241 6965 /**
mbed_official 155:8435094ec241 6966 * @brief EXTI6 configuration
mbed_official 155:8435094ec241 6967 */
mbed_official 155:8435094ec241 6968 #define SYSCFG_EXTIRCR_EXTI6_PA ((uint16_t)0x0000) /*!< PA[6] pin */
mbed_official 155:8435094ec241 6969 #define SYSCFG_EXTIRCR_EXTI6_PB ((uint16_t)0x0100) /*!< PB[6] pin */
mbed_official 155:8435094ec241 6970 #define SYSCFG_EXTIRCR_EXTI6_PC ((uint16_t)0x0200) /*!< PC[6] pin */
mbed_official 155:8435094ec241 6971 #define SYSCFG_EXTIRCR_EXTI6_PD ((uint16_t)0x0300) /*!< PD[6] pin */
mbed_official 155:8435094ec241 6972 #define SYSCFG_EXTIRCR_EXTI6_PE ((uint16_t)0x0400) /*!< PE[6] pin */
mbed_official 155:8435094ec241 6973 #define SYSCFG_EXTIRCR_EXTI6_PF ((uint16_t)0x0500) /*!< PF[6] pin */
mbed_official 155:8435094ec241 6974
mbed_official 155:8435094ec241 6975 /**
mbed_official 155:8435094ec241 6976 * @brief EXTI7 configuration
mbed_official 155:8435094ec241 6977 */
mbed_official 155:8435094ec241 6978 #define SYSCFG_EXTIRCR_EXTI7_PA ((uint16_t)0x0000) /*!< PA[7] pin */
mbed_official 155:8435094ec241 6979 #define SYSCFG_EXTIRCR_EXTI7_PB ((uint16_t)0x1000) /*!< PB[7] pin */
mbed_official 155:8435094ec241 6980 #define SYSCFG_EXTIRCR_EXTI7_PC ((uint16_t)0x2000) /*!< PC[7] pin */
mbed_official 155:8435094ec241 6981 #define SYSCFG_EXTIRCR_EXTI7_PD ((uint16_t)0x3000) /*!< PD[7] pin */
mbed_official 155:8435094ec241 6982 #define SYSCFG_EXTIRCR_EXTI7_PE ((uint16_t)0x4000) /*!< PE[7] pin */
mbed_official 155:8435094ec241 6983
mbed_official 155:8435094ec241 6984 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
mbed_official 155:8435094ec241 6985 #define SYSCFG_EXTICR3_EXTI8 ((uint16_t)0x000F) /*!< EXTI 8 configuration */
mbed_official 155:8435094ec241 6986 #define SYSCFG_EXTICR3_EXTI9 ((uint16_t)0x00F0) /*!< EXTI 9 configuration */
mbed_official 155:8435094ec241 6987 #define SYSCFG_EXTICR3_EXTI10 ((uint16_t)0x0F00) /*!< EXTI 10 configuration */
mbed_official 155:8435094ec241 6988 #define SYSCFG_EXTICR3_EXTI11 ((uint16_t)0xF000) /*!< EXTI 11 configuration */
mbed_official 155:8435094ec241 6989
mbed_official 155:8435094ec241 6990 /**
mbed_official 155:8435094ec241 6991 * @brief EXTI8 configuration
mbed_official 155:8435094ec241 6992 */
mbed_official 155:8435094ec241 6993 #define SYSCFG_EXTICR3_EXTI8_PA ((uint16_t)0x0000) /*!< PA[8] pin */
mbed_official 155:8435094ec241 6994 #define SYSCFG_EXTICR3_EXTI8_PB ((uint16_t)0x0001) /*!< PB[8] pin */
mbed_official 155:8435094ec241 6995 #define SYSCFG_EXTICR3_EXTI8_PC ((uint16_t)0x0002) /*!< PC[8] pin */
mbed_official 155:8435094ec241 6996 #define SYSCFG_EXTICR3_EXTI8_PD ((uint16_t)0x0003) /*!< PD[8] pin */
mbed_official 155:8435094ec241 6997 #define SYSCFG_EXTICR3_EXTI8_PE ((uint16_t)0x0004) /*!< PE[8] pin */
mbed_official 155:8435094ec241 6998
mbed_official 155:8435094ec241 6999 /**
mbed_official 155:8435094ec241 7000 * @brief EXTI9 configuration
mbed_official 155:8435094ec241 7001 */
mbed_official 155:8435094ec241 7002 #define SYSCFG_EXTICR3_EXTI9_PA ((uint16_t)0x0000) /*!< PA[9] pin */
mbed_official 155:8435094ec241 7003 #define SYSCFG_EXTICR3_EXTI9_PB ((uint16_t)0x0010) /*!< PB[9] pin */
mbed_official 155:8435094ec241 7004 #define SYSCFG_EXTICR3_EXTI9_PC ((uint16_t)0x0020) /*!< PC[9] pin */
mbed_official 155:8435094ec241 7005 #define SYSCFG_EXTICR3_EXTI9_PD ((uint16_t)0x0030) /*!< PD[9] pin */
mbed_official 155:8435094ec241 7006 #define SYSCFG_EXTICR3_EXTI9_PE ((uint16_t)0x0040) /*!< PE[9] pin */
mbed_official 155:8435094ec241 7007 #define SYSCFG_EXTICR3_EXTI9_PF ((uint16_t)0x0050) /*!< PF[9] pin */
mbed_official 155:8435094ec241 7008
mbed_official 155:8435094ec241 7009 /**
mbed_official 155:8435094ec241 7010 * @brief EXTI10 configuration
mbed_official 155:8435094ec241 7011 */
mbed_official 155:8435094ec241 7012 #define SYSCFG_EXTICR3_EXTI10_PA ((uint16_t)0x0000) /*!< PA[10] pin */
mbed_official 155:8435094ec241 7013 #define SYSCFG_EXTICR3_EXTI10_PB ((uint16_t)0x0100) /*!< PB[10] pin */
mbed_official 155:8435094ec241 7014 #define SYSCFG_EXTICR3_EXTI10_PC ((uint16_t)0x0200) /*!< PC[10] pin */
mbed_official 155:8435094ec241 7015 #define SYSCFG_EXTICR3_EXTI10_PD ((uint16_t)0x0300) /*!< PD[10] pin */
mbed_official 155:8435094ec241 7016 #define SYSCFG_EXTICR3_EXTI10_PE ((uint16_t)0x0400) /*!< PE[10] pin */
mbed_official 155:8435094ec241 7017 #define SYSCFG_EXTICR3_EXTI10_PF ((uint16_t)0x0500) /*!< PF[10] pin */
mbed_official 155:8435094ec241 7018
mbed_official 155:8435094ec241 7019 /**
mbed_official 155:8435094ec241 7020 * @brief EXTI11 configuration
mbed_official 155:8435094ec241 7021 */
mbed_official 155:8435094ec241 7022 #define SYSCFG_EXTICR3_EXTI11_PA ((uint16_t)0x0000) /*!< PA[11] pin */
mbed_official 155:8435094ec241 7023 #define SYSCFG_EXTICR3_EXTI11_PB ((uint16_t)0x1000) /*!< PB[11] pin */
mbed_official 155:8435094ec241 7024 #define SYSCFG_EXTICR3_EXTI11_PC ((uint16_t)0x2000) /*!< PC[11] pin */
mbed_official 155:8435094ec241 7025 #define SYSCFG_EXTICR3_EXTI11_PD ((uint16_t)0x3000) /*!< PD[11] pin */
mbed_official 155:8435094ec241 7026 #define SYSCFG_EXTICR3_EXTI11_PE ((uint16_t)0x4000) /*!< PE[11] pin */
mbed_official 155:8435094ec241 7027
mbed_official 155:8435094ec241 7028 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
mbed_official 155:8435094ec241 7029 #define SYSCFG_EXTICR4_EXTI12 ((uint16_t)0x000F) /*!< EXTI 12 configuration */
mbed_official 155:8435094ec241 7030 #define SYSCFG_EXTICR4_EXTI13 ((uint16_t)0x00F0) /*!< EXTI 13 configuration */
mbed_official 155:8435094ec241 7031 #define SYSCFG_EXTICR4_EXTI14 ((uint16_t)0x0F00) /*!< EXTI 14 configuration */
mbed_official 155:8435094ec241 7032 #define SYSCFG_EXTICR4_EXTI15 ((uint16_t)0xF000) /*!< EXTI 15 configuration */
mbed_official 155:8435094ec241 7033
mbed_official 155:8435094ec241 7034 /**
mbed_official 155:8435094ec241 7035 * @brief EXTI12 configuration
mbed_official 155:8435094ec241 7036 */
mbed_official 155:8435094ec241 7037 #define SYSCFG_EXTICR4_EXTI12_PA ((uint16_t)0x0000) /*!< PA[12] pin */
mbed_official 155:8435094ec241 7038 #define SYSCFG_EXTICR4_EXTI12_PB ((uint16_t)0x0001) /*!< PB[12] pin */
mbed_official 155:8435094ec241 7039 #define SYSCFG_EXTICR4_EXTI12_PC ((uint16_t)0x0002) /*!< PC[12] pin */
mbed_official 155:8435094ec241 7040 #define SYSCFG_EXTICR4_EXTI12_PD ((uint16_t)0x0003) /*!< PD[12] pin */
mbed_official 155:8435094ec241 7041 #define SYSCFG_EXTICR4_EXTI12_PE ((uint16_t)0x0004) /*!< PE[12] pin */
mbed_official 155:8435094ec241 7042
mbed_official 155:8435094ec241 7043 /**
mbed_official 155:8435094ec241 7044 * @brief EXTI13 configuration
mbed_official 155:8435094ec241 7045 */
mbed_official 155:8435094ec241 7046 #define SYSCFG_EXTICR4_EXTI13_PA ((uint16_t)0x0000) /*!< PA[13] pin */
mbed_official 155:8435094ec241 7047 #define SYSCFG_EXTICR4_EXTI13_PB ((uint16_t)0x0010) /*!< PB[13] pin */
mbed_official 155:8435094ec241 7048 #define SYSCFG_EXTICR4_EXTI13_PC ((uint16_t)0x0020) /*!< PC[13] pin */
mbed_official 155:8435094ec241 7049 #define SYSCFG_EXTICR4_EXTI13_PD ((uint16_t)0x0030) /*!< PD[13] pin */
mbed_official 155:8435094ec241 7050 #define SYSCFG_EXTICR4_EXTI13_PE ((uint16_t)0x0040) /*!< PE[13] pin */
mbed_official 155:8435094ec241 7051
mbed_official 155:8435094ec241 7052 /**
mbed_official 155:8435094ec241 7053 * @brief EXTI14 configuration
mbed_official 155:8435094ec241 7054 */
mbed_official 155:8435094ec241 7055 #define SYSCFG_EXTICR4_EXTI14_PA ((uint16_t)0x0000) /*!< PA[14] pin */
mbed_official 155:8435094ec241 7056 #define SYSCFG_EXTICR4_EXTI14_PB ((uint16_t)0x0100) /*!< PB[14] pin */
mbed_official 155:8435094ec241 7057 #define SYSCFG_EXTICR4_EXTI14_PC ((uint16_t)0x0200) /*!< PC[14] pin */
mbed_official 155:8435094ec241 7058 #define SYSCFG_EXTICR4_EXTI14_PD ((uint16_t)0x0300) /*!< PD[14] pin */
mbed_official 155:8435094ec241 7059 #define SYSCFG_EXTICR4_EXTI14_PE ((uint16_t)0x0400) /*!< PE[14] pin */
mbed_official 155:8435094ec241 7060
mbed_official 155:8435094ec241 7061 /**
mbed_official 155:8435094ec241 7062 * @brief EXTI15 configuration
mbed_official 155:8435094ec241 7063 */
mbed_official 155:8435094ec241 7064 #define SYSCFG_EXTICR4_EXTI15_PA ((uint16_t)0x0000) /*!< PA[15] pin */
mbed_official 155:8435094ec241 7065 #define SYSCFG_EXTICR4_EXTI15_PB ((uint16_t)0x1000) /*!< PB[15] pin */
mbed_official 155:8435094ec241 7066 #define SYSCFG_EXTICR4_EXTI15_PC ((uint16_t)0x2000) /*!< PC[15] pin */
mbed_official 155:8435094ec241 7067 #define SYSCFG_EXTICR4_EXTI15_PD ((uint16_t)0x3000) /*!< PD[15] pin */
mbed_official 155:8435094ec241 7068 #define SYSCFG_EXTICR4_EXTI15_PE ((uint16_t)0x4000) /*!< PE[15] pin */
mbed_official 155:8435094ec241 7069
mbed_official 155:8435094ec241 7070 /***************** Bit definition for SYSCFG_CFGR2 register *****************/
mbed_official 155:8435094ec241 7071 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the PVD connection with Timer1/8/15/16/17 Break Input and also the PVD_EN and PVDSEL[2:0] bits of the Power Control Interface */
mbed_official 155:8435094ec241 7072 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1/8/15/16/17 */
mbed_official 155:8435094ec241 7073 #define SYSCFG_CFGR2_PVD_LOCK ((uint32_t)0x00000004) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM4 with Break Input of TIMER1/8/15/16/17 */
mbed_official 155:8435094ec241 7074 #define SYSCFG_CFGR2_BYP_ADDR_PAR ((uint32_t)0x00000010) /*!< Disables the address parity check on RAM */
mbed_official 155:8435094ec241 7075 #define SYSCFG_CFGR2_SRAM_PE ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
mbed_official 155:8435094ec241 7076
mbed_official 155:8435094ec241 7077 /***************** Bit definition for SYSCFG_CFGR3 register *****************/
mbed_official 155:8435094ec241 7078 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP ((uint32_t)0x00000003) /*!< SPI1 RX DMA remap */
mbed_official 155:8435094ec241 7079 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_0 ((uint32_t)0x00000001) /*!< SPI1 RX DMA remap bit 0 */
mbed_official 155:8435094ec241 7080 #define SYSCFG_CFGR3_SPI1_RX_DMA_RMP_1 ((uint32_t)0x00000002) /*!< SPI1 RX DMA remap bit 1 */
mbed_official 155:8435094ec241 7081 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP ((uint32_t)0x0000000C) /*!< SPI1 TX DMA remap */
mbed_official 155:8435094ec241 7082 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_0 ((uint32_t)0x00000004) /*!< SPI1 TX DMA remap bit 0 */
mbed_official 155:8435094ec241 7083 #define SYSCFG_CFGR3_SPI1_TX_DMA_RMP_1 ((uint32_t)0x00000008) /*!< SPI1 TX DMA remap bit 1 */
mbed_official 155:8435094ec241 7084 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP ((uint32_t)0x00000030) /*!< I2C1 RX DMA remap */
mbed_official 155:8435094ec241 7085 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_0 ((uint32_t)0x00000010) /*!< I2C1 RX DMA remap bit 0 */
mbed_official 155:8435094ec241 7086 #define SYSCFG_CFGR3_I2C1_RX_DMA_RMP_1 ((uint32_t)0x00000020) /*!< I2C1 RX DMA remap bit 1 */
mbed_official 155:8435094ec241 7087 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP ((uint32_t)0x000000C0) /*!< I2C1 RX DMA remap */
mbed_official 155:8435094ec241 7088 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_0 ((uint32_t)0x00000040) /*!< I2C1 TX DMA remap bit 0 */
mbed_official 155:8435094ec241 7089 #define SYSCFG_CFGR3_I2C1_TX_DMA_RMP_1 ((uint32_t)0x00000080) /*!< I2C1 TX DMA remap bit 1 */
mbed_official 155:8435094ec241 7090 #define SYSCFG_CFGR3_ADC2_DMA_RMP ((uint32_t)0x00000300) /*!< ADC2 DMA remap */
mbed_official 155:8435094ec241 7091 #define SYSCFG_CFGR3_ADC2_DMA_RMP_0 ((uint32_t)0x00000100) /*!< ADC2 DMA remap bit 0 */
mbed_official 155:8435094ec241 7092 #define SYSCFG_CFGR3_ADC2_DMA_RMP_1 ((uint32_t)0x00000200) /*!< ADC2 DMA remap bit 1 */
mbed_official 155:8435094ec241 7093 #define SYSCFG_CFGR3_DAC1_TRG3_RMP ((uint32_t)0x00010000) /*!< DAC1 TRG3 remap */
mbed_official 155:8435094ec241 7094 #define SYSCFG_CFGR3_DAC1_TRG5_RMP ((uint32_t)0x00020000) /*!< DAC1 TRG5 remap */
mbed_official 155:8435094ec241 7095
mbed_official 155:8435094ec241 7096 /******************************************************************************/
mbed_official 155:8435094ec241 7097 /* */
mbed_official 155:8435094ec241 7098 /* TIM */
mbed_official 155:8435094ec241 7099 /* */
mbed_official 155:8435094ec241 7100 /******************************************************************************/
mbed_official 155:8435094ec241 7101 /******************* Bit definition for TIM_CR1 register ********************/
mbed_official 155:8435094ec241 7102 #define TIM_CR1_CEN ((uint16_t)0x0001) /*!<Counter enable */
mbed_official 155:8435094ec241 7103 #define TIM_CR1_UDIS ((uint16_t)0x0002) /*!<Update disable */
mbed_official 155:8435094ec241 7104 #define TIM_CR1_URS ((uint16_t)0x0004) /*!<Update request source */
mbed_official 155:8435094ec241 7105 #define TIM_CR1_OPM ((uint16_t)0x0008) /*!<One pulse mode */
mbed_official 155:8435094ec241 7106 #define TIM_CR1_DIR ((uint16_t)0x0010) /*!<Direction */
mbed_official 155:8435094ec241 7107
mbed_official 155:8435094ec241 7108 #define TIM_CR1_CMS ((uint16_t)0x0060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
mbed_official 155:8435094ec241 7109 #define TIM_CR1_CMS_0 ((uint16_t)0x0020) /*!<Bit 0 */
mbed_official 155:8435094ec241 7110 #define TIM_CR1_CMS_1 ((uint16_t)0x0040) /*!<Bit 1 */
mbed_official 155:8435094ec241 7111
mbed_official 155:8435094ec241 7112 #define TIM_CR1_ARPE ((uint16_t)0x0080) /*!<Auto-reload preload enable */
mbed_official 155:8435094ec241 7113
mbed_official 155:8435094ec241 7114 #define TIM_CR1_CKD ((uint16_t)0x0300) /*!<CKD[1:0] bits (clock division) */
mbed_official 155:8435094ec241 7115 #define TIM_CR1_CKD_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 155:8435094ec241 7116 #define TIM_CR1_CKD_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 155:8435094ec241 7117
mbed_official 155:8435094ec241 7118 #define TIM_CR1_UIFREMAP ((uint16_t)0x0800) /*!<Update interrupt flag remap */
mbed_official 155:8435094ec241 7119
mbed_official 155:8435094ec241 7120 /******************* Bit definition for TIM_CR2 register ********************/
mbed_official 155:8435094ec241 7121 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
mbed_official 155:8435094ec241 7122 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
mbed_official 155:8435094ec241 7123 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
mbed_official 155:8435094ec241 7124
mbed_official 155:8435094ec241 7125 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 155:8435094ec241 7126 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 7127 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 7128 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 7129
mbed_official 155:8435094ec241 7130 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
mbed_official 155:8435094ec241 7131 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
mbed_official 155:8435094ec241 7132 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
mbed_official 155:8435094ec241 7133 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
mbed_official 155:8435094ec241 7134 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
mbed_official 155:8435094ec241 7135 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
mbed_official 155:8435094ec241 7136 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
mbed_official 155:8435094ec241 7137 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 155:8435094ec241 7138 #define TIM_CR2_OIS5 ((uint32_t)0x00010000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 155:8435094ec241 7139 #define TIM_CR2_OIS6 ((uint32_t)0x00020000) /*!<Output Idle state 4 (OC4 output) */
mbed_official 155:8435094ec241 7140
mbed_official 155:8435094ec241 7141 #define TIM_CR2_MMS2 ((uint32_t)0x00F00000) /*!<MMS[2:0] bits (Master Mode Selection) */
mbed_official 155:8435094ec241 7142 #define TIM_CR2_MMS2_0 ((uint32_t)0x00100000) /*!<Bit 0 */
mbed_official 155:8435094ec241 7143 #define TIM_CR2_MMS2_1 ((uint32_t)0x00200000) /*!<Bit 1 */
mbed_official 155:8435094ec241 7144 #define TIM_CR2_MMS2_2 ((uint32_t)0x00400000) /*!<Bit 2 */
mbed_official 155:8435094ec241 7145 #define TIM_CR2_MMS2_3 ((uint32_t)0x00800000) /*!<Bit 2 */
mbed_official 155:8435094ec241 7146
mbed_official 155:8435094ec241 7147 /******************* Bit definition for TIM_SMCR register *******************/
mbed_official 155:8435094ec241 7148 #define TIM_SMCR_SMS ((uint32_t)0x00010007) /*!<SMS[2:0] bits (Slave mode selection) */
mbed_official 155:8435094ec241 7149 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7150 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7151 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 155:8435094ec241 7152 #define TIM_SMCR_SMS_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7153
mbed_official 155:8435094ec241 7154 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
mbed_official 155:8435094ec241 7155
mbed_official 155:8435094ec241 7156 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
mbed_official 155:8435094ec241 7157 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 7158 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 7159 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 7160
mbed_official 155:8435094ec241 7161 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
mbed_official 155:8435094ec241 7162
mbed_official 155:8435094ec241 7163 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
mbed_official 155:8435094ec241 7164 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 155:8435094ec241 7165 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 155:8435094ec241 7166 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
mbed_official 155:8435094ec241 7167 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
mbed_official 155:8435094ec241 7168
mbed_official 155:8435094ec241 7169 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
mbed_official 155:8435094ec241 7170 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 155:8435094ec241 7171 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 155:8435094ec241 7172
mbed_official 155:8435094ec241 7173 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
mbed_official 155:8435094ec241 7174 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
mbed_official 155:8435094ec241 7175
mbed_official 155:8435094ec241 7176 /******************* Bit definition for TIM_DIER register *******************/
mbed_official 155:8435094ec241 7177 #define TIM_DIER_UIE ((uint16_t)0x0001) /*!<Update interrupt enable */
mbed_official 155:8435094ec241 7178 #define TIM_DIER_CC1IE ((uint16_t)0x0002) /*!<Capture/Compare 1 interrupt enable */
mbed_official 155:8435094ec241 7179 #define TIM_DIER_CC2IE ((uint16_t)0x0004) /*!<Capture/Compare 2 interrupt enable */
mbed_official 155:8435094ec241 7180 #define TIM_DIER_CC3IE ((uint16_t)0x0008) /*!<Capture/Compare 3 interrupt enable */
mbed_official 155:8435094ec241 7181 #define TIM_DIER_CC4IE ((uint16_t)0x0010) /*!<Capture/Compare 4 interrupt enable */
mbed_official 155:8435094ec241 7182 #define TIM_DIER_COMIE ((uint16_t)0x0020) /*!<COM interrupt enable */
mbed_official 155:8435094ec241 7183 #define TIM_DIER_TIE ((uint16_t)0x0040) /*!<Trigger interrupt enable */
mbed_official 155:8435094ec241 7184 #define TIM_DIER_BIE ((uint16_t)0x0080) /*!<Break interrupt enable */
mbed_official 155:8435094ec241 7185 #define TIM_DIER_UDE ((uint16_t)0x0100) /*!<Update DMA request enable */
mbed_official 155:8435094ec241 7186 #define TIM_DIER_CC1DE ((uint16_t)0x0200) /*!<Capture/Compare 1 DMA request enable */
mbed_official 155:8435094ec241 7187 #define TIM_DIER_CC2DE ((uint16_t)0x0400) /*!<Capture/Compare 2 DMA request enable */
mbed_official 155:8435094ec241 7188 #define TIM_DIER_CC3DE ((uint16_t)0x0800) /*!<Capture/Compare 3 DMA request enable */
mbed_official 155:8435094ec241 7189 #define TIM_DIER_CC4DE ((uint16_t)0x1000) /*!<Capture/Compare 4 DMA request enable */
mbed_official 155:8435094ec241 7190 #define TIM_DIER_COMDE ((uint16_t)0x2000) /*!<COM DMA request enable */
mbed_official 155:8435094ec241 7191 #define TIM_DIER_TDE ((uint16_t)0x4000) /*!<Trigger DMA request enable */
mbed_official 155:8435094ec241 7192
mbed_official 155:8435094ec241 7193 /******************** Bit definition for TIM_SR register ********************/
mbed_official 155:8435094ec241 7194 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
mbed_official 155:8435094ec241 7195 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
mbed_official 155:8435094ec241 7196 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
mbed_official 155:8435094ec241 7197 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
mbed_official 155:8435094ec241 7198 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
mbed_official 155:8435094ec241 7199 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
mbed_official 155:8435094ec241 7200 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
mbed_official 155:8435094ec241 7201 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
mbed_official 155:8435094ec241 7202 #define TIM_SR_B2IF ((uint32_t)0x00000100) /*!<Break2 interrupt Flag */
mbed_official 155:8435094ec241 7203 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Over capture Flag */
mbed_official 155:8435094ec241 7204 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Over capture Flag */
mbed_official 155:8435094ec241 7205 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Over capture Flag */
mbed_official 155:8435094ec241 7206 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Over capture Flag */
mbed_official 155:8435094ec241 7207 #define TIM_SR_CC5IF ((uint32_t)0x00010000) /*!<Capture/Compare 5 interrupt Flag */
mbed_official 155:8435094ec241 7208 #define TIM_SR_CC6IF ((uint32_t)0x00020000) /*!<Capture/Compare 6 interrupt Flag */
mbed_official 155:8435094ec241 7209
mbed_official 155:8435094ec241 7210
mbed_official 155:8435094ec241 7211 /******************* Bit definition for TIM_EGR register ********************/
mbed_official 155:8435094ec241 7212 #define TIM_EGR_UG ((uint16_t)0x0001) /*!<Update Generation */
mbed_official 155:8435094ec241 7213 #define TIM_EGR_CC1G ((uint16_t)0x0002) /*!<Capture/Compare 1 Generation */
mbed_official 155:8435094ec241 7214 #define TIM_EGR_CC2G ((uint16_t)0x0004) /*!<Capture/Compare 2 Generation */
mbed_official 155:8435094ec241 7215 #define TIM_EGR_CC3G ((uint16_t)0x0008) /*!<Capture/Compare 3 Generation */
mbed_official 155:8435094ec241 7216 #define TIM_EGR_CC4G ((uint16_t)0x0010) /*!<Capture/Compare 4 Generation */
mbed_official 155:8435094ec241 7217 #define TIM_EGR_COMG ((uint16_t)0x0020) /*!<Capture/Compare Control Update Generation */
mbed_official 155:8435094ec241 7218 #define TIM_EGR_TG ((uint16_t)0x0040) /*!<Trigger Generation */
mbed_official 155:8435094ec241 7219 #define TIM_EGR_BG ((uint16_t)0x0080) /*!<Break Generation */
mbed_official 155:8435094ec241 7220 #define TIM_EGR_B2G ((uint16_t)0x0100) /*!<Break Generation */
mbed_official 155:8435094ec241 7221
mbed_official 155:8435094ec241 7222
mbed_official 155:8435094ec241 7223 /****************** Bit definition for TIM_CCMR1 register *******************/
mbed_official 155:8435094ec241 7224 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
mbed_official 155:8435094ec241 7225 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7226 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7227
mbed_official 155:8435094ec241 7228 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
mbed_official 155:8435094ec241 7229 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
mbed_official 155:8435094ec241 7230
mbed_official 155:8435094ec241 7231 #define TIM_CCMR1_OC1M ((uint32_t)0x00010070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
mbed_official 155:8435094ec241 7232 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 7233 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 7234 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 7235 #define TIM_CCMR1_OC1M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7236
mbed_official 155:8435094ec241 7237 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
mbed_official 155:8435094ec241 7238
mbed_official 155:8435094ec241 7239 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
mbed_official 155:8435094ec241 7240 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 155:8435094ec241 7241 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 155:8435094ec241 7242
mbed_official 155:8435094ec241 7243 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
mbed_official 155:8435094ec241 7244 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
mbed_official 155:8435094ec241 7245
mbed_official 155:8435094ec241 7246 #define TIM_CCMR1_OC2M ((uint32_t)0x01007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
mbed_official 155:8435094ec241 7247 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 155:8435094ec241 7248 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 155:8435094ec241 7249 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 155:8435094ec241 7250 #define TIM_CCMR1_OC2M_3 ((uint32_t)0x01000000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7251
mbed_official 155:8435094ec241 7252 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
mbed_official 155:8435094ec241 7253
mbed_official 155:8435094ec241 7254 /*----------------------------------------------------------------------------*/
mbed_official 155:8435094ec241 7255
mbed_official 155:8435094ec241 7256 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
mbed_official 155:8435094ec241 7257 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
mbed_official 155:8435094ec241 7258 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
mbed_official 155:8435094ec241 7259
mbed_official 155:8435094ec241 7260 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
mbed_official 155:8435094ec241 7261 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 7262 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 7263 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 7264 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
mbed_official 155:8435094ec241 7265
mbed_official 155:8435094ec241 7266 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
mbed_official 155:8435094ec241 7267 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
mbed_official 155:8435094ec241 7268 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
mbed_official 155:8435094ec241 7269
mbed_official 155:8435094ec241 7270 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
mbed_official 155:8435094ec241 7271 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 155:8435094ec241 7272 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 155:8435094ec241 7273 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 155:8435094ec241 7274 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7275
mbed_official 155:8435094ec241 7276 /****************** Bit definition for TIM_CCMR2 register *******************/
mbed_official 155:8435094ec241 7277 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
mbed_official 155:8435094ec241 7278 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7279 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7280
mbed_official 155:8435094ec241 7281 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
mbed_official 155:8435094ec241 7282 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
mbed_official 155:8435094ec241 7283
mbed_official 155:8435094ec241 7284 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
mbed_official 155:8435094ec241 7285 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 7286 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 7287 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 7288 #define TIM_CCMR2_OC3M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7289
mbed_official 155:8435094ec241 7290 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
mbed_official 155:8435094ec241 7291
mbed_official 155:8435094ec241 7292 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
mbed_official 155:8435094ec241 7293 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 155:8435094ec241 7294 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 155:8435094ec241 7295
mbed_official 155:8435094ec241 7296 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 155:8435094ec241 7297 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 155:8435094ec241 7298
mbed_official 155:8435094ec241 7299 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 155:8435094ec241 7300 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 155:8435094ec241 7301 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 155:8435094ec241 7302 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 155:8435094ec241 7303 #define TIM_CCMR2_OC4M_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7304
mbed_official 155:8435094ec241 7305 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 155:8435094ec241 7306
mbed_official 155:8435094ec241 7307 /*----------------------------------------------------------------------------*/
mbed_official 155:8435094ec241 7308
mbed_official 155:8435094ec241 7309 #define TIM_CCMR2_IC3PSC ((uint16_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
mbed_official 155:8435094ec241 7310 #define TIM_CCMR2_IC3PSC_0 ((uint16_t)0x00000004) /*!<Bit 0 */
mbed_official 155:8435094ec241 7311 #define TIM_CCMR2_IC3PSC_1 ((uint16_t)0x00000008) /*!<Bit 1 */
mbed_official 155:8435094ec241 7312
mbed_official 155:8435094ec241 7313 #define TIM_CCMR2_IC3F ((uint16_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
mbed_official 155:8435094ec241 7314 #define TIM_CCMR2_IC3F_0 ((uint16_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 7315 #define TIM_CCMR2_IC3F_1 ((uint16_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 7316 #define TIM_CCMR2_IC3F_2 ((uint16_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 7317 #define TIM_CCMR2_IC3F_3 ((uint16_t)0x00000080) /*!<Bit 3 */
mbed_official 155:8435094ec241 7318
mbed_official 155:8435094ec241 7319 #define TIM_CCMR2_IC4PSC ((uint16_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
mbed_official 155:8435094ec241 7320 #define TIM_CCMR2_IC4PSC_0 ((uint16_t)0x00000400) /*!<Bit 0 */
mbed_official 155:8435094ec241 7321 #define TIM_CCMR2_IC4PSC_1 ((uint16_t)0x00000800) /*!<Bit 1 */
mbed_official 155:8435094ec241 7322
mbed_official 155:8435094ec241 7323 #define TIM_CCMR2_IC4F ((uint16_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
mbed_official 155:8435094ec241 7324 #define TIM_CCMR2_IC4F_0 ((uint16_t)0x00001000) /*!<Bit 0 */
mbed_official 155:8435094ec241 7325 #define TIM_CCMR2_IC4F_1 ((uint16_t)0x00002000) /*!<Bit 1 */
mbed_official 155:8435094ec241 7326 #define TIM_CCMR2_IC4F_2 ((uint16_t)0x00004000) /*!<Bit 2 */
mbed_official 155:8435094ec241 7327 #define TIM_CCMR2_IC4F_3 ((uint16_t)0x00008000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7328
mbed_official 155:8435094ec241 7329 /******************* Bit definition for TIM_CCER register *******************/
mbed_official 155:8435094ec241 7330 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
mbed_official 155:8435094ec241 7331 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
mbed_official 155:8435094ec241 7332 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
mbed_official 155:8435094ec241 7333 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
mbed_official 155:8435094ec241 7334 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
mbed_official 155:8435094ec241 7335 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
mbed_official 155:8435094ec241 7336 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
mbed_official 155:8435094ec241 7337 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
mbed_official 155:8435094ec241 7338 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
mbed_official 155:8435094ec241 7339 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
mbed_official 155:8435094ec241 7340 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
mbed_official 155:8435094ec241 7341 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
mbed_official 155:8435094ec241 7342 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
mbed_official 155:8435094ec241 7343 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
mbed_official 155:8435094ec241 7344 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
mbed_official 155:8435094ec241 7345 #define TIM_CCER_CC5E ((uint32_t)0x00010000) /*!<Capture/Compare 5 output enable */
mbed_official 155:8435094ec241 7346 #define TIM_CCER_CC5P ((uint32_t)0x00020000) /*!<Capture/Compare 5 output Polarity */
mbed_official 155:8435094ec241 7347 #define TIM_CCER_CC6E ((uint32_t)0x00100000) /*!<Capture/Compare 6 output enable */
mbed_official 155:8435094ec241 7348 #define TIM_CCER_CC6P ((uint32_t)0x00200000) /*!<Capture/Compare 6 output Polarity */
mbed_official 155:8435094ec241 7349 /******************* Bit definition for TIM_CNT register ********************/
mbed_official 155:8435094ec241 7350 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
mbed_official 155:8435094ec241 7351 #define TIM_CNT_UIFCPY ((uint32_t)0x80000000) /*!<Update interrupt flag copy */
mbed_official 155:8435094ec241 7352 /******************* Bit definition for TIM_PSC register ********************/
mbed_official 155:8435094ec241 7353 #define TIM_PSC_PSC ((uint16_t)0xFFFF) /*!<Prescaler Value */
mbed_official 155:8435094ec241 7354
mbed_official 155:8435094ec241 7355 /******************* Bit definition for TIM_ARR register ********************/
mbed_official 155:8435094ec241 7356 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
mbed_official 155:8435094ec241 7357
mbed_official 155:8435094ec241 7358 /******************* Bit definition for TIM_RCR register ********************/
mbed_official 155:8435094ec241 7359 #define TIM_RCR_REP ((uint8_t)0xFF) /*!<Repetition Counter Value */
mbed_official 155:8435094ec241 7360
mbed_official 155:8435094ec241 7361 /******************* Bit definition for TIM_CCR1 register *******************/
mbed_official 155:8435094ec241 7362 #define TIM_CCR1_CCR1 ((uint16_t)0xFFFF) /*!<Capture/Compare 1 Value */
mbed_official 155:8435094ec241 7363
mbed_official 155:8435094ec241 7364 /******************* Bit definition for TIM_CCR2 register *******************/
mbed_official 155:8435094ec241 7365 #define TIM_CCR2_CCR2 ((uint16_t)0xFFFF) /*!<Capture/Compare 2 Value */
mbed_official 155:8435094ec241 7366
mbed_official 155:8435094ec241 7367 /******************* Bit definition for TIM_CCR3 register *******************/
mbed_official 155:8435094ec241 7368 #define TIM_CCR3_CCR3 ((uint16_t)0xFFFF) /*!<Capture/Compare 3 Value */
mbed_official 155:8435094ec241 7369
mbed_official 155:8435094ec241 7370 /******************* Bit definition for TIM_CCR4 register *******************/
mbed_official 155:8435094ec241 7371 #define TIM_CCR4_CCR4 ((uint16_t)0xFFFF) /*!<Capture/Compare 4 Value */
mbed_official 155:8435094ec241 7372
mbed_official 155:8435094ec241 7373 /******************* Bit definition for TIM_CCR5 register *******************/
mbed_official 155:8435094ec241 7374 #define TIM_CCR5_CCR5 ((uint32_t)0xFFFFFFFF) /*!<Capture/Compare 5 Value */
mbed_official 155:8435094ec241 7375 #define TIM_CCR5_GC5C1 ((uint32_t)0x20000000) /*!<Group Channel 5 and Channel 1 */
mbed_official 155:8435094ec241 7376 #define TIM_CCR5_GC5C2 ((uint32_t)0x40000000) /*!<Group Channel 5 and Channel 2 */
mbed_official 155:8435094ec241 7377 #define TIM_CCR5_GC5C3 ((uint32_t)0x80000000) /*!<Group Channel 5 and Channel 3 */
mbed_official 155:8435094ec241 7378
mbed_official 155:8435094ec241 7379 /******************* Bit definition for TIM_CCR6 register *******************/
mbed_official 155:8435094ec241 7380 #define TIM_CCR6_CCR6 ((uint16_t)0xFFFF) /*!<Capture/Compare 6 Value */
mbed_official 155:8435094ec241 7381
mbed_official 155:8435094ec241 7382 /******************* Bit definition for TIM_BDTR register *******************/
mbed_official 155:8435094ec241 7383 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
mbed_official 155:8435094ec241 7384 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7385 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7386 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
mbed_official 155:8435094ec241 7387 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
mbed_official 155:8435094ec241 7388 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
mbed_official 155:8435094ec241 7389 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
mbed_official 155:8435094ec241 7390 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
mbed_official 155:8435094ec241 7391 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
mbed_official 155:8435094ec241 7392
mbed_official 155:8435094ec241 7393 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
mbed_official 155:8435094ec241 7394 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
mbed_official 155:8435094ec241 7395 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
mbed_official 155:8435094ec241 7396
mbed_official 155:8435094ec241 7397 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
mbed_official 155:8435094ec241 7398 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
mbed_official 155:8435094ec241 7399 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable for Break1 */
mbed_official 155:8435094ec241 7400 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity for Break1 */
mbed_official 155:8435094ec241 7401 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
mbed_official 155:8435094ec241 7402 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
mbed_official 155:8435094ec241 7403
mbed_official 155:8435094ec241 7404 #define TIM_BDTR_BKF ((uint32_t)0x000F0000) /*!<Break Filter for Break1 */
mbed_official 155:8435094ec241 7405 #define TIM_BDTR_BK2F ((uint32_t)0x00F00000) /*!<Break Filter for Break2 */
mbed_official 155:8435094ec241 7406
mbed_official 155:8435094ec241 7407 #define TIM_BDTR_BK2E ((uint32_t)0x01000000) /*!<Break enable for Break2 */
mbed_official 155:8435094ec241 7408 #define TIM_BDTR_BK2P ((uint32_t)0x02000000) /*!<Break Polarity for Break2 */
mbed_official 155:8435094ec241 7409
mbed_official 155:8435094ec241 7410 /******************* Bit definition for TIM_DCR register ********************/
mbed_official 155:8435094ec241 7411 #define TIM_DCR_DBA ((uint16_t)0x001F) /*!<DBA[4:0] bits (DMA Base Address) */
mbed_official 155:8435094ec241 7412 #define TIM_DCR_DBA_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7413 #define TIM_DCR_DBA_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7414 #define TIM_DCR_DBA_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 155:8435094ec241 7415 #define TIM_DCR_DBA_3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 155:8435094ec241 7416 #define TIM_DCR_DBA_4 ((uint16_t)0x0010) /*!<Bit 4 */
mbed_official 155:8435094ec241 7417
mbed_official 155:8435094ec241 7418 #define TIM_DCR_DBL ((uint16_t)0x1F00) /*!<DBL[4:0] bits (DMA Burst Length) */
mbed_official 155:8435094ec241 7419 #define TIM_DCR_DBL_0 ((uint16_t)0x0100) /*!<Bit 0 */
mbed_official 155:8435094ec241 7420 #define TIM_DCR_DBL_1 ((uint16_t)0x0200) /*!<Bit 1 */
mbed_official 155:8435094ec241 7421 #define TIM_DCR_DBL_2 ((uint16_t)0x0400) /*!<Bit 2 */
mbed_official 155:8435094ec241 7422 #define TIM_DCR_DBL_3 ((uint16_t)0x0800) /*!<Bit 3 */
mbed_official 155:8435094ec241 7423 #define TIM_DCR_DBL_4 ((uint16_t)0x1000) /*!<Bit 4 */
mbed_official 155:8435094ec241 7424
mbed_official 155:8435094ec241 7425 /******************* Bit definition for TIM_DMAR register *******************/
mbed_official 155:8435094ec241 7426 #define TIM_DMAR_DMAB ((uint16_t)0xFFFF) /*!<DMA register for burst accesses */
mbed_official 155:8435094ec241 7427
mbed_official 155:8435094ec241 7428 /******************* Bit definition for TIM16_OR register *********************/
mbed_official 155:8435094ec241 7429 #define TIM16_OR_TI1_RMP ((uint16_t)0x00C0) /*!<TI1_RMP[1:0] bits (TIM16 Input 1 remap) */
mbed_official 155:8435094ec241 7430 #define TIM16_OR_TI1_RMP_0 ((uint16_t)0x0040) /*!<Bit 0 */
mbed_official 155:8435094ec241 7431 #define TIM16_OR_TI1_RMP_1 ((uint16_t)0x0080) /*!<Bit 1 */
mbed_official 155:8435094ec241 7432
mbed_official 155:8435094ec241 7433 /******************* Bit definition for TIM1_OR register *********************/
mbed_official 155:8435094ec241 7434 #define TIM1_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM1 ETR remap) */
mbed_official 155:8435094ec241 7435 #define TIM1_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7436 #define TIM1_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7437 #define TIM1_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 155:8435094ec241 7438 #define TIM1_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 155:8435094ec241 7439
mbed_official 155:8435094ec241 7440 /******************* Bit definition for TIM8_OR register *********************/
mbed_official 155:8435094ec241 7441 #define TIM8_OR_ETR_RMP ((uint16_t)0x000F) /*!<ETR_RMP[3:0] bits (TIM8 ETR remap) */
mbed_official 155:8435094ec241 7442 #define TIM8_OR_ETR_RMP_0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7443 #define TIM8_OR_ETR_RMP_1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7444 #define TIM8_OR_ETR_RMP_2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 155:8435094ec241 7445 #define TIM8_OR_ETR_RMP_3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 155:8435094ec241 7446
mbed_official 155:8435094ec241 7447 /****************** Bit definition for TIM_CCMR3 register *******************/
mbed_official 155:8435094ec241 7448 #define TIM_CCMR3_OC5FE ((uint32_t)0x00000004) /*!<Output Compare 5 Fast enable */
mbed_official 155:8435094ec241 7449 #define TIM_CCMR3_OC5PE ((uint32_t)0x00000008) /*!<Output Compare 5 Preload enable */
mbed_official 155:8435094ec241 7450
mbed_official 155:8435094ec241 7451 #define TIM_CCMR3_OC5M ((uint32_t)0x00000070) /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
mbed_official 155:8435094ec241 7452 #define TIM_CCMR3_OC5M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
mbed_official 155:8435094ec241 7453 #define TIM_CCMR3_OC5M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
mbed_official 155:8435094ec241 7454 #define TIM_CCMR3_OC5M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
mbed_official 155:8435094ec241 7455 #define TIM_CCMR3_OC5M_3 ((uint32_t)0x00010000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7456
mbed_official 155:8435094ec241 7457 #define TIM_CCMR3_OC5CE ((uint32_t)0x00000080) /*!<Output Compare 5 Clear Enable */
mbed_official 155:8435094ec241 7458
mbed_official 155:8435094ec241 7459 #define TIM_CCMR3_OC6FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
mbed_official 155:8435094ec241 7460 #define TIM_CCMR3_OC6PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
mbed_official 155:8435094ec241 7461
mbed_official 155:8435094ec241 7462 #define TIM_CCMR3_OC6M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
mbed_official 155:8435094ec241 7463 #define TIM_CCMR3_OC6M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
mbed_official 155:8435094ec241 7464 #define TIM_CCMR3_OC6M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
mbed_official 155:8435094ec241 7465 #define TIM_CCMR3_OC6M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
mbed_official 155:8435094ec241 7466 #define TIM_CCMR3_OC6M_3 ((uint32_t)0x00100000) /*!<Bit 3 */
mbed_official 155:8435094ec241 7467
mbed_official 155:8435094ec241 7468 #define TIM_CCMR3_OC6CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
mbed_official 155:8435094ec241 7469
mbed_official 155:8435094ec241 7470 /******************************************************************************/
mbed_official 155:8435094ec241 7471 /* */
mbed_official 155:8435094ec241 7472 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
mbed_official 155:8435094ec241 7473 /* */
mbed_official 155:8435094ec241 7474 /******************************************************************************/
mbed_official 155:8435094ec241 7475 /****************** Bit definition for USART_CR1 register *******************/
mbed_official 155:8435094ec241 7476 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
mbed_official 155:8435094ec241 7477 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
mbed_official 155:8435094ec241 7478 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
mbed_official 155:8435094ec241 7479 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
mbed_official 155:8435094ec241 7480 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
mbed_official 155:8435094ec241 7481 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
mbed_official 155:8435094ec241 7482 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
mbed_official 155:8435094ec241 7483 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
mbed_official 155:8435094ec241 7484 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
mbed_official 155:8435094ec241 7485 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
mbed_official 155:8435094ec241 7486 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
mbed_official 155:8435094ec241 7487 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
mbed_official 155:8435094ec241 7488 #define USART_CR1_M ((uint32_t)0x00001000) /*!< Word length */
mbed_official 155:8435094ec241 7489 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
mbed_official 155:8435094ec241 7490 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
mbed_official 155:8435094ec241 7491 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
mbed_official 155:8435094ec241 7492 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
mbed_official 155:8435094ec241 7493 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
mbed_official 155:8435094ec241 7494 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
mbed_official 155:8435094ec241 7495 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
mbed_official 155:8435094ec241 7496 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
mbed_official 155:8435094ec241 7497 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
mbed_official 155:8435094ec241 7498 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
mbed_official 155:8435094ec241 7499 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 155:8435094ec241 7500 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 155:8435094ec241 7501 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
mbed_official 155:8435094ec241 7502 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
mbed_official 155:8435094ec241 7503 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
mbed_official 155:8435094ec241 7504 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
mbed_official 155:8435094ec241 7505 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
mbed_official 155:8435094ec241 7506
mbed_official 155:8435094ec241 7507 /****************** Bit definition for USART_CR2 register *******************/
mbed_official 155:8435094ec241 7508 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
mbed_official 155:8435094ec241 7509 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
mbed_official 155:8435094ec241 7510 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
mbed_official 155:8435094ec241 7511 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
mbed_official 155:8435094ec241 7512 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
mbed_official 155:8435094ec241 7513 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
mbed_official 155:8435094ec241 7514 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
mbed_official 155:8435094ec241 7515 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
mbed_official 155:8435094ec241 7516 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
mbed_official 155:8435094ec241 7517 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
mbed_official 155:8435094ec241 7518 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
mbed_official 155:8435094ec241 7519 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
mbed_official 155:8435094ec241 7520 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
mbed_official 155:8435094ec241 7521 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
mbed_official 155:8435094ec241 7522 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
mbed_official 155:8435094ec241 7523 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
mbed_official 155:8435094ec241 7524 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
mbed_official 155:8435094ec241 7525 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
mbed_official 155:8435094ec241 7526 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
mbed_official 155:8435094ec241 7527 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
mbed_official 155:8435094ec241 7528 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
mbed_official 155:8435094ec241 7529 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
mbed_official 155:8435094ec241 7530
mbed_official 155:8435094ec241 7531 /****************** Bit definition for USART_CR3 register *******************/
mbed_official 155:8435094ec241 7532 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
mbed_official 155:8435094ec241 7533 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
mbed_official 155:8435094ec241 7534 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
mbed_official 155:8435094ec241 7535 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
mbed_official 155:8435094ec241 7536 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
mbed_official 155:8435094ec241 7537 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
mbed_official 155:8435094ec241 7538 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
mbed_official 155:8435094ec241 7539 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
mbed_official 155:8435094ec241 7540 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
mbed_official 155:8435094ec241 7541 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
mbed_official 155:8435094ec241 7542 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
mbed_official 155:8435094ec241 7543 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
mbed_official 155:8435094ec241 7544 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
mbed_official 155:8435094ec241 7545 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
mbed_official 155:8435094ec241 7546 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
mbed_official 155:8435094ec241 7547 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
mbed_official 155:8435094ec241 7548 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
mbed_official 155:8435094ec241 7549 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
mbed_official 155:8435094ec241 7550 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
mbed_official 155:8435094ec241 7551 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
mbed_official 155:8435094ec241 7552 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
mbed_official 155:8435094ec241 7553 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
mbed_official 155:8435094ec241 7554 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
mbed_official 155:8435094ec241 7555 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
mbed_official 155:8435094ec241 7556
mbed_official 155:8435094ec241 7557 /****************** Bit definition for USART_BRR register *******************/
mbed_official 155:8435094ec241 7558 #define USART_BRR_DIV_FRACTION ((uint16_t)0x000F) /*!< Fraction of USARTDIV */
mbed_official 155:8435094ec241 7559 #define USART_BRR_DIV_MANTISSA ((uint16_t)0xFFF0) /*!< Mantissa of USARTDIV */
mbed_official 155:8435094ec241 7560
mbed_official 155:8435094ec241 7561 /****************** Bit definition for USART_GTPR register ******************/
mbed_official 155:8435094ec241 7562 #define USART_GTPR_PSC ((uint16_t)0x00FF) /*!< PSC[7:0] bits (Prescaler value) */
mbed_official 155:8435094ec241 7563 #define USART_GTPR_GT ((uint16_t)0xFF00) /*!< GT[7:0] bits (Guard time value) */
mbed_official 155:8435094ec241 7564
mbed_official 155:8435094ec241 7565
mbed_official 155:8435094ec241 7566 /******************* Bit definition for USART_RTOR register *****************/
mbed_official 155:8435094ec241 7567 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
mbed_official 155:8435094ec241 7568 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
mbed_official 155:8435094ec241 7569
mbed_official 155:8435094ec241 7570 /******************* Bit definition for USART_RQR register ******************/
mbed_official 155:8435094ec241 7571 #define USART_RQR_ABRRQ ((uint16_t)0x0001) /*!< Auto-Baud Rate Request */
mbed_official 155:8435094ec241 7572 #define USART_RQR_SBKRQ ((uint16_t)0x0002) /*!< Send Break Request */
mbed_official 155:8435094ec241 7573 #define USART_RQR_MMRQ ((uint16_t)0x0004) /*!< Mute Mode Request */
mbed_official 155:8435094ec241 7574 #define USART_RQR_RXFRQ ((uint16_t)0x0008) /*!< Receive Data flush Request */
mbed_official 155:8435094ec241 7575 #define USART_RQR_TXFRQ ((uint16_t)0x0010) /*!< Transmit data flush Request */
mbed_official 155:8435094ec241 7576
mbed_official 155:8435094ec241 7577 /******************* Bit definition for USART_ISR register ******************/
mbed_official 155:8435094ec241 7578 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
mbed_official 155:8435094ec241 7579 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
mbed_official 155:8435094ec241 7580 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
mbed_official 155:8435094ec241 7581 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
mbed_official 155:8435094ec241 7582 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
mbed_official 155:8435094ec241 7583 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
mbed_official 155:8435094ec241 7584 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
mbed_official 155:8435094ec241 7585 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
mbed_official 155:8435094ec241 7586 #define USART_ISR_LBD ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
mbed_official 155:8435094ec241 7587 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
mbed_official 155:8435094ec241 7588 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
mbed_official 155:8435094ec241 7589 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
mbed_official 155:8435094ec241 7590 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
mbed_official 155:8435094ec241 7591 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
mbed_official 155:8435094ec241 7592 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
mbed_official 155:8435094ec241 7593 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
mbed_official 155:8435094ec241 7594 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
mbed_official 155:8435094ec241 7595 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
mbed_official 155:8435094ec241 7596 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
mbed_official 155:8435094ec241 7597 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
mbed_official 155:8435094ec241 7598 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
mbed_official 155:8435094ec241 7599 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
mbed_official 155:8435094ec241 7600
mbed_official 155:8435094ec241 7601 /******************* Bit definition for USART_ICR register ******************/
mbed_official 155:8435094ec241 7602 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
mbed_official 155:8435094ec241 7603 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
mbed_official 155:8435094ec241 7604 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
mbed_official 155:8435094ec241 7605 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
mbed_official 155:8435094ec241 7606 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
mbed_official 155:8435094ec241 7607 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
mbed_official 155:8435094ec241 7608 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
mbed_official 155:8435094ec241 7609 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
mbed_official 155:8435094ec241 7610 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
mbed_official 155:8435094ec241 7611 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
mbed_official 155:8435094ec241 7612 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
mbed_official 155:8435094ec241 7613 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
mbed_official 155:8435094ec241 7614
mbed_official 155:8435094ec241 7615 /******************* Bit definition for USART_RDR register ******************/
mbed_official 155:8435094ec241 7616 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
mbed_official 155:8435094ec241 7617
mbed_official 155:8435094ec241 7618 /******************* Bit definition for USART_TDR register ******************/
mbed_official 155:8435094ec241 7619 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
mbed_official 155:8435094ec241 7620
mbed_official 155:8435094ec241 7621 /******************************************************************************/
mbed_official 155:8435094ec241 7622 /* */
mbed_official 155:8435094ec241 7623 /* Window WATCHDOG */
mbed_official 155:8435094ec241 7624 /* */
mbed_official 155:8435094ec241 7625 /******************************************************************************/
mbed_official 155:8435094ec241 7626 /******************* Bit definition for WWDG_CR register ********************/
mbed_official 155:8435094ec241 7627 #define WWDG_CR_T ((uint8_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
mbed_official 155:8435094ec241 7628 #define WWDG_CR_T0 ((uint8_t)0x01) /*!<Bit 0 */
mbed_official 155:8435094ec241 7629 #define WWDG_CR_T1 ((uint8_t)0x02) /*!<Bit 1 */
mbed_official 155:8435094ec241 7630 #define WWDG_CR_T2 ((uint8_t)0x04) /*!<Bit 2 */
mbed_official 155:8435094ec241 7631 #define WWDG_CR_T3 ((uint8_t)0x08) /*!<Bit 3 */
mbed_official 155:8435094ec241 7632 #define WWDG_CR_T4 ((uint8_t)0x10) /*!<Bit 4 */
mbed_official 155:8435094ec241 7633 #define WWDG_CR_T5 ((uint8_t)0x20) /*!<Bit 5 */
mbed_official 155:8435094ec241 7634 #define WWDG_CR_T6 ((uint8_t)0x40) /*!<Bit 6 */
mbed_official 155:8435094ec241 7635
mbed_official 155:8435094ec241 7636 #define WWDG_CR_WDGA ((uint8_t)0x80) /*!<Activation bit */
mbed_official 155:8435094ec241 7637
mbed_official 155:8435094ec241 7638 /******************* Bit definition for WWDG_CFR register *******************/
mbed_official 155:8435094ec241 7639 #define WWDG_CFR_W ((uint16_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
mbed_official 155:8435094ec241 7640 #define WWDG_CFR_W0 ((uint16_t)0x0001) /*!<Bit 0 */
mbed_official 155:8435094ec241 7641 #define WWDG_CFR_W1 ((uint16_t)0x0002) /*!<Bit 1 */
mbed_official 155:8435094ec241 7642 #define WWDG_CFR_W2 ((uint16_t)0x0004) /*!<Bit 2 */
mbed_official 155:8435094ec241 7643 #define WWDG_CFR_W3 ((uint16_t)0x0008) /*!<Bit 3 */
mbed_official 155:8435094ec241 7644 #define WWDG_CFR_W4 ((uint16_t)0x0010) /*!<Bit 4 */
mbed_official 155:8435094ec241 7645 #define WWDG_CFR_W5 ((uint16_t)0x0020) /*!<Bit 5 */
mbed_official 155:8435094ec241 7646 #define WWDG_CFR_W6 ((uint16_t)0x0040) /*!<Bit 6 */
mbed_official 155:8435094ec241 7647
mbed_official 155:8435094ec241 7648 #define WWDG_CFR_WDGTB ((uint16_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
mbed_official 155:8435094ec241 7649 #define WWDG_CFR_WDGTB0 ((uint16_t)0x0080) /*!<Bit 0 */
mbed_official 155:8435094ec241 7650 #define WWDG_CFR_WDGTB1 ((uint16_t)0x0100) /*!<Bit 1 */
mbed_official 155:8435094ec241 7651
mbed_official 155:8435094ec241 7652 #define WWDG_CFR_EWI ((uint16_t)0x0200) /*!<Early Wakeup Interrupt */
mbed_official 155:8435094ec241 7653
mbed_official 155:8435094ec241 7654 /******************* Bit definition for WWDG_SR register ********************/
mbed_official 155:8435094ec241 7655 #define WWDG_SR_EWIF ((uint8_t)0x01) /*!<Early Wakeup Interrupt Flag */
mbed_official 155:8435094ec241 7656
mbed_official 155:8435094ec241 7657 /**
mbed_official 155:8435094ec241 7658 * @}
mbed_official 155:8435094ec241 7659 */
mbed_official 155:8435094ec241 7660
mbed_official 155:8435094ec241 7661 /**
mbed_official 155:8435094ec241 7662 * @}
mbed_official 155:8435094ec241 7663 */
mbed_official 155:8435094ec241 7664
mbed_official 155:8435094ec241 7665 #ifdef USE_STDPERIPH_DRIVER
mbed_official 155:8435094ec241 7666 #include "stm32f30x_conf.h"
mbed_official 155:8435094ec241 7667 #endif /*!< USE_STDPERIPH_DRIVER */
mbed_official 155:8435094ec241 7668
mbed_official 155:8435094ec241 7669 /** @addtogroup Exported_macro
mbed_official 155:8435094ec241 7670 * @{
mbed_official 155:8435094ec241 7671 */
mbed_official 155:8435094ec241 7672
mbed_official 155:8435094ec241 7673 #define SET_BIT(REG, BIT) ((REG) |= (BIT))
mbed_official 155:8435094ec241 7674
mbed_official 155:8435094ec241 7675 #define CLEAR_BIT(REG, BIT) ((REG) &= ~(BIT))
mbed_official 155:8435094ec241 7676
mbed_official 155:8435094ec241 7677 #define READ_BIT(REG, BIT) ((REG) & (BIT))
mbed_official 155:8435094ec241 7678
mbed_official 155:8435094ec241 7679 #define CLEAR_REG(REG) ((REG) = (0x0))
mbed_official 155:8435094ec241 7680
mbed_official 155:8435094ec241 7681 #define WRITE_REG(REG, VAL) ((REG) = (VAL))
mbed_official 155:8435094ec241 7682
mbed_official 155:8435094ec241 7683 #define READ_REG(REG) ((REG))
mbed_official 155:8435094ec241 7684
mbed_official 155:8435094ec241 7685 #define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
mbed_official 155:8435094ec241 7686
mbed_official 155:8435094ec241 7687 /**
mbed_official 155:8435094ec241 7688 * @}
mbed_official 155:8435094ec241 7689 */
mbed_official 155:8435094ec241 7690
mbed_official 155:8435094ec241 7691 #ifdef __cplusplus
mbed_official 155:8435094ec241 7692 }
mbed_official 155:8435094ec241 7693 #endif /* __cplusplus */
mbed_official 155:8435094ec241 7694
mbed_official 155:8435094ec241 7695 #endif /* __STM32F30x_H */
mbed_official 155:8435094ec241 7696
mbed_official 155:8435094ec241 7697 /**
mbed_official 155:8435094ec241 7698 * @}
mbed_official 155:8435094ec241 7699 */
mbed_official 155:8435094ec241 7700
mbed_official 155:8435094ec241 7701 /**
mbed_official 155:8435094ec241 7702 * @}
mbed_official 155:8435094ec241 7703 */
mbed_official 155:8435094ec241 7704
mbed_official 155:8435094ec241 7705 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/