test test test
Diff: snake-test/.link_script.sct
- Revision:
- 0:e4c5e6ec922e
diff -r 000000000000 -r e4c5e6ec922e snake-test/.link_script.sct --- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/snake-test/.link_script.sct Mon May 25 19:06:11 2020 +0000 @@ -0,0 +1,125 @@ +#! armclang -E --target=arm-arm-none-eabi -x c -mcpu=cortex-m4 -Imbed/TARGET_K64F/TOOLCHAIN_ARM_STD +/* +** ################################################################### +** Processors: MK64FN1M0CAJ12 +** MK64FN1M0VDC12 +** MK64FN1M0VLL12 +** MK64FN1M0VLQ12 +** MK64FN1M0VMD12 +** +** Compiler: Keil ARM C/C++ Compiler +** Reference manual: K64P144M120SF5RM, Rev.2, January 2014 +** Version: rev. 2.9, 2016-03-21 +** Build: b160406 +** +** Abstract: +** Linker file for the Keil ARM C/C++ Compiler +** +** Copyright (c) 2016 Freescale Semiconductor, Inc. +** All rights reserved. +** +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** o Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** o Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** o Neither the name of Freescale Semiconductor, Inc. nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.freescale.com +** mail: support@freescale.com +** +** ################################################################### +*/ +#define __ram_vector_table__ 1 + +#if (defined(__ram_vector_table__)) + #define __ram_vector_table_size__ 0x00000400 +#else + #define __ram_vector_table_size__ 0x00000000 +#endif + +#if !defined(MBED_APP_START) + #define MBED_APP_START 0 +#endif + +#if !defined(MBED_APP_SIZE) + #define MBED_APP_SIZE 0x100000 +#endif + +#define m_interrupts_start MBED_APP_START +#define m_interrupts_size 0x00000400 + +#define m_flash_config_start MBED_APP_START + 0x400 +#define m_flash_config_size 0x00000010 + +#define m_text_start MBED_APP_START + 0x410 +#define m_text_size MBED_APP_SIZE - 0x410 + +#define m_interrupts_ram_start 0x1FFF0000 +#define m_interrupts_ram_size __ram_vector_table_size__ + +#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size) +#define m_data_size (0x00010000 - m_interrupts_ram_size) + +#define m_data_2_start 0x20000000 +#define m_data_2_size 0x00030000 + +/* Sizes */ +#if (defined(__stack_size__)) + #define Stack_Size __stack_size__ +#else + #define Stack_Size 0x0400 +#endif + +#if (defined(__heap_size__)) + #define Heap_Size __heap_size__ +#else + #define Heap_Size 0x0400 +#endif + +LR_IROM1 m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region + VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address + * (RESET,+FIRST) + } + ER_m_flash_config m_flash_config_start FIXED m_flash_config_size { ; load address = execution address + * (FlashConfig) + } + ER_IROM1 m_text_start m_text_size { ; load address = execution address + * (InRoot$$Sections) + .ANY (+RO) + } + +#if (defined(__ram_vector_table__)) + VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size { + } +#else + VECTOR_RAM m_interrupts_start EMPTY 0 { + } +#endif + RW_m_data m_data_start m_data_size { ; RW data + .ANY (+RW +ZI) + } + RW_m_data_2 m_data_2_start m_data_2_size-Stack_Size-Heap_Size { ; RW data + .ANY (+RW +ZI) + } + RW_IRAM1 ImageLimit(RW_m_data_2) { ; Heap region growing up + } +}