Diff: inair.cpp

Revision:

4:0086deec9cac

Parent:

2:93cf5cb235ee

Child:

5:1a255cc8d54a

--- a/inair.cpp	Mon Sep 14 14:30:18 2015 +1000
+++ b/inair.cpp	Thu Sep 17 11:22:51 2015 +1000
@@ -14,6 +14,16 @@
 */
 #include "inair.h"
 
+//MODTRONIX BEGIN /////////////////////////////////////////////////////////////
+#define DEBUG_ENABLE            0
+#if (DEBUG_ENABLE == 1)
+    extern Stream* pMxDebug;            //Define Stream for debug output in user code called pMxDebug
+    #define MX_DEBUG pMxDebug->printf
+#else
+    #define MX_DEBUG(format, args...) ((void)0)
+#endif
+//MODTRONIX END ///////////////////////////////////////////////////////////////
+
 #define INAIR_ENABLE_FSK    0
 
 const FskBandwidth_t InAir::FskBandwidths[] =
@@ -1275,6 +1285,17 @@
                         {
                             this->settings.State = IDLE;
                         }
+                        //MODTRONIX BEGIN /////////////////////////////////////////
+                        // For Continuous reception, we remain in Receive mode. Delete current packet!
+                        // - RegFifoAddrPtr = FIFO Pointer used for SPI instructions.
+                        // - RegFifoRxByteAddr = Address of last byte written to FIFO + 1 = Start address of next receive packet
+                        else {
+                            //Get start address of next packet
+                            uint8_t startAddNxtPckt = Read(REG_LR_FIFORXBYTEADDR);
+                            //Set SPI pointer to address of next packet we will receive = delete current packet!
+                            Write(REG_LR_FIFOADDRPTR, startAddNxtPckt);
+                        }
+                        //MODTRONIX END ///////////////////////////////////////////
                         rxTimeoutTimer.detach( );
 
                         if( ( rxError != NULL ) )
@@ -1324,6 +1345,24 @@
                     }
 
                     this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
+
+                    //MODTRONIX BEGIN /////////////////////////////////////////
+                    //Debug Output:
+                    // - RegRxNbBytes = Nb bytes RXed
+                    // - RegFifoAddrPtr = FIFO Pointer used for SPI instructions.
+                    // - RegFifoRxBaseAddr = Set to 0 in Rx() function
+                    // - RegFifoRxCurrentAddr = Start address of last packet received
+                    // - RegFifoRxByteAddr = Address of last byte written to FIFO + 1 = Start address of next receive packet
+                    //
+                    MX_DEBUG("\r\nNB=%d AP=%d RB=%d CA=%d BA=%d", this->settings.LoRaPacketHandler.Size,
+                            Read(REG_LR_FIFOADDRPTR),
+                            Read(REG_LR_FIFORXBASEADDR),
+                            Read(REG_LR_FIFORXCURRENTADDR),
+                            Read(REG_LR_FIFORXBYTEADDR));
+                    //Ensure we read the last packet received. Without doing this, the bytes read can get out of sync
+                    //with the last packet received after errors occur!
+                    Write(REG_LR_FIFOADDRPTR, Read(REG_LR_FIFORXCURRENTADDR));
+                    //MODTRONIX END ///////////////////////////////////////////
                     ReadFifo( rxBuffer, this->settings.LoRaPacketHandler.Size );
                 
                     if( this->settings.LoRa.RxContinuous == false )