modtronix H / SX127x_modtronix

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Dependents:   SX1276_terminal SX1276_Semtech_GUI

Fork of SX127x by wayne roberts

sx127x.h@7:927a05f84ede, 2015-02-09 (annotated)

Committer:
dudmuck
Date:
Mon Feb 09 23:26:05 2015 +0000
Revision:
7:927a05f84ede
Parent:
5:dde68100518b 
added rf_switch callback for board-specific RF front-end implementation.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
dudmuck 0:27aa8733f85d 1 /* SX127x driver
dudmuck 0:27aa8733f85d 2 * Copyright (c) 2013 Semtech
dudmuck 0:27aa8733f85d 3 *
dudmuck 0:27aa8733f85d 4 * Licensed under the Apache License, Version 2.0 (the "License");
dudmuck 0:27aa8733f85d 5 * you may not use this file except in compliance with the License.
dudmuck 0:27aa8733f85d 6 * You may obtain a copy of the License at
dudmuck 0:27aa8733f85d 7 *
dudmuck 0:27aa8733f85d 8 * http://www.apache.org/licenses/LICENSE-2.0
dudmuck 0:27aa8733f85d 9 *
dudmuck 0:27aa8733f85d 10 * Unless required by applicable law or agreed to in writing, software
dudmuck 0:27aa8733f85d 11 * distributed under the License is distributed on an "AS IS" BASIS,
dudmuck 0:27aa8733f85d 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
dudmuck 0:27aa8733f85d 13 * See the License for the specific language governing permissions and
dudmuck 0:27aa8733f85d 14 * limitations under the License.
dudmuck 0:27aa8733f85d 15 */
dudmuck 0:27aa8733f85d 16
dudmuck 0:27aa8733f85d 17 #ifndef SX127x_H
dudmuck 0:27aa8733f85d 18 #define SX127x_H
dudmuck 0:27aa8733f85d 19
dudmuck 0:27aa8733f85d 20 #include "mbed.h"
dudmuck 0:27aa8733f85d 21
dudmuck 0:27aa8733f85d 22 #define XTAL_FREQ 32000000
dudmuck 0:27aa8733f85d 23
dudmuck 1:7dc60eb4c7ec 24 #define FREQ_STEP_MHZ 61.03515625e-6 // 32 / (2^19)
dudmuck 1:7dc60eb4c7ec 25 #define FREQ_STEP_KHZ 61.03515625e-3 // 32e3 / (2^19)
dudmuck 1:7dc60eb4c7ec 26 #define FREQ_STEP_HZ 61.03515625 // 32e6 / (2^19)
dudmuck 0:27aa8733f85d 27
dudmuck 0:27aa8733f85d 28 #define MHZ_TO_FRF(m) (m / FREQ_STEP_MHZ)
dudmuck 0:27aa8733f85d 29
dudmuck 0:27aa8733f85d 30 /******************************************************************************/
dudmuck 0:27aa8733f85d 31 /*!
dudmuck 0:27aa8733f85d 32 * SX127x Internal registers Address
dudmuck 0:27aa8733f85d 33 */
dudmuck 0:27aa8733f85d 34 #define REG_FIFO 0x00
dudmuck 0:27aa8733f85d 35 #define REG_OPMODE 0x01
dudmuck 0:27aa8733f85d 36 #define REG_FRFMSB 0x06
dudmuck 0:27aa8733f85d 37 #define REG_FRFMID 0x07
dudmuck 0:27aa8733f85d 38 #define REG_FRFLSB 0x08
dudmuck 0:27aa8733f85d 39 // Tx settings
dudmuck 0:27aa8733f85d 40 #define REG_PACONFIG 0x09
dudmuck 0:27aa8733f85d 41 #define REG_PARAMP 0x0A
dudmuck 0:27aa8733f85d 42 #define REG_OCP 0x0B
dudmuck 0:27aa8733f85d 43 // Rx settings
dudmuck 0:27aa8733f85d 44 #define REG_LNA 0x0C
dudmuck 0:27aa8733f85d 45
dudmuck 2:fdae76e1215e 46
dudmuck 0:27aa8733f85d 47 /***** registers above 0x40 are same as FSK/OOK page */
dudmuck 0:27aa8733f85d 48
dudmuck 0:27aa8733f85d 49 #define REG_DIOMAPPING1 0x40
dudmuck 0:27aa8733f85d 50 #define REG_DIOMAPPING2 0x41
dudmuck 0:27aa8733f85d 51 #define REG_VERSION 0x42
dudmuck 0:27aa8733f85d 52
dudmuck 7:927a05f84ede 53 #define REG_PDSTRIM1 0x5a
dudmuck 7:927a05f84ede 54 #define REG_PLL 0x5C // RX PLL bandwidth
dudmuck 7:927a05f84ede 55 #define REG_BSYNCTST2 0x67
dudmuck 2:fdae76e1215e 56 /******************************************************************************/
dudmuck 0:27aa8733f85d 57
dudmuck 0:27aa8733f85d 58
dudmuck 0:27aa8733f85d 59 typedef enum {
dudmuck 0:27aa8733f85d 60 RF_OPMODE_SLEEP = 0,
dudmuck 0:27aa8733f85d 61 RF_OPMODE_STANDBY, // 1
dudmuck 0:27aa8733f85d 62 RF_OPMODE_SYNTHESIZER_TX, // 2
dudmuck 0:27aa8733f85d 63 RF_OPMODE_TRANSMITTER, // 3
dudmuck 0:27aa8733f85d 64 RF_OPMODE_SYNTHESIZER_RX, // 4
dudmuck 0:27aa8733f85d 65 RF_OPMODE_RECEIVER, // 5
dudmuck 0:27aa8733f85d 66 RF_OPMODE_RECEIVER_SINGLE, // 6
dudmuck 0:27aa8733f85d 67 RF_OPMODE_CAD // 7
dudmuck 0:27aa8733f85d 68 } chip_mode_e;
dudmuck 0:27aa8733f85d 69
dudmuck 0:27aa8733f85d 70 typedef enum {
dudmuck 0:27aa8733f85d 71 SX_NONE = 0,
dudmuck 0:27aa8733f85d 72 SX1272,
dudmuck 0:27aa8733f85d 73 SX1276
dudmuck 0:27aa8733f85d 74 } type_e;
dudmuck 0:27aa8733f85d 75
dudmuck 0:27aa8733f85d 76 typedef enum {
dudmuck 0:27aa8733f85d 77 SERVICE_NONE = 0,
dudmuck 0:27aa8733f85d 78 SERVICE_ERROR,
dudmuck 0:27aa8733f85d 79 //! request to call read_fifo()
dudmuck 0:27aa8733f85d 80 SERVICE_READ_FIFO,
dudmuck 0:27aa8733f85d 81 //! notification to application of transmit complete
dudmuck 0:27aa8733f85d 82 SERVICE_TX_DONE
dudmuck 0:27aa8733f85d 83 } service_action_e;
dudmuck 0:27aa8733f85d 84
dudmuck 0:27aa8733f85d 85 /******************************************************************************/
dudmuck 0:27aa8733f85d 86
dudmuck 0:27aa8733f85d 87 typedef union {
dudmuck 0:27aa8733f85d 88 struct { // sx1272 register 0x01
dudmuck 0:27aa8733f85d 89 uint8_t Mode : 3; // 0,1,2
dudmuck 0:27aa8733f85d 90 uint8_t ModulationShaping : 2; // 3,4 FSK/OOK
dudmuck 0:27aa8733f85d 91 uint8_t ModulationType : 2; // 5,6 FSK/OOK
dudmuck 0:27aa8733f85d 92 uint8_t LongRangeMode : 1; // 7 change this bit only in sleep mode
dudmuck 0:27aa8733f85d 93 } bits;
dudmuck 0:27aa8733f85d 94 struct { // sx1276 register 0x01
dudmuck 0:27aa8733f85d 95 uint8_t Mode : 3; // 0,1,2
dudmuck 0:27aa8733f85d 96 uint8_t LowFrequencyModeOn : 1; // 3 1=access to LF test registers (0=HF regs)
dudmuck 0:27aa8733f85d 97 uint8_t reserved : 1; // 4
dudmuck 0:27aa8733f85d 98 uint8_t ModulationType : 2; // 5,6 FSK/OOK
dudmuck 0:27aa8733f85d 99 uint8_t LongRangeMode : 1; // 7 change this bit only in sleep mode
dudmuck 0:27aa8733f85d 100 } sx1276FSKbits;
dudmuck 0:27aa8733f85d 101 struct { // sx1276 register 0x01
dudmuck 0:27aa8733f85d 102 uint8_t Mode : 3; // 0,1,2
dudmuck 0:27aa8733f85d 103 uint8_t LowFrequencyModeOn : 1; // 3 1=access to LF test registers (0=HF regs)
dudmuck 0:27aa8733f85d 104 uint8_t reserved : 2; // 4,5
dudmuck 0:27aa8733f85d 105 uint8_t AccessSharedReg : 1; // 6 1=FSK registers while in LoRa mode
dudmuck 0:27aa8733f85d 106 uint8_t LongRangeMode : 1; // 7 change this bit only in sleep mode
dudmuck 0:27aa8733f85d 107 } sx1276LORAbits;
dudmuck 0:27aa8733f85d 108 uint8_t octet;
dudmuck 0:27aa8733f85d 109 } RegOpMode_t;
dudmuck 0:27aa8733f85d 110
dudmuck 0:27aa8733f85d 111 typedef union {
dudmuck 0:27aa8733f85d 112 struct { // sx12xx register 0x09
dudmuck 0:27aa8733f85d 113 uint8_t OutputPower : 4; // 0,1,2,3
dudmuck 0:27aa8733f85d 114 uint8_t MaxPower : 3; // 4,5,6
dudmuck 0:27aa8733f85d 115 uint8_t PaSelect : 1; // 7 1=PA_BOOST
dudmuck 0:27aa8733f85d 116 } bits;
dudmuck 0:27aa8733f85d 117 uint8_t octet;
dudmuck 0:27aa8733f85d 118 } RegPaConfig_t;
dudmuck 0:27aa8733f85d 119
dudmuck 0:27aa8733f85d 120 typedef union {
dudmuck 0:27aa8733f85d 121 struct { // sx12xx register 0x0b
dudmuck 0:27aa8733f85d 122 uint8_t OcpTrim : 5; // 0,1,2,3,4
dudmuck 0:27aa8733f85d 123 uint8_t OcpOn : 1; // 5
dudmuck 0:27aa8733f85d 124 uint8_t unused : 2; // 6,7
dudmuck 0:27aa8733f85d 125 } bits;
dudmuck 0:27aa8733f85d 126 uint8_t octet;
dudmuck 0:27aa8733f85d 127 } RegOcp_t;
dudmuck 0:27aa8733f85d 128
dudmuck 0:27aa8733f85d 129 typedef union {
dudmuck 0:27aa8733f85d 130 struct { // sx12xx register 0x0c
dudmuck 0:27aa8733f85d 131 uint8_t LnaBoostHF : 2; // 0,1
dudmuck 0:27aa8733f85d 132 uint8_t reserved : 1; // 2
dudmuck 0:27aa8733f85d 133 uint8_t LnaBoostLF : 2; // 3,4
dudmuck 0:27aa8733f85d 134 uint8_t LnaGain : 3; // 5,6,7
dudmuck 0:27aa8733f85d 135 } bits;
dudmuck 0:27aa8733f85d 136 uint8_t octet;
dudmuck 0:27aa8733f85d 137 } RegLna_t; // RXFE
dudmuck 0:27aa8733f85d 138
dudmuck 0:27aa8733f85d 139
dudmuck 2:fdae76e1215e 140 /*********************** ****************************/
dudmuck 0:27aa8733f85d 141
dudmuck 0:27aa8733f85d 142 typedef union {
dudmuck 0:27aa8733f85d 143 struct { // sx12xx register 0x40
dudmuck 0:27aa8733f85d 144 uint8_t Dio3Mapping : 2; // 0,1
dudmuck 0:27aa8733f85d 145 uint8_t Dio2Mapping : 2; // 2,3
dudmuck 0:27aa8733f85d 146 uint8_t Dio1Mapping : 2; // 4,5
dudmuck 0:27aa8733f85d 147 uint8_t Dio0Mapping : 2; // 6,7
dudmuck 0:27aa8733f85d 148 } bits;
dudmuck 0:27aa8733f85d 149 uint8_t octet;
dudmuck 0:27aa8733f85d 150 } RegDioMapping1_t;
dudmuck 0:27aa8733f85d 151
dudmuck 0:27aa8733f85d 152 typedef union {
dudmuck 0:27aa8733f85d 153 struct { // sx12xx register 0x41
dudmuck 0:27aa8733f85d 154 uint8_t MapPreambleDetect : 1; // 0 //DIO4 assign: 1b=preambleDet 0b=rssiThresh
dudmuck 0:27aa8733f85d 155 uint8_t io_mode : 3; // 1,2,3 //0=normal,1=debug,2=fpga,3=pll_tx,4=pll_rx,5=analog
dudmuck 0:27aa8733f85d 156 uint8_t Dio5Mapping : 2; // 4,5
dudmuck 0:27aa8733f85d 157 uint8_t Dio4Mapping : 2; // 6,7
dudmuck 0:27aa8733f85d 158 } bits;
dudmuck 0:27aa8733f85d 159 uint8_t octet;
dudmuck 0:27aa8733f85d 160 } RegDioMapping2_t;
dudmuck 0:27aa8733f85d 161
dudmuck 0:27aa8733f85d 162 /***************************************************/
dudmuck 0:27aa8733f85d 163
dudmuck 7:927a05f84ede 164 typedef union {
dudmuck 7:927a05f84ede 165 struct { // sx1272 register 0x5a
dudmuck 7:927a05f84ede 166 uint8_t prog_txdac : 3; // 0,1,2 BGR ref current to PA DAC
dudmuck 7:927a05f84ede 167 uint8_t pds_analog_test : 1; // 3
dudmuck 7:927a05f84ede 168 uint8_t pds_pa_test : 2; // 4,5
dudmuck 7:927a05f84ede 169 uint8_t pds_ptat : 2; // 6,7 leave at 2 (5uA)
dudmuck 7:927a05f84ede 170 } bits;
dudmuck 7:927a05f84ede 171 uint8_t octet;
dudmuck 7:927a05f84ede 172 } RegPdsTrim1_t;
dudmuck 7:927a05f84ede 173
dudmuck 7:927a05f84ede 174 typedef union {
dudmuck 7:927a05f84ede 175 struct { // sx1272 register 0x5c
dudmuck 7:927a05f84ede 176 uint8_t reserved : 6; // 0->5
dudmuck 7:927a05f84ede 177 uint8_t PllBandwidth : 2; // 6,7
dudmuck 7:927a05f84ede 178 } bits;
dudmuck 7:927a05f84ede 179 uint8_t octet;
dudmuck 7:927a05f84ede 180 } RegPll_t;
dudmuck 7:927a05f84ede 181
dudmuck 7:927a05f84ede 182 typedef union {
dudmuck 7:927a05f84ede 183 struct { // sx1272 register 0x67
dudmuck 7:927a05f84ede 184 uint8_t bsync_mode : 3; // 0,1,2
dudmuck 7:927a05f84ede 185 uint8_t reserved : 1; // 3
dudmuck 7:927a05f84ede 186 uint8_t bsync_thresh_validity : 1; // 4
dudmuck 7:927a05f84ede 187 uint8_t unused : 3; // 5,6,7
dudmuck 7:927a05f84ede 188 } bits;
dudmuck 7:927a05f84ede 189 uint8_t octet;
dudmuck 7:927a05f84ede 190 } RegBsyncTest2_t;
dudmuck 7:927a05f84ede 191
dudmuck 0:27aa8733f85d 192 /** FSK/LoRa radio transceiver.
dudmuck 0:27aa8733f85d 193 * see http://en.wikipedia.org/wiki/Chirp_spread_spectrum
dudmuck 0:27aa8733f85d 194 */
dudmuck 0:27aa8733f85d 195
dudmuck 0:27aa8733f85d 196 class SX127x {
dudmuck 0:27aa8733f85d 197 public:
dudmuck 0:27aa8733f85d 198 /** Create SX127x instance
dudmuck 0:27aa8733f85d 199 * @param mosi SPI master-out pin
dudmuck 0:27aa8733f85d 200 * @param miso SPI master-in pin
dudmuck 0:27aa8733f85d 201 * @param sclk SPI clock pin
dudmuck 0:27aa8733f85d 202 * @param cs SPI chip-select pin
dudmuck 0:27aa8733f85d 203 * @param rst radio hardware reset pin
dudmuck 0:27aa8733f85d 204 * @param dio_0 interrupt pin from radio
dudmuck 0:27aa8733f85d 205 * @param fem_ctx rx-tx switch for HF bands (800/900)
dudmuck 0:27aa8733f85d 206 * @param fem_cps rx-tx switch for LF bands (vhf/433)
dudmuck 0:27aa8733f85d 207 */
dudmuck 2:fdae76e1215e 208
dudmuck 7:927a05f84ede 209 SX127x(PinName mosi, PinName miso, PinName sclk, PinName cs, PinName rst, PinName dio_0, PinName dio_1);
dudmuck 0:27aa8733f85d 210
dudmuck 0:27aa8733f85d 211 ~SX127x();
dudmuck 0:27aa8733f85d 212
dudmuck 0:27aa8733f85d 213 /** set center operating frequency
dudmuck 0:27aa8733f85d 214 * @param MHz operating frequency in MHz
dudmuck 0:27aa8733f85d 215 */
dudmuck 0:27aa8733f85d 216 void set_frf_MHz( float MHz );
dudmuck 0:27aa8733f85d 217
dudmuck 0:27aa8733f85d 218 /** get center operating frequency
dudmuck 0:27aa8733f85d 219 * @returns operating frequency in MHz
dudmuck 0:27aa8733f85d 220 */
dudmuck 0:27aa8733f85d 221 float get_frf_MHz(void);
dudmuck 0:27aa8733f85d 222
dudmuck 0:27aa8733f85d 223 void set_opmode(chip_mode_e mode);
dudmuck 0:27aa8733f85d 224
dudmuck 0:27aa8733f85d 225 /** reset radio using pin
dudmuck 0:27aa8733f85d 226 */
dudmuck 0:27aa8733f85d 227 void hw_reset(void);
dudmuck 0:27aa8733f85d 228 /** initialise SX1232 class to radio
dudmuck 0:27aa8733f85d 229 * @note this is called from class instantiation, but must also be manually called after hardware reset
dudmuck 0:27aa8733f85d 230 */
dudmuck 0:27aa8733f85d 231 void init(void);
dudmuck 0:27aa8733f85d 232 void get_type(void); // identify radio chip
dudmuck 0:27aa8733f85d 233
dudmuck 0:27aa8733f85d 234 /** read register from radio
dudmuck 0:27aa8733f85d 235 * @param addr register address
dudmuck 0:27aa8733f85d 236 * @returns the value read from the register
dudmuck 0:27aa8733f85d 237 */
dudmuck 0:27aa8733f85d 238 uint8_t read_reg(uint8_t addr);
dudmuck 0:27aa8733f85d 239 uint16_t read_u16(uint8_t addr);
dudmuck 2:fdae76e1215e 240 int16_t read_s16(uint8_t addr);
dudmuck 0:27aa8733f85d 241
dudmuck 1:7dc60eb4c7ec 242 /** read register from radio. from an arbitrary amount of registers following the first
dudmuck 1:7dc60eb4c7ec 243 * @param addr register address
dudmuck 1:7dc60eb4c7ec 244 * @param buffer the read values will be placed here
dudmuck 1:7dc60eb4c7ec 245 * @param size how many registers to read
dudmuck 1:7dc60eb4c7ec 246 */
dudmuck 1:7dc60eb4c7ec 247 void ReadBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
dudmuck 1:7dc60eb4c7ec 248
dudmuck 0:27aa8733f85d 249 /** write register to radio
dudmuck 0:27aa8733f85d 250 * @param addr register address
dudmuck 0:27aa8733f85d 251 * @param data byte to write
dudmuck 0:27aa8733f85d 252 */
dudmuck 0:27aa8733f85d 253 void write_reg(uint8_t addr, uint8_t data);
dudmuck 4:d987ac2836bf 254 void write_u16(uint8_t addr, uint16_t data);
dudmuck 4:d987ac2836bf 255 void write_u24(uint8_t addr, uint32_t data);
dudmuck 0:27aa8733f85d 256
dudmuck 1:7dc60eb4c7ec 257 /** write register(s) to radio, to an arbitrary amount of registers following first
dudmuck 1:7dc60eb4c7ec 258 * @param addr register address
dudmuck 1:7dc60eb4c7ec 259 * @param buffer byte(s) to write
dudmuck 1:7dc60eb4c7ec 260 * @param size count of registers to write to
dudmuck 1:7dc60eb4c7ec 261 */
dudmuck 1:7dc60eb4c7ec 262 void WriteBuffer( uint8_t addr, uint8_t *buffer, uint8_t size );
dudmuck 1:7dc60eb4c7ec 263
dudmuck 1:7dc60eb4c7ec 264 /* *switch between FSK or LoRa modes */
dudmuck 2:fdae76e1215e 265 //void SetLoRaOn(bool);
dudmuck 1:7dc60eb4c7ec 266
dudmuck 0:27aa8733f85d 267 /*****************************************************/
dudmuck 0:27aa8733f85d 268
dudmuck 0:27aa8733f85d 269 //! RF transmit packet buffer
dudmuck 0:27aa8733f85d 270 uint8_t tx_buf[256]; // lora fifo size
dudmuck 0:27aa8733f85d 271
dudmuck 0:27aa8733f85d 272 //! RF receive packet buffer
dudmuck 0:27aa8733f85d 273 uint8_t rx_buf[256]; // lora fifo size
dudmuck 0:27aa8733f85d 274
dudmuck 0:27aa8733f85d 275 //! radio chip type plugged in
dudmuck 0:27aa8733f85d 276 type_e type;
dudmuck 0:27aa8733f85d 277
dudmuck 0:27aa8733f85d 278 //! operating mode
dudmuck 0:27aa8733f85d 279 RegOpMode_t RegOpMode;
dudmuck 0:27aa8733f85d 280
dudmuck 0:27aa8733f85d 281 //! transmitter power configuration
dudmuck 0:27aa8733f85d 282 RegPaConfig_t RegPaConfig;
dudmuck 0:27aa8733f85d 283
dudmuck 0:27aa8733f85d 284 RegOcp_t RegOcp; // 0x0b
dudmuck 0:27aa8733f85d 285
dudmuck 0:27aa8733f85d 286 // receiver front-end
dudmuck 0:27aa8733f85d 287 RegLna_t RegLna; // 0x0c
dudmuck 0:27aa8733f85d 288
dudmuck 0:27aa8733f85d 289 //! pin assignments
dudmuck 0:27aa8733f85d 290 RegDioMapping1_t RegDioMapping1;
dudmuck 0:27aa8733f85d 291
dudmuck 0:27aa8733f85d 292 //! pin assignments
dudmuck 2:fdae76e1215e 293 RegDioMapping2_t RegDioMapping2;
dudmuck 7:927a05f84ede 294
dudmuck 5:dde68100518b 295 DigitalIn dio0;
dudmuck 5:dde68100518b 296 DigitalIn dio1;
dudmuck 2:fdae76e1215e 297 DigitalOut m_cs;
dudmuck 2:fdae76e1215e 298 SPI m_spi;
dudmuck 2:fdae76e1215e 299 bool HF; // sx1272 is always HF
dudmuck 7:927a05f84ede 300
dudmuck 7:927a05f84ede 301 /*! board-specific RF switch callback, called whenever operating mode is changed
dudmuck 7:927a05f84ede 302 * This function should also set RegPaConfig.bits.PaSelect to use PA_BOOST or RFO during TX.
dudmuck 7:927a05f84ede 303 * examples:
dudmuck 7:927a05f84ede 304 * PE4259-63: controlled directly by radio chip, no software function needed
dudmuck 7:927a05f84ede 305 * SKY13350-385LF: two separate control lines, requires two DigitalOut pins
dudmuck 7:927a05f84ede 306 */
dudmuck 7:927a05f84ede 307 FunctionPointer rf_switch;
dudmuck 7:927a05f84ede 308
dudmuck 2:fdae76e1215e 309 private:
dudmuck 7:927a05f84ede 310 DigitalInOut reset_pin;
dudmuck 0:27aa8733f85d 311
dudmuck 0:27aa8733f85d 312 protected:
dudmuck 7:927a05f84ede 313 //FunctionPointer _callback_rx;
dudmuck 2:fdae76e1215e 314
dudmuck 0:27aa8733f85d 315 };
dudmuck 0:27aa8733f85d 316
dudmuck 0:27aa8733f85d 317 #endif /* SX127x_H */