Miguel Luis / SX1272Lib

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Fork of SX1272Lib by Semtech

sx1272/sx1272.cpp@7:ea82825968d2, 2016-11-24 (annotated)

Committer:
mluis
Date:
Thu Nov 24 12:22:04 2016 +0000
Revision:
7:ea82825968d2
Parent:
5:e90cbf646eb1
Child:
8:bfdcd5c6ec14
Synchronized radio driver with https://github.com/Lora-net/LoRaMac-node git develop branch commit 084b32173220ffb115e8360df17f50adb0ce5aaa

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mluis 0:45c4f0364ca4 1 /*
mluis 0:45c4f0364ca4 2 / _____) _ | |
mluis 0:45c4f0364ca4 3 ( (____ _____ ____ _| |_ _____ ____| |__
mluis 0:45c4f0364ca4 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
mluis 0:45c4f0364ca4 5 _____) ) ____| | | || |_| ____( (___| | | |
mluis 0:45c4f0364ca4 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 0:45c4f0364ca4 7 (C) 2015 Semtech
mluis 0:45c4f0364ca4 8
mluis 0:45c4f0364ca4 9 Description: Actual implementation of a SX1272 radio, inherits Radio
mluis 0:45c4f0364ca4 10
mluis 0:45c4f0364ca4 11 License: Revised BSD License, see LICENSE.TXT file include in the project
mluis 0:45c4f0364ca4 12
mluis 0:45c4f0364ca4 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
mluis 0:45c4f0364ca4 14 */
mluis 0:45c4f0364ca4 15 #include "sx1272.h"
mluis 0:45c4f0364ca4 16
mluis 0:45c4f0364ca4 17 const FskBandwidth_t SX1272::FskBandwidths[] =
mluis 0:45c4f0364ca4 18 {
mluis 0:45c4f0364ca4 19 { 2600 , 0x17 },
mluis 0:45c4f0364ca4 20 { 3100 , 0x0F },
mluis 0:45c4f0364ca4 21 { 3900 , 0x07 },
mluis 0:45c4f0364ca4 22 { 5200 , 0x16 },
mluis 0:45c4f0364ca4 23 { 6300 , 0x0E },
mluis 0:45c4f0364ca4 24 { 7800 , 0x06 },
mluis 0:45c4f0364ca4 25 { 10400 , 0x15 },
mluis 0:45c4f0364ca4 26 { 12500 , 0x0D },
mluis 0:45c4f0364ca4 27 { 15600 , 0x05 },
mluis 0:45c4f0364ca4 28 { 20800 , 0x14 },
mluis 0:45c4f0364ca4 29 { 25000 , 0x0C },
mluis 0:45c4f0364ca4 30 { 31300 , 0x04 },
mluis 0:45c4f0364ca4 31 { 41700 , 0x13 },
mluis 0:45c4f0364ca4 32 { 50000 , 0x0B },
mluis 0:45c4f0364ca4 33 { 62500 , 0x03 },
mluis 0:45c4f0364ca4 34 { 83333 , 0x12 },
mluis 0:45c4f0364ca4 35 { 100000, 0x0A },
mluis 0:45c4f0364ca4 36 { 125000, 0x02 },
mluis 0:45c4f0364ca4 37 { 166700, 0x11 },
mluis 0:45c4f0364ca4 38 { 200000, 0x09 },
mluis 0:45c4f0364ca4 39 { 250000, 0x01 },
mluis 0:45c4f0364ca4 40 { 300000, 0x00 }, // Invalid Badwidth
mluis 0:45c4f0364ca4 41 };
mluis 0:45c4f0364ca4 42
mluis 0:45c4f0364ca4 43
mluis 0:45c4f0364ca4 44 SX1272::SX1272( RadioEvents_t *events,
mluis 0:45c4f0364ca4 45 PinName mosi, PinName miso, PinName sclk, PinName nss, PinName reset,
mluis 0:45c4f0364ca4 46 PinName dio0, PinName dio1, PinName dio2, PinName dio3, PinName dio4, PinName dio5 )
mluis 0:45c4f0364ca4 47 : Radio( events ),
mluis 0:45c4f0364ca4 48 spi( mosi, miso, sclk ),
mluis 0:45c4f0364ca4 49 nss( nss ),
mluis 0:45c4f0364ca4 50 reset( reset ),
mluis 0:45c4f0364ca4 51 dio0( dio0 ), dio1( dio1 ), dio2( dio2 ), dio3( dio3 ), dio4( dio4 ), dio5( dio5 ),
mluis 0:45c4f0364ca4 52 isRadioActive( false )
mluis 0:45c4f0364ca4 53 {
mluis 0:45c4f0364ca4 54 wait_ms( 10 );
mluis 0:45c4f0364ca4 55 this->rxTx = 0;
GregCr 3:5baff45eb3c5 56 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 0:45c4f0364ca4 57 currentOpMode = RF_OPMODE_STANDBY;
mluis 0:45c4f0364ca4 58
mluis 0:45c4f0364ca4 59 this->RadioEvents = events;
mluis 0:45c4f0364ca4 60
mluis 0:45c4f0364ca4 61 this->dioIrq = new DioIrqHandler[6];
mluis 0:45c4f0364ca4 62
mluis 0:45c4f0364ca4 63 this->dioIrq[0] = &SX1272::OnDio0Irq;
mluis 0:45c4f0364ca4 64 this->dioIrq[1] = &SX1272::OnDio1Irq;
mluis 0:45c4f0364ca4 65 this->dioIrq[2] = &SX1272::OnDio2Irq;
mluis 0:45c4f0364ca4 66 this->dioIrq[3] = &SX1272::OnDio3Irq;
mluis 0:45c4f0364ca4 67 this->dioIrq[4] = &SX1272::OnDio4Irq;
mluis 0:45c4f0364ca4 68 this->dioIrq[5] = NULL;
mluis 0:45c4f0364ca4 69
mluis 0:45c4f0364ca4 70 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 71 }
mluis 0:45c4f0364ca4 72
mluis 0:45c4f0364ca4 73 SX1272::~SX1272( )
mluis 0:45c4f0364ca4 74 {
GregCr 3:5baff45eb3c5 75 delete this->rxtxBuffer;
mluis 0:45c4f0364ca4 76 delete this->dioIrq;
mluis 0:45c4f0364ca4 77 }
mluis 0:45c4f0364ca4 78
mluis 0:45c4f0364ca4 79 void SX1272::Init( RadioEvents_t *events )
mluis 0:45c4f0364ca4 80 {
mluis 0:45c4f0364ca4 81 this->RadioEvents = events;
mluis 0:45c4f0364ca4 82 }
mluis 0:45c4f0364ca4 83
mluis 0:45c4f0364ca4 84 RadioState SX1272::GetStatus( void )
mluis 0:45c4f0364ca4 85 {
mluis 0:45c4f0364ca4 86 return this->settings.State;
mluis 0:45c4f0364ca4 87 }
mluis 0:45c4f0364ca4 88
mluis 0:45c4f0364ca4 89 void SX1272::SetChannel( uint32_t freq )
mluis 0:45c4f0364ca4 90 {
mluis 0:45c4f0364ca4 91 this->settings.Channel = freq;
mluis 0:45c4f0364ca4 92 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 93 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
mluis 0:45c4f0364ca4 94 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 95 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
mluis 0:45c4f0364ca4 96 }
mluis 0:45c4f0364ca4 97
mluis 0:45c4f0364ca4 98 bool SX1272::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
mluis 0:45c4f0364ca4 99 {
mluis 0:45c4f0364ca4 100 int16_t rssi = 0;
mluis 4:90bd79f1b458 101
mluis 0:45c4f0364ca4 102 SetModem( modem );
mluis 0:45c4f0364ca4 103
mluis 0:45c4f0364ca4 104 SetChannel( freq );
mluis 4:90bd79f1b458 105
mluis 0:45c4f0364ca4 106 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 107
mluis 0:45c4f0364ca4 108 wait_ms( 1 );
mluis 4:90bd79f1b458 109
mluis 0:45c4f0364ca4 110 rssi = GetRssi( modem );
mluis 4:90bd79f1b458 111
mluis 0:45c4f0364ca4 112 Sleep( );
mluis 4:90bd79f1b458 113
mluis 0:45c4f0364ca4 114 if( rssi > rssiThresh )
mluis 0:45c4f0364ca4 115 {
mluis 0:45c4f0364ca4 116 return false;
mluis 0:45c4f0364ca4 117 }
mluis 0:45c4f0364ca4 118 return true;
mluis 0:45c4f0364ca4 119 }
mluis 0:45c4f0364ca4 120
mluis 0:45c4f0364ca4 121 uint32_t SX1272::Random( void )
mluis 0:45c4f0364ca4 122 {
mluis 0:45c4f0364ca4 123 uint8_t i;
mluis 0:45c4f0364ca4 124 uint32_t rnd = 0;
mluis 0:45c4f0364ca4 125
mluis 0:45c4f0364ca4 126 /*
mluis 4:90bd79f1b458 127 * Radio setup for random number generation
mluis 0:45c4f0364ca4 128 */
mluis 0:45c4f0364ca4 129 // Set LoRa modem ON
mluis 0:45c4f0364ca4 130 SetModem( MODEM_LORA );
mluis 0:45c4f0364ca4 131
mluis 0:45c4f0364ca4 132 // Disable LoRa modem interrupts
mluis 0:45c4f0364ca4 133 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 134 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 135 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 136 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 137 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 138 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 139 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 140 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 141
mluis 0:45c4f0364ca4 142 // Set radio in continuous reception
mluis 0:45c4f0364ca4 143 SetOpMode( RF_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 144
mluis 0:45c4f0364ca4 145 for( i = 0; i < 32; i++ )
mluis 0:45c4f0364ca4 146 {
mluis 0:45c4f0364ca4 147 wait_ms( 1 );
mluis 0:45c4f0364ca4 148 // Unfiltered RSSI value reading. Only takes the LSB value
mluis 0:45c4f0364ca4 149 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
mluis 0:45c4f0364ca4 150 }
mluis 0:45c4f0364ca4 151
mluis 0:45c4f0364ca4 152 Sleep( );
mluis 0:45c4f0364ca4 153
mluis 0:45c4f0364ca4 154 return rnd;
mluis 0:45c4f0364ca4 155 }
mluis 0:45c4f0364ca4 156
mluis 0:45c4f0364ca4 157 /*!
mluis 0:45c4f0364ca4 158 * Returns the known FSK bandwidth registers value
mluis 0:45c4f0364ca4 159 *
mluis 0:45c4f0364ca4 160 * \param [IN] bandwidth Bandwidth value in Hz
mluis 0:45c4f0364ca4 161 * \retval regValue Bandwidth register value.
mluis 0:45c4f0364ca4 162 */
mluis 0:45c4f0364ca4 163 uint8_t SX1272::GetFskBandwidthRegValue( uint32_t bandwidth )
mluis 0:45c4f0364ca4 164 {
mluis 0:45c4f0364ca4 165 uint8_t i;
mluis 0:45c4f0364ca4 166
mluis 0:45c4f0364ca4 167 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( FskBandwidth_t ) ) - 1; i++ )
mluis 0:45c4f0364ca4 168 {
mluis 0:45c4f0364ca4 169 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
mluis 0:45c4f0364ca4 170 {
mluis 0:45c4f0364ca4 171 return FskBandwidths[i].RegValue;
mluis 0:45c4f0364ca4 172 }
mluis 0:45c4f0364ca4 173 }
mluis 0:45c4f0364ca4 174 // ERROR: Value not found
mluis 0:45c4f0364ca4 175 while( 1 );
mluis 0:45c4f0364ca4 176 }
mluis 0:45c4f0364ca4 177
mluis 0:45c4f0364ca4 178 void SX1272::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
mluis 0:45c4f0364ca4 179 uint32_t datarate, uint8_t coderate,
mluis 0:45c4f0364ca4 180 uint32_t bandwidthAfc, uint16_t preambleLen,
mluis 0:45c4f0364ca4 181 uint16_t symbTimeout, bool fixLen,
mluis 0:45c4f0364ca4 182 uint8_t payloadLen,
mluis 0:45c4f0364ca4 183 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
mluis 0:45c4f0364ca4 184 bool iqInverted, bool rxContinuous )
mluis 0:45c4f0364ca4 185 {
mluis 0:45c4f0364ca4 186 SetModem( modem );
mluis 0:45c4f0364ca4 187
mluis 0:45c4f0364ca4 188 switch( modem )
mluis 0:45c4f0364ca4 189 {
mluis 0:45c4f0364ca4 190 case MODEM_FSK:
mluis 0:45c4f0364ca4 191 {
mluis 0:45c4f0364ca4 192 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 193 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 194 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
mluis 0:45c4f0364ca4 195 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 196 this->settings.Fsk.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 197 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 198 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 199 this->settings.Fsk.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 200 this->settings.Fsk.PreambleLen = preambleLen;
mluis 4:90bd79f1b458 201
mluis 0:45c4f0364ca4 202 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 203 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 204 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 205
mluis 0:45c4f0364ca4 206 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
mluis 0:45c4f0364ca4 207 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
mluis 0:45c4f0364ca4 208
mluis 0:45c4f0364ca4 209 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 210 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 4:90bd79f1b458 211
mluis 0:45c4f0364ca4 212 if( fixLen == 1 )
mluis 0:45c4f0364ca4 213 {
mluis 0:45c4f0364ca4 214 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 215 }
GregCr 3:5baff45eb3c5 216 else
GregCr 3:5baff45eb3c5 217 {
mluis 4:90bd79f1b458 218 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
GregCr 3:5baff45eb3c5 219 }
GregCr 3:5baff45eb3c5 220
mluis 0:45c4f0364ca4 221 Write( REG_PACKETCONFIG1,
mluis 4:90bd79f1b458 222 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 223 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 224 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 225 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 226 ( crcOn << 4 ) );
mluis 7:ea82825968d2 227 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
mluis 0:45c4f0364ca4 228 }
mluis 0:45c4f0364ca4 229 break;
mluis 0:45c4f0364ca4 230 case MODEM_LORA:
mluis 0:45c4f0364ca4 231 {
mluis 0:45c4f0364ca4 232 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 233 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 234 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 235 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 236 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 237 this->settings.LoRa.PayloadLen = payloadLen;
mluis 0:45c4f0364ca4 238 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 239 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 240 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 241 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 242 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 0:45c4f0364ca4 243
mluis 0:45c4f0364ca4 244 if( datarate > 12 )
mluis 0:45c4f0364ca4 245 {
mluis 0:45c4f0364ca4 246 datarate = 12;
mluis 0:45c4f0364ca4 247 }
mluis 0:45c4f0364ca4 248 else if( datarate < 6 )
mluis 0:45c4f0364ca4 249 {
mluis 0:45c4f0364ca4 250 datarate = 6;
mluis 0:45c4f0364ca4 251 }
mluis 4:90bd79f1b458 252
mluis 0:45c4f0364ca4 253 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 254 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 255 {
mluis 0:45c4f0364ca4 256 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 257 }
mluis 0:45c4f0364ca4 258 else
mluis 0:45c4f0364ca4 259 {
mluis 0:45c4f0364ca4 260 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 261 }
mluis 0:45c4f0364ca4 262
mluis 4:90bd79f1b458 263 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 264 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 265 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 266 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 267 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 268 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 269 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 4:90bd79f1b458 270 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 271 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 272 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 273
mluis 0:45c4f0364ca4 274 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 275 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 276 RFLR_MODEMCONFIG2_SF_MASK &
mluis 0:45c4f0364ca4 277 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
mluis 0:45c4f0364ca4 278 ( datarate << 4 ) |
mluis 0:45c4f0364ca4 279 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
mluis 0:45c4f0364ca4 280
mluis 0:45c4f0364ca4 281 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 4:90bd79f1b458 282
mluis 0:45c4f0364ca4 283 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 0:45c4f0364ca4 284 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 0:45c4f0364ca4 285
mluis 0:45c4f0364ca4 286 if( fixLen == 1 )
mluis 0:45c4f0364ca4 287 {
mluis 0:45c4f0364ca4 288 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 0:45c4f0364ca4 289 }
mluis 0:45c4f0364ca4 290
mluis 0:45c4f0364ca4 291 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 292 {
mluis 0:45c4f0364ca4 293 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 294 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 295 }
mluis 0:45c4f0364ca4 296
mluis 0:45c4f0364ca4 297 if( datarate == 6 )
mluis 0:45c4f0364ca4 298 {
mluis 4:90bd79f1b458 299 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 300 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 301 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 302 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 4:90bd79f1b458 303 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 304 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 305 }
mluis 0:45c4f0364ca4 306 else
mluis 0:45c4f0364ca4 307 {
mluis 0:45c4f0364ca4 308 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 309 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 310 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 311 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 4:90bd79f1b458 312 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 313 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 314 }
mluis 0:45c4f0364ca4 315 }
mluis 0:45c4f0364ca4 316 break;
mluis 0:45c4f0364ca4 317 }
mluis 0:45c4f0364ca4 318 }
mluis 0:45c4f0364ca4 319 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 320 /* PD_2=0 PD_2=1
mluis 0:45c4f0364ca4 321 op PaB rfo rfo
mluis 0:45c4f0364ca4 322 0 4.6 18.5 27.0
mluis 0:45c4f0364ca4 323 1 5.6 21.1 28.1
mluis 0:45c4f0364ca4 324 2 6.7 23.3 29.1
mluis 0:45c4f0364ca4 325 3 7.7 25.3 30.1
mluis 0:45c4f0364ca4 326 4 8.8 26.2 30.7
mluis 0:45c4f0364ca4 327 5 9.8 27.3 31.2
mluis 0:45c4f0364ca4 328 6 10.7 28.1 31.6
mluis 0:45c4f0364ca4 329 7 11.7 28.6 32.2
mluis 0:45c4f0364ca4 330 8 12.8 29.2 32.4
mluis 0:45c4f0364ca4 331 9 13.7 29.9 32.9
mluis 0:45c4f0364ca4 332 10 14.7 30.5 33.1
mluis 0:45c4f0364ca4 333 11 15.6 30.8 33.4
mluis 0:45c4f0364ca4 334 12 16.4 30.9 33.6
mluis 0:45c4f0364ca4 335 13 17.1 31.0 33.7
mluis 0:45c4f0364ca4 336 14 17.8 31.1 33.7
mluis 0:45c4f0364ca4 337 15 18.4 31.1 33.7
mluis 0:45c4f0364ca4 338 */
mluis 0:45c4f0364ca4 339 // txpow: 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
mluis 0:45c4f0364ca4 340 static const uint8_t PaBTable[20] = { 0, 0, 0, 0, 0, 1, 2, 3, 3, 4, 5, 6, 7, 8, 9, 10, 11, 13, 14, 15 };
mluis 0:45c4f0364ca4 341
mluis 0:45c4f0364ca4 342 // txpow: 20 21 22 23 24 25 26 27 28 29 30
mluis 0:45c4f0364ca4 343 static const uint8_t RfoTable[11] = { 1, 1, 1, 2, 2, 3, 4, 5, 6, 8, 9 };
mluis 0:45c4f0364ca4 344 #endif
mluis 0:45c4f0364ca4 345
mluis 4:90bd79f1b458 346 void SX1272::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
mluis 0:45c4f0364ca4 347 uint32_t bandwidth, uint32_t datarate,
mluis 0:45c4f0364ca4 348 uint8_t coderate, uint16_t preambleLen,
mluis 4:90bd79f1b458 349 bool fixLen, bool crcOn, bool freqHopOn,
mluis 0:45c4f0364ca4 350 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
mluis 0:45c4f0364ca4 351 {
mluis 0:45c4f0364ca4 352 uint8_t paConfig = 0;
mluis 0:45c4f0364ca4 353 uint8_t paDac = 0;
mluis 0:45c4f0364ca4 354
mluis 0:45c4f0364ca4 355 SetModem( modem );
mluis 4:90bd79f1b458 356
mluis 0:45c4f0364ca4 357 paConfig = Read( REG_PACONFIG );
mluis 0:45c4f0364ca4 358 paDac = Read( REG_PADAC );
mluis 0:45c4f0364ca4 359
mluis 0:45c4f0364ca4 360 #if defined ( TARGET_MOTE_L152RC )
mluis 0:45c4f0364ca4 361 if( power > 19 )
mluis 0:45c4f0364ca4 362 {
mluis 0:45c4f0364ca4 363 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_RFO;
mluis 0:45c4f0364ca4 364 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | RfoTable[power - 20];
mluis 0:45c4f0364ca4 365 }
mluis 0:45c4f0364ca4 366 else
mluis 0:45c4f0364ca4 367 {
mluis 0:45c4f0364ca4 368 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | RF_PACONFIG_PASELECT_PABOOST;
mluis 0:45c4f0364ca4 369 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | PaBTable[power];
mluis 0:45c4f0364ca4 370 }
mluis 0:45c4f0364ca4 371 #else
mluis 0:45c4f0364ca4 372 paConfig = ( paConfig & RF_PACONFIG_PASELECT_MASK ) | GetPaSelect( this->settings.Channel );
mluis 0:45c4f0364ca4 373
mluis 0:45c4f0364ca4 374 if( ( paConfig & RF_PACONFIG_PASELECT_PABOOST ) == RF_PACONFIG_PASELECT_PABOOST )
mluis 0:45c4f0364ca4 375 {
mluis 0:45c4f0364ca4 376 if( power > 17 )
mluis 0:45c4f0364ca4 377 {
mluis 0:45c4f0364ca4 378 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_ON;
mluis 0:45c4f0364ca4 379 }
mluis 0:45c4f0364ca4 380 else
mluis 0:45c4f0364ca4 381 {
mluis 0:45c4f0364ca4 382 paDac = ( paDac & RF_PADAC_20DBM_MASK ) | RF_PADAC_20DBM_OFF;
mluis 0:45c4f0364ca4 383 }
mluis 0:45c4f0364ca4 384 if( ( paDac & RF_PADAC_20DBM_ON ) == RF_PADAC_20DBM_ON )
mluis 0:45c4f0364ca4 385 {
mluis 0:45c4f0364ca4 386 if( power < 5 )
mluis 0:45c4f0364ca4 387 {
mluis 0:45c4f0364ca4 388 power = 5;
mluis 0:45c4f0364ca4 389 }
mluis 0:45c4f0364ca4 390 if( power > 20 )
mluis 0:45c4f0364ca4 391 {
mluis 0:45c4f0364ca4 392 power = 20;
mluis 0:45c4f0364ca4 393 }
mluis 0:45c4f0364ca4 394 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 5 ) & 0x0F );
mluis 0:45c4f0364ca4 395 }
mluis 0:45c4f0364ca4 396 else
mluis 0:45c4f0364ca4 397 {
mluis 0:45c4f0364ca4 398 if( power < 2 )
mluis 0:45c4f0364ca4 399 {
mluis 0:45c4f0364ca4 400 power = 2;
mluis 0:45c4f0364ca4 401 }
mluis 0:45c4f0364ca4 402 if( power > 17 )
mluis 0:45c4f0364ca4 403 {
mluis 0:45c4f0364ca4 404 power = 17;
mluis 0:45c4f0364ca4 405 }
mluis 0:45c4f0364ca4 406 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power - 2 ) & 0x0F );
mluis 0:45c4f0364ca4 407 }
mluis 0:45c4f0364ca4 408 }
mluis 0:45c4f0364ca4 409 else
mluis 0:45c4f0364ca4 410 {
mluis 0:45c4f0364ca4 411 if( power < -1 )
mluis 0:45c4f0364ca4 412 {
mluis 0:45c4f0364ca4 413 power = -1;
mluis 0:45c4f0364ca4 414 }
mluis 0:45c4f0364ca4 415 if( power > 14 )
mluis 0:45c4f0364ca4 416 {
mluis 0:45c4f0364ca4 417 power = 14;
mluis 0:45c4f0364ca4 418 }
mluis 0:45c4f0364ca4 419 paConfig = ( paConfig & RFLR_PACONFIG_OUTPUTPOWER_MASK ) | ( uint8_t )( ( uint16_t )( power + 1 ) & 0x0F );
mluis 0:45c4f0364ca4 420 }
mluis 0:45c4f0364ca4 421 #endif
mluis 0:45c4f0364ca4 422 Write( REG_PACONFIG, paConfig );
mluis 0:45c4f0364ca4 423 Write( REG_PADAC, paDac );
mluis 0:45c4f0364ca4 424
mluis 0:45c4f0364ca4 425 switch( modem )
mluis 0:45c4f0364ca4 426 {
mluis 0:45c4f0364ca4 427 case MODEM_FSK:
mluis 0:45c4f0364ca4 428 {
mluis 0:45c4f0364ca4 429 this->settings.Fsk.Power = power;
mluis 0:45c4f0364ca4 430 this->settings.Fsk.Fdev = fdev;
mluis 0:45c4f0364ca4 431 this->settings.Fsk.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 432 this->settings.Fsk.Datarate = datarate;
mluis 0:45c4f0364ca4 433 this->settings.Fsk.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 434 this->settings.Fsk.FixLen = fixLen;
mluis 0:45c4f0364ca4 435 this->settings.Fsk.CrcOn = crcOn;
mluis 0:45c4f0364ca4 436 this->settings.Fsk.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 437 this->settings.Fsk.TxTimeout = timeout;
mluis 4:90bd79f1b458 438
mluis 0:45c4f0364ca4 439 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
mluis 0:45c4f0364ca4 440 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
mluis 0:45c4f0364ca4 441 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
mluis 0:45c4f0364ca4 442
mluis 0:45c4f0364ca4 443 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
mluis 0:45c4f0364ca4 444 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
mluis 0:45c4f0364ca4 445 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
mluis 0:45c4f0364ca4 446
mluis 0:45c4f0364ca4 447 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 448 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
mluis 0:45c4f0364ca4 449
mluis 0:45c4f0364ca4 450 Write( REG_PACKETCONFIG1,
mluis 4:90bd79f1b458 451 ( Read( REG_PACKETCONFIG1 ) &
mluis 0:45c4f0364ca4 452 RF_PACKETCONFIG1_CRC_MASK &
mluis 0:45c4f0364ca4 453 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
mluis 0:45c4f0364ca4 454 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
mluis 0:45c4f0364ca4 455 ( crcOn << 4 ) );
mluis 7:ea82825968d2 456 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
mluis 0:45c4f0364ca4 457 }
mluis 0:45c4f0364ca4 458 break;
mluis 0:45c4f0364ca4 459 case MODEM_LORA:
mluis 0:45c4f0364ca4 460 {
mluis 0:45c4f0364ca4 461 this->settings.LoRa.Power = power;
mluis 0:45c4f0364ca4 462 this->settings.LoRa.Bandwidth = bandwidth;
mluis 0:45c4f0364ca4 463 this->settings.LoRa.Datarate = datarate;
mluis 0:45c4f0364ca4 464 this->settings.LoRa.Coderate = coderate;
mluis 0:45c4f0364ca4 465 this->settings.LoRa.PreambleLen = preambleLen;
mluis 0:45c4f0364ca4 466 this->settings.LoRa.FixLen = fixLen;
mluis 0:45c4f0364ca4 467 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 0:45c4f0364ca4 468 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 0:45c4f0364ca4 469 this->settings.LoRa.CrcOn = crcOn;
mluis 0:45c4f0364ca4 470 this->settings.LoRa.IqInverted = iqInverted;
mluis 0:45c4f0364ca4 471 this->settings.LoRa.TxTimeout = timeout;
mluis 0:45c4f0364ca4 472
mluis 0:45c4f0364ca4 473 if( datarate > 12 )
mluis 0:45c4f0364ca4 474 {
mluis 0:45c4f0364ca4 475 datarate = 12;
mluis 0:45c4f0364ca4 476 }
mluis 0:45c4f0364ca4 477 else if( datarate < 6 )
mluis 0:45c4f0364ca4 478 {
mluis 0:45c4f0364ca4 479 datarate = 6;
mluis 0:45c4f0364ca4 480 }
mluis 0:45c4f0364ca4 481 if( ( ( bandwidth == 0 ) && ( ( datarate == 11 ) || ( datarate == 12 ) ) ) ||
mluis 0:45c4f0364ca4 482 ( ( bandwidth == 1 ) && ( datarate == 12 ) ) )
mluis 0:45c4f0364ca4 483 {
mluis 0:45c4f0364ca4 484 this->settings.LoRa.LowDatarateOptimize = 0x01;
mluis 0:45c4f0364ca4 485 }
mluis 0:45c4f0364ca4 486 else
mluis 0:45c4f0364ca4 487 {
mluis 0:45c4f0364ca4 488 this->settings.LoRa.LowDatarateOptimize = 0x00;
mluis 0:45c4f0364ca4 489 }
mluis 0:45c4f0364ca4 490
mluis 0:45c4f0364ca4 491 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 492 {
mluis 0:45c4f0364ca4 493 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
mluis 0:45c4f0364ca4 494 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
mluis 0:45c4f0364ca4 495 }
mluis 0:45c4f0364ca4 496
mluis 4:90bd79f1b458 497 Write( REG_LR_MODEMCONFIG1,
mluis 0:45c4f0364ca4 498 ( Read( REG_LR_MODEMCONFIG1 ) &
mluis 0:45c4f0364ca4 499 RFLR_MODEMCONFIG1_BW_MASK &
mluis 0:45c4f0364ca4 500 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
mluis 0:45c4f0364ca4 501 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK &
mluis 0:45c4f0364ca4 502 RFLR_MODEMCONFIG1_RXPAYLOADCRC_MASK &
mluis 0:45c4f0364ca4 503 RFLR_MODEMCONFIG1_LOWDATARATEOPTIMIZE_MASK ) |
mluis 4:90bd79f1b458 504 ( bandwidth << 6 ) | ( coderate << 3 ) |
mluis 0:45c4f0364ca4 505 ( fixLen << 2 ) | ( crcOn << 1 ) |
mluis 0:45c4f0364ca4 506 this->settings.LoRa.LowDatarateOptimize );
mluis 0:45c4f0364ca4 507
mluis 0:45c4f0364ca4 508 Write( REG_LR_MODEMCONFIG2,
mluis 0:45c4f0364ca4 509 ( Read( REG_LR_MODEMCONFIG2 ) &
mluis 0:45c4f0364ca4 510 RFLR_MODEMCONFIG2_SF_MASK ) |
mluis 0:45c4f0364ca4 511 ( datarate << 4 ) );
mluis 0:45c4f0364ca4 512
mluis 4:90bd79f1b458 513
mluis 0:45c4f0364ca4 514 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
mluis 0:45c4f0364ca4 515 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 4:90bd79f1b458 516
mluis 0:45c4f0364ca4 517 if( datarate == 6 )
mluis 0:45c4f0364ca4 518 {
mluis 4:90bd79f1b458 519 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 520 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 521 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 522 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 4:90bd79f1b458 523 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 524 RFLR_DETECTIONTHRESH_SF6 );
mluis 0:45c4f0364ca4 525 }
mluis 0:45c4f0364ca4 526 else
mluis 0:45c4f0364ca4 527 {
mluis 0:45c4f0364ca4 528 Write( REG_LR_DETECTOPTIMIZE,
mluis 0:45c4f0364ca4 529 ( Read( REG_LR_DETECTOPTIMIZE ) &
mluis 0:45c4f0364ca4 530 RFLR_DETECTIONOPTIMIZE_MASK ) |
mluis 0:45c4f0364ca4 531 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 4:90bd79f1b458 532 Write( REG_LR_DETECTIONTHRESHOLD,
mluis 0:45c4f0364ca4 533 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
mluis 0:45c4f0364ca4 534 }
mluis 0:45c4f0364ca4 535 }
mluis 0:45c4f0364ca4 536 break;
mluis 0:45c4f0364ca4 537 }
mluis 0:45c4f0364ca4 538 }
mluis 0:45c4f0364ca4 539
mluis 0:45c4f0364ca4 540 double SX1272::TimeOnAir( RadioModems_t modem, uint8_t pktLen )
mluis 0:45c4f0364ca4 541 {
mluis 0:45c4f0364ca4 542 uint32_t airTime = 0;
mluis 0:45c4f0364ca4 543
mluis 0:45c4f0364ca4 544 switch( modem )
mluis 0:45c4f0364ca4 545 {
mluis 0:45c4f0364ca4 546 case MODEM_FSK:
mluis 0:45c4f0364ca4 547 {
mluis 0:45c4f0364ca4 548 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
mluis 0:45c4f0364ca4 549 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
mluis 0:45c4f0364ca4 550 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
mluis 0:45c4f0364ca4 551 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
mluis 0:45c4f0364ca4 552 pktLen +
mluis 0:45c4f0364ca4 553 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
mluis 0:45c4f0364ca4 554 this->settings.Fsk.Datarate ) * 1e6 );
mluis 0:45c4f0364ca4 555 }
mluis 0:45c4f0364ca4 556 break;
mluis 0:45c4f0364ca4 557 case MODEM_LORA:
mluis 0:45c4f0364ca4 558 {
mluis 0:45c4f0364ca4 559 double bw = 0.0;
mluis 0:45c4f0364ca4 560 switch( this->settings.LoRa.Bandwidth )
mluis 0:45c4f0364ca4 561 {
mluis 0:45c4f0364ca4 562 case 0: // 125 kHz
mluis 0:45c4f0364ca4 563 bw = 125e3;
mluis 0:45c4f0364ca4 564 break;
mluis 0:45c4f0364ca4 565 case 1: // 250 kHz
mluis 0:45c4f0364ca4 566 bw = 250e3;
mluis 0:45c4f0364ca4 567 break;
mluis 0:45c4f0364ca4 568 case 2: // 500 kHz
mluis 0:45c4f0364ca4 569 bw = 500e3;
mluis 0:45c4f0364ca4 570 break;
mluis 0:45c4f0364ca4 571 }
mluis 0:45c4f0364ca4 572
mluis 0:45c4f0364ca4 573 // Symbol rate : time for one symbol (secs)
mluis 0:45c4f0364ca4 574 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
mluis 0:45c4f0364ca4 575 double ts = 1 / rs;
mluis 0:45c4f0364ca4 576 // time of preamble
mluis 0:45c4f0364ca4 577 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
mluis 0:45c4f0364ca4 578 // Symbol length of payload and time
mluis 0:45c4f0364ca4 579 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
mluis 0:45c4f0364ca4 580 28 + 16 * this->settings.LoRa.CrcOn -
mluis 0:45c4f0364ca4 581 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
mluis 7:ea82825968d2 582 ( double )( 4 * ( this->settings.LoRa.Datarate -
mluis 7:ea82825968d2 583 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
mluis 0:45c4f0364ca4 584 ( this->settings.LoRa.Coderate + 4 );
mluis 0:45c4f0364ca4 585 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
mluis 0:45c4f0364ca4 586 double tPayload = nPayload * ts;
mluis 4:90bd79f1b458 587 // Time on air
mluis 0:45c4f0364ca4 588 double tOnAir = tPreamble + tPayload;
mluis 0:45c4f0364ca4 589 // return us secs
mluis 0:45c4f0364ca4 590 airTime = floor( tOnAir * 1e6 + 0.999 );
mluis 0:45c4f0364ca4 591 }
mluis 0:45c4f0364ca4 592 break;
mluis 0:45c4f0364ca4 593 }
mluis 0:45c4f0364ca4 594 return airTime;
mluis 0:45c4f0364ca4 595 }
mluis 0:45c4f0364ca4 596
mluis 0:45c4f0364ca4 597 void SX1272::Send( uint8_t *buffer, uint8_t size )
mluis 0:45c4f0364ca4 598 {
mluis 0:45c4f0364ca4 599 uint32_t txTimeout = 0;
mluis 0:45c4f0364ca4 600
mluis 0:45c4f0364ca4 601 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 602 {
mluis 0:45c4f0364ca4 603 case MODEM_FSK:
mluis 0:45c4f0364ca4 604 {
mluis 0:45c4f0364ca4 605 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 606 this->settings.FskPacketHandler.Size = size;
mluis 0:45c4f0364ca4 607
mluis 0:45c4f0364ca4 608 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 609 {
mluis 0:45c4f0364ca4 610 WriteFifo( ( uint8_t* )&size, 1 );
mluis 0:45c4f0364ca4 611 }
mluis 0:45c4f0364ca4 612 else
mluis 0:45c4f0364ca4 613 {
mluis 0:45c4f0364ca4 614 Write( REG_PAYLOADLENGTH, size );
mluis 4:90bd79f1b458 615 }
mluis 4:90bd79f1b458 616
mluis 0:45c4f0364ca4 617 if( ( size > 0 ) && ( size <= 64 ) )
mluis 0:45c4f0364ca4 618 {
mluis 0:45c4f0364ca4 619 this->settings.FskPacketHandler.ChunkSize = size;
mluis 0:45c4f0364ca4 620 }
mluis 0:45c4f0364ca4 621 else
mluis 0:45c4f0364ca4 622 {
GregCr 3:5baff45eb3c5 623 memcpy( rxtxBuffer, buffer, size );
mluis 0:45c4f0364ca4 624 this->settings.FskPacketHandler.ChunkSize = 32;
mluis 0:45c4f0364ca4 625 }
mluis 0:45c4f0364ca4 626
mluis 0:45c4f0364ca4 627 // Write payload buffer
mluis 0:45c4f0364ca4 628 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 629 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 630 txTimeout = this->settings.Fsk.TxTimeout;
mluis 0:45c4f0364ca4 631 }
mluis 0:45c4f0364ca4 632 break;
mluis 0:45c4f0364ca4 633 case MODEM_LORA:
mluis 0:45c4f0364ca4 634 {
mluis 0:45c4f0364ca4 635 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 636 {
mluis 0:45c4f0364ca4 637 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 0:45c4f0364ca4 638 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 639 }
mluis 0:45c4f0364ca4 640 else
mluis 0:45c4f0364ca4 641 {
mluis 0:45c4f0364ca4 642 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 643 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 4:90bd79f1b458 644 }
mluis 4:90bd79f1b458 645
mluis 0:45c4f0364ca4 646 this->settings.LoRaPacketHandler.Size = size;
mluis 0:45c4f0364ca4 647
mluis 0:45c4f0364ca4 648 // Initializes the payload size
mluis 0:45c4f0364ca4 649 Write( REG_LR_PAYLOADLENGTH, size );
mluis 0:45c4f0364ca4 650
mluis 4:90bd79f1b458 651 // Full buffer used for Tx
mluis 0:45c4f0364ca4 652 Write( REG_LR_FIFOTXBASEADDR, 0 );
mluis 0:45c4f0364ca4 653 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 654
mluis 0:45c4f0364ca4 655 // FIFO operations can not take place in Sleep mode
mluis 0:45c4f0364ca4 656 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 657 {
mluis 0:45c4f0364ca4 658 Standby( );
mluis 0:45c4f0364ca4 659 wait_ms( 1 );
mluis 0:45c4f0364ca4 660 }
mluis 0:45c4f0364ca4 661 // Write payload buffer
mluis 0:45c4f0364ca4 662 WriteFifo( buffer, size );
mluis 0:45c4f0364ca4 663 txTimeout = this->settings.LoRa.TxTimeout;
mluis 0:45c4f0364ca4 664 }
mluis 0:45c4f0364ca4 665 break;
mluis 0:45c4f0364ca4 666 }
mluis 0:45c4f0364ca4 667
mluis 0:45c4f0364ca4 668 Tx( txTimeout );
mluis 0:45c4f0364ca4 669 }
mluis 0:45c4f0364ca4 670
mluis 0:45c4f0364ca4 671 void SX1272::Sleep( void )
mluis 0:45c4f0364ca4 672 {
mluis 0:45c4f0364ca4 673 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 674 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 675
mluis 0:45c4f0364ca4 676 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 677 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 678 }
mluis 0:45c4f0364ca4 679
mluis 0:45c4f0364ca4 680 void SX1272::Standby( void )
mluis 0:45c4f0364ca4 681 {
mluis 0:45c4f0364ca4 682 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 683 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 684
mluis 0:45c4f0364ca4 685 SetOpMode( RF_OPMODE_STANDBY );
mluis 0:45c4f0364ca4 686 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 687 }
mluis 0:45c4f0364ca4 688
mluis 0:45c4f0364ca4 689 void SX1272::Rx( uint32_t timeout )
mluis 0:45c4f0364ca4 690 {
mluis 0:45c4f0364ca4 691 bool rxContinuous = false;
mluis 0:45c4f0364ca4 692
mluis 0:45c4f0364ca4 693 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 694 {
mluis 0:45c4f0364ca4 695 case MODEM_FSK:
mluis 0:45c4f0364ca4 696 {
mluis 0:45c4f0364ca4 697 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 4:90bd79f1b458 698
mluis 0:45c4f0364ca4 699 // DIO0=PayloadReady
mluis 0:45c4f0364ca4 700 // DIO1=FifoLevel
mluis 0:45c4f0364ca4 701 // DIO2=SyncAddr
mluis 0:45c4f0364ca4 702 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 703 // DIO4=Preamble
mluis 0:45c4f0364ca4 704 // DIO5=ModeReady
mluis 0:45c4f0364ca4 705 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 3:5baff45eb3c5 706 RF_DIOMAPPING1_DIO1_MASK &
mluis 0:45c4f0364ca4 707 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 0:45c4f0364ca4 708 RF_DIOMAPPING1_DIO0_00 |
mluis 4:90bd79f1b458 709 RF_DIOMAPPING1_DIO1_00 |
mluis 0:45c4f0364ca4 710 RF_DIOMAPPING1_DIO2_11 );
mluis 4:90bd79f1b458 711
mluis 0:45c4f0364ca4 712 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 4:90bd79f1b458 713 RF_DIOMAPPING2_MAP_MASK ) |
mluis 0:45c4f0364ca4 714 RF_DIOMAPPING2_DIO4_11 |
mluis 0:45c4f0364ca4 715 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 4:90bd79f1b458 716
mluis 0:45c4f0364ca4 717 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 4:90bd79f1b458 718
mluis 4:90bd79f1b458 719 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
mluis 4:90bd79f1b458 720
mluis 0:45c4f0364ca4 721 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 722 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 723 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 724 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 725 }
mluis 0:45c4f0364ca4 726 break;
mluis 0:45c4f0364ca4 727 case MODEM_LORA:
mluis 0:45c4f0364ca4 728 {
mluis 0:45c4f0364ca4 729 if( this->settings.LoRa.IqInverted == true )
mluis 0:45c4f0364ca4 730 {
mluis 0:45c4f0364ca4 731 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 732 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
mluis 0:45c4f0364ca4 733 }
mluis 0:45c4f0364ca4 734 else
mluis 0:45c4f0364ca4 735 {
mluis 0:45c4f0364ca4 736 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 0:45c4f0364ca4 737 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 4:90bd79f1b458 738 }
mluis 4:90bd79f1b458 739
mluis 0:45c4f0364ca4 740 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 4:90bd79f1b458 741
mluis 0:45c4f0364ca4 742 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 743 {
mluis 0:45c4f0364ca4 744 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 745 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 746 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 747 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 748 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 749 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 750 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 751 RFLR_IRQFLAGS_CADDETECTED );
mluis 4:90bd79f1b458 752
mluis 0:45c4f0364ca4 753 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 754 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 755 }
mluis 0:45c4f0364ca4 756 else
mluis 0:45c4f0364ca4 757 {
mluis 0:45c4f0364ca4 758 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 759 //RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 760 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 761 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 762 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 763 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 764 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 765 RFLR_IRQFLAGS_CADDETECTED );
mluis 4:90bd79f1b458 766
mluis 0:45c4f0364ca4 767 // DIO0=RxDone
mluis 0:45c4f0364ca4 768 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
mluis 0:45c4f0364ca4 769 }
mluis 0:45c4f0364ca4 770 Write( REG_LR_FIFORXBASEADDR, 0 );
mluis 0:45c4f0364ca4 771 Write( REG_LR_FIFOADDRPTR, 0 );
mluis 0:45c4f0364ca4 772 }
mluis 0:45c4f0364ca4 773 break;
mluis 0:45c4f0364ca4 774 }
mluis 0:45c4f0364ca4 775
GregCr 3:5baff45eb3c5 776 memset( rxtxBuffer, 0, ( size_t )RX_BUFFER_SIZE );
mluis 0:45c4f0364ca4 777
mluis 0:45c4f0364ca4 778 this->settings.State = RF_RX_RUNNING;
mluis 0:45c4f0364ca4 779 if( timeout != 0 )
mluis 0:45c4f0364ca4 780 {
mluis 0:45c4f0364ca4 781 rxTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 782 }
mluis 0:45c4f0364ca4 783
mluis 0:45c4f0364ca4 784 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 785 {
mluis 0:45c4f0364ca4 786 SetOpMode( RF_OPMODE_RECEIVER );
mluis 4:90bd79f1b458 787
mluis 0:45c4f0364ca4 788 if( rxContinuous == false )
mluis 0:45c4f0364ca4 789 {
mluis 4:90bd79f1b458 790 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 4:90bd79f1b458 791 ( ( Read( REG_SYNCCONFIG ) &
mluis 4:90bd79f1b458 792 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 4:90bd79f1b458 793 1.0 ) + 10.0 ) /
mluis 4:90bd79f1b458 794 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
mluis 0:45c4f0364ca4 795 }
mluis 0:45c4f0364ca4 796 }
mluis 0:45c4f0364ca4 797 else
mluis 0:45c4f0364ca4 798 {
mluis 0:45c4f0364ca4 799 if( rxContinuous == true )
mluis 0:45c4f0364ca4 800 {
mluis 0:45c4f0364ca4 801 SetOpMode( RFLR_OPMODE_RECEIVER );
mluis 0:45c4f0364ca4 802 }
mluis 0:45c4f0364ca4 803 else
mluis 0:45c4f0364ca4 804 {
mluis 0:45c4f0364ca4 805 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
mluis 0:45c4f0364ca4 806 }
mluis 0:45c4f0364ca4 807 }
mluis 0:45c4f0364ca4 808 }
mluis 0:45c4f0364ca4 809
mluis 0:45c4f0364ca4 810 void SX1272::Tx( uint32_t timeout )
mluis 0:45c4f0364ca4 811 {
mluis 0:45c4f0364ca4 812
mluis 0:45c4f0364ca4 813 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 814 {
mluis 0:45c4f0364ca4 815 case MODEM_FSK:
mluis 0:45c4f0364ca4 816 {
mluis 0:45c4f0364ca4 817 // DIO0=PacketSent
GregCr 3:5baff45eb3c5 818 // DIO1=FifoEmpty
mluis 0:45c4f0364ca4 819 // DIO2=FifoFull
mluis 0:45c4f0364ca4 820 // DIO3=FifoEmpty
mluis 0:45c4f0364ca4 821 // DIO4=LowBat
mluis 0:45c4f0364ca4 822 // DIO5=ModeReady
mluis 0:45c4f0364ca4 823 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
mluis 4:90bd79f1b458 824 RF_DIOMAPPING1_DIO1_MASK &
mluis 4:90bd79f1b458 825 RF_DIOMAPPING1_DIO2_MASK ) |
mluis 4:90bd79f1b458 826 RF_DIOMAPPING1_DIO1_01 );
mluis 0:45c4f0364ca4 827
mluis 0:45c4f0364ca4 828 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 0:45c4f0364ca4 829 RF_DIOMAPPING2_MAP_MASK ) );
mluis 0:45c4f0364ca4 830 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 0:45c4f0364ca4 831 }
mluis 0:45c4f0364ca4 832 break;
mluis 0:45c4f0364ca4 833 case MODEM_LORA:
mluis 0:45c4f0364ca4 834 {
mluis 0:45c4f0364ca4 835 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 836 {
mluis 0:45c4f0364ca4 837 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 838 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 839 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 840 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 841 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 842 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 843 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 844 RFLR_IRQFLAGS_CADDETECTED );
mluis 4:90bd79f1b458 845
mluis 0:45c4f0364ca4 846 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 0:45c4f0364ca4 847 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
mluis 0:45c4f0364ca4 848 }
mluis 0:45c4f0364ca4 849 else
mluis 0:45c4f0364ca4 850 {
mluis 0:45c4f0364ca4 851 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 852 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 853 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 854 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 855 //RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 856 RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 857 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 0:45c4f0364ca4 858 RFLR_IRQFLAGS_CADDETECTED );
mluis 0:45c4f0364ca4 859
mluis 0:45c4f0364ca4 860 // DIO0=TxDone
mluis 0:45c4f0364ca4 861 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
mluis 0:45c4f0364ca4 862 }
mluis 0:45c4f0364ca4 863 }
mluis 0:45c4f0364ca4 864 break;
mluis 0:45c4f0364ca4 865 }
mluis 0:45c4f0364ca4 866
mluis 0:45c4f0364ca4 867 this->settings.State = RF_TX_RUNNING;
mluis 0:45c4f0364ca4 868 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 0:45c4f0364ca4 869 SetOpMode( RF_OPMODE_TRANSMITTER );
mluis 0:45c4f0364ca4 870 }
mluis 0:45c4f0364ca4 871
mluis 0:45c4f0364ca4 872 void SX1272::StartCad( void )
mluis 0:45c4f0364ca4 873 {
mluis 0:45c4f0364ca4 874 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 875 {
mluis 0:45c4f0364ca4 876 case MODEM_FSK:
mluis 0:45c4f0364ca4 877 {
mluis 4:90bd79f1b458 878
mluis 0:45c4f0364ca4 879 }
mluis 0:45c4f0364ca4 880 break;
mluis 0:45c4f0364ca4 881 case MODEM_LORA:
mluis 0:45c4f0364ca4 882 {
mluis 0:45c4f0364ca4 883 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 0:45c4f0364ca4 884 RFLR_IRQFLAGS_RXDONE |
mluis 0:45c4f0364ca4 885 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 0:45c4f0364ca4 886 RFLR_IRQFLAGS_VALIDHEADER |
mluis 0:45c4f0364ca4 887 RFLR_IRQFLAGS_TXDONE |
mluis 0:45c4f0364ca4 888 //RFLR_IRQFLAGS_CADDONE |
mluis 0:45c4f0364ca4 889 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
mluis 4:90bd79f1b458 890 //RFLR_IRQFLAGS_CADDETECTED
mluis 0:45c4f0364ca4 891 );
mluis 4:90bd79f1b458 892
mluis 0:45c4f0364ca4 893 // DIO3=CADDone
mluis 7:ea82825968d2 894 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
mluis 4:90bd79f1b458 895
mluis 0:45c4f0364ca4 896 this->settings.State = RF_CAD;
mluis 0:45c4f0364ca4 897 SetOpMode( RFLR_OPMODE_CAD );
mluis 0:45c4f0364ca4 898 }
mluis 0:45c4f0364ca4 899 break;
mluis 0:45c4f0364ca4 900 default:
mluis 0:45c4f0364ca4 901 break;
mluis 0:45c4f0364ca4 902 }
mluis 0:45c4f0364ca4 903 }
mluis 0:45c4f0364ca4 904
mluis 7:ea82825968d2 905 void SX1272::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
mluis 7:ea82825968d2 906 {
mluis 7:ea82825968d2 907 uint32_t timeout = ( uint32_t )( time * 1e6 );
mluis 7:ea82825968d2 908
mluis 7:ea82825968d2 909 SetChannel( freq );
mluis 7:ea82825968d2 910
mluis 7:ea82825968d2 911 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
mluis 7:ea82825968d2 912
mluis 7:ea82825968d2 913 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
mluis 7:ea82825968d2 914 // Disable radio interrupts
mluis 7:ea82825968d2 915 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
mluis 7:ea82825968d2 916 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
mluis 7:ea82825968d2 917
mluis 7:ea82825968d2 918 this->settings.State = RF_TX_RUNNING;
mluis 7:ea82825968d2 919 txTimeoutTimer.attach_us( this, &SX1272::OnTimeoutIrq, timeout );
mluis 7:ea82825968d2 920 SetOpMode( RF_OPMODE_TRANSMITTER );
mluis 7:ea82825968d2 921 }
mluis 7:ea82825968d2 922
mluis 0:45c4f0364ca4 923 int16_t SX1272::GetRssi( RadioModems_t modem )
mluis 0:45c4f0364ca4 924 {
mluis 0:45c4f0364ca4 925 int16_t rssi = 0;
mluis 0:45c4f0364ca4 926
mluis 0:45c4f0364ca4 927 switch( modem )
mluis 0:45c4f0364ca4 928 {
mluis 0:45c4f0364ca4 929 case MODEM_FSK:
mluis 0:45c4f0364ca4 930 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 931 break;
mluis 0:45c4f0364ca4 932 case MODEM_LORA:
mluis 0:45c4f0364ca4 933 rssi = RSSI_OFFSET + Read( REG_LR_RSSIVALUE );
mluis 0:45c4f0364ca4 934 break;
mluis 0:45c4f0364ca4 935 default:
mluis 0:45c4f0364ca4 936 rssi = -1;
mluis 0:45c4f0364ca4 937 break;
mluis 0:45c4f0364ca4 938 }
mluis 0:45c4f0364ca4 939 return rssi;
mluis 0:45c4f0364ca4 940 }
mluis 0:45c4f0364ca4 941
mluis 0:45c4f0364ca4 942 void SX1272::SetOpMode( uint8_t opMode )
mluis 0:45c4f0364ca4 943 {
ubhat 5:e90cbf646eb1 944 currentOpMode = opMode; // Update global variable
mluis 7:ea82825968d2 945
mluis 4:90bd79f1b458 946 if( opMode == RF_OPMODE_SLEEP )
mluis 0:45c4f0364ca4 947 {
mluis 4:90bd79f1b458 948 SetAntSwLowPower( true );
mluis 4:90bd79f1b458 949 }
mluis 4:90bd79f1b458 950 else
mluis 4:90bd79f1b458 951 {
mluis 4:90bd79f1b458 952 SetAntSwLowPower( false );
mluis 4:90bd79f1b458 953 if( opMode == RF_OPMODE_TRANSMITTER )
mluis 0:45c4f0364ca4 954 {
mluis 4:90bd79f1b458 955 SetAntSw( 1 );
mluis 0:45c4f0364ca4 956 }
mluis 0:45c4f0364ca4 957 else
mluis 0:45c4f0364ca4 958 {
mluis 4:90bd79f1b458 959 SetAntSw( 0 );
mluis 0:45c4f0364ca4 960 }
mluis 0:45c4f0364ca4 961 }
mluis 4:90bd79f1b458 962 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
mluis 0:45c4f0364ca4 963 }
mluis 0:45c4f0364ca4 964
mluis 0:45c4f0364ca4 965 void SX1272::SetModem( RadioModems_t modem )
mluis 0:45c4f0364ca4 966 {
mluis 0:45c4f0364ca4 967 if( this->settings.Modem == modem )
mluis 0:45c4f0364ca4 968 {
mluis 0:45c4f0364ca4 969 return;
mluis 0:45c4f0364ca4 970 }
mluis 0:45c4f0364ca4 971
mluis 0:45c4f0364ca4 972 this->settings.Modem = modem;
mluis 0:45c4f0364ca4 973 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 974 {
mluis 0:45c4f0364ca4 975 default:
mluis 0:45c4f0364ca4 976 case MODEM_FSK:
mluis 0:45c4f0364ca4 977 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 978 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 0:45c4f0364ca4 979
mluis 0:45c4f0364ca4 980 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 981 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 0:45c4f0364ca4 982 break;
mluis 0:45c4f0364ca4 983 case MODEM_LORA:
mluis 0:45c4f0364ca4 984 SetOpMode( RF_OPMODE_SLEEP );
mluis 0:45c4f0364ca4 985 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 0:45c4f0364ca4 986
mluis 0:45c4f0364ca4 987 Write( REG_DIOMAPPING1, 0x00 );
mluis 0:45c4f0364ca4 988 Write( REG_DIOMAPPING2, 0x00 );
mluis 0:45c4f0364ca4 989 break;
mluis 0:45c4f0364ca4 990 }
mluis 0:45c4f0364ca4 991 }
mluis 0:45c4f0364ca4 992
mluis 0:45c4f0364ca4 993 void SX1272::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 0:45c4f0364ca4 994 {
mluis 0:45c4f0364ca4 995 this->SetModem( modem );
mluis 0:45c4f0364ca4 996
mluis 0:45c4f0364ca4 997 switch( modem )
mluis 0:45c4f0364ca4 998 {
mluis 0:45c4f0364ca4 999 case MODEM_FSK:
mluis 0:45c4f0364ca4 1000 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1001 {
mluis 0:45c4f0364ca4 1002 this->Write( REG_PAYLOADLENGTH, max );
mluis 0:45c4f0364ca4 1003 }
mluis 0:45c4f0364ca4 1004 break;
mluis 0:45c4f0364ca4 1005 case MODEM_LORA:
mluis 0:45c4f0364ca4 1006 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 0:45c4f0364ca4 1007 break;
mluis 0:45c4f0364ca4 1008 }
mluis 0:45c4f0364ca4 1009 }
mluis 0:45c4f0364ca4 1010
mluis 0:45c4f0364ca4 1011 void SX1272::OnTimeoutIrq( void )
mluis 0:45c4f0364ca4 1012 {
mluis 0:45c4f0364ca4 1013 switch( this->settings.State )
mluis 0:45c4f0364ca4 1014 {
mluis 0:45c4f0364ca4 1015 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1016 if( this->settings.Modem == MODEM_FSK )
mluis 0:45c4f0364ca4 1017 {
mluis 0:45c4f0364ca4 1018 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1019 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1020 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1021 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1022
mluis 0:45c4f0364ca4 1023 // Clear Irqs
mluis 4:90bd79f1b458 1024 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1025 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1026 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1027 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 0:45c4f0364ca4 1028
mluis 0:45c4f0364ca4 1029 if( this->settings.Fsk.RxContinuous == true )
mluis 0:45c4f0364ca4 1030 {
mluis 0:45c4f0364ca4 1031 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1032 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 4:90bd79f1b458 1033 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 4:90bd79f1b458 1034 ( ( Read( REG_SYNCCONFIG ) &
mluis 4:90bd79f1b458 1035 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 4:90bd79f1b458 1036 1.0 ) + 10.0 ) /
mluis 4:90bd79f1b458 1037 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
mluis 0:45c4f0364ca4 1038 }
mluis 0:45c4f0364ca4 1039 else
mluis 0:45c4f0364ca4 1040 {
mluis 0:45c4f0364ca4 1041 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1042 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1043 }
mluis 0:45c4f0364ca4 1044 }
mluis 0:45c4f0364ca4 1045 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1046 {
mluis 0:45c4f0364ca4 1047 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1048 }
mluis 0:45c4f0364ca4 1049 break;
mluis 0:45c4f0364ca4 1050 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1051 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1052 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1053 {
mluis 0:45c4f0364ca4 1054 this->RadioEvents->TxTimeout( );
mluis 0:45c4f0364ca4 1055 }
mluis 0:45c4f0364ca4 1056 break;
mluis 0:45c4f0364ca4 1057 default:
mluis 0:45c4f0364ca4 1058 break;
mluis 0:45c4f0364ca4 1059 }
mluis 0:45c4f0364ca4 1060 }
mluis 0:45c4f0364ca4 1061
mluis 0:45c4f0364ca4 1062 void SX1272::OnDio0Irq( void )
mluis 0:45c4f0364ca4 1063 {
mluis 0:45c4f0364ca4 1064 volatile uint8_t irqFlags = 0;
mluis 0:45c4f0364ca4 1065
mluis 0:45c4f0364ca4 1066 switch( this->settings.State )
mluis 4:90bd79f1b458 1067 {
mluis 0:45c4f0364ca4 1068 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1069 //TimerStop( &RxTimeoutTimer );
mluis 0:45c4f0364ca4 1070 // RxDone interrupt
mluis 0:45c4f0364ca4 1071 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1072 {
mluis 0:45c4f0364ca4 1073 case MODEM_FSK:
mluis 0:45c4f0364ca4 1074 if( this->settings.Fsk.CrcOn == true )
mluis 0:45c4f0364ca4 1075 {
mluis 0:45c4f0364ca4 1076 irqFlags = Read( REG_IRQFLAGS2 );
mluis 0:45c4f0364ca4 1077 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
mluis 0:45c4f0364ca4 1078 {
mluis 0:45c4f0364ca4 1079 // Clear Irqs
mluis 4:90bd79f1b458 1080 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
mluis 0:45c4f0364ca4 1081 RF_IRQFLAGS1_PREAMBLEDETECT |
mluis 0:45c4f0364ca4 1082 RF_IRQFLAGS1_SYNCADDRESSMATCH );
mluis 0:45c4f0364ca4 1083 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 4:90bd79f1b458 1084
mluis 4:90bd79f1b458 1085 rxTimeoutTimer.detach( );
mluis 4:90bd79f1b458 1086
mluis 0:45c4f0364ca4 1087 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1088 {
mluis 4:90bd79f1b458 1089 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1090 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1091 }
mluis 0:45c4f0364ca4 1092 else
mluis 0:45c4f0364ca4 1093 {
mluis 0:45c4f0364ca4 1094 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1095 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 4:90bd79f1b458 1096 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 4:90bd79f1b458 1097 ( ( Read( REG_SYNCCONFIG ) &
mluis 4:90bd79f1b458 1098 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 4:90bd79f1b458 1099 1.0 ) + 10.0 ) /
mluis 4:90bd79f1b458 1100 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
mluis 0:45c4f0364ca4 1101 }
mluis 4:90bd79f1b458 1102
mluis 0:45c4f0364ca4 1103 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1104 {
mluis 0:45c4f0364ca4 1105 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1106 }
mluis 0:45c4f0364ca4 1107 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1108 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1109 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1110 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1111 break;
mluis 0:45c4f0364ca4 1112 }
mluis 0:45c4f0364ca4 1113 }
mluis 0:45c4f0364ca4 1114
mluis 0:45c4f0364ca4 1115 // Read received packet size
mluis 0:45c4f0364ca4 1116 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1117 {
mluis 0:45c4f0364ca4 1118 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1119 {
mluis 0:45c4f0364ca4 1120 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1121 }
mluis 0:45c4f0364ca4 1122 else
mluis 0:45c4f0364ca4 1123 {
mluis 0:45c4f0364ca4 1124 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1125 }
GregCr 3:5baff45eb3c5 1126 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1127 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1128 }
mluis 0:45c4f0364ca4 1129 else
mluis 0:45c4f0364ca4 1130 {
GregCr 3:5baff45eb3c5 1131 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1132 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1133 }
mluis 0:45c4f0364ca4 1134
mluis 4:90bd79f1b458 1135 rxTimeoutTimer.detach( );
mluis 4:90bd79f1b458 1136
mluis 0:45c4f0364ca4 1137 if( this->settings.Fsk.RxContinuous == false )
mluis 0:45c4f0364ca4 1138 {
mluis 0:45c4f0364ca4 1139 this->settings.State = RF_IDLE;
mluis 4:90bd79f1b458 1140 rxTimeoutSyncWord.detach( );
mluis 0:45c4f0364ca4 1141 }
mluis 0:45c4f0364ca4 1142 else
mluis 0:45c4f0364ca4 1143 {
mluis 0:45c4f0364ca4 1144 // Continuous mode restart Rx chain
mluis 0:45c4f0364ca4 1145 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
mluis 4:90bd79f1b458 1146 rxTimeoutSyncWord.attach_us( this, &SX1272::OnTimeoutIrq, ceil( ( 8.0 * ( this->settings.Fsk.PreambleLen +
mluis 4:90bd79f1b458 1147 ( ( Read( REG_SYNCCONFIG ) &
mluis 4:90bd79f1b458 1148 ~RF_SYNCCONFIG_SYNCSIZE_MASK ) +
mluis 4:90bd79f1b458 1149 1.0 ) + 10.0 ) /
mluis 4:90bd79f1b458 1150 ( double )this->settings.Fsk.Datarate ) * 1e6 ) + 4000 );
mluis 0:45c4f0364ca4 1151 }
mluis 0:45c4f0364ca4 1152
mluis 0:45c4f0364ca4 1153 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1154 {
mluis 4:90bd79f1b458 1155 this->RadioEvents->RxDone( rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 4:90bd79f1b458 1156 }
mluis 0:45c4f0364ca4 1157 this->settings.FskPacketHandler.PreambleDetected = false;
mluis 0:45c4f0364ca4 1158 this->settings.FskPacketHandler.SyncWordDetected = false;
mluis 0:45c4f0364ca4 1159 this->settings.FskPacketHandler.NbBytes = 0;
mluis 0:45c4f0364ca4 1160 this->settings.FskPacketHandler.Size = 0;
mluis 0:45c4f0364ca4 1161 break;
mluis 0:45c4f0364ca4 1162 case MODEM_LORA:
mluis 0:45c4f0364ca4 1163 {
mluis 0:45c4f0364ca4 1164 int8_t snr = 0;
mluis 0:45c4f0364ca4 1165
mluis 0:45c4f0364ca4 1166 // Clear Irq
mluis 0:45c4f0364ca4 1167 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
mluis 0:45c4f0364ca4 1168
mluis 0:45c4f0364ca4 1169 irqFlags = Read( REG_LR_IRQFLAGS );
mluis 0:45c4f0364ca4 1170 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
mluis 0:45c4f0364ca4 1171 {
mluis 0:45c4f0364ca4 1172 // Clear Irq
mluis 0:45c4f0364ca4 1173 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
mluis 0:45c4f0364ca4 1174
mluis 0:45c4f0364ca4 1175 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1176 {
mluis 0:45c4f0364ca4 1177 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1178 }
mluis 0:45c4f0364ca4 1179 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1180
mluis 0:45c4f0364ca4 1181 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxError != NULL ) )
mluis 0:45c4f0364ca4 1182 {
mluis 0:45c4f0364ca4 1183 this->RadioEvents->RxError( );
mluis 0:45c4f0364ca4 1184 }
mluis 0:45c4f0364ca4 1185 break;
mluis 0:45c4f0364ca4 1186 }
mluis 0:45c4f0364ca4 1187
mluis 0:45c4f0364ca4 1188 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
mluis 0:45c4f0364ca4 1189 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
mluis 0:45c4f0364ca4 1190 {
mluis 0:45c4f0364ca4 1191 // Invert and divide by 4
mluis 0:45c4f0364ca4 1192 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1193 snr = -snr;
mluis 0:45c4f0364ca4 1194 }
mluis 0:45c4f0364ca4 1195 else
mluis 0:45c4f0364ca4 1196 {
mluis 0:45c4f0364ca4 1197 // Divide by 4
mluis 0:45c4f0364ca4 1198 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
mluis 0:45c4f0364ca4 1199 }
mluis 0:45c4f0364ca4 1200
mluis 0:45c4f0364ca4 1201 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 0:45c4f0364ca4 1202 if( snr < 0 )
mluis 0:45c4f0364ca4 1203 {
mluis 0:45c4f0364ca4 1204 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 ) +
mluis 0:45c4f0364ca4 1205 snr;
mluis 0:45c4f0364ca4 1206 }
mluis 0:45c4f0364ca4 1207 else
mluis 4:90bd79f1b458 1208 {
mluis 0:45c4f0364ca4 1209 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET + rssi + ( rssi >> 4 );
mluis 0:45c4f0364ca4 1210 }
mluis 0:45c4f0364ca4 1211
mluis 0:45c4f0364ca4 1212 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 3:5baff45eb3c5 1213 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 4:90bd79f1b458 1214
mluis 0:45c4f0364ca4 1215 if( this->settings.LoRa.RxContinuous == false )
mluis 0:45c4f0364ca4 1216 {
mluis 0:45c4f0364ca4 1217 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1218 }
mluis 0:45c4f0364ca4 1219 rxTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1220
mluis 0:45c4f0364ca4 1221 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxDone != NULL ) )
mluis 0:45c4f0364ca4 1222 {
GregCr 3:5baff45eb3c5 1223 this->RadioEvents->RxDone( rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
mluis 0:45c4f0364ca4 1224 }
mluis 0:45c4f0364ca4 1225 }
mluis 0:45c4f0364ca4 1226 break;
mluis 0:45c4f0364ca4 1227 default:
mluis 0:45c4f0364ca4 1228 break;
mluis 0:45c4f0364ca4 1229 }
mluis 0:45c4f0364ca4 1230 break;
mluis 0:45c4f0364ca4 1231 case RF_TX_RUNNING:
mluis 4:90bd79f1b458 1232 txTimeoutTimer.detach( );
mluis 0:45c4f0364ca4 1233 // TxDone interrupt
mluis 0:45c4f0364ca4 1234 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1235 {
mluis 0:45c4f0364ca4 1236 case MODEM_LORA:
mluis 0:45c4f0364ca4 1237 // Clear Irq
mluis 0:45c4f0364ca4 1238 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
mluis 0:45c4f0364ca4 1239 // Intentional fall through
mluis 0:45c4f0364ca4 1240 case MODEM_FSK:
mluis 0:45c4f0364ca4 1241 default:
mluis 0:45c4f0364ca4 1242 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1243 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->TxDone != NULL ) )
mluis 0:45c4f0364ca4 1244 {
mluis 0:45c4f0364ca4 1245 this->RadioEvents->TxDone( );
mluis 4:90bd79f1b458 1246 }
mluis 0:45c4f0364ca4 1247 break;
mluis 0:45c4f0364ca4 1248 }
mluis 0:45c4f0364ca4 1249 break;
mluis 0:45c4f0364ca4 1250 default:
mluis 0:45c4f0364ca4 1251 break;
mluis 0:45c4f0364ca4 1252 }
mluis 0:45c4f0364ca4 1253 }
mluis 0:45c4f0364ca4 1254
mluis 0:45c4f0364ca4 1255 void SX1272::OnDio1Irq( void )
mluis 0:45c4f0364ca4 1256 {
mluis 0:45c4f0364ca4 1257 switch( this->settings.State )
mluis 4:90bd79f1b458 1258 {
mluis 0:45c4f0364ca4 1259 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1260 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1261 {
mluis 0:45c4f0364ca4 1262 case MODEM_FSK:
mluis 0:45c4f0364ca4 1263 // FifoLevel interrupt
mluis 0:45c4f0364ca4 1264 // Read received packet size
mluis 0:45c4f0364ca4 1265 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
mluis 0:45c4f0364ca4 1266 {
mluis 0:45c4f0364ca4 1267 if( this->settings.Fsk.FixLen == false )
mluis 0:45c4f0364ca4 1268 {
mluis 0:45c4f0364ca4 1269 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
mluis 0:45c4f0364ca4 1270 }
mluis 0:45c4f0364ca4 1271 else
mluis 0:45c4f0364ca4 1272 {
mluis 0:45c4f0364ca4 1273 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
mluis 0:45c4f0364ca4 1274 }
mluis 0:45c4f0364ca4 1275 }
mluis 0:45c4f0364ca4 1276
mluis 0:45c4f0364ca4 1277 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
mluis 0:45c4f0364ca4 1278 {
GregCr 3:5baff45eb3c5 1279 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
mluis 0:45c4f0364ca4 1280 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
mluis 0:45c4f0364ca4 1281 }
mluis 0:45c4f0364ca4 1282 else
mluis 0:45c4f0364ca4 1283 {
GregCr 3:5baff45eb3c5 1284 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1285 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1286 }
mluis 0:45c4f0364ca4 1287 break;
mluis 0:45c4f0364ca4 1288 case MODEM_LORA:
mluis 0:45c4f0364ca4 1289 // Sync time out
mluis 0:45c4f0364ca4 1290 rxTimeoutTimer.detach( );
mluis 7:ea82825968d2 1291 // Clear Irq
mluis 7:ea82825968d2 1292 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
mluis 7:ea82825968d2 1293
mluis 0:45c4f0364ca4 1294 this->settings.State = RF_IDLE;
mluis 0:45c4f0364ca4 1295 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->RxTimeout != NULL ) )
mluis 0:45c4f0364ca4 1296 {
mluis 0:45c4f0364ca4 1297 this->RadioEvents->RxTimeout( );
mluis 0:45c4f0364ca4 1298 }
mluis 0:45c4f0364ca4 1299 break;
mluis 0:45c4f0364ca4 1300 default:
mluis 0:45c4f0364ca4 1301 break;
mluis 0:45c4f0364ca4 1302 }
mluis 0:45c4f0364ca4 1303 break;
mluis 0:45c4f0364ca4 1304 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1305 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1306 {
mluis 0:45c4f0364ca4 1307 case MODEM_FSK:
mluis 4:90bd79f1b458 1308 // FifoEmpty interrupt
mluis 0:45c4f0364ca4 1309 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
mluis 0:45c4f0364ca4 1310 {
GregCr 3:5baff45eb3c5 1311 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
mluis 0:45c4f0364ca4 1312 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
mluis 0:45c4f0364ca4 1313 }
mluis 4:90bd79f1b458 1314 else
mluis 0:45c4f0364ca4 1315 {
mluis 0:45c4f0364ca4 1316 // Write the last chunk of data
GregCr 3:5baff45eb3c5 1317 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
mluis 0:45c4f0364ca4 1318 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
mluis 0:45c4f0364ca4 1319 }
mluis 0:45c4f0364ca4 1320 break;
mluis 0:45c4f0364ca4 1321 case MODEM_LORA:
mluis 0:45c4f0364ca4 1322 break;
mluis 0:45c4f0364ca4 1323 default:
mluis 0:45c4f0364ca4 1324 break;
mluis 0:45c4f0364ca4 1325 }
mluis 0:45c4f0364ca4 1326 break;
mluis 0:45c4f0364ca4 1327 default:
mluis 0:45c4f0364ca4 1328 break;
mluis 0:45c4f0364ca4 1329 }
mluis 0:45c4f0364ca4 1330 }
mluis 0:45c4f0364ca4 1331
mluis 0:45c4f0364ca4 1332 void SX1272::OnDio2Irq( void )
mluis 0:45c4f0364ca4 1333 {
mluis 0:45c4f0364ca4 1334 switch( this->settings.State )
mluis 4:90bd79f1b458 1335 {
mluis 0:45c4f0364ca4 1336 case RF_RX_RUNNING:
mluis 0:45c4f0364ca4 1337 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1338 {
mluis 0:45c4f0364ca4 1339 case MODEM_FSK:
mluis 0:45c4f0364ca4 1340 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
mluis 0:45c4f0364ca4 1341 {
mluis 0:45c4f0364ca4 1342 rxTimeoutSyncWord.detach( );
mluis 4:90bd79f1b458 1343
mluis 0:45c4f0364ca4 1344 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 4:90bd79f1b458 1345
mluis 0:45c4f0364ca4 1346 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
mluis 0:45c4f0364ca4 1347
mluis 0:45c4f0364ca4 1348 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
mluis 0:45c4f0364ca4 1349 ( uint16_t )Read( REG_AFCLSB ) ) *
mluis 0:45c4f0364ca4 1350 ( double )FREQ_STEP;
mluis 0:45c4f0364ca4 1351 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
mluis 0:45c4f0364ca4 1352 }
mluis 0:45c4f0364ca4 1353 break;
mluis 0:45c4f0364ca4 1354 case MODEM_LORA:
mluis 0:45c4f0364ca4 1355 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1356 {
mluis 0:45c4f0364ca4 1357 // Clear Irq
mluis 0:45c4f0364ca4 1358 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 4:90bd79f1b458 1359
mluis 0:45c4f0364ca4 1360 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1361 {
mluis 0:45c4f0364ca4 1362 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1363 }
mluis 0:45c4f0364ca4 1364 }
mluis 0:45c4f0364ca4 1365 break;
mluis 0:45c4f0364ca4 1366 default:
mluis 0:45c4f0364ca4 1367 break;
mluis 0:45c4f0364ca4 1368 }
mluis 0:45c4f0364ca4 1369 break;
mluis 0:45c4f0364ca4 1370 case RF_TX_RUNNING:
mluis 0:45c4f0364ca4 1371 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1372 {
mluis 0:45c4f0364ca4 1373 case MODEM_FSK:
mluis 0:45c4f0364ca4 1374 break;
mluis 0:45c4f0364ca4 1375 case MODEM_LORA:
mluis 0:45c4f0364ca4 1376 if( this->settings.LoRa.FreqHopOn == true )
mluis 0:45c4f0364ca4 1377 {
mluis 0:45c4f0364ca4 1378 // Clear Irq
mluis 0:45c4f0364ca4 1379 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 4:90bd79f1b458 1380
mluis 0:45c4f0364ca4 1381 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->FhssChangeChannel != NULL ) )
mluis 0:45c4f0364ca4 1382 {
mluis 0:45c4f0364ca4 1383 this->RadioEvents->FhssChangeChannel( ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 0:45c4f0364ca4 1384 }
mluis 0:45c4f0364ca4 1385 }
mluis 0:45c4f0364ca4 1386 break;
mluis 0:45c4f0364ca4 1387 default:
mluis 0:45c4f0364ca4 1388 break;
mluis 0:45c4f0364ca4 1389 }
mluis 0:45c4f0364ca4 1390 break;
mluis 0:45c4f0364ca4 1391 default:
mluis 0:45c4f0364ca4 1392 break;
mluis 0:45c4f0364ca4 1393 }
mluis 0:45c4f0364ca4 1394 }
mluis 0:45c4f0364ca4 1395
mluis 0:45c4f0364ca4 1396 void SX1272::OnDio3Irq( void )
mluis 0:45c4f0364ca4 1397 {
mluis 0:45c4f0364ca4 1398 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1399 {
mluis 0:45c4f0364ca4 1400 case MODEM_FSK:
mluis 0:45c4f0364ca4 1401 break;
mluis 0:45c4f0364ca4 1402 case MODEM_LORA:
mluis 0:45c4f0364ca4 1403 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 0:45c4f0364ca4 1404 {
mluis 0:45c4f0364ca4 1405 // Clear Irq
mluis 0:45c4f0364ca4 1406 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1407 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1408 {
mluis 0:45c4f0364ca4 1409 this->RadioEvents->CadDone( true );
mluis 0:45c4f0364ca4 1410 }
mluis 0:45c4f0364ca4 1411 }
mluis 0:45c4f0364ca4 1412 else
mluis 4:90bd79f1b458 1413 {
mluis 0:45c4f0364ca4 1414 // Clear Irq
mluis 0:45c4f0364ca4 1415 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
mluis 0:45c4f0364ca4 1416 if( ( this->RadioEvents != NULL ) && ( this->RadioEvents->CadDone != NULL ) )
mluis 0:45c4f0364ca4 1417 {
mluis 0:45c4f0364ca4 1418 this->RadioEvents->CadDone( false );
mluis 0:45c4f0364ca4 1419 }
mluis 0:45c4f0364ca4 1420 }
mluis 0:45c4f0364ca4 1421 break;
mluis 0:45c4f0364ca4 1422 default:
mluis 0:45c4f0364ca4 1423 break;
mluis 0:45c4f0364ca4 1424 }
mluis 0:45c4f0364ca4 1425 }
mluis 0:45c4f0364ca4 1426
mluis 0:45c4f0364ca4 1427 void SX1272::OnDio4Irq( void )
mluis 0:45c4f0364ca4 1428 {
mluis 0:45c4f0364ca4 1429 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1430 {
mluis 0:45c4f0364ca4 1431 case MODEM_FSK:
mluis 0:45c4f0364ca4 1432 {
mluis 0:45c4f0364ca4 1433 if( this->settings.FskPacketHandler.PreambleDetected == false )
mluis 0:45c4f0364ca4 1434 {
mluis 0:45c4f0364ca4 1435 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 4:90bd79f1b458 1436 }
mluis 0:45c4f0364ca4 1437 }
mluis 0:45c4f0364ca4 1438 break;
mluis 0:45c4f0364ca4 1439 case MODEM_LORA:
mluis 0:45c4f0364ca4 1440 break;
mluis 0:45c4f0364ca4 1441 default:
mluis 0:45c4f0364ca4 1442 break;
mluis 0:45c4f0364ca4 1443 }
mluis 0:45c4f0364ca4 1444 }
mluis 0:45c4f0364ca4 1445
mluis 0:45c4f0364ca4 1446 void SX1272::OnDio5Irq( void )
mluis 0:45c4f0364ca4 1447 {
mluis 0:45c4f0364ca4 1448 switch( this->settings.Modem )
mluis 0:45c4f0364ca4 1449 {
mluis 0:45c4f0364ca4 1450 case MODEM_FSK:
mluis 0:45c4f0364ca4 1451 break;
mluis 0:45c4f0364ca4 1452 case MODEM_LORA:
mluis 0:45c4f0364ca4 1453 break;
mluis 0:45c4f0364ca4 1454 default:
mluis 0:45c4f0364ca4 1455 break;
mluis 0:45c4f0364ca4 1456 }
mluis 0:45c4f0364ca4 1457 }