ADE120x Library Files
ADE120x.cpp@1:2eb9d6296ec3, 2019-10-03 (annotated)
- Committer:
- mlambe
- Date:
- Thu Oct 03 15:05:59 2019 +0000
- Revision:
- 1:2eb9d6296ec3
- Parent:
- 0:952a6272c495
- Child:
- 2:f9a986799375
Added comments
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mlambe | 1:2eb9d6296ec3 | 1 | /** |
mlambe | 1:2eb9d6296ec3 | 2 | * @file ADE120x.cpp |
mlambe | 1:2eb9d6296ec3 | 3 | * @brief ADE120x library. This file contains all ADE120x library functions. |
mlambe | 1:2eb9d6296ec3 | 4 | * @version V0.0.1 |
mlambe | 1:2eb9d6296ec3 | 5 | * @author ADI |
mlambe | 1:2eb9d6296ec3 | 6 | * @date October 2019 |
mlambe | 1:2eb9d6296ec3 | 7 | * @par Revision History: |
mlambe | 1:2eb9d6296ec3 | 8 | * |
mlambe | 1:2eb9d6296ec3 | 9 | * Copyright (c) 2017-2019 Analog Devices, Inc. All Rights Reserved. |
mlambe | 1:2eb9d6296ec3 | 10 | * |
mlambe | 1:2eb9d6296ec3 | 11 | * This software is proprietary to Analog Devices, Inc. and its licensors. |
mlambe | 1:2eb9d6296ec3 | 12 | * By using this software you agree to the terms of the associated |
mlambe | 1:2eb9d6296ec3 | 13 | * Analog Devices Software License Agreement. |
mlambe | 1:2eb9d6296ec3 | 14 | **/ |
mlambe | 1:2eb9d6296ec3 | 15 | |
mlambe | 1:2eb9d6296ec3 | 16 | #include "ADE120x.h" |
mlambe | 1:2eb9d6296ec3 | 17 | |
mlambe | 1:2eb9d6296ec3 | 18 | /*! \mainpage ADE120x Library Introduction |
mlambe | 1:2eb9d6296ec3 | 19 | * |
mlambe | 1:2eb9d6296ec3 | 20 | * # Introduction |
mlambe | 1:2eb9d6296ec3 | 21 | * |
mlambe | 1:2eb9d6296ec3 | 22 | * The documentation is for ADE120x library and examples. |
mlambe | 1:2eb9d6296ec3 | 23 | * TBD |
mlambe | 1:2eb9d6296ec3 | 24 | */ |
mlambe | 1:2eb9d6296ec3 | 25 | |
mlambe | 1:2eb9d6296ec3 | 26 | |
mlambe | 1:2eb9d6296ec3 | 27 | /* Constructor for ADE120x; intializes the SPI interface only */ |
mlambe | 1:2eb9d6296ec3 | 28 | ADE120x::ADE120x( PinName mosi,PinName miso,PinName sclk,PinName cs) : spi_(mosi, miso, sclk), nCS_(cs) { |
mlambe | 1:2eb9d6296ec3 | 29 | //5MHz, allowed up to 10MHz |
mlambe | 1:2eb9d6296ec3 | 30 | nCS_ = 1; |
mlambe | 1:2eb9d6296ec3 | 31 | spi_.frequency(5000000); |
mlambe | 1:2eb9d6296ec3 | 32 | spi_.format(16, 3); |
mlambe | 1:2eb9d6296ec3 | 33 | } |
mlambe | 1:2eb9d6296ec3 | 34 | |
mlambe | 1:2eb9d6296ec3 | 35 | /** |
mlambe | 1:2eb9d6296ec3 | 36 | @brief Write to ADE120x register through SPI. |
mlambe | 1:2eb9d6296ec3 | 37 | @param addr: The address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 38 | @param reg_addr: register address |
mlambe | 1:2eb9d6296ec3 | 39 | @param data: register data |
mlambe | 1:2eb9d6296ec3 | 40 | @return received data. |
mlambe | 1:2eb9d6296ec3 | 41 | **/ |
mlambe | 1:2eb9d6296ec3 | 42 | void ADE120x::WriteReg(uint8_t addr, uint32_t reg_addr, uint32_t data) |
mlambe | 1:2eb9d6296ec3 | 43 | { |
mlambe | 1:2eb9d6296ec3 | 44 | int cmd; |
mlambe | 1:2eb9d6296ec3 | 45 | nCS_ = 0; |
mlambe | 1:2eb9d6296ec3 | 46 | wait_us(1); |
mlambe | 1:2eb9d6296ec3 | 47 | cmd = reg_addr * 0x0010 + addr; //R/nW bit set to 0 |
mlambe | 1:2eb9d6296ec3 | 48 | spi_.write(cmd); |
mlambe | 1:2eb9d6296ec3 | 49 | spi_.write(data); |
mlambe | 1:2eb9d6296ec3 | 50 | wait_us(1); |
mlambe | 1:2eb9d6296ec3 | 51 | nCS_ = 1; |
mlambe | 1:2eb9d6296ec3 | 52 | } |
mlambe | 1:2eb9d6296ec3 | 53 | /** |
mlambe | 1:2eb9d6296ec3 | 54 | @brief Read ADE120x register through SPI. |
mlambe | 1:2eb9d6296ec3 | 55 | @param addr: The address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 56 | @param reg_addr: register address |
mlambe | 1:2eb9d6296ec3 | 57 | @return received data. |
mlambe | 1:2eb9d6296ec3 | 58 | **/ |
mlambe | 1:2eb9d6296ec3 | 59 | uint32_t ADE120x::ReadReg(uint8_t addr, uint32_t reg_addr) |
mlambe | 1:2eb9d6296ec3 | 60 | { |
mlambe | 1:2eb9d6296ec3 | 61 | int cmd; |
mlambe | 1:2eb9d6296ec3 | 62 | int resp; |
mlambe | 1:2eb9d6296ec3 | 63 | nCS_ = 0; |
mlambe | 1:2eb9d6296ec3 | 64 | wait_us(1); |
mlambe | 1:2eb9d6296ec3 | 65 | //cmd = REG*0x0020 + 0x18 + addr; //R/nW bit set to 0 |
mlambe | 1:2eb9d6296ec3 | 66 | cmd = reg_addr*0x0010 + 0x8 + addr; |
mlambe | 1:2eb9d6296ec3 | 67 | spi_.write(cmd); |
mlambe | 1:2eb9d6296ec3 | 68 | resp = spi_.write(0xFFFF); |
mlambe | 1:2eb9d6296ec3 | 69 | wait_us(1); |
mlambe | 1:2eb9d6296ec3 | 70 | nCS_ = 1; |
mlambe | 1:2eb9d6296ec3 | 71 | return resp; |
mlambe | 1:2eb9d6296ec3 | 72 | } |
mlambe | 1:2eb9d6296ec3 | 73 | |
mlambe | 1:2eb9d6296ec3 | 74 | /** |
mlambe | 1:2eb9d6296ec3 | 75 | @brief Reset ADE120x. |
mlambe | 1:2eb9d6296ec3 | 76 | @param addr: The address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 77 | @return return none. |
mlambe | 1:2eb9d6296ec3 | 78 | **/ |
mlambe | 1:2eb9d6296ec3 | 79 | uint8_t ADE120x::Reset(uint8_t addr) |
mlambe | 1:2eb9d6296ec3 | 80 | { |
mlambe | 1:2eb9d6296ec3 | 81 | UnLock(addr); |
mlambe | 1:2eb9d6296ec3 | 82 | WriteReg(addr, REG_CTRL, 0x0010); |
mlambe | 1:2eb9d6296ec3 | 83 | //wait until RSTDONE bit is set |
mlambe | 1:2eb9d6296ec3 | 84 | while ((ReadReg(addr, REG_INT_STATUS) & INTSRC_RSTDONE) == 0) |
mlambe | 1:2eb9d6296ec3 | 85 | { } |
mlambe | 1:2eb9d6296ec3 | 86 | return 0; |
mlambe | 1:2eb9d6296ec3 | 87 | } |
mlambe | 1:2eb9d6296ec3 | 88 | |
mlambe | 1:2eb9d6296ec3 | 89 | /** |
mlambe | 1:2eb9d6296ec3 | 90 | @brief Read back device ID. |
mlambe | 1:2eb9d6296ec3 | 91 | @param addr: The address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 92 | @return device ID. |
mlambe | 1:2eb9d6296ec3 | 93 | **/ |
mlambe | 1:2eb9d6296ec3 | 94 | uint16_t ADE120x::GetDevID(uint8_t addr) |
mlambe | 1:2eb9d6296ec3 | 95 | { |
mlambe | 1:2eb9d6296ec3 | 96 | uint16_t response; |
mlambe | 1:2eb9d6296ec3 | 97 | response = ReadReg(addr, REG_CTRL); |
mlambe | 1:2eb9d6296ec3 | 98 | return response; |
mlambe | 1:2eb9d6296ec3 | 99 | } |
mlambe | 1:2eb9d6296ec3 | 100 | |
mlambe | 1:2eb9d6296ec3 | 101 | /** |
mlambe | 1:2eb9d6296ec3 | 102 | @brief Lock ADE120x. When device is locked all register writes are ignored |
mlambe | 1:2eb9d6296ec3 | 103 | @param addr: The address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 104 | @return none. |
mlambe | 1:2eb9d6296ec3 | 105 | **/ |
mlambe | 1:2eb9d6296ec3 | 106 | void ADE120x::Lock(uint8_t addr) |
mlambe | 1:2eb9d6296ec3 | 107 | { |
mlambe | 1:2eb9d6296ec3 | 108 | WriteReg(addr, REG_LOCK, DEV_LOCK); |
mlambe | 1:2eb9d6296ec3 | 109 | } |
mlambe | 1:2eb9d6296ec3 | 110 | |
mlambe | 1:2eb9d6296ec3 | 111 | /** |
mlambe | 1:2eb9d6296ec3 | 112 | @brief Unlock ADE120x. Unlock device before writing to registers |
mlambe | 1:2eb9d6296ec3 | 113 | @param addr: The address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 114 | @return none. |
mlambe | 1:2eb9d6296ec3 | 115 | **/ |
mlambe | 1:2eb9d6296ec3 | 116 | void ADE120x::UnLock(uint8_t addr) |
mlambe | 1:2eb9d6296ec3 | 117 | { |
mlambe | 1:2eb9d6296ec3 | 118 | WriteReg(addr, REG_LOCK, DEV_UNLOCK); |
mlambe | 1:2eb9d6296ec3 | 119 | wait_us(100); |
mlambe | 1:2eb9d6296ec3 | 120 | } |
mlambe | 1:2eb9d6296ec3 | 121 | |
mlambe | 1:2eb9d6296ec3 | 122 | /** |
mlambe | 1:2eb9d6296ec3 | 123 | @brief Configure interrupt. |
mlambe | 1:2eb9d6296ec3 | 124 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 125 | @param IntSrcSel: Interrupt source to enable. |
mlambe | 1:2eb9d6296ec3 | 126 | @return Status. |
mlambe | 1:2eb9d6296ec3 | 127 | **/ |
mlambe | 1:2eb9d6296ec3 | 128 | void ADE120x::SetInt(uint8_t addr, uint16_t IntSrcSel) |
mlambe | 1:2eb9d6296ec3 | 129 | { |
mlambe | 1:2eb9d6296ec3 | 130 | WriteReg(addr, REG_MASK, IntSrcSel); |
mlambe | 1:2eb9d6296ec3 | 131 | } |
mlambe | 1:2eb9d6296ec3 | 132 | /** |
mlambe | 1:2eb9d6296ec3 | 133 | @brief Clear interrupt status. |
mlambe | 1:2eb9d6296ec3 | 134 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 135 | @param IntSrcSel: Interrupt source to clear. |
mlambe | 1:2eb9d6296ec3 | 136 | @return Status. |
mlambe | 1:2eb9d6296ec3 | 137 | **/ |
mlambe | 1:2eb9d6296ec3 | 138 | void ADE120x::ClearIntStatus(uint8_t addr, uint16_t IntSrcSel) |
mlambe | 1:2eb9d6296ec3 | 139 | { |
mlambe | 1:2eb9d6296ec3 | 140 | WriteReg(addr, REG_INT_STATUS, IntSrcSel); |
mlambe | 1:2eb9d6296ec3 | 141 | } |
mlambe | 1:2eb9d6296ec3 | 142 | |
mlambe | 1:2eb9d6296ec3 | 143 | /** |
mlambe | 1:2eb9d6296ec3 | 144 | @brief Get Interrupt Status. |
mlambe | 1:2eb9d6296ec3 | 145 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 146 | @return Status. |
mlambe | 1:2eb9d6296ec3 | 147 | **/ |
mlambe | 1:2eb9d6296ec3 | 148 | uint16_t ADE120x::GetIntStatus(uint8_t addr) |
mlambe | 1:2eb9d6296ec3 | 149 | { |
mlambe | 1:2eb9d6296ec3 | 150 | uint16_t status; |
mlambe | 1:2eb9d6296ec3 | 151 | status = ReadReg(addr, REG_INT_STATUS); |
mlambe | 1:2eb9d6296ec3 | 152 | return status; |
mlambe | 1:2eb9d6296ec3 | 153 | } |
mlambe | 1:2eb9d6296ec3 | 154 | |
mlambe | 1:2eb9d6296ec3 | 155 | /** |
mlambe | 1:2eb9d6296ec3 | 156 | @brief Configure ADC PGA gain. |
mlambe | 1:2eb9d6296ec3 | 157 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 158 | @param Gain: Select from the following |
mlambe | 1:2eb9d6296ec3 | 159 | ADCPGA_1, ADCPGA_2, ADCPGA_5, ADCPGA_10. |
mlambe | 1:2eb9d6296ec3 | 160 | @return Status. |
mlambe | 1:2eb9d6296ec3 | 161 | **/ |
mlambe | 1:2eb9d6296ec3 | 162 | void ADE120x::SetPgaGain(uint8_t addr, uint16_t gain) |
mlambe | 1:2eb9d6296ec3 | 163 | { |
mlambe | 1:2eb9d6296ec3 | 164 | UnLock(addr); |
mlambe | 1:2eb9d6296ec3 | 165 | WriteReg(addr, REG_PGA_GAIN, gain); |
mlambe | 1:2eb9d6296ec3 | 166 | Lock(addr); |
mlambe | 1:2eb9d6296ec3 | 167 | } |
mlambe | 1:2eb9d6296ec3 | 168 | /** |
mlambe | 1:2eb9d6296ec3 | 169 | @brief Read ADC data. |
mlambe | 1:2eb9d6296ec3 | 170 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 171 | @param src: ADC source, ADC_DECIMATOR to select decimator output. ADC_RAW for raw output. |
mlambe | 1:2eb9d6296ec3 | 172 | @return Status. |
mlambe | 1:2eb9d6296ec3 | 173 | **/ |
mlambe | 1:2eb9d6296ec3 | 174 | uint8_t ADE120x::ReadADC(uint8_t addr, int8_t src) |
mlambe | 1:2eb9d6296ec3 | 175 | { |
mlambe | 1:2eb9d6296ec3 | 176 | uint8_t code; |
mlambe | 1:2eb9d6296ec3 | 177 | if(src == ADC_DECIMATOR) |
mlambe | 1:2eb9d6296ec3 | 178 | code = ReadReg(addr, REG_ADCDEC); |
mlambe | 1:2eb9d6296ec3 | 179 | else |
mlambe | 1:2eb9d6296ec3 | 180 | code = ReadReg(addr, REG_ADC); |
mlambe | 1:2eb9d6296ec3 | 181 | return code; |
mlambe | 1:2eb9d6296ec3 | 182 | } |
mlambe | 1:2eb9d6296ec3 | 183 | |
mlambe | 1:2eb9d6296ec3 | 184 | |
mlambe | 1:2eb9d6296ec3 | 185 | /** |
mlambe | 1:2eb9d6296ec3 | 186 | @brief Convert ADC Code to voltage. |
mlambe | 1:2eb9d6296ec3 | 187 | @param ADCCode: ADC code. |
mlambe | 1:2eb9d6296ec3 | 188 | @param ADCPga: the actual 1.82V reference voltage. |
mlambe | 1:2eb9d6296ec3 | 189 | @param VOLTAGE_Gain: THe gain factor set by the external resistor divider network |
mlambe | 1:2eb9d6296ec3 | 190 | @return Voltage in volt. |
mlambe | 1:2eb9d6296ec3 | 191 | **/ |
mlambe | 1:2eb9d6296ec3 | 192 | float ADE120x::ADCCode2Volt(uint32_t ADCCode, uint8_t ADCPga, float VOLTAGE_Gain) |
mlambe | 1:2eb9d6296ec3 | 193 | { |
mlambe | 1:2eb9d6296ec3 | 194 | float tmp = 0.0; |
mlambe | 1:2eb9d6296ec3 | 195 | float fVolt = 0.0; |
mlambe | 1:2eb9d6296ec3 | 196 | tmp = (ADCCode&0xFF); |
mlambe | 1:2eb9d6296ec3 | 197 | tmp = 1.25 * (tmp/255) / VOLTAGE_Gain; |
mlambe | 1:2eb9d6296ec3 | 198 | switch(ADCPga) |
mlambe | 1:2eb9d6296ec3 | 199 | { |
mlambe | 1:2eb9d6296ec3 | 200 | case ADCPGA_1: |
mlambe | 1:2eb9d6296ec3 | 201 | fVolt = tmp; |
mlambe | 1:2eb9d6296ec3 | 202 | break; |
mlambe | 1:2eb9d6296ec3 | 203 | case ADCPGA_2: |
mlambe | 1:2eb9d6296ec3 | 204 | fVolt = tmp/2; |
mlambe | 1:2eb9d6296ec3 | 205 | break; |
mlambe | 1:2eb9d6296ec3 | 206 | case ADCPGA_5: |
mlambe | 1:2eb9d6296ec3 | 207 | fVolt = tmp/5; |
mlambe | 1:2eb9d6296ec3 | 208 | break; |
mlambe | 1:2eb9d6296ec3 | 209 | case ADCPGA_10: |
mlambe | 1:2eb9d6296ec3 | 210 | fVolt = tmp/10; |
mlambe | 1:2eb9d6296ec3 | 211 | break; |
mlambe | 1:2eb9d6296ec3 | 212 | default:break; |
mlambe | 1:2eb9d6296ec3 | 213 | } |
mlambe | 1:2eb9d6296ec3 | 214 | return fVolt; |
mlambe | 1:2eb9d6296ec3 | 215 | } |
mlambe | 1:2eb9d6296ec3 | 216 | |
mlambe | 1:2eb9d6296ec3 | 217 | /** |
mlambe | 1:2eb9d6296ec3 | 218 | @brief Set binary Threshold. |
mlambe | 1:2eb9d6296ec3 | 219 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 220 | @param thresh: Threshold value. |
mlambe | 1:2eb9d6296ec3 | 221 | @return none. |
mlambe | 1:2eb9d6296ec3 | 222 | **/ |
mlambe | 1:2eb9d6296ec3 | 223 | void ADE120x::SetBinaryThresh(uint8_t addr, uint16_t thresh) |
mlambe | 1:2eb9d6296ec3 | 224 | { |
mlambe | 1:2eb9d6296ec3 | 225 | WriteReg(addr, REG_BIN_THR, thresh); |
mlambe | 1:2eb9d6296ec3 | 226 | } |
mlambe | 1:2eb9d6296ec3 | 227 | |
mlambe | 1:2eb9d6296ec3 | 228 | /** |
mlambe | 1:2eb9d6296ec3 | 229 | @brief Calculate threshold register code. |
mlambe | 1:2eb9d6296ec3 | 230 | @param V_Thresh: Threshold value in volts. |
mlambe | 1:2eb9d6296ec3 | 231 | @param ADCPga: PGA gain value |
mlambe | 1:2eb9d6296ec3 | 232 | @param V_Gain: Gain of external voltage divider circuit |
mlambe | 1:2eb9d6296ec3 | 233 | @return 0. |
mlambe | 1:2eb9d6296ec3 | 234 | **/ |
mlambe | 1:2eb9d6296ec3 | 235 | uint8_t ADE120x::CalculateThreshCode(float V_Thresh, uint8_t ADCPga, float V_Gain) |
mlambe | 1:2eb9d6296ec3 | 236 | { |
mlambe | 1:2eb9d6296ec3 | 237 | uint8_t code; |
mlambe | 1:2eb9d6296ec3 | 238 | float tmp; |
mlambe | 1:2eb9d6296ec3 | 239 | tmp = (V_Thresh * V_Gain * ADCPga * 255)/1.25 + 0.5; |
mlambe | 1:2eb9d6296ec3 | 240 | code = (uint8_t)tmp; |
mlambe | 1:2eb9d6296ec3 | 241 | return code; |
mlambe | 1:2eb9d6296ec3 | 242 | } |
mlambe | 1:2eb9d6296ec3 | 243 | |
mlambe | 1:2eb9d6296ec3 | 244 | /** |
mlambe | 1:2eb9d6296ec3 | 245 | @brief Configure threshold fvoltage for BIN, WARNA, WARNB and WARNC. |
mlambe | 1:2eb9d6296ec3 | 246 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 247 | @param pCfg: Pointer to structure |
mlambe | 1:2eb9d6296ec3 | 248 | @return 0. |
mlambe | 1:2eb9d6296ec3 | 249 | **/ |
mlambe | 1:2eb9d6296ec3 | 250 | uint8_t ADE120x::ThresholdCfg(uint8_t addr, THRESHCfg_Type *pCfg) |
mlambe | 1:2eb9d6296ec3 | 251 | { |
mlambe | 1:2eb9d6296ec3 | 252 | uint8_t Thresh_H, Thresh_L; |
mlambe | 1:2eb9d6296ec3 | 253 | uint16_t bin_ctrl, tmp; |
mlambe | 1:2eb9d6296ec3 | 254 | UnLock(addr); |
mlambe | 1:2eb9d6296ec3 | 255 | Thresh_H = CalculateThreshCode(pCfg->BIN_HighThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 256 | Thresh_L = CalculateThreshCode(pCfg->BIN_LowThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 257 | WriteReg(addr, REG_BIN_THR, (Thresh_L<<8)|Thresh_H); |
mlambe | 1:2eb9d6296ec3 | 258 | |
mlambe | 1:2eb9d6296ec3 | 259 | Thresh_H = CalculateThreshCode(pCfg->WARNA_HighThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 260 | Thresh_L = CalculateThreshCode(pCfg->WARNA_LowThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 261 | WriteReg(addr, REG_WARNA_THR , (Thresh_L<<8)|Thresh_H); |
mlambe | 1:2eb9d6296ec3 | 262 | |
mlambe | 1:2eb9d6296ec3 | 263 | Thresh_H = CalculateThreshCode(pCfg->WARNB_HighThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 264 | Thresh_L = CalculateThreshCode(pCfg->WARNB_LowThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 265 | WriteReg(addr, REG_WARNB_THR, (Thresh_L<<8)|Thresh_H); |
mlambe | 1:2eb9d6296ec3 | 266 | |
mlambe | 1:2eb9d6296ec3 | 267 | Thresh_H = CalculateThreshCode(pCfg->WARNC_HighThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 268 | Thresh_L = CalculateThreshCode(pCfg->WARNC_LowThresh, pCfg->ADCPga, pCfg->VGain); |
mlambe | 1:2eb9d6296ec3 | 269 | WriteReg(addr, REG_WARNC_THR, (Thresh_L<<8)|Thresh_H); |
mlambe | 1:2eb9d6296ec3 | 270 | |
mlambe | 1:2eb9d6296ec3 | 271 | bin_ctrl = (pCfg->BIN_Mode<<6)|(pCfg->WARNA_Mode<<8)|(pCfg->WARNB_Mode<<10)|(pCfg->WARNC_Mode<<12); |
mlambe | 1:2eb9d6296ec3 | 272 | tmp = ReadReg(addr, REG_BIN_CTRL); |
mlambe | 1:2eb9d6296ec3 | 273 | tmp &= 0xFFFF&~(0xFF<<6); |
mlambe | 1:2eb9d6296ec3 | 274 | WriteReg(addr, REG_BIN_CTRL, tmp|bin_ctrl); |
mlambe | 1:2eb9d6296ec3 | 275 | tmp = ReadReg(addr, REG_BIN_CTRL); |
mlambe | 1:2eb9d6296ec3 | 276 | return 0; |
mlambe | 1:2eb9d6296ec3 | 277 | } |
mlambe | 1:2eb9d6296ec3 | 278 | /** |
mlambe | 1:2eb9d6296ec3 | 279 | @brief Configure programmable load. |
mlambe | 1:2eb9d6296ec3 | 280 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 281 | @param pCfg: Pointer to structure |
mlambe | 1:2eb9d6296ec3 | 282 | @return 0. |
mlambe | 1:2eb9d6296ec3 | 283 | **/ |
mlambe | 1:2eb9d6296ec3 | 284 | uint8_t ADE120x::ProgrammableLoadCfg(uint8_t addr, PLOADCfg_Type *pCfg) |
mlambe | 1:2eb9d6296ec3 | 285 | { |
mlambe | 1:2eb9d6296ec3 | 286 | float tmp; |
mlambe | 1:2eb9d6296ec3 | 287 | WriteReg(addr, REG_PL_CTRL, pCfg->mode); |
mlambe | 1:2eb9d6296ec3 | 288 | if(pCfg->mode == LOW_IDLE) |
mlambe | 1:2eb9d6296ec3 | 289 | WriteReg(addr, REG_PL_RISE_THR, |
mlambe | 1:2eb9d6296ec3 | 290 | CalculateThreshCode(pCfg->VoltThresh, pCfg->ADCPga, pCfg->VGain)); |
mlambe | 1:2eb9d6296ec3 | 291 | |
mlambe | 1:2eb9d6296ec3 | 292 | tmp = (pCfg->HighCurrent/0.2) + 0.5f; /* add 0.5 to round up */ |
mlambe | 1:2eb9d6296ec3 | 293 | WriteReg(addr, REG_PL_HIGH_CODE, (uint16_t)tmp); |
mlambe | 1:2eb9d6296ec3 | 294 | |
mlambe | 1:2eb9d6296ec3 | 295 | tmp = (pCfg->HighTime/10) + 0.5f; |
mlambe | 1:2eb9d6296ec3 | 296 | WriteReg(addr, REG_PL_HIGH_TIME, (uint16_t)tmp); |
mlambe | 1:2eb9d6296ec3 | 297 | |
mlambe | 1:2eb9d6296ec3 | 298 | tmp = (pCfg->LowCurrent/0.1) + 0.5f; |
mlambe | 1:2eb9d6296ec3 | 299 | WriteReg(addr, REG_PL_LOW_CODE, (uint16_t)tmp); |
mlambe | 1:2eb9d6296ec3 | 300 | |
mlambe | 1:2eb9d6296ec3 | 301 | if(pCfg->enable == CH1_Enable) |
mlambe | 1:2eb9d6296ec3 | 302 | WriteReg(addr, REG_PL_EN, PL_CH1_ENABLE); |
mlambe | 1:2eb9d6296ec3 | 303 | if(pCfg->enable == CH2_Enable) |
mlambe | 1:2eb9d6296ec3 | 304 | WriteReg(addr, REG_PL_EN, PL_CH2_ENABLE); |
mlambe | 1:2eb9d6296ec3 | 305 | if(pCfg->enable == CH1_CH2_Enable) |
mlambe | 1:2eb9d6296ec3 | 306 | WriteReg(addr, REG_PL_EN, PL_CH2_ENABLE|PL_CH1_ENABLE); |
mlambe | 1:2eb9d6296ec3 | 307 | if(pCfg->enable == CH1_Disable) |
mlambe | 1:2eb9d6296ec3 | 308 | WriteReg(addr, REG_PL_EN, 0); |
mlambe | 1:2eb9d6296ec3 | 309 | |
mlambe | 1:2eb9d6296ec3 | 310 | return 0; |
mlambe | 1:2eb9d6296ec3 | 311 | } |
mlambe | 1:2eb9d6296ec3 | 312 | |
mlambe | 1:2eb9d6296ec3 | 313 | /** |
mlambe | 1:2eb9d6296ec3 | 314 | @brief Configure Energy Meter. |
mlambe | 1:2eb9d6296ec3 | 315 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 316 | @param pCfg: Pointer to structure |
mlambe | 1:2eb9d6296ec3 | 317 | @return 0. |
mlambe | 1:2eb9d6296ec3 | 318 | **/ |
mlambe | 1:2eb9d6296ec3 | 319 | uint8_t ADE120x::EnergyMtrCfg(uint8_t addr, EnergyMtrCfg_Type *pCfg) |
mlambe | 1:2eb9d6296ec3 | 320 | { |
mlambe | 1:2eb9d6296ec3 | 321 | float pulse_enrgy, AvgADCCode, tmp; |
mlambe | 1:2eb9d6296ec3 | 322 | uint16_t reg_val, reg_mtr_ctrl; |
mlambe | 1:2eb9d6296ec3 | 323 | AvgADCCode = (255*pCfg->WorkingVoltage*pCfg->VGain*pCfg->ADCPga)/1.25; |
mlambe | 1:2eb9d6296ec3 | 324 | /* Step 1: Calculate pulse energy in Jules: (Pulse time * Working Current * Voltage) / 1000 */ |
mlambe | 1:2eb9d6296ec3 | 325 | pulse_enrgy = (pCfg->PulseMagnitude * pCfg->FET_Energy * pCfg->PulseTime)/1000; |
mlambe | 1:2eb9d6296ec3 | 326 | |
mlambe | 1:2eb9d6296ec3 | 327 | /* Step 2: Calculate ENERGY_MTR register value: */ |
mlambe | 1:2eb9d6296ec3 | 328 | tmp = (AvgADCCode * (pCfg->PulseTime/1000))/(128 * pCfg->SampleRate)+0.5; |
mlambe | 1:2eb9d6296ec3 | 329 | reg_val = (uint16_t)tmp; |
mlambe | 1:2eb9d6296ec3 | 330 | WriteReg(addr, REG_EGY_MTR_THR, reg_val); |
mlambe | 1:2eb9d6296ec3 | 331 | |
mlambe | 1:2eb9d6296ec3 | 332 | |
mlambe | 1:2eb9d6296ec3 | 333 | reg_mtr_ctrl = (pCfg->Cooldown_Decr<<8)|pCfg->Cooldown_Sec|(pCfg->Cooldown_TimeStep<<4)|(pCfg->Ov_Scale<<6); |
mlambe | 1:2eb9d6296ec3 | 334 | WriteReg(addr, REG_EGY_MTR_CTRL, reg_mtr_ctrl); |
mlambe | 1:2eb9d6296ec3 | 335 | |
mlambe | 1:2eb9d6296ec3 | 336 | return 1; |
mlambe | 1:2eb9d6296ec3 | 337 | } |
mlambe | 1:2eb9d6296ec3 | 338 | |
mlambe | 1:2eb9d6296ec3 | 339 | /** |
mlambe | 1:2eb9d6296ec3 | 340 | @brief Read all ADE120xregisters. |
mlambe | 1:2eb9d6296ec3 | 341 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 342 | @return 0. |
mlambe | 1:2eb9d6296ec3 | 343 | **/ |
mlambe | 1:2eb9d6296ec3 | 344 | void ADE120x::GetRegisterData(uint8_t addr, RegisterData_Type *pBuff) |
mlambe | 1:2eb9d6296ec3 | 345 | { |
mlambe | 1:2eb9d6296ec3 | 346 | uint16_t reg_addr[] = { |
mlambe | 1:2eb9d6296ec3 | 347 | REG_CTRL, |
mlambe | 1:2eb9d6296ec3 | 348 | REG_BIN_CTRL, |
mlambe | 1:2eb9d6296ec3 | 349 | REG_BIN_THR, |
mlambe | 1:2eb9d6296ec3 | 350 | REG_WARNA_THR, |
mlambe | 1:2eb9d6296ec3 | 351 | REG_WARNB_THR, |
mlambe | 1:2eb9d6296ec3 | 352 | REG_WARNC_THR, |
mlambe | 1:2eb9d6296ec3 | 353 | REG_BIN_FILTER, |
mlambe | 1:2eb9d6296ec3 | 354 | REG_WARNA_FILTER, |
mlambe | 1:2eb9d6296ec3 | 355 | REG_WARNB_FILTER, |
mlambe | 1:2eb9d6296ec3 | 356 | REG_WARNC_FILTER, |
mlambe | 1:2eb9d6296ec3 | 357 | REG_MASK, |
mlambe | 1:2eb9d6296ec3 | 358 | REG_PL_CTRL, |
mlambe | 1:2eb9d6296ec3 | 359 | REG_PL_RISE_THR, |
mlambe | 1:2eb9d6296ec3 | 360 | REG_PL_LOW_CODE, |
mlambe | 1:2eb9d6296ec3 | 361 | REG_PL_HIGH_CODE, |
mlambe | 1:2eb9d6296ec3 | 362 | REG_PL_HIGH_TIME, |
mlambe | 1:2eb9d6296ec3 | 363 | REG_EGY_MTR_CTRL, |
mlambe | 1:2eb9d6296ec3 | 364 | REG_EGY_MTR_THR, |
mlambe | 1:2eb9d6296ec3 | 365 | REG_PL_EN, |
mlambe | 1:2eb9d6296ec3 | 366 | REG_PGA_GAIN}; |
mlambe | 1:2eb9d6296ec3 | 367 | |
mlambe | 1:2eb9d6296ec3 | 368 | uint8_t reg_addr_size = sizeof(reg_addr)/sizeof(*reg_addr); |
mlambe | 1:2eb9d6296ec3 | 369 | uint8_t i = 0; |
mlambe | 1:2eb9d6296ec3 | 370 | while(i<reg_addr_size) |
mlambe | 1:2eb9d6296ec3 | 371 | { |
mlambe | 1:2eb9d6296ec3 | 372 | pBuff[i].reg_addr = reg_addr[i]; |
mlambe | 1:2eb9d6296ec3 | 373 | pBuff[i].reg_data = ReadReg(addr, reg_addr[i]); |
mlambe | 1:2eb9d6296ec3 | 374 | i++; |
mlambe | 1:2eb9d6296ec3 | 375 | wait_us(1000); |
mlambe | 1:2eb9d6296ec3 | 376 | } |
mlambe | 1:2eb9d6296ec3 | 377 | } |
mlambe | 1:2eb9d6296ec3 | 378 | /** |
mlambe | 1:2eb9d6296ec3 | 379 | @brief Configure Device with default settings. |
mlambe | 1:2eb9d6296ec3 | 380 | @param addr: the address of the ADE120x device. |
mlambe | 1:2eb9d6296ec3 | 381 | @return 0. |
mlambe | 1:2eb9d6296ec3 | 382 | **/ |
mlambe | 1:2eb9d6296ec3 | 383 | uint8_t ADE120x::DefaultConfig(uint8_t addr) |
mlambe | 1:2eb9d6296ec3 | 384 | { |
mlambe | 1:2eb9d6296ec3 | 385 | /** Array defined for configuration ***/ |
mlambe | 1:2eb9d6296ec3 | 386 | uint16_t config[] = { |
mlambe | 1:2eb9d6296ec3 | 387 | //REG_CTRL, 0x04, |
mlambe | 1:2eb9d6296ec3 | 388 | // REG_BIN_CTRL, 0x0000, |
mlambe | 1:2eb9d6296ec3 | 389 | REG_BIN_THR, 0x757d, // fail |
mlambe | 1:2eb9d6296ec3 | 390 | REG_WARNA_THR, 0xcccc, |
mlambe | 1:2eb9d6296ec3 | 391 | REG_WARNB_THR, 0x5a88, |
mlambe | 1:2eb9d6296ec3 | 392 | REG_WARNC_THR, 0x2d2d, |
mlambe | 1:2eb9d6296ec3 | 393 | REG_BIN_FILTER, BIN_FILTER_VAL, //fail using this register to validate against unintended resets in the DOUT validate |
mlambe | 1:2eb9d6296ec3 | 394 | REG_WARNA_FILTER, 0x80fa, |
mlambe | 1:2eb9d6296ec3 | 395 | REG_WARNB_FILTER, 0x80fa, |
mlambe | 1:2eb9d6296ec3 | 396 | REG_WARNC_FILTER, 0x80fa, |
mlambe | 1:2eb9d6296ec3 | 397 | REG_MASK, 0x4000, |
mlambe | 1:2eb9d6296ec3 | 398 | REG_PL_CTRL, 0x0000, |
mlambe | 1:2eb9d6296ec3 | 399 | REG_PL_RISE_THR, 0x007d, // fail |
mlambe | 1:2eb9d6296ec3 | 400 | REG_PL_LOW_CODE, 0x001e, |
mlambe | 1:2eb9d6296ec3 | 401 | REG_PL_HIGH_CODE, 0x000f, // fail |
mlambe | 1:2eb9d6296ec3 | 402 | REG_PL_HIGH_TIME, 0x0001, // fail |
mlambe | 1:2eb9d6296ec3 | 403 | REG_EGY_MTR_CTRL, 0x0505, |
mlambe | 1:2eb9d6296ec3 | 404 | REG_EGY_MTR_THR, 0x9ba3, |
mlambe | 1:2eb9d6296ec3 | 405 | REG_PL_EN, 0xC000, //fail |
mlambe | 1:2eb9d6296ec3 | 406 | REG_PGA_GAIN, ADCPGA_10 }; //fail |
mlambe | 1:2eb9d6296ec3 | 407 | |
mlambe | 1:2eb9d6296ec3 | 408 | uint8_t config_size = sizeof(config)/sizeof(*config); |
mlambe | 1:2eb9d6296ec3 | 409 | uint8_t i = 0; |
mlambe | 1:2eb9d6296ec3 | 410 | int resp; |
mlambe | 1:2eb9d6296ec3 | 411 | wait_us(10000); |
mlambe | 1:2eb9d6296ec3 | 412 | while(i<config_size-1) |
mlambe | 1:2eb9d6296ec3 | 413 | { |
mlambe | 1:2eb9d6296ec3 | 414 | WriteReg(addr, config[i], config[i+1]); |
mlambe | 1:2eb9d6296ec3 | 415 | resp = ReadReg(addr, config[i]); |
mlambe | 1:2eb9d6296ec3 | 416 | if (resp != config[i+1]) |
mlambe | 1:2eb9d6296ec3 | 417 | { |
mlambe | 1:2eb9d6296ec3 | 418 | printf("Register 0x%x write failed: Expected: 0x%x , Actual: 0x%x \r\n", config[i], config[i+1], resp); |
mlambe | 1:2eb9d6296ec3 | 419 | return 255; |
mlambe | 1:2eb9d6296ec3 | 420 | } |
mlambe | 1:2eb9d6296ec3 | 421 | // printf("Register 0x%x write passed: Expected: 0x%x , Actual: 0x%x \r\n", config[i], config[i+1], resp); |
mlambe | 1:2eb9d6296ec3 | 422 | i+=2; |
mlambe | 1:2eb9d6296ec3 | 423 | wait_us(1000); |
mlambe | 1:2eb9d6296ec3 | 424 | } |
mlambe | 1:2eb9d6296ec3 | 425 | return 0; |
mlambe | 1:2eb9d6296ec3 | 426 | } |