File content as of revision 36:20bb47609697:

/* Copyright (c) 2010-2011 mbed.org, MIT License
*
* Permission is hereby granted, free of charge, to any person obtaining a copy of this software
* and associated documentation files (the "Software"), to deal in the Software without
* restriction, including without limitation the rights to use, copy, modify, merge, publish,
* distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in all copies or
* substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
* BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
* DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
*/

#define DEBUG_PRINTF // enable debug messages

#if defined(TARGET_KL25Z) | defined(TARGET_KL46Z) | defined(TARGET_K20D5M) | defined(TARGET_K64F)

#include "USBHAL.h"

USBHAL * USBHAL::instance;

// DMAERR has occurred
bool USB_DMAERR;


// Perform an operation atomically, by disabling interrupts.  This must be
// used for any test-and-write operations in non-IRQ code, including increment, 
// decrement, bit set, and bit clear, on variables that are also written 
// within the IRQ handler.  (Operations *within* the IRQ handler don't require 
// this, because regular code can't interrupt an interrupt handler.)  This
// applies in particular to 'epComplete' and 'Data1' updates, which are both
// bit vectors that are written with bitwise test-and-set operations in
// regular code and IRQ code.
#define atomic(_stm_) \
    do { \
        NVIC_DisableIRQ(USB0_IRQn); \
        _stm_; \
        NVIC_EnableIRQ(USB0_IRQn); \
    } while (0)
    
// Convert physical endpoint number to register bit
#define EP(endpoint) (1<<(endpoint))

// Convert physical to logical
#define PHY_TO_LOG(endpoint)    ((endpoint)>>1)

// Get endpoint direction
#define IN_EP(endpoint)     ((endpoint) & 1U ? true : false)
#define OUT_EP(endpoint)    ((endpoint) & 1U ? false : true)

#define BD_OWN_MASK        (1<<7)
#define BD_DATA01_MASK     (1<<6)
#define BD_KEEP_MASK       (1<<5)
#define BD_NINC_MASK       (1<<4)
#define BD_DTS_MASK        (1<<3)
#define BD_STALL_MASK      (1<<2)

// Endpoint direction.  These are relative to the DEVICE:
//  TX = transmit to host = "IN" endpoint
//  RX = receive from host = "OUT" endpoint
#define TX    1
#define RX    0

// Double-buffering parity.  The hadrware SIE has a native double-buffering
// scheme that switches back and forth between two buffers per physical
// endpoint.  We disable this feature, so we effectively only use the EVEN
// buffer for each endpoint.
#define EVEN  0
#define ODD   1

// Get the BDT index for a given endpoint.  'logep' is the LOGICAL
// endpoint number; 'dir' is the direction (TX or RX).  'odd' is
// the even/odd flag for the hardware SIE double-buffering system.
// We don't actually use the double-buffering scheme, so this is 
// essentially always EVEN throughout this implementation.
#define EP_BDT_IDX(logep, dir, odd) ((4*(logep)) + (2*(dir)) + (1*(odd)))

// get the BDT for a given physical endpoint
#define PEP_BDT_IDX(phyep, odd) ((2*(phyep)) + (1*(odd)))


#define SETUP_TOKEN    0x0D
#define IN_TOKEN       0x09
#define OUT_TOKEN      0x01
#define TOK_PID(idx)   ((bdt[idx].info >> 2) & 0x0F)


// Buffer Descriptor Table (BDT) entry.
//
// Each entry in the BDT uses this structure, which is defined by
// the hardware SIE design.
typedef struct BDT {
    uint8_t   info;       // BD[0:7]
    uint8_t   dummy;      // RSVD: BD[8:15]
    uint16_t  byte_count; // BD[16:25] reserved[26:31]
    uint32_t  address;    // Addr
} __attribute__((packed)) BDT;

// The Buffer Descriptor Table is a contiguous block of BDT entries
// (the structure defined above).  This memory block is shared with the
// hardware SIE to coordinate endpoint send/receive operations between
// the hardware and software.  The hardware design requires this block
// to be aligned on a 512-byte boundary; the location of the block is
// stored in a hardware register that we set during initialization.
//
// There are:
//    * 16 logical endpoints (EP0 .. EP15)
//    * 2 physical endpoints (TX and RX) per logical endpoint -> 32 physical endpoints
//    * two buffers per physical endpoint (EVEN and ODD) -> 64 buffers
__attribute__((__aligned__(512))) BDT bdt[NUMBER_OF_PHYSICAL_ENDPOINTS * 2];
uint8_t *endpoint_buffer[NUMBER_OF_PHYSICAL_ENDPOINTS];

// The device's bus address
static uint8_t addr = 0;

// Mode flag indicating that the host will send our assigned address
// in the next packet
static uint8_t set_addr = 0;

// Private data per endpoint
struct {
    uint32_t flags;     // flags set when endpoint was realized
    uint32_t bufsiz;    // allocated buffer size for endpoint
} epInfo[NUMBER_OF_PHYSICAL_ENDPOINTS];
    
// Endpoint completion flags (one for each endpoint).  These flags indicate
// if the last read or write operation on an endpoint has completed.  It's 
// set by the interrupt handler when a send/receive operation completes.  
// It's cleared by the readResult/writeResult routines on retrieving a 
// successful completion status.
static volatile int epComplete = 0;

// clear a completion flag - must be atomic, as the IRQ also manipulates these bits
#define clear_completion(endpoint) atomic(epComplete &= ~EP(endpoint))
    
// Endpoint ready flags.  These indicate if endpoints are ready for their
// next read/write operations.  These are set by the read/write routines, and
// cleared by the interrupt handler.  Note that these are *almost* the
// inverse of the epComplete flags, but not quite: these aren't consumed by
// the status checks.  We use these to check for clearance before starting an
// operation, to make sure we're not attempting to overwrite a previous one.
static volatile uint32_t epReady = 0;

// set/clear the ready flag - must be atomic, as the IRQ also manipulates these bits
#define set_ready(endpoint) atomic(epReady |= EP(endpoint))
#define clear_ready(endpoint) atomic(epReady &= ~EP(endpoint))


// DATA0/DATA1 setting for next packet on each endpoint
static volatile uint32_t Data1  = 0x55555555;

// set DATA0/DATA1 status on an endpoint (must be atomic as the IRQ handler
// manpulates this variable)
#define set_DATA0(endpoint) atomic(Data1 &= ~EP(endpoint))
#define set_DATA1(endpoint) atomic(Data1 |= EP(endpoint))
#define toggle_DATA01(endpoint) atomic(Data1 ^= EP(endpoint))

static uint32_t frameNumber() {
    return((USB0->FRMNUML | (USB0->FRMNUMH << 8)) & 0x07FF);
}

uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
    return 0;
}

USBHAL::USBHAL(void) 
{
    // Disable IRQ
    NVIC_DisableIRQ(USB0_IRQn);

#if defined(TARGET_K64F)
    MPU->CESR=0;
#endif
    // fill in callback array
    epCallback[0] = &USBHAL::EP1_OUT_callback;
    epCallback[1] = &USBHAL::EP1_IN_callback;
    epCallback[2] = &USBHAL::EP2_OUT_callback;
    epCallback[3] = &USBHAL::EP2_IN_callback;
    epCallback[4] = &USBHAL::EP3_OUT_callback;
    epCallback[5] = &USBHAL::EP3_IN_callback;
    epCallback[6] = &USBHAL::EP4_OUT_callback;
    epCallback[7] = &USBHAL::EP4_IN_callback;
    epCallback[8] = &USBHAL::EP5_OUT_callback;
    epCallback[9] = &USBHAL::EP5_IN_callback;
    epCallback[10] = &USBHAL::EP6_OUT_callback;
    epCallback[11] = &USBHAL::EP6_IN_callback;
    epCallback[12] = &USBHAL::EP7_OUT_callback;
    epCallback[13] = &USBHAL::EP7_IN_callback;
    epCallback[14] = &USBHAL::EP8_OUT_callback;
    epCallback[15] = &USBHAL::EP8_IN_callback;
    epCallback[16] = &USBHAL::EP9_OUT_callback;
    epCallback[17] = &USBHAL::EP9_IN_callback;
    epCallback[18] = &USBHAL::EP10_OUT_callback;
    epCallback[19] = &USBHAL::EP10_IN_callback;
    epCallback[20] = &USBHAL::EP11_OUT_callback;
    epCallback[21] = &USBHAL::EP11_IN_callback;
    epCallback[22] = &USBHAL::EP12_OUT_callback;
    epCallback[23] = &USBHAL::EP12_IN_callback;
    epCallback[24] = &USBHAL::EP13_OUT_callback;
    epCallback[25] = &USBHAL::EP13_IN_callback;
    epCallback[26] = &USBHAL::EP14_OUT_callback;
    epCallback[27] = &USBHAL::EP14_IN_callback;
    epCallback[28] = &USBHAL::EP15_OUT_callback;
    epCallback[29] = &USBHAL::EP15_IN_callback;

    // choose usb src as PLL
    SIM->SOPT2 |= (SIM_SOPT2_USBSRC_MASK | SIM_SOPT2_PLLFLLSEL_MASK);

    // enable OTG clock
    SIM->SCGC4 |= SIM_SCGC4_USBOTG_MASK;

    // USB Module Configuration
    // Reset USB Module
    USB0->USBTRC0 |= USB_USBTRC0_USBRESET_MASK;
    while(USB0->USBTRC0 & USB_USBTRC0_USBRESET_MASK);

    // Set BDT Base Register
    USB0->BDTPAGE1 = (uint8_t)(uint32_t(bdt) >> 8);
    USB0->BDTPAGE2 = (uint8_t)(uint32_t(bdt) >> 16);
    USB0->BDTPAGE3 = (uint8_t)(uint32_t(bdt) >> 24);

    // Clear interrupt flag
    USB0->ISTAT = 0xff;

    // USB Interrupt Enablers
    USB0->INTEN = USB_INTEN_TOKDNEEN_MASK |
                  USB_INTEN_SOFTOKEN_MASK |
                  USB_INTEN_ERROREN_MASK  |
                  USB_INTEN_SLEEPEN_MASK |
                  USB_INTEN_RESUMEEN_MASK |
                  USB_INTEN_USBRSTEN_MASK |
                  (1 << 7);                   // stall mask

    // Attach IRQ
    instance = this;
    NVIC_SetVector(USB0_IRQn, (uint32_t)&_usbisr);
    NVIC_EnableIRQ(USB0_IRQn);

    // Disable weak pull downs
    USB0->USBCTRL &= ~(USB_USBCTRL_PDE_MASK | USB_USBCTRL_SUSP_MASK);
    USB0->USBTRC0 |= 0x40;
}

USBHAL::~USBHAL(void) { }

void USBHAL::connect(void) 
{
    // enable USB
    USB0->CTL |= USB_CTL_USBENSOFEN_MASK;
    
    // Pull up enable
    USB0->CONTROL |= USB_CONTROL_DPPULLUPNONOTG_MASK;
}

void USBHAL::disconnect(void) 
{
    // disable USB
    USB0->CTL &= ~USB_CTL_USBENSOFEN_MASK;

    // Pull up disable
    USB0->CONTROL &= ~USB_CONTROL_DPPULLUPNONOTG_MASK;

    //Free buffers if required:
    for (int i = 0 ; i < NUMBER_OF_PHYSICAL_ENDPOINTS ; i++) {
        free(endpoint_buffer[i]);
        endpoint_buffer[i] = NULL;
    }
}

void USBHAL::configureDevice(void) {
    // not needed
}

void USBHAL::unconfigureDevice(void) {
    // not needed
}

void USBHAL::setAddress(uint8_t address) {
    // we don't set the address now otherwise the usb controller does not ack
    // we set a flag instead
    // see usbisr when an IN token is received
    set_addr = 1;
    addr = address;
 }

bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket, uint32_t flags) 
{
    uint32_t handshake_flag;
    uint32_t alo_size;

    if (endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS)
        return false;

    uint32_t log_endpoint = PHY_TO_LOG(endpoint);
    
    if (flags & ISOCHRONOUS) {
        handshake_flag = 0;
        alo_size = 1023;
    }
    else {
        handshake_flag = USB_ENDPT_EPHSHK_MASK;
        alo_size = 64;
    }
    
    // if we have a buffer, but the new buffer size is bigger, delete the old one
    if (endpoint_buffer[endpoint] != 0 && epInfo[endpoint].bufsiz < maxPacket) {
        free(endpoint_buffer[endpoint]);
        endpoint_buffer[endpoint] = 0;
        epInfo[endpoint].bufsiz = 0;
    }
    
    // allocate a new buffer if we don't already have one    
    if (endpoint_buffer[endpoint] == 0) {
        endpoint_buffer[endpoint] = (uint8_t *)malloc(alo_size);
        epInfo[endpoint].bufsiz = alo_size;
    }
    
    // remember the realisation flags for the endpoint
    epInfo[endpoint].flags = flags;

    // Set DATA1 initially on the endpoint.  If it's an RX endpoint, we're about to start
    // a read with DATA0, so the next read will be DATA1.  If it's a TX endpoint, we'll
    // actually want to send DATA0 for the first packet, but for that we need the flag
    // to be set to DATA1, since the write routine always inverts the flag *before*
    // using it.
    set_DATA1(endpoint);
    
    // the endpoint hasn't completed its first operation yet
    clear_completion(endpoint);
    
    if (IN_EP(endpoint)) 
    {
        // IN endpt -> device to host (TX)
        set_ready(endpoint);
        USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag |        // ep handshaking (not if iso endpoint)
                                              USB_ENDPT_EPTXEN_MASK;  // en TX (IN) tran
        bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].info       = 0;
        bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].info       = 0;
        bdt[EP_BDT_IDX(log_endpoint, TX, EVEN)].address = (uint32_t) endpoint_buffer[endpoint];
        bdt[EP_BDT_IDX(log_endpoint, TX, ODD )].address = 0;
    }
    else 
    {
        // OUT endpt -> host to device (RX)
        clear_ready(endpoint);
        USB0->ENDPOINT[log_endpoint].ENDPT |= handshake_flag |        // ep handshaking (not if iso endpoint)
                                              USB_ENDPT_EPRXEN_MASK;  // en RX (OUT) tran.
        bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].byte_count = maxPacket;
        bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].address    = (uint32_t) endpoint_buffer[endpoint];
        bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].address    = 0;
        bdt[EP_BDT_IDX(log_endpoint, RX, EVEN)].info       = BD_OWN_MASK | BD_DTS_MASK;
        bdt[EP_BDT_IDX(log_endpoint, RX, ODD )].info       = 0;
    }

    // success
    return true;
}

// read setup packet
void USBHAL::EP0setup(uint8_t *buffer) 
{
    uint32_t sz;
    if (endpointReadResult(EP0OUT, buffer, &sz) != EP_COMPLETED)
        printf("EP0setup not ready\r\n"); // $$$
    if (sz != 8) 
        printf("EP0setup - wrong size! %d bytes, expected 8 bytes\r\n", sz); // $$$
}

void USBHAL::EP0readStage(void) 
{
    uint32_t idx = EP_BDT_IDX(PHY_TO_LOG(EP0OUT), RX, 0);
    set_DATA0(EP0OUT);                              // set DATA0 for the next packet
    { // if (epReady & EP(EP0OUT)) {
        bdt[idx].byte_count = MAX_PACKET_SIZE_EP0;
        bdt[idx].info = (BD_DTS_MASK | BD_OWN_MASK);    // start the read
    }
#ifdef DEBUG_PRINTF
 //   else printf("!!! EP0readStage() not ready !!!\r\n");
#endif
}

void USBHAL::EP0read(void) 
{
}

uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) 
{
    uint32_t sz;
    while (endpointReadResult(EP0OUT, buffer, &sz) == EP_PENDING) ;
    return sz;
}

void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
    while (endpointWrite(EP0IN, buffer, size) == EP_BUSY) ;
}

void USBHAL::EP0getWriteResult(void) {
}

void USBHAL::EP0stall(void) 
{
    stallEndpoint(EP0OUT);
}

EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) 
{
    return EP_PENDING;
}

EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t *buffer, uint32_t *bytesRead) 
{
    // validate the endpoint number
    if (endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS)
        return EP_INVALID;

    // we can only read an OUT endpoint
    if (IN_EP(endpoint))
        return EP_INVALID;

    // get the logical endpoint number
    uint32_t log_endpoint = PHY_TO_LOG(endpoint);

    // get the BDT index
    int idx = EP_BDT_IDX(log_endpoint, RX, 0);
 
#if 1 // $$$$   
#ifdef DEBUG_PRINTF
    if (endpoint == EP0OUT && !(epReady & EP(endpoint))) printf("!!! EP0 read not ready\r\n");
#endif
    // if the endpoint isn't ready, the read is pending
    if (!(epReady & EP(endpoint)))
        return EP_PENDING;
#else
    // If the endpoint isn't ready, the read is still pending.  Ignore this
    // for EP0, since the control procotol inherently serializes packets on
    // both the RX and TX endpoints.
    if (endpoint != EP0OUT && !(epReady & EP(endpoint)))
        return EP_PENDING;
#endif

    // make sure we're marked as complete (except for isochronous endpoints)
    bool iso = epInfo[log_endpoint].flags & ISOCHRONOUS;
    if ((log_endpoint != 0) && !iso && !(epComplete & EP(endpoint)))
        return EP_PENDING;

    // this consumes the read status - clear the completion flag to prepare for the next read
    clear_completion(endpoint);
    
    // the new operation is pending, so the endpoint is not ready
    clear_ready(endpoint);

    // copy the data from the hardware buffer to the caller's buffer
    uint8_t *ep_buf = (uint8_t *)bdt[idx].address;
    uint32_t sz = *bytesRead = bdt[idx].byte_count;
    for (uint32_t n = 0; n < sz; n++)
        buffer[n] = ep_buf[n];
    
    // Figure the DATA0/DATA1 value for the next packet.  If we have a
    // SETUP token with no data stage, it's DATA0.  Otherwise we just
    // flip the last value, assuming the new token matches what we expect.
    bool setup = (log_endpoint == 0 && TOK_PID(idx) == SETUP_TOKEN);
    if (((Data1 >> endpoint) & 1) == ((bdt[idx].info >> 6) & 1)) {
        if (setup && (buffer[6] == 0)) {
            set_DATA0(EP0OUT);          // no setup data stage, so set DATA0
        }
        else {
            toggle_DATA01(endpoint);    // in other cases, toggle the DATA0/DATA1 status on each packet 
        }
    }

    // hand off the BDT to start the next read
    bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | (((Data1 >> endpoint) & 1) << 6);

    // If this is a SETUP packet, clear the "suspend token busy" hardware flag.
    // The SIE sets this bit during setup to allow non-interrupted processing.
    if (setup)
        USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
    
    // operation completed
    return EP_COMPLETED;
}

EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) 
{
    // validate the endpoint number
    if (endpoint >= NUMBER_OF_PHYSICAL_ENDPOINTS)
        return EP_INVALID;

    // if write on a OUT endpoint -> error
    if (OUT_EP(endpoint))
        return EP_INVALID;

    // get the BDT entry for the endpoint
    int idx = EP_BDT_IDX(PHY_TO_LOG(endpoint), TX, 0);

#if 0
#ifdef DEBUG_PRINTF
    if (endpoint == EP0IN && !(epReady & EP(endpoint))) printf("!!! EP0 write not ready\r\n");
#endif
    // $$$
    // if the endpoint isn't ready, return BUSY, since we have an outstanding
    // write that hasn't completed yet
    if (!(epReady & EP(endpoint)))
        return EP_BUSY;
#else
    // If the endpoint isn't marked as ready, return BUSY, since we have an
    // outstanding write on the endpoint that hasn't completed yet.  Skip this
    // test for EP0, since EP0 is handled entirely through interrupt callbacks
    // and packet exchange is inherently serialized by the protocol.  
    if (endpoint != EP0IN && !(epReady & EP(endpoint)))
        return EP_BUSY;
#endif

    // copy the bytes to the endpoint hardware buffer
    uint8_t *ep_buf = (uint8_t *)bdt[idx].address;
    bdt[idx].byte_count = size;
    for (uint32_t n = 0 ; n < size ; n++)
        ep_buf[n] = data[n];

    // toggle DATA0/DATA1 on each packet
    toggle_DATA01(endpoint);
    
    // mark the endpoint as not ready and not complete
    clear_completion(endpoint);
    clear_ready(endpoint);

    // hand the buffer to the SIE
    bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK | (((Data1 >> endpoint) & 1) << 6);

    // the packet is now pending
    return EP_PENDING;
}

EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) 
{
    // if the endpoint is ready, and the completion flag is set, we're done
    uint32_t mask = EP(endpoint);
    if ((epReady & mask) && (epComplete & mask)) {
        clear_completion(endpoint);
        return EP_COMPLETED;
    }
    
    return EP_PENDING;
}

void USBHAL::stallEndpoint(uint8_t endpoint) 
{
#ifdef DEBUG_PRINTF
    printf("Stall %d\r\n", endpoint);
#endif
    int idx = PEP_BDT_IDX(endpoint, EVEN);
    if ((epReady & EP(endpoint)) && !(bdt[idx].info & BD_OWN_MASK))
        bdt[idx].info |= BD_STALL_MASK;
    else
        USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT |= USB_ENDPT_EPSTALL_MASK;
}

void USBHAL::unstallEndpoint(uint8_t endpoint) 
{
#ifdef DEBUG_PRINTF
    printf("Unstall %d\r\n", endpoint);
#endif

    // get the physical endpoint
    int logep = PHY_TO_LOG(endpoint);
    
    // figure the new endpoint control register flags
    uint8_t f = IN_EP(endpoint) ? USB_ENDPT_EPTXEN_MASK : USB_ENDPT_EPRXEN_MASK;
    if (logep != 0)
    {
        // add the HANDSHAKE flag if it's not isochronous
        if (!(epInfo[endpoint].flags & ISOCHRONOUS))
            f |= USB_ENDPT_EPHSHK_MASK;
    }
            
    // set the new flags
    USB0->ENDPOINT[logep].ENDPT = f;
    
    // clear the STALL bit in the endponit control register
    USB0->ENDPOINT[logep].ENDPT &= ~USB_ENDPT_EPSTALL_MASK;
    
    // clear the stall bit in the BDT, and take ownership
    int idx = PEP_BDT_IDX(endpoint, EVEN);
    bdt[idx].info &= ~(BD_OWN_MASK | BD_STALL_MASK);
    
    // the endpoint is now NOT COMPLETED
    clear_completion(endpoint);
    
    // Set the data flag to DATA1 for the endpoint.  If it's TX, the next
    // packet sent needs to be DATA0, and write flips the bit first, so we
    // want it to be DATA1 now.  If it's RX, we're about to start a read
    // with DATA0, so the next read will be back to DATA1.
    set_DATA1(endpoint);

    // check the endpoint type for final settings
    if (IN_EP(endpoint))
    {
        // TX endpoint - mark as ready so that next write operation can proceed,
        // and set the DATA1 flag so that the next packet will be sent as DATA0
        // (the write opereation flips the bit before sending)
        set_ready(endpoint);
    }
    else
    {
        // RX endpoint - start next read operation with DATA0
        if (epReady & EP(endpoint))
        {
            clear_ready(endpoint);
            bdt[idx].byte_count = epInfo[endpoint].bufsiz;
            bdt[idx].info = BD_OWN_MASK | BD_DTS_MASK;
        }
    }
}

bool USBHAL::getEndpointStallState(uint8_t endpoint) 
{
    return (USB0->ENDPOINT[PHY_TO_LOG(endpoint)].ENDPT & USB_ENDPT_EPSTALL_MASK) != 0;
}

void USBHAL::remoteWakeup(void) {
    // [TODO]
}


void USBHAL::_usbisr(void) {
    instance->usbisr();
}


void USBHAL::usbisr(void) 
{
    uint8_t i;
    uint8_t istat = USB0->ISTAT;

    // reset interrupt
    if (istat & USB_ISTAT_USBRST_MASK) 
    {
#ifdef DEBUG_PRINTF
       // printf("\r\n>>> USB RESET\r\n");
#endif

        // disable all endpt
        for(i = 0 ; i < 16 ; i++) {
            USB0->ENDPOINT[i].ENDPT = 0x00;
        }

        // enable control endpoint
        realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
        realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);

        Data1 = 0x55555555;
        epComplete = 0;
        
        // Reset the SIE even/odd buffer state.  We keep this bit
        // set throughout the session, which makes the EVEN buffer
        // the only one that's ever used, effectively disabling the
        // double-buffering system.
        USB0->CTL |=  USB_CTL_ODDRST_MASK;

        USB0->ERRSTAT =  0xBF;  // clear all error flags
        USB0->ERREN   =  0x9F; // 0xBF;  // enable error interrupt sources 
        USB0->ADDR    =  0x00;  // set default address
        
        // notify upper layers of the bus reset
        busReset();
        
        // we're not suspended
        suspendStateChanged(0);

        // clear all interrupt status flags and return        
        USB0->ISTAT = 0xFF;
        return;
    }

    // resume interrupt
    if (istat & USB_ISTAT_RESUME_MASK) {
        suspendStateChanged(0);
        USB0->ISTAT = USB_ISTAT_RESUME_MASK;
        return;
    }

    // SOF interrupt
    if (istat & USB_ISTAT_SOFTOK_MASK) {
        // SOF event, read frame number
        SOF(frameNumber());
        USB0->ISTAT = USB_ISTAT_SOFTOK_MASK;
        return;
    }

    // stall interrupt
    if (istat & USB_ISTAT_STALL_MASK)
    {
#ifdef DEBUG_PRINTF
        printf("\r\n>>>>STALL INTERRUPT\r\n");
#endif
        if (USB0->ENDPOINT[0].ENDPT & USB_ENDPT_EPSTALL_MASK) {
            unstallEndpoint(EP0IN);
            unstallEndpoint(EP0OUT);
        }
        USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;
        USB0->ISTAT = USB_ISTAT_STALL_MASK;
        return;
    }

    // TOKEN DONE interrupt
    if (istat & USB_ISTAT_TOKDNE_MASK)
    {
        uint32_t stat = USB0->STAT;
        uint32_t num  = (stat >> 4) & 0x0F;
        uint32_t dir  = (stat >> 3) & 0x01;
        uint32_t ev_odd = (stat >> 2) & 0x01;
        int endpoint = (num << 1) | dir;
        int idx = EP_BDT_IDX(num, dir, ev_odd);
        int pid = TOK_PID(idx);
        int len = bdt[idx].byte_count;
        
        if (ev_odd) printf("!!! odd BDT entry???\r\n");//$$$

        // endpoint is ready for next operation
        epReady |= EP(endpoint);
        // if (num == 0) epReady |= EP(EP0OUT) | EP(EP0IN);
        
        //$$$for (int i = 0 ; (bdt[idx].info & BD_OWN_MASK) && i < 10000000 ; ++i) ;
        //$$$static int unrel;
       //$$$ if (bdt[idx].info & BD_OWN_MASK) { printf("\r\nIRQ: BDT wasn't released from SIE to CPU (ep=%d)\r\n", endpoint); } 
        if (pid == SETUP_TOKEN && len != 8) {
            pid = OUT_TOKEN;
          //$$$  printf("IRQ: SETUP packet has wrong size (%d)\r\n", bdt[EP_BDT_IDX(num, dir, ev_odd)].byte_count);//$$$
        }
            
        // setup packet
        if (num == 0 && pid == SETUP_TOKEN)
        {
            Data1 &= ~0x02;
            //bdt[EP_BDT_IDX(0, TX, EVEN)].info &= ~BD_OWN_MASK;
            //bdt[EP_BDT_IDX(0, TX, ODD )].info &= ~BD_OWN_MASK;

            // EP0 SETUP event (SETUP data received)
            EP0setupCallback();
        } 
        else if (pid == OUT_TOKEN)
        {
            // OUT packet
            if (num == 0)
                EP0out();
            else 
            {
                epComplete |= EP(endpoint);
                if ((instance->*(epCallback[endpoint - 2]))())
                    epComplete &= ~EP(endpoint);
            }
        }
        else if (pid == IN_TOKEN)
        {
            // IN packet
            if (num == 0) 
            {
                EP0in();
                if (set_addr == 1) 
                {
                    USB0->ADDR = addr & 0x7F;
                    set_addr = 0;
                }
            }
            else 
            {
                epComplete |= EP(endpoint);
                if ((instance->*(epCallback[endpoint - 2]))())
                    epComplete &= ~EP(endpoint);
            }
        }

        USB0->ISTAT = USB_ISTAT_TOKDNE_MASK;
        return;
    }

    // sleep interrupt
    if (istat & USB_ISTAT_SLEEP_MASK) 
    {
#ifdef DEBUG_PRINTF
        //printf("\r\n>>> USB SLEEP INTERRUPT\r\n");
#endif
        suspendStateChanged(1);
        USB0->ISTAT = USB_ISTAT_SLEEP_MASK;
        return;
    }

    // error interrupt
    if (istat & USB_ISTAT_ERROR_MASK) 
    {
        uint32_t errstat = USB0->ERRSTAT;
#ifdef DEBUG_PRINTF
        printf("\r\n>>>>ERROR INTERRUPT: ERRSTAT=%x\r\n", errstat);
#endif
        if (errstat & 0x20)
            USB_DMAERR = true;

        // reset the error status
        USB0->ERRSTAT = 0xBF;
        
        // allow the SIE to continue token processing
        USB0->CTL &= ~USB_CTL_TXSUSPENDTOKENBUSY_MASK;

        // reset the interrupt
        USB0->ISTAT = USB_ISTAT_ERROR_MASK;
        return;
    }
}


#ifdef DEBUG_PRINTF
void USBDeviceStatusDump()
{
    printf("USBDevice status:\r\n");
    printf("        0  0  1  1  2  2  3  3  4  4  5  5  6  6  7  7  8  8  9  9 10 10 11 11 12 12 13 13 14 14 15 15\r\n");
    printf("       RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX RX TX\r\n");
    printf("Data1  ");
    for (int i = 0 ; i < 32 ; ++i)
        printf(" %d ", (Data1 >> i) & 1);
    printf("\r\n"
           "Cmplt  ");
    for (int i = 0 ; i < 32 ; ++i)
        printf(" %d ", (epComplete >> i) & 1);
    printf("\r\n"
           "Ready  ");
    for (int i = 0 ; i < 32 ; ++i)
        printf(" %d ", (epReady >> i) & 1);
    printf("\r\n"
           "OWN    ");
    for (int i = 0 ; i < 16 ; ++i)
        printf(" %d  %d ", (bdt[EP_BDT_IDX(i, RX, 0)].info >> 7) & 1, (bdt[EP_BDT_IDX(i, TX, 0)].info >> 7) & 1);
    printf("\r\n"
           "Stall  ");
    for (int i = 0 ; i < 16 ; ++i)
        printf("  %s   ", (USB0->ENDPOINT[i].ENDPT & USB_ENDPT_EPSTALL_MASK) ? "S" : ".");
    printf("\r\n\r\n");
}
#endif

#endif