Paul Jeon / Mbed 2 deprecated GSMTest2PICO-ece493

works!

Dependencies:   mbed

USBSerialLib/USBDevice/USBRegs_STM32.h@2:5e5cdc3504fe, 2020-02-21 (annotated)

Committer:
kchhouk
Date:
Fri Feb 21 21:03:41 2020 +0000
Revision:
2:5e5cdc3504fe
Parent:
1:6e512faaa17c 
Added the functionality of scanf

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mjoun 1:6e512faaa17c 1 /**
mjoun 1:6e512faaa17c 2 ******************************************************************************
mjoun 1:6e512faaa17c 3 * @file usb_regs.h
mjoun 1:6e512faaa17c 4 * @author MCD Application Team
mjoun 1:6e512faaa17c 5 * @version V2.1.0
mjoun 1:6e512faaa17c 6 * @date 19-March-2012
mjoun 1:6e512faaa17c 7 * @brief hardware registers
mjoun 1:6e512faaa17c 8 ******************************************************************************
mjoun 1:6e512faaa17c 9 * @attention
mjoun 1:6e512faaa17c 10 *
mjoun 1:6e512faaa17c 11 * <h2><center>&copy; COPYRIGHT 2012 STMicroelectronics</center></h2>
mjoun 1:6e512faaa17c 12 *
mjoun 1:6e512faaa17c 13 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
mjoun 1:6e512faaa17c 14 * You may not use this file except in compliance with the License.
mjoun 1:6e512faaa17c 15 * You may obtain a copy of the License at:
mjoun 1:6e512faaa17c 16 *
mjoun 1:6e512faaa17c 17 * http://www.st.com/software_license_agreement_liberty_v2
mjoun 1:6e512faaa17c 18 *
mjoun 1:6e512faaa17c 19 * Unless required by applicable law or agreed to in writing, software
mjoun 1:6e512faaa17c 20 * distributed under the License is distributed on an "AS IS" BASIS,
mjoun 1:6e512faaa17c 21 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
mjoun 1:6e512faaa17c 22 * See the License for the specific language governing permissions and
mjoun 1:6e512faaa17c 23 * limitations under the License.
mjoun 1:6e512faaa17c 24 *
mjoun 1:6e512faaa17c 25 ******************************************************************************
mjoun 1:6e512faaa17c 26 */
mjoun 1:6e512faaa17c 27
mjoun 1:6e512faaa17c 28 #ifndef __USB_OTG_REGS_H__
mjoun 1:6e512faaa17c 29 #define __USB_OTG_REGS_H__
mjoun 1:6e512faaa17c 30
mjoun 1:6e512faaa17c 31 typedef struct //000h
mjoun 1:6e512faaa17c 32 {
mjoun 1:6e512faaa17c 33 __IO uint32_t GOTGCTL; /* USB_OTG Control and Status Register 000h*/
mjoun 1:6e512faaa17c 34 __IO uint32_t GOTGINT; /* USB_OTG Interrupt Register 004h*/
mjoun 1:6e512faaa17c 35 __IO uint32_t GAHBCFG; /* Core AHB Configuration Register 008h*/
mjoun 1:6e512faaa17c 36 __IO uint32_t GUSBCFG; /* Core USB Configuration Register 00Ch*/
mjoun 1:6e512faaa17c 37 __IO uint32_t GRSTCTL; /* Core Reset Register 010h*/
mjoun 1:6e512faaa17c 38 __IO uint32_t GINTSTS; /* Core Interrupt Register 014h*/
mjoun 1:6e512faaa17c 39 __IO uint32_t GINTMSK; /* Core Interrupt Mask Register 018h*/
mjoun 1:6e512faaa17c 40 __IO uint32_t GRXSTSR; /* Receive Sts Q Read Register 01Ch*/
mjoun 1:6e512faaa17c 41 __IO uint32_t GRXSTSP; /* Receive Sts Q Read & POP Register 020h*/
mjoun 1:6e512faaa17c 42 __IO uint32_t GRXFSIZ; /* Receive FIFO Size Register 024h*/
mjoun 1:6e512faaa17c 43 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /* EP0 / Non Periodic Tx FIFO Size Register 028h*/
mjoun 1:6e512faaa17c 44 __IO uint32_t HNPTXSTS; /* Non Periodic Tx FIFO/Queue Sts reg 02Ch*/
mjoun 1:6e512faaa17c 45 uint32_t Reserved30[2]; /* Reserved 030h*/
mjoun 1:6e512faaa17c 46 __IO uint32_t GCCFG; /* General Purpose IO Register 038h*/
mjoun 1:6e512faaa17c 47 __IO uint32_t CID; /* User ID Register 03Ch*/
mjoun 1:6e512faaa17c 48 uint32_t Reserved40[48]; /* Reserved 040h-0FFh*/
mjoun 1:6e512faaa17c 49 __IO uint32_t HPTXFSIZ; /* Host Periodic Tx FIFO Size Reg 100h*/
mjoun 1:6e512faaa17c 50 __IO uint32_t DIEPTXF[3];/* dev Periodic Transmit FIFO */
mjoun 1:6e512faaa17c 51 }
mjoun 1:6e512faaa17c 52 USB_OTG_GREGS;
mjoun 1:6e512faaa17c 53
mjoun 1:6e512faaa17c 54 typedef struct // 800h
mjoun 1:6e512faaa17c 55 {
mjoun 1:6e512faaa17c 56 __IO uint32_t DCFG; /* dev Configuration Register 800h*/
mjoun 1:6e512faaa17c 57 __IO uint32_t DCTL; /* dev Control Register 804h*/
mjoun 1:6e512faaa17c 58 __IO uint32_t DSTS; /* dev Status Register (RO) 808h*/
mjoun 1:6e512faaa17c 59 uint32_t Reserved0C; /* Reserved 80Ch*/
mjoun 1:6e512faaa17c 60 __IO uint32_t DIEPMSK; /* dev IN Endpoint Mask 810h*/
mjoun 1:6e512faaa17c 61 __IO uint32_t DOEPMSK; /* dev OUT Endpoint Mask 814h*/
mjoun 1:6e512faaa17c 62 __IO uint32_t DAINT; /* dev All Endpoints Itr Reg 818h*/
mjoun 1:6e512faaa17c 63 __IO uint32_t DAINTMSK; /* dev All Endpoints Itr Mask 81Ch*/
mjoun 1:6e512faaa17c 64 uint32_t Reserved20; /* Reserved 820h*/
mjoun 1:6e512faaa17c 65 uint32_t Reserved9; /* Reserved 824h*/
mjoun 1:6e512faaa17c 66 __IO uint32_t DVBUSDIS; /* dev VBUS discharge Register 828h*/
mjoun 1:6e512faaa17c 67 __IO uint32_t DVBUSPULSE; /* dev VBUS Pulse Register 82Ch*/
mjoun 1:6e512faaa17c 68 __IO uint32_t DTHRCTL; /* dev thr 830h*/
mjoun 1:6e512faaa17c 69 __IO uint32_t DIEPEMPMSK; /* dev empty msk 834h*/
mjoun 1:6e512faaa17c 70 }
mjoun 1:6e512faaa17c 71 USB_OTG_DREGS;
mjoun 1:6e512faaa17c 72
mjoun 1:6e512faaa17c 73 typedef struct
mjoun 1:6e512faaa17c 74 {
mjoun 1:6e512faaa17c 75 __IO uint32_t DIEPCTL; /* dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h*/
mjoun 1:6e512faaa17c 76 uint32_t Reserved04; /* Reserved 900h + (ep_num * 20h) + 04h*/
mjoun 1:6e512faaa17c 77 __IO uint32_t DIEPINT; /* dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h*/
mjoun 1:6e512faaa17c 78 uint32_t Reserved0C; /* Reserved 900h + (ep_num * 20h) + 0Ch*/
mjoun 1:6e512faaa17c 79 __IO uint32_t DIEPTSIZ; /* IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h*/
mjoun 1:6e512faaa17c 80 uint32_t Reserved14;
mjoun 1:6e512faaa17c 81 __IO uint32_t DTXFSTS;/*IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h*/
mjoun 1:6e512faaa17c 82 uint32_t Reserved1C; /* Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch*/
mjoun 1:6e512faaa17c 83 }
mjoun 1:6e512faaa17c 84 USB_OTG_INEPREGS;
mjoun 1:6e512faaa17c 85
mjoun 1:6e512faaa17c 86 typedef struct
mjoun 1:6e512faaa17c 87 {
mjoun 1:6e512faaa17c 88 __IO uint32_t DOEPCTL; /* dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h*/
mjoun 1:6e512faaa17c 89 uint32_t Reserved04; /* Reserved B00h + (ep_num * 20h) + 04h*/
mjoun 1:6e512faaa17c 90 __IO uint32_t DOEPINT; /* dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h*/
mjoun 1:6e512faaa17c 91 uint32_t Reserved0C; /* Reserved B00h + (ep_num * 20h) + 0Ch*/
mjoun 1:6e512faaa17c 92 __IO uint32_t DOEPTSIZ; /* dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h*/
mjoun 1:6e512faaa17c 93 uint32_t Reserved14[3];
mjoun 1:6e512faaa17c 94 }
mjoun 1:6e512faaa17c 95 USB_OTG_OUTEPREGS;
mjoun 1:6e512faaa17c 96
mjoun 1:6e512faaa17c 97 typedef struct
mjoun 1:6e512faaa17c 98 {
mjoun 1:6e512faaa17c 99 __IO uint32_t HCFG; /* Host Configuration Register 400h*/
mjoun 1:6e512faaa17c 100 __IO uint32_t HFIR; /* Host Frame Interval Register 404h*/
mjoun 1:6e512faaa17c 101 __IO uint32_t HFNUM; /* Host Frame Nbr/Frame Remaining 408h*/
mjoun 1:6e512faaa17c 102 uint32_t Reserved40C; /* Reserved 40Ch*/
mjoun 1:6e512faaa17c 103 __IO uint32_t HPTXSTS; /* Host Periodic Tx FIFO/ Queue Status 410h*/
mjoun 1:6e512faaa17c 104 __IO uint32_t HAINT; /* Host All Channels Interrupt Register 414h*/
mjoun 1:6e512faaa17c 105 __IO uint32_t HAINTMSK; /* Host All Channels Interrupt Mask 418h*/
mjoun 1:6e512faaa17c 106 }
mjoun 1:6e512faaa17c 107 USB_OTG_HREGS;
mjoun 1:6e512faaa17c 108
mjoun 1:6e512faaa17c 109 typedef struct
mjoun 1:6e512faaa17c 110 {
mjoun 1:6e512faaa17c 111 __IO uint32_t HCCHAR;
mjoun 1:6e512faaa17c 112 __IO uint32_t HCSPLT;
mjoun 1:6e512faaa17c 113 __IO uint32_t HCINT;
mjoun 1:6e512faaa17c 114 __IO uint32_t HCINTMSK;
mjoun 1:6e512faaa17c 115 __IO uint32_t HCTSIZ;
mjoun 1:6e512faaa17c 116 uint32_t Reserved[3];
mjoun 1:6e512faaa17c 117 }
mjoun 1:6e512faaa17c 118 USB_OTG_HC_REGS;
mjoun 1:6e512faaa17c 119
mjoun 1:6e512faaa17c 120 typedef struct
mjoun 1:6e512faaa17c 121 {
mjoun 1:6e512faaa17c 122 USB_OTG_GREGS GREGS;
mjoun 1:6e512faaa17c 123 uint32_t RESERVED0[188];
mjoun 1:6e512faaa17c 124 USB_OTG_HREGS HREGS;
mjoun 1:6e512faaa17c 125 uint32_t RESERVED1[9];
mjoun 1:6e512faaa17c 126 __IO uint32_t HPRT;
mjoun 1:6e512faaa17c 127 uint32_t RESERVED2[47];
mjoun 1:6e512faaa17c 128 USB_OTG_HC_REGS HC_REGS[8];
mjoun 1:6e512faaa17c 129 uint32_t RESERVED3[128];
mjoun 1:6e512faaa17c 130 USB_OTG_DREGS DREGS;
mjoun 1:6e512faaa17c 131 uint32_t RESERVED4[50];
mjoun 1:6e512faaa17c 132 USB_OTG_INEPREGS INEP_REGS[4];
mjoun 1:6e512faaa17c 133 uint32_t RESERVED5[96];
mjoun 1:6e512faaa17c 134 USB_OTG_OUTEPREGS OUTEP_REGS[4];
mjoun 1:6e512faaa17c 135 uint32_t RESERVED6[160];
mjoun 1:6e512faaa17c 136 __IO uint32_t PCGCCTL;
mjoun 1:6e512faaa17c 137 uint32_t RESERVED7[127];
mjoun 1:6e512faaa17c 138 __IO uint32_t FIFO[4][1024];
mjoun 1:6e512faaa17c 139 }
mjoun 1:6e512faaa17c 140 USB_OTG_CORE_REGS;
mjoun 1:6e512faaa17c 141
mjoun 1:6e512faaa17c 142
mjoun 1:6e512faaa17c 143 #define OTG_FS_BASE (AHB2PERIPH_BASE + 0x0000)
mjoun 1:6e512faaa17c 144 #define OTG_FS ((USB_OTG_CORE_REGS *) OTG_FS_BASE)
mjoun 1:6e512faaa17c 145
mjoun 1:6e512faaa17c 146 #endif //__USB_OTG_REGS_H__
mjoun 1:6e512faaa17c 147
mjoun 1:6e512faaa17c 148 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
mjoun 1:6e512faaa17c 149