Paul Jeon / Mbed 2 deprecated GSMTest2PICO-ece493

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Dependencies:   mbed

USBSerialLib/USBDevice/USBHAL_STM32F4.cpp@2:5e5cdc3504fe, 2020-02-21 (annotated)

Committer:
kchhouk
Date:
Fri Feb 21 21:03:41 2020 +0000
Revision:
2:5e5cdc3504fe
Parent:
1:6e512faaa17c 
Added the functionality of scanf

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mjoun 1:6e512faaa17c 1 /* Copyright (c) 2010-2011 mbed.org, MIT License
mjoun 1:6e512faaa17c 2 *
mjoun 1:6e512faaa17c 3 * Permission is hereby granted, free of charge, to any person obtaining a copy of this software
mjoun 1:6e512faaa17c 4 * and associated documentation files (the "Software"), to deal in the Software without
mjoun 1:6e512faaa17c 5 * restriction, including without limitation the rights to use, copy, modify, merge, publish,
mjoun 1:6e512faaa17c 6 * distribute, sublicense, and/or sell copies of the Software, and to permit persons to whom the
mjoun 1:6e512faaa17c 7 * Software is furnished to do so, subject to the following conditions:
mjoun 1:6e512faaa17c 8 *
mjoun 1:6e512faaa17c 9 * The above copyright notice and this permission notice shall be included in all copies or
mjoun 1:6e512faaa17c 10 * substantial portions of the Software.
mjoun 1:6e512faaa17c 11 *
mjoun 1:6e512faaa17c 12 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING
mjoun 1:6e512faaa17c 13 * BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
mjoun 1:6e512faaa17c 14 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM,
mjoun 1:6e512faaa17c 15 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
mjoun 1:6e512faaa17c 16 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
mjoun 1:6e512faaa17c 17 */
mjoun 1:6e512faaa17c 18
mjoun 1:6e512faaa17c 19 #if defined(TARGET_STM32F4)
mjoun 1:6e512faaa17c 20
mjoun 1:6e512faaa17c 21 #include "USBHAL.h"
mjoun 1:6e512faaa17c 22 #include "USBRegs_STM32.h"
mjoun 1:6e512faaa17c 23 #include "pinmap.h"
mjoun 1:6e512faaa17c 24
mjoun 1:6e512faaa17c 25 USBHAL * USBHAL::instance;
mjoun 1:6e512faaa17c 26
mjoun 1:6e512faaa17c 27 static volatile int epComplete = 0;
mjoun 1:6e512faaa17c 28
mjoun 1:6e512faaa17c 29 static uint32_t bufferEnd = 0;
mjoun 1:6e512faaa17c 30 static const uint32_t rxFifoSize = 512;
mjoun 1:6e512faaa17c 31 static uint32_t rxFifoCount = 0;
mjoun 1:6e512faaa17c 32
mjoun 1:6e512faaa17c 33 static uint32_t setupBuffer[MAX_PACKET_SIZE_EP0 >> 2];
mjoun 1:6e512faaa17c 34
mjoun 1:6e512faaa17c 35 uint32_t USBHAL::endpointReadcore(uint8_t endpoint, uint8_t *buffer) {
mjoun 1:6e512faaa17c 36 return 0;
mjoun 1:6e512faaa17c 37 }
mjoun 1:6e512faaa17c 38
mjoun 1:6e512faaa17c 39 USBHAL::USBHAL(void) {
mjoun 1:6e512faaa17c 40 NVIC_DisableIRQ(OTG_FS_IRQn);
mjoun 1:6e512faaa17c 41 epCallback[0] = &USBHAL::EP1_OUT_callback;
mjoun 1:6e512faaa17c 42 epCallback[1] = &USBHAL::EP1_IN_callback;
mjoun 1:6e512faaa17c 43 epCallback[2] = &USBHAL::EP2_OUT_callback;
mjoun 1:6e512faaa17c 44 epCallback[3] = &USBHAL::EP2_IN_callback;
mjoun 1:6e512faaa17c 45 epCallback[4] = &USBHAL::EP3_OUT_callback;
mjoun 1:6e512faaa17c 46 epCallback[5] = &USBHAL::EP3_IN_callback;
mjoun 1:6e512faaa17c 47
mjoun 1:6e512faaa17c 48 // Enable power and clocking
mjoun 1:6e512faaa17c 49 RCC->AHB1ENR |= RCC_AHB1ENR_GPIOAEN;
mjoun 1:6e512faaa17c 50
mjoun 1:6e512faaa17c 51 #if defined(TARGET_STM32F407VG) || defined(TARGET_STM32F401RE) || defined(TARGET_STM32F411RE) || defined(TARGET_STM32F429ZI)
mjoun 1:6e512faaa17c 52 pin_function(PA_8, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
mjoun 1:6e512faaa17c 53 pin_function(PA_9, STM_PIN_DATA(STM_MODE_INPUT, GPIO_PULLDOWN, GPIO_AF10_OTG_FS));
mjoun 1:6e512faaa17c 54 pin_function(PA_10, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_PULLUP, GPIO_AF10_OTG_FS));
mjoun 1:6e512faaa17c 55 pin_function(PA_11, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
mjoun 1:6e512faaa17c 56 pin_function(PA_12, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF10_OTG_FS));
mjoun 1:6e512faaa17c 57 #else
mjoun 1:6e512faaa17c 58 pin_function(PA_8, STM_PIN_DATA(2, 10));
mjoun 1:6e512faaa17c 59 pin_function(PA_9, STM_PIN_DATA(0, 0));
mjoun 1:6e512faaa17c 60 pin_function(PA_10, STM_PIN_DATA(2, 10));
mjoun 1:6e512faaa17c 61 pin_function(PA_11, STM_PIN_DATA(2, 10));
mjoun 1:6e512faaa17c 62 pin_function(PA_12, STM_PIN_DATA(2, 10));
mjoun 1:6e512faaa17c 63
mjoun 1:6e512faaa17c 64 // Set ID pin to open drain with pull-up resistor
mjoun 1:6e512faaa17c 65 pin_mode(PA_10, OpenDrain);
mjoun 1:6e512faaa17c 66 GPIOA->PUPDR &= ~(0x3 << 20);
mjoun 1:6e512faaa17c 67 GPIOA->PUPDR |= 1 << 20;
mjoun 1:6e512faaa17c 68
mjoun 1:6e512faaa17c 69 // Set VBUS pin to open drain
mjoun 1:6e512faaa17c 70 pin_mode(PA_9, OpenDrain);
mjoun 1:6e512faaa17c 71 #endif
mjoun 1:6e512faaa17c 72
mjoun 1:6e512faaa17c 73 RCC->AHB2ENR |= RCC_AHB2ENR_OTGFSEN;
mjoun 1:6e512faaa17c 74
mjoun 1:6e512faaa17c 75 // Enable interrupts
mjoun 1:6e512faaa17c 76 OTG_FS->GREGS.GAHBCFG |= (1 << 0);
mjoun 1:6e512faaa17c 77
mjoun 1:6e512faaa17c 78 // Turnaround time to maximum value - too small causes packet loss
mjoun 1:6e512faaa17c 79 OTG_FS->GREGS.GUSBCFG |= (0xF << 10);
mjoun 1:6e512faaa17c 80
mjoun 1:6e512faaa17c 81 // Unmask global interrupts
mjoun 1:6e512faaa17c 82 OTG_FS->GREGS.GINTMSK |= (1 << 3) | // SOF
mjoun 1:6e512faaa17c 83 (1 << 4) | // RX FIFO not empty
mjoun 1:6e512faaa17c 84 (1 << 12); // USB reset
mjoun 1:6e512faaa17c 85
mjoun 1:6e512faaa17c 86 OTG_FS->DREGS.DCFG |= (0x3 << 0) | // Full speed
mjoun 1:6e512faaa17c 87 (1 << 2); // Non-zero-length status OUT handshake
mjoun 1:6e512faaa17c 88
mjoun 1:6e512faaa17c 89 OTG_FS->GREGS.GCCFG |= (1 << 19) | // Enable VBUS sensing
mjoun 1:6e512faaa17c 90 (1 << 16); // Power Up
mjoun 1:6e512faaa17c 91
mjoun 1:6e512faaa17c 92 instance = this;
mjoun 1:6e512faaa17c 93 NVIC_SetVector(OTG_FS_IRQn, (uint32_t)&_usbisr);
mjoun 1:6e512faaa17c 94 NVIC_SetPriority(OTG_FS_IRQn, 1);
mjoun 1:6e512faaa17c 95 }
mjoun 1:6e512faaa17c 96
mjoun 1:6e512faaa17c 97 USBHAL::~USBHAL(void) {
mjoun 1:6e512faaa17c 98 }
mjoun 1:6e512faaa17c 99
mjoun 1:6e512faaa17c 100 void USBHAL::connect(void) {
mjoun 1:6e512faaa17c 101 NVIC_EnableIRQ(OTG_FS_IRQn);
mjoun 1:6e512faaa17c 102 }
mjoun 1:6e512faaa17c 103
mjoun 1:6e512faaa17c 104 void USBHAL::disconnect(void) {
mjoun 1:6e512faaa17c 105 NVIC_DisableIRQ(OTG_FS_IRQn);
mjoun 1:6e512faaa17c 106 }
mjoun 1:6e512faaa17c 107
mjoun 1:6e512faaa17c 108 void USBHAL::configureDevice(void) {
mjoun 1:6e512faaa17c 109 // Not needed
mjoun 1:6e512faaa17c 110 }
mjoun 1:6e512faaa17c 111
mjoun 1:6e512faaa17c 112 void USBHAL::unconfigureDevice(void) {
mjoun 1:6e512faaa17c 113 // Not needed
mjoun 1:6e512faaa17c 114 }
mjoun 1:6e512faaa17c 115
mjoun 1:6e512faaa17c 116 void USBHAL::setAddress(uint8_t address) {
mjoun 1:6e512faaa17c 117 OTG_FS->DREGS.DCFG |= (address << 4);
mjoun 1:6e512faaa17c 118 EP0write(0, 0);
mjoun 1:6e512faaa17c 119 }
mjoun 1:6e512faaa17c 120
mjoun 1:6e512faaa17c 121 bool USBHAL::realiseEndpoint(uint8_t endpoint, uint32_t maxPacket,
mjoun 1:6e512faaa17c 122 uint32_t flags) {
mjoun 1:6e512faaa17c 123 uint32_t epIndex = endpoint >> 1;
mjoun 1:6e512faaa17c 124
mjoun 1:6e512faaa17c 125 uint32_t type;
mjoun 1:6e512faaa17c 126 switch (endpoint) {
mjoun 1:6e512faaa17c 127 case EP0IN:
mjoun 1:6e512faaa17c 128 case EP0OUT:
mjoun 1:6e512faaa17c 129 type = 0;
mjoun 1:6e512faaa17c 130 break;
mjoun 1:6e512faaa17c 131 case EPISO_IN:
mjoun 1:6e512faaa17c 132 case EPISO_OUT:
mjoun 1:6e512faaa17c 133 type = 1;
mjoun 1:6e512faaa17c 134 case EPBULK_IN:
mjoun 1:6e512faaa17c 135 case EPBULK_OUT:
mjoun 1:6e512faaa17c 136 type = 2;
mjoun 1:6e512faaa17c 137 break;
mjoun 1:6e512faaa17c 138 case EPINT_IN:
mjoun 1:6e512faaa17c 139 case EPINT_OUT:
mjoun 1:6e512faaa17c 140 type = 3;
mjoun 1:6e512faaa17c 141 break;
mjoun 1:6e512faaa17c 142 }
mjoun 1:6e512faaa17c 143
mjoun 1:6e512faaa17c 144 // Generic in or out EP controls
mjoun 1:6e512faaa17c 145 uint32_t control = (maxPacket << 0) | // Packet size
mjoun 1:6e512faaa17c 146 (1 << 15) | // Active endpoint
mjoun 1:6e512faaa17c 147 (type << 18); // Endpoint type
mjoun 1:6e512faaa17c 148
mjoun 1:6e512faaa17c 149 if (endpoint & 0x1) { // In Endpoint
mjoun 1:6e512faaa17c 150 // Set up the Tx FIFO
mjoun 1:6e512faaa17c 151 if (endpoint == EP0IN) {
mjoun 1:6e512faaa17c 152 OTG_FS->GREGS.DIEPTXF0_HNPTXFSIZ = ((maxPacket >> 2) << 16) |
mjoun 1:6e512faaa17c 153 (bufferEnd << 0);
mjoun 1:6e512faaa17c 154 }
mjoun 1:6e512faaa17c 155 else {
mjoun 1:6e512faaa17c 156 OTG_FS->GREGS.DIEPTXF[epIndex - 1] = ((maxPacket >> 2) << 16) |
mjoun 1:6e512faaa17c 157 (bufferEnd << 0);
mjoun 1:6e512faaa17c 158 }
mjoun 1:6e512faaa17c 159 bufferEnd += maxPacket >> 2;
mjoun 1:6e512faaa17c 160
mjoun 1:6e512faaa17c 161 // Set the In EP specific control settings
mjoun 1:6e512faaa17c 162 if (endpoint != EP0IN) {
mjoun 1:6e512faaa17c 163 control |= (1 << 28); // SD0PID
mjoun 1:6e512faaa17c 164 }
mjoun 1:6e512faaa17c 165
mjoun 1:6e512faaa17c 166 control |= (epIndex << 22) | // TxFIFO index
mjoun 1:6e512faaa17c 167 (1 << 27); // SNAK
mjoun 1:6e512faaa17c 168 OTG_FS->INEP_REGS[epIndex].DIEPCTL = control;
mjoun 1:6e512faaa17c 169
mjoun 1:6e512faaa17c 170 // Unmask the interrupt
mjoun 1:6e512faaa17c 171 OTG_FS->DREGS.DAINTMSK |= (1 << epIndex);
mjoun 1:6e512faaa17c 172 }
mjoun 1:6e512faaa17c 173 else { // Out endpoint
mjoun 1:6e512faaa17c 174 // Set the out EP specific control settings
mjoun 1:6e512faaa17c 175 control |= (1 << 26); // CNAK
mjoun 1:6e512faaa17c 176 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL = control;
mjoun 1:6e512faaa17c 177
mjoun 1:6e512faaa17c 178 // Unmask the interrupt
mjoun 1:6e512faaa17c 179 OTG_FS->DREGS.DAINTMSK |= (1 << (epIndex + 16));
mjoun 1:6e512faaa17c 180 }
mjoun 1:6e512faaa17c 181 return true;
mjoun 1:6e512faaa17c 182 }
mjoun 1:6e512faaa17c 183
mjoun 1:6e512faaa17c 184 // read setup packet
mjoun 1:6e512faaa17c 185 void USBHAL::EP0setup(uint8_t *buffer) {
mjoun 1:6e512faaa17c 186 memcpy(buffer, setupBuffer, MAX_PACKET_SIZE_EP0);
mjoun 1:6e512faaa17c 187 }
mjoun 1:6e512faaa17c 188
mjoun 1:6e512faaa17c 189 void USBHAL::EP0readStage(void) {
mjoun 1:6e512faaa17c 190 }
mjoun 1:6e512faaa17c 191
mjoun 1:6e512faaa17c 192 void USBHAL::EP0read(void) {
mjoun 1:6e512faaa17c 193 }
mjoun 1:6e512faaa17c 194
mjoun 1:6e512faaa17c 195 uint32_t USBHAL::EP0getReadResult(uint8_t *buffer) {
mjoun 1:6e512faaa17c 196 uint32_t* buffer32 = (uint32_t *) buffer;
mjoun 1:6e512faaa17c 197 uint32_t length = rxFifoCount;
mjoun 1:6e512faaa17c 198 for (uint32_t i = 0; i < length; i += 4) {
mjoun 1:6e512faaa17c 199 buffer32[i >> 2] = OTG_FS->FIFO[0][0];
mjoun 1:6e512faaa17c 200 }
mjoun 1:6e512faaa17c 201
mjoun 1:6e512faaa17c 202 rxFifoCount = 0;
mjoun 1:6e512faaa17c 203 return length;
mjoun 1:6e512faaa17c 204 }
mjoun 1:6e512faaa17c 205
mjoun 1:6e512faaa17c 206 void USBHAL::EP0write(uint8_t *buffer, uint32_t size) {
mjoun 1:6e512faaa17c 207 endpointWrite(0, buffer, size);
mjoun 1:6e512faaa17c 208 }
mjoun 1:6e512faaa17c 209
mjoun 1:6e512faaa17c 210 void USBHAL::EP0getWriteResult(void) {
mjoun 1:6e512faaa17c 211 }
mjoun 1:6e512faaa17c 212
mjoun 1:6e512faaa17c 213 void USBHAL::EP0stall(void) {
mjoun 1:6e512faaa17c 214 // If we stall the out endpoint here then we have problems transferring
mjoun 1:6e512faaa17c 215 // and setup requests after the (stalled) get device qualifier requests.
mjoun 1:6e512faaa17c 216 // TODO: Find out if this is correct behavior, or whether we are doing
mjoun 1:6e512faaa17c 217 // something else wrong
mjoun 1:6e512faaa17c 218 stallEndpoint(EP0IN);
mjoun 1:6e512faaa17c 219 // stallEndpoint(EP0OUT);
mjoun 1:6e512faaa17c 220 }
mjoun 1:6e512faaa17c 221
mjoun 1:6e512faaa17c 222 EP_STATUS USBHAL::endpointRead(uint8_t endpoint, uint32_t maximumSize) {
mjoun 1:6e512faaa17c 223 uint32_t epIndex = endpoint >> 1;
mjoun 1:6e512faaa17c 224 uint32_t size = (1 << 19) | // 1 packet
mjoun 1:6e512faaa17c 225 (maximumSize << 0); // Packet size
mjoun 1:6e512faaa17c 226 // if (endpoint == EP0OUT) {
mjoun 1:6e512faaa17c 227 size |= (1 << 29); // 1 setup packet
mjoun 1:6e512faaa17c 228 // }
mjoun 1:6e512faaa17c 229 OTG_FS->OUTEP_REGS[epIndex].DOEPTSIZ = size;
mjoun 1:6e512faaa17c 230 OTG_FS->OUTEP_REGS[epIndex].DOEPCTL |= (1 << 31) | // Enable endpoint
mjoun 1:6e512faaa17c 231 (1 << 26); // Clear NAK
mjoun 1:6e512faaa17c 232
mjoun 1:6e512faaa17c 233 epComplete &= ~(1 << endpoint);
mjoun 1:6e512faaa17c 234 return EP_PENDING;
mjoun 1:6e512faaa17c 235 }
mjoun 1:6e512faaa17c 236
mjoun 1:6e512faaa17c 237 EP_STATUS USBHAL::endpointReadResult(uint8_t endpoint, uint8_t * buffer, uint32_t *bytesRead) {
mjoun 1:6e512faaa17c 238 if (!(epComplete & (1 << endpoint))) {
mjoun 1:6e512faaa17c 239 return EP_PENDING;
mjoun 1:6e512faaa17c 240 }
mjoun 1:6e512faaa17c 241
mjoun 1:6e512faaa17c 242 uint32_t* buffer32 = (uint32_t *) buffer;
mjoun 1:6e512faaa17c 243 uint32_t length = rxFifoCount;
mjoun 1:6e512faaa17c 244 for (uint32_t i = 0; i < length; i += 4) {
mjoun 1:6e512faaa17c 245 buffer32[i >> 2] = OTG_FS->FIFO[endpoint >> 1][0];
mjoun 1:6e512faaa17c 246 }
mjoun 1:6e512faaa17c 247 rxFifoCount = 0;
mjoun 1:6e512faaa17c 248 *bytesRead = length;
mjoun 1:6e512faaa17c 249 return EP_COMPLETED;
mjoun 1:6e512faaa17c 250 }
mjoun 1:6e512faaa17c 251
mjoun 1:6e512faaa17c 252 EP_STATUS USBHAL::endpointWrite(uint8_t endpoint, uint8_t *data, uint32_t size) {
mjoun 1:6e512faaa17c 253 uint32_t epIndex = endpoint >> 1;
mjoun 1:6e512faaa17c 254 OTG_FS->INEP_REGS[epIndex].DIEPTSIZ = (1 << 19) | // 1 packet
mjoun 1:6e512faaa17c 255 (size << 0); // Size of packet
mjoun 1:6e512faaa17c 256 OTG_FS->INEP_REGS[epIndex].DIEPCTL |= (1 << 31) | // Enable endpoint
mjoun 1:6e512faaa17c 257 (1 << 26); // CNAK
mjoun 1:6e512faaa17c 258 OTG_FS->DREGS.DIEPEMPMSK = (1 << epIndex);
mjoun 1:6e512faaa17c 259
mjoun 1:6e512faaa17c 260 while ((OTG_FS->INEP_REGS[epIndex].DTXFSTS & 0XFFFF) < ((size + 3) >> 2));
mjoun 1:6e512faaa17c 261
mjoun 1:6e512faaa17c 262 for (uint32_t i=0; i<(size + 3) >> 2; i++, data+=4) {
mjoun 1:6e512faaa17c 263 OTG_FS->FIFO[epIndex][0] = *(uint32_t *)data;
mjoun 1:6e512faaa17c 264 }
mjoun 1:6e512faaa17c 265
mjoun 1:6e512faaa17c 266 epComplete &= ~(1 << endpoint);
mjoun 1:6e512faaa17c 267
mjoun 1:6e512faaa17c 268 return EP_PENDING;
mjoun 1:6e512faaa17c 269 }
mjoun 1:6e512faaa17c 270
mjoun 1:6e512faaa17c 271 EP_STATUS USBHAL::endpointWriteResult(uint8_t endpoint) {
mjoun 1:6e512faaa17c 272 if (epComplete & (1 << endpoint)) {
mjoun 1:6e512faaa17c 273 epComplete &= ~(1 << endpoint);
mjoun 1:6e512faaa17c 274 return EP_COMPLETED;
mjoun 1:6e512faaa17c 275 }
mjoun 1:6e512faaa17c 276
mjoun 1:6e512faaa17c 277 return EP_PENDING;
mjoun 1:6e512faaa17c 278 }
mjoun 1:6e512faaa17c 279
mjoun 1:6e512faaa17c 280 void USBHAL::stallEndpoint(uint8_t endpoint) {
mjoun 1:6e512faaa17c 281 if (endpoint & 0x1) { // In EP
mjoun 1:6e512faaa17c 282 OTG_FS->INEP_REGS[endpoint >> 1].DIEPCTL |= (1 << 30) | // Disable
mjoun 1:6e512faaa17c 283 (1 << 21); // Stall
mjoun 1:6e512faaa17c 284 }
mjoun 1:6e512faaa17c 285 else { // Out EP
mjoun 1:6e512faaa17c 286 OTG_FS->DREGS.DCTL |= (1 << 9); // Set global out NAK
mjoun 1:6e512faaa17c 287 OTG_FS->OUTEP_REGS[endpoint >> 1].DOEPCTL |= (1 << 30) | // Disable
mjoun 1:6e512faaa17c 288 (1 << 21); // Stall
mjoun 1:6e512faaa17c 289 }
mjoun 1:6e512faaa17c 290 }
mjoun 1:6e512faaa17c 291
mjoun 1:6e512faaa17c 292 void USBHAL::unstallEndpoint(uint8_t endpoint) {
mjoun 1:6e512faaa17c 293
mjoun 1:6e512faaa17c 294 }
mjoun 1:6e512faaa17c 295
mjoun 1:6e512faaa17c 296 bool USBHAL::getEndpointStallState(uint8_t endpoint) {
mjoun 1:6e512faaa17c 297 return false;
mjoun 1:6e512faaa17c 298 }
mjoun 1:6e512faaa17c 299
mjoun 1:6e512faaa17c 300 void USBHAL::remoteWakeup(void) {
mjoun 1:6e512faaa17c 301 }
mjoun 1:6e512faaa17c 302
mjoun 1:6e512faaa17c 303
mjoun 1:6e512faaa17c 304 void USBHAL::_usbisr(void) {
mjoun 1:6e512faaa17c 305 instance->usbisr();
mjoun 1:6e512faaa17c 306 }
mjoun 1:6e512faaa17c 307
mjoun 1:6e512faaa17c 308
mjoun 1:6e512faaa17c 309 void USBHAL::usbisr(void) {
mjoun 1:6e512faaa17c 310 if (OTG_FS->GREGS.GINTSTS & (1 << 11)) { // USB Suspend
mjoun 1:6e512faaa17c 311 suspendStateChanged(1);
mjoun 1:6e512faaa17c 312 };
mjoun 1:6e512faaa17c 313
mjoun 1:6e512faaa17c 314 if (OTG_FS->GREGS.GINTSTS & (1 << 12)) { // USB Reset
mjoun 1:6e512faaa17c 315 suspendStateChanged(0);
mjoun 1:6e512faaa17c 316
mjoun 1:6e512faaa17c 317 // Set SNAK bits
mjoun 1:6e512faaa17c 318 OTG_FS->OUTEP_REGS[0].DOEPCTL |= (1 << 27);
mjoun 1:6e512faaa17c 319 OTG_FS->OUTEP_REGS[1].DOEPCTL |= (1 << 27);
mjoun 1:6e512faaa17c 320 OTG_FS->OUTEP_REGS[2].DOEPCTL |= (1 << 27);
mjoun 1:6e512faaa17c 321 OTG_FS->OUTEP_REGS[3].DOEPCTL |= (1 << 27);
mjoun 1:6e512faaa17c 322
mjoun 1:6e512faaa17c 323 OTG_FS->DREGS.DIEPMSK = (1 << 0);
mjoun 1:6e512faaa17c 324
mjoun 1:6e512faaa17c 325 bufferEnd = 0;
mjoun 1:6e512faaa17c 326
mjoun 1:6e512faaa17c 327 // Set the receive FIFO size
mjoun 1:6e512faaa17c 328 OTG_FS->GREGS.GRXFSIZ = rxFifoSize >> 2;
mjoun 1:6e512faaa17c 329 bufferEnd += rxFifoSize >> 2;
mjoun 1:6e512faaa17c 330
mjoun 1:6e512faaa17c 331 // Create the endpoints, and wait for setup packets on out EP0
mjoun 1:6e512faaa17c 332 realiseEndpoint(EP0IN, MAX_PACKET_SIZE_EP0, 0);
mjoun 1:6e512faaa17c 333 realiseEndpoint(EP0OUT, MAX_PACKET_SIZE_EP0, 0);
mjoun 1:6e512faaa17c 334 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
mjoun 1:6e512faaa17c 335
mjoun 1:6e512faaa17c 336 OTG_FS->GREGS.GINTSTS = (1 << 12);
mjoun 1:6e512faaa17c 337 }
mjoun 1:6e512faaa17c 338
mjoun 1:6e512faaa17c 339 if (OTG_FS->GREGS.GINTSTS & (1 << 4)) { // RX FIFO not empty
mjoun 1:6e512faaa17c 340 uint32_t status = OTG_FS->GREGS.GRXSTSP;
mjoun 1:6e512faaa17c 341
mjoun 1:6e512faaa17c 342 uint32_t endpoint = (status & 0xF) << 1;
mjoun 1:6e512faaa17c 343 uint32_t length = (status >> 4) & 0x7FF;
mjoun 1:6e512faaa17c 344 uint32_t type = (status >> 17) & 0xF;
mjoun 1:6e512faaa17c 345
mjoun 1:6e512faaa17c 346 rxFifoCount = length;
mjoun 1:6e512faaa17c 347
mjoun 1:6e512faaa17c 348 if (type == 0x6) {
mjoun 1:6e512faaa17c 349 // Setup packet
mjoun 1:6e512faaa17c 350 for (uint32_t i=0; i<length; i+=4) {
mjoun 1:6e512faaa17c 351 setupBuffer[i >> 2] = OTG_FS->FIFO[0][i >> 2];
mjoun 1:6e512faaa17c 352 }
mjoun 1:6e512faaa17c 353 rxFifoCount = 0;
mjoun 1:6e512faaa17c 354 }
mjoun 1:6e512faaa17c 355
mjoun 1:6e512faaa17c 356 if (type == 0x4) {
mjoun 1:6e512faaa17c 357 // Setup complete
mjoun 1:6e512faaa17c 358 EP0setupCallback();
mjoun 1:6e512faaa17c 359 endpointRead(EP0OUT, MAX_PACKET_SIZE_EP0);
mjoun 1:6e512faaa17c 360 }
mjoun 1:6e512faaa17c 361
mjoun 1:6e512faaa17c 362 if (type == 0x2) {
mjoun 1:6e512faaa17c 363 // Out packet
mjoun 1:6e512faaa17c 364 if (endpoint == EP0OUT) {
mjoun 1:6e512faaa17c 365 EP0out();
mjoun 1:6e512faaa17c 366 }
mjoun 1:6e512faaa17c 367 else {
mjoun 1:6e512faaa17c 368 epComplete |= (1 << endpoint);
mjoun 1:6e512faaa17c 369 if ((instance->*(epCallback[endpoint - 2]))()) {
mjoun 1:6e512faaa17c 370 epComplete &= (1 << endpoint);
mjoun 1:6e512faaa17c 371 }
mjoun 1:6e512faaa17c 372 }
mjoun 1:6e512faaa17c 373 }
mjoun 1:6e512faaa17c 374
mjoun 1:6e512faaa17c 375 for (uint32_t i=0; i<rxFifoCount; i+=4) {
mjoun 1:6e512faaa17c 376 (void) OTG_FS->FIFO[0][0];
mjoun 1:6e512faaa17c 377 }
mjoun 1:6e512faaa17c 378 OTG_FS->GREGS.GINTSTS = (1 << 4);
mjoun 1:6e512faaa17c 379 }
mjoun 1:6e512faaa17c 380
mjoun 1:6e512faaa17c 381 if (OTG_FS->GREGS.GINTSTS & (1 << 18)) { // In endpoint interrupt
mjoun 1:6e512faaa17c 382 // Loop through the in endpoints
mjoun 1:6e512faaa17c 383 for (uint32_t i=0; i<4; i++) {
mjoun 1:6e512faaa17c 384 if (OTG_FS->DREGS.DAINT & (1 << i)) { // Interrupt is on endpoint
mjoun 1:6e512faaa17c 385
mjoun 1:6e512faaa17c 386 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 7)) {// Tx FIFO empty
mjoun 1:6e512faaa17c 387 // If the Tx FIFO is empty on EP0 we need to send a further
mjoun 1:6e512faaa17c 388 // packet, so call EP0in()
mjoun 1:6e512faaa17c 389 if (i == 0) {
mjoun 1:6e512faaa17c 390 EP0in();
mjoun 1:6e512faaa17c 391 }
mjoun 1:6e512faaa17c 392 // Clear the interrupt
mjoun 1:6e512faaa17c 393 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 7);
mjoun 1:6e512faaa17c 394 // Stop firing Tx empty interrupts
mjoun 1:6e512faaa17c 395 // Will get turned on again if another write is called
mjoun 1:6e512faaa17c 396 OTG_FS->DREGS.DIEPEMPMSK &= ~(1 << i);
mjoun 1:6e512faaa17c 397 }
mjoun 1:6e512faaa17c 398
mjoun 1:6e512faaa17c 399 // If the transfer is complete
mjoun 1:6e512faaa17c 400 if (OTG_FS->INEP_REGS[i].DIEPINT & (1 << 0)) { // Tx Complete
mjoun 1:6e512faaa17c 401 epComplete |= (1 << (1 + (i << 1)));
mjoun 1:6e512faaa17c 402 OTG_FS->INEP_REGS[i].DIEPINT = (1 << 0);
mjoun 1:6e512faaa17c 403 }
mjoun 1:6e512faaa17c 404 }
mjoun 1:6e512faaa17c 405 }
mjoun 1:6e512faaa17c 406 OTG_FS->GREGS.GINTSTS = (1 << 18);
mjoun 1:6e512faaa17c 407 }
mjoun 1:6e512faaa17c 408
mjoun 1:6e512faaa17c 409 if (OTG_FS->GREGS.GINTSTS & (1 << 3)) { // Start of frame
mjoun 1:6e512faaa17c 410 SOF((OTG_FS->GREGS.GRXSTSR >> 17) & 0xF);
mjoun 1:6e512faaa17c 411 OTG_FS->GREGS.GINTSTS = (1 << 3);
mjoun 1:6e512faaa17c 412 }
mjoun 1:6e512faaa17c 413 }
mjoun 1:6e512faaa17c 414
mjoun 1:6e512faaa17c 415
mjoun 1:6e512faaa17c 416 #endif