Michaël Nagels / project_bachproef2

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source/platform/stm32_bluenrg_ble_dma_lp.c@213:edfc72290462, 2016-03-05 (annotated)

Committer:
mjnagels
Date:
Sat Mar 05 09:49:47 2016 +0000
Revision:
213:edfc72290462
Parent:
132:51056160fa4a 
used bikeservice

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Wolfgang Betz 132:51056160fa4a 1 /**
Wolfgang Betz 132:51056160fa4a 2 ******************************************************************************
Wolfgang Betz 132:51056160fa4a 3 * @file stm32_bluenrg_ble_dma_lp.c
Wolfgang Betz 132:51056160fa4a 4 * @author CL
Wolfgang Betz 132:51056160fa4a 5 * @version V1.0.0
Wolfgang Betz 132:51056160fa4a 6 * @date 04-July-2014
Wolfgang Betz 132:51056160fa4a 7 * @brief
Wolfgang Betz 132:51056160fa4a 8 ******************************************************************************
Wolfgang Betz 132:51056160fa4a 9 * @attention
Wolfgang Betz 132:51056160fa4a 10 *
Wolfgang Betz 132:51056160fa4a 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
Wolfgang Betz 132:51056160fa4a 12 *
Wolfgang Betz 132:51056160fa4a 13 * Redistribution and use in source and binary forms, with or without modification,
Wolfgang Betz 132:51056160fa4a 14 * are permitted provided that the following conditions are met:
Wolfgang Betz 132:51056160fa4a 15 * 1. Redistributions of source code must retain the above copyright notice,
Wolfgang Betz 132:51056160fa4a 16 * this list of conditions and the following disclaimer.
Wolfgang Betz 132:51056160fa4a 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
Wolfgang Betz 132:51056160fa4a 18 * this list of conditions and the following disclaimer in the documentation
Wolfgang Betz 132:51056160fa4a 19 * and/or other materials provided with the distribution.
Wolfgang Betz 132:51056160fa4a 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Wolfgang Betz 132:51056160fa4a 21 * may be used to endorse or promote products derived from this software
Wolfgang Betz 132:51056160fa4a 22 * without specific prior written permission.
Wolfgang Betz 132:51056160fa4a 23 *
Wolfgang Betz 132:51056160fa4a 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Wolfgang Betz 132:51056160fa4a 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Wolfgang Betz 132:51056160fa4a 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Wolfgang Betz 132:51056160fa4a 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Wolfgang Betz 132:51056160fa4a 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Wolfgang Betz 132:51056160fa4a 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Wolfgang Betz 132:51056160fa4a 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Wolfgang Betz 132:51056160fa4a 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Wolfgang Betz 132:51056160fa4a 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Wolfgang Betz 132:51056160fa4a 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Wolfgang Betz 132:51056160fa4a 34 *
Wolfgang Betz 132:51056160fa4a 35 ******************************************************************************
Wolfgang Betz 132:51056160fa4a 36 */
Wolfgang Betz 132:51056160fa4a 37
Wolfgang Betz 132:51056160fa4a 38 // ANDREA -- FIXME: to exclude from building when DMA is disabled
Wolfgang Betz 132:51056160fa4a 39 #ifdef __DMA_LP__
Wolfgang Betz 132:51056160fa4a 40
Wolfgang Betz 132:51056160fa4a 41 /* Includes ------------------------------------------------------------------*/
Wolfgang Betz 132:51056160fa4a 42 #include "stm32_bluenrg_ble_dma_lp.h"
Wolfgang Betz 132:51056160fa4a 43 #include "hci_const.h"
Wolfgang Betz 132:51056160fa4a 44
Wolfgang Betz 132:51056160fa4a 45 /** @addtogroup BSP
Wolfgang Betz 132:51056160fa4a 46 * @{
Wolfgang Betz 132:51056160fa4a 47 */
Wolfgang Betz 132:51056160fa4a 48
Wolfgang Betz 132:51056160fa4a 49 /** @addtogroup X-NUCLEO-IDB04A1
Wolfgang Betz 132:51056160fa4a 50 * @{
Wolfgang Betz 132:51056160fa4a 51 */
Wolfgang Betz 132:51056160fa4a 52
Wolfgang Betz 132:51056160fa4a 53 /** @defgroup STM32_BLUENRG_BLE_DMA_LP
Wolfgang Betz 132:51056160fa4a 54 * @{
Wolfgang Betz 132:51056160fa4a 55 */
Wolfgang Betz 132:51056160fa4a 56
Wolfgang Betz 132:51056160fa4a 57 /** @defgroup STM32_BLUENRG_BLE_DMA_LP_Private_Defines
Wolfgang Betz 132:51056160fa4a 58 * @{
Wolfgang Betz 132:51056160fa4a 59 */
Wolfgang Betz 132:51056160fa4a 60
Wolfgang Betz 132:51056160fa4a 61 #define TEST_TX_BUFFER_LIMITATION 0
Wolfgang Betz 132:51056160fa4a 62 #define MAX_TX_BUFFER_SIZE 0x7F
Wolfgang Betz 132:51056160fa4a 63 #define BLUENRG_READY_STATE 0x02
Wolfgang Betz 132:51056160fa4a 64
Wolfgang Betz 132:51056160fa4a 65 #define HEADER_SIZE 5
Wolfgang Betz 132:51056160fa4a 66 #define MAX_BUFFER_SIZE 255
Wolfgang Betz 132:51056160fa4a 67
Wolfgang Betz 132:51056160fa4a 68 /**
Wolfgang Betz 132:51056160fa4a 69 * @}
Wolfgang Betz 132:51056160fa4a 70 */
Wolfgang Betz 132:51056160fa4a 71
Wolfgang Betz 132:51056160fa4a 72 /** @defgroup STM32_BLUENRG_BLE_DMA_LP_Private_Types
Wolfgang Betz 132:51056160fa4a 73 * @{
Wolfgang Betz 132:51056160fa4a 74 */
Wolfgang Betz 132:51056160fa4a 75
Wolfgang Betz 132:51056160fa4a 76 typedef enum
Wolfgang Betz 132:51056160fa4a 77 {
Wolfgang Betz 132:51056160fa4a 78 SPI_HEADER_TRANSMIT,
Wolfgang Betz 132:51056160fa4a 79 SPI_PAYLOAD_TRANSMIT
Wolfgang Betz 132:51056160fa4a 80 } SPI_TRANSMIT_REQUEST_t;
Wolfgang Betz 132:51056160fa4a 81
Wolfgang Betz 132:51056160fa4a 82 typedef enum
Wolfgang Betz 132:51056160fa4a 83 {
Wolfgang Betz 132:51056160fa4a 84 SPI_HEADER_TRANSMITTED,
Wolfgang Betz 132:51056160fa4a 85 SPI_PAYLOAD_TRANSMITTED
Wolfgang Betz 132:51056160fa4a 86 } SPI_TRANSMIT_EVENT_t;
Wolfgang Betz 132:51056160fa4a 87
Wolfgang Betz 132:51056160fa4a 88 typedef enum
Wolfgang Betz 132:51056160fa4a 89 {
Wolfgang Betz 132:51056160fa4a 90 SPI_REQUEST_VALID_HEADER_FOR_RX,
Wolfgang Betz 132:51056160fa4a 91 SPI_REQUEST_VALID_HEADER_FOR_TX,
Wolfgang Betz 132:51056160fa4a 92 SPI_REQUEST_PAYLOAD
Wolfgang Betz 132:51056160fa4a 93 } SPI_RECEIVE_REQUEST_t;
Wolfgang Betz 132:51056160fa4a 94
Wolfgang Betz 132:51056160fa4a 95 typedef enum
Wolfgang Betz 132:51056160fa4a 96 {
Wolfgang Betz 132:51056160fa4a 97 SPI_CHECK_RECEIVED_HEADER_FOR_RX,
Wolfgang Betz 132:51056160fa4a 98 SPI_CHECK_RECEIVED_HEADER_FOR_TX,
Wolfgang Betz 132:51056160fa4a 99 SPI_RECEIVE_END
Wolfgang Betz 132:51056160fa4a 100 } SPI_RECEIVE_EVENT_t;
Wolfgang Betz 132:51056160fa4a 101
Wolfgang Betz 132:51056160fa4a 102 typedef enum
Wolfgang Betz 132:51056160fa4a 103 {
Wolfgang Betz 132:51056160fa4a 104 SPI_AVAILABLE,
Wolfgang Betz 132:51056160fa4a 105 SPI_BUSY
Wolfgang Betz 132:51056160fa4a 106 } SPI_PERIPHERAL_STATUS_t;
Wolfgang Betz 132:51056160fa4a 107
Wolfgang Betz 132:51056160fa4a 108 typedef struct
Wolfgang Betz 132:51056160fa4a 109 {
Wolfgang Betz 132:51056160fa4a 110 SPI_TRANSMIT_EVENT_t Spi_Transmit_Event;
Wolfgang Betz 132:51056160fa4a 111 uint8_t* header_data;
Wolfgang Betz 132:51056160fa4a 112 uint8_t* payload_data;
Wolfgang Betz 132:51056160fa4a 113 uint8_t header_size;
Wolfgang Betz 132:51056160fa4a 114 uint8_t payload_size;
Wolfgang Betz 132:51056160fa4a 115 uint8_t payload_size_to_transmit;
Wolfgang Betz 132:51056160fa4a 116 uint8_t packet_cont;
Wolfgang Betz 132:51056160fa4a 117 uint8_t RequestPending;
Wolfgang Betz 132:51056160fa4a 118 } SPI_Transmit_Context_t;
Wolfgang Betz 132:51056160fa4a 119
Wolfgang Betz 132:51056160fa4a 120 typedef struct
Wolfgang Betz 132:51056160fa4a 121 {
Wolfgang Betz 132:51056160fa4a 122 SPI_RECEIVE_EVENT_t Spi_Receive_Event;
Wolfgang Betz 132:51056160fa4a 123 uint16_t payload_len;
Wolfgang Betz 132:51056160fa4a 124 uint8_t* buffer;
Wolfgang Betz 132:51056160fa4a 125 uint8_t buffer_size;
Wolfgang Betz 132:51056160fa4a 126 } SPI_Receive_Context_t;
Wolfgang Betz 132:51056160fa4a 127
Wolfgang Betz 132:51056160fa4a 128 typedef struct
Wolfgang Betz 132:51056160fa4a 129 {
Wolfgang Betz 132:51056160fa4a 130 SPI_HandleTypeDef *hspi;
Wolfgang Betz 132:51056160fa4a 131 SPI_PERIPHERAL_STATUS_t Spi_Peripheral_State;
Wolfgang Betz 132:51056160fa4a 132 SPI_Receive_Context_t SPI_Receive_Context;
Wolfgang Betz 132:51056160fa4a 133 SPI_Transmit_Context_t SPI_Transmit_Context;
Wolfgang Betz 132:51056160fa4a 134 } SPI_Context_t;
Wolfgang Betz 132:51056160fa4a 135
Wolfgang Betz 132:51056160fa4a 136 /**
Wolfgang Betz 132:51056160fa4a 137 * @}
Wolfgang Betz 132:51056160fa4a 138 */
Wolfgang Betz 132:51056160fa4a 139
Wolfgang Betz 132:51056160fa4a 140 /** @defgroup STM32_BLUENRG_BLE_DMA_LP_Private_Variables
Wolfgang Betz 132:51056160fa4a 141 * @{
Wolfgang Betz 132:51056160fa4a 142 */
Wolfgang Betz 132:51056160fa4a 143
Wolfgang Betz 132:51056160fa4a 144 SPI_HandleTypeDef SpiHandle;
Wolfgang Betz 132:51056160fa4a 145 SPI_Context_t SPI_Context;
Wolfgang Betz 132:51056160fa4a 146
Wolfgang Betz 132:51056160fa4a 147 const uint8_t Write_Header_CMD[HEADER_SIZE] = {0x0a, 0x00, 0x00, 0x00, 0x00};
Wolfgang Betz 132:51056160fa4a 148 const uint8_t Read_Header_CMD[HEADER_SIZE] = {0x0b, 0x00, 0x00, 0x00, 0x00};
Wolfgang Betz 132:51056160fa4a 149 const uint8_t dummy_bytes = 0xFF;
Wolfgang Betz 132:51056160fa4a 150
Wolfgang Betz 132:51056160fa4a 151 uint8_t Received_Header[HEADER_SIZE];
Wolfgang Betz 132:51056160fa4a 152
Wolfgang Betz 132:51056160fa4a 153 #ifdef ENABLE_SPI_FIX
Wolfgang Betz 132:51056160fa4a 154 static uint8_t StartupTimerId;
Wolfgang Betz 132:51056160fa4a 155 #endif
Wolfgang Betz 132:51056160fa4a 156 static uint8_t TxRxTimerId;
Wolfgang Betz 132:51056160fa4a 157 volatile uint8_t ubnRFresetTimerLock;
Wolfgang Betz 132:51056160fa4a 158 pf_TIMER_TimerCallBack_t pTimerTxRxCallback;
Wolfgang Betz 132:51056160fa4a 159
Wolfgang Betz 132:51056160fa4a 160 /**
Wolfgang Betz 132:51056160fa4a 161 * @}
Wolfgang Betz 132:51056160fa4a 162 */
Wolfgang Betz 132:51056160fa4a 163
Wolfgang Betz 132:51056160fa4a 164 /** @defgroup STM32_BLUENRG_BLE_DMA_LP_Extern_Variables
Wolfgang Betz 132:51056160fa4a 165 * @{
Wolfgang Betz 132:51056160fa4a 166 */
Wolfgang Betz 132:51056160fa4a 167 extern uint8_t* HCI_read_packet;
Wolfgang Betz 132:51056160fa4a 168
Wolfgang Betz 132:51056160fa4a 169 /**
Wolfgang Betz 132:51056160fa4a 170 * @}
Wolfgang Betz 132:51056160fa4a 171 */
Wolfgang Betz 132:51056160fa4a 172
Wolfgang Betz 132:51056160fa4a 173 /** @defgroup STM32_BLUENRG_BLE_DMA_LP_Private_Function_Prototypes
Wolfgang Betz 132:51056160fa4a 174 * @{
Wolfgang Betz 132:51056160fa4a 175 */
Wolfgang Betz 132:51056160fa4a 176
Wolfgang Betz 132:51056160fa4a 177 /* Private function prototypes -----------------------------------------------*/
Wolfgang Betz 132:51056160fa4a 178 static void SPI_Transmit_Manager(SPI_TRANSMIT_REQUEST_t TransmitRequest);
Wolfgang Betz 132:51056160fa4a 179 static void SPI_Receive_Manager(SPI_RECEIVE_REQUEST_t ReceiveRequest);
Wolfgang Betz 132:51056160fa4a 180 static void set_irq_as_output(void);
Wolfgang Betz 132:51056160fa4a 181 static void set_irq_as_input(void);
Wolfgang Betz 132:51056160fa4a 182 static void Disable_SPI_Receiving_Path(void);
Wolfgang Betz 132:51056160fa4a 183 static void Enable_SPI_Receiving_Path(void);
Wolfgang Betz 132:51056160fa4a 184 static void Enable_SPI_CS(void);
Wolfgang Betz 132:51056160fa4a 185 static void Disable_SPI_CS(void);
Wolfgang Betz 132:51056160fa4a 186 static void DisableEnable_SPI_CS(void);
Wolfgang Betz 132:51056160fa4a 187 static void TransmitClosure(void);
Wolfgang Betz 132:51056160fa4a 188 static void ReceiveClosure(void);
Wolfgang Betz 132:51056160fa4a 189 static void ReceiveHeader(SPI_RECEIVE_EVENT_t ReceiveEvent, uint8_t * DataHeader);
Wolfgang Betz 132:51056160fa4a 190 static void WakeupBlueNRG(void);
Wolfgang Betz 132:51056160fa4a 191 static void TimerStartupCallback(void);
Wolfgang Betz 132:51056160fa4a 192 static void TimerTransmitCallback(void);
Wolfgang Betz 132:51056160fa4a 193 static void pf_nRFResetTimerCallBack(void);
Wolfgang Betz 132:51056160fa4a 194 static void TimerTxRxCallback(void);
Wolfgang Betz 132:51056160fa4a 195 static void ProcessEndOfReceive(void);
Wolfgang Betz 132:51056160fa4a 196
Wolfgang Betz 132:51056160fa4a 197 /**
Wolfgang Betz 132:51056160fa4a 198 * @}
Wolfgang Betz 132:51056160fa4a 199 */
Wolfgang Betz 132:51056160fa4a 200
Wolfgang Betz 132:51056160fa4a 201 /** @defgroup STM32_BLUENRG_BLE_DMA_LP_Exported_Functions
Wolfgang Betz 132:51056160fa4a 202 * @{
Wolfgang Betz 132:51056160fa4a 203 */
Wolfgang Betz 132:51056160fa4a 204
Wolfgang Betz 132:51056160fa4a 205 /**
Wolfgang Betz 132:51056160fa4a 206 * @brief This function notify when then BlueNRG nRESET may be released
Wolfgang Betz 132:51056160fa4a 207 * @param None
Wolfgang Betz 132:51056160fa4a 208 * @retval None
Wolfgang Betz 132:51056160fa4a 209 */
Wolfgang Betz 132:51056160fa4a 210 static void pf_nRFResetTimerCallBack(void)
Wolfgang Betz 132:51056160fa4a 211 {
Wolfgang Betz 132:51056160fa4a 212 ubnRFresetTimerLock = 0;
Wolfgang Betz 132:51056160fa4a 213
Wolfgang Betz 132:51056160fa4a 214 return;
Wolfgang Betz 132:51056160fa4a 215 }
Wolfgang Betz 132:51056160fa4a 216
Wolfgang Betz 132:51056160fa4a 217 /**
Wolfgang Betz 132:51056160fa4a 218 * @brief Timer callback to handle RxTx Timers
Wolfgang Betz 132:51056160fa4a 219 * @param None
Wolfgang Betz 132:51056160fa4a 220 * @retval None
Wolfgang Betz 132:51056160fa4a 221 */
Wolfgang Betz 132:51056160fa4a 222 static void TimerTxRxCallback(void)
Wolfgang Betz 132:51056160fa4a 223 {
Wolfgang Betz 132:51056160fa4a 224 pTimerTxRxCallback();
Wolfgang Betz 132:51056160fa4a 225
Wolfgang Betz 132:51056160fa4a 226 return;
Wolfgang Betz 132:51056160fa4a 227 }
Wolfgang Betz 132:51056160fa4a 228
Wolfgang Betz 132:51056160fa4a 229 /**
Wolfgang Betz 132:51056160fa4a 230 * @brief Close the receiver path
Wolfgang Betz 132:51056160fa4a 231 * @param None
Wolfgang Betz 132:51056160fa4a 232 * @retval None
Wolfgang Betz 132:51056160fa4a 233 */
Wolfgang Betz 132:51056160fa4a 234 static void ReceiveClosure(void)
Wolfgang Betz 132:51056160fa4a 235 {
Wolfgang Betz 132:51056160fa4a 236 /*
Wolfgang Betz 132:51056160fa4a 237 * Disable both DMA
Wolfgang Betz 132:51056160fa4a 238 */
Wolfgang Betz 132:51056160fa4a 239 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx);
Wolfgang Betz 132:51056160fa4a 240 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx);
Wolfgang Betz 132:51056160fa4a 241
Wolfgang Betz 132:51056160fa4a 242 /*
Wolfgang Betz 132:51056160fa4a 243 * Check if a command is pending
Wolfgang Betz 132:51056160fa4a 244 */
Wolfgang Betz 132:51056160fa4a 245 __disable_irq();
Wolfgang Betz 132:51056160fa4a 246 if(SPI_Context.SPI_Transmit_Context.RequestPending == TRUE)
Wolfgang Betz 132:51056160fa4a 247 {
Wolfgang Betz 132:51056160fa4a 248 SPI_Context.SPI_Transmit_Context.RequestPending = FALSE;
Wolfgang Betz 132:51056160fa4a 249 SPI_Context.Spi_Peripheral_State = SPI_BUSY;
Wolfgang Betz 132:51056160fa4a 250 Disable_SPI_Receiving_Path();
Wolfgang Betz 132:51056160fa4a 251 __enable_irq();
Wolfgang Betz 132:51056160fa4a 252 WakeupBlueNRG();
Wolfgang Betz 132:51056160fa4a 253 }
Wolfgang Betz 132:51056160fa4a 254 else
Wolfgang Betz 132:51056160fa4a 255 {
Wolfgang Betz 132:51056160fa4a 256 SPI_Context.Spi_Peripheral_State = SPI_AVAILABLE;
Wolfgang Betz 132:51056160fa4a 257 __enable_irq();
Wolfgang Betz 132:51056160fa4a 258 }
Wolfgang Betz 132:51056160fa4a 259
Wolfgang Betz 132:51056160fa4a 260 return;
Wolfgang Betz 132:51056160fa4a 261 }
Wolfgang Betz 132:51056160fa4a 262
Wolfgang Betz 132:51056160fa4a 263 /**
Wolfgang Betz 132:51056160fa4a 264 * @brief Delay Notification to the App to prevent dummy event read
Wolfgang Betz 132:51056160fa4a 265 * @param None
Wolfgang Betz 132:51056160fa4a 266 * @retval None
Wolfgang Betz 132:51056160fa4a 267 */
Wolfgang Betz 132:51056160fa4a 268 static void ProcessEndOfReceive(void)
Wolfgang Betz 132:51056160fa4a 269 {
Wolfgang Betz 132:51056160fa4a 270 ReceiveClosure();
Wolfgang Betz 132:51056160fa4a 271
Wolfgang Betz 132:51056160fa4a 272 HCI_Isr(HCI_read_packet, SPI_Context.SPI_Receive_Context.payload_len);
Wolfgang Betz 132:51056160fa4a 273
Wolfgang Betz 132:51056160fa4a 274 return;
Wolfgang Betz 132:51056160fa4a 275 }
Wolfgang Betz 132:51056160fa4a 276
Wolfgang Betz 132:51056160fa4a 277 /**
Wolfgang Betz 132:51056160fa4a 278 * @brief Timer callback to apply timeout SPI FIX
Wolfgang Betz 132:51056160fa4a 279 * @param None
Wolfgang Betz 132:51056160fa4a 280 * @retval None
Wolfgang Betz 132:51056160fa4a 281 */
Wolfgang Betz 132:51056160fa4a 282 static void TimerTransmitCallback(void)
Wolfgang Betz 132:51056160fa4a 283 {
Wolfgang Betz 132:51056160fa4a 284 SPI_Receive_Manager(SPI_REQUEST_VALID_HEADER_FOR_TX); /**< BlueNRG not ready for writing */
Wolfgang Betz 132:51056160fa4a 285 LPM_Mode_Request(eLPM_SPI_TX, eLPM_Mode_Sleep);
Wolfgang Betz 132:51056160fa4a 286
Wolfgang Betz 132:51056160fa4a 287 return;
Wolfgang Betz 132:51056160fa4a 288 }
Wolfgang Betz 132:51056160fa4a 289
Wolfgang Betz 132:51056160fa4a 290 /**
Wolfgang Betz 132:51056160fa4a 291 * @brief Closes the SPI when BLE is disabled by the application
Wolfgang Betz 132:51056160fa4a 292 * Releases allocated resources
Wolfgang Betz 132:51056160fa4a 293 * @param None
Wolfgang Betz 132:51056160fa4a 294 * @retval None
Wolfgang Betz 132:51056160fa4a 295 */
Wolfgang Betz 132:51056160fa4a 296 void BNRG_SPI_Close(void)
Wolfgang Betz 132:51056160fa4a 297 {
Wolfgang Betz 132:51056160fa4a 298 #ifdef ENABLE_SPI_FIX
Wolfgang Betz 132:51056160fa4a 299 TIMER_Delete(StartupTimerId);
Wolfgang Betz 132:51056160fa4a 300 #endif
Wolfgang Betz 132:51056160fa4a 301 TIMER_Delete(TxRxTimerId);
Wolfgang Betz 132:51056160fa4a 302
Wolfgang Betz 132:51056160fa4a 303 return;
Wolfgang Betz 132:51056160fa4a 304 }
Wolfgang Betz 132:51056160fa4a 305
Wolfgang Betz 132:51056160fa4a 306 /**
Wolfgang Betz 132:51056160fa4a 307 * @brief Initializes the SPI communication with the BlueNRG Shield.
Wolfgang Betz 132:51056160fa4a 308 * @param None
Wolfgang Betz 132:51056160fa4a 309 * @retval None
Wolfgang Betz 132:51056160fa4a 310 */
Wolfgang Betz 132:51056160fa4a 311 void BNRG_SPI_Init(void)
Wolfgang Betz 132:51056160fa4a 312 {
Wolfgang Betz 132:51056160fa4a 313 BNRG_MSP_SPI_Init(&SpiHandle);
Wolfgang Betz 132:51056160fa4a 314
Wolfgang Betz 132:51056160fa4a 315 SPI_Context.hspi = &SpiHandle;
Wolfgang Betz 132:51056160fa4a 316
Wolfgang Betz 132:51056160fa4a 317 SPI_Context.Spi_Peripheral_State = SPI_AVAILABLE;
Wolfgang Betz 132:51056160fa4a 318 SPI_Context.SPI_Transmit_Context.RequestPending = FALSE;
Wolfgang Betz 132:51056160fa4a 319
Wolfgang Betz 132:51056160fa4a 320 __HAL_BLUENRG_SPI_ENABLE_DMAREQ(&SpiHandle, SPI_CR2_RXDMAEN | SPI_CR2_TXDMAEN);
Wolfgang Betz 132:51056160fa4a 321
Wolfgang Betz 132:51056160fa4a 322 __HAL_SPI_ENABLE(&SpiHandle);
Wolfgang Betz 132:51056160fa4a 323
Wolfgang Betz 132:51056160fa4a 324 #ifdef ENABLE_SPI_FIX
Wolfgang Betz 132:51056160fa4a 325 TIMER_Create(eTimerModuleID_Interrupt, &StartupTimerId, eTimerMode_SingleShot, TimerStartupCallback);
Wolfgang Betz 132:51056160fa4a 326 #endif
Wolfgang Betz 132:51056160fa4a 327 TIMER_Create(eTimerModuleID_Interrupt, &TxRxTimerId, eTimerMode_SingleShot, TimerTxRxCallback);
Wolfgang Betz 132:51056160fa4a 328 return;
Wolfgang Betz 132:51056160fa4a 329 }
Wolfgang Betz 132:51056160fa4a 330
Wolfgang Betz 132:51056160fa4a 331 /**
Wolfgang Betz 132:51056160fa4a 332 * @brief Initializes the SPI communication with the BlueNRG Shield
Wolfgang Betz 132:51056160fa4a 333 * @param None
Wolfgang Betz 132:51056160fa4a 334 * @retval None
Wolfgang Betz 132:51056160fa4a 335 */
Wolfgang Betz 132:51056160fa4a 336 void BNRG_MSP_SPI_Init(SPI_HandleTypeDef * hspi)
Wolfgang Betz 132:51056160fa4a 337 {
Wolfgang Betz 132:51056160fa4a 338 hspi->Instance = BNRG_SPI_INSTANCE;
Wolfgang Betz 132:51056160fa4a 339 hspi->Init.Mode = BNRG_SPI_MODE;
Wolfgang Betz 132:51056160fa4a 340 hspi->Init.Direction = BNRG_SPI_DIRECTION;
Wolfgang Betz 132:51056160fa4a 341 hspi->Init.DataSize = BNRG_SPI_DATASIZE;
Wolfgang Betz 132:51056160fa4a 342 hspi->Init.CLKPolarity = BNRG_SPI_CLKPOLARITY;
Wolfgang Betz 132:51056160fa4a 343 hspi->Init.CLKPhase = BNRG_SPI_CLKPHASE;
Wolfgang Betz 132:51056160fa4a 344 hspi->Init.NSS = BNRG_SPI_NSS;
Wolfgang Betz 132:51056160fa4a 345 hspi->Init.FirstBit = BNRG_SPI_FIRSTBIT;
Wolfgang Betz 132:51056160fa4a 346 hspi->Init.TIMode = BNRG_SPI_TIMODE;
Wolfgang Betz 132:51056160fa4a 347 hspi->Init.CRCPolynomial = BNRG_SPI_CRCPOLYNOMIAL;
Wolfgang Betz 132:51056160fa4a 348 hspi->Init.BaudRatePrescaler = BNRG_SPI_BAUDRATEPRESCALER;
Wolfgang Betz 132:51056160fa4a 349 hspi->Init.CRCCalculation = BNRG_SPI_CRCCALCULATION;
Wolfgang Betz 132:51056160fa4a 350
Wolfgang Betz 132:51056160fa4a 351 HAL_SPI_Init(hspi);
Wolfgang Betz 132:51056160fa4a 352
Wolfgang Betz 132:51056160fa4a 353 return;
Wolfgang Betz 132:51056160fa4a 354 }
Wolfgang Betz 132:51056160fa4a 355
Wolfgang Betz 132:51056160fa4a 356 /**
Wolfgang Betz 132:51056160fa4a 357 * @brief Resets the BlueNRG.
Wolfgang Betz 132:51056160fa4a 358 * @param None
Wolfgang Betz 132:51056160fa4a 359 * @retval None
Wolfgang Betz 132:51056160fa4a 360 */
Wolfgang Betz 132:51056160fa4a 361 void BlueNRG_RST(void)
Wolfgang Betz 132:51056160fa4a 362 {
Wolfgang Betz 132:51056160fa4a 363 uint8_t ubnRFResetTimerID;
Wolfgang Betz 132:51056160fa4a 364
Wolfgang Betz 132:51056160fa4a 365 GPIO_InitTypeDef GPIO_InitStruct;
Wolfgang Betz 132:51056160fa4a 366
Wolfgang Betz 132:51056160fa4a 367 GPIO_InitStruct.Pin = BNRG_SPI_RESET_PIN;
Wolfgang Betz 132:51056160fa4a 368 GPIO_InitStruct.Speed = BNRG_SPI_RESET_SPEED;
Wolfgang Betz 132:51056160fa4a 369 TIMER_Create(eTimerModuleID_Interrupt, &ubnRFResetTimerID, eTimerMode_SingleShot, pf_nRFResetTimerCallBack);
Wolfgang Betz 132:51056160fa4a 370
Wolfgang Betz 132:51056160fa4a 371 BNRG_SPI_RESET_CLK_ENABLE();
Wolfgang Betz 132:51056160fa4a 372
Wolfgang Betz 132:51056160fa4a 373 HAL_GPIO_WritePin(BNRG_SPI_RESET_PORT, BNRG_SPI_RESET_PIN, GPIO_PIN_RESET);
Wolfgang Betz 132:51056160fa4a 374 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
Wolfgang Betz 132:51056160fa4a 375 GPIO_InitStruct.Pull = GPIO_NOPULL;
Wolfgang Betz 132:51056160fa4a 376 HAL_GPIO_Init(BNRG_SPI_RESET_PORT, &GPIO_InitStruct);
Wolfgang Betz 132:51056160fa4a 377
Wolfgang Betz 132:51056160fa4a 378 TIMER_Start(ubnRFResetTimerID, BLUENRG_HOLD_TIME_IN_RESET);
Wolfgang Betz 132:51056160fa4a 379 ubnRFresetTimerLock = 1;
Wolfgang Betz 132:51056160fa4a 380 while(ubnRFresetTimerLock == 1);
Wolfgang Betz 132:51056160fa4a 381
Wolfgang Betz 132:51056160fa4a 382 HAL_GPIO_WritePin(BNRG_SPI_RESET_PORT, BNRG_SPI_RESET_PIN, GPIO_PIN_SET);
Wolfgang Betz 132:51056160fa4a 383
Wolfgang Betz 132:51056160fa4a 384 #if 1
Wolfgang Betz 132:51056160fa4a 385 /*
Wolfgang Betz 132:51056160fa4a 386 * Limitation in HAL V1.1.0
Wolfgang Betz 132:51056160fa4a 387 * The HAL_GPIO_Init() is first configuring the Mode of the IO before the Pull UP configuration
Wolfgang Betz 132:51056160fa4a 388 * To avoid glitch on the IO, the configuration shall go through an extra step OUTPUT/PULLUP
Wolfgang Betz 132:51056160fa4a 389 * to set upfront the PULL UP configuration.
Wolfgang Betz 132:51056160fa4a 390 */
Wolfgang Betz 132:51056160fa4a 391 GPIO_InitStruct.Mode = GPIO_MODE_OUTPUT_PP;
Wolfgang Betz 132:51056160fa4a 392 GPIO_InitStruct.Pull = GPIO_PULLUP;
Wolfgang Betz 132:51056160fa4a 393 HAL_GPIO_Init(BNRG_SPI_RESET_PORT, &GPIO_InitStruct);
Wolfgang Betz 132:51056160fa4a 394 #endif
Wolfgang Betz 132:51056160fa4a 395
Wolfgang Betz 132:51056160fa4a 396 GPIO_InitStruct.Mode = GPIO_MODE_INPUT;
Wolfgang Betz 132:51056160fa4a 397 GPIO_InitStruct.Pull = GPIO_PULLUP;
Wolfgang Betz 132:51056160fa4a 398 HAL_GPIO_Init(BNRG_SPI_RESET_PORT, &GPIO_InitStruct);
Wolfgang Betz 132:51056160fa4a 399
Wolfgang Betz 132:51056160fa4a 400 TIMER_Start(ubnRFResetTimerID, BLUENRG_HOLD_TIME_AFTER_RESET);
Wolfgang Betz 132:51056160fa4a 401 ubnRFresetTimerLock = 1;
Wolfgang Betz 132:51056160fa4a 402 while(ubnRFresetTimerLock == 1);
Wolfgang Betz 132:51056160fa4a 403 TIMER_Delete(ubnRFResetTimerID);
Wolfgang Betz 132:51056160fa4a 404
Wolfgang Betz 132:51056160fa4a 405 return;
Wolfgang Betz 132:51056160fa4a 406 }
Wolfgang Betz 132:51056160fa4a 407
Wolfgang Betz 132:51056160fa4a 408 /**
Wolfgang Betz 132:51056160fa4a 409 * @brief Writes data from local buffer to SPI.
Wolfgang Betz 132:51056160fa4a 410 * @param hspi: SPI handle
Wolfgang Betz 132:51056160fa4a 411 * @param header_data: First data buffer to be written
Wolfgang Betz 132:51056160fa4a 412 * @param payload_data: Second data buffer to be written
Wolfgang Betz 132:51056160fa4a 413 * @param header_size: Size of first data buffer to be written
Wolfgang Betz 132:51056160fa4a 414 * @param payload_size: Size of second data buffer to be written
Wolfgang Betz 132:51056160fa4a 415 * @retval Number of read bytes
Wolfgang Betz 132:51056160fa4a 416 */
Wolfgang Betz 132:51056160fa4a 417 void BlueNRG_SPI_Write(uint8_t* header_data, uint8_t* payload_data, uint8_t header_size, uint8_t payload_size)
Wolfgang Betz 132:51056160fa4a 418 {
Wolfgang Betz 132:51056160fa4a 419 SPI_Context.SPI_Transmit_Context.header_data = header_data;
Wolfgang Betz 132:51056160fa4a 420 SPI_Context.SPI_Transmit_Context.payload_data = payload_data;
Wolfgang Betz 132:51056160fa4a 421 SPI_Context.SPI_Transmit_Context.header_size = header_size;
Wolfgang Betz 132:51056160fa4a 422 SPI_Context.SPI_Transmit_Context.payload_size = payload_size;
Wolfgang Betz 132:51056160fa4a 423
Wolfgang Betz 132:51056160fa4a 424 SPI_Context.SPI_Transmit_Context.packet_cont = FALSE;
Wolfgang Betz 132:51056160fa4a 425
Wolfgang Betz 132:51056160fa4a 426 __disable_irq();
Wolfgang Betz 132:51056160fa4a 427 if(SPI_Context.Spi_Peripheral_State == SPI_AVAILABLE)
Wolfgang Betz 132:51056160fa4a 428 {
Wolfgang Betz 132:51056160fa4a 429 SPI_Context.Spi_Peripheral_State = SPI_BUSY;
Wolfgang Betz 132:51056160fa4a 430 Disable_SPI_Receiving_Path();
Wolfgang Betz 132:51056160fa4a 431 __enable_irq();
Wolfgang Betz 132:51056160fa4a 432 WakeupBlueNRG();
Wolfgang Betz 132:51056160fa4a 433 }
Wolfgang Betz 132:51056160fa4a 434 else
Wolfgang Betz 132:51056160fa4a 435 {
Wolfgang Betz 132:51056160fa4a 436 SPI_Context.SPI_Transmit_Context.RequestPending = TRUE;
Wolfgang Betz 132:51056160fa4a 437 __enable_irq();
Wolfgang Betz 132:51056160fa4a 438 }
Wolfgang Betz 132:51056160fa4a 439
Wolfgang Betz 132:51056160fa4a 440 return;
Wolfgang Betz 132:51056160fa4a 441 }
Wolfgang Betz 132:51056160fa4a 442
Wolfgang Betz 132:51056160fa4a 443 /**
Wolfgang Betz 132:51056160fa4a 444 * @brief Set in Output mode the IRQ.
Wolfgang Betz 132:51056160fa4a 445 * @param None
Wolfgang Betz 132:51056160fa4a 446 * @retval None
Wolfgang Betz 132:51056160fa4a 447 */
Wolfgang Betz 132:51056160fa4a 448 static void set_irq_as_output(void)
Wolfgang Betz 132:51056160fa4a 449 {
Wolfgang Betz 132:51056160fa4a 450 HAL_GPIO_WritePin(BNRG_SPI_IRQ_PORT, BNRG_SPI_IRQ_PIN, GPIO_PIN_SET);
Wolfgang Betz 132:51056160fa4a 451 HAL_LPPUART_GPIO_Set_Mode(BNRG_SPI_IRQ_PORT, BNRG_SPI_IRQ_PIN_POSITION, GPIO_MODE_OUTPUT_PP);
Wolfgang Betz 132:51056160fa4a 452 __HAL_GPIO_EXTI_CLEAR_IT(BNRG_SPI_IRQ_PIN);
Wolfgang Betz 132:51056160fa4a 453 }
Wolfgang Betz 132:51056160fa4a 454
Wolfgang Betz 132:51056160fa4a 455 /**
Wolfgang Betz 132:51056160fa4a 456 * @brief Set the IRQ in input mode.
Wolfgang Betz 132:51056160fa4a 457 * @param None
Wolfgang Betz 132:51056160fa4a 458 * @retval None
Wolfgang Betz 132:51056160fa4a 459 */
Wolfgang Betz 132:51056160fa4a 460 static void set_irq_as_input(void)
Wolfgang Betz 132:51056160fa4a 461 {
Wolfgang Betz 132:51056160fa4a 462 HAL_GPIO_WritePin(BNRG_SPI_IRQ_PORT, BNRG_SPI_IRQ_PIN, GPIO_PIN_RESET); // WARNING: it may conflict with BlueNRG driving High
Wolfgang Betz 132:51056160fa4a 463 HAL_LPPUART_GPIO_Set_Mode(BNRG_SPI_IRQ_PORT, BNRG_SPI_IRQ_PIN_POSITION, GPIO_MODE_INPUT);
Wolfgang Betz 132:51056160fa4a 464 }
Wolfgang Betz 132:51056160fa4a 465
Wolfgang Betz 132:51056160fa4a 466 /**
Wolfgang Betz 132:51056160fa4a 467 * @brief Enable SPI IRQ.
Wolfgang Betz 132:51056160fa4a 468 * @param None
Wolfgang Betz 132:51056160fa4a 469 * @retval None
Wolfgang Betz 132:51056160fa4a 470 */
Wolfgang Betz 132:51056160fa4a 471 static void Enable_SPI_Receiving_Path(void)
Wolfgang Betz 132:51056160fa4a 472 {
Wolfgang Betz 132:51056160fa4a 473 __HAL_GPIO_EXTI_CLEAR_IT(BNRG_SPI_EXTI_PIN);
Wolfgang Betz 132:51056160fa4a 474 HAL_NVIC_ClearPendingIRQ(BNRG_SPI_EXTI_IRQn);
Wolfgang Betz 132:51056160fa4a 475 HAL_NVIC_EnableIRQ(BNRG_SPI_EXTI_IRQn);
Wolfgang Betz 132:51056160fa4a 476
Wolfgang Betz 132:51056160fa4a 477 if (HAL_GPIO_ReadPin(BNRG_SPI_IRQ_PORT, BNRG_SPI_IRQ_PIN) == GPIO_PIN_SET)
Wolfgang Betz 132:51056160fa4a 478 {
Wolfgang Betz 132:51056160fa4a 479 __HAL_GPIO_EXTI_GENERATE_SWIT(BNRG_SPI_IRQ_PIN);
Wolfgang Betz 132:51056160fa4a 480 }
Wolfgang Betz 132:51056160fa4a 481 }
Wolfgang Betz 132:51056160fa4a 482
Wolfgang Betz 132:51056160fa4a 483 /**
Wolfgang Betz 132:51056160fa4a 484 * @brief Disable SPI IRQ.
Wolfgang Betz 132:51056160fa4a 485 * @param None
Wolfgang Betz 132:51056160fa4a 486 * @retval None
Wolfgang Betz 132:51056160fa4a 487 */
Wolfgang Betz 132:51056160fa4a 488 static void Disable_SPI_Receiving_Path(void)
Wolfgang Betz 132:51056160fa4a 489 {
Wolfgang Betz 132:51056160fa4a 490 HAL_NVIC_DisableIRQ(BNRG_SPI_EXTI_IRQn);
Wolfgang Betz 132:51056160fa4a 491 }
Wolfgang Betz 132:51056160fa4a 492
Wolfgang Betz 132:51056160fa4a 493 /**
Wolfgang Betz 132:51056160fa4a 494 * @brief Enable SPI CS.
Wolfgang Betz 132:51056160fa4a 495 * @param None
Wolfgang Betz 132:51056160fa4a 496 * @retval None
Wolfgang Betz 132:51056160fa4a 497 */
Wolfgang Betz 132:51056160fa4a 498 static void Enable_SPI_CS(void)
Wolfgang Betz 132:51056160fa4a 499 {
Wolfgang Betz 132:51056160fa4a 500 /* CS reset */
Wolfgang Betz 132:51056160fa4a 501 HAL_GPIO_WritePin(BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_RESET);
Wolfgang Betz 132:51056160fa4a 502 }
Wolfgang Betz 132:51056160fa4a 503
Wolfgang Betz 132:51056160fa4a 504 /**
Wolfgang Betz 132:51056160fa4a 505 * @brief Disable SPI CS.
Wolfgang Betz 132:51056160fa4a 506 * @param None
Wolfgang Betz 132:51056160fa4a 507 * @retval None
Wolfgang Betz 132:51056160fa4a 508 */
Wolfgang Betz 132:51056160fa4a 509 static void Disable_SPI_CS(void)
Wolfgang Betz 132:51056160fa4a 510 {
Wolfgang Betz 132:51056160fa4a 511 while (__HAL_SPI_GET_FLAG(SPI_Context.hspi,SPI_FLAG_BSY) == SET);
Wolfgang Betz 132:51056160fa4a 512
Wolfgang Betz 132:51056160fa4a 513 /* CS set */
Wolfgang Betz 132:51056160fa4a 514 HAL_GPIO_WritePin(BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_SET);
Wolfgang Betz 132:51056160fa4a 515 }
Wolfgang Betz 132:51056160fa4a 516
Wolfgang Betz 132:51056160fa4a 517 /**
Wolfgang Betz 132:51056160fa4a 518 * @brief Disable and Enable SPI CS.
Wolfgang Betz 132:51056160fa4a 519 * @param None
Wolfgang Betz 132:51056160fa4a 520 * @retval None
Wolfgang Betz 132:51056160fa4a 521 */
Wolfgang Betz 132:51056160fa4a 522 static void DisableEnable_SPI_CS(void)
Wolfgang Betz 132:51056160fa4a 523 {
Wolfgang Betz 132:51056160fa4a 524 while (__HAL_SPI_GET_FLAG(SPI_Context.hspi,SPI_FLAG_BSY) == SET);
Wolfgang Betz 132:51056160fa4a 525
Wolfgang Betz 132:51056160fa4a 526 /* CS set */
Wolfgang Betz 132:51056160fa4a 527 HAL_GPIO_WritePin(BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_SET);
Wolfgang Betz 132:51056160fa4a 528
Wolfgang Betz 132:51056160fa4a 529 /* CS reset */
Wolfgang Betz 132:51056160fa4a 530 HAL_GPIO_WritePin(BNRG_SPI_CS_PORT, BNRG_SPI_CS_PIN, GPIO_PIN_RESET);
Wolfgang Betz 132:51056160fa4a 531 }
Wolfgang Betz 132:51056160fa4a 532
Wolfgang Betz 132:51056160fa4a 533 /**
Wolfgang Betz 132:51056160fa4a 534 * @brief Tx and Rx Transfer completed callbacks
Wolfgang Betz 132:51056160fa4a 535 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
Wolfgang Betz 132:51056160fa4a 536 * the configuration information for SPI module.
Wolfgang Betz 132:51056160fa4a 537 * @retval None
Wolfgang Betz 132:51056160fa4a 538 */
Wolfgang Betz 132:51056160fa4a 539 void BlueNRG_DMA_RxCallback(void)
Wolfgang Betz 132:51056160fa4a 540 {
Wolfgang Betz 132:51056160fa4a 541 uint16_t byte_count;
Wolfgang Betz 132:51056160fa4a 542 uint8_t ready_state;
Wolfgang Betz 132:51056160fa4a 543
Wolfgang Betz 132:51056160fa4a 544 __HAL_DMA_CLEAR_FLAG(SPI_Context.hspi->hdmarx, BNRG_SPI_RX_DMA_TC_FLAG);
Wolfgang Betz 132:51056160fa4a 545
Wolfgang Betz 132:51056160fa4a 546 /**
Wolfgang Betz 132:51056160fa4a 547 * The TCIF shall be cleared to be able to start a new DMA transmission later on when required.
Wolfgang Betz 132:51056160fa4a 548 * When receiving data, the TCIE is not set as there is no need to handle the interrupt
Wolfgang Betz 132:51056160fa4a 549 * handler of the DMA_Tx.
Wolfgang Betz 132:51056160fa4a 550 * The TCIF clearing is mandatory on STM32F4 but not on STM32L0.
Wolfgang Betz 132:51056160fa4a 551 * In order to keep code identical across platform, the TCIF clearing may be kept as well on
Wolfgang Betz 132:51056160fa4a 552 * the STM32L0 and all other MCUs.
Wolfgang Betz 132:51056160fa4a 553 */
Wolfgang Betz 132:51056160fa4a 554 __HAL_DMA_CLEAR_FLAG(SPI_Context.hspi->hdmatx, BNRG_SPI_TX_DMA_TC_FLAG);
Wolfgang Betz 132:51056160fa4a 555 switch (SPI_Context.SPI_Receive_Context.Spi_Receive_Event)
Wolfgang Betz 132:51056160fa4a 556 {
Wolfgang Betz 132:51056160fa4a 557 case SPI_CHECK_RECEIVED_HEADER_FOR_RX:
Wolfgang Betz 132:51056160fa4a 558 byte_count = (Received_Header[4]<<8)|Received_Header[3];
Wolfgang Betz 132:51056160fa4a 559 ready_state = Received_Header[0];
Wolfgang Betz 132:51056160fa4a 560
Wolfgang Betz 132:51056160fa4a 561 if ((byte_count == 0) || (ready_state != BLUENRG_READY_STATE))
Wolfgang Betz 132:51056160fa4a 562 {
Wolfgang Betz 132:51056160fa4a 563 if (HAL_GPIO_ReadPin(BNRG_SPI_IRQ_PORT, BNRG_SPI_IRQ_PIN) == GPIO_PIN_RESET)
Wolfgang Betz 132:51056160fa4a 564 {
Wolfgang Betz 132:51056160fa4a 565 /**
Wolfgang Betz 132:51056160fa4a 566 * This USE CASE shall never happen as this may break the IRQ/CS specification
Wolfgang Betz 132:51056160fa4a 567 * The IRQ line shall never be low when CS is low to avoid BlueNRG race condition when
Wolfgang Betz 132:51056160fa4a 568 * entering low power mode
Wolfgang Betz 132:51056160fa4a 569 * the SPI_END_RECEIVE_FIX has been implemented to make sure this USE CASE never occurs
Wolfgang Betz 132:51056160fa4a 570 * However, even when the behavior is not compliant to the specification, the BlueNRG
Wolfgang Betz 132:51056160fa4a 571 * may not fail so it is increasing robustness by adding this checking just in case the
Wolfgang Betz 132:51056160fa4a 572 * timeout define in the workaround is too short which will end up to marginally brake
Wolfgang Betz 132:51056160fa4a 573 * the specification.
Wolfgang Betz 132:51056160fa4a 574 * This checking will poping BluenRG for a dummy even
Wolfgang Betz 132:51056160fa4a 575 */
Wolfgang Betz 132:51056160fa4a 576
Wolfgang Betz 132:51056160fa4a 577 /* Release CS line */
Wolfgang Betz 132:51056160fa4a 578 Disable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 579
Wolfgang Betz 132:51056160fa4a 580 LPM_Mode_Request(eLPM_SPI_RX, eLPM_Mode_LP_Stop);
Wolfgang Betz 132:51056160fa4a 581
Wolfgang Betz 132:51056160fa4a 582 ReceiveClosure();
Wolfgang Betz 132:51056160fa4a 583 }
Wolfgang Betz 132:51056160fa4a 584 else
Wolfgang Betz 132:51056160fa4a 585 {
Wolfgang Betz 132:51056160fa4a 586 DisableEnable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 587 SPI_Receive_Manager(SPI_REQUEST_VALID_HEADER_FOR_RX); /**< BlueNRG not ready for reading */
Wolfgang Betz 132:51056160fa4a 588 }
Wolfgang Betz 132:51056160fa4a 589 }
Wolfgang Betz 132:51056160fa4a 590 else
Wolfgang Betz 132:51056160fa4a 591 {
Wolfgang Betz 132:51056160fa4a 592 SPI_Receive_Manager(SPI_REQUEST_PAYLOAD); /**< BlueNRG is ready for reading */
Wolfgang Betz 132:51056160fa4a 593 }
Wolfgang Betz 132:51056160fa4a 594 break;
Wolfgang Betz 132:51056160fa4a 595
Wolfgang Betz 132:51056160fa4a 596 case SPI_RECEIVE_END:
Wolfgang Betz 132:51056160fa4a 597 /* Release CS line */
Wolfgang Betz 132:51056160fa4a 598 Disable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 599
Wolfgang Betz 132:51056160fa4a 600 LPM_Mode_Request(eLPM_SPI_RX, eLPM_Mode_LP_Stop);
Wolfgang Betz 132:51056160fa4a 601
Wolfgang Betz 132:51056160fa4a 602 #if (SPI_END_RECEIVE_FIX == 1)
Wolfgang Betz 132:51056160fa4a 603 pTimerTxRxCallback = ProcessEndOfReceive;
Wolfgang Betz 132:51056160fa4a 604 TIMER_Start(TxRxTimerId, SPI_END_RECEIVE_FIX_TIMEOUT);
Wolfgang Betz 132:51056160fa4a 605 #else
Wolfgang Betz 132:51056160fa4a 606 ProcessEndOfReceive();
Wolfgang Betz 132:51056160fa4a 607 #endif
Wolfgang Betz 132:51056160fa4a 608 break;
Wolfgang Betz 132:51056160fa4a 609
Wolfgang Betz 132:51056160fa4a 610 case SPI_CHECK_RECEIVED_HEADER_FOR_TX:
Wolfgang Betz 132:51056160fa4a 611 byte_count = (Received_Header[2]<<8)|Received_Header[1];
Wolfgang Betz 132:51056160fa4a 612 ready_state = Received_Header[0];
Wolfgang Betz 132:51056160fa4a 613
Wolfgang Betz 132:51056160fa4a 614 if ((byte_count == 0) || (ready_state != BLUENRG_READY_STATE))
Wolfgang Betz 132:51056160fa4a 615 {
Wolfgang Betz 132:51056160fa4a 616 DisableEnable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 617 SPI_Receive_Manager(SPI_REQUEST_VALID_HEADER_FOR_TX); /**< BlueNRG not ready for writing */
Wolfgang Betz 132:51056160fa4a 618 }
Wolfgang Betz 132:51056160fa4a 619 else
Wolfgang Betz 132:51056160fa4a 620 {
Wolfgang Betz 132:51056160fa4a 621 #if (TEST_TX_BUFFER_LIMITATION == 1)
Wolfgang Betz 132:51056160fa4a 622 if(byte_count > MAX_TX_BUFFER_SIZE)
Wolfgang Betz 132:51056160fa4a 623 {
Wolfgang Betz 132:51056160fa4a 624 byte_count = MAX_TX_BUFFER_SIZE;
Wolfgang Betz 132:51056160fa4a 625 }
Wolfgang Betz 132:51056160fa4a 626 #endif
Wolfgang Betz 132:51056160fa4a 627
Wolfgang Betz 132:51056160fa4a 628 if(SPI_Context.SPI_Transmit_Context.packet_cont != TRUE)
Wolfgang Betz 132:51056160fa4a 629 {
Wolfgang Betz 132:51056160fa4a 630 if( byte_count < (SPI_Context.SPI_Transmit_Context.header_size + SPI_Context.SPI_Transmit_Context.payload_size))
Wolfgang Betz 132:51056160fa4a 631 {
Wolfgang Betz 132:51056160fa4a 632 SPI_Context.SPI_Transmit_Context.payload_size_to_transmit = byte_count - SPI_Context.SPI_Transmit_Context.header_size;
Wolfgang Betz 132:51056160fa4a 633 SPI_Context.SPI_Transmit_Context.payload_size -= SPI_Context.SPI_Transmit_Context.payload_size_to_transmit;
Wolfgang Betz 132:51056160fa4a 634 SPI_Context.SPI_Transmit_Context.packet_cont = TRUE;
Wolfgang Betz 132:51056160fa4a 635 }
Wolfgang Betz 132:51056160fa4a 636 else
Wolfgang Betz 132:51056160fa4a 637 {
Wolfgang Betz 132:51056160fa4a 638 SPI_Context.SPI_Transmit_Context.payload_size_to_transmit = SPI_Context.SPI_Transmit_Context.payload_size;
Wolfgang Betz 132:51056160fa4a 639 }
Wolfgang Betz 132:51056160fa4a 640
Wolfgang Betz 132:51056160fa4a 641 SPI_Transmit_Manager(SPI_HEADER_TRANSMIT);
Wolfgang Betz 132:51056160fa4a 642 }
Wolfgang Betz 132:51056160fa4a 643 else
Wolfgang Betz 132:51056160fa4a 644 {
Wolfgang Betz 132:51056160fa4a 645 if( byte_count < SPI_Context.SPI_Transmit_Context.payload_size)
Wolfgang Betz 132:51056160fa4a 646 {
Wolfgang Betz 132:51056160fa4a 647 SPI_Context.SPI_Transmit_Context.payload_size_to_transmit = byte_count;
Wolfgang Betz 132:51056160fa4a 648 SPI_Context.SPI_Transmit_Context.payload_size -= SPI_Context.SPI_Transmit_Context.payload_size_to_transmit;
Wolfgang Betz 132:51056160fa4a 649 }
Wolfgang Betz 132:51056160fa4a 650 else
Wolfgang Betz 132:51056160fa4a 651 {
Wolfgang Betz 132:51056160fa4a 652 SPI_Context.SPI_Transmit_Context.payload_size_to_transmit = SPI_Context.SPI_Transmit_Context.payload_size;
Wolfgang Betz 132:51056160fa4a 653 SPI_Context.SPI_Transmit_Context.payload_size = 0;
Wolfgang Betz 132:51056160fa4a 654 }
Wolfgang Betz 132:51056160fa4a 655
Wolfgang Betz 132:51056160fa4a 656 SPI_Transmit_Manager(SPI_PAYLOAD_TRANSMIT);
Wolfgang Betz 132:51056160fa4a 657 }
Wolfgang Betz 132:51056160fa4a 658 }
Wolfgang Betz 132:51056160fa4a 659
Wolfgang Betz 132:51056160fa4a 660 break;
Wolfgang Betz 132:51056160fa4a 661
Wolfgang Betz 132:51056160fa4a 662 default:
Wolfgang Betz 132:51056160fa4a 663 break;
Wolfgang Betz 132:51056160fa4a 664 }
Wolfgang Betz 132:51056160fa4a 665 }
Wolfgang Betz 132:51056160fa4a 666
Wolfgang Betz 132:51056160fa4a 667 #ifdef ENABLE_SPI_FIX
Wolfgang Betz 132:51056160fa4a 668 /**
Wolfgang Betz 132:51056160fa4a 669 * @brief Wakeup BlueNRG
Wolfgang Betz 132:51056160fa4a 670 * @param None
Wolfgang Betz 132:51056160fa4a 671 * @retval None
Wolfgang Betz 132:51056160fa4a 672 */
Wolfgang Betz 132:51056160fa4a 673 static void WakeupBlueNRG(void)
Wolfgang Betz 132:51056160fa4a 674 {
Wolfgang Betz 132:51056160fa4a 675 Disable_SPI_Receiving_Path();
Wolfgang Betz 132:51056160fa4a 676 pTimerTxRxCallback = TimerTransmitCallback;
Wolfgang Betz 132:51056160fa4a 677 set_irq_as_output();
Wolfgang Betz 132:51056160fa4a 678 TIMER_Start(StartupTimerId, SPI_FIX_TIMEOUT);
Wolfgang Betz 132:51056160fa4a 679 TIMER_Start(TxRxTimerId, SPI_FIX_TIMEOUT+SPI_TX_TIMEOUT);
Wolfgang Betz 132:51056160fa4a 680 LPM_Mode_Request(eLPM_SPI_TX, eLPM_Mode_LP_Stop);
Wolfgang Betz 132:51056160fa4a 681
Wolfgang Betz 132:51056160fa4a 682 return;
Wolfgang Betz 132:51056160fa4a 683 }
Wolfgang Betz 132:51056160fa4a 684
Wolfgang Betz 132:51056160fa4a 685 /**
Wolfgang Betz 132:51056160fa4a 686 * @brief Timer callback to apply timeout SPI FIX
Wolfgang Betz 132:51056160fa4a 687 * @param None
Wolfgang Betz 132:51056160fa4a 688 * @retval None
Wolfgang Betz 132:51056160fa4a 689 */
Wolfgang Betz 132:51056160fa4a 690 static void TimerStartupCallback(void)
Wolfgang Betz 132:51056160fa4a 691 {
Wolfgang Betz 132:51056160fa4a 692 Enable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 693
Wolfgang Betz 132:51056160fa4a 694 return;
Wolfgang Betz 132:51056160fa4a 695 }
Wolfgang Betz 132:51056160fa4a 696
Wolfgang Betz 132:51056160fa4a 697 #else
Wolfgang Betz 132:51056160fa4a 698 /**
Wolfgang Betz 132:51056160fa4a 699 * @brief Wakeup BlueNRG
Wolfgang Betz 132:51056160fa4a 700 * @param None
Wolfgang Betz 132:51056160fa4a 701 * @retval None
Wolfgang Betz 132:51056160fa4a 702 */
Wolfgang Betz 132:51056160fa4a 703 static void WakeupBlueNRG(void)
Wolfgang Betz 132:51056160fa4a 704 {
Wolfgang Betz 132:51056160fa4a 705 Disable_SPI_Receiving_Path();
Wolfgang Betz 132:51056160fa4a 706 pTimerTxRxCallback = TimerTransmitCallback;
Wolfgang Betz 132:51056160fa4a 707 Enable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 708 TIMER_Start(TxRxTimerId, SPI_TX_TIMEOUT);
Wolfgang Betz 132:51056160fa4a 709 LPM_Mode_Request(eLPM_SPI_TX, eLPM_Mode_LP_Stop);
Wolfgang Betz 132:51056160fa4a 710
Wolfgang Betz 132:51056160fa4a 711 return;
Wolfgang Betz 132:51056160fa4a 712 }
Wolfgang Betz 132:51056160fa4a 713 #endif /* ENABLE_SPI_FIX */
Wolfgang Betz 132:51056160fa4a 714
Wolfgang Betz 132:51056160fa4a 715 /**
Wolfgang Betz 132:51056160fa4a 716 * @brief Tx and Rx Transfer completed callbacks
Wolfgang Betz 132:51056160fa4a 717 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
Wolfgang Betz 132:51056160fa4a 718 * the configuration information for SPI module.
Wolfgang Betz 132:51056160fa4a 719 * @retval None
Wolfgang Betz 132:51056160fa4a 720 */
Wolfgang Betz 132:51056160fa4a 721 void BlueNRG_DMA_TxCallback(void)
Wolfgang Betz 132:51056160fa4a 722 {
Wolfgang Betz 132:51056160fa4a 723 __HAL_DMA_CLEAR_FLAG(SPI_Context.hspi->hdmatx, BNRG_SPI_TX_DMA_TC_FLAG);
Wolfgang Betz 132:51056160fa4a 724
Wolfgang Betz 132:51056160fa4a 725 switch (SPI_Context.SPI_Transmit_Context.Spi_Transmit_Event)
Wolfgang Betz 132:51056160fa4a 726 {
Wolfgang Betz 132:51056160fa4a 727 case SPI_HEADER_TRANSMITTED:
Wolfgang Betz 132:51056160fa4a 728 if(SPI_Context.SPI_Transmit_Context.payload_size_to_transmit != 0)
Wolfgang Betz 132:51056160fa4a 729 {
Wolfgang Betz 132:51056160fa4a 730 SPI_Transmit_Manager(SPI_PAYLOAD_TRANSMIT);
Wolfgang Betz 132:51056160fa4a 731 }
Wolfgang Betz 132:51056160fa4a 732 else
Wolfgang Betz 132:51056160fa4a 733 {
Wolfgang Betz 132:51056160fa4a 734 TransmitClosure();
Wolfgang Betz 132:51056160fa4a 735 }
Wolfgang Betz 132:51056160fa4a 736 break;
Wolfgang Betz 132:51056160fa4a 737
Wolfgang Betz 132:51056160fa4a 738 case SPI_PAYLOAD_TRANSMITTED:
Wolfgang Betz 132:51056160fa4a 739 if( (SPI_Context.SPI_Transmit_Context.packet_cont == TRUE) && (SPI_Context.SPI_Transmit_Context.payload_size != 0))
Wolfgang Betz 132:51056160fa4a 740 {
Wolfgang Betz 132:51056160fa4a 741 SPI_Context.SPI_Transmit_Context.payload_data += SPI_Context.SPI_Transmit_Context.payload_size_to_transmit;
Wolfgang Betz 132:51056160fa4a 742 DisableEnable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 743 SPI_Receive_Manager(SPI_REQUEST_VALID_HEADER_FOR_TX);
Wolfgang Betz 132:51056160fa4a 744 }
Wolfgang Betz 132:51056160fa4a 745 else
Wolfgang Betz 132:51056160fa4a 746 {
Wolfgang Betz 132:51056160fa4a 747 TransmitClosure();
Wolfgang Betz 132:51056160fa4a 748 }
Wolfgang Betz 132:51056160fa4a 749 break;
Wolfgang Betz 132:51056160fa4a 750
Wolfgang Betz 132:51056160fa4a 751 default:
Wolfgang Betz 132:51056160fa4a 752 break;
Wolfgang Betz 132:51056160fa4a 753 }
Wolfgang Betz 132:51056160fa4a 754
Wolfgang Betz 132:51056160fa4a 755 return;
Wolfgang Betz 132:51056160fa4a 756 }
Wolfgang Betz 132:51056160fa4a 757
Wolfgang Betz 132:51056160fa4a 758 /**
Wolfgang Betz 132:51056160fa4a 759 * @brief Close the transmit mechanism after packet has been sent
Wolfgang Betz 132:51056160fa4a 760 * Wait for the event to come back
Wolfgang Betz 132:51056160fa4a 761 * @param None
Wolfgang Betz 132:51056160fa4a 762 * @retval None
Wolfgang Betz 132:51056160fa4a 763 */
Wolfgang Betz 132:51056160fa4a 764 static void TransmitClosure(void)
Wolfgang Betz 132:51056160fa4a 765 {
Wolfgang Betz 132:51056160fa4a 766 LPM_Mode_Request(eLPM_SPI_TX, eLPM_Mode_LP_Stop);
Wolfgang Betz 132:51056160fa4a 767 SPI_Context.Spi_Peripheral_State = SPI_AVAILABLE;
Wolfgang Betz 132:51056160fa4a 768 Disable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 769 /*
Wolfgang Betz 132:51056160fa4a 770 * Disable both DMA
Wolfgang Betz 132:51056160fa4a 771 */
Wolfgang Betz 132:51056160fa4a 772 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx);
Wolfgang Betz 132:51056160fa4a 773 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx);
Wolfgang Betz 132:51056160fa4a 774 Enable_SPI_Receiving_Path();
Wolfgang Betz 132:51056160fa4a 775
Wolfgang Betz 132:51056160fa4a 776 return;
Wolfgang Betz 132:51056160fa4a 777 }
Wolfgang Betz 132:51056160fa4a 778
Wolfgang Betz 132:51056160fa4a 779 /**
Wolfgang Betz 132:51056160fa4a 780 * @brief Manage the SPI transmit
Wolfgang Betz 132:51056160fa4a 781 * @param TransmitRequest: the transmit request
Wolfgang Betz 132:51056160fa4a 782 * @retval None
Wolfgang Betz 132:51056160fa4a 783 */
Wolfgang Betz 132:51056160fa4a 784 static void SPI_Transmit_Manager(SPI_TRANSMIT_REQUEST_t TransmitRequest)
Wolfgang Betz 132:51056160fa4a 785 {
Wolfgang Betz 132:51056160fa4a 786 /*
Wolfgang Betz 132:51056160fa4a 787 * Disable both DMA
Wolfgang Betz 132:51056160fa4a 788 */
Wolfgang Betz 132:51056160fa4a 789 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx);
Wolfgang Betz 132:51056160fa4a 790 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx);
Wolfgang Betz 132:51056160fa4a 791
Wolfgang Betz 132:51056160fa4a 792 __HAL_DMA_DISABLE_IT(SPI_Context.hspi->hdmarx, DMA_IT_TC); /**< Disable Receive packet notification */
Wolfgang Betz 132:51056160fa4a 793
Wolfgang Betz 132:51056160fa4a 794 __HAL_DMA_CLEAR_FLAG(SPI_Context.hspi->hdmatx, BNRG_SPI_TX_DMA_TC_FLAG); /**< Clear flag in DMA */
Wolfgang Betz 132:51056160fa4a 795 HAL_NVIC_ClearPendingIRQ(BNRG_SPI_DMA_TX_IRQn); /**< Clear DMA pending bit in NVIC */
Wolfgang Betz 132:51056160fa4a 796 __HAL_DMA_ENABLE_IT(SPI_Context.hspi->hdmatx, DMA_IT_TC); /**< Enable Transmit packet notification */
Wolfgang Betz 132:51056160fa4a 797
Wolfgang Betz 132:51056160fa4a 798 __HAL_BLUENRG_DMA_SET_MINC(SPI_Context.hspi->hdmatx); /**< Configure DMA to send Tx packet */
Wolfgang Betz 132:51056160fa4a 799
Wolfgang Betz 132:51056160fa4a 800 switch (TransmitRequest)
Wolfgang Betz 132:51056160fa4a 801 {
Wolfgang Betz 132:51056160fa4a 802 case SPI_HEADER_TRANSMIT:
Wolfgang Betz 132:51056160fa4a 803 SPI_Context.SPI_Transmit_Context.Spi_Transmit_Event = SPI_HEADER_TRANSMITTED;
Wolfgang Betz 132:51056160fa4a 804
Wolfgang Betz 132:51056160fa4a 805 #ifdef ENABLE_SPI_FIX
Wolfgang Betz 132:51056160fa4a 806 set_irq_as_input();
Wolfgang Betz 132:51056160fa4a 807 #endif
Wolfgang Betz 132:51056160fa4a 808
Wolfgang Betz 132:51056160fa4a 809 __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, SPI_Context.SPI_Transmit_Context.header_size); /**< Set counter in DMA TX */
Wolfgang Betz 132:51056160fa4a 810 __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)SPI_Context.SPI_Transmit_Context.header_data); /**< Set memory address in DMA TX */
Wolfgang Betz 132:51056160fa4a 811 break;
Wolfgang Betz 132:51056160fa4a 812
Wolfgang Betz 132:51056160fa4a 813 case SPI_PAYLOAD_TRANSMIT:
Wolfgang Betz 132:51056160fa4a 814 SPI_Context.SPI_Transmit_Context.Spi_Transmit_Event = SPI_PAYLOAD_TRANSMITTED;
Wolfgang Betz 132:51056160fa4a 815
Wolfgang Betz 132:51056160fa4a 816 __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, SPI_Context.SPI_Transmit_Context.payload_size_to_transmit); /**< Set counter in DMA TX */
Wolfgang Betz 132:51056160fa4a 817 __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)SPI_Context.SPI_Transmit_Context.payload_data); /**< Set memory address in DMA TX */
Wolfgang Betz 132:51056160fa4a 818 break;
Wolfgang Betz 132:51056160fa4a 819
Wolfgang Betz 132:51056160fa4a 820 default:
Wolfgang Betz 132:51056160fa4a 821 break;
Wolfgang Betz 132:51056160fa4a 822 }
Wolfgang Betz 132:51056160fa4a 823
Wolfgang Betz 132:51056160fa4a 824 __HAL_DMA_ENABLE(SPI_Context.hspi->hdmatx); /**< Enable DMA TX */
Wolfgang Betz 132:51056160fa4a 825
Wolfgang Betz 132:51056160fa4a 826 }
Wolfgang Betz 132:51056160fa4a 827
Wolfgang Betz 132:51056160fa4a 828 /**
Wolfgang Betz 132:51056160fa4a 829 * @brief Manage the SPI receive
Wolfgang Betz 132:51056160fa4a 830 * @param ReceiveRequest: the receive request
Wolfgang Betz 132:51056160fa4a 831 * @retval None
Wolfgang Betz 132:51056160fa4a 832 */
Wolfgang Betz 132:51056160fa4a 833 static void SPI_Receive_Manager(SPI_RECEIVE_REQUEST_t ReceiveRequest)
Wolfgang Betz 132:51056160fa4a 834 {
Wolfgang Betz 132:51056160fa4a 835 uint16_t byte_count;
Wolfgang Betz 132:51056160fa4a 836 uint8_t localloop;
Wolfgang Betz 132:51056160fa4a 837
Wolfgang Betz 132:51056160fa4a 838 /*
Wolfgang Betz 132:51056160fa4a 839 * Disable both DMA
Wolfgang Betz 132:51056160fa4a 840 */
Wolfgang Betz 132:51056160fa4a 841 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmatx);
Wolfgang Betz 132:51056160fa4a 842 __HAL_DMA_DISABLE(SPI_Context.hspi->hdmarx);
Wolfgang Betz 132:51056160fa4a 843
Wolfgang Betz 132:51056160fa4a 844 /**
Wolfgang Betz 132:51056160fa4a 845 * Flush the Rx register or FIFO
Wolfgang Betz 132:51056160fa4a 846 */
Wolfgang Betz 132:51056160fa4a 847 for (localloop = 0 ; localloop < SPI_FIFO_RX_DEPTH ; localloop++)
Wolfgang Betz 132:51056160fa4a 848 {
Wolfgang Betz 132:51056160fa4a 849 *(volatile uint8_t*)__HAL_BLUENRG_SPI_GET_RX_DATA_REGISTER_ADDRESS(SPI_Context.hspi);
Wolfgang Betz 132:51056160fa4a 850 }
Wolfgang Betz 132:51056160fa4a 851
Wolfgang Betz 132:51056160fa4a 852 __HAL_DMA_ENABLE_IT(SPI_Context.hspi->hdmarx, DMA_IT_TC); /**< Enable Receive packet notification */
Wolfgang Betz 132:51056160fa4a 853 __HAL_DMA_DISABLE_IT(SPI_Context.hspi->hdmatx, DMA_IT_TC); /**< Disable Transmit packet notification */
Wolfgang Betz 132:51056160fa4a 854
Wolfgang Betz 132:51056160fa4a 855 switch (ReceiveRequest)
Wolfgang Betz 132:51056160fa4a 856 {
Wolfgang Betz 132:51056160fa4a 857 case SPI_REQUEST_VALID_HEADER_FOR_RX:
Wolfgang Betz 132:51056160fa4a 858 ReceiveHeader(SPI_CHECK_RECEIVED_HEADER_FOR_RX, (uint8_t *)Read_Header_CMD);
Wolfgang Betz 132:51056160fa4a 859 break;
Wolfgang Betz 132:51056160fa4a 860
Wolfgang Betz 132:51056160fa4a 861 case SPI_REQUEST_VALID_HEADER_FOR_TX:
Wolfgang Betz 132:51056160fa4a 862 ReceiveHeader(SPI_CHECK_RECEIVED_HEADER_FOR_TX, (uint8_t *)Write_Header_CMD);
Wolfgang Betz 132:51056160fa4a 863 break;
Wolfgang Betz 132:51056160fa4a 864
Wolfgang Betz 132:51056160fa4a 865 case SPI_REQUEST_PAYLOAD:
Wolfgang Betz 132:51056160fa4a 866 SPI_Context.SPI_Receive_Context.Spi_Receive_Event = SPI_RECEIVE_END;
Wolfgang Betz 132:51056160fa4a 867
Wolfgang Betz 132:51056160fa4a 868 /*
Wolfgang Betz 132:51056160fa4a 869 * Check data to received is not available buffer size
Wolfgang Betz 132:51056160fa4a 870 */
Wolfgang Betz 132:51056160fa4a 871 byte_count = (Received_Header[4]<<8)|Received_Header[3];
Wolfgang Betz 132:51056160fa4a 872 if (byte_count > SPI_Context.SPI_Receive_Context.buffer_size)
Wolfgang Betz 132:51056160fa4a 873 {
Wolfgang Betz 132:51056160fa4a 874 byte_count = SPI_Context.SPI_Receive_Context.buffer_size;
Wolfgang Betz 132:51056160fa4a 875 }
Wolfgang Betz 132:51056160fa4a 876 SPI_Context.SPI_Receive_Context.payload_len = byte_count;
Wolfgang Betz 132:51056160fa4a 877
Wolfgang Betz 132:51056160fa4a 878 __HAL_BLUENRG_DMA_CLEAR_MINC(SPI_Context.hspi->hdmatx); /**< Configure DMA to send same Byte */
Wolfgang Betz 132:51056160fa4a 879
Wolfgang Betz 132:51056160fa4a 880 /*
Wolfgang Betz 132:51056160fa4a 881 * Set counter in both DMA
Wolfgang Betz 132:51056160fa4a 882 */
Wolfgang Betz 132:51056160fa4a 883 __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmarx, byte_count);
Wolfgang Betz 132:51056160fa4a 884 __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, byte_count);
Wolfgang Betz 132:51056160fa4a 885
Wolfgang Betz 132:51056160fa4a 886 /*
Wolfgang Betz 132:51056160fa4a 887 * Set memory address in both DMA
Wolfgang Betz 132:51056160fa4a 888 */
Wolfgang Betz 132:51056160fa4a 889 __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmarx, (uint32_t)SPI_Context.SPI_Receive_Context.buffer);
Wolfgang Betz 132:51056160fa4a 890 __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)&dummy_bytes);
Wolfgang Betz 132:51056160fa4a 891 break;
Wolfgang Betz 132:51056160fa4a 892
Wolfgang Betz 132:51056160fa4a 893 default:
Wolfgang Betz 132:51056160fa4a 894 break;
Wolfgang Betz 132:51056160fa4a 895 }
Wolfgang Betz 132:51056160fa4a 896
Wolfgang Betz 132:51056160fa4a 897 /*
Wolfgang Betz 132:51056160fa4a 898 * Enable both DMA - Rx First
Wolfgang Betz 132:51056160fa4a 899 */
Wolfgang Betz 132:51056160fa4a 900 __HAL_DMA_ENABLE(SPI_Context.hspi->hdmarx);
Wolfgang Betz 132:51056160fa4a 901 __HAL_DMA_ENABLE(SPI_Context.hspi->hdmatx);
Wolfgang Betz 132:51056160fa4a 902
Wolfgang Betz 132:51056160fa4a 903 return;
Wolfgang Betz 132:51056160fa4a 904 }
Wolfgang Betz 132:51056160fa4a 905
Wolfgang Betz 132:51056160fa4a 906 /**
Wolfgang Betz 132:51056160fa4a 907 * @brief Receive header
Wolfgang Betz 132:51056160fa4a 908 * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
Wolfgang Betz 132:51056160fa4a 909 * the configuration information for SPI module.
Wolfgang Betz 132:51056160fa4a 910 * @retval None
Wolfgang Betz 132:51056160fa4a 911 */
Wolfgang Betz 132:51056160fa4a 912 static void ReceiveHeader(SPI_RECEIVE_EVENT_t ReceiveEvent, uint8_t * DataHeader)
Wolfgang Betz 132:51056160fa4a 913 {
Wolfgang Betz 132:51056160fa4a 914 SPI_Context.SPI_Receive_Context.Spi_Receive_Event = ReceiveEvent;
Wolfgang Betz 132:51056160fa4a 915
Wolfgang Betz 132:51056160fa4a 916 __HAL_BLUENRG_DMA_SET_MINC(SPI_Context.hspi->hdmatx); /**< Configure DMA to send Tx packet */
Wolfgang Betz 132:51056160fa4a 917
Wolfgang Betz 132:51056160fa4a 918 /*
Wolfgang Betz 132:51056160fa4a 919 * Set counter in both DMA
Wolfgang Betz 132:51056160fa4a 920 */
Wolfgang Betz 132:51056160fa4a 921 __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmatx, HEADER_SIZE);
Wolfgang Betz 132:51056160fa4a 922 __HAL_BLUENRG_DMA_SET_COUNTER(SPI_Context.hspi->hdmarx, HEADER_SIZE);
Wolfgang Betz 132:51056160fa4a 923
Wolfgang Betz 132:51056160fa4a 924 /*
Wolfgang Betz 132:51056160fa4a 925 * Set memory address in both DMA
Wolfgang Betz 132:51056160fa4a 926 */
Wolfgang Betz 132:51056160fa4a 927 __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmarx, (uint32_t)Received_Header);
Wolfgang Betz 132:51056160fa4a 928 __HAL_BLUENRG_DMA_SET_MEMORY_ADDRESS(SPI_Context.hspi->hdmatx, (uint32_t)DataHeader);
Wolfgang Betz 132:51056160fa4a 929
Wolfgang Betz 132:51056160fa4a 930 return;
Wolfgang Betz 132:51056160fa4a 931 }
Wolfgang Betz 132:51056160fa4a 932
Wolfgang Betz 132:51056160fa4a 933 /**
Wolfgang Betz 132:51056160fa4a 934 * @brief BlueNRG SPI request event
Wolfgang Betz 132:51056160fa4a 935 * @param buffer: the event
Wolfgang Betz 132:51056160fa4a 936 * @param buff_size: the event size
Wolfgang Betz 132:51056160fa4a 937 * @retval None
Wolfgang Betz 132:51056160fa4a 938 */
Wolfgang Betz 132:51056160fa4a 939 void BlueNRG_SPI_Request_Events(uint8_t *buffer, uint8_t buff_size)
Wolfgang Betz 132:51056160fa4a 940 {
Wolfgang Betz 132:51056160fa4a 941 SPI_Context.SPI_Receive_Context.buffer = buffer;
Wolfgang Betz 132:51056160fa4a 942 SPI_Context.SPI_Receive_Context.buffer_size = buff_size;
Wolfgang Betz 132:51056160fa4a 943
Wolfgang Betz 132:51056160fa4a 944 Enable_SPI_Receiving_Path();
Wolfgang Betz 132:51056160fa4a 945
Wolfgang Betz 132:51056160fa4a 946 return;
Wolfgang Betz 132:51056160fa4a 947 }
Wolfgang Betz 132:51056160fa4a 948
Wolfgang Betz 132:51056160fa4a 949 /**
Wolfgang Betz 132:51056160fa4a 950 * @brief BlueNRG SPI IRQ Callback
Wolfgang Betz 132:51056160fa4a 951 * @param None
Wolfgang Betz 132:51056160fa4a 952 * @retval None
Wolfgang Betz 132:51056160fa4a 953 */
Wolfgang Betz 132:51056160fa4a 954 void BlueNRG_SPI_IRQ_Callback(void)
Wolfgang Betz 132:51056160fa4a 955 {
Wolfgang Betz 132:51056160fa4a 956 __disable_irq();
Wolfgang Betz 132:51056160fa4a 957 if(SPI_Context.Spi_Peripheral_State == SPI_AVAILABLE)
Wolfgang Betz 132:51056160fa4a 958 {
Wolfgang Betz 132:51056160fa4a 959 SPI_Context.Spi_Peripheral_State = SPI_BUSY;
Wolfgang Betz 132:51056160fa4a 960 __enable_irq();
Wolfgang Betz 132:51056160fa4a 961 Enable_SPI_CS();
Wolfgang Betz 132:51056160fa4a 962 SPI_Receive_Manager(SPI_REQUEST_VALID_HEADER_FOR_RX);
Wolfgang Betz 132:51056160fa4a 963 LPM_Mode_Request(eLPM_SPI_RX, eLPM_Mode_Sleep);
Wolfgang Betz 132:51056160fa4a 964 }
Wolfgang Betz 132:51056160fa4a 965 else
Wolfgang Betz 132:51056160fa4a 966 {
Wolfgang Betz 132:51056160fa4a 967 __enable_irq();
Wolfgang Betz 132:51056160fa4a 968 }
Wolfgang Betz 132:51056160fa4a 969 }
Wolfgang Betz 132:51056160fa4a 970
Wolfgang Betz 132:51056160fa4a 971 #endif /* __DMA_LP__ */
Wolfgang Betz 132:51056160fa4a 972
Wolfgang Betz 132:51056160fa4a 973 /**
Wolfgang Betz 132:51056160fa4a 974 * @}
Wolfgang Betz 132:51056160fa4a 975 */
Wolfgang Betz 132:51056160fa4a 976
Wolfgang Betz 132:51056160fa4a 977 /**
Wolfgang Betz 132:51056160fa4a 978 * @}
Wolfgang Betz 132:51056160fa4a 979 */
Wolfgang Betz 132:51056160fa4a 980
Wolfgang Betz 132:51056160fa4a 981 /**
Wolfgang Betz 132:51056160fa4a 982 * @}
Wolfgang Betz 132:51056160fa4a 983 */
Wolfgang Betz 132:51056160fa4a 984
Wolfgang Betz 132:51056160fa4a 985 /**
Wolfgang Betz 132:51056160fa4a 986 * @}
Wolfgang Betz 132:51056160fa4a 987 */
Wolfgang Betz 132:51056160fa4a 988
Wolfgang Betz 132:51056160fa4a 989 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/