Test mbed1.

Dependencies:   mbed-src

Committer:
mja054
Date:
Thu Mar 13 16:35:52 2014 +0000
Revision:
2:9f7506fa29d4
Parent:
1:1019095e41c4
Tested for 1ms to 10s;

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mja054 1:1019095e41c4 1 /*^^^^^^^^^^^^^^^^ LCD HARDWARE CONECTION ^^^^^^^^^^^^^^^^^^^^^^^^*/
mja054 1:1019095e41c4 2 #define _LCDFRONTPLANES (8) // # of frontPlanes
mja054 1:1019095e41c4 3 #define _LCDBACKPLANES (4) // # of backplanes
mja054 1:1019095e41c4 4
mja054 1:1019095e41c4 5 /*
mja054 1:1019095e41c4 6 LCD logical organization definition
mja054 1:1019095e41c4 7 This section indicates how the LCD is distributed how many characteres of (7-seg, 14,seg, 16 seg, or colums in case of Dot Matrix) does it contain
mja054 1:1019095e41c4 8 First character is forced only one can be written
mja054 1:1019095e41c4 9
mja054 1:1019095e41c4 10 */
mja054 1:1019095e41c4 11 // HARDWARE_CONFIG Changing LCD pins Allows to verify all LCD pins easily
mja054 1:1019095e41c4 12 // if HARDWARE_CONFIG == 0 FRDM-KL46 RevB
mja054 1:1019095e41c4 13 // if HARDWARE_CONFIG == 1 FRDM-KL46 RevA
mja054 1:1019095e41c4 14 #ifdef FRDM_REVA
mja054 1:1019095e41c4 15 #define HARDWARE_CONFIG 1
mja054 1:1019095e41c4 16 #else
mja054 1:1019095e41c4 17 #define HARDWARE_CONFIG 0
mja054 1:1019095e41c4 18 #endif
mja054 1:1019095e41c4 19
mja054 1:1019095e41c4 20 #define _CHARNUM (4) //number of chars that can be written
mja054 1:1019095e41c4 21 #define _CHAR_SIZE (2) // Used only when Dot Matrix is used
mja054 1:1019095e41c4 22 #define _LCDTYPE (2) //indicate how many LCD_WF are required to write a single Character
mja054 1:1019095e41c4 23
mja054 1:1019095e41c4 24 /*
mja054 1:1019095e41c4 25 Following definitions indicate how characters are associated to waveform
mja054 1:1019095e41c4 26 */
mja054 1:1019095e41c4 27 /* Hardware configuration */
mja054 1:1019095e41c4 28 #if HARDWARE_CONFIG == 0
mja054 1:1019095e41c4 29
mja054 1:1019095e41c4 30 // LCD PIN1 to LCDWF0 Rev B
mja054 1:1019095e41c4 31 #define CHAR1a 37 // LCD Pin 5
mja054 1:1019095e41c4 32 #define CHAR1b 17 // LCD Pin 6
mja054 1:1019095e41c4 33 #define CHAR2a 7 // LCD Pin 7
mja054 1:1019095e41c4 34 #define CHAR2b 8 // LCD Pin 8
mja054 1:1019095e41c4 35 #define CHAR3a 53 // LCD Pin 9
mja054 1:1019095e41c4 36 #define CHAR3b 38 // LCD Pin 10
mja054 1:1019095e41c4 37 #define CHAR4a 10 // LCD Pin 11
mja054 1:1019095e41c4 38 #define CHAR4b 11 // LCD Pin 12
mja054 1:1019095e41c4 39 #define CHARCOM0 40 // LCD Pin 1
mja054 1:1019095e41c4 40 #define CHARCOM1 52 // LCD Pin 2
mja054 1:1019095e41c4 41 #define CHARCOM2 19 // LCD Pin 3
mja054 1:1019095e41c4 42 #define CHARCOM3 18 // LCD Pin 4
mja054 1:1019095e41c4 43
mja054 1:1019095e41c4 44 // LCD PIN1 to LCDWF2 for FRDM-KL46Z
mja054 1:1019095e41c4 45 #elif HARDWARE_CONFIG == 1
mja054 1:1019095e41c4 46 #define CHAR1a 37 // LCD Pin 5
mja054 1:1019095e41c4 47 #define CHAR1b 17 // LCD Pin 6
mja054 1:1019095e41c4 48 #define CHAR2a 7 // LCD Pin 7
mja054 1:1019095e41c4 49 #define CHAR2b 8 // LCD Pin 8
mja054 1:1019095e41c4 50 #define CHAR3a 12 // LCD Pin 9
mja054 1:1019095e41c4 51 #define CHAR3b 26 // LCD Pin 10
mja054 1:1019095e41c4 52 #define CHAR4a 10 // LCD Pin 11
mja054 1:1019095e41c4 53 #define CHAR4b 11 // LCD Pin 12
mja054 1:1019095e41c4 54 #define CHARCOM0 51 // LCD Pin 1
mja054 1:1019095e41c4 55 #define CHARCOM1 52 // LCD Pin 2
mja054 1:1019095e41c4 56 #define CHARCOM2 19 // LCD Pin 3
mja054 1:1019095e41c4 57 #define CHARCOM3 16 // LCD Pin 4
mja054 1:1019095e41c4 58
mja054 1:1019095e41c4 59 #endif
mja054 1:1019095e41c4 60
mja054 1:1019095e41c4 61
mja054 1:1019095e41c4 62 /*Ascii Codification table information */
mja054 1:1019095e41c4 63 #define ASCCI_TABLE_START '0' // indicates which is the first Ascii character in the table
mja054 1:1019095e41c4 64 #define ASCCI_TABLE_END 'Z' // indicates which is the first Ascii character in the table
mja054 1:1019095e41c4 65 #define BLANK_CHARACTER '>' // Indicate which ASCII character is a blank character (depends on ASCII table)
mja054 1:1019095e41c4 66
mja054 1:1019095e41c4 67 #define _ALLON 0xFF // Used for ALL_on function
mja054 1:1019095e41c4 68
mja054 1:1019095e41c4 69 #define SEGDP 0x01
mja054 1:1019095e41c4 70 #define SEGC 0x02
mja054 1:1019095e41c4 71 #define SEGB 0x04
mja054 1:1019095e41c4 72 #define SEGA 0x08
mja054 1:1019095e41c4 73
mja054 1:1019095e41c4 74 #define SEGD 0x01
mja054 1:1019095e41c4 75 #define SEGE 0x02
mja054 1:1019095e41c4 76 #define SEGG 0x04
mja054 1:1019095e41c4 77 #define SEGF 0x08
mja054 1:1019095e41c4 78
mja054 1:1019095e41c4 79
mja054 1:1019095e41c4 80 /* Fault detect initial limits */
mja054 1:1019095e41c4 81
mja054 1:1019095e41c4 82 /* Fault detect initial parameters and limits */
mja054 1:1019095e41c4 83 #define FAULTD_FP_FDPRS FDPRS_32
mja054 1:1019095e41c4 84 #define FAULTD_FP_FDSWW FDSWW_128
mja054 1:1019095e41c4 85 #define FAULTD_BP_FDPRS FDPRS_64
mja054 1:1019095e41c4 86 #define FAULTD_BP_FDSWW FDSWW_128
mja054 1:1019095e41c4 87
mja054 1:1019095e41c4 88 #define FAULTD_FP_HI 127
mja054 1:1019095e41c4 89 #define FAULTD_FP_LO 110
mja054 1:1019095e41c4 90 #define FAULTD_BP_HI 127
mja054 1:1019095e41c4 91 #define FAULTD_BP_LO 110
mja054 1:1019095e41c4 92 #define FAULTD_TIME 6
mja054 1:1019095e41c4 93
mja054 1:1019095e41c4 94 extern const uint8_t WF_ORDERING_TABLE[]; // Logical Front plane N to LCD_WFx
mja054 1:1019095e41c4 95
mja054 1:1019095e41c4 96