Junaid Ahmed / Mbed 2 deprecated 202A_hw1_maxrate

Generate the maximum sampling rate

Dependencies:   MAG31101 mbed

SLCD/FRDM-s401.h@0:d62b58e30f71, 2014-02-15 (annotated)

Committer:
mja054
Date:
Sat Feb 15 01:05:44 2014 +0000
Revision:
0:d62b58e30f71
Generate the maximum sampling rate

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mja054 0:d62b58e30f71 1 /*^^^^^^^^^^^^^^^^ LCD HARDWARE CONECTION ^^^^^^^^^^^^^^^^^^^^^^^^*/
mja054 0:d62b58e30f71 2 #define _LCDFRONTPLANES (8) // # of frontPlanes
mja054 0:d62b58e30f71 3 #define _LCDBACKPLANES (4) // # of backplanes
mja054 0:d62b58e30f71 4
mja054 0:d62b58e30f71 5 /*
mja054 0:d62b58e30f71 6 LCD logical organization definition
mja054 0:d62b58e30f71 7 This section indicates how the LCD is distributed how many characteres of (7-seg, 14,seg, 16 seg, or colums in case of Dot Matrix) does it contain
mja054 0:d62b58e30f71 8 First character is forced only one can be written
mja054 0:d62b58e30f71 9
mja054 0:d62b58e30f71 10 */
mja054 0:d62b58e30f71 11 // HARDWARE_CONFIG Changing LCD pins Allows to verify all LCD pins easily
mja054 0:d62b58e30f71 12 // if HARDWARE_CONFIG == 0 FRDM-KL46 RevB
mja054 0:d62b58e30f71 13 // if HARDWARE_CONFIG == 1 FRDM-KL46 RevA
mja054 0:d62b58e30f71 14 #ifdef FRDM_REVA
mja054 0:d62b58e30f71 15 #define HARDWARE_CONFIG 1
mja054 0:d62b58e30f71 16 #else
mja054 0:d62b58e30f71 17 #define HARDWARE_CONFIG 0
mja054 0:d62b58e30f71 18 #endif
mja054 0:d62b58e30f71 19
mja054 0:d62b58e30f71 20 #define _CHARNUM (4) //number of chars that can be written
mja054 0:d62b58e30f71 21 #define _CHAR_SIZE (2) // Used only when Dot Matrix is used
mja054 0:d62b58e30f71 22 #define _LCDTYPE (2) //indicate how many LCD_WF are required to write a single Character
mja054 0:d62b58e30f71 23
mja054 0:d62b58e30f71 24 /*
mja054 0:d62b58e30f71 25 Following definitions indicate how characters are associated to waveform
mja054 0:d62b58e30f71 26 */
mja054 0:d62b58e30f71 27 /* Hardware configuration */
mja054 0:d62b58e30f71 28 #if HARDWARE_CONFIG == 0
mja054 0:d62b58e30f71 29
mja054 0:d62b58e30f71 30 // LCD PIN1 to LCDWF0 Rev B
mja054 0:d62b58e30f71 31 #define CHAR1a 37 // LCD Pin 5
mja054 0:d62b58e30f71 32 #define CHAR1b 17 // LCD Pin 6
mja054 0:d62b58e30f71 33 #define CHAR2a 7 // LCD Pin 7
mja054 0:d62b58e30f71 34 #define CHAR2b 8 // LCD Pin 8
mja054 0:d62b58e30f71 35 #define CHAR3a 53 // LCD Pin 9
mja054 0:d62b58e30f71 36 #define CHAR3b 38 // LCD Pin 10
mja054 0:d62b58e30f71 37 #define CHAR4a 10 // LCD Pin 11
mja054 0:d62b58e30f71 38 #define CHAR4b 11 // LCD Pin 12
mja054 0:d62b58e30f71 39 #define CHARCOM0 40 // LCD Pin 1
mja054 0:d62b58e30f71 40 #define CHARCOM1 52 // LCD Pin 2
mja054 0:d62b58e30f71 41 #define CHARCOM2 19 // LCD Pin 3
mja054 0:d62b58e30f71 42 #define CHARCOM3 18 // LCD Pin 4
mja054 0:d62b58e30f71 43
mja054 0:d62b58e30f71 44 // LCD PIN1 to LCDWF2 for FRDM-KL46Z
mja054 0:d62b58e30f71 45 #elif HARDWARE_CONFIG == 1
mja054 0:d62b58e30f71 46 #define CHAR1a 37 // LCD Pin 5
mja054 0:d62b58e30f71 47 #define CHAR1b 17 // LCD Pin 6
mja054 0:d62b58e30f71 48 #define CHAR2a 7 // LCD Pin 7
mja054 0:d62b58e30f71 49 #define CHAR2b 8 // LCD Pin 8
mja054 0:d62b58e30f71 50 #define CHAR3a 12 // LCD Pin 9
mja054 0:d62b58e30f71 51 #define CHAR3b 26 // LCD Pin 10
mja054 0:d62b58e30f71 52 #define CHAR4a 10 // LCD Pin 11
mja054 0:d62b58e30f71 53 #define CHAR4b 11 // LCD Pin 12
mja054 0:d62b58e30f71 54 #define CHARCOM0 51 // LCD Pin 1
mja054 0:d62b58e30f71 55 #define CHARCOM1 52 // LCD Pin 2
mja054 0:d62b58e30f71 56 #define CHARCOM2 19 // LCD Pin 3
mja054 0:d62b58e30f71 57 #define CHARCOM3 16 // LCD Pin 4
mja054 0:d62b58e30f71 58
mja054 0:d62b58e30f71 59 #endif
mja054 0:d62b58e30f71 60
mja054 0:d62b58e30f71 61
mja054 0:d62b58e30f71 62 /*Ascii Codification table information */
mja054 0:d62b58e30f71 63 #define ASCCI_TABLE_START '0' // indicates which is the first Ascii character in the table
mja054 0:d62b58e30f71 64 #define ASCCI_TABLE_END 'Z' // indicates which is the first Ascii character in the table
mja054 0:d62b58e30f71 65 #define BLANK_CHARACTER '>' // Indicate which ASCII character is a blank character (depends on ASCII table)
mja054 0:d62b58e30f71 66
mja054 0:d62b58e30f71 67 #define _ALLON 0xFF // Used for ALL_on function
mja054 0:d62b58e30f71 68
mja054 0:d62b58e30f71 69 #define SEGDP 0x01
mja054 0:d62b58e30f71 70 #define SEGC 0x02
mja054 0:d62b58e30f71 71 #define SEGB 0x04
mja054 0:d62b58e30f71 72 #define SEGA 0x08
mja054 0:d62b58e30f71 73
mja054 0:d62b58e30f71 74 #define SEGD 0x01
mja054 0:d62b58e30f71 75 #define SEGE 0x02
mja054 0:d62b58e30f71 76 #define SEGG 0x04
mja054 0:d62b58e30f71 77 #define SEGF 0x08
mja054 0:d62b58e30f71 78
mja054 0:d62b58e30f71 79
mja054 0:d62b58e30f71 80 /* Fault detect initial limits */
mja054 0:d62b58e30f71 81
mja054 0:d62b58e30f71 82 /* Fault detect initial parameters and limits */
mja054 0:d62b58e30f71 83 #define FAULTD_FP_FDPRS FDPRS_32
mja054 0:d62b58e30f71 84 #define FAULTD_FP_FDSWW FDSWW_128
mja054 0:d62b58e30f71 85 #define FAULTD_BP_FDPRS FDPRS_64
mja054 0:d62b58e30f71 86 #define FAULTD_BP_FDSWW FDSWW_128
mja054 0:d62b58e30f71 87
mja054 0:d62b58e30f71 88 #define FAULTD_FP_HI 127
mja054 0:d62b58e30f71 89 #define FAULTD_FP_LO 110
mja054 0:d62b58e30f71 90 #define FAULTD_BP_HI 127
mja054 0:d62b58e30f71 91 #define FAULTD_BP_LO 110
mja054 0:d62b58e30f71 92 #define FAULTD_TIME 6
mja054 0:d62b58e30f71 93
mja054 0:d62b58e30f71 94 extern const uint8_t WF_ORDERING_TABLE[]; // Logical Front plane N to LCD_WFx
mja054 0:d62b58e30f71 95
mja054 0:d62b58e30f71 96