AD9832 DDS Sinewave (Based on MLabo's AD9834 DDS Sinewave)
Diff: main.cpp
- Revision:
- 2:e12ef0540b3c
- Parent:
- 1:323280ad1468
--- a/main.cpp Mon May 28 00:23:21 2012 +0000 +++ b/main.cpp Mon May 28 01:07:55 2012 +0000 @@ -4,13 +4,13 @@ #define XTAL_FREQ ((double)16160000.0) -DigitalOut FSYNC(p8); +DigitalOut FSYN(p8); DigitalOut SCLK(p7); DigitalOut SDATA(p5); Serial pc(USBTX,USBRX); void serial_out(uint16_t data) { - FSYNC = 0; + FSYN = 0; data & 0x8000? SDATA = 1 : SDATA = 0; SCLK = 0; SCLK = 1; data & 0x4000? SDATA = 1 : SDATA = 0; SCLK = 0; SCLK = 1; data & 0x2000? SDATA = 1 : SDATA = 0; SCLK = 0; SCLK = 1; @@ -27,32 +27,32 @@ data & 0x0004? SDATA = 1 : SDATA = 0; SCLK = 0; SCLK = 1; data & 0x0002? SDATA = 1 : SDATA = 0; SCLK = 0; SCLK = 1; data & 0x0001? SDATA = 1 : SDATA = 0; SCLK = 0; SCLK = 1; - FSYNC = 1; + FSYN = 1; } typedef union { - uint32_t UI; - uint8_t B[4]; + uint32_t UI; + uint8_t B[4]; } FREQDATA ; void AD9832_Init(void) { FREQDATA FreqReg ; FreqReg.UI = 0 ; - serial_out(0xF800); - serial_out(0x3300 + FreqReg.B[3]); - serial_out(0x2200 + FreqReg.B[2]); - serial_out(0x3100 + FreqReg.B[1]); - serial_out(0x2000 + FreqReg.B[0]); - serial_out(0xC000); + serial_out(0xF800); + serial_out(0x3300 + FreqReg.B[3]); + serial_out(0x2200 + FreqReg.B[2]); + serial_out(0x3100 + FreqReg.B[1]); + serial_out(0x2000 + FreqReg.B[0]); + serial_out(0xC000); } void AD9832_SetFreq(double freq) { FREQDATA FreqReg ; FreqReg.UI = (uint32_t)(freq * (double)(0x100000000UL) / (XTAL_FREQ) + 0.5); - serial_out(0x3300 + FreqReg.B[3]); - serial_out(0x2200 + FreqReg.B[2]); - serial_out(0x3100 + FreqReg.B[1]); - serial_out(0x2000 + FreqReg.B[0]); + serial_out(0x3300 + FreqReg.B[3]); + serial_out(0x2200 + FreqReg.B[2]); + serial_out(0x3100 + FreqReg.B[1]); + serial_out(0x2000 + FreqReg.B[0]); } int main() { @@ -63,7 +63,7 @@ pc.baud(38400); SCLK = 1; SDATA = 0; - FSYNC = 1; + FSYN = 1; AD9832_Init(); AD9832_SetFreq(60.0) ; while(1) {