fuyuno sakura / Mbed 2 deprecated 5MHzOSC

5MHz OSC. output (using p21) with self frequency counter(using p30).

Dependencies:   mbed

LPC1768 mbed を使った矩形波発生/カウンタプログラムです。

  • PWM ライブラリでは出力の難しい高速の矩形波(1MHz over)を作れます
  • 確認用に内蔵カウンタを利用した周波数カウンタも付属です。こちらも高速なパルスを計測できます。

Rectangular wave generator / counter program using LPC1768 mbed.

  • High-speed rectangular wave (1MHz over) can be made.
  • The frequency counter which uses the 1768 built-in counter, can measure high-rate pulse.

main.cpp@4:e7d16ef216d4, 2013-06-18 (annotated)

Committer:
mio
Date:
Tue Jun 18 14:18:04 2013 +0000
Revision:
4:e7d16ef216d4
Parent:
3:603f4efe3985 
Wrong comment about MR6 and output pulse duty fix.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mio 0:c988614df67a 1 //
mio 2:bff82681a822 2 // CLOCK OUT to PWM1[6] Sample with Freq Counter using Cap2.0
mio 1:2a347c40b1da 3 // For LPC1768-mbed
mio 0:c988614df67a 4 //
mio 4:e7d16ef216d4 5 // Reference: 5MHz Clock Out Code and Comment - http://mbed.org/forum/mbed/topic/733/
mio 0:c988614df67a 6 //
mio 1:2a347c40b1da 7 // !! To Self Measurement Output Clock, Connect p21 <-> p30 with jumper wire.
mio 4:e7d16ef216d4 8 // 2013.6.18 : Wrong comment about MR6 and Duty fix.
mio 0:c988614df67a 9 //
mio 0:c988614df67a 10
mio 0:c988614df67a 11 #include "mbed.h"
mio 0:c988614df67a 12
mio 1:2a347c40b1da 13 PwmOut fmclck(p21); // for RESERVE pin21 as PWM1[6]
mio 1:2a347c40b1da 14 DigitalIn clkin(p30); // for RESERVE pin30 as CAP2[0]
mio 1:2a347c40b1da 15
mio 1:2a347c40b1da 16 // Reset Counter and Count Start
mio 1:2a347c40b1da 17 void P30_RESET_CTR(void)
mio 1:2a347c40b1da 18 {
mio 1:2a347c40b1da 19 LPC_TIM2->TCR = 2; // Reset the counter (bit1<=1,bit0<=0)
mio 1:2a347c40b1da 20 LPC_TIM2->TCR = 1; // UnReset counter (bit1<=0,bit0<=1)
mio 1:2a347c40b1da 21 }
mio 1:2a347c40b1da 22
mio 1:2a347c40b1da 23 // Get Counter Value
mio 1:2a347c40b1da 24 int P30_GET_CTR(void)
mio 1:2a347c40b1da 25 {
mio 1:2a347c40b1da 26 return LPC_TIM2->TC; // Read the counter value
mio 1:2a347c40b1da 27 }
mio 0:c988614df67a 28
mio 1:2a347c40b1da 29 // Setting p30 to Cap2.0
mio 1:2a347c40b1da 30 void P30_INIT_CTR(void)
mio 1:2a347c40b1da 31 {
mio 1:2a347c40b1da 32 LPC_SC->PCONP |= 1 << 22; // 1)Power up TimerCounter2 (bit22)
mio 1:2a347c40b1da 33 LPC_PINCON->PINSEL0 |= 3 << 8; // 2)Set P0[4] to CAP2[0]
mio 1:2a347c40b1da 34 LPC_TIM2->TCR = 2; // 3)Counter Reset (bit1<=1,bit0<=0)
mio 1:2a347c40b1da 35 LPC_TIM2->CTCR = 1; // 4)Count on riging edge Cap2[0]
mio 1:2a347c40b1da 36 LPC_TIM2->CCR = 0; // 5)Input Capture Disabled
mio 1:2a347c40b1da 37 LPC_TIM2->TCR = 1; // 6)Counter Start (bit1<=0,bit0<=1)
mio 1:2a347c40b1da 38 }
mio 1:2a347c40b1da 39
mio 1:2a347c40b1da 40 // Clock Output From pin21(PWM6)
mio 1:2a347c40b1da 41 // Set Clock Freq with div.
mio 1:2a347c40b1da 42 // if mbed is running at 96MHz, div is set 96 to Get 1MHz.
mio 1:2a347c40b1da 43 void PWM6_SETCLK(int div)
mio 1:2a347c40b1da 44 {
mio 0:c988614df67a 45 LPC_PWM1->TCR = (1 << 1); // 1)Reset counter, disable PWM
mio 0:c988614df67a 46 LPC_SC->PCLKSEL0 &= ~(0x3 << 12);
mio 0:c988614df67a 47 LPC_SC->PCLKSEL0 |= (1 << 12); // 2)Set peripheral clock divider to /1, i.e. system clock
mio 1:2a347c40b1da 48 LPC_PWM1->MR0 = div - 1; // 3)Match Register 0 is shared period counter for all PWM1
mio 3:603f4efe3985 49 LPC_PWM1->MR6 = (div + 1)>> 1; //
mio 0:c988614df67a 50 LPC_PWM1->LER |= 1; // 4)Start updating at next period start
mio 1:2a347c40b1da 51 LPC_PWM1->TCR = (1 << 0) || (1 << 3); // 5)Enable counter and PWM
mio 1:2a347c40b1da 52 }
mio 0:c988614df67a 53
mio 1:2a347c40b1da 54 int main() {
mio 4:e7d16ef216d4 55 PWM6_SETCLK(19) ; // Outout mbed's "PWM6" pin to 96MHZ/19 = 5.052MHz (Approx)
mio 4:e7d16ef216d4 56 // PWM6_SETCLK(96) ; // Outout mbed's "PWM6" pin to 96MHZ/96 = 1.000MHz (Approx)
mio 1:2a347c40b1da 57 P30_INIT_CTR();
mio 1:2a347c40b1da 58 while(1){
mio 1:2a347c40b1da 59 P30_RESET_CTR();
mio 1:2a347c40b1da 60 wait(1.0); // Gate time for count
mio 1:2a347c40b1da 61 printf("pin30 Freq = %d (Hz)\r\n",P30_GET_CTR());
mio 1:2a347c40b1da 62 }
mio 1:2a347c40b1da 63 }