Mirjana Radosavljevic
Battery Management System LV - 2020/2021
bq79606.h@3:4dc457ed63d5, 2021-03-20 (annotated)
- Committer:
- minamax
- Date:
- Sat Mar 20 17:54:12 2021 +0000
- Revision:
- 3:4dc457ed63d5
- Parent:
- 2:03a6da61d834
This works
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| minamax | 1:d0662d4ffb8c | 1 | #ifndef bq |
| minamax | 1:d0662d4ffb8c | 2 | #define bq |
| minamax | 1:d0662d4ffb8c | 3 | #include "mbed.h" |
| minamax | 0:e22b53fffed7 | 4 | |
| minamax | 0:e22b53fffed7 | 5 | // User defines |
| minamax | 0:e22b53fffed7 | 6 | #define TOTALBOARDS 1 //MUST SET: total boards in the stack |
| minamax | 2:03a6da61d834 | 7 | #define BAUDRATE 1000000 //set global baudrate |
| minamax | 0:e22b53fffed7 | 8 | #define MAXBYTES 6*2 //6 CELLS, 2 BYTES EACH |
| minamax | 0:e22b53fffed7 | 9 | |
| minamax | 0:e22b53fffed7 | 10 | #define FRMWRT_SGL_R 0x00 // single device write with response |
| minamax | 0:e22b53fffed7 | 11 | #define FRMWRT_SGL_NR 0x10 // single device write without response |
| minamax | 0:e22b53fffed7 | 12 | #define FRMWRT_STK_R 0x20 // stack broadcast with response |
| minamax | 0:e22b53fffed7 | 13 | #define FRMWRT_STK_NR 0x30 // stack broadcast without response |
| minamax | 0:e22b53fffed7 | 14 | #define FRMWRT_ALL_R 0x40 // general broadcast with response |
| minamax | 0:e22b53fffed7 | 15 | #define FRMWRT_ALL_NR 0x50 // general broadcast without response |
| minamax | 0:e22b53fffed7 | 16 | #define FRMWRT_REV_ALL_NR 0xE0 //broadcast write reverse direction |
| minamax | 0:e22b53fffed7 | 17 | |
| minamax | 0:e22b53fffed7 | 18 | typedef unsigned char BYTE; |
| minamax | 0:e22b53fffed7 | 19 | |
| minamax | 0:e22b53fffed7 | 20 | // Register defines |
| minamax | 0:e22b53fffed7 | 21 | #define DEVADD_OTP 0x00 // Device address OTP |
| minamax | 0:e22b53fffed7 | 22 | #define CONFIG 0x01 // Device configuration |
| minamax | 0:e22b53fffed7 | 23 | #define GPIO_FLT_MSK 0x02 // GPIO fault mask |
| minamax | 0:e22b53fffed7 | 24 | #define UV_FLT_MSK 0x03 // UV comparator fault mask |
| minamax | 0:e22b53fffed7 | 25 | #define OV_FLT_MSK 0x04 // OV comparator fault mask |
| minamax | 0:e22b53fffed7 | 26 | #define UT_FLT_MSK 0x05 // UT comparator fault mask |
| minamax | 0:e22b53fffed7 | 27 | #define OT_FLT_MSK 0x06 // OT comparator fault mask |
| minamax | 0:e22b53fffed7 | 28 | #define TONE_FLT_MSK 0x07 // Fault bus tone fault mask |
| minamax | 0:e22b53fffed7 | 29 | #define COMM_UART_FLT_MSK 0x08 // UART fault mask |
| minamax | 0:e22b53fffed7 | 30 | #define COMM_UART_RC_FLT_MSK 0x09 // UART receive command fault mask |
| minamax | 0:e22b53fffed7 | 31 | #define COMM_UART_RR_FLT_MSK 0x0A // UART receive response fault mask |
| minamax | 0:e22b53fffed7 | 32 | #define COMM_UART_TR_FLT_MSK 0x0B // UART transmit fault mask |
| minamax | 0:e22b53fffed7 | 33 | #define COMM_COMH_FLT_MSK 0x0C // COMH bus fault mask |
| minamax | 0:e22b53fffed7 | 34 | #define COMM_COMH_RC_FLT_MSK 0x0D // COMH bus receive command fault mask |
| minamax | 0:e22b53fffed7 | 35 | #define COMM_COMH_RR_FLT_MSK 0x0E // COMH bus receive command fault mask |
| minamax | 0:e22b53fffed7 | 36 | #define COMM_COMH_TR_FLT_MSK 0x0F // COMH bus transmit fault mask |
| minamax | 0:e22b53fffed7 | 37 | #define COMM_COML_FLT_MSK 0x10 // COML bus fault mask |
| minamax | 0:e22b53fffed7 | 38 | #define COMM_COML_RC_FLT_MSK 0x11 // COML bus receive command fault mask |
| minamax | 0:e22b53fffed7 | 39 | #define COMM_COML_RR_FLT_MSK 0x12 // COML bus receive command fault mask |
| minamax | 0:e22b53fffed7 | 40 | #define COMM_COML_TR_FLT_MSK 0x13 // COML bus transmit fault mask |
| minamax | 0:e22b53fffed7 | 41 | #define OTP_FLT_MSK 0x14 // OTP page fault mask |
| minamax | 0:e22b53fffed7 | 42 | #define RAIL_FLT_MSK 0x15 // Power rail fault mask |
| minamax | 0:e22b53fffed7 | 43 | #define SYSFLT1_FLT_MSK 0x16 // System fault 1 mask |
| minamax | 0:e22b53fffed7 | 44 | #define SYSFLT2_FLT_MSK 0x17 // System fault 2 mask |
| minamax | 0:e22b53fffed7 | 45 | #define SYSFLT3_FLT_MSK 0x18 // IC system fault 3 mask |
| minamax | 0:e22b53fffed7 | 46 | #define OVUV_BIST_FLT_MSK 0x19 // OVUV bist fault mask |
| minamax | 0:e22b53fffed7 | 47 | #define OTUT_BIST_FLT_MSK 0x1A // OTUT bist fault mask |
| minamax | 0:e22b53fffed7 | 48 | #define SPARE_01 0x1B // Spare register |
| minamax | 0:e22b53fffed7 | 49 | #define SPARE_02 0x1C // Spare register |
| minamax | 0:e22b53fffed7 | 50 | #define SPARE_03 0x1D // Spare register |
| minamax | 0:e22b53fffed7 | 51 | #define SPARE_04 0x1E // Spare register |
| minamax | 0:e22b53fffed7 | 52 | #define SPARE_05 0x1F // Spare register |
| minamax | 0:e22b53fffed7 | 53 | #define COMM_CTRL 0x20 // Communication control |
| minamax | 0:e22b53fffed7 | 54 | #define DAISY_CHAIN_CTRL 0x21 // Daisy chain RX/TX anable control |
| minamax | 0:e22b53fffed7 | 55 | #define TX_HOLD_OFF 0x22 // Transmitter holdoff control |
| minamax | 0:e22b53fffed7 | 56 | #define COMM_TO 0x23 // Communication timeout control |
| minamax | 0:e22b53fffed7 | 57 | #define CELL_ADC_CONF1 0x24 // Cell ADC configuration 1 |
| minamax | 0:e22b53fffed7 | 58 | #define CELL_ADC_CONF2 0x25 // Cell ADC configuration 2 |
| minamax | 0:e22b53fffed7 | 59 | #define AUX_ADC_CONF 0x26 // Auxiliary ADC configuration |
| minamax | 0:e22b53fffed7 | 60 | #define ADC_DELAY 0x27 // ADC configuration |
| minamax | 0:e22b53fffed7 | 61 | #define GPIO_ADC_CONF 0x28 // GPIO_ADC result configuration |
| minamax | 0:e22b53fffed7 | 62 | #define OVUV_CTRL 0x29 // Cell hardware protection channel control |
| minamax | 0:e22b53fffed7 | 63 | #define UV_THRESH 0x2A // Comparator undervoltage threshold |
| minamax | 0:e22b53fffed7 | 64 | #define OV_THRESH 0x2B // Comparator overvoltage threshold |
| minamax | 0:e22b53fffed7 | 65 | #define OTUT_CTRL 0x2C // GPIO over and under temperature comparator control |
| minamax | 0:e22b53fffed7 | 66 | #define OTUT_THRESH 0x2D // GPIO comparator over and under temperature threshold |
| minamax | 0:e22b53fffed7 | 67 | #define COMP_DG 0x2E // Comparator protection deglitch |
| minamax | 0:e22b53fffed7 | 68 | #define GPIO1_CONF 0x2F // GPIO1 configuration |
| minamax | 0:e22b53fffed7 | 69 | #define GPIO2_CONF 0x30 // GPIO2 configuration |
| minamax | 0:e22b53fffed7 | 70 | #define GPIO3_CONF 0x31 // GPIO3 configuration |
| minamax | 0:e22b53fffed7 | 71 | #define GPIO4_CONF 0x32 // GPIO4 configuration |
| minamax | 0:e22b53fffed7 | 72 | #define GPIO5_CONF 0x33 // GPIO5 configuration |
| minamax | 0:e22b53fffed7 | 73 | #define GPIO6_CONF 0x34 // GPIO6 configuration |
| minamax | 0:e22b53fffed7 | 74 | #define CELL1_GAIN 0x35 // Cell 1 gain calibration |
| minamax | 0:e22b53fffed7 | 75 | #define CELL2_GAIN 0x36 // Cell 2 gain calibration |
| minamax | 0:e22b53fffed7 | 76 | #define CELL3_GAIN 0x37 // Cell 3 gain calibration |
| minamax | 0:e22b53fffed7 | 77 | #define CELL4_GAIN 0x38 // Cell 4 gain calibration |
| minamax | 0:e22b53fffed7 | 78 | #define CELL5_GAIN 0x39 // Cell 5 gain calibration |
| minamax | 0:e22b53fffed7 | 79 | #define CELL6_GAIN 0x3A // Cell 6 gain calibration |
| minamax | 0:e22b53fffed7 | 80 | #define CELL1_OFF 0x3B // Cell 1 offset calibration |
| minamax | 0:e22b53fffed7 | 81 | #define CELL2_OFF 0x3C // Cell 2 offset calibration |
| minamax | 0:e22b53fffed7 | 82 | #define CELL3_OFF 0x3D // Cell 3 offset calibration |
| minamax | 0:e22b53fffed7 | 83 | #define CELL4_OFF 0x3E // Cell 4 offset calibration |
| minamax | 0:e22b53fffed7 | 84 | #define CELL5_OFF 0x3F // Cell 5 offset calibration |
| minamax | 0:e22b53fffed7 | 85 | #define CELL6_OFF 0x40 // Cell 6 offset calibration |
| minamax | 0:e22b53fffed7 | 86 | #define GPIO1_GAIN 0x41 // GPIO1 gain calibration |
| minamax | 0:e22b53fffed7 | 87 | #define GPIO2_GAIN 0x42 // GPIO2 gain calibration |
| minamax | 0:e22b53fffed7 | 88 | #define GPIO3_GAIN 0x43 // GPIO3 gain calibration |
| minamax | 0:e22b53fffed7 | 89 | #define GPIO4_GAIN 0x44 // GPIO4 gain calibration |
| minamax | 0:e22b53fffed7 | 90 | #define GPIO5_GAIN 0x45 // GPIO5 gain calibration |
| minamax | 0:e22b53fffed7 | 91 | #define GPIO6_GAIN 0x46 // GPIO6 gain calibration |
| minamax | 0:e22b53fffed7 | 92 | #define GPIO1_OFF 0x47 // GPIO1 offset calibration |
| minamax | 0:e22b53fffed7 | 93 | #define GPIO2_OFF 0x48 // GPIO2 offset calibration |
| minamax | 0:e22b53fffed7 | 94 | #define GPIO3_OFF 0x49 // GPIO3 offset calibration |
| minamax | 0:e22b53fffed7 | 95 | #define GPIO4_OFF 0x4A // GPIO4 offset calibration |
| minamax | 0:e22b53fffed7 | 96 | #define GPIO5_OFF 0x4B // GPIO5 offset calibration |
| minamax | 0:e22b53fffed7 | 97 | #define GPIO6_OFF 0x4C // GPIO6 offset calibration |
| minamax | 0:e22b53fffed7 | 98 | #define GPAUXCELL_GAIN 0x4D // GP ADC gain, CH1 |
| minamax | 0:e22b53fffed7 | 99 | #define GPAUXCELL_OFF 0x4E // GP ADC offset, CH1 |
| minamax | 0:e22b53fffed7 | 100 | #define GPAUX_GAIN 0x4F // GP ADC gain, CH2-32 |
| minamax | 0:e22b53fffed7 | 101 | #define GPAUX_OFF 0x50 // GP ADC offset, CH2-32 |
| minamax | 0:e22b53fffed7 | 102 | #define VC1COEFF1 0x51 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 103 | #define VC1COEFF2 0x52 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 104 | #define VC1COEFF3 0x53 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 105 | #define VC1COEFF4 0x54 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 106 | #define VC1COEFF5 0x55 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 107 | #define VC1COEFF6 0x56 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 108 | #define VC1COEFF7 0x57 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 109 | #define VC1COEFF8 0x58 // Cell 1 ADC gain correction |
| minamax | 0:e22b53fffed7 | 110 | #define VC1COEFF9 0x59 // Cell 1 ADC offset/gain correction |
| minamax | 0:e22b53fffed7 | 111 | #define VC1COEFF10 0x5A // Cell 1 ADC offset correction |
| minamax | 0:e22b53fffed7 | 112 | #define VC1COEFF11 0x5B // Cell 1 ADC offset correction |
| minamax | 0:e22b53fffed7 | 113 | #define VC1COEFF12 0x5C // Cell 1 ADC offset correction |
| minamax | 0:e22b53fffed7 | 114 | #define VC1COEFF13 0x5D // Cell 1 ADC offset correction |
| minamax | 0:e22b53fffed7 | 115 | #define VC1COEFF14 0x5E // Cell 1 ADC offset correction |
| minamax | 0:e22b53fffed7 | 116 | #define VC2COEFF1 0x5F // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 117 | #define VC2COEFF2 0x60 // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 118 | #define VC2COEFF3 0x61 // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 119 | #define VC2COEFF4 0x62 // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 120 | #define VC2COEFF5 0x63 // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 121 | #define VC2COEFF6 0x64 // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 122 | #define VC2COEFF7 0x65 // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 123 | #define VC2COEFF8 0x66 // Cell 2 ADC gain correction |
| minamax | 0:e22b53fffed7 | 124 | #define VC2COEFF9 0x67 // Cell 2 ADC offset/gain correction |
| minamax | 0:e22b53fffed7 | 125 | #define VC2COEFF10 0x68 // Cell 2 ADC offset correction |
| minamax | 0:e22b53fffed7 | 126 | #define VC2COEFF11 0x69 // Cell 2 ADC offset correction |
| minamax | 0:e22b53fffed7 | 127 | #define VC2COEFF12 0x6A // Cell 2 ADC offset correction |
| minamax | 0:e22b53fffed7 | 128 | #define VC2COEFF13 0x6B // Cell 2 ADC offset correction |
| minamax | 0:e22b53fffed7 | 129 | #define VC2COEFF14 0x6C // Cell 2 ADC offset correction |
| minamax | 0:e22b53fffed7 | 130 | #define VC3COEFF1 0x6D // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 131 | #define VC3COEFF2 0x6E // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 132 | #define VC3COEFF3 0x6F // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 133 | #define VC3COEFF4 0x70 // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 134 | #define VC3COEFF5 0x71 // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 135 | #define VC3COEFF6 0x72 // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 136 | #define VC3COEFF7 0x73 // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 137 | #define VC3COEFF8 0x74 // Cell 3 ADC gain correction |
| minamax | 0:e22b53fffed7 | 138 | #define VC3COEFF9 0x75 // Cell 3 ADC offset/gain correction |
| minamax | 0:e22b53fffed7 | 139 | #define VC3COEFF10 0x76 // Cell 3 ADC offset correction |
| minamax | 0:e22b53fffed7 | 140 | #define VC3COEFF11 0x77 // Cell 3 ADC offset correction |
| minamax | 0:e22b53fffed7 | 141 | #define VC3COEFF12 0x78 // Cell 3 ADC offset correction |
| minamax | 0:e22b53fffed7 | 142 | #define VC3COEFF13 0x79 // Cell 3 ADC offset correction |
| minamax | 0:e22b53fffed7 | 143 | #define VC3COEFF14 0x7A // Cell 3 ADC offset correction |
| minamax | 0:e22b53fffed7 | 144 | #define VC4COEFF1 0x7B // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 145 | #define VC4COEFF2 0x7C // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 146 | #define VC4COEFF3 0x7D // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 147 | #define VC4COEFF4 0x7E // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 148 | #define VC4COEFF5 0x7F // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 149 | #define VC4COEFF6 0x80 // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 150 | #define VC4COEFF7 0x81 // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 151 | #define VC4COEFF8 0x82 // Cell 4 ADC gain correction |
| minamax | 0:e22b53fffed7 | 152 | #define VC4COEFF9 0x83 // Cell 4 ADC offset/gain correction |
| minamax | 0:e22b53fffed7 | 153 | #define VC4COEFF10 0x84 // Cell 4 ADC offset correction |
| minamax | 0:e22b53fffed7 | 154 | #define VC4COEFF11 0x85 // Cell 4 ADC offset correction |
| minamax | 0:e22b53fffed7 | 155 | #define VC4COEFF12 0x86 // Cell 4 ADC offset correction |
| minamax | 0:e22b53fffed7 | 156 | #define VC4COEFF13 0x87 // Cell 4 ADC offset correction |
| minamax | 0:e22b53fffed7 | 157 | #define VC4COEFF14 0x88 // Cell 4 ADC offset correction |
| minamax | 0:e22b53fffed7 | 158 | #define VC5COEFF1 0x89 // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 159 | #define VC5COEFF2 0x8A // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 160 | #define VC5COEFF3 0x8B // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 161 | #define VC5COEFF4 0x8C // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 162 | #define VC5COEFF5 0x8D // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 163 | #define VC5COEFF6 0x8E // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 164 | #define VC5COEFF7 0x8F // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 165 | #define VC5COEFF8 0x90 // Cell 5 ADC gain correction |
| minamax | 0:e22b53fffed7 | 166 | #define VC5COEFF9 0x91 // Cell 5 ADC offset/gain correction |
| minamax | 0:e22b53fffed7 | 167 | #define VC5COEFF10 0x92 // Cell 5 ADC offset correction |
| minamax | 0:e22b53fffed7 | 168 | #define VC5COEFF11 0x93 // Cell 5 ADC offset correction |
| minamax | 0:e22b53fffed7 | 169 | #define VC5COEFF12 0x94 // Cell 5 ADC offset correction |
| minamax | 0:e22b53fffed7 | 170 | #define VC5COEFF13 0x95 // Cell 5 ADC offset correction |
| minamax | 0:e22b53fffed7 | 171 | #define VC5COEFF14 0x96 // Cell 5 ADC offset correction |
| minamax | 0:e22b53fffed7 | 172 | #define VC6COEFF1 0x97 // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 173 | #define VC6COEFF2 0x98 // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 174 | #define VC6COEFF3 0x99 // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 175 | #define VC6COEFF4 0x9A // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 176 | #define VC6COEFF5 0x9B // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 177 | #define VC6COEFF6 0x9C // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 178 | #define VC6COEFF7 0x9D // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 179 | #define VC6COEFF8 0x9E // Cell 6 ADC gain correction |
| minamax | 0:e22b53fffed7 | 180 | #define VC6COEFF9 0x9F // Cell 6 ADC offset/gain correction |
| minamax | 0:e22b53fffed7 | 181 | #define VC6COEFF10 0xA0 // Cell 6 ADC offset correction |
| minamax | 0:e22b53fffed7 | 182 | #define VC6COEFF11 0xA1 // Cell 6 ADC offset correction |
| minamax | 0:e22b53fffed7 | 183 | #define VC6COEFF12 0xA2 // Cell 6 ADC offset correction |
| minamax | 0:e22b53fffed7 | 184 | #define VC6COEFF13 0xA3 // Cell 6 ADC offset correction |
| minamax | 0:e22b53fffed7 | 185 | #define VC6COEFF14 0xA4 // Cell 6 ADC offset correction |
| minamax | 0:e22b53fffed7 | 186 | #define VAUXCOEFF1 0xA5 // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 187 | #define VAUXCOEFF2 0xA6 // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 188 | #define VAUXCOEFF3 0xA7 // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 189 | #define VAUXCOEFF4 0xA8 // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 190 | #define VAUXCOEFF5 0xA9 // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 191 | #define VAUXCOEFF6 0xAA // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 192 | #define VAUXCOEFF7 0xAB // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 193 | #define VAUXCOEFF8 0xAC // GP ADC gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 194 | #define VAUXCOEFF9 0xAD // GP ADC offset/gain correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 195 | #define VAUXCOEFF10 0xAE // GP ADC offset correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 196 | #define VAUXCOEFF11 0xAF // GP ADC offset correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 197 | #define VAUXCOEFF12 0xB0 // GP ADC offset correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 198 | #define VAUXCOEFF13 0xB1 // GP ADC offset correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 199 | #define VAUXCOEFF14 0xB2 // GP ADC offset correction - CH2-32 |
| minamax | 0:e22b53fffed7 | 200 | #define VAUXCELLCOEFF1 0xB3 // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 201 | #define VAUXCELLCOEFF2 0xB4 // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 202 | #define VAUXCELLCOEFF3 0xB5 // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 203 | #define VAUXCELLCOEFF4 0xB6 // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 204 | #define VAUXCELLCOEFF5 0xB7 // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 205 | #define VAUXCELLCOEFF6 0xB8 // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 206 | #define VAUXCELLCOEFF7 0xB9 // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 207 | #define VAUXCELLCOEFF8 0xBA // GP ADC gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 208 | #define VAUXCELLCOEFF9 0xBB // GP ADC offset/gain correction - CH1 |
| minamax | 0:e22b53fffed7 | 209 | #define VAUXCELLCOEFF10 0xBC // GP ADC offset correction - CH1 |
| minamax | 0:e22b53fffed7 | 210 | #define VAUXCELLCOEFF11 0xBD // GP ADC offset correction - CH1 |
| minamax | 0:e22b53fffed7 | 211 | #define VAUXCELLCOEFF12 0xBE // GP ADC offset correction - CH1 |
| minamax | 0:e22b53fffed7 | 212 | #define VAUXCELLCOEFF13 0xBF // GP ADC offset correction - CH1 |
| minamax | 0:e22b53fffed7 | 213 | #define VAUXCELLCOEFF14 0xC0 // GP ADC offset correction - CH1 |
| minamax | 0:e22b53fffed7 | 214 | #define SPARE_06 0xC1 // Spare register |
| minamax | 0:e22b53fffed7 | 215 | #define CUST_MISC1 0xC2 // Customer OTP memory 1 |
| minamax | 0:e22b53fffed7 | 216 | #define CUST_MISC2 0xC3 // Customer OTP memory 2 |
| minamax | 0:e22b53fffed7 | 217 | #define CUST_MISC3 0xC4 // Customer OTP memory 3 |
| minamax | 0:e22b53fffed7 | 218 | #define CUST_MISC4 0xC5 // Customer OTP memory 4 |
| minamax | 0:e22b53fffed7 | 219 | #define CUST_CRCH 0xC6 // Customer CRC high byte |
| minamax | 0:e22b53fffed7 | 220 | #define CUST_CRCL 0xC7 // Customer CRC low byte |
| minamax | 0:e22b53fffed7 | 221 | #define OTP_PROG_UNLOCK1A 0x100 // OTP program unlock code 1A |
| minamax | 0:e22b53fffed7 | 222 | #define OTP_PROG_UNLOCK1B 0x101 // OTP program unlock code 1B |
| minamax | 0:e22b53fffed7 | 223 | #define OTP_PROG_UNLOCK1C 0x102 // OTP program unlock code 1C |
| minamax | 0:e22b53fffed7 | 224 | #define OTP_PROG_UNLOCK1D 0x103 // OTP program unlock code 1D |
| minamax | 0:e22b53fffed7 | 225 | #define DEVADD_USR 0x104 // Programmable device address |
| minamax | 0:e22b53fffed7 | 226 | #define CONTROL1 0x105 // Device control |
| minamax | 0:e22b53fffed7 | 227 | #define CONTROL2 0x106 // Function enable control |
| minamax | 0:e22b53fffed7 | 228 | #define OTP_PROG_CTRL 0x107 // OTP programming control |
| minamax | 0:e22b53fffed7 | 229 | #define GPIO_OUT 0x108 // GPIO output control |
| minamax | 0:e22b53fffed7 | 230 | #define CELL_ADC_CTRL 0x109 // Cell ADC control |
| minamax | 0:e22b53fffed7 | 231 | #define AUX_ADC_CTRL1 0x10A // Auxiliary ADC control 1 |
| minamax | 0:e22b53fffed7 | 232 | #define AUX_ADC_CTRL2 0x10B // Auxiliary ADC control 2 |
| minamax | 0:e22b53fffed7 | 233 | #define AUX_ADC_CTRL3 0x10C // Auxiliary ADC control 3 |
| minamax | 0:e22b53fffed7 | 234 | #define CB_CONFIG 0x10D // Balance timer configuration |
| minamax | 0:e22b53fffed7 | 235 | #define CB_CELL1_CTRL 0x10E // Cell 1 balance timer configuration |
| minamax | 0:e22b53fffed7 | 236 | #define CB_CELL2_CTRL 0x10F // Cell 2 balance timer configuration |
| minamax | 0:e22b53fffed7 | 237 | #define CB_CELL3_CTRL 0x110 // Cell 3 balance timer configuration |
| minamax | 0:e22b53fffed7 | 238 | #define CB_CELL4_CTRL 0x111 // Cell 4 balance timer configuration |
| minamax | 0:e22b53fffed7 | 239 | #define CB_CELL5_CTRL 0x112 // Cell 5 balance timer configuration |
| minamax | 0:e22b53fffed7 | 240 | #define CB_CELL6_CTRL 0x113 // Cell 6 balance timer configuration |
| minamax | 0:e22b53fffed7 | 241 | #define CB_DONE_THRESHOLD 0x114 // Cell balance done comparator threshold |
| minamax | 0:e22b53fffed7 | 242 | #define CB_SW_EN 0x115 // Cell balancing manual switch enable |
| minamax | 0:e22b53fffed7 | 243 | #define DIAG_CTRL1 0x116 // Diagnostic control register 1 |
| minamax | 0:e22b53fffed7 | 244 | #define DIAG_CTRL2 0x117 // Diagnostic control register 2 |
| minamax | 0:e22b53fffed7 | 245 | #define DIAG_CTRL3 0x118 // Diagnostic control register 3 |
| minamax | 0:e22b53fffed7 | 246 | #define DIAG_CTRL4 0x119 // Diagnostic control register 4 |
| minamax | 0:e22b53fffed7 | 247 | #define VC_CS_CTRL 0x11A // VC current source/sink control |
| minamax | 0:e22b53fffed7 | 248 | #define CB_CS_CTRL 0x11B // CB current source/sink control |
| minamax | 0:e22b53fffed7 | 249 | #define CBVC_COMP_CTRL 0x11C // CB switch comparator control |
| minamax | 0:e22b53fffed7 | 250 | #define ECC_TEST 0x11D // ECC test |
| minamax | 0:e22b53fffed7 | 251 | #define ECC_DATAIN0 0x11E // 1st data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 252 | #define ECC_DATAIN1 0x11F // 2nd data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 253 | #define ECC_DATAIN2 0x120 // 3rd data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 254 | #define ECC_DATAIN3 0x121 // 4th data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 255 | #define ECC_DATAIN4 0x122 // 5th data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 256 | #define ECC_DATAIN5 0x123 // 6th data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 257 | #define ECC_DATAIN6 0x124 // 7th data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 258 | #define ECC_DATAIN7 0x125 // 8th data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 259 | #define ECC_DATAIN8 0x126 // 9th data in byte for manual ECC test |
| minamax | 0:e22b53fffed7 | 260 | #define GPIO_FLT_RST 0x127 // GPIO fault reset |
| minamax | 0:e22b53fffed7 | 261 | #define UV_FLT_RST 0x128 // UV comparator fault reset |
| minamax | 0:e22b53fffed7 | 262 | #define OV_FLT_RST 0x129 // OV comparator fault reset |
| minamax | 0:e22b53fffed7 | 263 | #define UT_FLT_RST 0x12A // UT comparator fault reset |
| minamax | 0:e22b53fffed7 | 264 | #define OT_FLT_RST 0x12B // OT comparator fault reset |
| minamax | 0:e22b53fffed7 | 265 | #define TONE_FLT_RST 0x12C // Fault bus status reset |
| minamax | 0:e22b53fffed7 | 266 | #define COMM_UART_FLT_RST 0x12D // UART fault status reset |
| minamax | 0:e22b53fffed7 | 267 | #define COMM_UART_RC_FLT_RST 0x12E // UART receive command fault reset |
| minamax | 0:e22b53fffed7 | 268 | #define COMM_UART_RR_FLT_RST 0x12F // UART receive response fault reset |
| minamax | 0:e22b53fffed7 | 269 | #define COMM_UART_TR_FLT_RST 0x130 // UART transmit fault reset |
| minamax | 0:e22b53fffed7 | 270 | #define COMM_COMH_FLT_RST 0x131 // COMH bus fault reset |
| minamax | 0:e22b53fffed7 | 271 | #define COMM_COMH_RC_FLT_RST 0x132 // COMH bus receive command fault reset |
| minamax | 0:e22b53fffed7 | 272 | #define COMM_COMH_RR_FLT_RST 0x133 // COMH bus receive command fault reset |
| minamax | 0:e22b53fffed7 | 273 | #define COMM_COMH_TR_FLT_RST 0x134 // COMH bus transmit fault reset |
| minamax | 0:e22b53fffed7 | 274 | #define COMM_COML_FLT_RST 0x135 // COML bus fault reset |
| minamax | 0:e22b53fffed7 | 275 | #define COMM_COML_RC_FLT_RST 0x136 // COML bus receive command fault reset |
| minamax | 0:e22b53fffed7 | 276 | #define COMM_COML_RR_FLT_RST 0x137 // COML bus receive command fault reset |
| minamax | 0:e22b53fffed7 | 277 | #define COMM_COML_TR_FLT_RST 0x138 // COML bus transmit fault reset |
| minamax | 0:e22b53fffed7 | 278 | #define OTP_FLT_RST 0x139 // OTP page fault reset |
| minamax | 0:e22b53fffed7 | 279 | #define RAIL_FLT_RST 0x13A // Power rail reset |
| minamax | 0:e22b53fffed7 | 280 | #define SYSFLT1_FLT_RST 0x13B // System fault 1 reset |
| minamax | 0:e22b53fffed7 | 281 | #define SYSFLT2_FLT_RST 0x13C // System fault 2 reset |
| minamax | 0:e22b53fffed7 | 282 | #define SYSFLT3_FLT_RST 0x13D // IC system fault 3 reset |
| minamax | 0:e22b53fffed7 | 283 | #define OVUV_BIST_FLT_RST 0x13E // OVUV bist fault reset |
| minamax | 0:e22b53fffed7 | 284 | #define OTUT_BIST_FLT_RST 0x13F // OTUT bist fault reset |
| minamax | 0:e22b53fffed7 | 285 | #define OTP_PROG_UNLOCK2A 0x150 // OTP program unlock code 2A |
| minamax | 0:e22b53fffed7 | 286 | #define OTP_PROG_UNLOCK2B 0x151 // OTP program unlock code 2B |
| minamax | 0:e22b53fffed7 | 287 | #define OTP_PROG_UNLOCK2C 0x152 // OTP program unlock code 2C |
| minamax | 0:e22b53fffed7 | 288 | #define OTP_PROG_UNLOCK2D 0x153 // OTP program unlock code 2D |
| minamax | 0:e22b53fffed7 | 289 | #define SPI_CFG 0x154 // SPI master configuration |
| minamax | 0:e22b53fffed7 | 290 | #define SPI_TX 0x155 // SPI byte to transmit |
| minamax | 0:e22b53fffed7 | 291 | #define SPI_EXE 0x156 // SPI command execute |
| minamax | 0:e22b53fffed7 | 292 | #define PARTID 0x200 // Customer revision information |
| minamax | 0:e22b53fffed7 | 293 | #define SYS_FAULT1 0x201 // System fault 1 status |
| minamax | 0:e22b53fffed7 | 294 | #define SYS_FAULT2 0x202 // System fault 2 status |
| minamax | 0:e22b53fffed7 | 295 | #define SYS_FAULT3 0x203 // IC system fault 3 status |
| minamax | 0:e22b53fffed7 | 296 | #define DEV_STAT 0x204 // Device status |
| minamax | 0:e22b53fffed7 | 297 | #define LOOP_STAT 0x205 // Round robin status |
| minamax | 0:e22b53fffed7 | 298 | #define FAULT_SUM 0x206 // Fault summary |
| minamax | 0:e22b53fffed7 | 299 | #define VCELL1_HF 0x207 // Cell 1 voltage high byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 300 | #define VCELL1_LF 0x208 // Cell 1 voltage low byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 301 | #define VCELL2_HF 0x209 // Cell 2 voltage high byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 302 | #define VCELL2_LF 0x20A // Cell 2 voltage low byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 303 | #define VCELL3_HF 0x20B // Cell 3 voltage high byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 304 | #define VCELL3_LF 0x20C // Cell 3 voltage low byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 305 | #define VCELL4_HF 0x20D // Cell 4 voltage high byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 306 | #define VCELL4_LF 0x20E // Cell 4 voltage low byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 307 | #define VCELL5_HF 0x20F // Cell 5 voltage high byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 308 | #define VCELL5_LF 0x210 // Cell 5 voltage low byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 309 | #define VCELL6_HF 0x211 // Cell 6 voltage high byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 310 | #define VCELL6_LF 0x212 // Cell 6 voltage low byte (low pass filtered) |
| minamax | 0:e22b53fffed7 | 311 | #define CONV_CNTH 0x213 // Cell ADC conversion counter high byte |
| minamax | 0:e22b53fffed7 | 312 | #define CONV_CNTL 0x214 // Cell ADC conversion counter low byte |
| minamax | 0:e22b53fffed7 | 313 | #define VCELL1H 0x215 // Cell 1 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 314 | #define VCELL1L 0x216 // Cell 1 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 315 | #define VCELL2H 0x217 // Cell 2 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 316 | #define VCELL2L 0x218 // Cell 2 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 317 | #define VCELL3H 0x219 // Cell 3 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 318 | #define VCELL3L 0x21A // Cell 3 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 319 | #define VCELL4H 0x21B // Cell 4 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 320 | #define VCELL4L 0x21C // Cell 4 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 321 | #define VCELL5H 0x21D // Cell 5 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 322 | #define VCELL5L 0x21E // Cell 5 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 323 | #define VCELL6H 0x21F // Cell 6 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 324 | #define VCELL6L 0x220 // Cell 6 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 325 | #define VCELL_FACTCORRH 0x221 // Selected cell factory corrected high byte |
| minamax | 0:e22b53fffed7 | 326 | #define VCELL_FACTCORRL 0x222 // Selected cell factory corrected low byte |
| minamax | 0:e22b53fffed7 | 327 | #define AUX_CELLH 0x223 // AUX measurement voltage high byte |
| minamax | 0:e22b53fffed7 | 328 | #define AUX_CELLL 0x224 // AUX measurement voltage low byte |
| minamax | 0:e22b53fffed7 | 329 | #define AUX_BATH 0x225 // Cell stack voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 330 | #define AUX_BATL 0x226 // Cell stack voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 331 | #define AUX_REF2H 0x227 // Bandgap 1 measurement voltage high byte |
| minamax | 0:e22b53fffed7 | 332 | #define AUX_REF2L 0x228 // Bandgap 1 measurement voltage low byte |
| minamax | 0:e22b53fffed7 | 333 | #define AUX_ZEROH 0x229 // ZERO reference voltage high byte |
| minamax | 0:e22b53fffed7 | 334 | #define AUX_ZEROL 0x22A // ZERO reference voltage low byte |
| minamax | 0:e22b53fffed7 | 335 | #define AUX_AVDDH 0x22B // AVDD LDO voltage output high byte |
| minamax | 0:e22b53fffed7 | 336 | #define AUX_AVDDL 0x22C // AVDD LDO voltage output low byte |
| minamax | 0:e22b53fffed7 | 337 | #define AUX_GPIO1H 0x22D // GPIO1 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 338 | #define AUX_GPIO1L 0x22E // GPIO1 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 339 | #define AUX_GPIO2H 0x22F // GPIO2 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 340 | #define AUX_GPIO2L 0x230 // GPIO2 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 341 | #define AUX_GPIO3H 0x231 // GPIO3 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 342 | #define AUX_GPIO3L 0x232 // GPIO3 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 343 | #define AUX_GPIO4H 0x233 // GPIO4 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 344 | #define AUX_GPIO4L 0x234 // GPIO4 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 345 | #define AUX_GPIO5H 0x235 // GPIO5 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 346 | #define AUX_GPIO5L 0x236 // GPIO5 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 347 | #define AUX_GPIO6H 0x237 // GPIO6 voltage high byte (corrected) |
| minamax | 0:e22b53fffed7 | 348 | #define AUX_GPIO6L 0x238 // GPIO6 voltage low byte (corrected) |
| minamax | 0:e22b53fffed7 | 349 | #define AUX_FACTCORRH 0x239 // Selected GPIO factory corrected high byte |
| minamax | 0:e22b53fffed7 | 350 | #define AUX_FACTCORRL 0x23A // Selected GPIO factory corrected low byte |
| minamax | 0:e22b53fffed7 | 351 | #define DIE_TEMPH 0x23B // Die junction temperature high byte |
| minamax | 0:e22b53fffed7 | 352 | #define DIE_TEMPL 0x23C // Die junction temperature low byte |
| minamax | 0:e22b53fffed7 | 353 | #define AUX_REF3H 0x23D // Bandgap 2 voltage output high byte |
| minamax | 0:e22b53fffed7 | 354 | #define AUX_REF3L 0x23E // Bandgap 2 voltage output low byte |
| minamax | 0:e22b53fffed7 | 355 | #define AUX_OV_DACH 0x23F // OV reference voltage high byte |
| minamax | 0:e22b53fffed7 | 356 | #define AUX_OV_DACL 0x240 // OV reference voltage low byte |
| minamax | 0:e22b53fffed7 | 357 | #define AUX_UV_DACH 0x241 // UV reference voltage high byte |
| minamax | 0:e22b53fffed7 | 358 | #define AUX_UV_DACL 0x242 // UV reference voltage low byte |
| minamax | 0:e22b53fffed7 | 359 | #define AUX_OT_DACH 0x243 // OT reference voltage high byte |
| minamax | 0:e22b53fffed7 | 360 | #define AUX_OT_DACL 0x244 // OT reference voltage low byte |
| minamax | 0:e22b53fffed7 | 361 | #define AUX_UT_DACH 0x245 // UT reference voltage high byte |
| minamax | 0:e22b53fffed7 | 362 | #define AUX_UT_DACL 0x246 // UT reference voltage low byte |
| minamax | 0:e22b53fffed7 | 363 | #define AUX_TWARN_PTATH 0x247 // TWARN PTAT current high byte |
| minamax | 0:e22b53fffed7 | 364 | #define AUX_TWARN_PTATL 0x248 // TWARN PTAT current low byte |
| minamax | 0:e22b53fffed7 | 365 | #define AUX_DVDDH 0x249 // DVDD LDO voltage output high byte |
| minamax | 0:e22b53fffed7 | 366 | #define AUX_DVDDL 0x24A // DVDD LDO voltage output low byte |
| minamax | 0:e22b53fffed7 | 367 | #define AUX_TSREFH 0x24B // TSREF voltage output high byte |
| minamax | 0:e22b53fffed7 | 368 | #define AUX_TSREFL 0x24C // TSREF voltage output low byte |
| minamax | 0:e22b53fffed7 | 369 | #define AUX_CVDDH 0x24D // CVDD LDO voltage output high byte |
| minamax | 0:e22b53fffed7 | 370 | #define AUX_CVDDL 0x24E // CVDD LDO voltage output low byte |
| minamax | 0:e22b53fffed7 | 371 | #define AUX_AVAOH 0x24F // AVAO reference voltage output high byte |
| minamax | 0:e22b53fffed7 | 372 | #define AUX_AVAOL 0x250 // AVAO reference voltage output low byte |
| minamax | 0:e22b53fffed7 | 373 | #define SPI_RX 0x260 // SPI byte read |
| minamax | 0:e22b53fffed7 | 374 | #define CB_DONE 0x261 // Cell balancing complete status |
| minamax | 0:e22b53fffed7 | 375 | #define GPIO_STAT 0x262 // GPIO input status |
| minamax | 0:e22b53fffed7 | 376 | #define CBVC_COMP_STAT 0x263 // CBVC comparator status |
| minamax | 0:e22b53fffed7 | 377 | #define CBVC_VCLOW_STAT 0x264 // CBVC VCLOW comparator status |
| minamax | 0:e22b53fffed7 | 378 | #define COMM_UART_RC_STAT3 0x265 // Discarded UART command frame counter |
| minamax | 0:e22b53fffed7 | 379 | #define COMM_COML_RC_STAT3 0x266 // Discarded COML command frame counter |
| minamax | 0:e22b53fffed7 | 380 | #define COMM_COMH_RR_STAT3 0x267 // Discarded COMH response frame counter |
| minamax | 0:e22b53fffed7 | 381 | #define COMM_COML_RR_STAT3 0x268 // Discarded COML response frame counter |
| minamax | 0:e22b53fffed7 | 382 | #define COMM_COMH_RC_STAT3 0x269 // Discarded COMH command frame counter |
| minamax | 0:e22b53fffed7 | 383 | #define COMM_UART_RR_STAT3 0x26A // Discarded UART response frame counter |
| minamax | 0:e22b53fffed7 | 384 | #define COMM_UART_RC_STAT1 0x26B // Valid UART command frame counter high byte |
| minamax | 0:e22b53fffed7 | 385 | #define COMM_UART_RC_STAT2 0x26C // Valid UART command frame counter low byte |
| minamax | 0:e22b53fffed7 | 386 | #define COMM_COML_RC_STAT1 0x26D // Valid COML command frame counter high byte |
| minamax | 0:e22b53fffed7 | 387 | #define COMM_COML_RC_STAT2 0x26E // Valid COML command frame counter low byte |
| minamax | 0:e22b53fffed7 | 388 | #define COMM_COMH_RR_STAT1 0x26F // Valid COMH response frame counter high byte |
| minamax | 0:e22b53fffed7 | 389 | #define COMM_COMH_RR_STAT2 0x270 // Valid COMH response frame counter low byte |
| minamax | 0:e22b53fffed7 | 390 | #define COMM_UART_TR_STAT1 0x271 // Transmitted UART response frame counter high byte |
| minamax | 0:e22b53fffed7 | 391 | #define COMM_UART_TR_STAT2 0x272 // Transmitted UART response frame counter low byte |
| minamax | 0:e22b53fffed7 | 392 | #define COMM_COML_TR_STAT1 0x273 // Transmitted COML response frame counter high byte |
| minamax | 0:e22b53fffed7 | 393 | #define COMM_COML_TR_STAT2 0x274 // Transmitted COML response frame counter low byte |
| minamax | 0:e22b53fffed7 | 394 | #define COMM_COMH_RC_STAT1 0x275 // Valid COMH command frame counter high byte |
| minamax | 0:e22b53fffed7 | 395 | #define COMM_COMH_RC_STAT2 0x276 // Valid COMH command frame counter low byte |
| minamax | 0:e22b53fffed7 | 396 | #define COMM_COML_RR_STAT1 0x277 // Valid COML response frame counter high byte |
| minamax | 0:e22b53fffed7 | 397 | #define COMM_COML_RR_STAT2 0x278 // Valid COML response frame counter low byte |
| minamax | 0:e22b53fffed7 | 398 | #define COMM_COMH_TR_STAT1 0x279 // Transmitted COMH response frame counter high byte |
| minamax | 0:e22b53fffed7 | 399 | #define COMM_COMH_TR_STAT2 0x27A // Transmitted COMH response frame counter low byte |
| minamax | 0:e22b53fffed7 | 400 | #define COMM_UART_RR_STAT1 0x27B // Valid UART response frame counter high byte |
| minamax | 0:e22b53fffed7 | 401 | #define COMM_UART_RR_STAT2 0x27C // Valid UART response frame counter low byte |
| minamax | 0:e22b53fffed7 | 402 | #define OTP_PROG_STAT 0x27D // OTP programming status |
| minamax | 0:e22b53fffed7 | 403 | #define OTP_CUST1_STAT1 0x27E // Customer OTP page 1 status |
| minamax | 0:e22b53fffed7 | 404 | #define OTP_CUST1_STAT2 0x27F // Customer OTP page 2 programming status |
| minamax | 0:e22b53fffed7 | 405 | #define OTP_CUST2_STAT1 0x280 // Customer OTP page 1 status |
| minamax | 0:e22b53fffed7 | 406 | #define OTP_CUST2_STAT2 0x281 // Customer OTP page 2 programming status |
| minamax | 0:e22b53fffed7 | 407 | #define CB_SW_STAT 0x282 // Cell balancing switch status |
| minamax | 0:e22b53fffed7 | 408 | #define GPIO_FAULT 0x290 // GPIO fault status |
| minamax | 0:e22b53fffed7 | 409 | #define UV_FAULT 0x291 // UV comparator fault status |
| minamax | 0:e22b53fffed7 | 410 | #define OV_FAULT 0x292 // OV comparator fault status |
| minamax | 0:e22b53fffed7 | 411 | #define UT_FAULT 0x293 // UT comparator fault status |
| minamax | 0:e22b53fffed7 | 412 | #define OT_FAULT 0x294 // OT comparator fault status |
| minamax | 0:e22b53fffed7 | 413 | #define TONE_FAULT 0x295 // Fault bus status |
| minamax | 0:e22b53fffed7 | 414 | #define COMM_UART_FAULT 0x296 // UART fault status |
| minamax | 0:e22b53fffed7 | 415 | #define COMM_UART_RC_FAULT 0x297 // UART receive command fault status |
| minamax | 0:e22b53fffed7 | 416 | #define COMM_UART_RR_FAULT 0x298 // UART receive response fault status (only valid in multidrop mode) |
| minamax | 0:e22b53fffed7 | 417 | #define COMM_UART_TR_FAULT 0x299 // UART transmit fault status |
| minamax | 0:e22b53fffed7 | 418 | #define COMM_COMH_FAULT 0x29A // COMH fault status |
| minamax | 0:e22b53fffed7 | 419 | #define COMM_COMH_RC_FAULT 0x29B // COMH receive command fault status |
| minamax | 0:e22b53fffed7 | 420 | #define COMM_COMH_RR_FAULT 0x29C // COMH receive response fault status |
| minamax | 0:e22b53fffed7 | 421 | #define COMM_COMH_TR_FAULT 0x29D // COMH transmit fault status |
| minamax | 0:e22b53fffed7 | 422 | #define COMM_COML_FAULT 0x29E // COML fault status |
| minamax | 0:e22b53fffed7 | 423 | #define COMM_COML_RC_FAULT 0x29F // COML receive command fault status |
| minamax | 0:e22b53fffed7 | 424 | #define COMM_COML_RR_FAULT 0x2A0 // COML receive response fault status |
| minamax | 0:e22b53fffed7 | 425 | #define COMM_COML_TR_FAULT 0x2A1 // COML transmit fault status |
| minamax | 0:e22b53fffed7 | 426 | #define OTP_FAULT 0x2A2 // OTP page fault status |
| minamax | 0:e22b53fffed7 | 427 | #define RAIL_FAULT 0x2A3 // Power rail fault status |
| minamax | 0:e22b53fffed7 | 428 | #define OVUV_BIST_FAULT 0x2A4 // OVUV BIST fault status |
| minamax | 0:e22b53fffed7 | 429 | #define OTUT_BIST_FAULT 0x2A5 // OTUT BIST fault status |
| minamax | 0:e22b53fffed7 | 430 | #define ECC_DATAOUT0 0x2B0 // 1st data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 431 | #define ECC_DATAOUT1 0x2B1 // 2nd data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 432 | #define ECC_DATAOUT2 0x2B2 // 3rd data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 433 | #define ECC_DATAOUT3 0x2B3 // 4th data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 434 | #define ECC_DATAOUT4 0x2B4 // 5th data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 435 | #define ECC_DATAOUT5 0x2B5 // 6th data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 436 | #define ECC_DATAOUT6 0x2B6 // 7th data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 437 | #define ECC_DATAOUT7 0x2B7 // 8th data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 438 | #define ECC_DATAOUT8 0x2B8 // 9th data out byte for ECC test |
| minamax | 0:e22b53fffed7 | 439 | #define SEC_BLK 0x2B9 // SEC detected block |
| minamax | 0:e22b53fffed7 | 440 | #define DED_BLK 0x2BA // DED detected block |
| minamax | 0:e22b53fffed7 | 441 | #define DEV_ADD_STAT 0x2BB // Device address status |
| minamax | 0:e22b53fffed7 | 442 | #define COMM_STAT 0x2BC // Communication status register |
| minamax | 0:e22b53fffed7 | 443 | #define DAISY_CHAIN_STAT 0x2BD // Communication status register |
| minamax | 0:e22b53fffed7 | 444 | #define VCELL1_HU 0x2C0 // Cell 1 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 445 | #define VCELL1_MU 0x2C1 // Cell 1 voltage middle byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 446 | #define VCELL1_LU 0x2C2 // Cell 1 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 447 | #define VCELL2_HU 0x2C3 // Cell 2 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 448 | #define VCELL2_MU 0x2C4 // Cell 2 voltage middle byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 449 | #define VCELL2_LU 0x2C5 // Cell 2 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 450 | #define VCELL3_HU 0x2C6 // Cell 3 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 451 | #define VCELL3_MU 0x2C7 // Cell 3 voltage middle byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 452 | #define VCELL3_LU 0x2C8 // Cell 3 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 453 | #define VCELL4_HU 0x2C9 // Cell 4 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 454 | #define VCELL4_MU 0x2CA // Cell 4 voltage middle byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 455 | #define VCELL4_LU 0x2CB // Cell 4 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 456 | #define VCELL5_HU 0x2CC // Cell 5 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 457 | #define VCELL5_MU 0x2CD // Cell 5 voltage middle byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 458 | #define VCELL5_LU 0x2CE // Cell 5 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 459 | #define VCELL6_HU 0x2CF // Cell 6 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 460 | #define VCELL6_MU 0x2D0 // Cell 6 voltage middle byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 461 | #define VCELL6_LU 0x2D1 // Cell 6 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 462 | #define AUX_BAT_HU 0x2D2 // Cell stack voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 463 | #define AUX_BAT_LU 0x2D3 // Cell stack voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 464 | #define AUX_GPIO1_HU 0x2D4 // GPIO1 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 465 | #define AUX_GPIO1_MU 0x2D5 // GPIO1 voltage middle byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 466 | #define AUX_GPIO1_LU 0x2D6 // GPIO1 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 467 | #define AUX_GPIO2_HU 0x2D7 // GPIO2 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 468 | #define AUX_GPIO2_LU 0x2D8 // GPIO2 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 469 | #define AUX_GPIO3_HU 0x2D9 // GPIO3 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 470 | #define AUX_GPIO3_LU 0x2DA // GPIO3 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 471 | #define AUX_GPIO4_HU 0x2DB // GPIO4 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 472 | #define AUX_GPIO4_LU 0x2DC // GPIO4 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 473 | #define AUX_GPIO5_HU 0x2DD // GPIO5 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 474 | #define AUX_GPIO5_LU 0x2DE // GPIO5 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 475 | #define AUX_GPIO6_HU 0x2DF // GPIO6 voltage high byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 476 | #define AUX_GPIO6_LU 0x2E0 // GPIO6 voltage low byte (uncorrected) |
| minamax | 0:e22b53fffed7 | 477 | #define CUST_CRC_RSLTH 0x2E1 // Calculated customer CRC result high byte |
| minamax | 0:e22b53fffed7 | 478 | #define CUST_CRC_RSLTL 0x2E2 // Calculated customer CRC result low byte |
| minamax | 0:e22b53fffed7 | 479 | |
| minamax | 0:e22b53fffed7 | 480 | |
| minamax | 0:e22b53fffed7 | 481 | |
| minamax | 0:e22b53fffed7 | 482 | // Function Prototypes |
| minamax | 1:d0662d4ffb8c | 483 | void Wake79606(void); |
| minamax | 0:e22b53fffed7 | 484 | //void CommClear(void); |
| minamax | 0:e22b53fffed7 | 485 | //void CommSleepToWake(void); |
| minamax | 0:e22b53fffed7 | 486 | //void CommReset(void); |
| minamax | 0:e22b53fffed7 | 487 | void AutoAddress(void); |
| minamax | 0:e22b53fffed7 | 488 | |
| minamax | 1:d0662d4ffb8c | 489 | uint16_t CRC16(BYTE *pBuf, int nLen); |
| minamax | 0:e22b53fffed7 | 490 | |
| minamax | 0:e22b53fffed7 | 491 | void sendUART(int length, uint8_t * data); |
| minamax | 1:d0662d4ffb8c | 492 | void init(void); |
| minamax | 0:e22b53fffed7 | 493 | |
| minamax | 1:d0662d4ffb8c | 494 | int WriteReg(BYTE bID, uint16_t wAddr, uint64_t dwData, BYTE bLen, BYTE bWriteType); |
| minamax | 1:d0662d4ffb8c | 495 | int ReadReg(BYTE bID, uint16_t wAddr, BYTE * pData, BYTE bLen, uint32_t dwTimeOut, BYTE bWriteType); |
| minamax | 0:e22b53fffed7 | 496 | |
| minamax | 1:d0662d4ffb8c | 497 | int WriteFrame(BYTE bID, uint16_t wAddr, BYTE * pData, BYTE bLen, BYTE bWriteType); |
| minamax | 1:d0662d4ffb8c | 498 | int ReadFrameReq(BYTE bID, uint16_t wAddr, BYTE bByteToReturn,BYTE bWriteType); |
| minamax | 0:e22b53fffed7 | 499 | |
| minamax | 0:e22b53fffed7 | 500 | //void delayms(uint16 ms); |
| minamax | 0:e22b53fffed7 | 501 | //void delayus(uint16 us); |
| minamax | 0:e22b53fffed7 | 502 | //float Complement(uint16 rawData, float multiplier); |
| minamax | 1:d0662d4ffb8c | 503 | #endif |