mi mi / Scheduler

For Cortex-M3,Cortex-M0, Multitask scheduler library. Arduino due compatible

Dependents:   scheduler-demo-cq-lpc11u35 scheduler-demo scheduler-demo-cq-lpc11u35 mbed-scli-test

Diff: Scheduler.cpp

Revision:
1:8967b575bb46
Parent:
0:c68459544a17
diff -r c68459544a17 -r 8967b575bb46 Scheduler.cpp
--- a/Scheduler.cpp	Sun Aug 25 16:48:21 2013 +0900
+++ b/Scheduler.cpp	Sun Aug 25 10:25:11 2013 +0000
@@ -1,6 +1,7 @@
 /*
- * Copyright (C) 2012 audin
+ * Copyright (C) 2012-2013 audin
  * This program is licensed under the Apache License, Version 2.0.
+ * 2013/08: Modify for mbed for LPC1114FN28
  * Modified 2012/10: For working on Cortex-M0 and M3.
  *                   Defined static tcb option for the cpu that has quite a less SRAM < 8kbyte.  
  *
@@ -24,6 +25,7 @@
  */
 
 #include <stdint.h>
+#include "mbed.h"
 #include "Scheduler.h"
 
 #define _ARM_CM0_			1		/* 1: Cortex-M0 or M3,  0: Cortex-M3		*/
@@ -77,7 +79,44 @@
 	cur = next;
 	return next;
 }
+#ifdef __CC_ARM 
+__asm static void coopTaskStart(void) {
+	import coopSchedule
+#if _ARM_CM0_
+	/* for Cortex-m0 */
+		mov   r0, r5;
+		blx   r4;
+		movs   r0, #1;
+		bl    coopSchedule;
+	/****	ldmia r0, {r4-r12, lr};	*/
+		adds r0, r0, #16;
+		ldmia r0!, {r4-r7};		/* get r7->r11, r6->r10, r5->r9, r4->r8		*/
+		mov r11, r7;
+		mov r10, r6;
+		mov r9,  r5;
+		mov r8 , r4;
 
+		ldmia r0!, {r4-r5};		/* get r5->lr, r4->r12						*/
+		mov lr,  r5;
+		mov r12, r4;
+
+		subs r0, r0, #40;			/* set offset for r4, 40 = 10reg * 4byte	*/
+		ldmia  r0!, {r4-r7};		/* get r7,r6,r5,r4							*/
+	/**** end ldmia converted by Cortex-M0 instructions	*/
+		msr   msp, r12;			/* use main stack							*/
+		bx    lr;
+#else
+	/* for Cortex-m3 or ARM code cpu */
+		mov   r0, r5;						/* r5 = new task func */
+		blx   r4;							/* r4 = helper func   */
+		movs   r0, #1;						
+		bl    coopSchedule;
+		ldmia r0, {r4-r12, lr};
+		mov   sp, r12;
+		bx    lr;
+#endif
+}
+#else
 static void __attribute__((naked)) __attribute__((noinline)) coopTaskStart(void) {
 #if _ARM_CM0_
 	/* for Cortex-m0 */
@@ -117,7 +156,61 @@
 	);
 #endif
 }
+#endif
 
+#ifdef __CC_ARM
+__asm static void coopDoYield(CoopTask* curTask) {
+#if _ARM_CM0_
+	/* for Cortex-m0 */
+			mrs   r12, msp;
+		/**** stmia r0, {r4-r12, lr}; */
+			stmia r0!, {r4-r7};		/* first store r4-r7 data				*/
+
+			mov r4, r8;
+			mov r5, r9;
+			mov r6, r10;
+			mov r7, r11;
+			stmia r0!, {r4-r7};		/* store r8-r11							*/
+
+			mov r4, r12;
+			mov r5, lr;
+			stmia r0!, {r4,r5};		/* store r12, lr						*/
+		/**** end stmia converted by cortex-m0 instructions	*/
+
+			movs   r0, #0;
+			bl    coopSchedule;
+
+		/**** ldmia r0, {r4-r12, lr};	*/
+			adds r0, r0, #16;			/* set offset for r8					*/
+			ldmia r0!, {r4-r7};		/* get r7->r11, r6->r10, r5->r9, r4->r8 */
+			mov r11, r7;
+			mov r10, r6;
+			mov r9,  r5;
+			mov r8 , r4;
+
+			ldmia r0!, {r4-r5};		/* get r5->lr, r4->r12					*/
+			mov lr,  r5;
+			mov r12, r4;
+
+			subs r0, r0, #40;			/* set offset for r4, 40 = 10reg * 4byte  */
+			ldmia  r0!, {r4-r7};
+		/**** end ldmia converted by Cortex-M0 instructions	*/
+
+			msr   msp, r12;
+			bx    lr;
+#else
+	/* for Cortex-m3 or ARM code cpu */
+			mov   r12, sp;
+			stmia r0, {r4-r12, lr};
+			movs   r0, #0;
+			bl    coopSchedule;
+			ldmia r0, {r4-r12, lr};
+			mov   sp, r12;
+			bx    lr;
+#endif
+}
+
+#else
 static void __attribute__((naked)) __attribute__((noinline)) coopDoYield(CoopTask* curTask) {
 #if _ARM_CM0_
 	/* for Cortex-m0 */
@@ -173,7 +266,7 @@
 #endif
 
 }
-
+#endif
 static int coopInit(void) {
 	CoopTask* task;
 #if _USE_MALLOC_
@@ -243,11 +336,21 @@
 	coopDoYield(cur);
 }
 
+#ifdef MBED_H
+void taskWait(uint32_t ms) {
+    uint32_t start = us_ticker_read();
+    while ((us_ticker_read() - start) < (uint32_t)(ms*1000)){
+		yield();
+    }
+}
+#else
 void wait(uint32_t ms) {
 	uint32_t start = millis();
-	while (millis() - start < ms)
+	while (millis() - start < ms){
 		yield();
+	}
 }
+#endif
 
 #ifdef __cplusplus
 }; // extern "C"