first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.
Dependents: SDFileSystemDMA-test DmdFullRGB_0_1
Fork of SDFileSystemDMA by
SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)
Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/
Supported SPI port is shown below table.
(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.
Caution
If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.
Supported Boards:
Cortex-M0
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
NUCLEO-F030R8 | 8KB | (v) | ||
DISCO-F051R8 | 8KB | (w) | ||
4KB | (f) | |||
NUCLEO-F042K6 | 6KB | (r) | ||
NUCLEO-F070RB | 16KB | (w) | ||
NUCLEO-F072RB | 16KB | (w) | ||
NUCLEO-F091RC | 32KB | (c) |
Cortex-L0
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
DISCO-L053C8 | 8KB | (c) | ||
NUCLEO-L053R8 | 8KB | (c) | ||
NUCLEO-L073RZ | 20KB | (c) |
Cortex-M3
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
DISCO-F100RB | 8KB | (v) | (v) | - |
BLUEPILL-F103CB | 20KB | (w) | (w) | - |
NUCLEO-F103RB | 20KB | (v) | (v) | - |
NUCLEO-L152RE | 80KB | (v) | (w) | - |
MOTE-L152RC | 32KB | (w) | (w) | - |
Cortex-M4
F3
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
DISCO-F303VC | 40KB | - | (v) | (v) |
NUCLEO-F303RE | 64KB | (w) | (w) | (w) |
NUCLEO-F302R8 | 16KB | - | - | (c) |
NUCLEO-F303K8 | 12KB | (c) | - | - |
DISCO-F334C8 | 12KB | (c) | - | - |
NUCLEO-F334R8 | 12KB | (c) | - | - |
F4
Board | SPI1 | SPI2 | SPI3 |
---|---|---|---|
ELMO-F411RE | (w) | - | (w) |
MTS-MDOT-F411RE | (u) | - | (u) |
MTS-DRAGONFLY-F411RE | (w) | - | (w) |
NUCLEO-F411RE | (v) | - | (v) |
NUCLEO-F401RE | (w) | - | (w) |
MTS-MDOT-F405RG | (u) | - | (u) |
NUCLEO-F410RB | (c) | - | (c) |
NUCLEO-F446RE | (c) | - | (c) |
NUCLEO-F429ZI | (c) | - | (c) |
B96B-F446VE | (c) | - | (c) |
NUCLEO-F446ZE | (c) | - | (c) |
DISCO-F429ZI | (u) | - | (u) |
DISCO-F469NI | (c) | - | (c) |
Information
This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .
spi_dma/spi_dma_stm32f0.c@21:41129109d6ab, 2016-02-16 (annotated)
- Committer:
- mimi3
- Date:
- Tue Feb 16 23:45:35 2016 +0900
- Revision:
- 21:41129109d6ab
- Parent:
- 19:3fdd401607c8
- Child:
- 30:dde6a5f67add
For F0,F1,F4: Generalize SPI device name.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mimi3 | 2:0e871408d51b | 1 | #if defined(TARGET_STM32F0) |
mimi3 | 2:0e871408d51b | 2 | /* |
mimi3 | 2:0e871408d51b | 3 | |
mimi3 | 2:0e871408d51b | 4 | This file is licensed under Apache 2.0 license. |
mimi3 | 2:0e871408d51b | 5 | (C) 2016 dinau |
mimi3 | 2:0e871408d51b | 6 | |
mimi3 | 2:0e871408d51b | 7 | */ |
mimi3 | 2:0e871408d51b | 8 | #include "spi_dma.h" |
mimi3 | 2:0e871408d51b | 9 | |
mimi3 | 21:41129109d6ab | 10 | /* For SPI1 */ |
mimi3 | 18:1b1a0e68008a | 11 | #define DMAx_CLK_ENABLE() __DMA1_CLK_ENABLE() |
mimi3 | 18:1b1a0e68008a | 12 | #define SPIx_TX_DMA_CHANNEL DMA1_Channel3 |
mimi3 | 18:1b1a0e68008a | 13 | #define SPIx_RX_DMA_CHANNEL DMA1_Channel2 |
mimi3 | 21:41129109d6ab | 14 | #if defined(TARGET_STM32F091RC) |
mimi3 | 21:41129109d6ab | 15 | #define SPIx_DMA_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn |
mimi3 | 21:41129109d6ab | 16 | #define DMA_SPI_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
mimi3 | 21:41129109d6ab | 17 | #else |
mimi3 | 21:41129109d6ab | 18 | #define SPIx_DMA_IRQn DMA1_Channel2_3_IRQn |
mimi3 | 21:41129109d6ab | 19 | #define DMA_SPI_IRQHandler DMA1_Channel2_3_IRQHandler |
mimi3 | 21:41129109d6ab | 20 | #endif |
mimi3 | 21:41129109d6ab | 21 | |
mimi3 | 18:1b1a0e68008a | 22 | |
mimi3 | 18:1b1a0e68008a | 23 | #if defined(TARGET_STM32F091RC) |
mimi3 | 18:1b1a0e68008a | 24 | #define SPIx_DMA_IRQn DMA1_Ch2_3_DMA2_Ch1_2_IRQn |
mimi3 | 18:1b1a0e68008a | 25 | #define DMA_SPI_IRQHandler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
mimi3 | 18:1b1a0e68008a | 26 | #else |
mimi3 | 18:1b1a0e68008a | 27 | #define SPIx_DMA_IRQn DMA1_Channel2_3_IRQn |
mimi3 | 18:1b1a0e68008a | 28 | #define DMA_SPI_IRQHandler DMA1_Channel2_3_IRQHandler |
mimi3 | 18:1b1a0e68008a | 29 | #endif |
mimi3 | 18:1b1a0e68008a | 30 | |
mimi3 | 18:1b1a0e68008a | 31 | #define readReg( reg, mask) ( (reg) & (mask) ) |
mimi3 | 2:0e871408d51b | 32 | |
mimi3 | 2:0e871408d51b | 33 | void spi_dma_get_info( SPI_TypeDef *spi ) |
mimi3 | 2:0e871408d51b | 34 | { |
mimi3 | 21:41129109d6ab | 35 | SpiHandle.Instance = spi; |
mimi3 | 21:41129109d6ab | 36 | SpiHandle.Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER); |
mimi3 | 21:41129109d6ab | 37 | SpiHandle.Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR); |
mimi3 | 21:41129109d6ab | 38 | SpiHandle.Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE); |
mimi3 | 21:41129109d6ab | 39 | SpiHandle.Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA); |
mimi3 | 21:41129109d6ab | 40 | SpiHandle.Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL); |
mimi3 | 21:41129109d6ab | 41 | SpiHandle.Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN); |
mimi3 | 21:41129109d6ab | 42 | SpiHandle.Init.CRCPolynomial = spi->CRCPR & 0xFFFF; |
mimi3 | 21:41129109d6ab | 43 | SpiHandle.Init.DataSize = readReg(spi->CR2, SPI_CR2_DS); |
mimi3 | 21:41129109d6ab | 44 | SpiHandle.Init.FirstBit = SPI_FIRSTBIT_MSB; |
mimi3 | 21:41129109d6ab | 45 | SpiHandle.Init.NSS = readReg(spi->CR1, SPI_CR1_SSM); |
mimi3 | 21:41129109d6ab | 46 | SpiHandle.Init.TIMode = SPI_TIMODE_DISABLED; |
mimi3 | 21:41129109d6ab | 47 | SpiHandle.State = HAL_SPI_STATE_READY; |
mimi3 | 2:0e871408d51b | 48 | } |
mimi3 | 2:0e871408d51b | 49 | |
mimi3 | 18:1b1a0e68008a | 50 | void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode ) |
mimi3 | 18:1b1a0e68008a | 51 | { |
mimi3 | 21:41129109d6ab | 52 | (void)spi; |
mimi3 | 21:41129109d6ab | 53 | static uint8_t dma_handle_inited = 0; |
mimi3 | 21:41129109d6ab | 54 | /* Peripheral DMA init*/ |
mimi3 | 21:41129109d6ab | 55 | /* TX: */ |
mimi3 | 21:41129109d6ab | 56 | if( !dma_handle_inited ){ |
mimi3 | 21:41129109d6ab | 57 | hdma_spi_tx.Instance = SPIx_TX_DMA_CHANNEL; |
mimi3 | 21:41129109d6ab | 58 | hdma_spi_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; |
mimi3 | 21:41129109d6ab | 59 | hdma_spi_tx.Init.PeriphInc = DMA_PINC_DISABLE; |
mimi3 | 21:41129109d6ab | 60 | hdma_spi_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; |
mimi3 | 21:41129109d6ab | 61 | hdma_spi_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
mimi3 | 21:41129109d6ab | 62 | hdma_spi_tx.Init.Mode = DMA_NORMAL; |
mimi3 | 21:41129109d6ab | 63 | hdma_spi_tx.Init.Priority = DMA_PRIORITY_HIGH; |
mimi3 | 21:41129109d6ab | 64 | } |
mimi3 | 21:41129109d6ab | 65 | hdma_spi_tx.Init.MemInc = ( mode == DMA_SPI_READ) ? DMA_MINC_DISABLE : DMA_MINC_ENABLE; |
mimi3 | 21:41129109d6ab | 66 | HAL_DMA_Init(&hdma_spi_tx); |
mimi3 | 21:41129109d6ab | 67 | __HAL_LINKDMA( &SpiHandle,hdmatx,hdma_spi_tx); |
mimi3 | 21:41129109d6ab | 68 | /* RX: */ |
mimi3 | 21:41129109d6ab | 69 | if( !dma_handle_inited ){ |
mimi3 | 21:41129109d6ab | 70 | hdma_spi_rx.Instance = SPIx_RX_DMA_CHANNEL; |
mimi3 | 21:41129109d6ab | 71 | hdma_spi_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; |
mimi3 | 21:41129109d6ab | 72 | hdma_spi_rx.Init.PeriphInc = DMA_PINC_DISABLE; |
mimi3 | 21:41129109d6ab | 73 | hdma_spi_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; |
mimi3 | 21:41129109d6ab | 74 | hdma_spi_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
mimi3 | 21:41129109d6ab | 75 | hdma_spi_rx.Init.Mode = DMA_NORMAL; |
mimi3 | 21:41129109d6ab | 76 | hdma_spi_rx.Init.Priority = DMA_PRIORITY_LOW; |
mimi3 | 21:41129109d6ab | 77 | } |
mimi3 | 21:41129109d6ab | 78 | hdma_spi_rx.Init.MemInc = (mode == DMA_SPI_READ) ? DMA_MINC_ENABLE : DMA_MINC_DISABLE; |
mimi3 | 21:41129109d6ab | 79 | HAL_DMA_Init(&hdma_spi_rx); |
mimi3 | 21:41129109d6ab | 80 | __HAL_LINKDMA( &SpiHandle,hdmarx,hdma_spi_rx); |
mimi3 | 2:0e871408d51b | 81 | |
mimi3 | 21:41129109d6ab | 82 | dma_handle_inited = 1; |
mimi3 | 2:0e871408d51b | 83 | } |
mimi3 | 2:0e871408d51b | 84 | |
mimi3 | 2:0e871408d51b | 85 | void spi_dma_irq_setup( SPI_TypeDef *spi) |
mimi3 | 2:0e871408d51b | 86 | { |
mimi3 | 21:41129109d6ab | 87 | (void)spi; |
mimi3 | 21:41129109d6ab | 88 | /* DMA controller clock enable */ |
mimi3 | 21:41129109d6ab | 89 | DMAx_CLK_ENABLE(); |
mimi3 | 2:0e871408d51b | 90 | |
mimi3 | 21:41129109d6ab | 91 | /* DMA interrupt init */ |
mimi3 | 21:41129109d6ab | 92 | HAL_NVIC_SetPriority(SPIx_DMA_IRQn, 1, 0); |
mimi3 | 21:41129109d6ab | 93 | HAL_NVIC_EnableIRQ( SPIx_DMA_IRQn); |
mimi3 | 2:0e871408d51b | 94 | } |
mimi3 | 2:0e871408d51b | 95 | |
mimi3 | 18:1b1a0e68008a | 96 | void DMA_SPI_IRQHandler(void) |
mimi3 | 2:0e871408d51b | 97 | { |
mimi3 | 21:41129109d6ab | 98 | HAL_DMA_IRQHandler(&hdma_spi_rx); |
mimi3 | 21:41129109d6ab | 99 | HAL_DMA_IRQHandler(&hdma_spi_tx); |
mimi3 | 2:0e871408d51b | 100 | } |
mimi3 | 2:0e871408d51b | 101 | |
mimi3 | 2:0e871408d51b | 102 | |
mimi3 | 18:1b1a0e68008a | 103 | #endif /* TARGET_STM32F0 */ |
mimi3 | 2:0e871408d51b | 104 |