first 2016/02 SDFileSystemDMA inherited from Official SDFileSystem.
Dependents: SDFileSystemDMA-test DmdFullRGB_0_1
Fork of SDFileSystemDMA by
SDFileSystemDMA is enhanced SDFileSystem library for STM32 micros by using DMA functionality.
Max read transfer rate reaches over 2MByte/sec at 24MHz SPI clock if enough read buffer size is set.
Even though minimum read buffer size (512Byte) is set, read transfer rate will reach over 1MByte/sec at 24MHz SPI Clock.
( but depends on the ability of each SD card)
Test program is here.
https://developer.mbed.org/users/mimi3/code/SDFileSystemDMA-test/
Supported SPI port is shown below table.
(v): Verified. It works well.
(w): Probably it will work well. (not tested)
(c): Only compiled. (not tested)
(f): Over flash.
(r): Only read mode. (when _FS_READONLY==1)
(u) Under construction
(z): Dose not work.
Caution
If your board has SRAM less than or equal to 8KB, the buffer size must be set to 512 Bytes.
Supported Boards:
Cortex-M0
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
NUCLEO-F030R8 | 8KB | (v) | ||
DISCO-F051R8 | 8KB | (w) | ||
4KB | (f) | |||
NUCLEO-F042K6 | 6KB | (r) | ||
NUCLEO-F070RB | 16KB | (w) | ||
NUCLEO-F072RB | 16KB | (w) | ||
NUCLEO-F091RC | 32KB | (c) |
Cortex-L0
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
DISCO-L053C8 | 8KB | (c) | ||
NUCLEO-L053R8 | 8KB | (c) | ||
NUCLEO-L073RZ | 20KB | (c) |
Cortex-M3
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
DISCO-F100RB | 8KB | (v) | (v) | - |
BLUEPILL-F103CB | 20KB | (w) | (w) | - |
NUCLEO-F103RB | 20KB | (v) | (v) | - |
NUCLEO-L152RE | 80KB | (v) | (w) | - |
MOTE-L152RC | 32KB | (w) | (w) | - |
Cortex-M4
F3
Board | SRAM | SPI1 | SPI2 | SPI3 |
---|---|---|---|---|
DISCO-F303VC | 40KB | - | (v) | (v) |
NUCLEO-F303RE | 64KB | (w) | (w) | (w) |
NUCLEO-F302R8 | 16KB | - | - | (c) |
NUCLEO-F303K8 | 12KB | (c) | - | - |
DISCO-F334C8 | 12KB | (c) | - | - |
NUCLEO-F334R8 | 12KB | (c) | - | - |
F4
Board | SPI1 | SPI2 | SPI3 |
---|---|---|---|
ELMO-F411RE | (w) | - | (w) |
MTS-MDOT-F411RE | (u) | - | (u) |
MTS-DRAGONFLY-F411RE | (w) | - | (w) |
NUCLEO-F411RE | (v) | - | (v) |
NUCLEO-F401RE | (w) | - | (w) |
MTS-MDOT-F405RG | (u) | - | (u) |
NUCLEO-F410RB | (c) | - | (c) |
NUCLEO-F446RE | (c) | - | (c) |
NUCLEO-F429ZI | (c) | - | (c) |
B96B-F446VE | (c) | - | (c) |
NUCLEO-F446ZE | (c) | - | (c) |
DISCO-F429ZI | (u) | - | (u) |
DISCO-F469NI | (c) | - | (c) |
Information
This library is set to use "short file name" in SDFileSystemDMA/FATFileSystem/ChaN/ffconf.h . ( _USE_LFN=0)
You can change this option to _USE_LFN=1 .
spi_dma/spi_dma_stm32f0.c@2:0e871408d51b, 2016-02-13 (annotated)
- Committer:
- mimi3
- Date:
- Sat Feb 13 18:50:11 2016 +0900
- Revision:
- 2:0e871408d51b
- Child:
- 18:1b1a0e68008a
split files for each model
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
mimi3 | 2:0e871408d51b | 1 | #if defined(TARGET_STM32F0) |
mimi3 | 2:0e871408d51b | 2 | /* |
mimi3 | 2:0e871408d51b | 3 | |
mimi3 | 2:0e871408d51b | 4 | This file is licensed under Apache 2.0 license. |
mimi3 | 2:0e871408d51b | 5 | (C) 2016 dinau |
mimi3 | 2:0e871408d51b | 6 | |
mimi3 | 2:0e871408d51b | 7 | */ |
mimi3 | 2:0e871408d51b | 8 | #include "spi_dma.h" |
mimi3 | 2:0e871408d51b | 9 | |
mimi3 | 2:0e871408d51b | 10 | #define readReg( reg, mask) ( (reg) & (mask) ) |
mimi3 | 2:0e871408d51b | 11 | |
mimi3 | 2:0e871408d51b | 12 | |
mimi3 | 2:0e871408d51b | 13 | void spi_dma_get_info( SPI_TypeDef *spi ) |
mimi3 | 2:0e871408d51b | 14 | { |
mimi3 | 2:0e871408d51b | 15 | SPI_HandleTypeDef *hspi; |
mimi3 | 2:0e871408d51b | 16 | if( spi == SPI1 ){ |
mimi3 | 2:0e871408d51b | 17 | hspi = &Spi1Handle; |
mimi3 | 2:0e871408d51b | 18 | } |
mimi3 | 2:0e871408d51b | 19 | #if 0 |
mimi3 | 2:0e871408d51b | 20 | else { |
mimi3 | 2:0e871408d51b | 21 | hspi = &Spi2Handle; |
mimi3 | 2:0e871408d51b | 22 | } |
mimi3 | 2:0e871408d51b | 23 | #endif |
mimi3 | 2:0e871408d51b | 24 | hspi->Instance = spi; |
mimi3 | 2:0e871408d51b | 25 | hspi->Init.Mode = readReg(spi->CR1, SPI_MODE_MASTER); |
mimi3 | 2:0e871408d51b | 26 | hspi->Init.BaudRatePrescaler = readReg(spi->CR1, SPI_CR1_BR); |
mimi3 | 2:0e871408d51b | 27 | hspi->Init.Direction = readReg(spi->CR1, SPI_CR1_BIDIMODE); |
mimi3 | 2:0e871408d51b | 28 | hspi->Init.CLKPhase = readReg(spi->CR1, SPI_CR1_CPHA); |
mimi3 | 2:0e871408d51b | 29 | hspi->Init.CLKPolarity = readReg(spi->CR1, SPI_CR1_CPOL); |
mimi3 | 2:0e871408d51b | 30 | hspi->Init.CRCCalculation = readReg(spi->CR1, SPI_CR1_CRCEN); |
mimi3 | 2:0e871408d51b | 31 | hspi->Init.CRCPolynomial = spi->CRCPR & 0xFFFF; |
mimi3 | 2:0e871408d51b | 32 | hspi->Init.DataSize = readReg(spi->CR2, SPI_CR2_DS); |
mimi3 | 2:0e871408d51b | 33 | hspi->Init.FirstBit = SPI_FIRSTBIT_MSB; |
mimi3 | 2:0e871408d51b | 34 | hspi->Init.NSS = readReg(spi->CR1, SPI_CR1_SSM); |
mimi3 | 2:0e871408d51b | 35 | hspi->Init.TIMode = SPI_TIMODE_DISABLED; |
mimi3 | 2:0e871408d51b | 36 | hspi->State = HAL_SPI_STATE_READY; |
mimi3 | 2:0e871408d51b | 37 | } |
mimi3 | 2:0e871408d51b | 38 | |
mimi3 | 2:0e871408d51b | 39 | void spi_dma_handle_setup( SPI_TypeDef *spi, uint8_t mode ){ |
mimi3 | 2:0e871408d51b | 40 | /* Peripheral DMA init*/ |
mimi3 | 2:0e871408d51b | 41 | if( spi == SPI1 ){ |
mimi3 | 2:0e871408d51b | 42 | /* TX: */ |
mimi3 | 2:0e871408d51b | 43 | hdma_spi1_tx.Instance = DMA1_Channel3; |
mimi3 | 2:0e871408d51b | 44 | hdma_spi1_tx.Init.Direction = DMA_MEMORY_TO_PERIPH; |
mimi3 | 2:0e871408d51b | 45 | hdma_spi1_tx.Init.PeriphInc = DMA_PINC_DISABLE; |
mimi3 | 2:0e871408d51b | 46 | if (mode == DMA_SPI_READ){ |
mimi3 | 2:0e871408d51b | 47 | hdma_spi1_tx.Init.MemInc = DMA_MINC_DISABLE; |
mimi3 | 2:0e871408d51b | 48 | } |
mimi3 | 2:0e871408d51b | 49 | else{ |
mimi3 | 2:0e871408d51b | 50 | hdma_spi1_tx.Init.MemInc = DMA_MINC_ENABLE; |
mimi3 | 2:0e871408d51b | 51 | } |
mimi3 | 2:0e871408d51b | 52 | hdma_spi1_tx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; |
mimi3 | 2:0e871408d51b | 53 | hdma_spi1_tx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
mimi3 | 2:0e871408d51b | 54 | hdma_spi1_tx.Init.Mode = DMA_NORMAL; |
mimi3 | 2:0e871408d51b | 55 | hdma_spi1_tx.Init.Priority = DMA_PRIORITY_HIGH; |
mimi3 | 2:0e871408d51b | 56 | HAL_DMA_Init(&hdma_spi1_tx); |
mimi3 | 2:0e871408d51b | 57 | __HAL_LINKDMA( &Spi1Handle,hdmatx,hdma_spi1_tx); |
mimi3 | 2:0e871408d51b | 58 | |
mimi3 | 2:0e871408d51b | 59 | /* RX: */ |
mimi3 | 2:0e871408d51b | 60 | hdma_spi1_rx.Instance = DMA1_Channel2; |
mimi3 | 2:0e871408d51b | 61 | hdma_spi1_rx.Init.Direction = DMA_PERIPH_TO_MEMORY; |
mimi3 | 2:0e871408d51b | 62 | hdma_spi1_rx.Init.PeriphInc = DMA_PINC_DISABLE; |
mimi3 | 2:0e871408d51b | 63 | if (mode == DMA_SPI_READ){ |
mimi3 | 2:0e871408d51b | 64 | hdma_spi1_rx.Init.MemInc = DMA_MINC_ENABLE; |
mimi3 | 2:0e871408d51b | 65 | } |
mimi3 | 2:0e871408d51b | 66 | else{ |
mimi3 | 2:0e871408d51b | 67 | hdma_spi1_rx.Init.MemInc = DMA_MINC_DISABLE; |
mimi3 | 2:0e871408d51b | 68 | } |
mimi3 | 2:0e871408d51b | 69 | hdma_spi1_rx.Init.PeriphDataAlignment = DMA_PDATAALIGN_BYTE; |
mimi3 | 2:0e871408d51b | 70 | hdma_spi1_rx.Init.MemDataAlignment = DMA_MDATAALIGN_BYTE; |
mimi3 | 2:0e871408d51b | 71 | hdma_spi1_rx.Init.Mode = DMA_NORMAL; |
mimi3 | 2:0e871408d51b | 72 | hdma_spi1_rx.Init.Priority = DMA_PRIORITY_LOW; |
mimi3 | 2:0e871408d51b | 73 | HAL_DMA_Init(&hdma_spi1_rx); |
mimi3 | 2:0e871408d51b | 74 | |
mimi3 | 2:0e871408d51b | 75 | __HAL_LINKDMA( &Spi1Handle,hdmarx,hdma_spi1_rx); |
mimi3 | 2:0e871408d51b | 76 | } |
mimi3 | 2:0e871408d51b | 77 | #if 0 |
mimi3 | 2:0e871408d51b | 78 | else if( spi == SPI2 ) { |
mimi3 | 2:0e871408d51b | 79 | |
mimi3 | 2:0e871408d51b | 80 | } |
mimi3 | 2:0e871408d51b | 81 | #endif |
mimi3 | 2:0e871408d51b | 82 | } |
mimi3 | 2:0e871408d51b | 83 | |
mimi3 | 2:0e871408d51b | 84 | void spi_dma_irq_setup( SPI_TypeDef *spi) |
mimi3 | 2:0e871408d51b | 85 | { |
mimi3 | 2:0e871408d51b | 86 | if( spi == SPI1 ) { |
mimi3 | 2:0e871408d51b | 87 | /* DMA controller clock enable */ |
mimi3 | 2:0e871408d51b | 88 | __DMA1_CLK_ENABLE(); |
mimi3 | 2:0e871408d51b | 89 | |
mimi3 | 2:0e871408d51b | 90 | /* DMA interrupt init */ |
mimi3 | 2:0e871408d51b | 91 | |
mimi3 | 2:0e871408d51b | 92 | #if defined(TARGET_STM32F091RC) |
mimi3 | 2:0e871408d51b | 93 | HAL_NVIC_SetPriority(DMA1_Ch2_3_DMA2_Ch1_2_IRQn, 1, 0); |
mimi3 | 2:0e871408d51b | 94 | HAL_NVIC_EnableIRQ( DMA1_Ch2_3_DMA2_Ch1_2_IRQn); |
mimi3 | 2:0e871408d51b | 95 | #else |
mimi3 | 2:0e871408d51b | 96 | HAL_NVIC_SetPriority(DMA1_Channel2_3_IRQn, 1, 0); |
mimi3 | 2:0e871408d51b | 97 | HAL_NVIC_EnableIRQ( DMA1_Channel2_3_IRQn); |
mimi3 | 2:0e871408d51b | 98 | #endif |
mimi3 | 2:0e871408d51b | 99 | |
mimi3 | 2:0e871408d51b | 100 | } |
mimi3 | 2:0e871408d51b | 101 | #if 0 |
mimi3 | 2:0e871408d51b | 102 | else if ( spi == SPI2 ){ |
mimi3 | 2:0e871408d51b | 103 | |
mimi3 | 2:0e871408d51b | 104 | } |
mimi3 | 2:0e871408d51b | 105 | #endif |
mimi3 | 2:0e871408d51b | 106 | } |
mimi3 | 2:0e871408d51b | 107 | |
mimi3 | 2:0e871408d51b | 108 | |
mimi3 | 2:0e871408d51b | 109 | #if defined(TARGET_STM32F091RC) |
mimi3 | 2:0e871408d51b | 110 | #define DMA_SPI_IRQ_Handler DMA1_Ch2_3_DMA2_Ch1_2_IRQHandler |
mimi3 | 2:0e871408d51b | 111 | #else |
mimi3 | 2:0e871408d51b | 112 | #define DMA_SPI_IRQ_Handler DMA1_Channel2_3_IRQHandler |
mimi3 | 2:0e871408d51b | 113 | #endif |
mimi3 | 2:0e871408d51b | 114 | void DMA_SPI_IRQ_Handler(void) |
mimi3 | 2:0e871408d51b | 115 | { |
mimi3 | 2:0e871408d51b | 116 | HAL_DMA_IRQHandler(&hdma_spi1_rx); |
mimi3 | 2:0e871408d51b | 117 | HAL_DMA_IRQHandler(&hdma_spi1_tx); |
mimi3 | 2:0e871408d51b | 118 | } |
mimi3 | 2:0e871408d51b | 119 | |
mimi3 | 2:0e871408d51b | 120 | |
mimi3 | 2:0e871408d51b | 121 | #endif /* TARGET_STM32F1 */ |
mimi3 | 2:0e871408d51b | 122 |