mi mi / FastPWM

My forked repository. DISCO_F407VG, DISCO_F303VC, DISCO_F051R8 and DISCO_F100RB maybe added.

Dependents:   FastPWM-DISCO-test

Fork of FastPWM by Erik -

Device/FastPWM_STM_TIM_PinOut.cpp@24:3467fafa8a21, 2016-02-11 (annotated)

Committer:
mimi3
Date:
Thu Feb 11 03:35:05 2016 +0900
Revision:
24:3467fafa8a21
Parent:
21:aa2884be5496 
Added: DISCO-{F051R8, F100RB, F303VC, F407VG}

       NUCLEO-L152RE

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Sissors 13:cdefd9d75b64 1 #include "mbed.h"
Sissors 13:cdefd9d75b64 2
mimi3 24:3467fafa8a21 3 #if defined (TARGET_NUCLEO_F030R8) || (TARGET_DISCO_F051R8)
Sissors 13:cdefd9d75b64 4 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 13:cdefd9d75b64 5 switch (pin) {
Sissors 13:cdefd9d75b64 6 // Channels 1
Sissors 13:cdefd9d75b64 7 case PA_4: case PA_6: case PB_1: case PB_4: case PB_8: case PB_9: case PB_14: case PC_6: case PB_6: case PB_7:
Sissors 13:cdefd9d75b64 8 return &pwm->CCR1;
Sissors 13:cdefd9d75b64 9
Sissors 13:cdefd9d75b64 10 // Channels 2
Sissors 13:cdefd9d75b64 11 case PA_7: case PB_5: case PC_7:
Sissors 13:cdefd9d75b64 12 return &pwm->CCR2;
Sissors 13:cdefd9d75b64 13
Sissors 13:cdefd9d75b64 14 // Channels 3
Sissors 13:cdefd9d75b64 15 case PB_0: case PC_8:
Sissors 13:cdefd9d75b64 16 return &pwm->CCR3;
Sissors 13:cdefd9d75b64 17
Sissors 13:cdefd9d75b64 18 // Channels 4
Sissors 13:cdefd9d75b64 19 case PC_9:
Sissors 13:cdefd9d75b64 20 return &pwm->CCR4;
mimi3 24:3467fafa8a21 21 default:
mimi3 24:3467fafa8a21 22 /* NOP */
mimi3 24:3467fafa8a21 23 break;
Sissors 13:cdefd9d75b64 24 }
Sissors 13:cdefd9d75b64 25 return NULL;
Sissors 13:cdefd9d75b64 26 }
Sissors 13:cdefd9d75b64 27 #endif
Sissors 13:cdefd9d75b64 28
jocis 15:49a7eff133b3 29 #if defined TARGET_NUCLEO_F401RE || defined TARGET_NUCLEO_F411RE
Sissors 13:cdefd9d75b64 30 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 13:cdefd9d75b64 31 switch (pin) {
jocis 16:ec208b5ec0bb 32 // Channels 1 : PWMx/1
Sissors 13:cdefd9d75b64 33 case PA_0: case PA_5: case PA_6: case PA_8: case PA_15: case PB_4: case PB_6: case PC_6: case PA_7: case PB_13:
Sissors 13:cdefd9d75b64 34 return &pwm->CCR1;
Sissors 13:cdefd9d75b64 35
jocis 16:ec208b5ec0bb 36 // Channels 2 : PWMx/2
Sissors 13:cdefd9d75b64 37 case PA_1: case PA_9: case PB_3: case PB_5: case PB_7: case PC_7: case PB_0: case PB_14:
Sissors 13:cdefd9d75b64 38 return &pwm->CCR2;
Sissors 13:cdefd9d75b64 39
jocis 16:ec208b5ec0bb 40 // Channels 3 : PWMx/3
Sissors 13:cdefd9d75b64 41 case PA_2: case PA_10: case PB_8: case PB_10: case PC_8: case PB_1: case PB_15:
Sissors 13:cdefd9d75b64 42 return &pwm->CCR3;
Sissors 13:cdefd9d75b64 43
jocis 16:ec208b5ec0bb 44 // Channels 4 : PWMx/4
Sissors 13:cdefd9d75b64 45 case PA_3: case PA_11: case PB_9: case PC_9:
Sissors 13:cdefd9d75b64 46 return &pwm->CCR4;
mimi3 24:3467fafa8a21 47 default:
mimi3 24:3467fafa8a21 48 /* NOP */
mimi3 24:3467fafa8a21 49 break;
Sissors 13:cdefd9d75b64 50 }
Sissors 13:cdefd9d75b64 51 return NULL;
Sissors 13:cdefd9d75b64 52 }
jocis 16:ec208b5ec0bb 53 #endif
jocis 16:ec208b5ec0bb 54
mimi3 24:3467fafa8a21 55 #if defined (TARGET_NUCLEO_F103RB) || (TARGET_DISCO_F100RB)
mimi3 24:3467fafa8a21 56 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
jocis 16:ec208b5ec0bb 57 switch (pin) {
jocis 16:ec208b5ec0bb 58 // Channels 1 : PWMx/1
jocis 16:ec208b5ec0bb 59 case PA_6: case PA_8: case PA_15: case PB_4: case PC_6: case PB_13:
jocis 17:8378bc456f0d 60 return &pwm->CCR1;
jocis 16:ec208b5ec0bb 61
jocis 16:ec208b5ec0bb 62 // Channels 2 : PWMx/2
jocis 16:ec208b5ec0bb 63 case PA_1: case PA_7: case PA_9: case PB_3: case PB_5: case PC_7: case PB_14:
jocis 17:8378bc456f0d 64 return &pwm->CCR2;
jocis 16:ec208b5ec0bb 65
jocis 16:ec208b5ec0bb 66 // Channels 3 : PWMx/3
jocis 16:ec208b5ec0bb 67 case PA_2: case PA_10: case PB_0: case PB_10: case PC_8: case PB_15:
jocis 17:8378bc456f0d 68 return &pwm->CCR3;
jocis 16:ec208b5ec0bb 69
jocis 16:ec208b5ec0bb 70 // Channels 4 : PWMx/4
jocis 16:ec208b5ec0bb 71 case PA_3: case PA_11: case PB_1: case PB_11: case PC_9:
jocis 17:8378bc456f0d 72 return &pwm->CCR4;
mimi3 24:3467fafa8a21 73 default:
mimi3 24:3467fafa8a21 74 /* NOP */
mimi3 24:3467fafa8a21 75 break;
jocis 16:ec208b5ec0bb 76 }
jocis 16:ec208b5ec0bb 77 return NULL;
jocis 16:ec208b5ec0bb 78 }
Sissors 19:ba7a5bf634b3 79 #endif
Sissors 19:ba7a5bf634b3 80
Sissors 19:ba7a5bf634b3 81 #ifdef TARGET_NUCLEO_F334R8
Sissors 19:ba7a5bf634b3 82 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
Sissors 19:ba7a5bf634b3 83 switch (pin) {
Sissors 19:ba7a5bf634b3 84 // Channels 1
Sissors 19:ba7a5bf634b3 85 case PA_2: case PA_6: case PA_7: case PA_8: case PA_12: case PB_4: case PB_5: case PB_8: case PB_9: case PB_14: case PC_0: case PC_6:
Sissors 19:ba7a5bf634b3 86 case PA_1: case PA_13: case PB_6: case PB_13: case PC_13:
Sissors 19:ba7a5bf634b3 87 return &pwm->CCR1;
Sissors 19:ba7a5bf634b3 88
Sissors 19:ba7a5bf634b3 89 // Channels 2
Sissors 19:ba7a5bf634b3 90 case PA_3: case PA_4: case PA_9: case PB_15: case PC_1: case PC_7:
Sissors 19:ba7a5bf634b3 91 return &pwm->CCR2;
Sissors 19:ba7a5bf634b3 92
Sissors 19:ba7a5bf634b3 93 // Channels 3
Sissors 19:ba7a5bf634b3 94 case PA_10: case PB_0: case PC_2: case PC_8:
Sissors 19:ba7a5bf634b3 95 case PF_0:
Sissors 19:ba7a5bf634b3 96 return &pwm->CCR3;
Sissors 19:ba7a5bf634b3 97
Sissors 19:ba7a5bf634b3 98 // Channels 4
Sissors 19:ba7a5bf634b3 99 case PA_11: case PB_1: case PB_7: case PC_3: case PC_9:
Sissors 19:ba7a5bf634b3 100 return &pwm->CCR4;
mimi3 24:3467fafa8a21 101 default:
mimi3 24:3467fafa8a21 102 /* NOP */
mimi3 24:3467fafa8a21 103 break;
Sissors 19:ba7a5bf634b3 104 }
Sissors 19:ba7a5bf634b3 105 return NULL;
Sissors 19:ba7a5bf634b3 106 }
altaran 20:3c609bc4ae9c 107 #endif
altaran 20:3c609bc4ae9c 108
altaran 20:3c609bc4ae9c 109 #if defined TARGET_NUCLEO_F072RB
altaran 20:3c609bc4ae9c 110 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
altaran 20:3c609bc4ae9c 111 switch (pin) {
altaran 20:3c609bc4ae9c 112 // Channels 1 : PWMx/1
altaran 20:3c609bc4ae9c 113 case PA_2: case PA_6: case PA_4: case PA_7: case PA_8: case PB_1: case PB_4: case PB_8: case PB_9: case PB_14: case PC_6:
altaran 21:aa2884be5496 114 // Channels 1N : PWMx/1N
altaran 21:aa2884be5496 115 case PA_1: case PB_6: case PB_7: case PB_13:
altaran 20:3c609bc4ae9c 116 return &pwm->CCR1;
altaran 20:3c609bc4ae9c 117
altaran 20:3c609bc4ae9c 118 // Channels 2 : PWMx/2
altaran 20:3c609bc4ae9c 119 case PA_3: case PA_9: case PB_5: case PC_7: case PB_15:
altaran 20:3c609bc4ae9c 120 return &pwm->CCR2;
altaran 20:3c609bc4ae9c 121
altaran 20:3c609bc4ae9c 122 // Channels 3 : PWMx/3
altaran 20:3c609bc4ae9c 123 case PA_10: case PB_0: case PC_8:
altaran 20:3c609bc4ae9c 124 return &pwm->CCR3;
altaran 20:3c609bc4ae9c 125
altaran 20:3c609bc4ae9c 126 // Channels 4 : PWMx/4
altaran 20:3c609bc4ae9c 127 case PA_11: case PC_9:
altaran 20:3c609bc4ae9c 128 return &pwm->CCR4;
mimi3 24:3467fafa8a21 129 default:
mimi3 24:3467fafa8a21 130 /* NOP */
mimi3 24:3467fafa8a21 131 break;
mimi3 24:3467fafa8a21 132 }
mimi3 24:3467fafa8a21 133 return NULL;
mimi3 24:3467fafa8a21 134 }
mimi3 24:3467fafa8a21 135 #endif
mimi3 24:3467fafa8a21 136
mimi3 24:3467fafa8a21 137 #if defined (TARGET_NUCLEO_L152RE)
mimi3 24:3467fafa8a21 138 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
mimi3 24:3467fafa8a21 139 switch (pin) {
mimi3 24:3467fafa8a21 140 // Channels 1 : PWMx/1
mimi3 24:3467fafa8a21 141 case PA_6: case PB_4: case PB_12: case PB_13: case PC_6:
mimi3 24:3467fafa8a21 142 return &pwm->CCR1;
mimi3 24:3467fafa8a21 143
mimi3 24:3467fafa8a21 144 // Channels 2 : PWMx/2
mimi3 24:3467fafa8a21 145 case PA_1: case PA_7: case PB_3: case PB_5: case PB_14: case PB_7: case PC_7:
mimi3 24:3467fafa8a21 146 return &pwm->CCR2;
mimi3 24:3467fafa8a21 147
mimi3 24:3467fafa8a21 148 // Channels 3 : PWMx/3
mimi3 24:3467fafa8a21 149 case PA_2: case PB_0: case PB_8: case PB_10: case PC_8:
mimi3 24:3467fafa8a21 150 return &pwm->CCR3;
mimi3 24:3467fafa8a21 151
mimi3 24:3467fafa8a21 152 // Channels 4 : PWMx/4
mimi3 24:3467fafa8a21 153 case PA_3: case PB_1:case PB_9: case PB_11: case PC_9:
mimi3 24:3467fafa8a21 154 return &pwm->CCR4;
mimi3 24:3467fafa8a21 155 default:
mimi3 24:3467fafa8a21 156 /* NOP */
mimi3 24:3467fafa8a21 157 break;
altaran 20:3c609bc4ae9c 158 }
altaran 20:3c609bc4ae9c 159 return NULL;
altaran 20:3c609bc4ae9c 160 }
mimi3 24:3467fafa8a21 161 #endif
mimi3 24:3467fafa8a21 162
mimi3 24:3467fafa8a21 163 #ifdef TARGET_DISCO_F303VC
mimi3 24:3467fafa8a21 164 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
mimi3 24:3467fafa8a21 165 switch (pin) {
mimi3 24:3467fafa8a21 166 // Channels 1
mimi3 24:3467fafa8a21 167 case PA_1: case PA_2: case PA_6: case PA_7: case PA_8: case PA_12: case PA_13:
mimi3 24:3467fafa8a21 168 case PB_3: case PB_4: case PB_5: case PB_6: case PB_7: case PB_8: case PB_9: case PB_13: case PB_14:
mimi3 24:3467fafa8a21 169 case PC_6: case PC_10:
mimi3 24:3467fafa8a21 170 case PD_12:
mimi3 24:3467fafa8a21 171 case PE_0:case PE_1:case PE_2:case PE_8:case PE_9:
mimi3 24:3467fafa8a21 172 return &pwm->CCR1;
mimi3 24:3467fafa8a21 173
mimi3 24:3467fafa8a21 174 // Channels 2
mimi3 24:3467fafa8a21 175 case PA_3: case PA_4: case PA_9: case PA_14:
mimi3 24:3467fafa8a21 176 case PB_0:case PB_15:
mimi3 24:3467fafa8a21 177 case PC_7:
mimi3 24:3467fafa8a21 178 case PD_13:
mimi3 24:3467fafa8a21 179 case PE_3: case PE_10: case PE_11:
mimi3 24:3467fafa8a21 180 return &pwm->CCR2;
mimi3 24:3467fafa8a21 181
mimi3 24:3467fafa8a21 182 // Channels 3
mimi3 24:3467fafa8a21 183 case PA_10:
mimi3 24:3467fafa8a21 184 case PB_1:
mimi3 24:3467fafa8a21 185 case PC_8: case PC_12:
mimi3 24:3467fafa8a21 186 case PD_14:
mimi3 24:3467fafa8a21 187 case PE_4: case PE_12: case PE_13:
mimi3 24:3467fafa8a21 188 case PF_0:
mimi3 24:3467fafa8a21 189 return &pwm->CCR3;
mimi3 24:3467fafa8a21 190
mimi3 24:3467fafa8a21 191 // Channels 4
mimi3 24:3467fafa8a21 192 case PA_11:
mimi3 24:3467fafa8a21 193 case PC_9: case PC_13:
mimi3 24:3467fafa8a21 194 case PD_1: case PD_15:
mimi3 24:3467fafa8a21 195 case PE_5: case PE_14:
mimi3 24:3467fafa8a21 196 return &pwm->CCR4;
mimi3 24:3467fafa8a21 197 default:
mimi3 24:3467fafa8a21 198 /* NOP */
mimi3 24:3467fafa8a21 199 break;
mimi3 24:3467fafa8a21 200 }
mimi3 24:3467fafa8a21 201 return NULL;
mimi3 24:3467fafa8a21 202 }
mimi3 24:3467fafa8a21 203 #endif
mimi3 24:3467fafa8a21 204
mimi3 24:3467fafa8a21 205 #if defined TARGET_DISCO_F407VG
mimi3 24:3467fafa8a21 206 __IO uint32_t* getChannel(TIM_TypeDef* pwm, PinName pin) {
mimi3 24:3467fafa8a21 207 switch (pin) {
mimi3 24:3467fafa8a21 208 // Channels 1 : PWMx/1
mimi3 24:3467fafa8a21 209 case PA_0: case PA_5: case PA_6: case PA_7: case PA_8: case PA_15:
mimi3 24:3467fafa8a21 210 case PB_4: case PB_6: case PB_13:
mimi3 24:3467fafa8a21 211 case PC_6:
mimi3 24:3467fafa8a21 212 case PD_12:
mimi3 24:3467fafa8a21 213 case PE_5: case PE_8: case PE_9:
mimi3 24:3467fafa8a21 214 case PF_6: case PF_7: case PF_8: case PF_9:
mimi3 24:3467fafa8a21 215 case PH_13:
mimi3 24:3467fafa8a21 216 case PI_5:
mimi3 24:3467fafa8a21 217 return &pwm->CCR1;
mimi3 24:3467fafa8a21 218
mimi3 24:3467fafa8a21 219 // Channels 2 : PWMx/2
mimi3 24:3467fafa8a21 220 case PA_1: case PA_9:
mimi3 24:3467fafa8a21 221 case PB_0: case PB_3: case PB_5: case PB_7: case PB_14:
mimi3 24:3467fafa8a21 222 case PC_7:
mimi3 24:3467fafa8a21 223 case PD_13:
mimi3 24:3467fafa8a21 224 case PE_6: case PE_10: case PE_11:
mimi3 24:3467fafa8a21 225 case PH_14:
mimi3 24:3467fafa8a21 226 case PI_6:
mimi3 24:3467fafa8a21 227 return &pwm->CCR2;
mimi3 24:3467fafa8a21 228
mimi3 24:3467fafa8a21 229 // Channels 3 : PWMx/3
mimi3 24:3467fafa8a21 230 case PA_2: case PA_10:
mimi3 24:3467fafa8a21 231 case PB_1: case PB_8: case PB_10: case PB_15:
mimi3 24:3467fafa8a21 232 case PC_8:
mimi3 24:3467fafa8a21 233 case PD_14:
mimi3 24:3467fafa8a21 234 case PE_12: case PE_13:
mimi3 24:3467fafa8a21 235 case PH_15:
mimi3 24:3467fafa8a21 236 case PI_7:
mimi3 24:3467fafa8a21 237 return &pwm->CCR3;
mimi3 24:3467fafa8a21 238
mimi3 24:3467fafa8a21 239 // Channels 4 : PWMx/4
mimi3 24:3467fafa8a21 240 case PA_3: case PA_11:
mimi3 24:3467fafa8a21 241 case PB_9: case PB_11:
mimi3 24:3467fafa8a21 242 case PC_9:
mimi3 24:3467fafa8a21 243 case PD_15:
mimi3 24:3467fafa8a21 244 case PE_14:
mimi3 24:3467fafa8a21 245 case PI_2:
mimi3 24:3467fafa8a21 246 return &pwm->CCR4;
mimi3 24:3467fafa8a21 247 default:
mimi3 24:3467fafa8a21 248 /* NOP */
mimi3 24:3467fafa8a21 249 break;
mimi3 24:3467fafa8a21 250 }
mimi3 24:3467fafa8a21 251 return NULL;
mimi3 24:3467fafa8a21 252 }
mimi3 24:3467fafa8a21 253 #endif
mimi3 24:3467fafa8a21 254