cao yang / juli111

cycyy

Dependencies:   MCP23017 WattBob_TextLCD

targets.json@0:a9b4ee4ed395, 2019-05-08 (annotated)

Committer:
mihaidd
Date:
Wed May 08 03:58:47 2019 +0000
Revision:
0:a9b4ee4ed395
ccc

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mihaidd 0:a9b4ee4ed395 1 {
mihaidd 0:a9b4ee4ed395 2 "Target": {
mihaidd 0:a9b4ee4ed395 3 "core": null,
mihaidd 0:a9b4ee4ed395 4 "default_toolchain": "ARM",
mihaidd 0:a9b4ee4ed395 5 "supported_toolchains": null,
mihaidd 0:a9b4ee4ed395 6 "extra_labels": [],
mihaidd 0:a9b4ee4ed395 7 "is_disk_virtual": false,
mihaidd 0:a9b4ee4ed395 8 "macros": [],
mihaidd 0:a9b4ee4ed395 9 "device_has": [],
mihaidd 0:a9b4ee4ed395 10 "features": [],
mihaidd 0:a9b4ee4ed395 11 "detect_code": [],
mihaidd 0:a9b4ee4ed395 12 "public": false,
mihaidd 0:a9b4ee4ed395 13 "default_lib": "std",
mihaidd 0:a9b4ee4ed395 14 "bootloader_supported": false
mihaidd 0:a9b4ee4ed395 15 },
mihaidd 0:a9b4ee4ed395 16 "Super_Target": {
mihaidd 0:a9b4ee4ed395 17 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 18 "core": "Cortex-M4",
mihaidd 0:a9b4ee4ed395 19 "features_add": ["UVISOR", "BLE", "CLIENT", "IPV4", "IPV6"],
mihaidd 0:a9b4ee4ed395 20 "supported_toolchains": ["ARM"]
mihaidd 0:a9b4ee4ed395 21 },
mihaidd 0:a9b4ee4ed395 22 "CM4_UARM": {
mihaidd 0:a9b4ee4ed395 23 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 24 "core": "Cortex-M4",
mihaidd 0:a9b4ee4ed395 25 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 26 "public": false,
mihaidd 0:a9b4ee4ed395 27 "supported_toolchains": ["uARM"],
mihaidd 0:a9b4ee4ed395 28 "default_lib": "small"
mihaidd 0:a9b4ee4ed395 29 },
mihaidd 0:a9b4ee4ed395 30 "CM4_ARM": {
mihaidd 0:a9b4ee4ed395 31 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 32 "core": "Cortex-M4",
mihaidd 0:a9b4ee4ed395 33 "public": false,
mihaidd 0:a9b4ee4ed395 34 "supported_toolchains": ["ARM"]
mihaidd 0:a9b4ee4ed395 35 },
mihaidd 0:a9b4ee4ed395 36 "CM4F_UARM": {
mihaidd 0:a9b4ee4ed395 37 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 38 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 39 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 40 "public": false,
mihaidd 0:a9b4ee4ed395 41 "supported_toolchains": ["uARM"],
mihaidd 0:a9b4ee4ed395 42 "default_lib": "small"
mihaidd 0:a9b4ee4ed395 43 },
mihaidd 0:a9b4ee4ed395 44 "CM4F_ARM": {
mihaidd 0:a9b4ee4ed395 45 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 46 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 47 "public": false,
mihaidd 0:a9b4ee4ed395 48 "supported_toolchains": ["ARM"]
mihaidd 0:a9b4ee4ed395 49 },
mihaidd 0:a9b4ee4ed395 50 "LPCTarget": {
mihaidd 0:a9b4ee4ed395 51 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 52 "post_binary_hook": {"function": "LPCTargetCode.lpc_patch"},
mihaidd 0:a9b4ee4ed395 53 "public": false
mihaidd 0:a9b4ee4ed395 54 },
mihaidd 0:a9b4ee4ed395 55 "LPC11C24": {
mihaidd 0:a9b4ee4ed395 56 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 57 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 58 "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11CXX"],
mihaidd 0:a9b4ee4ed395 59 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 60 "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 61 "device_name": "LPC11C24FBD48/301"
mihaidd 0:a9b4ee4ed395 62 },
mihaidd 0:a9b4ee4ed395 63 "LPC1114": {
mihaidd 0:a9b4ee4ed395 64 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 65 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 66 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 67 "extra_labels": ["NXP", "LPC11XX_11CXX", "LPC11XX"],
mihaidd 0:a9b4ee4ed395 68 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 69 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 70 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 71 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 72 "device_name": "LPC1114FN28/102"
mihaidd 0:a9b4ee4ed395 73 },
mihaidd 0:a9b4ee4ed395 74 "LPC11U24": {
mihaidd 0:a9b4ee4ed395 75 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 76 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 77 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 78 "extra_labels": ["NXP", "LPC11UXX", "LPC11U24_401"],
mihaidd 0:a9b4ee4ed395 79 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 80 "detect_code": ["1040"],
mihaidd 0:a9b4ee4ed395 81 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 82 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 83 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 84 "device_name": "LPC11U24FBD48/401"
mihaidd 0:a9b4ee4ed395 85 },
mihaidd 0:a9b4ee4ed395 86 "OC_MBUINO": {
mihaidd 0:a9b4ee4ed395 87 "inherits": ["LPC11U24"],
mihaidd 0:a9b4ee4ed395 88 "macros": ["TARGET_LPC11U24"],
mihaidd 0:a9b4ee4ed395 89 "extra_labels": ["NXP", "LPC11UXX"],
mihaidd 0:a9b4ee4ed395 90 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 91 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 92 },
mihaidd 0:a9b4ee4ed395 93 "LPC11U24_301": {
mihaidd 0:a9b4ee4ed395 94 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 95 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 96 "extra_labels": ["NXP", "LPC11UXX"],
mihaidd 0:a9b4ee4ed395 97 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 98 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SEMIHOST", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 99 "device_name": "LPC11U24FHI33/301"
mihaidd 0:a9b4ee4ed395 100 },
mihaidd 0:a9b4ee4ed395 101 "LPC11U34_421": {
mihaidd 0:a9b4ee4ed395 102 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 103 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 104 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 105 "extra_labels": ["NXP", "LPC11UXX"],
mihaidd 0:a9b4ee4ed395 106 "supported_toolchains": ["ARM", "uARM", "GCC_ARM"],
mihaidd 0:a9b4ee4ed395 107 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 108 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 109 "device_name": "LPC11U34FBD48/311"
mihaidd 0:a9b4ee4ed395 110 },
mihaidd 0:a9b4ee4ed395 111 "MICRONFCBOARD": {
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mihaidd 0:a9b4ee4ed395 113 "macros": ["LPC11U34_421", "APPNEARME_MICRONFCBOARD"],
mihaidd 0:a9b4ee4ed395 114 "extra_labels_add": ["APPNEARME_MICRONFCBOARD"],
mihaidd 0:a9b4ee4ed395 115 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 116 "device_name": "LPC11U34FBD48/311"
mihaidd 0:a9b4ee4ed395 117 },
mihaidd 0:a9b4ee4ed395 118 "LPC11U35_401": {
mihaidd 0:a9b4ee4ed395 119 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 120 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 121 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 122 "extra_labels": ["NXP", "LPC11UXX"],
mihaidd 0:a9b4ee4ed395 123 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 124 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 125 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 126 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 127 "device_name": "LPC11U35FBD48/401"
mihaidd 0:a9b4ee4ed395 128 },
mihaidd 0:a9b4ee4ed395 129 "LPC11U35_501": {
mihaidd 0:a9b4ee4ed395 130 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 131 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 132 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 133 "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
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mihaidd 0:a9b4ee4ed395 135 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 136 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 137 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 138 "device_name": "LPC11U35FHI33/501"
mihaidd 0:a9b4ee4ed395 139 },
mihaidd 0:a9b4ee4ed395 140 "LPC11U35_501_IBDAP": {
mihaidd 0:a9b4ee4ed395 141 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 142 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 143 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 144 "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
mihaidd 0:a9b4ee4ed395 145 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 146 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 147 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 148 "device_name": "LPC11U35FHI33/501"
mihaidd 0:a9b4ee4ed395 149 },
mihaidd 0:a9b4ee4ed395 150 "XADOW_M0": {
mihaidd 0:a9b4ee4ed395 151 "inherits": ["LPC11U35_501"]
mihaidd 0:a9b4ee4ed395 152 },
mihaidd 0:a9b4ee4ed395 153 "LPC11U35_Y5_MBUG": {
mihaidd 0:a9b4ee4ed395 154 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 155 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 156 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 157 "extra_labels": ["NXP", "LPC11UXX", "MCU_LPC11U35_501"],
mihaidd 0:a9b4ee4ed395 158 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 159 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 160 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 161 "device_name": "LPC11U35FHI33/501"
mihaidd 0:a9b4ee4ed395 162 },
mihaidd 0:a9b4ee4ed395 163 "LPC11U37_501": {
mihaidd 0:a9b4ee4ed395 164 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 165 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 166 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 167 "extra_labels": ["NXP", "LPC11UXX"],
mihaidd 0:a9b4ee4ed395 168 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 169 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 170 "device_name": "LPC11U37FBD64/501"
mihaidd 0:a9b4ee4ed395 171 },
mihaidd 0:a9b4ee4ed395 172 "LPCCAPPUCCINO": {
mihaidd 0:a9b4ee4ed395 173 "inherits": ["LPC11U37_501"],
mihaidd 0:a9b4ee4ed395 174 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 175 "device_name": "LPC11U37FBD64/501"
mihaidd 0:a9b4ee4ed395 176 },
mihaidd 0:a9b4ee4ed395 177 "ARCH_GPRS": {
mihaidd 0:a9b4ee4ed395 178 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 179 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 180 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 181 "extra_labels": ["NXP", "LPC11UXX", "LPC11U37_501"],
mihaidd 0:a9b4ee4ed395 182 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 183 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 184 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 185 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 186 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 187 "device_name": "LPC11U37FBD64/501"
mihaidd 0:a9b4ee4ed395 188 },
mihaidd 0:a9b4ee4ed395 189 "LPC11U68": {
mihaidd 0:a9b4ee4ed395 190 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 191 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 192 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 193 "extra_labels": ["NXP", "LPC11U6X"],
mihaidd 0:a9b4ee4ed395 194 "supported_toolchains": ["ARM", "uARM", "GCC_CR", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 195 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 196 "detect_code": ["1168"],
mihaidd 0:a9b4ee4ed395 197 "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "I2CSLAVE", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI"],
mihaidd 0:a9b4ee4ed395 198 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 199 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 200 "device_name": "LPC11U68JBD100"
mihaidd 0:a9b4ee4ed395 201 },
mihaidd 0:a9b4ee4ed395 202 "LPC1347": {
mihaidd 0:a9b4ee4ed395 203 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 204 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 205 "extra_labels": ["NXP", "LPC13XX"],
mihaidd 0:a9b4ee4ed395 206 "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 207 "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 208 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 209 "device_name": "LPC1347FBD48"
mihaidd 0:a9b4ee4ed395 210 },
mihaidd 0:a9b4ee4ed395 211 "LPC1549": {
mihaidd 0:a9b4ee4ed395 212 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 213 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 214 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 215 "extra_labels": ["NXP", "LPC15XX"],
mihaidd 0:a9b4ee4ed395 216 "supported_toolchains": ["uARM", "GCC_CR", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 217 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 218 "detect_code": ["1549"],
mihaidd 0:a9b4ee4ed395 219 "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "I2C", "INTERRUPTIN", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 220 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 221 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 222 "device_name": "LPC1549JBD64"
mihaidd 0:a9b4ee4ed395 223 },
mihaidd 0:a9b4ee4ed395 224 "LPC1768": {
mihaidd 0:a9b4ee4ed395 225 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 226 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 227 "extra_labels": ["NXP", "LPC176X", "MBED_LPC1768"],
mihaidd 0:a9b4ee4ed395 228 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 229 "detect_code": ["1010"],
mihaidd 0:a9b4ee4ed395 230 "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "LOCALFILESYSTEM", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SEMIHOST", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 231 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 232 "features": ["LWIP"],
mihaidd 0:a9b4ee4ed395 233 "device_name": "LPC1768"
mihaidd 0:a9b4ee4ed395 234 },
mihaidd 0:a9b4ee4ed395 235 "ARCH_PRO": {
mihaidd 0:a9b4ee4ed395 236 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 237 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 238 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 239 "extra_labels": ["NXP", "LPC176X"],
mihaidd 0:a9b4ee4ed395 240 "macros": ["TARGET_LPC1768"],
mihaidd 0:a9b4ee4ed395 241 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 242 "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 243 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 244 "features": ["LWIP"],
mihaidd 0:a9b4ee4ed395 245 "device_name": "LPC1768"
mihaidd 0:a9b4ee4ed395 246 },
mihaidd 0:a9b4ee4ed395 247 "UBLOX_C027": {
mihaidd 0:a9b4ee4ed395 248 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 249 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 250 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "GCC_CR", "IAR"],
mihaidd 0:a9b4ee4ed395 251 "extra_labels": ["NXP", "LPC176X"],
mihaidd 0:a9b4ee4ed395 252 "macros": ["TARGET_LPC1768"],
mihaidd 0:a9b4ee4ed395 253 "inherits": ["LPCTarget"],
mihaidd 0:a9b4ee4ed395 254 "device_has": ["ANALOGIN", "ANALOGOUT", "CAN", "DEBUG_AWARENESS", "ERROR_RED", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 255 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 256 "features": ["LWIP"],
mihaidd 0:a9b4ee4ed395 257 "device_name": "LPC1768"
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mihaidd 0:a9b4ee4ed395 1398 "name": "s110_nrf51822_6.0.0_softdevice.hex",
mihaidd 0:a9b4ee4ed395 1399 "offset": 81920
mihaidd 0:a9b4ee4ed395 1400 }
mihaidd 0:a9b4ee4ed395 1401 ],
mihaidd 0:a9b4ee4ed395 1402 "detect_code": ["1070"],
mihaidd 0:a9b4ee4ed395 1403 "post_binary_hook": {
mihaidd 0:a9b4ee4ed395 1404 "function": "MCU_NRF51Code.binary_hook",
mihaidd 0:a9b4ee4ed395 1405 "toolchains": ["ARM_STD", "GCC_ARM"]
mihaidd 0:a9b4ee4ed395 1406 },
mihaidd 0:a9b4ee4ed395 1407 "program_cycle_s": 6,
mihaidd 0:a9b4ee4ed395 1408 "features": ["BLE"],
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mihaidd 0:a9b4ee4ed395 1410 },
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mihaidd 0:a9b4ee4ed395 1415 "public": false,
mihaidd 0:a9b4ee4ed395 1416 "default_lib": "small"
mihaidd 0:a9b4ee4ed395 1417 },
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mihaidd 0:a9b4ee4ed395 1430 "MERGE_SOFT_DEVICE": false
mihaidd 0:a9b4ee4ed395 1431 },
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mihaidd 0:a9b4ee4ed395 1434 "extra_labels_add": ["MCU_NRF51_16K_S130"],
mihaidd 0:a9b4ee4ed395 1435 "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
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mihaidd 0:a9b4ee4ed395 1437 },
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mihaidd 0:a9b4ee4ed395 1440 "macros_add": ["TARGET_MCU_NRF51_16K_S110"],
mihaidd 0:a9b4ee4ed395 1441 "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
mihaidd 0:a9b4ee4ed395 1442 {
mihaidd 0:a9b4ee4ed395 1443 "name": "s110_nrf51822_8.0.0_softdevice.hex",
mihaidd 0:a9b4ee4ed395 1444 "boot": "s110_nrf51822_8.0.0_bootloader.hex",
mihaidd 0:a9b4ee4ed395 1445 "offset": 98304
mihaidd 0:a9b4ee4ed395 1446 },
mihaidd 0:a9b4ee4ed395 1447 {
mihaidd 0:a9b4ee4ed395 1448 "name": "s110_nrf51822_7.1.0_softdevice.hex",
mihaidd 0:a9b4ee4ed395 1449 "boot": "s110_nrf51822_7.1.0_bootloader.hex",
mihaidd 0:a9b4ee4ed395 1450 "offset": 90112
mihaidd 0:a9b4ee4ed395 1451 }
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mihaidd 0:a9b4ee4ed395 1453 "public": false
mihaidd 0:a9b4ee4ed395 1454 },
mihaidd 0:a9b4ee4ed395 1455 "MCU_NRF51_16K_S110": {
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mihaidd 0:a9b4ee4ed395 1457 "public": false
mihaidd 0:a9b4ee4ed395 1458 },
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mihaidd 0:a9b4ee4ed395 1464 },
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mihaidd 0:a9b4ee4ed395 1472 "macros_add": ["TARGET_MCU_NRF51_16K_S130"],
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mihaidd 0:a9b4ee4ed395 1474 },
mihaidd 0:a9b4ee4ed395 1475 "MCU_NRF51_16K_OTA_S110": {
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mihaidd 0:a9b4ee4ed395 1477 "public": false
mihaidd 0:a9b4ee4ed395 1478 },
mihaidd 0:a9b4ee4ed395 1479 "MCU_NRF51_32K": {
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mihaidd 0:a9b4ee4ed395 1481 "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
mihaidd 0:a9b4ee4ed395 1482 "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
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mihaidd 0:a9b4ee4ed395 1485 "MCU_NRF51_32K_BOOT": {
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mihaidd 0:a9b4ee4ed395 1487 "MERGE_BOOTLOADER": true,
mihaidd 0:a9b4ee4ed395 1488 "extra_labels_add": ["MCU_NRF51_32K_BOOT"],
mihaidd 0:a9b4ee4ed395 1489 "macros_add": ["TARGET_MCU_NRF51_32K_BOOT", "TARGET_OTA_ENABLED"],
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mihaidd 0:a9b4ee4ed395 1491 },
mihaidd 0:a9b4ee4ed395 1492 "MCU_NRF51_32K_OTA": {
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mihaidd 0:a9b4ee4ed395 1497 "MERGE_SOFT_DEVICE": false
mihaidd 0:a9b4ee4ed395 1498 },
mihaidd 0:a9b4ee4ed395 1499 "NRF51822": {
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mihaidd 0:a9b4ee4ed395 1501 "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
mihaidd 0:a9b4ee4ed395 1502 "macros_add": ["TARGET_NRF51822_MKIT"],
mihaidd 0:a9b4ee4ed395 1503 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1504 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1505 },
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mihaidd 0:a9b4ee4ed395 1508 "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
mihaidd 0:a9b4ee4ed395 1509 "macros_add": ["TARGET_NRF51822_MKIT"]
mihaidd 0:a9b4ee4ed395 1510 },
mihaidd 0:a9b4ee4ed395 1511 "NRF51822_OTA": {
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mihaidd 0:a9b4ee4ed395 1513 "extra_labels_add": ["NRF51822", "NRF51822_MKIT"],
mihaidd 0:a9b4ee4ed395 1514 "macros_add": ["TARGET_NRF51822_MKIT"]
mihaidd 0:a9b4ee4ed395 1515 },
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mihaidd 0:a9b4ee4ed395 1519 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1520 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1521 },
mihaidd 0:a9b4ee4ed395 1522 "ARCH_BLE_BOOT": {
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mihaidd 0:a9b4ee4ed395 1528 "ARCH_BLE_OTA": {
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mihaidd 0:a9b4ee4ed395 1531 "extra_labels_add": ["ARCH_BLE"],
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mihaidd 0:a9b4ee4ed395 1533 },
mihaidd 0:a9b4ee4ed395 1534 "ARCH_LINK": {
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mihaidd 0:a9b4ee4ed395 1537 "extra_labels_add": ["ARCH_BLE"],
mihaidd 0:a9b4ee4ed395 1538 "macros_add": ["TARGET_ARCH_BLE"]
mihaidd 0:a9b4ee4ed395 1539 },
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mihaidd 0:a9b4ee4ed395 1542 "inherits": ["MCU_NRF51_16K_BOOT"],
mihaidd 0:a9b4ee4ed395 1543 "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
mihaidd 0:a9b4ee4ed395 1544 "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
mihaidd 0:a9b4ee4ed395 1545 },
mihaidd 0:a9b4ee4ed395 1546 "ARCH_LINK_OTA": {
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mihaidd 0:a9b4ee4ed395 1548 "inherits": ["MCU_NRF51_16K_OTA"],
mihaidd 0:a9b4ee4ed395 1549 "extra_labels_add": ["ARCH_BLE", "ARCH_LINK"],
mihaidd 0:a9b4ee4ed395 1550 "macros_add": ["TARGET_ARCH_BLE", "TARGET_ARCH_LINK"]
mihaidd 0:a9b4ee4ed395 1551 },
mihaidd 0:a9b4ee4ed395 1552 "SEEED_TINY_BLE": {
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mihaidd 0:a9b4ee4ed395 1554 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1555 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1556 },
mihaidd 0:a9b4ee4ed395 1557 "SEEED_TINY_BLE_BOOT": {
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mihaidd 0:a9b4ee4ed395 1560 "macros_add": ["TARGET_SEEED_TINY_BLE"]
mihaidd 0:a9b4ee4ed395 1561 },
mihaidd 0:a9b4ee4ed395 1562 "SEEED_TINY_BLE_OTA": {
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mihaidd 0:a9b4ee4ed395 1564 "extra_labels_add": ["SEEED_TINY_BLE"],
mihaidd 0:a9b4ee4ed395 1565 "macros_add": ["TARGET_SEEED_TINY_BLE"]
mihaidd 0:a9b4ee4ed395 1566 },
mihaidd 0:a9b4ee4ed395 1567 "HRM1017": {
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mihaidd 0:a9b4ee4ed395 1569 "macros_add": ["TARGET_NRF_LFCLK_RC"],
mihaidd 0:a9b4ee4ed395 1570 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1571 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1572 },
mihaidd 0:a9b4ee4ed395 1573 "HRM1017_BOOT": {
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mihaidd 0:a9b4ee4ed395 1575 "extra_labels_add": ["HRM1017"],
mihaidd 0:a9b4ee4ed395 1576 "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1577 },
mihaidd 0:a9b4ee4ed395 1578 "HRM1017_OTA": {
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mihaidd 0:a9b4ee4ed395 1580 "extra_labels_add": ["HRM1017"],
mihaidd 0:a9b4ee4ed395 1581 "macros_add": ["TARGET_HRM1017", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1582 },
mihaidd 0:a9b4ee4ed395 1583 "RBLAB_NRF51822": {
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mihaidd 0:a9b4ee4ed395 1586 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1587 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1588 },
mihaidd 0:a9b4ee4ed395 1589 "RBLAB_NRF51822_BOOT": {
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mihaidd 0:a9b4ee4ed395 1591 "inherits": ["MCU_NRF51_16K_BOOT"],
mihaidd 0:a9b4ee4ed395 1592 "extra_labels_add": ["RBLAB_NRF51822"],
mihaidd 0:a9b4ee4ed395 1593 "macros_add": ["TARGET_RBLAB_NRF51822"]
mihaidd 0:a9b4ee4ed395 1594 },
mihaidd 0:a9b4ee4ed395 1595 "RBLAB_NRF51822_OTA": {
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mihaidd 0:a9b4ee4ed395 1597 "inherits": ["MCU_NRF51_16K_OTA"],
mihaidd 0:a9b4ee4ed395 1598 "extra_labels_add": ["RBLAB_NRF51822"],
mihaidd 0:a9b4ee4ed395 1599 "macros_add": ["TARGET_RBLAB_NRF51822"]
mihaidd 0:a9b4ee4ed395 1600 },
mihaidd 0:a9b4ee4ed395 1601 "RBLAB_BLENANO": {
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mihaidd 0:a9b4ee4ed395 1603 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 1604 },
mihaidd 0:a9b4ee4ed395 1605 "RBLAB_BLENANO_BOOT": {
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mihaidd 0:a9b4ee4ed395 1607 "extra_labels_add": ["RBLAB_BLENANO"],
mihaidd 0:a9b4ee4ed395 1608 "macros_add": ["TARGET_RBLAB_BLENANO"]
mihaidd 0:a9b4ee4ed395 1609 },
mihaidd 0:a9b4ee4ed395 1610 "RBLAB_BLENANO_OTA": {
mihaidd 0:a9b4ee4ed395 1611 "inherits": ["MCU_NRF51_16K_OTA"],
mihaidd 0:a9b4ee4ed395 1612 "extra_labels_add": ["RBLAB_BLENANO"],
mihaidd 0:a9b4ee4ed395 1613 "macros_add": ["TARGET_RBLAB_BLENANO"]
mihaidd 0:a9b4ee4ed395 1614 },
mihaidd 0:a9b4ee4ed395 1615 "NRF51822_Y5_MBUG": {
mihaidd 0:a9b4ee4ed395 1616 "inherits": ["MCU_NRF51_16K"]
mihaidd 0:a9b4ee4ed395 1617 },
mihaidd 0:a9b4ee4ed395 1618 "WALLBOT_BLE": {
mihaidd 0:a9b4ee4ed395 1619 "inherits": ["MCU_NRF51_16K"],
mihaidd 0:a9b4ee4ed395 1620 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 1621 },
mihaidd 0:a9b4ee4ed395 1622 "WALLBOT_BLE_BOOT": {
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mihaidd 0:a9b4ee4ed395 1624 "extra_labels_add": ["WALLBOT_BLE"],
mihaidd 0:a9b4ee4ed395 1625 "macros_add": ["TARGET_WALLBOT_BLE"]
mihaidd 0:a9b4ee4ed395 1626 },
mihaidd 0:a9b4ee4ed395 1627 "WALLBOT_BLE_OTA": {
mihaidd 0:a9b4ee4ed395 1628 "inherits": ["MCU_NRF51_16K_OTA"],
mihaidd 0:a9b4ee4ed395 1629 "extra_labels_add": ["WALLBOT_BLE"],
mihaidd 0:a9b4ee4ed395 1630 "macros_add": ["TARGET_WALLBOT_BLE"]
mihaidd 0:a9b4ee4ed395 1631 },
mihaidd 0:a9b4ee4ed395 1632 "DELTA_DFCM_NNN40": {
mihaidd 0:a9b4ee4ed395 1633 "inherits": ["MCU_NRF51_32K"],
mihaidd 0:a9b4ee4ed395 1634 "program_cycle_s": 10,
mihaidd 0:a9b4ee4ed395 1635 "macros_add": ["TARGET_NRF_LFCLK_RC"],
mihaidd 0:a9b4ee4ed395 1636 "device_has": ["ANALOGIN", "DEBUG_AWARENESS", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 1637 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1638 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1639 },
mihaidd 0:a9b4ee4ed395 1640 "DELTA_DFCM_NNN40_BOOT": {
mihaidd 0:a9b4ee4ed395 1641 "inherits": ["MCU_NRF51_32K_BOOT"],
mihaidd 0:a9b4ee4ed395 1642 "program_cycle_s": 10,
mihaidd 0:a9b4ee4ed395 1643 "extra_labels_add": ["DELTA_DFCM_NNN40"],
mihaidd 0:a9b4ee4ed395 1644 "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1645 },
mihaidd 0:a9b4ee4ed395 1646 "DELTA_DFCM_NNN40_OTA": {
mihaidd 0:a9b4ee4ed395 1647 "inherits": ["MCU_NRF51_32K_OTA"],
mihaidd 0:a9b4ee4ed395 1648 "program_cycle_s": 10,
mihaidd 0:a9b4ee4ed395 1649 "extra_labels_add": ["DELTA_DFCM_NNN40"],
mihaidd 0:a9b4ee4ed395 1650 "macros_add": ["TARGET_DELTA_DFCM_NNN40", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1651 },
mihaidd 0:a9b4ee4ed395 1652 "DELTA_DFCM_NNN50": {
mihaidd 0:a9b4ee4ed395 1653 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 1654 "inherits": ["MCU_NRF51_32K_UNIFIED"],
mihaidd 0:a9b4ee4ed395 1655 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 1656 "device_name": "nRF51822_xxAC"
mihaidd 0:a9b4ee4ed395 1657 },
mihaidd 0:a9b4ee4ed395 1658 "DELTA_DFCM_NNN50_BOOT": {
mihaidd 0:a9b4ee4ed395 1659 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 1660 "inherits": ["MCU_NRF51_32K_BOOT"],
mihaidd 0:a9b4ee4ed395 1661 "extra_labels_add": ["DELTA_DFCM_NNN50"],
mihaidd 0:a9b4ee4ed395 1662 "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
mihaidd 0:a9b4ee4ed395 1663 },
mihaidd 0:a9b4ee4ed395 1664 "DELTA_DFCM_NNN50_OTA": {
mihaidd 0:a9b4ee4ed395 1665 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 1666 "inherits": ["MCU_NRF51_32K_OTA"],
mihaidd 0:a9b4ee4ed395 1667 "extra_labels_add": ["DELTA_DFCM_NNN50"],
mihaidd 0:a9b4ee4ed395 1668 "macros_add": ["TARGET_DELTA_DFCM_NNN50"]
mihaidd 0:a9b4ee4ed395 1669 },
mihaidd 0:a9b4ee4ed395 1670 "NRF51_DK_LEGACY": {
mihaidd 0:a9b4ee4ed395 1671 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 1672 "inherits": ["MCU_NRF51_32K"],
mihaidd 0:a9b4ee4ed395 1673 "extra_labels_add": ["NRF51_DK"]
mihaidd 0:a9b4ee4ed395 1674 },
mihaidd 0:a9b4ee4ed395 1675 "NRF51_DK_BOOT": {
mihaidd 0:a9b4ee4ed395 1676 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 1677 "inherits": ["MCU_NRF51_32K_BOOT"],
mihaidd 0:a9b4ee4ed395 1678 "extra_labels_add": ["NRF51_DK"],
mihaidd 0:a9b4ee4ed395 1679 "macros_add": ["TARGET_NRF51_DK"]
mihaidd 0:a9b4ee4ed395 1680 },
mihaidd 0:a9b4ee4ed395 1681 "NRF51_DK_OTA": {
mihaidd 0:a9b4ee4ed395 1682 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 1683 "inherits": ["MCU_NRF51_32K_OTA"],
mihaidd 0:a9b4ee4ed395 1684 "extra_labels_add": ["NRF51_DK"],
mihaidd 0:a9b4ee4ed395 1685 "macros_add": ["TARGET_NRF51_DK"]
mihaidd 0:a9b4ee4ed395 1686 },
mihaidd 0:a9b4ee4ed395 1687 "NRF51_DONGLE_LEGACY": {
mihaidd 0:a9b4ee4ed395 1688 "inherits": ["MCU_NRF51_32K"],
mihaidd 0:a9b4ee4ed395 1689 "extra_labels_add": ["NRF51_DONGLE"],
mihaidd 0:a9b4ee4ed395 1690 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1691 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1692 },
mihaidd 0:a9b4ee4ed395 1693 "NRF51_DONGLE_BOOT": {
mihaidd 0:a9b4ee4ed395 1694 "inherits": ["MCU_NRF51_32K_BOOT"],
mihaidd 0:a9b4ee4ed395 1695 "extra_labels_add": ["NRF51_DONGLE"],
mihaidd 0:a9b4ee4ed395 1696 "macros_add": ["TARGET_NRF51_DONGLE"]
mihaidd 0:a9b4ee4ed395 1697 },
mihaidd 0:a9b4ee4ed395 1698 "NRF51_DONGLE_OTA": {
mihaidd 0:a9b4ee4ed395 1699 "inherits": ["MCU_NRF51_32K_OTA"],
mihaidd 0:a9b4ee4ed395 1700 "extra_labels_add": ["NRF51_DONGLE"],
mihaidd 0:a9b4ee4ed395 1701 "macros_add": ["TARGET_NRF51_DONGLE"]
mihaidd 0:a9b4ee4ed395 1702 },
mihaidd 0:a9b4ee4ed395 1703 "NRF51_MICROBIT": {
mihaidd 0:a9b4ee4ed395 1704 "inherits": ["MCU_NRF51_16K_S110"],
mihaidd 0:a9b4ee4ed395 1705 "macros_add": ["TARGET_NRF_LFCLK_RC"],
mihaidd 0:a9b4ee4ed395 1706 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1707 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1708 },
mihaidd 0:a9b4ee4ed395 1709 "NRF51_MICROBIT_BOOT": {
mihaidd 0:a9b4ee4ed395 1710 "inherits": ["MCU_NRF51_16K_BOOT_S110"],
mihaidd 0:a9b4ee4ed395 1711 "extra_labels_add": ["NRF51_MICROBIT"],
mihaidd 0:a9b4ee4ed395 1712 "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1713 },
mihaidd 0:a9b4ee4ed395 1714 "NRF51_MICROBIT_OTA": {
mihaidd 0:a9b4ee4ed395 1715 "inherits": ["MCU_NRF51_16K_OTA_S110"],
mihaidd 0:a9b4ee4ed395 1716 "extra_labels_add": ["NRF51_MICROBIT"],
mihaidd 0:a9b4ee4ed395 1717 "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1718 },
mihaidd 0:a9b4ee4ed395 1719 "NRF51_MICROBIT_B": {
mihaidd 0:a9b4ee4ed395 1720 "inherits": ["MCU_NRF51_16K"],
mihaidd 0:a9b4ee4ed395 1721 "extra_labels_add": ["NRF51_MICROBIT"],
mihaidd 0:a9b4ee4ed395 1722 "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"],
mihaidd 0:a9b4ee4ed395 1723 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 1724 },
mihaidd 0:a9b4ee4ed395 1725 "NRF51_MICROBIT_B_BOOT": {
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mihaidd 0:a9b4ee4ed395 1727 "extra_labels_add": ["NRF51_MICROBIT"],
mihaidd 0:a9b4ee4ed395 1728 "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1729 },
mihaidd 0:a9b4ee4ed395 1730 "NRF51_MICROBIT_B_OTA": {
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mihaidd 0:a9b4ee4ed395 1732 "extra_labels_add": ["NRF51_MICROBIT"],
mihaidd 0:a9b4ee4ed395 1733 "macros_add": ["TARGET_NRF51_MICROBIT", "TARGET_NRF_LFCLK_RC"]
mihaidd 0:a9b4ee4ed395 1734 },
mihaidd 0:a9b4ee4ed395 1735 "MTM_MTCONNECT04S": {
mihaidd 0:a9b4ee4ed395 1736 "inherits": ["MCU_NRF51_32K"],
mihaidd 0:a9b4ee4ed395 1737 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 1738 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1739 },
mihaidd 0:a9b4ee4ed395 1740 "MTM_MTCONNECT04S_BOOT": {
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mihaidd 0:a9b4ee4ed395 1742 "extra_labels_add": ["MTM_CONNECT04S"],
mihaidd 0:a9b4ee4ed395 1743 "macros_add": ["TARGET_MTM_CONNECT04S"]
mihaidd 0:a9b4ee4ed395 1744 },
mihaidd 0:a9b4ee4ed395 1745 "MTM_MTCONNECT04S_OTA": {
mihaidd 0:a9b4ee4ed395 1746 "inherits": ["MCU_NRF51_32K_OTA"],
mihaidd 0:a9b4ee4ed395 1747 "extra_labels_add": ["MTM_CONNECT04S"],
mihaidd 0:a9b4ee4ed395 1748 "macros_add": ["TARGET_MTM_CONNECT04S"]
mihaidd 0:a9b4ee4ed395 1749 },
mihaidd 0:a9b4ee4ed395 1750 "TY51822R3": {
mihaidd 0:a9b4ee4ed395 1751 "inherits": ["MCU_NRF51_32K_UNIFIED"],
mihaidd 0:a9b4ee4ed395 1752 "macros_add": ["TARGET_NRF_32MHZ_XTAL"],
mihaidd 0:a9b4ee4ed395 1753 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 1754 "detect_code": ["1019"],
mihaidd 0:a9b4ee4ed395 1755 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 1756 "overrides": {"uart_hwfc": 0},
mihaidd 0:a9b4ee4ed395 1757 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 1758 },
mihaidd 0:a9b4ee4ed395 1759 "TY51822R3_BOOT": {
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mihaidd 0:a9b4ee4ed395 1761 "extra_labels_add": ["TY51822R3"],
mihaidd 0:a9b4ee4ed395 1762 "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
mihaidd 0:a9b4ee4ed395 1763 },
mihaidd 0:a9b4ee4ed395 1764 "TY51822R3_OTA": {
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mihaidd 0:a9b4ee4ed395 1766 "extra_labels_add": ["NRF51_DK"],
mihaidd 0:a9b4ee4ed395 1767 "macros_add": ["TARGET_TY51822R3", "TARGET_NRF_32MHZ_XTAL"]
mihaidd 0:a9b4ee4ed395 1768 },
mihaidd 0:a9b4ee4ed395 1769 "ARM_MPS2_Target": {
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mihaidd 0:a9b4ee4ed395 1771 "public": false,
mihaidd 0:a9b4ee4ed395 1772 "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
mihaidd 0:a9b4ee4ed395 1773 },
mihaidd 0:a9b4ee4ed395 1774 "ARM_MPS2_M0": {
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mihaidd 0:a9b4ee4ed395 1776 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 1777 "supported_toolchains": ["ARM"],
mihaidd 0:a9b4ee4ed395 1778 "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M0"],
mihaidd 0:a9b4ee4ed395 1779 "macros": ["CMSDK_CM0"],
mihaidd 0:a9b4ee4ed395 1780 "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
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mihaidd 0:a9b4ee4ed395 1782 },
mihaidd 0:a9b4ee4ed395 1783 "ARM_MPS2_M0P": {
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mihaidd 0:a9b4ee4ed395 1785 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 1786 "supported_toolchains": ["ARM"],
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mihaidd 0:a9b4ee4ed395 1788 "macros": ["CMSDK_CM0plus"],
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mihaidd 0:a9b4ee4ed395 1790 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 1791 },
mihaidd 0:a9b4ee4ed395 1792 "ARM_MPS2_M1": {
mihaidd 0:a9b4ee4ed395 1793 "inherits": ["ARM_MPS2_Target"],
mihaidd 0:a9b4ee4ed395 1794 "core": "Cortex-M1",
mihaidd 0:a9b4ee4ed395 1795 "supported_toolchains": ["ARM"],
mihaidd 0:a9b4ee4ed395 1796 "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M1"],
mihaidd 0:a9b4ee4ed395 1797 "macros": ["CMSDK_CM1"],
mihaidd 0:a9b4ee4ed395 1798 "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
mihaidd 0:a9b4ee4ed395 1799 },
mihaidd 0:a9b4ee4ed395 1800 "ARM_MPS2_M3": {
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mihaidd 0:a9b4ee4ed395 1802 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 1803 "supported_toolchains": ["ARM"],
mihaidd 0:a9b4ee4ed395 1804 "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M3"],
mihaidd 0:a9b4ee4ed395 1805 "macros": ["CMSDK_CM3"],
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mihaidd 0:a9b4ee4ed395 1808 },
mihaidd 0:a9b4ee4ed395 1809 "ARM_MPS2_M4": {
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mihaidd 0:a9b4ee4ed395 1811 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 1812 "supported_toolchains": ["ARM"],
mihaidd 0:a9b4ee4ed395 1813 "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M4"],
mihaidd 0:a9b4ee4ed395 1814 "macros": ["CMSDK_CM4"],
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mihaidd 0:a9b4ee4ed395 1816 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 1817 },
mihaidd 0:a9b4ee4ed395 1818 "ARM_MPS2_M7": {
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mihaidd 0:a9b4ee4ed395 1820 "core": "Cortex-M7",
mihaidd 0:a9b4ee4ed395 1821 "supported_toolchains": ["ARM"],
mihaidd 0:a9b4ee4ed395 1822 "extra_labels": ["ARM_SSG", "MPS2", "MPS2_M7"],
mihaidd 0:a9b4ee4ed395 1823 "macros": ["CMSDK_CM7"],
mihaidd 0:a9b4ee4ed395 1824 "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
mihaidd 0:a9b4ee4ed395 1825 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 1826 },
mihaidd 0:a9b4ee4ed395 1827 "ARM_IOTSS_Target": {
mihaidd 0:a9b4ee4ed395 1828 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1829 "public": false,
mihaidd 0:a9b4ee4ed395 1830 "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"]
mihaidd 0:a9b4ee4ed395 1831 },
mihaidd 0:a9b4ee4ed395 1832 "ARM_IOTSS_BEID": {
mihaidd 0:a9b4ee4ed395 1833 "inherits": ["ARM_IOTSS_Target"],
mihaidd 0:a9b4ee4ed395 1834 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 1835 "supported_toolchains": ["ARM"],
mihaidd 0:a9b4ee4ed395 1836 "extra_labels": ["ARM_SSG", "IOTSS", "IOTSS_BEID"],
mihaidd 0:a9b4ee4ed395 1837 "macros": ["CMSDK_BEID"],
mihaidd 0:a9b4ee4ed395 1838 "device_has": ["AACI", "ANALOGIN", "CLCD", "ETHERNET", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "TSC"],
mihaidd 0:a9b4ee4ed395 1839 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 1840 },
mihaidd 0:a9b4ee4ed395 1841 "ARM_BEETLE_SOC": {
mihaidd 0:a9b4ee4ed395 1842 "inherits": ["ARM_IOTSS_Target"],
mihaidd 0:a9b4ee4ed395 1843 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 1844 "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 1845 "default_toolchain": "ARM",
mihaidd 0:a9b4ee4ed395 1846 "extra_labels": ["ARM_SSG", "BEETLE"],
mihaidd 0:a9b4ee4ed395 1847 "macros": ["CMSDK_BEETLE", "WSF_MS_PER_TICK=20", "WSF_TOKEN_ENABLED=FALSE", "WSF_TRACE_ENABLED=TRUE", "WSF_ASSERT_ENABLED=FALSE", "WSF_PRINTF_MAX_LEN=128", "ASIC", "CONFIG_HOST_REV=0x20", "CONFIG_ALLOW_DEEP_SLEEP=FALSE", "HCI_VS_TARGET", "CONFIG_ALLOW_SETTING_WRITE=TRUE", "WSF_MAX_HANDLERS=20", "NO_LEDS"],
mihaidd 0:a9b4ee4ed395 1848 "device_has": ["ANALOGIN", "CLCD", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "SPI"],
mihaidd 0:a9b4ee4ed395 1849 "features": ["BLE"],
mihaidd 0:a9b4ee4ed395 1850 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1851 },
mihaidd 0:a9b4ee4ed395 1852 "RZ_A1H": {
mihaidd 0:a9b4ee4ed395 1853 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 1854 "core": "Cortex-A9",
mihaidd 0:a9b4ee4ed395 1855 "program_cycle_s": 2,
mihaidd 0:a9b4ee4ed395 1856 "extra_labels": ["RENESAS", "MBRZA1H"],
mihaidd 0:a9b4ee4ed395 1857 "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 1858 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1859 "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1860 "features": ["LWIP"],
mihaidd 0:a9b4ee4ed395 1861 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1862 },
mihaidd 0:a9b4ee4ed395 1863 "VK_RZ_A1H": {
mihaidd 0:a9b4ee4ed395 1864 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1865 "core": "Cortex-A9",
mihaidd 0:a9b4ee4ed395 1866 "extra_labels": ["RENESAS", "VKRZA1H"],
mihaidd 0:a9b4ee4ed395 1867 "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 1868 "default_toolchain": "ARM",
mihaidd 0:a9b4ee4ed395 1869 "program_cycle_s": 2,
mihaidd 0:a9b4ee4ed395 1870 "device_has": ["ANALOGIN", "CAN", "ERROR_PATTERN", "ETHERNET", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1871 "features": ["LWIP"],
mihaidd 0:a9b4ee4ed395 1872 "default_lib": "std",
mihaidd 0:a9b4ee4ed395 1873 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1874 },
mihaidd 0:a9b4ee4ed395 1875 "MAXWSNENV": {
mihaidd 0:a9b4ee4ed395 1876 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1877 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 1878 "macros": ["__SYSTEM_HFX=24000000"],
mihaidd 0:a9b4ee4ed395 1879 "extra_labels": ["Maxim", "MAX32610"],
mihaidd 0:a9b4ee4ed395 1880 "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
mihaidd 0:a9b4ee4ed395 1881 "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1882 "features": ["BLE"],
mihaidd 0:a9b4ee4ed395 1883 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1884 },
mihaidd 0:a9b4ee4ed395 1885 "MAX32600MBED": {
mihaidd 0:a9b4ee4ed395 1886 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1887 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 1888 "macros": ["__SYSTEM_HFX=24000000"],
mihaidd 0:a9b4ee4ed395 1889 "extra_labels": ["Maxim", "MAX32600"],
mihaidd 0:a9b4ee4ed395 1890 "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
mihaidd 0:a9b4ee4ed395 1891 "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1892 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1893 },
mihaidd 0:a9b4ee4ed395 1894 "MAX32620HSP": {
mihaidd 0:a9b4ee4ed395 1895 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1896 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 1897 "extra_labels": ["Maxim", "MAX32620"],
mihaidd 0:a9b4ee4ed395 1898 "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
mihaidd 0:a9b4ee4ed395 1899 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1900 "features": ["BLE"],
mihaidd 0:a9b4ee4ed395 1901 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1902 },
mihaidd 0:a9b4ee4ed395 1903 "MAX32625MBED": {
mihaidd 0:a9b4ee4ed395 1904 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1905 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 1906 "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
mihaidd 0:a9b4ee4ed395 1907 "extra_labels": ["Maxim", "MAX32625"],
mihaidd 0:a9b4ee4ed395 1908 "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
mihaidd 0:a9b4ee4ed395 1909 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1910 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1911 },
mihaidd 0:a9b4ee4ed395 1912 "MAX32625NEXPAQ": {
mihaidd 0:a9b4ee4ed395 1913 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1914 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 1915 "macros": ["__SYSTEM_HFX=96000000","TARGET=MAX32625","TARGET_REV=0x4132"],
mihaidd 0:a9b4ee4ed395 1916 "extra_labels": ["Maxim", "MAX32625"],
mihaidd 0:a9b4ee4ed395 1917 "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
mihaidd 0:a9b4ee4ed395 1918 "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1919 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1920 },
mihaidd 0:a9b4ee4ed395 1921 "MAX32630FTHR": {
mihaidd 0:a9b4ee4ed395 1922 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1923 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 1924 "macros": ["__SYSTEM_HFX=96000000", "TARGET=MAX32630", "TARGET_REV=0x4132"],
mihaidd 0:a9b4ee4ed395 1925 "extra_labels": ["Maxim", "MAX32630"],
mihaidd 0:a9b4ee4ed395 1926 "supported_toolchains": ["GCC_ARM", "IAR", "ARM"],
mihaidd 0:a9b4ee4ed395 1927 "device_has": ["ANALOGIN", "ERROR_RED", "I2C", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1928 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 1929 },
mihaidd 0:a9b4ee4ed395 1930 "EFM32": {
mihaidd 0:a9b4ee4ed395 1931 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 1932 "extra_labels": ["Silicon_Labs", "EFM32"],
mihaidd 0:a9b4ee4ed395 1933 "public": false
mihaidd 0:a9b4ee4ed395 1934 },
mihaidd 0:a9b4ee4ed395 1935 "EFM32GG990F1024": {
mihaidd 0:a9b4ee4ed395 1936 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 1937 "extra_labels_add": ["EFM32GG", "1024K", "SL_AES"],
mihaidd 0:a9b4ee4ed395 1938 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 1939 "macros": ["EFM32GG990F1024", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 1940 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 1941 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 1942 "device_name": "EFM32GG990F1024",
mihaidd 0:a9b4ee4ed395 1943 "public": false
mihaidd 0:a9b4ee4ed395 1944 },
mihaidd 0:a9b4ee4ed395 1945 "EFM32GG_STK3700": {
mihaidd 0:a9b4ee4ed395 1946 "inherits": ["EFM32GG990F1024"],
mihaidd 0:a9b4ee4ed395 1947 "progen": {"target": "efm32gg-stk"},
mihaidd 0:a9b4ee4ed395 1948 "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 1949 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 1950 "config": {
mihaidd 0:a9b4ee4ed395 1951 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 1952 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 1953 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 1954 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 1955 },
mihaidd 0:a9b4ee4ed395 1956 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 1957 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 1958 "value": "48000000",
mihaidd 0:a9b4ee4ed395 1959 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 1960 },
mihaidd 0:a9b4ee4ed395 1961 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 1962 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 1963 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 1964 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 1965 },
mihaidd 0:a9b4ee4ed395 1966 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 1967 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 1968 "value": "32768",
mihaidd 0:a9b4ee4ed395 1969 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 1970 },
mihaidd 0:a9b4ee4ed395 1971 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 1972 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 1973 "value": "21000000",
mihaidd 0:a9b4ee4ed395 1974 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 1975 },
mihaidd 0:a9b4ee4ed395 1976 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 1977 "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 1978 "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
mihaidd 0:a9b4ee4ed395 1979 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 1980 },
mihaidd 0:a9b4ee4ed395 1981 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 1982 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 1983 "value": "PF7",
mihaidd 0:a9b4ee4ed395 1984 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 1985 }
mihaidd 0:a9b4ee4ed395 1986 }
mihaidd 0:a9b4ee4ed395 1987 },
mihaidd 0:a9b4ee4ed395 1988 "EFM32LG990F256": {
mihaidd 0:a9b4ee4ed395 1989 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 1990 "extra_labels_add": ["EFM32LG", "256K", "SL_AES"],
mihaidd 0:a9b4ee4ed395 1991 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 1992 "macros": ["EFM32LG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 1993 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 1994 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 1995 "device_name": "EFM32LG990F256",
mihaidd 0:a9b4ee4ed395 1996 "public": false
mihaidd 0:a9b4ee4ed395 1997 },
mihaidd 0:a9b4ee4ed395 1998 "EFM32LG_STK3600": {
mihaidd 0:a9b4ee4ed395 1999 "inherits": ["EFM32LG990F256"],
mihaidd 0:a9b4ee4ed395 2000 "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2001 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 2002 "device_name": "EFM32LG990F256",
mihaidd 0:a9b4ee4ed395 2003 "config": {
mihaidd 0:a9b4ee4ed395 2004 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2005 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2006 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2007 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2008 },
mihaidd 0:a9b4ee4ed395 2009 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2010 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2011 "value": "48000000",
mihaidd 0:a9b4ee4ed395 2012 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2013 },
mihaidd 0:a9b4ee4ed395 2014 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2015 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2016 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2017 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2018 },
mihaidd 0:a9b4ee4ed395 2019 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2020 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2021 "value": "32768",
mihaidd 0:a9b4ee4ed395 2022 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2023 },
mihaidd 0:a9b4ee4ed395 2024 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2025 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2026 "value": "21000000",
mihaidd 0:a9b4ee4ed395 2027 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2028 },
mihaidd 0:a9b4ee4ed395 2029 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2030 "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2031 "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
mihaidd 0:a9b4ee4ed395 2032 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2033 },
mihaidd 0:a9b4ee4ed395 2034 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 2035 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 2036 "value": "PF7",
mihaidd 0:a9b4ee4ed395 2037 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 2038 }
mihaidd 0:a9b4ee4ed395 2039 }
mihaidd 0:a9b4ee4ed395 2040 },
mihaidd 0:a9b4ee4ed395 2041 "EFM32WG990F256": {
mihaidd 0:a9b4ee4ed395 2042 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2043 "extra_labels_add": ["EFM32WG", "256K", "SL_AES"],
mihaidd 0:a9b4ee4ed395 2044 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2045 "macros": ["EFM32WG990F256", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 2046 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2047 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2048 "device_name": "EFM32WG990F256",
mihaidd 0:a9b4ee4ed395 2049 "public": false
mihaidd 0:a9b4ee4ed395 2050 },
mihaidd 0:a9b4ee4ed395 2051 "EFM32WG_STK3800": {
mihaidd 0:a9b4ee4ed395 2052 "inherits": ["EFM32WG990F256"],
mihaidd 0:a9b4ee4ed395 2053 "progen": {"target": "efm32wg-stk"},
mihaidd 0:a9b4ee4ed395 2054 "device_has": ["ANALOGIN", "ANALOGOUT", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2055 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 2056 "config": {
mihaidd 0:a9b4ee4ed395 2057 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2058 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2059 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2060 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2061 },
mihaidd 0:a9b4ee4ed395 2062 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2063 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2064 "value": "48000000",
mihaidd 0:a9b4ee4ed395 2065 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2066 },
mihaidd 0:a9b4ee4ed395 2067 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2068 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2069 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2070 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2071 },
mihaidd 0:a9b4ee4ed395 2072 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2073 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2074 "value": "32768",
mihaidd 0:a9b4ee4ed395 2075 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2076 },
mihaidd 0:a9b4ee4ed395 2077 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2078 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2079 "value": "21000000",
mihaidd 0:a9b4ee4ed395 2080 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2081 },
mihaidd 0:a9b4ee4ed395 2082 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2083 "help": "Value: One of _CMU_HFRCOCTRL_BAND_28MHZ, _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2084 "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
mihaidd 0:a9b4ee4ed395 2085 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2086 },
mihaidd 0:a9b4ee4ed395 2087 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 2088 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 2089 "value": "PF7",
mihaidd 0:a9b4ee4ed395 2090 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 2091 }
mihaidd 0:a9b4ee4ed395 2092 }
mihaidd 0:a9b4ee4ed395 2093 },
mihaidd 0:a9b4ee4ed395 2094 "EFM32ZG222F32": {
mihaidd 0:a9b4ee4ed395 2095 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2096 "extra_labels_add": ["EFM32ZG", "32K", "SL_AES"],
mihaidd 0:a9b4ee4ed395 2097 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 2098 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 2099 "macros": ["EFM32ZG222F32", "TRANSACTION_QUEUE_SIZE_SPI=0"],
mihaidd 0:a9b4ee4ed395 2100 "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2101 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 2102 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 2103 "device_name": "EFM32ZG222F32",
mihaidd 0:a9b4ee4ed395 2104 "public": false
mihaidd 0:a9b4ee4ed395 2105 },
mihaidd 0:a9b4ee4ed395 2106 "EFM32ZG_STK3200": {
mihaidd 0:a9b4ee4ed395 2107 "inherits": ["EFM32ZG222F32"],
mihaidd 0:a9b4ee4ed395 2108 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2109 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 2110 "config": {
mihaidd 0:a9b4ee4ed395 2111 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2112 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2113 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2114 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2115 },
mihaidd 0:a9b4ee4ed395 2116 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2117 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2118 "value": "24000000",
mihaidd 0:a9b4ee4ed395 2119 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2120 },
mihaidd 0:a9b4ee4ed395 2121 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2122 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2123 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2124 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2125 },
mihaidd 0:a9b4ee4ed395 2126 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2127 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2128 "value": "32768",
mihaidd 0:a9b4ee4ed395 2129 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2130 },
mihaidd 0:a9b4ee4ed395 2131 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2132 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2133 "value": "21000000",
mihaidd 0:a9b4ee4ed395 2134 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2135 },
mihaidd 0:a9b4ee4ed395 2136 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2137 "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2138 "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
mihaidd 0:a9b4ee4ed395 2139 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2140 },
mihaidd 0:a9b4ee4ed395 2141 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 2142 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 2143 "value": "PA9",
mihaidd 0:a9b4ee4ed395 2144 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 2145 }
mihaidd 0:a9b4ee4ed395 2146 }
mihaidd 0:a9b4ee4ed395 2147 },
mihaidd 0:a9b4ee4ed395 2148 "EFM32HG322F64": {
mihaidd 0:a9b4ee4ed395 2149 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2150 "extra_labels_add": ["EFM32HG", "64K", "SL_AES"],
mihaidd 0:a9b4ee4ed395 2151 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 2152 "default_toolchain": "uARM",
mihaidd 0:a9b4ee4ed395 2153 "macros": ["EFM32HG322F64", "TRANSACTION_QUEUE_SIZE_SPI=0"],
mihaidd 0:a9b4ee4ed395 2154 "supported_toolchains": ["GCC_ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2155 "default_lib": "small",
mihaidd 0:a9b4ee4ed395 2156 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 2157 "device_name": "EFM32HG322F64",
mihaidd 0:a9b4ee4ed395 2158 "public": false
mihaidd 0:a9b4ee4ed395 2159 },
mihaidd 0:a9b4ee4ed395 2160 "EFM32HG_STK3400": {
mihaidd 0:a9b4ee4ed395 2161 "inherits": ["EFM32HG322F64"],
mihaidd 0:a9b4ee4ed395 2162 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2163 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 2164 "config": {
mihaidd 0:a9b4ee4ed395 2165 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2166 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2167 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2168 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2169 },
mihaidd 0:a9b4ee4ed395 2170 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2171 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2172 "value": "24000000",
mihaidd 0:a9b4ee4ed395 2173 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2174 },
mihaidd 0:a9b4ee4ed395 2175 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2176 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2177 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2178 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2179 },
mihaidd 0:a9b4ee4ed395 2180 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2181 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2182 "value": "32768",
mihaidd 0:a9b4ee4ed395 2183 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2184 },
mihaidd 0:a9b4ee4ed395 2185 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2186 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2187 "value": "21000000",
mihaidd 0:a9b4ee4ed395 2188 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2189 },
mihaidd 0:a9b4ee4ed395 2190 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2191 "help": "Value: One of _CMU_HFRCOCTRL_BAND_21MHZ, _CMU_HFRCOCTRL_BAND_14MHZ, _CMU_HFRCOCTRL_BAND_11MHZ, _CMU_HFRCOCTRL_BAND_7MHZ, _CMU_HFRCOCTRL_BAND_1MHZ. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2192 "value": "_CMU_HFRCOCTRL_BAND_21MHZ",
mihaidd 0:a9b4ee4ed395 2193 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2194 },
mihaidd 0:a9b4ee4ed395 2195 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 2196 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 2197 "value": "PA9",
mihaidd 0:a9b4ee4ed395 2198 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 2199 }
mihaidd 0:a9b4ee4ed395 2200 }
mihaidd 0:a9b4ee4ed395 2201 },
mihaidd 0:a9b4ee4ed395 2202 "EFM32PG1B100F256GM32": {
mihaidd 0:a9b4ee4ed395 2203 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2204 "extra_labels_add": ["EFM32PG", "256K", "SL_CRYPTO"],
mihaidd 0:a9b4ee4ed395 2205 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2206 "macros": ["EFM32PG1B100F256GM32", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 2207 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2208 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2209 "device_name": "EFM32PG1B100F256GM32",
mihaidd 0:a9b4ee4ed395 2210 "public": false
mihaidd 0:a9b4ee4ed395 2211 },
mihaidd 0:a9b4ee4ed395 2212 "EFM32PG_STK3401": {
mihaidd 0:a9b4ee4ed395 2213 "inherits": ["EFM32PG1B100F256GM32"],
mihaidd 0:a9b4ee4ed395 2214 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2215 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 2216 "config": {
mihaidd 0:a9b4ee4ed395 2217 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2218 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2219 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2220 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2221 },
mihaidd 0:a9b4ee4ed395 2222 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2223 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2224 "value": "40000000",
mihaidd 0:a9b4ee4ed395 2225 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2226 },
mihaidd 0:a9b4ee4ed395 2227 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2228 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2229 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2230 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2231 },
mihaidd 0:a9b4ee4ed395 2232 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2233 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2234 "value": "32768",
mihaidd 0:a9b4ee4ed395 2235 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2236 },
mihaidd 0:a9b4ee4ed395 2237 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2238 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2239 "value": "32000000",
mihaidd 0:a9b4ee4ed395 2240 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2241 },
mihaidd 0:a9b4ee4ed395 2242 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2243 "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2244 "value": "cmuHFRCOFreq_32M0Hz",
mihaidd 0:a9b4ee4ed395 2245 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2246 },
mihaidd 0:a9b4ee4ed395 2247 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 2248 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 2249 "value": "PA5",
mihaidd 0:a9b4ee4ed395 2250 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 2251 }
mihaidd 0:a9b4ee4ed395 2252 }
mihaidd 0:a9b4ee4ed395 2253 },
mihaidd 0:a9b4ee4ed395 2254 "EFR32MG1P132F256GM48": {
mihaidd 0:a9b4ee4ed395 2255 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2256 "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
mihaidd 0:a9b4ee4ed395 2257 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2258 "macros": ["EFR32MG1P132F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 2259 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2260 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2261 "device_name": "EFR32MG1P132F256GM48",
mihaidd 0:a9b4ee4ed395 2262 "public": false
mihaidd 0:a9b4ee4ed395 2263 },
mihaidd 0:a9b4ee4ed395 2264 "EFR32MG1P233F256GM48": {
mihaidd 0:a9b4ee4ed395 2265 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2266 "extra_labels_add": ["EFR32MG1", "256K", "SL_RAIL", "SL_CRYPTO"],
mihaidd 0:a9b4ee4ed395 2267 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2268 "macros": ["EFR32MG1P233F256GM48", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 2269 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2270 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2271 "public": false
mihaidd 0:a9b4ee4ed395 2272 },
mihaidd 0:a9b4ee4ed395 2273 "EFR32MG1_BRD4150": {
mihaidd 0:a9b4ee4ed395 2274 "inherits": ["EFR32MG1P132F256GM48"],
mihaidd 0:a9b4ee4ed395 2275 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2276 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 2277 "config": {
mihaidd 0:a9b4ee4ed395 2278 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2279 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2280 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2281 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2282 },
mihaidd 0:a9b4ee4ed395 2283 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2284 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2285 "value": "38400000",
mihaidd 0:a9b4ee4ed395 2286 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2287 },
mihaidd 0:a9b4ee4ed395 2288 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2289 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2290 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2291 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2292 },
mihaidd 0:a9b4ee4ed395 2293 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2294 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2295 "value": "32768",
mihaidd 0:a9b4ee4ed395 2296 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2297 },
mihaidd 0:a9b4ee4ed395 2298 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2299 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2300 "value": "32000000",
mihaidd 0:a9b4ee4ed395 2301 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2302 },
mihaidd 0:a9b4ee4ed395 2303 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2304 "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2305 "value": "cmuHFRCOFreq_32M0Hz",
mihaidd 0:a9b4ee4ed395 2306 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2307 },
mihaidd 0:a9b4ee4ed395 2308 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 2309 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 2310 "value": "PA5",
mihaidd 0:a9b4ee4ed395 2311 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 2312 }
mihaidd 0:a9b4ee4ed395 2313 },
mihaidd 0:a9b4ee4ed395 2314 "public": false
mihaidd 0:a9b4ee4ed395 2315 },
mihaidd 0:a9b4ee4ed395 2316 "TB_SENSE_1": {
mihaidd 0:a9b4ee4ed395 2317 "inherits": ["EFR32MG1P233F256GM48"],
mihaidd 0:a9b4ee4ed395 2318 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2319 "forced_reset_timeout": 5,
mihaidd 0:a9b4ee4ed395 2320 "config": {
mihaidd 0:a9b4ee4ed395 2321 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2322 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2323 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2324 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2325 },
mihaidd 0:a9b4ee4ed395 2326 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2327 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2328 "value": "38400000",
mihaidd 0:a9b4ee4ed395 2329 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2330 },
mihaidd 0:a9b4ee4ed395 2331 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2332 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2333 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2334 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2335 },
mihaidd 0:a9b4ee4ed395 2336 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2337 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2338 "value": "32768",
mihaidd 0:a9b4ee4ed395 2339 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2340 },
mihaidd 0:a9b4ee4ed395 2341 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2342 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2343 "value": "32000000",
mihaidd 0:a9b4ee4ed395 2344 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2345 },
mihaidd 0:a9b4ee4ed395 2346 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2347 "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2348 "value": "cmuHFRCOFreq_32M0Hz",
mihaidd 0:a9b4ee4ed395 2349 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2350 }
mihaidd 0:a9b4ee4ed395 2351 }
mihaidd 0:a9b4ee4ed395 2352 },
mihaidd 0:a9b4ee4ed395 2353 "EFM32PG12B500F1024GL125": {
mihaidd 0:a9b4ee4ed395 2354 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2355 "extra_labels_add": ["EFM32PG12", "1024K", "SL_CRYPTO"],
mihaidd 0:a9b4ee4ed395 2356 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2357 "macros": ["EFM32PG12B500F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 2358 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2359 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2360 "public": false
mihaidd 0:a9b4ee4ed395 2361 },
mihaidd 0:a9b4ee4ed395 2362 "EFM32PG12_STK3402": {
mihaidd 0:a9b4ee4ed395 2363 "inherits": ["EFM32PG12B500F1024GL125"],
mihaidd 0:a9b4ee4ed395 2364 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2365 "forced_reset_timeout": 2,
mihaidd 0:a9b4ee4ed395 2366 "config": {
mihaidd 0:a9b4ee4ed395 2367 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2368 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2369 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2370 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2371 },
mihaidd 0:a9b4ee4ed395 2372 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2373 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2374 "value": "40000000",
mihaidd 0:a9b4ee4ed395 2375 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2376 },
mihaidd 0:a9b4ee4ed395 2377 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2378 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2379 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2380 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2381 },
mihaidd 0:a9b4ee4ed395 2382 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2383 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2384 "value": "32768",
mihaidd 0:a9b4ee4ed395 2385 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2386 },
mihaidd 0:a9b4ee4ed395 2387 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2388 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2389 "value": "32000000",
mihaidd 0:a9b4ee4ed395 2390 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2391 },
mihaidd 0:a9b4ee4ed395 2392 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2393 "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2394 "value": "cmuHFRCOFreq_32M0Hz",
mihaidd 0:a9b4ee4ed395 2395 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2396 },
mihaidd 0:a9b4ee4ed395 2397 "board_controller_enable": {
mihaidd 0:a9b4ee4ed395 2398 "help": "Pin to pull high for enabling the USB serial port",
mihaidd 0:a9b4ee4ed395 2399 "value": "PA5",
mihaidd 0:a9b4ee4ed395 2400 "macro_name": "EFM_BC_EN"
mihaidd 0:a9b4ee4ed395 2401 }
mihaidd 0:a9b4ee4ed395 2402 }
mihaidd 0:a9b4ee4ed395 2403 },
mihaidd 0:a9b4ee4ed395 2404 "EFR32MG12P332F1024GL125": {
mihaidd 0:a9b4ee4ed395 2405 "inherits": ["EFM32"],
mihaidd 0:a9b4ee4ed395 2406 "extra_labels_add": ["EFR32MG12", "1024K", "SL_RAIL", "SL_CRYPTO"],
mihaidd 0:a9b4ee4ed395 2407 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2408 "macros": ["EFR32MG12P332F1024GL125", "TRANSACTION_QUEUE_SIZE_SPI=4"],
mihaidd 0:a9b4ee4ed395 2409 "supported_toolchains": ["GCC_ARM", "ARM", "uARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2410 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2411 "public": false
mihaidd 0:a9b4ee4ed395 2412 },
mihaidd 0:a9b4ee4ed395 2413 "TB_SENSE_12": {
mihaidd 0:a9b4ee4ed395 2414 "inherits": ["EFR32MG12P332F1024GL125"],
mihaidd 0:a9b4ee4ed395 2415 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2416 "forced_reset_timeout": 5,
mihaidd 0:a9b4ee4ed395 2417 "config": {
mihaidd 0:a9b4ee4ed395 2418 "hf_clock_src": {
mihaidd 0:a9b4ee4ed395 2419 "help": "Value: HFXO for external crystal, HFRCO for internal RC oscillator",
mihaidd 0:a9b4ee4ed395 2420 "value": "HFXO",
mihaidd 0:a9b4ee4ed395 2421 "macro_name": "CORE_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2422 },
mihaidd 0:a9b4ee4ed395 2423 "hfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2424 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2425 "value": "38400000",
mihaidd 0:a9b4ee4ed395 2426 "macro_name": "HFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2427 },
mihaidd 0:a9b4ee4ed395 2428 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2429 "help": "Value: LFXO for external crystal, LFRCO for internal RC oscillator, ULFRCO for internal 1KHz RC oscillator",
mihaidd 0:a9b4ee4ed395 2430 "value": "LFXO",
mihaidd 0:a9b4ee4ed395 2431 "macro_name": "LOW_ENERGY_CLOCK_SOURCE"
mihaidd 0:a9b4ee4ed395 2432 },
mihaidd 0:a9b4ee4ed395 2433 "lfxo_clock_freq": {
mihaidd 0:a9b4ee4ed395 2434 "help": "Value: External crystal frequency in hertz",
mihaidd 0:a9b4ee4ed395 2435 "value": "32768",
mihaidd 0:a9b4ee4ed395 2436 "macro_name": "LFXO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2437 },
mihaidd 0:a9b4ee4ed395 2438 "hfrco_clock_freq": {
mihaidd 0:a9b4ee4ed395 2439 "help": "Value: Frequency in hertz, must correspond to setting of hfrco_band_select",
mihaidd 0:a9b4ee4ed395 2440 "value": "32000000",
mihaidd 0:a9b4ee4ed395 2441 "macro_name": "HFRCO_FREQUENCY"
mihaidd 0:a9b4ee4ed395 2442 },
mihaidd 0:a9b4ee4ed395 2443 "hfrco_band_select": {
mihaidd 0:a9b4ee4ed395 2444 "help": "Value: One of cmuHFRCOFreq_1M0Hz, cmuHFRCOFreq_2M0Hz, cmuHFRCOFreq_4M0Hz, cmuHFRCOFreq_7M0Hz, cmuHFRCOFreq_13M0Hz, cmuHFRCOFreq_16M0Hz, cmuHFRCOFreq_19M0Hz, cmuHFRCOFreq_26M0Hz, cmuHFRCOFreq_32M0Hz, cmuHFRCOFreq_38M0Hz. Be sure to set hfrco_clock_freq accordingly!",
mihaidd 0:a9b4ee4ed395 2445 "value": "cmuHFRCOFreq_32M0Hz",
mihaidd 0:a9b4ee4ed395 2446 "macro_name": "HFRCO_FREQUENCY_ENUM"
mihaidd 0:a9b4ee4ed395 2447 }
mihaidd 0:a9b4ee4ed395 2448 }
mihaidd 0:a9b4ee4ed395 2449 },
mihaidd 0:a9b4ee4ed395 2450 "WIZWIKI_W7500": {
mihaidd 0:a9b4ee4ed395 2451 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 2452 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 2453 "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500"],
mihaidd 0:a9b4ee4ed395 2454 "supported_toolchains": ["uARM", "ARM"],
mihaidd 0:a9b4ee4ed395 2455 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2456 "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2457 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 2458 },
mihaidd 0:a9b4ee4ed395 2459 "WIZWIKI_W7500P": {
mihaidd 0:a9b4ee4ed395 2460 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 2461 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 2462 "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500P"],
mihaidd 0:a9b4ee4ed395 2463 "supported_toolchains": ["uARM", "ARM"],
mihaidd 0:a9b4ee4ed395 2464 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2465 "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2466 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 2467 },
mihaidd 0:a9b4ee4ed395 2468 "WIZWIKI_W7500ECO": {
mihaidd 0:a9b4ee4ed395 2469 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2470 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 2471 "extra_labels": ["WIZNET", "W7500x", "WIZwiki_W7500ECO"],
mihaidd 0:a9b4ee4ed395 2472 "supported_toolchains": ["uARM", "ARM"],
mihaidd 0:a9b4ee4ed395 2473 "device_has": ["ANALOGIN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2474 "release_versions": ["2"]
mihaidd 0:a9b4ee4ed395 2475 },
mihaidd 0:a9b4ee4ed395 2476 "SAMR21G18A": {
mihaidd 0:a9b4ee4ed395 2477 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2478 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 2479 "macros": ["__SAMR21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
mihaidd 0:a9b4ee4ed395 2480 "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMR21"],
mihaidd 0:a9b4ee4ed395 2481 "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
mihaidd 0:a9b4ee4ed395 2482 "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
mihaidd 0:a9b4ee4ed395 2483 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 2484 "device_name": "ATSAMR21G18A"
mihaidd 0:a9b4ee4ed395 2485 },
mihaidd 0:a9b4ee4ed395 2486 "SAMD21J18A": {
mihaidd 0:a9b4ee4ed395 2487 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2488 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 2489 "macros": ["__SAMD21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
mihaidd 0:a9b4ee4ed395 2490 "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
mihaidd 0:a9b4ee4ed395 2491 "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
mihaidd 0:a9b4ee4ed395 2492 "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
mihaidd 0:a9b4ee4ed395 2493 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 2494 "device_name" : "ATSAMD21J18A"
mihaidd 0:a9b4ee4ed395 2495 },
mihaidd 0:a9b4ee4ed395 2496 "SAMD21G18A": {
mihaidd 0:a9b4ee4ed395 2497 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2498 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 2499 "macros": ["__SAMD21G18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
mihaidd 0:a9b4ee4ed395 2500 "extra_labels": ["Atmel", "SAM_CortexM0P", "SAMD21"],
mihaidd 0:a9b4ee4ed395 2501 "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
mihaidd 0:a9b4ee4ed395 2502 "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
mihaidd 0:a9b4ee4ed395 2503 "release_versions": ["2"],
mihaidd 0:a9b4ee4ed395 2504 "device_name": "ATSAMD21G18A"
mihaidd 0:a9b4ee4ed395 2505 },
mihaidd 0:a9b4ee4ed395 2506 "SAML21J18A": {
mihaidd 0:a9b4ee4ed395 2507 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2508 "core": "Cortex-M0+",
mihaidd 0:a9b4ee4ed395 2509 "macros": ["__SAML21J18A__", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
mihaidd 0:a9b4ee4ed395 2510 "extra_labels": ["Atmel", "SAM_CortexM0P", "SAML21"],
mihaidd 0:a9b4ee4ed395 2511 "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
mihaidd 0:a9b4ee4ed395 2512 "device_has": ["ANALOGIN", "ANALOGOUT", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
mihaidd 0:a9b4ee4ed395 2513 "device_name": "ATSAML21J18A"
mihaidd 0:a9b4ee4ed395 2514 },
mihaidd 0:a9b4ee4ed395 2515 "SAMG55J19": {
mihaidd 0:a9b4ee4ed395 2516 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2517 "core": "Cortex-M4",
mihaidd 0:a9b4ee4ed395 2518 "extra_labels": ["Atmel", "SAM_CortexM4", "SAMG55"],
mihaidd 0:a9b4ee4ed395 2519 "macros": ["__SAMG55J19__", "BOARD=75", "I2C_MASTER_CALLBACK_MODE=true", "EXTINT_CALLBACK_MODE=true", "USART_CALLBACK_MODE=true", "TC_ASYNC=true"],
mihaidd 0:a9b4ee4ed395 2520 "supported_toolchains": ["GCC_ARM", "ARM", "uARM"],
mihaidd 0:a9b4ee4ed395 2521 "default_toolchain": "ARM",
mihaidd 0:a9b4ee4ed395 2522 "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH"],
mihaidd 0:a9b4ee4ed395 2523 "default_lib": "std",
mihaidd 0:a9b4ee4ed395 2524 "device_name": "ATSAMG55J19"
mihaidd 0:a9b4ee4ed395 2525 },
mihaidd 0:a9b4ee4ed395 2526 "MCU_NRF51_UNIFIED": {
mihaidd 0:a9b4ee4ed395 2527 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2528 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 2529 "OVERRIDE_BOOTLOADER_FILENAME": "nrf51822_bootloader.hex",
mihaidd 0:a9b4ee4ed395 2530 "macros": [
mihaidd 0:a9b4ee4ed395 2531 "NRF51",
mihaidd 0:a9b4ee4ed395 2532 "TARGET_NRF51822",
mihaidd 0:a9b4ee4ed395 2533 "BLE_STACK_SUPPORT_REQD",
mihaidd 0:a9b4ee4ed395 2534 "SOFTDEVICE_PRESENT",
mihaidd 0:a9b4ee4ed395 2535 "S130",
mihaidd 0:a9b4ee4ed395 2536 "TARGET_MCU_NRF51822"
mihaidd 0:a9b4ee4ed395 2537 ],
mihaidd 0:a9b4ee4ed395 2538 "MERGE_BOOTLOADER": false,
mihaidd 0:a9b4ee4ed395 2539 "extra_labels": ["NORDIC", "MCU_NRF51", "MCU_NRF51822_UNIFIED", "NRF5"],
mihaidd 0:a9b4ee4ed395 2540 "OUTPUT_EXT": "hex",
mihaidd 0:a9b4ee4ed395 2541 "is_disk_virtual": true,
mihaidd 0:a9b4ee4ed395 2542 "supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2543 "public": false,
mihaidd 0:a9b4ee4ed395 2544 "MERGE_SOFT_DEVICE": true,
mihaidd 0:a9b4ee4ed395 2545 "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
mihaidd 0:a9b4ee4ed395 2546 {
mihaidd 0:a9b4ee4ed395 2547 "boot": "",
mihaidd 0:a9b4ee4ed395 2548 "name": "s130_nrf51_2.0.0_softdevice.hex",
mihaidd 0:a9b4ee4ed395 2549 "offset": 110592
mihaidd 0:a9b4ee4ed395 2550 }
mihaidd 0:a9b4ee4ed395 2551 ],
mihaidd 0:a9b4ee4ed395 2552 "detect_code": ["1070"],
mihaidd 0:a9b4ee4ed395 2553 "post_binary_hook": {
mihaidd 0:a9b4ee4ed395 2554 "function": "MCU_NRF51Code.binary_hook",
mihaidd 0:a9b4ee4ed395 2555 "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
mihaidd 0:a9b4ee4ed395 2556 },
mihaidd 0:a9b4ee4ed395 2557 "program_cycle_s": 6,
mihaidd 0:a9b4ee4ed395 2558 "features": ["BLE"],
mihaidd 0:a9b4ee4ed395 2559 "config": {
mihaidd 0:a9b4ee4ed395 2560 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2561 "value": "NRF_LF_SRC_XTAL",
mihaidd 0:a9b4ee4ed395 2562 "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
mihaidd 0:a9b4ee4ed395 2563 },
mihaidd 0:a9b4ee4ed395 2564 "uart_hwfc": {
mihaidd 0:a9b4ee4ed395 2565 "help": "Value: 1 for enable, 0 for disable",
mihaidd 0:a9b4ee4ed395 2566 "value": 1,
mihaidd 0:a9b4ee4ed395 2567 "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
mihaidd 0:a9b4ee4ed395 2568 }
mihaidd 0:a9b4ee4ed395 2569 },
mihaidd 0:a9b4ee4ed395 2570 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
mihaidd 0:a9b4ee4ed395 2571 },
mihaidd 0:a9b4ee4ed395 2572 "MCU_NRF51_32K_UNIFIED": {
mihaidd 0:a9b4ee4ed395 2573 "inherits": ["MCU_NRF51_UNIFIED"],
mihaidd 0:a9b4ee4ed395 2574 "extra_labels_add": ["MCU_NORDIC_32K", "MCU_NRF51_32K"],
mihaidd 0:a9b4ee4ed395 2575 "macros_add": ["TARGET_MCU_NORDIC_32K", "TARGET_MCU_NRF51_32K"],
mihaidd 0:a9b4ee4ed395 2576 "public": false
mihaidd 0:a9b4ee4ed395 2577 },
mihaidd 0:a9b4ee4ed395 2578 "NRF51_DK": {
mihaidd 0:a9b4ee4ed395 2579 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 2580 "inherits": ["MCU_NRF51_32K_UNIFIED"],
mihaidd 0:a9b4ee4ed395 2581 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2582 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2583 "device_name": "nRF51822_xxAA"
mihaidd 0:a9b4ee4ed395 2584 },
mihaidd 0:a9b4ee4ed395 2585 "NRF51_DONGLE": {
mihaidd 0:a9b4ee4ed395 2586 "inherits": ["MCU_NRF51_32K_UNIFIED"],
mihaidd 0:a9b4ee4ed395 2587 "progen": {"target": "nrf51-dongle"},
mihaidd 0:a9b4ee4ed395 2588 "device_has": ["ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2589 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 2590 },
mihaidd 0:a9b4ee4ed395 2591 "MCU_NRF52": {
mihaidd 0:a9b4ee4ed395 2592 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2593 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2594 "macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132"],
mihaidd 0:a9b4ee4ed395 2595 "extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5"],
mihaidd 0:a9b4ee4ed395 2596 "OUTPUT_EXT": "hex",
mihaidd 0:a9b4ee4ed395 2597 "is_disk_virtual": true,
mihaidd 0:a9b4ee4ed395 2598 "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2599 "public": false,
mihaidd 0:a9b4ee4ed395 2600 "detect_code": ["1101"],
mihaidd 0:a9b4ee4ed395 2601 "program_cycle_s": 6,
mihaidd 0:a9b4ee4ed395 2602 "MERGE_SOFT_DEVICE": true,
mihaidd 0:a9b4ee4ed395 2603 "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
mihaidd 0:a9b4ee4ed395 2604 {
mihaidd 0:a9b4ee4ed395 2605 "boot": "",
mihaidd 0:a9b4ee4ed395 2606 "name": "s132_nrf52_2.0.0_softdevice.hex",
mihaidd 0:a9b4ee4ed395 2607 "offset": 114688
mihaidd 0:a9b4ee4ed395 2608 }
mihaidd 0:a9b4ee4ed395 2609 ],
mihaidd 0:a9b4ee4ed395 2610 "post_binary_hook": {
mihaidd 0:a9b4ee4ed395 2611 "function": "MCU_NRF51Code.binary_hook",
mihaidd 0:a9b4ee4ed395 2612 "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
mihaidd 0:a9b4ee4ed395 2613 },
mihaidd 0:a9b4ee4ed395 2614 "MERGE_BOOTLOADER": false,
mihaidd 0:a9b4ee4ed395 2615 "features": ["BLE"],
mihaidd 0:a9b4ee4ed395 2616 "config": {
mihaidd 0:a9b4ee4ed395 2617 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2618 "value": "NRF_LF_SRC_XTAL",
mihaidd 0:a9b4ee4ed395 2619 "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
mihaidd 0:a9b4ee4ed395 2620 },
mihaidd 0:a9b4ee4ed395 2621 "uart_hwfc": {
mihaidd 0:a9b4ee4ed395 2622 "help": "Value: 1 for enable, 0 for disable",
mihaidd 0:a9b4ee4ed395 2623 "value": 1,
mihaidd 0:a9b4ee4ed395 2624 "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
mihaidd 0:a9b4ee4ed395 2625 }
mihaidd 0:a9b4ee4ed395 2626 }
mihaidd 0:a9b4ee4ed395 2627 },
mihaidd 0:a9b4ee4ed395 2628 "NRF52_DK": {
mihaidd 0:a9b4ee4ed395 2629 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 2630 "inherits": ["MCU_NRF52"],
mihaidd 0:a9b4ee4ed395 2631 "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
mihaidd 0:a9b4ee4ed395 2632 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2633 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2634 "device_name": "nRF52832_xxAA"
mihaidd 0:a9b4ee4ed395 2635 },
mihaidd 0:a9b4ee4ed395 2636 "UBLOX_EVA_NINA": {
mihaidd 0:a9b4ee4ed395 2637 "inherits": ["MCU_NRF52"],
mihaidd 0:a9b4ee4ed395 2638 "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
mihaidd 0:a9b4ee4ed395 2639 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2640 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2641 "overrides": {"uart_hwfc": 0},
mihaidd 0:a9b4ee4ed395 2642 "device_name": "nRF52832_xxAA"
mihaidd 0:a9b4ee4ed395 2643 },
mihaidd 0:a9b4ee4ed395 2644 "UBLOX_EVK_NINA_B1": {
mihaidd 0:a9b4ee4ed395 2645 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 2646 "inherits": ["MCU_NRF52"],
mihaidd 0:a9b4ee4ed395 2647 "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
mihaidd 0:a9b4ee4ed395 2648 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2649 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2650 "device_name": "nRF52832_xxAA"
mihaidd 0:a9b4ee4ed395 2651 },
mihaidd 0:a9b4ee4ed395 2652 "DELTA_DFBM_NQ620": {
mihaidd 0:a9b4ee4ed395 2653 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 2654 "inherits": ["MCU_NRF52"],
mihaidd 0:a9b4ee4ed395 2655 "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
mihaidd 0:a9b4ee4ed395 2656 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2657 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2658 "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
mihaidd 0:a9b4ee4ed395 2659 "config": {
mihaidd 0:a9b4ee4ed395 2660 "lf_clock_rc_calib_timer_interval": {
mihaidd 0:a9b4ee4ed395 2661 "value": 16,
mihaidd 0:a9b4ee4ed395 2662 "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_TIMER_INTERVAL"
mihaidd 0:a9b4ee4ed395 2663 },
mihaidd 0:a9b4ee4ed395 2664 "lf_clock_rc_calib_mode_config": {
mihaidd 0:a9b4ee4ed395 2665 "value": 0,
mihaidd 0:a9b4ee4ed395 2666 "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_CALIB_MODE_CONFIG"
mihaidd 0:a9b4ee4ed395 2667 }
mihaidd 0:a9b4ee4ed395 2668 },
mihaidd 0:a9b4ee4ed395 2669 "device_name": "nRF52832_xxAA"
mihaidd 0:a9b4ee4ed395 2670 },
mihaidd 0:a9b4ee4ed395 2671 "MCU_NRF52840": {
mihaidd 0:a9b4ee4ed395 2672 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2673 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2674 "macros": ["TARGET_NRF52840", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S140", "NRF_SD_BLE_API_VERSION=5", "NRF52840_XXAA", "NRF_DFU_SETTINGS_VERSION=1", "NRF_SD_BLE_API_VERSION=5"],
mihaidd 0:a9b4ee4ed395 2675 "extra_labels": ["NORDIC", "MCU_NRF52840", "NRF5_SDK13"],
mihaidd 0:a9b4ee4ed395 2676 "OUTPUT_EXT": "hex",
mihaidd 0:a9b4ee4ed395 2677 "is_disk_virtual": true,
mihaidd 0:a9b4ee4ed395 2678 "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2679 "public": false,
mihaidd 0:a9b4ee4ed395 2680 "detect_code": ["1101"],
mihaidd 0:a9b4ee4ed395 2681 "program_cycle_s": 6,
mihaidd 0:a9b4ee4ed395 2682 "MERGE_SOFT_DEVICE": true,
mihaidd 0:a9b4ee4ed395 2683 "EXPECTED_SOFTDEVICES_WITH_OFFSETS": [
mihaidd 0:a9b4ee4ed395 2684 {
mihaidd 0:a9b4ee4ed395 2685 "boot": "",
mihaidd 0:a9b4ee4ed395 2686 "name": "s140_nrf52840_5.0.0-1.alpha_softdevice.hex",
mihaidd 0:a9b4ee4ed395 2687 "offset": 135168
mihaidd 0:a9b4ee4ed395 2688 }
mihaidd 0:a9b4ee4ed395 2689 ],
mihaidd 0:a9b4ee4ed395 2690 "bootloader_select_index": 0,
mihaidd 0:a9b4ee4ed395 2691 "post_binary_hook": {
mihaidd 0:a9b4ee4ed395 2692 "function": "MCU_NRF51Code.binary_hook",
mihaidd 0:a9b4ee4ed395 2693 "toolchains": ["ARM_STD", "GCC_ARM", "IAR"]
mihaidd 0:a9b4ee4ed395 2694 },
mihaidd 0:a9b4ee4ed395 2695 "MERGE_BOOTLOADER": false,
mihaidd 0:a9b4ee4ed395 2696 "features": ["BLE"],
mihaidd 0:a9b4ee4ed395 2697 "config": {
mihaidd 0:a9b4ee4ed395 2698 "lf_clock_src": {
mihaidd 0:a9b4ee4ed395 2699 "value": "NRF_LF_SRC_XTAL",
mihaidd 0:a9b4ee4ed395 2700 "macro_name": "MBED_CONF_NORDIC_NRF_LF_CLOCK_SRC"
mihaidd 0:a9b4ee4ed395 2701 },
mihaidd 0:a9b4ee4ed395 2702 "uart_hwfc": {
mihaidd 0:a9b4ee4ed395 2703 "help": "Value: 1 for enable, 0 for disable",
mihaidd 0:a9b4ee4ed395 2704 "value": 1,
mihaidd 0:a9b4ee4ed395 2705 "macro_name": "MBED_CONF_NORDIC_UART_HWFC"
mihaidd 0:a9b4ee4ed395 2706 }
mihaidd 0:a9b4ee4ed395 2707 }
mihaidd 0:a9b4ee4ed395 2708 },
mihaidd 0:a9b4ee4ed395 2709 "NRF52840_DK": {
mihaidd 0:a9b4ee4ed395 2710 "supported_form_factors": ["ARDUINO"],
mihaidd 0:a9b4ee4ed395 2711 "inherits": ["MCU_NRF52840"],
mihaidd 0:a9b4ee4ed395 2712 "macros_add": ["BOARD_PCA10056", "CONFIG_GPIO_AS_PINRESET", "SWI_DISABLE0", "NRF52_ERRATA_20"],
mihaidd 0:a9b4ee4ed395 2713 "device_has": ["ANALOGIN", "ERROR_PATTERN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2714 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2715 "device_name": "nRF52840_xxAA"
mihaidd 0:a9b4ee4ed395 2716 },
mihaidd 0:a9b4ee4ed395 2717 "BLUEPILL_F103C8": {
mihaidd 0:a9b4ee4ed395 2718 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 2719 "default_toolchain": "GCC_ARM",
mihaidd 0:a9b4ee4ed395 2720 "extra_labels": ["STM", "STM32F1", "STM32F103C8"],
mihaidd 0:a9b4ee4ed395 2721 "supported_toolchains": ["GCC_ARM"],
mihaidd 0:a9b4ee4ed395 2722 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2723 "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"]
mihaidd 0:a9b4ee4ed395 2724 },
mihaidd 0:a9b4ee4ed395 2725 "NUMAKER_PFM_NUC472": {
mihaidd 0:a9b4ee4ed395 2726 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2727 "default_toolchain": "ARM",
mihaidd 0:a9b4ee4ed395 2728 "extra_labels": ["NUVOTON", "NUC472", "NU_XRAM_SUPPORTED", "FLASH_CMSIS_ALGO"],
mihaidd 0:a9b4ee4ed395 2729 "is_disk_virtual": true,
mihaidd 0:a9b4ee4ed395 2730 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2731 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2732 "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "TRNG", "CAN", "FLASH"],
mihaidd 0:a9b4ee4ed395 2733 "features": ["LWIP"],
mihaidd 0:a9b4ee4ed395 2734 "release_versions": ["5"],
mihaidd 0:a9b4ee4ed395 2735 "device_name": "NUC472HI8AE",
mihaidd 0:a9b4ee4ed395 2736 "bootloader_supported": true
mihaidd 0:a9b4ee4ed395 2737 },
mihaidd 0:a9b4ee4ed395 2738 "NCS36510": {
mihaidd 0:a9b4ee4ed395 2739 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2740 "core": "Cortex-M3",
mihaidd 0:a9b4ee4ed395 2741 "extra_labels": ["ONSEMI"],
mihaidd 0:a9b4ee4ed395 2742 "config": {
mihaidd 0:a9b4ee4ed395 2743 "mac-addr-low": {
mihaidd 0:a9b4ee4ed395 2744 "help": "Lower 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
mihaidd 0:a9b4ee4ed395 2745 "value": "0xFFFFFFFF"
mihaidd 0:a9b4ee4ed395 2746 },
mihaidd 0:a9b4ee4ed395 2747 "mac-addr-high": {
mihaidd 0:a9b4ee4ed395 2748 "help": "Higher 32 bits of the MAC extended address. All FFs indicates that factory programmed MAC address shall be used. In order to override the factory programmed MAC address this value needs to be changed from 0xFFFFFFFF to any chosen value.",
mihaidd 0:a9b4ee4ed395 2749 "value": "0xFFFFFFFF"
mihaidd 0:a9b4ee4ed395 2750 },
mihaidd 0:a9b4ee4ed395 2751 "32KHz-clk-trim": {
mihaidd 0:a9b4ee4ed395 2752 "help": "32KHz clock trim",
mihaidd 0:a9b4ee4ed395 2753 "value": "0x39"
mihaidd 0:a9b4ee4ed395 2754 },
mihaidd 0:a9b4ee4ed395 2755 "32MHz-clk-trim": {
mihaidd 0:a9b4ee4ed395 2756 "help": "32MHz clock trim",
mihaidd 0:a9b4ee4ed395 2757 "value": "0x17"
mihaidd 0:a9b4ee4ed395 2758 },
mihaidd 0:a9b4ee4ed395 2759 "rssi-trim": {
mihaidd 0:a9b4ee4ed395 2760 "help": "RSSI trim",
mihaidd 0:a9b4ee4ed395 2761 "value": "0x3D"
mihaidd 0:a9b4ee4ed395 2762 },
mihaidd 0:a9b4ee4ed395 2763 "txtune-trim": {
mihaidd 0:a9b4ee4ed395 2764 "help": "TX tune trim",
mihaidd 0:a9b4ee4ed395 2765 "value": "0xFFFFFFFF"
mihaidd 0:a9b4ee4ed395 2766 }
mihaidd 0:a9b4ee4ed395 2767 },
mihaidd 0:a9b4ee4ed395 2768 "post_binary_hook": {"function": "NCS36510TargetCode.ncs36510_addfib"},
mihaidd 0:a9b4ee4ed395 2769 "macros": ["CM3", "CPU_NCS36510", "TARGET_NCS36510", "LOAD_ADDRESS=0x3000"],
mihaidd 0:a9b4ee4ed395 2770 "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2771 "device_has": ["ANALOGIN", "SERIAL", "I2C", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_FC", "SLEEP", "SPI", "LOWPOWERTIMER", "TRNG", "SPISLAVE"],
mihaidd 0:a9b4ee4ed395 2772 "release_versions": ["2", "5"]
mihaidd 0:a9b4ee4ed395 2773 },
mihaidd 0:a9b4ee4ed395 2774 "NUMAKER_PFM_M453": {
mihaidd 0:a9b4ee4ed395 2775 "core": "Cortex-M4F",
mihaidd 0:a9b4ee4ed395 2776 "default_toolchain": "ARM",
mihaidd 0:a9b4ee4ed395 2777 "extra_labels": ["NUVOTON", "M451", "NUMAKER_PFM_M453", "FLASH_CMSIS_ALGO"],
mihaidd 0:a9b4ee4ed395 2778 "is_disk_virtual": true,
mihaidd 0:a9b4ee4ed395 2779 "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2780 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2781 "progen": {"target": "numaker-pfm-m453"},
mihaidd 0:a9b4ee4ed395 2782 "device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "STDIO_MESSAGES", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "CAN", "FLASH"],
mihaidd 0:a9b4ee4ed395 2783 "release_versions": ["2", "5"],
mihaidd 0:a9b4ee4ed395 2784 "device_name": "M453VG6AE",
mihaidd 0:a9b4ee4ed395 2785 "bootloader_supported": true
mihaidd 0:a9b4ee4ed395 2786 },
mihaidd 0:a9b4ee4ed395 2787 "HI2110": {
mihaidd 0:a9b4ee4ed395 2788 "inherits": ["Target"],
mihaidd 0:a9b4ee4ed395 2789 "core": "Cortex-M0",
mihaidd 0:a9b4ee4ed395 2790 "default_toolchain": "GCC_ARM",
mihaidd 0:a9b4ee4ed395 2791 "supported_toolchains": ["GCC_ARM", "ARM", "IAR"],
mihaidd 0:a9b4ee4ed395 2792 "extra_labels": ["ublox"],
mihaidd 0:a9b4ee4ed395 2793 "macros": ["TARGET_PROCESSOR_FAMILY_BOUDICA", "BOUDICA_SARA", "NDEBUG=1"],
mihaidd 0:a9b4ee4ed395 2794 "public": false,
mihaidd 0:a9b4ee4ed395 2795 "target_overrides": {
mihaidd 0:a9b4ee4ed395 2796 "*": {
mihaidd 0:a9b4ee4ed395 2797 "core.stdio-flush-at-exit": false
mihaidd 0:a9b4ee4ed395 2798 }
mihaidd 0:a9b4ee4ed395 2799 },
mihaidd 0:a9b4ee4ed395 2800 "device_has": ["INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "SERIAL", "SLEEP", "STDIO_MESSAGES"],
mihaidd 0:a9b4ee4ed395 2801 "default_lib": "std",
mihaidd 0:a9b4ee4ed395 2802 "release_versions": ["5"]
mihaidd 0:a9b4ee4ed395 2803 },
mihaidd 0:a9b4ee4ed395 2804 "SARA_NBIOT": {
mihaidd 0:a9b4ee4ed395 2805 "inherits": ["HI2110"],
mihaidd 0:a9b4ee4ed395 2806 "extra_labels": ["ublox", "HI2110"],
mihaidd 0:a9b4ee4ed395 2807 "public": false
mihaidd 0:a9b4ee4ed395 2808 },
mihaidd 0:a9b4ee4ed395 2809 "SARA_NBIOT_EVK": {
mihaidd 0:a9b4ee4ed395 2810 "inherits": ["SARA_NBIOT"],
mihaidd 0:a9b4ee4ed395 2811 "extra_labels": ["ublox", "HI2110", "SARA_NBIOT"]
mihaidd 0:a9b4ee4ed395 2812 }
mihaidd 0:a9b4ee4ed395 2813 }