Michele Riccio / mbed-dsp_F767ZI

mbed-os 6.10 versione

cmsis_dsp/BasicMathFunctions/arm_scale_q15.c@1:fdd22bb7aa52, 2012-11-28 (annotated)

Committer:
emilmont
Date:
Wed Nov 28 12:30:09 2012 +0000
Revision:
1:fdd22bb7aa52
Child:
2:da51fb522205
DSP library code

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
emilmont 1:fdd22bb7aa52 2 * Copyright (C) 2010 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
emilmont 1:fdd22bb7aa52 4 * $Date: 15. February 2012
emilmont 1:fdd22bb7aa52 5 * $Revision: V1.1.0
emilmont 1:fdd22bb7aa52 6 *
emilmont 1:fdd22bb7aa52 7 * Project: CMSIS DSP Library
emilmont 1:fdd22bb7aa52 8 * Title: arm_scale_q15.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 1:fdd22bb7aa52 10 * Description: Multiplies a Q15 vector by a scalar.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
emilmont 1:fdd22bb7aa52 14 * Version 1.1.0 2012/02/15
emilmont 1:fdd22bb7aa52 15 * Updated with more optimizations, bug fixes and minor API changes.
emilmont 1:fdd22bb7aa52 16 *
emilmont 1:fdd22bb7aa52 17 * Version 1.0.10 2011/7/15
emilmont 1:fdd22bb7aa52 18 * Big Endian support added and Merged M0 and M3/M4 Source code.
emilmont 1:fdd22bb7aa52 19 *
emilmont 1:fdd22bb7aa52 20 * Version 1.0.3 2010/11/29
emilmont 1:fdd22bb7aa52 21 * Re-organized the CMSIS folders and updated documentation.
emilmont 1:fdd22bb7aa52 22 *
emilmont 1:fdd22bb7aa52 23 * Version 1.0.2 2010/11/11
emilmont 1:fdd22bb7aa52 24 * Documentation updated.
emilmont 1:fdd22bb7aa52 25 *
emilmont 1:fdd22bb7aa52 26 * Version 1.0.1 2010/10/05
emilmont 1:fdd22bb7aa52 27 * Production release and review comments incorporated.
emilmont 1:fdd22bb7aa52 28 *
emilmont 1:fdd22bb7aa52 29 * Version 1.0.0 2010/09/20
emilmont 1:fdd22bb7aa52 30 * Production release and review comments incorporated
emilmont 1:fdd22bb7aa52 31 *
emilmont 1:fdd22bb7aa52 32 * Version 0.0.7 2010/06/10
emilmont 1:fdd22bb7aa52 33 * Misra-C changes done
emilmont 1:fdd22bb7aa52 34 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 35
emilmont 1:fdd22bb7aa52 36 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 37
emilmont 1:fdd22bb7aa52 38 /**
emilmont 1:fdd22bb7aa52 39 * @ingroup groupMath
emilmont 1:fdd22bb7aa52 40 */
emilmont 1:fdd22bb7aa52 41
emilmont 1:fdd22bb7aa52 42 /**
emilmont 1:fdd22bb7aa52 43 * @addtogroup scale
emilmont 1:fdd22bb7aa52 44 * @{
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @brief Multiplies a Q15 vector by a scalar.
emilmont 1:fdd22bb7aa52 49 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 50 * @param[in] scaleFract fractional portion of the scale value
emilmont 1:fdd22bb7aa52 51 * @param[in] shift number of bits to shift the result by
emilmont 1:fdd22bb7aa52 52 * @param[out] *pDst points to the output vector
emilmont 1:fdd22bb7aa52 53 * @param[in] blockSize number of samples in the vector
emilmont 1:fdd22bb7aa52 54 * @return none.
emilmont 1:fdd22bb7aa52 55 *
emilmont 1:fdd22bb7aa52 56 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 57 * \par
emilmont 1:fdd22bb7aa52 58 * The input data <code>*pSrc</code> and <code>scaleFract</code> are in 1.15 format.
emilmont 1:fdd22bb7aa52 59 * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.
emilmont 1:fdd22bb7aa52 60 */
emilmont 1:fdd22bb7aa52 61
emilmont 1:fdd22bb7aa52 62
emilmont 1:fdd22bb7aa52 63 void arm_scale_q15(
emilmont 1:fdd22bb7aa52 64 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 65 q15_t scaleFract,
emilmont 1:fdd22bb7aa52 66 int8_t shift,
emilmont 1:fdd22bb7aa52 67 q15_t * pDst,
emilmont 1:fdd22bb7aa52 68 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 69 {
emilmont 1:fdd22bb7aa52 70 int8_t kShift = 15 - shift; /* shift to apply after scaling */
emilmont 1:fdd22bb7aa52 71 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 72
emilmont 1:fdd22bb7aa52 73 #ifndef ARM_MATH_CM0
emilmont 1:fdd22bb7aa52 74
emilmont 1:fdd22bb7aa52 75 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 76 q15_t in1, in2, in3, in4;
emilmont 1:fdd22bb7aa52 77 q31_t inA1, inA2; /* Temporary variables */
emilmont 1:fdd22bb7aa52 78 q31_t out1, out2, out3, out4;
emilmont 1:fdd22bb7aa52 79
emilmont 1:fdd22bb7aa52 80
emilmont 1:fdd22bb7aa52 81 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 82 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 83
emilmont 1:fdd22bb7aa52 84 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 85 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 86 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 87 {
emilmont 1:fdd22bb7aa52 88 /* Reading 2 inputs from memory */
emilmont 1:fdd22bb7aa52 89 inA1 = *__SIMD32(pSrc)++;
emilmont 1:fdd22bb7aa52 90 inA2 = *__SIMD32(pSrc)++;
emilmont 1:fdd22bb7aa52 91
emilmont 1:fdd22bb7aa52 92 /* C = A * scale */
emilmont 1:fdd22bb7aa52 93 /* Scale the inputs and then store the 2 results in the destination buffer
emilmont 1:fdd22bb7aa52 94 * in single cycle by packing the outputs */
emilmont 1:fdd22bb7aa52 95 out1 = (q31_t) ((q15_t) (inA1 >> 16) * scaleFract);
emilmont 1:fdd22bb7aa52 96 out2 = (q31_t) ((q15_t) inA1 * scaleFract);
emilmont 1:fdd22bb7aa52 97 out3 = (q31_t) ((q15_t) (inA2 >> 16) * scaleFract);
emilmont 1:fdd22bb7aa52 98 out4 = (q31_t) ((q15_t) inA2 * scaleFract);
emilmont 1:fdd22bb7aa52 99
emilmont 1:fdd22bb7aa52 100 /* apply shifting */
emilmont 1:fdd22bb7aa52 101 out1 = out1 >> kShift;
emilmont 1:fdd22bb7aa52 102 out2 = out2 >> kShift;
emilmont 1:fdd22bb7aa52 103 out3 = out3 >> kShift;
emilmont 1:fdd22bb7aa52 104 out4 = out4 >> kShift;
emilmont 1:fdd22bb7aa52 105
emilmont 1:fdd22bb7aa52 106 /* saturate the output */
emilmont 1:fdd22bb7aa52 107 in1 = (q15_t) (__SSAT(out1, 16));
emilmont 1:fdd22bb7aa52 108 in2 = (q15_t) (__SSAT(out2, 16));
emilmont 1:fdd22bb7aa52 109 in3 = (q15_t) (__SSAT(out3, 16));
emilmont 1:fdd22bb7aa52 110 in4 = (q15_t) (__SSAT(out4, 16));
emilmont 1:fdd22bb7aa52 111
emilmont 1:fdd22bb7aa52 112 /* store the result to destination */
emilmont 1:fdd22bb7aa52 113 *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
emilmont 1:fdd22bb7aa52 114 *__SIMD32(pDst)++ = __PKHBT(in4, in3, 16);
emilmont 1:fdd22bb7aa52 115
emilmont 1:fdd22bb7aa52 116 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 117 blkCnt--;
emilmont 1:fdd22bb7aa52 118 }
emilmont 1:fdd22bb7aa52 119
emilmont 1:fdd22bb7aa52 120 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 121 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 122 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 123
emilmont 1:fdd22bb7aa52 124 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 125 {
emilmont 1:fdd22bb7aa52 126 /* C = A * scale */
emilmont 1:fdd22bb7aa52 127 /* Scale the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 128 *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16));
emilmont 1:fdd22bb7aa52 129
emilmont 1:fdd22bb7aa52 130 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 131 blkCnt--;
emilmont 1:fdd22bb7aa52 132 }
emilmont 1:fdd22bb7aa52 133
emilmont 1:fdd22bb7aa52 134 #else
emilmont 1:fdd22bb7aa52 135
emilmont 1:fdd22bb7aa52 136 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 137
emilmont 1:fdd22bb7aa52 138 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 139 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 140
emilmont 1:fdd22bb7aa52 141 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 142 {
emilmont 1:fdd22bb7aa52 143 /* C = A * scale */
emilmont 1:fdd22bb7aa52 144 /* Scale the input and then store the result in the destination buffer. */
emilmont 1:fdd22bb7aa52 145 *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16));
emilmont 1:fdd22bb7aa52 146
emilmont 1:fdd22bb7aa52 147 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 148 blkCnt--;
emilmont 1:fdd22bb7aa52 149 }
emilmont 1:fdd22bb7aa52 150
emilmont 1:fdd22bb7aa52 151 #endif /* #ifndef ARM_MATH_CM0 */
emilmont 1:fdd22bb7aa52 152
emilmont 1:fdd22bb7aa52 153 }
emilmont 1:fdd22bb7aa52 154
emilmont 1:fdd22bb7aa52 155 /**
emilmont 1:fdd22bb7aa52 156 * @} end of scale group
emilmont 1:fdd22bb7aa52 157 */