Michele Riccio / mbed-dsp_F767ZI

mbed-os 6.10 versione

cmsis_dsp/BasicMathFunctions/arm_offset_q15.c@5:ed60e5c5c2a8, 2021-06-21 (annotated)

Committer:
michelericcio
Date:
Mon Jun 21 10:16:02 2021 +0000
Revision:
5:ed60e5c5c2a8
Parent:
3:7a284390b0ce 
mbed-dsp working on ST Nucleo F767ZI and mbed-OS 6

Who changed what in which revision?

UserRevisionLine numberNew contents of line
emilmont 1:fdd22bb7aa52 1 /* ----------------------------------------------------------------------
mbed_official 3:7a284390b0ce 2 * Copyright (C) 2010-2013 ARM Limited. All rights reserved.
emilmont 1:fdd22bb7aa52 3 *
mbed_official 3:7a284390b0ce 4 * $Date: 17. January 2013
mbed_official 3:7a284390b0ce 5 * $Revision: V1.4.1
emilmont 1:fdd22bb7aa52 6 *
emilmont 2:da51fb522205 7 * Project: CMSIS DSP Library
emilmont 2:da51fb522205 8 * Title: arm_offset_q15.c
emilmont 1:fdd22bb7aa52 9 *
emilmont 2:da51fb522205 10 * Description: Q15 vector offset.
emilmont 1:fdd22bb7aa52 11 *
emilmont 1:fdd22bb7aa52 12 * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
emilmont 1:fdd22bb7aa52 13 *
mbed_official 3:7a284390b0ce 14 * Redistribution and use in source and binary forms, with or without
mbed_official 3:7a284390b0ce 15 * modification, are permitted provided that the following conditions
mbed_official 3:7a284390b0ce 16 * are met:
mbed_official 3:7a284390b0ce 17 * - Redistributions of source code must retain the above copyright
mbed_official 3:7a284390b0ce 18 * notice, this list of conditions and the following disclaimer.
mbed_official 3:7a284390b0ce 19 * - Redistributions in binary form must reproduce the above copyright
mbed_official 3:7a284390b0ce 20 * notice, this list of conditions and the following disclaimer in
mbed_official 3:7a284390b0ce 21 * the documentation and/or other materials provided with the
mbed_official 3:7a284390b0ce 22 * distribution.
mbed_official 3:7a284390b0ce 23 * - Neither the name of ARM LIMITED nor the names of its contributors
mbed_official 3:7a284390b0ce 24 * may be used to endorse or promote products derived from this
mbed_official 3:7a284390b0ce 25 * software without specific prior written permission.
mbed_official 3:7a284390b0ce 26 *
mbed_official 3:7a284390b0ce 27 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
mbed_official 3:7a284390b0ce 28 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
mbed_official 3:7a284390b0ce 29 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
mbed_official 3:7a284390b0ce 30 * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
mbed_official 3:7a284390b0ce 31 * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
mbed_official 3:7a284390b0ce 32 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
mbed_official 3:7a284390b0ce 33 * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
mbed_official 3:7a284390b0ce 34 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
mbed_official 3:7a284390b0ce 35 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
mbed_official 3:7a284390b0ce 36 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
mbed_official 3:7a284390b0ce 37 * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mbed_official 3:7a284390b0ce 38 * POSSIBILITY OF SUCH DAMAGE.
emilmont 1:fdd22bb7aa52 39 * -------------------------------------------------------------------- */
emilmont 1:fdd22bb7aa52 40
emilmont 1:fdd22bb7aa52 41 #include "arm_math.h"
emilmont 1:fdd22bb7aa52 42
emilmont 1:fdd22bb7aa52 43 /**
emilmont 1:fdd22bb7aa52 44 * @ingroup groupMath
emilmont 1:fdd22bb7aa52 45 */
emilmont 1:fdd22bb7aa52 46
emilmont 1:fdd22bb7aa52 47 /**
emilmont 1:fdd22bb7aa52 48 * @addtogroup offset
emilmont 1:fdd22bb7aa52 49 * @{
emilmont 1:fdd22bb7aa52 50 */
emilmont 1:fdd22bb7aa52 51
emilmont 1:fdd22bb7aa52 52 /**
emilmont 1:fdd22bb7aa52 53 * @brief Adds a constant offset to a Q15 vector.
emilmont 1:fdd22bb7aa52 54 * @param[in] *pSrc points to the input vector
emilmont 1:fdd22bb7aa52 55 * @param[in] offset is the offset to be added
emilmont 1:fdd22bb7aa52 56 * @param[out] *pDst points to the output vector
emilmont 1:fdd22bb7aa52 57 * @param[in] blockSize number of samples in the vector
emilmont 1:fdd22bb7aa52 58 * @return none.
emilmont 1:fdd22bb7aa52 59 *
emilmont 1:fdd22bb7aa52 60 * <b>Scaling and Overflow Behavior:</b>
emilmont 1:fdd22bb7aa52 61 * \par
emilmont 1:fdd22bb7aa52 62 * The function uses saturating arithmetic.
emilmont 1:fdd22bb7aa52 63 * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated.
emilmont 1:fdd22bb7aa52 64 */
emilmont 1:fdd22bb7aa52 65
emilmont 1:fdd22bb7aa52 66 void arm_offset_q15(
emilmont 1:fdd22bb7aa52 67 q15_t * pSrc,
emilmont 1:fdd22bb7aa52 68 q15_t offset,
emilmont 1:fdd22bb7aa52 69 q15_t * pDst,
emilmont 1:fdd22bb7aa52 70 uint32_t blockSize)
emilmont 1:fdd22bb7aa52 71 {
emilmont 1:fdd22bb7aa52 72 uint32_t blkCnt; /* loop counter */
emilmont 1:fdd22bb7aa52 73
mbed_official 3:7a284390b0ce 74 #ifndef ARM_MATH_CM0_FAMILY
emilmont 1:fdd22bb7aa52 75
emilmont 1:fdd22bb7aa52 76 /* Run the below code for Cortex-M4 and Cortex-M3 */
emilmont 1:fdd22bb7aa52 77 q31_t offset_packed; /* Offset packed to 32 bit */
emilmont 1:fdd22bb7aa52 78
emilmont 1:fdd22bb7aa52 79
emilmont 1:fdd22bb7aa52 80 /*loop Unrolling */
emilmont 1:fdd22bb7aa52 81 blkCnt = blockSize >> 2u;
emilmont 1:fdd22bb7aa52 82
emilmont 1:fdd22bb7aa52 83 /* Offset is packed to 32 bit in order to use SIMD32 for addition */
emilmont 1:fdd22bb7aa52 84 offset_packed = __PKHBT(offset, offset, 16);
emilmont 1:fdd22bb7aa52 85
emilmont 1:fdd22bb7aa52 86 /* First part of the processing with loop unrolling. Compute 4 outputs at a time.
emilmont 1:fdd22bb7aa52 87 ** a second loop below computes the remaining 1 to 3 samples. */
emilmont 1:fdd22bb7aa52 88 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 89 {
emilmont 1:fdd22bb7aa52 90 /* C = A + offset */
emilmont 1:fdd22bb7aa52 91 /* Add offset and then store the results in the destination buffer, 2 samples at a time. */
emilmont 1:fdd22bb7aa52 92 *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
emilmont 1:fdd22bb7aa52 93 *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed);
emilmont 1:fdd22bb7aa52 94
emilmont 1:fdd22bb7aa52 95 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 96 blkCnt--;
emilmont 1:fdd22bb7aa52 97 }
emilmont 1:fdd22bb7aa52 98
emilmont 1:fdd22bb7aa52 99 /* If the blockSize is not a multiple of 4, compute any remaining output samples here.
emilmont 1:fdd22bb7aa52 100 ** No loop unrolling is used. */
emilmont 1:fdd22bb7aa52 101 blkCnt = blockSize % 0x4u;
emilmont 1:fdd22bb7aa52 102
emilmont 1:fdd22bb7aa52 103 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 104 {
emilmont 1:fdd22bb7aa52 105 /* C = A + offset */
emilmont 1:fdd22bb7aa52 106 /* Add offset and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 107 *pDst++ = (q15_t) __QADD16(*pSrc++, offset);
emilmont 1:fdd22bb7aa52 108
emilmont 1:fdd22bb7aa52 109 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 110 blkCnt--;
emilmont 1:fdd22bb7aa52 111 }
emilmont 1:fdd22bb7aa52 112
emilmont 1:fdd22bb7aa52 113 #else
emilmont 1:fdd22bb7aa52 114
emilmont 1:fdd22bb7aa52 115 /* Run the below code for Cortex-M0 */
emilmont 1:fdd22bb7aa52 116
emilmont 1:fdd22bb7aa52 117 /* Initialize blkCnt with number of samples */
emilmont 1:fdd22bb7aa52 118 blkCnt = blockSize;
emilmont 1:fdd22bb7aa52 119
emilmont 1:fdd22bb7aa52 120 while(blkCnt > 0u)
emilmont 1:fdd22bb7aa52 121 {
emilmont 1:fdd22bb7aa52 122 /* C = A + offset */
emilmont 1:fdd22bb7aa52 123 /* Add offset and then store the results in the destination buffer. */
emilmont 1:fdd22bb7aa52 124 *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16);
emilmont 1:fdd22bb7aa52 125
emilmont 1:fdd22bb7aa52 126 /* Decrement the loop counter */
emilmont 1:fdd22bb7aa52 127 blkCnt--;
emilmont 1:fdd22bb7aa52 128 }
emilmont 1:fdd22bb7aa52 129
mbed_official 3:7a284390b0ce 130 #endif /* #ifndef ARM_MATH_CM0_FAMILY */
emilmont 1:fdd22bb7aa52 131
emilmont 1:fdd22bb7aa52 132 }
emilmont 1:fdd22bb7aa52 133
emilmont 1:fdd22bb7aa52 134 /**
emilmont 1:fdd22bb7aa52 135 * @} end of offset group
emilmont 1:fdd22bb7aa52 136 */