Mark Gottscho / SensorsLib

A compilation of some hardware sensors and their shared programming interfaces.

MAG3110.cpp@1:15396cab58d1, 2014-03-19 (annotated)

Committer:
mgottscho
Date:
Wed Mar 19 00:35:31 2014 +0000
Revision:
1:15396cab58d1
Parent:
0:8d34cc2ff388 
Updated for most recent UtilityLib.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mgottscho 0:8d34cc2ff388 1 /* MAG3110.cpp
mgottscho 0:8d34cc2ff388 2 * Tested with mbed board: FRDM-KL46Z
mgottscho 0:8d34cc2ff388 3 * Author: Mark Gottscho
mgottscho 0:8d34cc2ff388 4 * mgottscho@ucla.edu
mgottscho 0:8d34cc2ff388 5 */
mgottscho 0:8d34cc2ff388 6
mgottscho 0:8d34cc2ff388 7 #include "mbed.h"
mgottscho 0:8d34cc2ff388 8 #include "I2CSensor.h"
mgottscho 0:8d34cc2ff388 9 #include "PeriodicSensor.h"
mgottscho 0:8d34cc2ff388 10 #include "MAG3110.h"
mgottscho 0:8d34cc2ff388 11
mgottscho 0:8d34cc2ff388 12 using namespace std;
mgottscho 0:8d34cc2ff388 13
mgottscho 0:8d34cc2ff388 14 MAG3110::MAG3110(PinName sda, PinName scl, int i2c_addr) :
mgottscho 0:8d34cc2ff388 15 I2CSensor(sda, scl, i2c_addr),
mgottscho 0:8d34cc2ff388 16 PeriodicSensor(0.05), //default max sampling rate of 20Hz
mgottscho 0:8d34cc2ff388 17 __x(0),
mgottscho 0:8d34cc2ff388 18 __y(0),
mgottscho 0:8d34cc2ff388 19 __z(0),
mgottscho 0:8d34cc2ff388 20 __active(false),
mgottscho 0:8d34cc2ff388 21 __adc_rate(adc_smpl_rate_t(0)),
mgottscho 0:8d34cc2ff388 22 __ratio(oversmpl_ratio_t(0)),
mgottscho 0:8d34cc2ff388 23 __rate(smpl_rate_t(0))
mgottscho 0:8d34cc2ff388 24 {
mgottscho 0:8d34cc2ff388 25 }
mgottscho 0:8d34cc2ff388 26
mgottscho 0:8d34cc2ff388 27 MAG3110::~MAG3110() {}
mgottscho 0:8d34cc2ff388 28
mgottscho 0:8d34cc2ff388 29 void MAG3110::selfInit() {
mgottscho 0:8d34cc2ff388 30 __i2c.frequency(400000);
mgottscho 0:8d34cc2ff388 31 setOutputSamplingParameters(HZ80, O16, NULL);
mgottscho 0:8d34cc2ff388 32
mgottscho 0:8d34cc2ff388 33 //Enable auto magnetic sensor reset before each sample, as recommended in the datasheet
mgottscho 0:8d34cc2ff388 34 uint8_t data = getRegister(CTRL_REG2);
mgottscho 0:8d34cc2ff388 35 data |= CTRL_REG2_AUTO_MRST_EN_MASK; //Set the AUTO_MRST_EN bit
mgottscho 0:8d34cc2ff388 36 setRegister(CTRL_REG2, data);
mgottscho 0:8d34cc2ff388 37 }
mgottscho 0:8d34cc2ff388 38
mgottscho 0:8d34cc2ff388 39 uint8_t MAG3110::whoAmI() {
mgottscho 0:8d34cc2ff388 40 return getRegister(WHO_AM_I);
mgottscho 0:8d34cc2ff388 41 }
mgottscho 0:8d34cc2ff388 42
mgottscho 0:8d34cc2ff388 43 uint8_t MAG3110::getDataRegisterStatus() {
mgottscho 0:8d34cc2ff388 44 return getRegister(DR_STATUS);
mgottscho 0:8d34cc2ff388 45 }
mgottscho 0:8d34cc2ff388 46
mgottscho 0:8d34cc2ff388 47 uint8_t MAG3110::getSystemMode() {
mgottscho 0:8d34cc2ff388 48 return getRegister(SYSMOD);
mgottscho 0:8d34cc2ff388 49 }
mgottscho 0:8d34cc2ff388 50
mgottscho 0:8d34cc2ff388 51 bool MAG3110::isActive() {
mgottscho 0:8d34cc2ff388 52 return (bool) (getRegister(CTRL_REG1) & 0x01);
mgottscho 0:8d34cc2ff388 53 }
mgottscho 0:8d34cc2ff388 54
mgottscho 0:8d34cc2ff388 55 void MAG3110::setActive(bool activate) {
mgottscho 0:8d34cc2ff388 56 uint8_t data;
mgottscho 0:8d34cc2ff388 57 data = getRegister(CTRL_REG1);
mgottscho 0:8d34cc2ff388 58 if (activate)
mgottscho 0:8d34cc2ff388 59 data |= CTRL_REG1_AC_MASK; //Set bit
mgottscho 0:8d34cc2ff388 60 else
mgottscho 0:8d34cc2ff388 61 data &= ~CTRL_REG1_AC_MASK; //Clear bit
mgottscho 0:8d34cc2ff388 62 setRegister(CTRL_REG1, data);
mgottscho 0:8d34cc2ff388 63 __active = activate;
mgottscho 0:8d34cc2ff388 64 }
mgottscho 0:8d34cc2ff388 65
mgottscho 0:8d34cc2ff388 66
mgottscho 0:8d34cc2ff388 67 void MAG3110::getOutputSamplingParameters(smpl_rate_t *rate, oversmpl_ratio_t *ratio, adc_smpl_rate_t *adc_rate) {
mgottscho 0:8d34cc2ff388 68 if (rate != NULL)
mgottscho 0:8d34cc2ff388 69 *rate = __rate;
mgottscho 0:8d34cc2ff388 70 if (ratio != NULL)
mgottscho 0:8d34cc2ff388 71 *ratio = __ratio;
mgottscho 0:8d34cc2ff388 72 if (ratio != NULL)
mgottscho 0:8d34cc2ff388 73 *adc_rate = __adc_rate;
mgottscho 0:8d34cc2ff388 74 }
mgottscho 0:8d34cc2ff388 75
mgottscho 0:8d34cc2ff388 76
mgottscho 0:8d34cc2ff388 77 bool MAG3110::setOutputSamplingParameters(smpl_rate_t rate, oversmpl_ratio_t ratio, adc_smpl_rate_t *adc_rate) {
mgottscho 0:8d34cc2ff388 78 uint8_t dr;
mgottscho 0:8d34cc2ff388 79 uint8_t os;
mgottscho 0:8d34cc2ff388 80 adc_smpl_rate_t tmp_adc_rate;
mgottscho 0:8d34cc2ff388 81
mgottscho 0:8d34cc2ff388 82 switch (rate) {
mgottscho 0:8d34cc2ff388 83 default:
mgottscho 0:8d34cc2ff388 84 case HZ80:
mgottscho 0:8d34cc2ff388 85 switch (ratio) {
mgottscho 0:8d34cc2ff388 86 case O16:
mgottscho 0:8d34cc2ff388 87 tmp_adc_rate = AHZ1280;
mgottscho 0:8d34cc2ff388 88 dr = 0;
mgottscho 0:8d34cc2ff388 89 os = 0;
mgottscho 0:8d34cc2ff388 90 break;
mgottscho 0:8d34cc2ff388 91 //Other rate-ratio combinations are illegal
mgottscho 0:8d34cc2ff388 92 default:
mgottscho 0:8d34cc2ff388 93 return false;
mgottscho 0:8d34cc2ff388 94 }
mgottscho 0:8d34cc2ff388 95 break;
mgottscho 0:8d34cc2ff388 96
mgottscho 0:8d34cc2ff388 97 case HZ40:
mgottscho 0:8d34cc2ff388 98 switch (ratio) {
mgottscho 0:8d34cc2ff388 99 case O16:
mgottscho 0:8d34cc2ff388 100 tmp_adc_rate = AHZ640;
mgottscho 0:8d34cc2ff388 101 dr = 1;
mgottscho 0:8d34cc2ff388 102 os = 0;
mgottscho 0:8d34cc2ff388 103 break;
mgottscho 0:8d34cc2ff388 104 case O32:
mgottscho 0:8d34cc2ff388 105 tmp_adc_rate = AHZ1280;
mgottscho 0:8d34cc2ff388 106 dr = 0;
mgottscho 0:8d34cc2ff388 107 os = 1;
mgottscho 0:8d34cc2ff388 108 break;
mgottscho 0:8d34cc2ff388 109 //Other rate-ratio combinations are illegal
mgottscho 0:8d34cc2ff388 110 default:
mgottscho 0:8d34cc2ff388 111 return false;
mgottscho 0:8d34cc2ff388 112 }
mgottscho 0:8d34cc2ff388 113 break;
mgottscho 0:8d34cc2ff388 114
mgottscho 0:8d34cc2ff388 115 case HZ20:
mgottscho 0:8d34cc2ff388 116 switch (ratio) {
mgottscho 0:8d34cc2ff388 117 case O16:
mgottscho 0:8d34cc2ff388 118 tmp_adc_rate = AHZ320;
mgottscho 0:8d34cc2ff388 119 dr = 2;
mgottscho 0:8d34cc2ff388 120 os = 0;
mgottscho 0:8d34cc2ff388 121 break;
mgottscho 0:8d34cc2ff388 122 case O32:
mgottscho 0:8d34cc2ff388 123 tmp_adc_rate = AHZ640;
mgottscho 0:8d34cc2ff388 124 dr = 1;
mgottscho 0:8d34cc2ff388 125 os = 1;
mgottscho 0:8d34cc2ff388 126 break;
mgottscho 0:8d34cc2ff388 127 case O64:
mgottscho 0:8d34cc2ff388 128 tmp_adc_rate = AHZ1280;
mgottscho 0:8d34cc2ff388 129 dr = 0;
mgottscho 0:8d34cc2ff388 130 os = 2;
mgottscho 0:8d34cc2ff388 131 break;
mgottscho 0:8d34cc2ff388 132 //Other rate-ratio combinations are illegal
mgottscho 0:8d34cc2ff388 133 default:
mgottscho 0:8d34cc2ff388 134 return false;
mgottscho 0:8d34cc2ff388 135 }
mgottscho 0:8d34cc2ff388 136 break;
mgottscho 0:8d34cc2ff388 137
mgottscho 0:8d34cc2ff388 138 case HZ10:
mgottscho 0:8d34cc2ff388 139 switch (ratio) {
mgottscho 0:8d34cc2ff388 140 case O16:
mgottscho 0:8d34cc2ff388 141 tmp_adc_rate = AHZ160;
mgottscho 0:8d34cc2ff388 142 dr = 3;
mgottscho 0:8d34cc2ff388 143 os = 0;
mgottscho 0:8d34cc2ff388 144 break;
mgottscho 0:8d34cc2ff388 145 case O32:
mgottscho 0:8d34cc2ff388 146 tmp_adc_rate = AHZ320;
mgottscho 0:8d34cc2ff388 147 dr = 2;
mgottscho 0:8d34cc2ff388 148 os = 1;
mgottscho 0:8d34cc2ff388 149 break;
mgottscho 0:8d34cc2ff388 150 case O64:
mgottscho 0:8d34cc2ff388 151 tmp_adc_rate = AHZ640;
mgottscho 0:8d34cc2ff388 152 dr = 1;
mgottscho 0:8d34cc2ff388 153 os = 2;
mgottscho 0:8d34cc2ff388 154 break;
mgottscho 0:8d34cc2ff388 155 case O128:
mgottscho 0:8d34cc2ff388 156 tmp_adc_rate = AHZ1280;
mgottscho 0:8d34cc2ff388 157 dr = 0;
mgottscho 0:8d34cc2ff388 158 os = 3;
mgottscho 0:8d34cc2ff388 159 break;
mgottscho 0:8d34cc2ff388 160 //This should be impossible
mgottscho 0:8d34cc2ff388 161 default:
mgottscho 0:8d34cc2ff388 162 return false;
mgottscho 0:8d34cc2ff388 163 }
mgottscho 0:8d34cc2ff388 164 break;
mgottscho 0:8d34cc2ff388 165
mgottscho 0:8d34cc2ff388 166 case HZ5:
mgottscho 0:8d34cc2ff388 167 switch (ratio) {
mgottscho 0:8d34cc2ff388 168 case O16:
mgottscho 0:8d34cc2ff388 169 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 170 dr = 4;
mgottscho 0:8d34cc2ff388 171 os = 0;
mgottscho 0:8d34cc2ff388 172 break;
mgottscho 0:8d34cc2ff388 173 case O32:
mgottscho 0:8d34cc2ff388 174 tmp_adc_rate = AHZ160;
mgottscho 0:8d34cc2ff388 175 dr = 3;
mgottscho 0:8d34cc2ff388 176 os = 1;
mgottscho 0:8d34cc2ff388 177 break;
mgottscho 0:8d34cc2ff388 178 case O64:
mgottscho 0:8d34cc2ff388 179 tmp_adc_rate = AHZ320;
mgottscho 0:8d34cc2ff388 180 dr = 2;
mgottscho 0:8d34cc2ff388 181 os = 2;
mgottscho 0:8d34cc2ff388 182 break;
mgottscho 0:8d34cc2ff388 183 case O128:
mgottscho 0:8d34cc2ff388 184 tmp_adc_rate = AHZ640;
mgottscho 0:8d34cc2ff388 185 dr = 1;
mgottscho 0:8d34cc2ff388 186 os = 3;
mgottscho 0:8d34cc2ff388 187 break;
mgottscho 0:8d34cc2ff388 188 //This should be impossible
mgottscho 0:8d34cc2ff388 189 default:
mgottscho 0:8d34cc2ff388 190 return false;
mgottscho 0:8d34cc2ff388 191 }
mgottscho 0:8d34cc2ff388 192 break;
mgottscho 0:8d34cc2ff388 193
mgottscho 0:8d34cc2ff388 194 case HZ2_5:
mgottscho 0:8d34cc2ff388 195 switch (ratio) {
mgottscho 0:8d34cc2ff388 196 case O16:
mgottscho 0:8d34cc2ff388 197 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 198 dr = 5;
mgottscho 0:8d34cc2ff388 199 os = 0;
mgottscho 0:8d34cc2ff388 200 break;
mgottscho 0:8d34cc2ff388 201 case O32:
mgottscho 0:8d34cc2ff388 202 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 203 dr = 4;
mgottscho 0:8d34cc2ff388 204 os = 1;
mgottscho 0:8d34cc2ff388 205 break;
mgottscho 0:8d34cc2ff388 206 case O64:
mgottscho 0:8d34cc2ff388 207 tmp_adc_rate = AHZ160;
mgottscho 0:8d34cc2ff388 208 dr = 3;
mgottscho 0:8d34cc2ff388 209 os = 2;
mgottscho 0:8d34cc2ff388 210 break;
mgottscho 0:8d34cc2ff388 211 case O128:
mgottscho 0:8d34cc2ff388 212 tmp_adc_rate = AHZ320;
mgottscho 0:8d34cc2ff388 213 dr = 2;
mgottscho 0:8d34cc2ff388 214 os = 3;
mgottscho 0:8d34cc2ff388 215 break;
mgottscho 0:8d34cc2ff388 216 //This should be impossible
mgottscho 0:8d34cc2ff388 217 default:
mgottscho 0:8d34cc2ff388 218 return false;
mgottscho 0:8d34cc2ff388 219 }
mgottscho 0:8d34cc2ff388 220 break;
mgottscho 0:8d34cc2ff388 221
mgottscho 0:8d34cc2ff388 222 case HZ1_25:
mgottscho 0:8d34cc2ff388 223 switch (ratio) {
mgottscho 0:8d34cc2ff388 224 case O16:
mgottscho 0:8d34cc2ff388 225 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 226 dr = 6;
mgottscho 0:8d34cc2ff388 227 os = 0;
mgottscho 0:8d34cc2ff388 228 break;
mgottscho 0:8d34cc2ff388 229 case O32:
mgottscho 0:8d34cc2ff388 230 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 231 dr = 5;
mgottscho 0:8d34cc2ff388 232 os = 1;
mgottscho 0:8d34cc2ff388 233 break;
mgottscho 0:8d34cc2ff388 234 case O64:
mgottscho 0:8d34cc2ff388 235 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 236 dr = 4;
mgottscho 0:8d34cc2ff388 237 os = 2;
mgottscho 0:8d34cc2ff388 238 break;
mgottscho 0:8d34cc2ff388 239 case O128:
mgottscho 0:8d34cc2ff388 240 tmp_adc_rate = AHZ160;
mgottscho 0:8d34cc2ff388 241 dr = 3;
mgottscho 0:8d34cc2ff388 242 os = 3;
mgottscho 0:8d34cc2ff388 243 break;
mgottscho 0:8d34cc2ff388 244 //This should be impossible
mgottscho 0:8d34cc2ff388 245 default:
mgottscho 0:8d34cc2ff388 246 return false;
mgottscho 0:8d34cc2ff388 247 }
mgottscho 0:8d34cc2ff388 248 break;
mgottscho 0:8d34cc2ff388 249
mgottscho 0:8d34cc2ff388 250 case HZ0_63:
mgottscho 0:8d34cc2ff388 251 switch (ratio) {
mgottscho 0:8d34cc2ff388 252 case O16:
mgottscho 0:8d34cc2ff388 253 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 254 dr = 7;
mgottscho 0:8d34cc2ff388 255 os = 0;
mgottscho 0:8d34cc2ff388 256 break;
mgottscho 0:8d34cc2ff388 257 case O32:
mgottscho 0:8d34cc2ff388 258 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 259 dr = 6;
mgottscho 0:8d34cc2ff388 260 os = 1;
mgottscho 0:8d34cc2ff388 261 break;
mgottscho 0:8d34cc2ff388 262 case O64:
mgottscho 0:8d34cc2ff388 263 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 264 dr = 5;
mgottscho 0:8d34cc2ff388 265 os = 2;
mgottscho 0:8d34cc2ff388 266 break;
mgottscho 0:8d34cc2ff388 267 case O128:
mgottscho 0:8d34cc2ff388 268 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 269 dr = 4;
mgottscho 0:8d34cc2ff388 270 os = 3;
mgottscho 0:8d34cc2ff388 271 break;
mgottscho 0:8d34cc2ff388 272 //This should be impossible
mgottscho 0:8d34cc2ff388 273 default:
mgottscho 0:8d34cc2ff388 274 return false;
mgottscho 0:8d34cc2ff388 275 }
mgottscho 0:8d34cc2ff388 276 break;
mgottscho 0:8d34cc2ff388 277
mgottscho 0:8d34cc2ff388 278 case HZ0_31:
mgottscho 0:8d34cc2ff388 279 switch (ratio) {
mgottscho 0:8d34cc2ff388 280 case O32:
mgottscho 0:8d34cc2ff388 281 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 282 dr = 7;
mgottscho 0:8d34cc2ff388 283 os = 1;
mgottscho 0:8d34cc2ff388 284 break;
mgottscho 0:8d34cc2ff388 285 case O64:
mgottscho 0:8d34cc2ff388 286 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 287 dr = 6;
mgottscho 0:8d34cc2ff388 288 os = 2;
mgottscho 0:8d34cc2ff388 289 break;
mgottscho 0:8d34cc2ff388 290 case O128:
mgottscho 0:8d34cc2ff388 291 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 292 dr = 5;
mgottscho 0:8d34cc2ff388 293 os = 3;
mgottscho 0:8d34cc2ff388 294 break;
mgottscho 0:8d34cc2ff388 295 default:
mgottscho 0:8d34cc2ff388 296 return false;
mgottscho 0:8d34cc2ff388 297 }
mgottscho 0:8d34cc2ff388 298 break;
mgottscho 0:8d34cc2ff388 299
mgottscho 0:8d34cc2ff388 300 case HZ0_16:
mgottscho 0:8d34cc2ff388 301 switch (ratio) {
mgottscho 0:8d34cc2ff388 302 case O64:
mgottscho 0:8d34cc2ff388 303 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 304 dr = 7;
mgottscho 0:8d34cc2ff388 305 os = 2;
mgottscho 0:8d34cc2ff388 306 break;
mgottscho 0:8d34cc2ff388 307 case O128:
mgottscho 0:8d34cc2ff388 308 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 309 dr = 6;
mgottscho 0:8d34cc2ff388 310 os = 3;
mgottscho 0:8d34cc2ff388 311 break;
mgottscho 0:8d34cc2ff388 312 default:
mgottscho 0:8d34cc2ff388 313 return false;
mgottscho 0:8d34cc2ff388 314 }
mgottscho 0:8d34cc2ff388 315 break;
mgottscho 0:8d34cc2ff388 316
mgottscho 0:8d34cc2ff388 317 case HZ0_08:
mgottscho 0:8d34cc2ff388 318 switch (ratio) {
mgottscho 0:8d34cc2ff388 319 case O128:
mgottscho 0:8d34cc2ff388 320 tmp_adc_rate = AHZ80;
mgottscho 0:8d34cc2ff388 321 dr = 7;
mgottscho 0:8d34cc2ff388 322 os = 3;
mgottscho 0:8d34cc2ff388 323 break;
mgottscho 0:8d34cc2ff388 324 default:
mgottscho 0:8d34cc2ff388 325 return false;
mgottscho 0:8d34cc2ff388 326 }
mgottscho 0:8d34cc2ff388 327 break;
mgottscho 0:8d34cc2ff388 328 }
mgottscho 0:8d34cc2ff388 329
mgottscho 0:8d34cc2ff388 330 //Deactivate to update register
mgottscho 0:8d34cc2ff388 331 bool wasActive = __active;
mgottscho 0:8d34cc2ff388 332 setActive(false);
mgottscho 0:8d34cc2ff388 333
mgottscho 0:8d34cc2ff388 334 //Update value for the caller
mgottscho 0:8d34cc2ff388 335 if (adc_rate != NULL)
mgottscho 0:8d34cc2ff388 336 *adc_rate = tmp_adc_rate;
mgottscho 0:8d34cc2ff388 337
mgottscho 0:8d34cc2ff388 338 //Update CTRL_REG1 DR and OS fields
mgottscho 0:8d34cc2ff388 339 uint8_t data = getRegister(CTRL_REG1);
mgottscho 0:8d34cc2ff388 340 uint8_t dr_os = (dr << 5) | (os << 3); //Set DR in 3 MSB, OS in next 2 bits. 3 LSB are 0
mgottscho 0:8d34cc2ff388 341 data = (data & ~(CTRL_REG1_DR_MASK | CTRL_REG1_OS_MASK)) | ((CTRL_REG1_DR_MASK | CTRL_REG1_OS_MASK) & dr_os); //Update 5 MSB
mgottscho 0:8d34cc2ff388 342 setRegister(CTRL_REG1, data);
mgottscho 0:8d34cc2ff388 343
mgottscho 0:8d34cc2ff388 344 //Update cached values
mgottscho 0:8d34cc2ff388 345 __adc_rate = tmp_adc_rate;
mgottscho 0:8d34cc2ff388 346 __ratio = ratio;
mgottscho 0:8d34cc2ff388 347 __rate = rate;
mgottscho 0:8d34cc2ff388 348
mgottscho 0:8d34cc2ff388 349 if (wasActive)
mgottscho 0:8d34cc2ff388 350 setActive(true);
mgottscho 0:8d34cc2ff388 351
mgottscho 0:8d34cc2ff388 352 return true;
mgottscho 0:8d34cc2ff388 353 }
mgottscho 0:8d34cc2ff388 354
mgottscho 0:8d34cc2ff388 355
mgottscho 0:8d34cc2ff388 356
mgottscho 0:8d34cc2ff388 357 int16_t MAG3110::getX(bool sampleNow) {
mgottscho 0:8d34cc2ff388 358 __disable_irq();
mgottscho 0:8d34cc2ff388 359 if (sampleNow) {
mgottscho 0:8d34cc2ff388 360 uint8_t data_msb, data_lsb;
mgottscho 0:8d34cc2ff388 361 data_msb = getRegister(OUT_X_MSB);
mgottscho 0:8d34cc2ff388 362 data_lsb = getRegister(OUT_X_LSB);
mgottscho 0:8d34cc2ff388 363 __x = data_msb << 8;
mgottscho 0:8d34cc2ff388 364 __x |= data_lsb;
mgottscho 0:8d34cc2ff388 365 }
mgottscho 0:8d34cc2ff388 366
mgottscho 0:8d34cc2ff388 367 __dataReady = false;
mgottscho 0:8d34cc2ff388 368 __enable_irq();
mgottscho 0:8d34cc2ff388 369
mgottscho 0:8d34cc2ff388 370 return __x;
mgottscho 0:8d34cc2ff388 371 }
mgottscho 0:8d34cc2ff388 372
mgottscho 0:8d34cc2ff388 373 int16_t MAG3110::getY(bool sampleNow) {
mgottscho 0:8d34cc2ff388 374 __disable_irq();
mgottscho 0:8d34cc2ff388 375 if (sampleNow) {
mgottscho 0:8d34cc2ff388 376 uint8_t data_msb, data_lsb;
mgottscho 0:8d34cc2ff388 377 data_msb = getRegister(OUT_Y_MSB);
mgottscho 0:8d34cc2ff388 378 data_lsb = getRegister(OUT_Y_LSB);
mgottscho 0:8d34cc2ff388 379 __y = data_msb << 8;
mgottscho 0:8d34cc2ff388 380 __y |= data_lsb;
mgottscho 0:8d34cc2ff388 381 }
mgottscho 0:8d34cc2ff388 382
mgottscho 0:8d34cc2ff388 383 __dataReady = false;
mgottscho 0:8d34cc2ff388 384 __enable_irq();
mgottscho 0:8d34cc2ff388 385
mgottscho 0:8d34cc2ff388 386 return __y;
mgottscho 0:8d34cc2ff388 387 }
mgottscho 0:8d34cc2ff388 388
mgottscho 0:8d34cc2ff388 389 int16_t MAG3110::getZ(bool sampleNow) {
mgottscho 0:8d34cc2ff388 390 __disable_irq();
mgottscho 0:8d34cc2ff388 391 if (sampleNow) {
mgottscho 0:8d34cc2ff388 392 uint8_t data_msb, data_lsb;
mgottscho 0:8d34cc2ff388 393 data_msb = getRegister(OUT_Z_MSB);
mgottscho 0:8d34cc2ff388 394 data_lsb = getRegister(OUT_Z_LSB);
mgottscho 0:8d34cc2ff388 395 __z = data_msb << 8;
mgottscho 0:8d34cc2ff388 396 __z |= data_lsb;
mgottscho 0:8d34cc2ff388 397 }
mgottscho 0:8d34cc2ff388 398
mgottscho 0:8d34cc2ff388 399 __dataReady = false;
mgottscho 0:8d34cc2ff388 400 __enable_irq();
mgottscho 0:8d34cc2ff388 401
mgottscho 0:8d34cc2ff388 402 return __z;
mgottscho 0:8d34cc2ff388 403 }
mgottscho 0:8d34cc2ff388 404
mgottscho 0:8d34cc2ff388 405 float MAG3110::getFloatX(bool sampleNow) {
mgottscho 0:8d34cc2ff388 406 return getX(sampleNow) * DATA_CONVERSION;
mgottscho 0:8d34cc2ff388 407 }
mgottscho 0:8d34cc2ff388 408
mgottscho 0:8d34cc2ff388 409 float MAG3110::getFloatY(bool sampleNow) {
mgottscho 0:8d34cc2ff388 410 return getY(sampleNow) * DATA_CONVERSION;
mgottscho 0:8d34cc2ff388 411 }
mgottscho 0:8d34cc2ff388 412
mgottscho 0:8d34cc2ff388 413 float MAG3110::getFloatZ(bool sampleNow) {
mgottscho 0:8d34cc2ff388 414 return getZ(sampleNow) * DATA_CONVERSION;
mgottscho 0:8d34cc2ff388 415 }
mgottscho 0:8d34cc2ff388 416
mgottscho 0:8d34cc2ff388 417 int8_t MAG3110::getDieTemp() {
mgottscho 0:8d34cc2ff388 418 return (int8_t) getRegister(DIE_TEMP);
mgottscho 0:8d34cc2ff388 419 }
mgottscho 0:8d34cc2ff388 420
mgottscho 0:8d34cc2ff388 421 float MAG3110::getFloatDieTemp() {
mgottscho 0:8d34cc2ff388 422 return getDieTemp() * TEMP_DIV;
mgottscho 0:8d34cc2ff388 423 }
mgottscho 0:8d34cc2ff388 424
mgottscho 0:8d34cc2ff388 425 void MAG3110::__sample_data_ISR() {
mgottscho 0:8d34cc2ff388 426 getX(true);
mgottscho 0:8d34cc2ff388 427 getY(true);
mgottscho 0:8d34cc2ff388 428 getZ(true);
mgottscho 0:8d34cc2ff388 429 __dataReady = true;
mgottscho 0:8d34cc2ff388 430 }