Implementation of 1-Wire with added Alarm Search Functionality
Dependents: Max32630_One_Wire_Interface
Masters/TARGET_Maxim/TARGET_MAX32600/TOOLCHAIN_IAR/owlink.s@138:5bd0a7a82bb4, 2016-12-02 (annotated)
- Committer:
- j3
- Date:
- Fri Dec 02 19:21:55 2016 +0000
- Revision:
- 138:5bd0a7a82bb4
- Child:
- 139:f0e0a7976846
Updated project tree under Masters to add TARGET and TOOLCHAIN folders for new build tools to support asm code needed by OwGpio class.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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j3 | 138:5bd0a7a82bb4 | 1 | /******************************************************************//** |
j3 | 138:5bd0a7a82bb4 | 2 | * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved. |
j3 | 138:5bd0a7a82bb4 | 3 | * |
j3 | 138:5bd0a7a82bb4 | 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
j3 | 138:5bd0a7a82bb4 | 5 | * copy of this software and associated documentation files (the "Software"), |
j3 | 138:5bd0a7a82bb4 | 6 | * to deal in the Software without restriction, including without limitation |
j3 | 138:5bd0a7a82bb4 | 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
j3 | 138:5bd0a7a82bb4 | 8 | * and/or sell copies of the Software, and to permit persons to whom the |
j3 | 138:5bd0a7a82bb4 | 9 | * Software is furnished to do so, subject to the following conditions: |
j3 | 138:5bd0a7a82bb4 | 10 | * |
j3 | 138:5bd0a7a82bb4 | 11 | * The above copyright notice and this permission notice shall be included |
j3 | 138:5bd0a7a82bb4 | 12 | * in all copies or substantial portions of the Software. |
j3 | 138:5bd0a7a82bb4 | 13 | * |
j3 | 138:5bd0a7a82bb4 | 14 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS |
j3 | 138:5bd0a7a82bb4 | 15 | * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
j3 | 138:5bd0a7a82bb4 | 16 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. |
j3 | 138:5bd0a7a82bb4 | 17 | * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES |
j3 | 138:5bd0a7a82bb4 | 18 | * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, |
j3 | 138:5bd0a7a82bb4 | 19 | * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR |
j3 | 138:5bd0a7a82bb4 | 20 | * OTHER DEALINGS IN THE SOFTWARE. |
j3 | 138:5bd0a7a82bb4 | 21 | * |
j3 | 138:5bd0a7a82bb4 | 22 | * Except as contained in this notice, the name of Maxim Integrated |
j3 | 138:5bd0a7a82bb4 | 23 | * Products, Inc. shall not be used except as stated in the Maxim Integrated |
j3 | 138:5bd0a7a82bb4 | 24 | * Products, Inc. Branding Policy. |
j3 | 138:5bd0a7a82bb4 | 25 | * |
j3 | 138:5bd0a7a82bb4 | 26 | * The mere transfer of this software does not imply any licenses |
j3 | 138:5bd0a7a82bb4 | 27 | * of trade secrets, proprietary technology, copyrights, patents, |
j3 | 138:5bd0a7a82bb4 | 28 | * trademarks, maskwork rights, or any other form of intellectual |
j3 | 138:5bd0a7a82bb4 | 29 | * property whatsoever. Maxim Integrated Products, Inc. retains all |
j3 | 138:5bd0a7a82bb4 | 30 | * ownership rights. |
j3 | 138:5bd0a7a82bb4 | 31 | **********************************************************************/ |
j3 | 138:5bd0a7a82bb4 | 32 | |
j3 | 138:5bd0a7a82bb4 | 33 | // ow_usdelay configuration |
j3 | 138:5bd0a7a82bb4 | 34 | #define PROC_CLOCK_MHZ (__SYSTEM_HFX / 1000000) // Processor clock in MHz |
j3 | 138:5bd0a7a82bb4 | 35 | #define OVERHEAD_TUNING 18 // Fraction where OverheadTime(us) = OVERHEAD_TUNING / PROC_CLOCK_MHZ |
j3 | 138:5bd0a7a82bb4 | 36 | // Make PROC_CLOCK_MHZ and OVERHEAD_TUNING divisible by PROC_CYCLES_PER_LOOP for best results |
j3 | 138:5bd0a7a82bb4 | 37 | |
j3 | 138:5bd0a7a82bb4 | 38 | // ow_usdelay constants |
j3 | 138:5bd0a7a82bb4 | 39 | #define PIPELINE_REFILL_PROC_CYCLES 1 // ARM specifies 1-3 cycles for pipeline refill following a branch |
j3 | 138:5bd0a7a82bb4 | 40 | #define PROC_CYCLES_PER_LOOP (2 + PIPELINE_REFILL_PROC_CYCLES) |
j3 | 138:5bd0a7a82bb4 | 41 | #define LOOPS_PER_US (PROC_CLOCK_MHZ / PROC_CYCLES_PER_LOOP) // Number of loop passes for a 1 us delay |
j3 | 138:5bd0a7a82bb4 | 42 | #define LOOPS_REMOVED_TUNING (OVERHEAD_TUNING / PROC_CYCLES_PER_LOOP) |
j3 | 138:5bd0a7a82bb4 | 43 | |
j3 | 138:5bd0a7a82bb4 | 44 | // OwTiming offsets |
j3 | 138:5bd0a7a82bb4 | 45 | #define tRSTL_OFFSET 0 |
j3 | 138:5bd0a7a82bb4 | 46 | #define tMSP_OFFSET 2 |
j3 | 138:5bd0a7a82bb4 | 47 | #define tW0L_OFFSET 4 |
j3 | 138:5bd0a7a82bb4 | 48 | #define tW1L_OFFSET 6 |
j3 | 138:5bd0a7a82bb4 | 49 | #define tMSR_OFFSET 8 |
j3 | 138:5bd0a7a82bb4 | 50 | #define tSLOT_OFFSET 10 |
j3 | 138:5bd0a7a82bb4 | 51 | |
j3 | 138:5bd0a7a82bb4 | 52 | // Define a code section |
j3 | 138:5bd0a7a82bb4 | 53 | SECTION owlink : CODE |
j3 | 138:5bd0a7a82bb4 | 54 | |
j3 | 138:5bd0a7a82bb4 | 55 | // void ow_usdelay(unsigned int time_us) |
j3 | 138:5bd0a7a82bb4 | 56 | EXPORT ow_usdelay |
j3 | 138:5bd0a7a82bb4 | 57 | ow_usdelay |
j3 | 138:5bd0a7a82bb4 | 58 | cmp R0, #0 // Return if time_us equals zero |
j3 | 138:5bd0a7a82bb4 | 59 | beq ow_usdelay_return |
j3 | 138:5bd0a7a82bb4 | 60 | mov R2, #LOOPS_PER_US |
j3 | 138:5bd0a7a82bb4 | 61 | mul R0, R0, R2 |
j3 | 138:5bd0a7a82bb4 | 62 | sub R0, R0, #LOOPS_REMOVED_TUNING |
j3 | 138:5bd0a7a82bb4 | 63 | loop |
j3 | 138:5bd0a7a82bb4 | 64 | subs R0, R0, #1 |
j3 | 138:5bd0a7a82bb4 | 65 | bne loop |
j3 | 138:5bd0a7a82bb4 | 66 | ow_usdelay_return |
j3 | 138:5bd0a7a82bb4 | 67 | bx R14 |
j3 | 138:5bd0a7a82bb4 | 68 | |
j3 | 138:5bd0a7a82bb4 | 69 | // static void write_ow_gpio_low(unsigned int * portReg, unsigned int pinMask) |
j3 | 138:5bd0a7a82bb4 | 70 | write_ow_gpio_low MACRO |
j3 | 138:5bd0a7a82bb4 | 71 | ldr R2, [R0] |
j3 | 138:5bd0a7a82bb4 | 72 | bic R2, R2, R1 |
j3 | 138:5bd0a7a82bb4 | 73 | str R2, [R0] |
j3 | 138:5bd0a7a82bb4 | 74 | ENDM |
j3 | 138:5bd0a7a82bb4 | 75 | |
j3 | 138:5bd0a7a82bb4 | 76 | // static void write_ow_gpio_high(unsigned int * portReg, unsigned int pinMask) |
j3 | 138:5bd0a7a82bb4 | 77 | write_ow_gpio_high MACRO |
j3 | 138:5bd0a7a82bb4 | 78 | ldr R2, [R0] |
j3 | 138:5bd0a7a82bb4 | 79 | orr R2, R2, R1 |
j3 | 138:5bd0a7a82bb4 | 80 | str R2, [R0] |
j3 | 138:5bd0a7a82bb4 | 81 | ENDM |
j3 | 138:5bd0a7a82bb4 | 82 | |
j3 | 138:5bd0a7a82bb4 | 83 | // void ow_bit(uint8_t * sendrecvbit, volatile uint32_t * inPortReg, volatile uint32_t * outPortReg, unsigned int pinMask, const OwTiming * timing) |
j3 | 138:5bd0a7a82bb4 | 84 | EXPORT ow_bit |
j3 | 138:5bd0a7a82bb4 | 85 | ow_bit |
j3 | 138:5bd0a7a82bb4 | 86 | push {R4-R8, R14} |
j3 | 138:5bd0a7a82bb4 | 87 | // Retrive extra parameters from stack |
j3 | 138:5bd0a7a82bb4 | 88 | add R6, SP, #24 // Find beginning of stack: 6 scratch registers * 4 bytes each |
j3 | 138:5bd0a7a82bb4 | 89 | ldr R6, [R6] // Load timing struct |
j3 | 138:5bd0a7a82bb4 | 90 | ldrh R4, [R6, #tSLOT_OFFSET] |
j3 | 138:5bd0a7a82bb4 | 91 | ldrh R5, [R6, #tMSR_OFFSET] |
j3 | 138:5bd0a7a82bb4 | 92 | // R0: sendrecvbit |
j3 | 138:5bd0a7a82bb4 | 93 | // R1: inPortReg |
j3 | 138:5bd0a7a82bb4 | 94 | // R2: outPortReg |
j3 | 138:5bd0a7a82bb4 | 95 | // R3: pinMask |
j3 | 138:5bd0a7a82bb4 | 96 | // R4: tSLOT |
j3 | 138:5bd0a7a82bb4 | 97 | // R5: tMSR |
j3 | 138:5bd0a7a82bb4 | 98 | // R6: timing |
j3 | 138:5bd0a7a82bb4 | 99 | // R7: Scratch |
j3 | 138:5bd0a7a82bb4 | 100 | // R8: Scratch |
j3 | 138:5bd0a7a82bb4 | 101 | // R14: Scratch |
j3 | 138:5bd0a7a82bb4 | 102 | |
j3 | 138:5bd0a7a82bb4 | 103 | // Reorganize registers for upcoming function calls |
j3 | 138:5bd0a7a82bb4 | 104 | mov R8, R1 // inPortReg to R8 |
j3 | 138:5bd0a7a82bb4 | 105 | mov R7, R2 // outPortReg to R7 |
j3 | 138:5bd0a7a82bb4 | 106 | mov R1, R3 // pinMask to R1 |
j3 | 138:5bd0a7a82bb4 | 107 | mov R3, R0 // sendrecvbit to R3 |
j3 | 138:5bd0a7a82bb4 | 108 | // R0: Scratch |
j3 | 138:5bd0a7a82bb4 | 109 | // R1: pinMask |
j3 | 138:5bd0a7a82bb4 | 110 | // R2: Scratch |
j3 | 138:5bd0a7a82bb4 | 111 | // R3: sendrecvbit |
j3 | 138:5bd0a7a82bb4 | 112 | // R4: tSLOT |
j3 | 138:5bd0a7a82bb4 | 113 | // R5: tMSR |
j3 | 138:5bd0a7a82bb4 | 114 | // R6: timing |
j3 | 138:5bd0a7a82bb4 | 115 | // R7: outPortReg |
j3 | 138:5bd0a7a82bb4 | 116 | // R8: inPortReg |
j3 | 138:5bd0a7a82bb4 | 117 | // R14: Scratch |
j3 | 138:5bd0a7a82bb4 | 118 | |
j3 | 138:5bd0a7a82bb4 | 119 | // if (*sendrecvbit & 1) |
j3 | 138:5bd0a7a82bb4 | 120 | ldrb R14, [R3] |
j3 | 138:5bd0a7a82bb4 | 121 | tst R14, #1 |
j3 | 138:5bd0a7a82bb4 | 122 | beq write_zero |
j3 | 138:5bd0a7a82bb4 | 123 | ldrh R6, [R6, #tW1L_OFFSET] // tW1L |
j3 | 138:5bd0a7a82bb4 | 124 | sub R4, R4, R5 // tREC = tSLOT - tMSR |
j3 | 138:5bd0a7a82bb4 | 125 | sub R5, R5, R6 // delay2 = tMSR - tLW1L |
j3 | 138:5bd0a7a82bb4 | 126 | // R0: Scratch |
j3 | 138:5bd0a7a82bb4 | 127 | // R1: pinMask |
j3 | 138:5bd0a7a82bb4 | 128 | // R2: Scratch |
j3 | 138:5bd0a7a82bb4 | 129 | // R3: sendrecvbit |
j3 | 138:5bd0a7a82bb4 | 130 | // R4: tREC |
j3 | 138:5bd0a7a82bb4 | 131 | // R5: delay2 |
j3 | 138:5bd0a7a82bb4 | 132 | // R6: tW1L |
j3 | 138:5bd0a7a82bb4 | 133 | // R7: outPortReg |
j3 | 138:5bd0a7a82bb4 | 134 | // R8: inPortReg |
j3 | 138:5bd0a7a82bb4 | 135 | // R14: Scratch |
j3 | 138:5bd0a7a82bb4 | 136 | mov R0, R7 // outPortReg |
j3 | 138:5bd0a7a82bb4 | 137 | write_ow_gpio_low // Pull low |
j3 | 138:5bd0a7a82bb4 | 138 | mov R0, R6 // tLOW |
j3 | 138:5bd0a7a82bb4 | 139 | bl ow_usdelay // Delay for tLOW |
j3 | 138:5bd0a7a82bb4 | 140 | mov R0, R7 // outPortReg |
j3 | 138:5bd0a7a82bb4 | 141 | write_ow_gpio_high // Release pin |
j3 | 138:5bd0a7a82bb4 | 142 | mov R0, R5 // delay2 |
j3 | 138:5bd0a7a82bb4 | 143 | bl ow_usdelay // Delay for sample time |
j3 | 138:5bd0a7a82bb4 | 144 | ldr R5, [R8] // Read *inPortReg |
j3 | 138:5bd0a7a82bb4 | 145 | b recovery_delay |
j3 | 138:5bd0a7a82bb4 | 146 | // else |
j3 | 138:5bd0a7a82bb4 | 147 | write_zero |
j3 | 138:5bd0a7a82bb4 | 148 | ldrh R6, [R6, #tW0L_OFFSET] // tW0L |
j3 | 138:5bd0a7a82bb4 | 149 | sub R4, R4, R6 // tREC = tSLOT - tLW0L |
j3 | 138:5bd0a7a82bb4 | 150 | sub R6, R6, R5 // delay2 = tW0L - tMSR |
j3 | 138:5bd0a7a82bb4 | 151 | // R0: Scratch |
j3 | 138:5bd0a7a82bb4 | 152 | // R1: pinMask |
j3 | 138:5bd0a7a82bb4 | 153 | // R2: Scratch |
j3 | 138:5bd0a7a82bb4 | 154 | // R3: sendrecvbit |
j3 | 138:5bd0a7a82bb4 | 155 | // R4: tREC |
j3 | 138:5bd0a7a82bb4 | 156 | // R5: tMSR |
j3 | 138:5bd0a7a82bb4 | 157 | // R6: delay2 |
j3 | 138:5bd0a7a82bb4 | 158 | // R7: outPortReg |
j3 | 138:5bd0a7a82bb4 | 159 | // R8: inPortReg |
j3 | 138:5bd0a7a82bb4 | 160 | // R14: Scratch |
j3 | 138:5bd0a7a82bb4 | 161 | mov R0, R7 // outPortReg |
j3 | 138:5bd0a7a82bb4 | 162 | write_ow_gpio_low // Pull low |
j3 | 138:5bd0a7a82bb4 | 163 | mov R0, R5 // tMSR |
j3 | 138:5bd0a7a82bb4 | 164 | bl ow_usdelay // Delay for tMSR |
j3 | 138:5bd0a7a82bb4 | 165 | ldr R5, [R8] // Read *inPortReg |
j3 | 138:5bd0a7a82bb4 | 166 | mov R0, R6 // delay2 |
j3 | 138:5bd0a7a82bb4 | 167 | bl ow_usdelay // Delay for release |
j3 | 138:5bd0a7a82bb4 | 168 | mov R0, R7 // outPortReg |
j3 | 138:5bd0a7a82bb4 | 169 | write_ow_gpio_high // Release pin |
j3 | 138:5bd0a7a82bb4 | 170 | // endif (*sendrecvbit & 1) |
j3 | 138:5bd0a7a82bb4 | 171 | // R0: Scratch |
j3 | 138:5bd0a7a82bb4 | 172 | // R1: pinMask |
j3 | 138:5bd0a7a82bb4 | 173 | // R2: Scratch |
j3 | 138:5bd0a7a82bb4 | 174 | // R3: sendrecvbit |
j3 | 138:5bd0a7a82bb4 | 175 | // R4: tREC |
j3 | 138:5bd0a7a82bb4 | 176 | // R5: *inPortReg |
j3 | 138:5bd0a7a82bb4 | 177 | // R6: Scratch |
j3 | 138:5bd0a7a82bb4 | 178 | // R7: outPortReg |
j3 | 138:5bd0a7a82bb4 | 179 | // R8: inPortReg |
j3 | 138:5bd0a7a82bb4 | 180 | // R14: Scratch |
j3 | 138:5bd0a7a82bb4 | 181 | |
j3 | 138:5bd0a7a82bb4 | 182 | recovery_delay |
j3 | 138:5bd0a7a82bb4 | 183 | mov R0, R4 |
j3 | 138:5bd0a7a82bb4 | 184 | bl ow_usdelay // Delay for tREC |
j3 | 138:5bd0a7a82bb4 | 185 | |
j3 | 138:5bd0a7a82bb4 | 186 | // Parse received bit |
j3 | 138:5bd0a7a82bb4 | 187 | // *sendrecvbit = ((*inPortReg & pinMask) == pinMask) |
j3 | 138:5bd0a7a82bb4 | 188 | and R5, R5, R1 |
j3 | 138:5bd0a7a82bb4 | 189 | cmp R5, R1 |
j3 | 138:5bd0a7a82bb4 | 190 | ite eq |
j3 | 138:5bd0a7a82bb4 | 191 | moveq R5, #1 |
j3 | 138:5bd0a7a82bb4 | 192 | movne R5, #0 |
j3 | 138:5bd0a7a82bb4 | 193 | strb R5, [R3] |
j3 | 138:5bd0a7a82bb4 | 194 | |
j3 | 138:5bd0a7a82bb4 | 195 | pop {R4-R8, R14} |
j3 | 138:5bd0a7a82bb4 | 196 | bx R14 |
j3 | 138:5bd0a7a82bb4 | 197 | END |
j3 | 138:5bd0a7a82bb4 | 198 |