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cmsis/core_cmFunc.h@146:03e976389d16, 2017-03-16 (annotated)

Committer:
mega64
Date:
Thu Mar 16 06:15:53 2017 +0000
Revision:
146:03e976389d16
fully rebuild, now based on mbed-dev v160

Who changed what in which revision?

UserRevisionLine numberNew contents of line
mega64 146:03e976389d16 1 /**************************************************************************//**
mega64 146:03e976389d16 2 * @file core_cmFunc.h
mega64 146:03e976389d16 3 * @brief CMSIS Cortex-M Core Function Access Header File
mega64 146:03e976389d16 4 * @version V4.10
mega64 146:03e976389d16 5 * @date 18. March 2015
mega64 146:03e976389d16 6 *
mega64 146:03e976389d16 7 * @note
mega64 146:03e976389d16 8 *
mega64 146:03e976389d16 9 ******************************************************************************/
mega64 146:03e976389d16 10 /* Copyright (c) 2009 - 2015 ARM LIMITED
mega64 146:03e976389d16 11
mega64 146:03e976389d16 12 All rights reserved.
mega64 146:03e976389d16 13 Redistribution and use in source and binary forms, with or without
mega64 146:03e976389d16 14 modification, are permitted provided that the following conditions are met:
mega64 146:03e976389d16 15 - Redistributions of source code must retain the above copyright
mega64 146:03e976389d16 16 notice, this list of conditions and the following disclaimer.
mega64 146:03e976389d16 17 - Redistributions in binary form must reproduce the above copyright
mega64 146:03e976389d16 18 notice, this list of conditions and the following disclaimer in the
mega64 146:03e976389d16 19 documentation and/or other materials provided with the distribution.
mega64 146:03e976389d16 20 - Neither the name of ARM nor the names of its contributors may be used
mega64 146:03e976389d16 21 to endorse or promote products derived from this software without
mega64 146:03e976389d16 22 specific prior written permission.
mega64 146:03e976389d16 23 *
mega64 146:03e976389d16 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mega64 146:03e976389d16 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mega64 146:03e976389d16 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mega64 146:03e976389d16 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mega64 146:03e976389d16 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mega64 146:03e976389d16 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mega64 146:03e976389d16 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mega64 146:03e976389d16 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mega64 146:03e976389d16 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mega64 146:03e976389d16 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mega64 146:03e976389d16 34 POSSIBILITY OF SUCH DAMAGE.
mega64 146:03e976389d16 35 ---------------------------------------------------------------------------*/
mega64 146:03e976389d16 36
mega64 146:03e976389d16 37
mega64 146:03e976389d16 38 #ifndef __CORE_CMFUNC_H
mega64 146:03e976389d16 39 #define __CORE_CMFUNC_H
mega64 146:03e976389d16 40
mega64 146:03e976389d16 41
mega64 146:03e976389d16 42 /* ########################### Core Function Access ########################### */
mega64 146:03e976389d16 43 /** \ingroup CMSIS_Core_FunctionInterface
mega64 146:03e976389d16 44 \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
mega64 146:03e976389d16 45 @{
mega64 146:03e976389d16 46 */
mega64 146:03e976389d16 47
mega64 146:03e976389d16 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
mega64 146:03e976389d16 49 /* ARM armcc specific functions */
mega64 146:03e976389d16 50
mega64 146:03e976389d16 51 #if (__ARMCC_VERSION < 400677)
mega64 146:03e976389d16 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
mega64 146:03e976389d16 53 #endif
mega64 146:03e976389d16 54
mega64 146:03e976389d16 55 /* intrinsic void __enable_irq(); */
mega64 146:03e976389d16 56 /* intrinsic void __disable_irq(); */
mega64 146:03e976389d16 57
mega64 146:03e976389d16 58 /** \brief Get Control Register
mega64 146:03e976389d16 59
mega64 146:03e976389d16 60 This function returns the content of the Control Register.
mega64 146:03e976389d16 61
mega64 146:03e976389d16 62 \return Control Register value
mega64 146:03e976389d16 63 */
mega64 146:03e976389d16 64 __STATIC_INLINE uint32_t __get_CONTROL(void)
mega64 146:03e976389d16 65 {
mega64 146:03e976389d16 66 register uint32_t __regControl __ASM("control");
mega64 146:03e976389d16 67 return(__regControl);
mega64 146:03e976389d16 68 }
mega64 146:03e976389d16 69
mega64 146:03e976389d16 70
mega64 146:03e976389d16 71 /** \brief Set Control Register
mega64 146:03e976389d16 72
mega64 146:03e976389d16 73 This function writes the given value to the Control Register.
mega64 146:03e976389d16 74
mega64 146:03e976389d16 75 \param [in] control Control Register value to set
mega64 146:03e976389d16 76 */
mega64 146:03e976389d16 77 __STATIC_INLINE void __set_CONTROL(uint32_t control)
mega64 146:03e976389d16 78 {
mega64 146:03e976389d16 79 register uint32_t __regControl __ASM("control");
mega64 146:03e976389d16 80 __regControl = control;
mega64 146:03e976389d16 81 }
mega64 146:03e976389d16 82
mega64 146:03e976389d16 83
mega64 146:03e976389d16 84 /** \brief Get IPSR Register
mega64 146:03e976389d16 85
mega64 146:03e976389d16 86 This function returns the content of the IPSR Register.
mega64 146:03e976389d16 87
mega64 146:03e976389d16 88 \return IPSR Register value
mega64 146:03e976389d16 89 */
mega64 146:03e976389d16 90 __STATIC_INLINE uint32_t __get_IPSR(void)
mega64 146:03e976389d16 91 {
mega64 146:03e976389d16 92 register uint32_t __regIPSR __ASM("ipsr");
mega64 146:03e976389d16 93 return(__regIPSR);
mega64 146:03e976389d16 94 }
mega64 146:03e976389d16 95
mega64 146:03e976389d16 96
mega64 146:03e976389d16 97 /** \brief Get APSR Register
mega64 146:03e976389d16 98
mega64 146:03e976389d16 99 This function returns the content of the APSR Register.
mega64 146:03e976389d16 100
mega64 146:03e976389d16 101 \return APSR Register value
mega64 146:03e976389d16 102 */
mega64 146:03e976389d16 103 __STATIC_INLINE uint32_t __get_APSR(void)
mega64 146:03e976389d16 104 {
mega64 146:03e976389d16 105 register uint32_t __regAPSR __ASM("apsr");
mega64 146:03e976389d16 106 return(__regAPSR);
mega64 146:03e976389d16 107 }
mega64 146:03e976389d16 108
mega64 146:03e976389d16 109
mega64 146:03e976389d16 110 /** \brief Get xPSR Register
mega64 146:03e976389d16 111
mega64 146:03e976389d16 112 This function returns the content of the xPSR Register.
mega64 146:03e976389d16 113
mega64 146:03e976389d16 114 \return xPSR Register value
mega64 146:03e976389d16 115 */
mega64 146:03e976389d16 116 __STATIC_INLINE uint32_t __get_xPSR(void)
mega64 146:03e976389d16 117 {
mega64 146:03e976389d16 118 register uint32_t __regXPSR __ASM("xpsr");
mega64 146:03e976389d16 119 return(__regXPSR);
mega64 146:03e976389d16 120 }
mega64 146:03e976389d16 121
mega64 146:03e976389d16 122
mega64 146:03e976389d16 123 /** \brief Get Process Stack Pointer
mega64 146:03e976389d16 124
mega64 146:03e976389d16 125 This function returns the current value of the Process Stack Pointer (PSP).
mega64 146:03e976389d16 126
mega64 146:03e976389d16 127 \return PSP Register value
mega64 146:03e976389d16 128 */
mega64 146:03e976389d16 129 __STATIC_INLINE uint32_t __get_PSP(void)
mega64 146:03e976389d16 130 {
mega64 146:03e976389d16 131 register uint32_t __regProcessStackPointer __ASM("psp");
mega64 146:03e976389d16 132 return(__regProcessStackPointer);
mega64 146:03e976389d16 133 }
mega64 146:03e976389d16 134
mega64 146:03e976389d16 135
mega64 146:03e976389d16 136 /** \brief Set Process Stack Pointer
mega64 146:03e976389d16 137
mega64 146:03e976389d16 138 This function assigns the given value to the Process Stack Pointer (PSP).
mega64 146:03e976389d16 139
mega64 146:03e976389d16 140 \param [in] topOfProcStack Process Stack Pointer value to set
mega64 146:03e976389d16 141 */
mega64 146:03e976389d16 142 __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mega64 146:03e976389d16 143 {
mega64 146:03e976389d16 144 register uint32_t __regProcessStackPointer __ASM("psp");
mega64 146:03e976389d16 145 __regProcessStackPointer = topOfProcStack;
mega64 146:03e976389d16 146 }
mega64 146:03e976389d16 147
mega64 146:03e976389d16 148
mega64 146:03e976389d16 149 /** \brief Get Main Stack Pointer
mega64 146:03e976389d16 150
mega64 146:03e976389d16 151 This function returns the current value of the Main Stack Pointer (MSP).
mega64 146:03e976389d16 152
mega64 146:03e976389d16 153 \return MSP Register value
mega64 146:03e976389d16 154 */
mega64 146:03e976389d16 155 __STATIC_INLINE uint32_t __get_MSP(void)
mega64 146:03e976389d16 156 {
mega64 146:03e976389d16 157 register uint32_t __regMainStackPointer __ASM("msp");
mega64 146:03e976389d16 158 return(__regMainStackPointer);
mega64 146:03e976389d16 159 }
mega64 146:03e976389d16 160
mega64 146:03e976389d16 161
mega64 146:03e976389d16 162 /** \brief Set Main Stack Pointer
mega64 146:03e976389d16 163
mega64 146:03e976389d16 164 This function assigns the given value to the Main Stack Pointer (MSP).
mega64 146:03e976389d16 165
mega64 146:03e976389d16 166 \param [in] topOfMainStack Main Stack Pointer value to set
mega64 146:03e976389d16 167 */
mega64 146:03e976389d16 168 __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mega64 146:03e976389d16 169 {
mega64 146:03e976389d16 170 register uint32_t __regMainStackPointer __ASM("msp");
mega64 146:03e976389d16 171 __regMainStackPointer = topOfMainStack;
mega64 146:03e976389d16 172 }
mega64 146:03e976389d16 173
mega64 146:03e976389d16 174
mega64 146:03e976389d16 175 /** \brief Get Priority Mask
mega64 146:03e976389d16 176
mega64 146:03e976389d16 177 This function returns the current state of the priority mask bit from the Priority Mask Register.
mega64 146:03e976389d16 178
mega64 146:03e976389d16 179 \return Priority Mask value
mega64 146:03e976389d16 180 */
mega64 146:03e976389d16 181 __STATIC_INLINE uint32_t __get_PRIMASK(void)
mega64 146:03e976389d16 182 {
mega64 146:03e976389d16 183 register uint32_t __regPriMask __ASM("primask");
mega64 146:03e976389d16 184 return(__regPriMask);
mega64 146:03e976389d16 185 }
mega64 146:03e976389d16 186
mega64 146:03e976389d16 187
mega64 146:03e976389d16 188 /** \brief Set Priority Mask
mega64 146:03e976389d16 189
mega64 146:03e976389d16 190 This function assigns the given value to the Priority Mask Register.
mega64 146:03e976389d16 191
mega64 146:03e976389d16 192 \param [in] priMask Priority Mask
mega64 146:03e976389d16 193 */
mega64 146:03e976389d16 194 __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mega64 146:03e976389d16 195 {
mega64 146:03e976389d16 196 register uint32_t __regPriMask __ASM("primask");
mega64 146:03e976389d16 197 __regPriMask = (priMask);
mega64 146:03e976389d16 198 }
mega64 146:03e976389d16 199
mega64 146:03e976389d16 200
mega64 146:03e976389d16 201 #if (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300)
mega64 146:03e976389d16 202
mega64 146:03e976389d16 203 /** \brief Enable FIQ
mega64 146:03e976389d16 204
mega64 146:03e976389d16 205 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mega64 146:03e976389d16 206 Can only be executed in Privileged modes.
mega64 146:03e976389d16 207 */
mega64 146:03e976389d16 208 #define __enable_fault_irq __enable_fiq
mega64 146:03e976389d16 209
mega64 146:03e976389d16 210
mega64 146:03e976389d16 211 /** \brief Disable FIQ
mega64 146:03e976389d16 212
mega64 146:03e976389d16 213 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mega64 146:03e976389d16 214 Can only be executed in Privileged modes.
mega64 146:03e976389d16 215 */
mega64 146:03e976389d16 216 #define __disable_fault_irq __disable_fiq
mega64 146:03e976389d16 217
mega64 146:03e976389d16 218
mega64 146:03e976389d16 219 /** \brief Get Base Priority
mega64 146:03e976389d16 220
mega64 146:03e976389d16 221 This function returns the current value of the Base Priority register.
mega64 146:03e976389d16 222
mega64 146:03e976389d16 223 \return Base Priority register value
mega64 146:03e976389d16 224 */
mega64 146:03e976389d16 225 __STATIC_INLINE uint32_t __get_BASEPRI(void)
mega64 146:03e976389d16 226 {
mega64 146:03e976389d16 227 register uint32_t __regBasePri __ASM("basepri");
mega64 146:03e976389d16 228 return(__regBasePri);
mega64 146:03e976389d16 229 }
mega64 146:03e976389d16 230
mega64 146:03e976389d16 231
mega64 146:03e976389d16 232 /** \brief Set Base Priority
mega64 146:03e976389d16 233
mega64 146:03e976389d16 234 This function assigns the given value to the Base Priority register.
mega64 146:03e976389d16 235
mega64 146:03e976389d16 236 \param [in] basePri Base Priority value to set
mega64 146:03e976389d16 237 */
mega64 146:03e976389d16 238 __STATIC_INLINE void __set_BASEPRI(uint32_t basePri)
mega64 146:03e976389d16 239 {
mega64 146:03e976389d16 240 register uint32_t __regBasePri __ASM("basepri");
mega64 146:03e976389d16 241 __regBasePri = (basePri & 0xff);
mega64 146:03e976389d16 242 }
mega64 146:03e976389d16 243
mega64 146:03e976389d16 244
mega64 146:03e976389d16 245 /** \brief Set Base Priority with condition
mega64 146:03e976389d16 246
mega64 146:03e976389d16 247 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
mega64 146:03e976389d16 248 or the new value increases the BASEPRI priority level.
mega64 146:03e976389d16 249
mega64 146:03e976389d16 250 \param [in] basePri Base Priority value to set
mega64 146:03e976389d16 251 */
mega64 146:03e976389d16 252 __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t basePri)
mega64 146:03e976389d16 253 {
mega64 146:03e976389d16 254 register uint32_t __regBasePriMax __ASM("basepri_max");
mega64 146:03e976389d16 255 __regBasePriMax = (basePri & 0xff);
mega64 146:03e976389d16 256 }
mega64 146:03e976389d16 257
mega64 146:03e976389d16 258
mega64 146:03e976389d16 259 /** \brief Get Fault Mask
mega64 146:03e976389d16 260
mega64 146:03e976389d16 261 This function returns the current value of the Fault Mask register.
mega64 146:03e976389d16 262
mega64 146:03e976389d16 263 \return Fault Mask register value
mega64 146:03e976389d16 264 */
mega64 146:03e976389d16 265 __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mega64 146:03e976389d16 266 {
mega64 146:03e976389d16 267 register uint32_t __regFaultMask __ASM("faultmask");
mega64 146:03e976389d16 268 return(__regFaultMask);
mega64 146:03e976389d16 269 }
mega64 146:03e976389d16 270
mega64 146:03e976389d16 271
mega64 146:03e976389d16 272 /** \brief Set Fault Mask
mega64 146:03e976389d16 273
mega64 146:03e976389d16 274 This function assigns the given value to the Fault Mask register.
mega64 146:03e976389d16 275
mega64 146:03e976389d16 276 \param [in] faultMask Fault Mask value to set
mega64 146:03e976389d16 277 */
mega64 146:03e976389d16 278 __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mega64 146:03e976389d16 279 {
mega64 146:03e976389d16 280 register uint32_t __regFaultMask __ASM("faultmask");
mega64 146:03e976389d16 281 __regFaultMask = (faultMask & (uint32_t)1);
mega64 146:03e976389d16 282 }
mega64 146:03e976389d16 283
mega64 146:03e976389d16 284 #endif /* (__CORTEX_M >= 0x03) || (__CORTEX_SC >= 300) */
mega64 146:03e976389d16 285
mega64 146:03e976389d16 286
mega64 146:03e976389d16 287 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
mega64 146:03e976389d16 288
mega64 146:03e976389d16 289 /** \brief Get FPSCR
mega64 146:03e976389d16 290
mega64 146:03e976389d16 291 This function returns the current value of the Floating Point Status/Control register.
mega64 146:03e976389d16 292
mega64 146:03e976389d16 293 \return Floating Point Status/Control register value
mega64 146:03e976389d16 294 */
mega64 146:03e976389d16 295 __STATIC_INLINE uint32_t __get_FPSCR(void)
mega64 146:03e976389d16 296 {
mega64 146:03e976389d16 297 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 298 register uint32_t __regfpscr __ASM("fpscr");
mega64 146:03e976389d16 299 return(__regfpscr);
mega64 146:03e976389d16 300 #else
mega64 146:03e976389d16 301 return(0);
mega64 146:03e976389d16 302 #endif
mega64 146:03e976389d16 303 }
mega64 146:03e976389d16 304
mega64 146:03e976389d16 305
mega64 146:03e976389d16 306 /** \brief Set FPSCR
mega64 146:03e976389d16 307
mega64 146:03e976389d16 308 This function assigns the given value to the Floating Point Status/Control register.
mega64 146:03e976389d16 309
mega64 146:03e976389d16 310 \param [in] fpscr Floating Point Status/Control value to set
mega64 146:03e976389d16 311 */
mega64 146:03e976389d16 312 __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mega64 146:03e976389d16 313 {
mega64 146:03e976389d16 314 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 315 register uint32_t __regfpscr __ASM("fpscr");
mega64 146:03e976389d16 316 __regfpscr = (fpscr);
mega64 146:03e976389d16 317 #endif
mega64 146:03e976389d16 318 }
mega64 146:03e976389d16 319
mega64 146:03e976389d16 320 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
mega64 146:03e976389d16 321
mega64 146:03e976389d16 322
mega64 146:03e976389d16 323 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
mega64 146:03e976389d16 324 /* GNU gcc specific functions */
mega64 146:03e976389d16 325
mega64 146:03e976389d16 326 /** \brief Enable IRQ Interrupts
mega64 146:03e976389d16 327
mega64 146:03e976389d16 328 This function enables IRQ interrupts by clearing the I-bit in the CPSR.
mega64 146:03e976389d16 329 Can only be executed in Privileged modes.
mega64 146:03e976389d16 330 */
mega64 146:03e976389d16 331 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_irq(void)
mega64 146:03e976389d16 332 {
mega64 146:03e976389d16 333 __ASM volatile ("cpsie i" : : : "memory");
mega64 146:03e976389d16 334 }
mega64 146:03e976389d16 335
mega64 146:03e976389d16 336
mega64 146:03e976389d16 337 /** \brief Disable IRQ Interrupts
mega64 146:03e976389d16 338
mega64 146:03e976389d16 339 This function disables IRQ interrupts by setting the I-bit in the CPSR.
mega64 146:03e976389d16 340 Can only be executed in Privileged modes.
mega64 146:03e976389d16 341 */
mega64 146:03e976389d16 342 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_irq(void)
mega64 146:03e976389d16 343 {
mega64 146:03e976389d16 344 __ASM volatile ("cpsid i" : : : "memory");
mega64 146:03e976389d16 345 }
mega64 146:03e976389d16 346
mega64 146:03e976389d16 347
mega64 146:03e976389d16 348 /** \brief Get Control Register
mega64 146:03e976389d16 349
mega64 146:03e976389d16 350 This function returns the content of the Control Register.
mega64 146:03e976389d16 351
mega64 146:03e976389d16 352 \return Control Register value
mega64 146:03e976389d16 353 */
mega64 146:03e976389d16 354 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_CONTROL(void)
mega64 146:03e976389d16 355 {
mega64 146:03e976389d16 356 uint32_t result;
mega64 146:03e976389d16 357
mega64 146:03e976389d16 358 __ASM volatile ("MRS %0, control" : "=r" (result) );
mega64 146:03e976389d16 359 return(result);
mega64 146:03e976389d16 360 }
mega64 146:03e976389d16 361
mega64 146:03e976389d16 362
mega64 146:03e976389d16 363 /** \brief Set Control Register
mega64 146:03e976389d16 364
mega64 146:03e976389d16 365 This function writes the given value to the Control Register.
mega64 146:03e976389d16 366
mega64 146:03e976389d16 367 \param [in] control Control Register value to set
mega64 146:03e976389d16 368 */
mega64 146:03e976389d16 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_CONTROL(uint32_t control)
mega64 146:03e976389d16 370 {
mega64 146:03e976389d16 371 __ASM volatile ("MSR control, %0" : : "r" (control) : "memory");
mega64 146:03e976389d16 372 }
mega64 146:03e976389d16 373
mega64 146:03e976389d16 374
mega64 146:03e976389d16 375 /** \brief Get IPSR Register
mega64 146:03e976389d16 376
mega64 146:03e976389d16 377 This function returns the content of the IPSR Register.
mega64 146:03e976389d16 378
mega64 146:03e976389d16 379 \return IPSR Register value
mega64 146:03e976389d16 380 */
mega64 146:03e976389d16 381 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_IPSR(void)
mega64 146:03e976389d16 382 {
mega64 146:03e976389d16 383 uint32_t result;
mega64 146:03e976389d16 384
mega64 146:03e976389d16 385 __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
mega64 146:03e976389d16 386 return(result);
mega64 146:03e976389d16 387 }
mega64 146:03e976389d16 388
mega64 146:03e976389d16 389
mega64 146:03e976389d16 390 /** \brief Get APSR Register
mega64 146:03e976389d16 391
mega64 146:03e976389d16 392 This function returns the content of the APSR Register.
mega64 146:03e976389d16 393
mega64 146:03e976389d16 394 \return APSR Register value
mega64 146:03e976389d16 395 */
mega64 146:03e976389d16 396 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_APSR(void)
mega64 146:03e976389d16 397 {
mega64 146:03e976389d16 398 uint32_t result;
mega64 146:03e976389d16 399
mega64 146:03e976389d16 400 __ASM volatile ("MRS %0, apsr" : "=r" (result) );
mega64 146:03e976389d16 401 return(result);
mega64 146:03e976389d16 402 }
mega64 146:03e976389d16 403
mega64 146:03e976389d16 404
mega64 146:03e976389d16 405 /** \brief Get xPSR Register
mega64 146:03e976389d16 406
mega64 146:03e976389d16 407 This function returns the content of the xPSR Register.
mega64 146:03e976389d16 408
mega64 146:03e976389d16 409 \return xPSR Register value
mega64 146:03e976389d16 410 */
mega64 146:03e976389d16 411 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_xPSR(void)
mega64 146:03e976389d16 412 {
mega64 146:03e976389d16 413 uint32_t result;
mega64 146:03e976389d16 414
mega64 146:03e976389d16 415 __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
mega64 146:03e976389d16 416 return(result);
mega64 146:03e976389d16 417 }
mega64 146:03e976389d16 418
mega64 146:03e976389d16 419
mega64 146:03e976389d16 420 /** \brief Get Process Stack Pointer
mega64 146:03e976389d16 421
mega64 146:03e976389d16 422 This function returns the current value of the Process Stack Pointer (PSP).
mega64 146:03e976389d16 423
mega64 146:03e976389d16 424 \return PSP Register value
mega64 146:03e976389d16 425 */
mega64 146:03e976389d16 426 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PSP(void)
mega64 146:03e976389d16 427 {
mega64 146:03e976389d16 428 register uint32_t result;
mega64 146:03e976389d16 429
mega64 146:03e976389d16 430 __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
mega64 146:03e976389d16 431 return(result);
mega64 146:03e976389d16 432 }
mega64 146:03e976389d16 433
mega64 146:03e976389d16 434
mega64 146:03e976389d16 435 /** \brief Set Process Stack Pointer
mega64 146:03e976389d16 436
mega64 146:03e976389d16 437 This function assigns the given value to the Process Stack Pointer (PSP).
mega64 146:03e976389d16 438
mega64 146:03e976389d16 439 \param [in] topOfProcStack Process Stack Pointer value to set
mega64 146:03e976389d16 440 */
mega64 146:03e976389d16 441 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PSP(uint32_t topOfProcStack)
mega64 146:03e976389d16 442 {
mega64 146:03e976389d16 443 __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) : "sp");
mega64 146:03e976389d16 444 }
mega64 146:03e976389d16 445
mega64 146:03e976389d16 446
mega64 146:03e976389d16 447 /** \brief Get Main Stack Pointer
mega64 146:03e976389d16 448
mega64 146:03e976389d16 449 This function returns the current value of the Main Stack Pointer (MSP).
mega64 146:03e976389d16 450
mega64 146:03e976389d16 451 \return MSP Register value
mega64 146:03e976389d16 452 */
mega64 146:03e976389d16 453 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_MSP(void)
mega64 146:03e976389d16 454 {
mega64 146:03e976389d16 455 register uint32_t result;
mega64 146:03e976389d16 456
mega64 146:03e976389d16 457 __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
mega64 146:03e976389d16 458 return(result);
mega64 146:03e976389d16 459 }
mega64 146:03e976389d16 460
mega64 146:03e976389d16 461
mega64 146:03e976389d16 462 /** \brief Set Main Stack Pointer
mega64 146:03e976389d16 463
mega64 146:03e976389d16 464 This function assigns the given value to the Main Stack Pointer (MSP).
mega64 146:03e976389d16 465
mega64 146:03e976389d16 466 \param [in] topOfMainStack Main Stack Pointer value to set
mega64 146:03e976389d16 467 */
mega64 146:03e976389d16 468 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_MSP(uint32_t topOfMainStack)
mega64 146:03e976389d16 469 {
mega64 146:03e976389d16 470 __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) : "sp");
mega64 146:03e976389d16 471 }
mega64 146:03e976389d16 472
mega64 146:03e976389d16 473
mega64 146:03e976389d16 474 /** \brief Get Priority Mask
mega64 146:03e976389d16 475
mega64 146:03e976389d16 476 This function returns the current state of the priority mask bit from the Priority Mask Register.
mega64 146:03e976389d16 477
mega64 146:03e976389d16 478 \return Priority Mask value
mega64 146:03e976389d16 479 */
mega64 146:03e976389d16 480 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_PRIMASK(void)
mega64 146:03e976389d16 481 {
mega64 146:03e976389d16 482 uint32_t result;
mega64 146:03e976389d16 483
mega64 146:03e976389d16 484 __ASM volatile ("MRS %0, primask" : "=r" (result) );
mega64 146:03e976389d16 485 return(result);
mega64 146:03e976389d16 486 }
mega64 146:03e976389d16 487
mega64 146:03e976389d16 488
mega64 146:03e976389d16 489 /** \brief Set Priority Mask
mega64 146:03e976389d16 490
mega64 146:03e976389d16 491 This function assigns the given value to the Priority Mask Register.
mega64 146:03e976389d16 492
mega64 146:03e976389d16 493 \param [in] priMask Priority Mask
mega64 146:03e976389d16 494 */
mega64 146:03e976389d16 495 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_PRIMASK(uint32_t priMask)
mega64 146:03e976389d16 496 {
mega64 146:03e976389d16 497 __ASM volatile ("MSR primask, %0" : : "r" (priMask) : "memory");
mega64 146:03e976389d16 498 }
mega64 146:03e976389d16 499
mega64 146:03e976389d16 500
mega64 146:03e976389d16 501 #if (__CORTEX_M >= 0x03)
mega64 146:03e976389d16 502
mega64 146:03e976389d16 503 /** \brief Enable FIQ
mega64 146:03e976389d16 504
mega64 146:03e976389d16 505 This function enables FIQ interrupts by clearing the F-bit in the CPSR.
mega64 146:03e976389d16 506 Can only be executed in Privileged modes.
mega64 146:03e976389d16 507 */
mega64 146:03e976389d16 508 __attribute__( ( always_inline ) ) __STATIC_INLINE void __enable_fault_irq(void)
mega64 146:03e976389d16 509 {
mega64 146:03e976389d16 510 __ASM volatile ("cpsie f" : : : "memory");
mega64 146:03e976389d16 511 }
mega64 146:03e976389d16 512
mega64 146:03e976389d16 513
mega64 146:03e976389d16 514 /** \brief Disable FIQ
mega64 146:03e976389d16 515
mega64 146:03e976389d16 516 This function disables FIQ interrupts by setting the F-bit in the CPSR.
mega64 146:03e976389d16 517 Can only be executed in Privileged modes.
mega64 146:03e976389d16 518 */
mega64 146:03e976389d16 519 __attribute__( ( always_inline ) ) __STATIC_INLINE void __disable_fault_irq(void)
mega64 146:03e976389d16 520 {
mega64 146:03e976389d16 521 __ASM volatile ("cpsid f" : : : "memory");
mega64 146:03e976389d16 522 }
mega64 146:03e976389d16 523
mega64 146:03e976389d16 524
mega64 146:03e976389d16 525 /** \brief Get Base Priority
mega64 146:03e976389d16 526
mega64 146:03e976389d16 527 This function returns the current value of the Base Priority register.
mega64 146:03e976389d16 528
mega64 146:03e976389d16 529 \return Base Priority register value
mega64 146:03e976389d16 530 */
mega64 146:03e976389d16 531 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_BASEPRI(void)
mega64 146:03e976389d16 532 {
mega64 146:03e976389d16 533 uint32_t result;
mega64 146:03e976389d16 534
mega64 146:03e976389d16 535 __ASM volatile ("MRS %0, basepri" : "=r" (result) );
mega64 146:03e976389d16 536 return(result);
mega64 146:03e976389d16 537 }
mega64 146:03e976389d16 538
mega64 146:03e976389d16 539
mega64 146:03e976389d16 540 /** \brief Set Base Priority
mega64 146:03e976389d16 541
mega64 146:03e976389d16 542 This function assigns the given value to the Base Priority register.
mega64 146:03e976389d16 543
mega64 146:03e976389d16 544 \param [in] basePri Base Priority value to set
mega64 146:03e976389d16 545 */
mega64 146:03e976389d16 546 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI(uint32_t value)
mega64 146:03e976389d16 547 {
mega64 146:03e976389d16 548 __ASM volatile ("MSR basepri, %0" : : "r" (value) : "memory");
mega64 146:03e976389d16 549 }
mega64 146:03e976389d16 550
mega64 146:03e976389d16 551
mega64 146:03e976389d16 552 /** \brief Set Base Priority with condition
mega64 146:03e976389d16 553
mega64 146:03e976389d16 554 This function assigns the given value to the Base Priority register only if BASEPRI masking is disabled,
mega64 146:03e976389d16 555 or the new value increases the BASEPRI priority level.
mega64 146:03e976389d16 556
mega64 146:03e976389d16 557 \param [in] basePri Base Priority value to set
mega64 146:03e976389d16 558 */
mega64 146:03e976389d16 559 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_BASEPRI_MAX(uint32_t value)
mega64 146:03e976389d16 560 {
mega64 146:03e976389d16 561 __ASM volatile ("MSR basepri_max, %0" : : "r" (value) : "memory");
mega64 146:03e976389d16 562 }
mega64 146:03e976389d16 563
mega64 146:03e976389d16 564
mega64 146:03e976389d16 565 /** \brief Get Fault Mask
mega64 146:03e976389d16 566
mega64 146:03e976389d16 567 This function returns the current value of the Fault Mask register.
mega64 146:03e976389d16 568
mega64 146:03e976389d16 569 \return Fault Mask register value
mega64 146:03e976389d16 570 */
mega64 146:03e976389d16 571 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FAULTMASK(void)
mega64 146:03e976389d16 572 {
mega64 146:03e976389d16 573 uint32_t result;
mega64 146:03e976389d16 574
mega64 146:03e976389d16 575 __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
mega64 146:03e976389d16 576 return(result);
mega64 146:03e976389d16 577 }
mega64 146:03e976389d16 578
mega64 146:03e976389d16 579
mega64 146:03e976389d16 580 /** \brief Set Fault Mask
mega64 146:03e976389d16 581
mega64 146:03e976389d16 582 This function assigns the given value to the Fault Mask register.
mega64 146:03e976389d16 583
mega64 146:03e976389d16 584 \param [in] faultMask Fault Mask value to set
mega64 146:03e976389d16 585 */
mega64 146:03e976389d16 586 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FAULTMASK(uint32_t faultMask)
mega64 146:03e976389d16 587 {
mega64 146:03e976389d16 588 __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) : "memory");
mega64 146:03e976389d16 589 }
mega64 146:03e976389d16 590
mega64 146:03e976389d16 591 #endif /* (__CORTEX_M >= 0x03) */
mega64 146:03e976389d16 592
mega64 146:03e976389d16 593
mega64 146:03e976389d16 594 #if (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07)
mega64 146:03e976389d16 595
mega64 146:03e976389d16 596 /** \brief Get FPSCR
mega64 146:03e976389d16 597
mega64 146:03e976389d16 598 This function returns the current value of the Floating Point Status/Control register.
mega64 146:03e976389d16 599
mega64 146:03e976389d16 600 \return Floating Point Status/Control register value
mega64 146:03e976389d16 601 */
mega64 146:03e976389d16 602 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __get_FPSCR(void)
mega64 146:03e976389d16 603 {
mega64 146:03e976389d16 604 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 605 uint32_t result;
mega64 146:03e976389d16 606
mega64 146:03e976389d16 607 /* Empty asm statement works as a scheduling barrier */
mega64 146:03e976389d16 608 __ASM volatile ("");
mega64 146:03e976389d16 609 __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
mega64 146:03e976389d16 610 __ASM volatile ("");
mega64 146:03e976389d16 611 return(result);
mega64 146:03e976389d16 612 #else
mega64 146:03e976389d16 613 return(0);
mega64 146:03e976389d16 614 #endif
mega64 146:03e976389d16 615 }
mega64 146:03e976389d16 616
mega64 146:03e976389d16 617
mega64 146:03e976389d16 618 /** \brief Set FPSCR
mega64 146:03e976389d16 619
mega64 146:03e976389d16 620 This function assigns the given value to the Floating Point Status/Control register.
mega64 146:03e976389d16 621
mega64 146:03e976389d16 622 \param [in] fpscr Floating Point Status/Control value to set
mega64 146:03e976389d16 623 */
mega64 146:03e976389d16 624 __attribute__( ( always_inline ) ) __STATIC_INLINE void __set_FPSCR(uint32_t fpscr)
mega64 146:03e976389d16 625 {
mega64 146:03e976389d16 626 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
mega64 146:03e976389d16 627 /* Empty asm statement works as a scheduling barrier */
mega64 146:03e976389d16 628 __ASM volatile ("");
mega64 146:03e976389d16 629 __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) : "vfpcc");
mega64 146:03e976389d16 630 __ASM volatile ("");
mega64 146:03e976389d16 631 #endif
mega64 146:03e976389d16 632 }
mega64 146:03e976389d16 633
mega64 146:03e976389d16 634 #endif /* (__CORTEX_M == 0x04) || (__CORTEX_M == 0x07) */
mega64 146:03e976389d16 635
mega64 146:03e976389d16 636
mega64 146:03e976389d16 637 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
mega64 146:03e976389d16 638 /* IAR iccarm specific functions */
mega64 146:03e976389d16 639 #include <cmsis_iar.h>
mega64 146:03e976389d16 640
mega64 146:03e976389d16 641
mega64 146:03e976389d16 642 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
mega64 146:03e976389d16 643 /* TI CCS specific functions */
mega64 146:03e976389d16 644 #include <cmsis_ccs.h>
mega64 146:03e976389d16 645
mega64 146:03e976389d16 646
mega64 146:03e976389d16 647 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
mega64 146:03e976389d16 648 /* TASKING carm specific functions */
mega64 146:03e976389d16 649 /*
mega64 146:03e976389d16 650 * The CMSIS functions have been implemented as intrinsics in the compiler.
mega64 146:03e976389d16 651 * Please use "carm -?i" to get an up to date list of all intrinsics,
mega64 146:03e976389d16 652 * Including the CMSIS ones.
mega64 146:03e976389d16 653 */
mega64 146:03e976389d16 654
mega64 146:03e976389d16 655
mega64 146:03e976389d16 656 #elif defined ( __CSMC__ ) /*------------------ COSMIC Compiler -------------------*/
mega64 146:03e976389d16 657 /* Cosmic specific functions */
mega64 146:03e976389d16 658 #include <cmsis_csm.h>
mega64 146:03e976389d16 659
mega64 146:03e976389d16 660 #endif
mega64 146:03e976389d16 661
mega64 146:03e976389d16 662 /*@} end of CMSIS_Core_RegAccFunctions */
mega64 146:03e976389d16 663
mega64 146:03e976389d16 664 #endif /* __CORE_CMFUNC_H */