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targets/cmsis/TARGET_STM/TARGET_STM32F1/stm32f1xx_hal_pwr.h@0:9b334a45a8ff, 2015-10-01 (annotated)

Committer:
bogdanm
Date:
Thu Oct 01 15:25:22 2015 +0300
Revision:
0:9b334a45a8ff
Initial commit on mbed-dev



Replaces mbed-src (now inactive)

Who changed what in which revision?

UserRevisionLine numberNew contents of line
bogdanm 0:9b334a45a8ff 1 /**
bogdanm 0:9b334a45a8ff 2 ******************************************************************************
bogdanm 0:9b334a45a8ff 3 * @file stm32f1xx_hal_pwr.h
bogdanm 0:9b334a45a8ff 4 * @author MCD Application Team
bogdanm 0:9b334a45a8ff 5 * @version V1.0.0
bogdanm 0:9b334a45a8ff 6 * @date 15-December-2014
bogdanm 0:9b334a45a8ff 7 * @brief Header file of PWR HAL module.
bogdanm 0:9b334a45a8ff 8 ******************************************************************************
bogdanm 0:9b334a45a8ff 9 * @attention
bogdanm 0:9b334a45a8ff 10 *
bogdanm 0:9b334a45a8ff 11 * <h2><center>&copy; COPYRIGHT(c) 2014 STMicroelectronics</center></h2>
bogdanm 0:9b334a45a8ff 12 *
bogdanm 0:9b334a45a8ff 13 * Redistribution and use in source and binary forms, with or without modification,
bogdanm 0:9b334a45a8ff 14 * are permitted provided that the following conditions are met:
bogdanm 0:9b334a45a8ff 15 * 1. Redistributions of source code must retain the above copyright notice,
bogdanm 0:9b334a45a8ff 16 * this list of conditions and the following disclaimer.
bogdanm 0:9b334a45a8ff 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
bogdanm 0:9b334a45a8ff 18 * this list of conditions and the following disclaimer in the documentation
bogdanm 0:9b334a45a8ff 19 * and/or other materials provided with the distribution.
bogdanm 0:9b334a45a8ff 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
bogdanm 0:9b334a45a8ff 21 * may be used to endorse or promote products derived from this software
bogdanm 0:9b334a45a8ff 22 * without specific prior written permission.
bogdanm 0:9b334a45a8ff 23 *
bogdanm 0:9b334a45a8ff 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
bogdanm 0:9b334a45a8ff 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
bogdanm 0:9b334a45a8ff 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
bogdanm 0:9b334a45a8ff 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
bogdanm 0:9b334a45a8ff 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
bogdanm 0:9b334a45a8ff 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
bogdanm 0:9b334a45a8ff 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
bogdanm 0:9b334a45a8ff 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
bogdanm 0:9b334a45a8ff 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
bogdanm 0:9b334a45a8ff 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
bogdanm 0:9b334a45a8ff 34 *
bogdanm 0:9b334a45a8ff 35 ******************************************************************************
bogdanm 0:9b334a45a8ff 36 */
bogdanm 0:9b334a45a8ff 37
bogdanm 0:9b334a45a8ff 38 /* Define to prevent recursive inclusion -------------------------------------*/
bogdanm 0:9b334a45a8ff 39 #ifndef __STM32F1xx_HAL_PWR_H
bogdanm 0:9b334a45a8ff 40 #define __STM32F1xx_HAL_PWR_H
bogdanm 0:9b334a45a8ff 41
bogdanm 0:9b334a45a8ff 42 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 43 extern "C" {
bogdanm 0:9b334a45a8ff 44 #endif
bogdanm 0:9b334a45a8ff 45
bogdanm 0:9b334a45a8ff 46 /* Includes ------------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 47 #include "stm32f1xx_hal_def.h"
bogdanm 0:9b334a45a8ff 48
bogdanm 0:9b334a45a8ff 49 /** @addtogroup STM32F1xx_HAL_Driver
bogdanm 0:9b334a45a8ff 50 * @{
bogdanm 0:9b334a45a8ff 51 */
bogdanm 0:9b334a45a8ff 52
bogdanm 0:9b334a45a8ff 53 /** @addtogroup PWR
bogdanm 0:9b334a45a8ff 54 * @{
bogdanm 0:9b334a45a8ff 55 */
bogdanm 0:9b334a45a8ff 56
bogdanm 0:9b334a45a8ff 57 /* Exported types ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 58
bogdanm 0:9b334a45a8ff 59 /** @defgroup PWR_Exported_Types PWR Exported Types
bogdanm 0:9b334a45a8ff 60 * @{
bogdanm 0:9b334a45a8ff 61 */
bogdanm 0:9b334a45a8ff 62
bogdanm 0:9b334a45a8ff 63 /**
bogdanm 0:9b334a45a8ff 64 * @brief PWR PVD configuration structure definition
bogdanm 0:9b334a45a8ff 65 */
bogdanm 0:9b334a45a8ff 66 typedef struct
bogdanm 0:9b334a45a8ff 67 {
bogdanm 0:9b334a45a8ff 68 uint32_t PVDLevel; /*!< PVDLevel: Specifies the PVD detection level.
bogdanm 0:9b334a45a8ff 69 This parameter can be a value of @ref PWR_PVD_detection_level */
bogdanm 0:9b334a45a8ff 70
bogdanm 0:9b334a45a8ff 71 uint32_t Mode; /*!< Mode: Specifies the operating mode for the selected pins.
bogdanm 0:9b334a45a8ff 72 This parameter can be a value of @ref PWR_PVD_Mode */
bogdanm 0:9b334a45a8ff 73 }PWR_PVDTypeDef;
bogdanm 0:9b334a45a8ff 74
bogdanm 0:9b334a45a8ff 75
bogdanm 0:9b334a45a8ff 76 /**
bogdanm 0:9b334a45a8ff 77 * @}
bogdanm 0:9b334a45a8ff 78 */
bogdanm 0:9b334a45a8ff 79
bogdanm 0:9b334a45a8ff 80
bogdanm 0:9b334a45a8ff 81 /* Internal constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 82
bogdanm 0:9b334a45a8ff 83 /** @addtogroup PWR_Private_Constants
bogdanm 0:9b334a45a8ff 84 * @{
bogdanm 0:9b334a45a8ff 85 */
bogdanm 0:9b334a45a8ff 86
bogdanm 0:9b334a45a8ff 87 #define PWR_EXTI_LINE_PVD ((uint32_t)0x00010000) /*!< External interrupt line 16 Connected to the PVD EXTI Line */
bogdanm 0:9b334a45a8ff 88
bogdanm 0:9b334a45a8ff 89 /**
bogdanm 0:9b334a45a8ff 90 * @}
bogdanm 0:9b334a45a8ff 91 */
bogdanm 0:9b334a45a8ff 92
bogdanm 0:9b334a45a8ff 93
bogdanm 0:9b334a45a8ff 94 /* Exported constants --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 95
bogdanm 0:9b334a45a8ff 96 /** @defgroup PWR_Exported_Constants PWR Exported Constants
bogdanm 0:9b334a45a8ff 97 * @{
bogdanm 0:9b334a45a8ff 98 */
bogdanm 0:9b334a45a8ff 99
bogdanm 0:9b334a45a8ff 100 /** @defgroup PWR_PVD_detection_level PWR PVD detection level
bogdanm 0:9b334a45a8ff 101 * @{
bogdanm 0:9b334a45a8ff 102 */
bogdanm 0:9b334a45a8ff 103 #define PWR_PVDLEVEL_0 PWR_CR_PLS_2V2
bogdanm 0:9b334a45a8ff 104 #define PWR_PVDLEVEL_1 PWR_CR_PLS_2V3
bogdanm 0:9b334a45a8ff 105 #define PWR_PVDLEVEL_2 PWR_CR_PLS_2V4
bogdanm 0:9b334a45a8ff 106 #define PWR_PVDLEVEL_3 PWR_CR_PLS_2V5
bogdanm 0:9b334a45a8ff 107 #define PWR_PVDLEVEL_4 PWR_CR_PLS_2V6
bogdanm 0:9b334a45a8ff 108 #define PWR_PVDLEVEL_5 PWR_CR_PLS_2V7
bogdanm 0:9b334a45a8ff 109 #define PWR_PVDLEVEL_6 PWR_CR_PLS_2V8
bogdanm 0:9b334a45a8ff 110 #define PWR_PVDLEVEL_7 PWR_CR_PLS_2V9
bogdanm 0:9b334a45a8ff 111
bogdanm 0:9b334a45a8ff 112 /**
bogdanm 0:9b334a45a8ff 113 * @}
bogdanm 0:9b334a45a8ff 114 */
bogdanm 0:9b334a45a8ff 115
bogdanm 0:9b334a45a8ff 116 /** @defgroup PWR_PVD_Mode PWR PVD Mode
bogdanm 0:9b334a45a8ff 117 * @{
bogdanm 0:9b334a45a8ff 118 */
bogdanm 0:9b334a45a8ff 119 #define PWR_PVD_MODE_NORMAL ((uint32_t)0x00000000) /*!< basic mode is used */
bogdanm 0:9b334a45a8ff 120 #define PWR_PVD_MODE_IT_RISING ((uint32_t)0x00010001) /*!< External Interrupt Mode with Rising edge trigger detection */
bogdanm 0:9b334a45a8ff 121 #define PWR_PVD_MODE_IT_FALLING ((uint32_t)0x00010002) /*!< External Interrupt Mode with Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 122 #define PWR_PVD_MODE_IT_RISING_FALLING ((uint32_t)0x00010003) /*!< External Interrupt Mode with Rising/Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 123 #define PWR_PVD_MODE_EVENT_RISING ((uint32_t)0x00020001) /*!< Event Mode with Rising edge trigger detection */
bogdanm 0:9b334a45a8ff 124 #define PWR_PVD_MODE_EVENT_FALLING ((uint32_t)0x00020002) /*!< Event Mode with Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 125 #define PWR_PVD_MODE_EVENT_RISING_FALLING ((uint32_t)0x00020003) /*!< Event Mode with Rising/Falling edge trigger detection */
bogdanm 0:9b334a45a8ff 126
bogdanm 0:9b334a45a8ff 127 /**
bogdanm 0:9b334a45a8ff 128 * @}
bogdanm 0:9b334a45a8ff 129 */
bogdanm 0:9b334a45a8ff 130
bogdanm 0:9b334a45a8ff 131
bogdanm 0:9b334a45a8ff 132 /** @defgroup PWR_WakeUp_Pins PWR WakeUp Pins
bogdanm 0:9b334a45a8ff 133 * @{
bogdanm 0:9b334a45a8ff 134 */
bogdanm 0:9b334a45a8ff 135
bogdanm 0:9b334a45a8ff 136 #define PWR_WAKEUP_PIN1 PWR_CSR_EWUP
bogdanm 0:9b334a45a8ff 137
bogdanm 0:9b334a45a8ff 138 /**
bogdanm 0:9b334a45a8ff 139 * @}
bogdanm 0:9b334a45a8ff 140 */
bogdanm 0:9b334a45a8ff 141
bogdanm 0:9b334a45a8ff 142 /** @defgroup PWR_Regulator_state_in_SLEEP_STOP_mode PWR Regulator state in SLEEP/STOP mode
bogdanm 0:9b334a45a8ff 143 * @{
bogdanm 0:9b334a45a8ff 144 */
bogdanm 0:9b334a45a8ff 145 #define PWR_MAINREGULATOR_ON ((uint32_t)0x00000000)
bogdanm 0:9b334a45a8ff 146 #define PWR_LOWPOWERREGULATOR_ON PWR_CR_LPDS
bogdanm 0:9b334a45a8ff 147
bogdanm 0:9b334a45a8ff 148 /**
bogdanm 0:9b334a45a8ff 149 * @}
bogdanm 0:9b334a45a8ff 150 */
bogdanm 0:9b334a45a8ff 151
bogdanm 0:9b334a45a8ff 152 /** @defgroup PWR_SLEEP_mode_entry PWR SLEEP mode entry
bogdanm 0:9b334a45a8ff 153 * @{
bogdanm 0:9b334a45a8ff 154 */
bogdanm 0:9b334a45a8ff 155 #define PWR_SLEEPENTRY_WFI ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 156 #define PWR_SLEEPENTRY_WFE ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 157
bogdanm 0:9b334a45a8ff 158 /**
bogdanm 0:9b334a45a8ff 159 * @}
bogdanm 0:9b334a45a8ff 160 */
bogdanm 0:9b334a45a8ff 161
bogdanm 0:9b334a45a8ff 162 /** @defgroup PWR_STOP_mode_entry PWR STOP mode entry
bogdanm 0:9b334a45a8ff 163 * @{
bogdanm 0:9b334a45a8ff 164 */
bogdanm 0:9b334a45a8ff 165 #define PWR_STOPENTRY_WFI ((uint8_t)0x01)
bogdanm 0:9b334a45a8ff 166 #define PWR_STOPENTRY_WFE ((uint8_t)0x02)
bogdanm 0:9b334a45a8ff 167
bogdanm 0:9b334a45a8ff 168 /**
bogdanm 0:9b334a45a8ff 169 * @}
bogdanm 0:9b334a45a8ff 170 */
bogdanm 0:9b334a45a8ff 171
bogdanm 0:9b334a45a8ff 172 /** @defgroup PWR_Flag PWR Flag
bogdanm 0:9b334a45a8ff 173 * @{
bogdanm 0:9b334a45a8ff 174 */
bogdanm 0:9b334a45a8ff 175 #define PWR_FLAG_WU PWR_CSR_WUF
bogdanm 0:9b334a45a8ff 176 #define PWR_FLAG_SB PWR_CSR_SBF
bogdanm 0:9b334a45a8ff 177 #define PWR_FLAG_PVDO PWR_CSR_PVDO
bogdanm 0:9b334a45a8ff 178
bogdanm 0:9b334a45a8ff 179
bogdanm 0:9b334a45a8ff 180 /**
bogdanm 0:9b334a45a8ff 181 * @}
bogdanm 0:9b334a45a8ff 182 */
bogdanm 0:9b334a45a8ff 183
bogdanm 0:9b334a45a8ff 184 /**
bogdanm 0:9b334a45a8ff 185 * @}
bogdanm 0:9b334a45a8ff 186 */
bogdanm 0:9b334a45a8ff 187
bogdanm 0:9b334a45a8ff 188 /* Exported macro ------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 189 /** @defgroup PWR_Exported_Macros PWR Exported Macros
bogdanm 0:9b334a45a8ff 190 * @{
bogdanm 0:9b334a45a8ff 191 */
bogdanm 0:9b334a45a8ff 192
bogdanm 0:9b334a45a8ff 193 /** @brief Check PWR flag is set or not.
bogdanm 0:9b334a45a8ff 194 * @param __FLAG__: specifies the flag to check.
bogdanm 0:9b334a45a8ff 195 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 196 * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event
bogdanm 0:9b334a45a8ff 197 * was received from the WKUP pin or from the RTC alarm
bogdanm 0:9b334a45a8ff 198 * An additional wakeup event is detected if the WKUP pin is enabled
bogdanm 0:9b334a45a8ff 199 * (by setting the EWUP bit) when the WKUP pin level is already high.
bogdanm 0:9b334a45a8ff 200 * @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
bogdanm 0:9b334a45a8ff 201 * resumed from StandBy mode.
bogdanm 0:9b334a45a8ff 202 * @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled
bogdanm 0:9b334a45a8ff 203 * by the HAL_PWR_EnablePVD() function. The PVD is stopped by Standby mode
bogdanm 0:9b334a45a8ff 204 * For this reason, this bit is equal to 0 after Standby or reset
bogdanm 0:9b334a45a8ff 205 * until the PVDE bit is set.
bogdanm 0:9b334a45a8ff 206 * @retval The new state of __FLAG__ (TRUE or FALSE).
bogdanm 0:9b334a45a8ff 207 */
bogdanm 0:9b334a45a8ff 208 #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__))
bogdanm 0:9b334a45a8ff 209
bogdanm 0:9b334a45a8ff 210 /** @brief Clear the PWR's pending flags.
bogdanm 0:9b334a45a8ff 211 * @param __FLAG__: specifies the flag to clear.
bogdanm 0:9b334a45a8ff 212 * This parameter can be one of the following values:
bogdanm 0:9b334a45a8ff 213 * @arg PWR_FLAG_WU: Wake Up flag
bogdanm 0:9b334a45a8ff 214 * @arg PWR_FLAG_SB: StandBy flag
bogdanm 0:9b334a45a8ff 215 */
bogdanm 0:9b334a45a8ff 216 #define __HAL_PWR_CLEAR_FLAG(__FLAG__) SET_BIT(PWR->CR, ((__FLAG__) << 2))
bogdanm 0:9b334a45a8ff 217
bogdanm 0:9b334a45a8ff 218 /**
bogdanm 0:9b334a45a8ff 219 * @brief Enable interrupt on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 220 * @retval None.
bogdanm 0:9b334a45a8ff 221 */
bogdanm 0:9b334a45a8ff 222 #define __HAL_PWR_PVD_EXTI_ENABLE_IT() SET_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 223
bogdanm 0:9b334a45a8ff 224 /**
bogdanm 0:9b334a45a8ff 225 * @brief Disable interrupt on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 226 * @retval None.
bogdanm 0:9b334a45a8ff 227 */
bogdanm 0:9b334a45a8ff 228 #define __HAL_PWR_PVD_EXTI_DISABLE_IT() CLEAR_BIT(EXTI->IMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 229
bogdanm 0:9b334a45a8ff 230 /**
bogdanm 0:9b334a45a8ff 231 * @brief Enable event on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 232 * @retval None.
bogdanm 0:9b334a45a8ff 233 */
bogdanm 0:9b334a45a8ff 234 #define __HAL_PWR_PVD_EXTI_ENABLE_EVENT() SET_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 235
bogdanm 0:9b334a45a8ff 236 /**
bogdanm 0:9b334a45a8ff 237 * @brief Disable event on PVD Exti Line 16.
bogdanm 0:9b334a45a8ff 238 * @retval None.
bogdanm 0:9b334a45a8ff 239 */
bogdanm 0:9b334a45a8ff 240 #define __HAL_PWR_PVD_EXTI_DISABLE_EVENT() CLEAR_BIT(EXTI->EMR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 241
bogdanm 0:9b334a45a8ff 242
bogdanm 0:9b334a45a8ff 243 /**
bogdanm 0:9b334a45a8ff 244 * @brief PVD EXTI line configuration: set falling edge trigger.
bogdanm 0:9b334a45a8ff 245 * @retval None.
bogdanm 0:9b334a45a8ff 246 */
bogdanm 0:9b334a45a8ff 247 #define __HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE() SET_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 248
bogdanm 0:9b334a45a8ff 249
bogdanm 0:9b334a45a8ff 250 /**
bogdanm 0:9b334a45a8ff 251 * @brief Disable the PVD Extended Interrupt Falling Trigger.
bogdanm 0:9b334a45a8ff 252 * @retval None.
bogdanm 0:9b334a45a8ff 253 */
bogdanm 0:9b334a45a8ff 254 #define __HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE() CLEAR_BIT(EXTI->FTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 255
bogdanm 0:9b334a45a8ff 256
bogdanm 0:9b334a45a8ff 257 /**
bogdanm 0:9b334a45a8ff 258 * @brief PVD EXTI line configuration: set rising edge trigger.
bogdanm 0:9b334a45a8ff 259 * @retval None.
bogdanm 0:9b334a45a8ff 260 */
bogdanm 0:9b334a45a8ff 261 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE() SET_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 262
bogdanm 0:9b334a45a8ff 263 /**
bogdanm 0:9b334a45a8ff 264 * @brief Disable the PVD Extended Interrupt Rising Trigger.
bogdanm 0:9b334a45a8ff 265 * This parameter can be:
bogdanm 0:9b334a45a8ff 266 * @retval None.
bogdanm 0:9b334a45a8ff 267 */
bogdanm 0:9b334a45a8ff 268 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE() CLEAR_BIT(EXTI->RTSR, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 269
bogdanm 0:9b334a45a8ff 270 /**
bogdanm 0:9b334a45a8ff 271 * @brief PVD EXTI line configuration: set rising & falling edge trigger.
bogdanm 0:9b334a45a8ff 272 * @retval None.
bogdanm 0:9b334a45a8ff 273 */
bogdanm 0:9b334a45a8ff 274 #define __HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 275
bogdanm 0:9b334a45a8ff 276 /**
bogdanm 0:9b334a45a8ff 277 * @brief Disable the PVD Extended Interrupt Rising & Falling Trigger.
bogdanm 0:9b334a45a8ff 278 * This parameter can be:
bogdanm 0:9b334a45a8ff 279 * @retval None.
bogdanm 0:9b334a45a8ff 280 */
bogdanm 0:9b334a45a8ff 281 #define __HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE() __HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE();__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE();
bogdanm 0:9b334a45a8ff 282
bogdanm 0:9b334a45a8ff 283
bogdanm 0:9b334a45a8ff 284
bogdanm 0:9b334a45a8ff 285 /**
bogdanm 0:9b334a45a8ff 286 * @brief Check whether the specified PVD EXTI interrupt flag is set or not.
bogdanm 0:9b334a45a8ff 287 * @retval EXTI PVD Line Status.
bogdanm 0:9b334a45a8ff 288 */
bogdanm 0:9b334a45a8ff 289 #define __HAL_PWR_PVD_EXTI_GET_FLAG() (EXTI->PR & (PWR_EXTI_LINE_PVD))
bogdanm 0:9b334a45a8ff 290
bogdanm 0:9b334a45a8ff 291 /**
bogdanm 0:9b334a45a8ff 292 * @brief Clear the PVD EXTI flag.
bogdanm 0:9b334a45a8ff 293 * @retval None.
bogdanm 0:9b334a45a8ff 294 */
bogdanm 0:9b334a45a8ff 295 #define __HAL_PWR_PVD_EXTI_CLEAR_FLAG() (EXTI->PR = (PWR_EXTI_LINE_PVD))
bogdanm 0:9b334a45a8ff 296
bogdanm 0:9b334a45a8ff 297 /**
bogdanm 0:9b334a45a8ff 298 * @brief Generate a Software interrupt on selected EXTI line.
bogdanm 0:9b334a45a8ff 299 * @retval None.
bogdanm 0:9b334a45a8ff 300 */
bogdanm 0:9b334a45a8ff 301 #define __HAL_PWR_PVD_EXTI_GENERATE_SWIT() SET_BIT(EXTI->SWIER, PWR_EXTI_LINE_PVD)
bogdanm 0:9b334a45a8ff 302 /**
bogdanm 0:9b334a45a8ff 303 * @}
bogdanm 0:9b334a45a8ff 304 */
bogdanm 0:9b334a45a8ff 305
bogdanm 0:9b334a45a8ff 306 /* Private macro -------------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 307 /** @defgroup PWR_Private_Macros PWR Private Macros
bogdanm 0:9b334a45a8ff 308 * @{
bogdanm 0:9b334a45a8ff 309 */
bogdanm 0:9b334a45a8ff 310 #define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLEVEL_0) || ((LEVEL) == PWR_PVDLEVEL_1)|| \
bogdanm 0:9b334a45a8ff 311 ((LEVEL) == PWR_PVDLEVEL_2) || ((LEVEL) == PWR_PVDLEVEL_3)|| \
bogdanm 0:9b334a45a8ff 312 ((LEVEL) == PWR_PVDLEVEL_4) || ((LEVEL) == PWR_PVDLEVEL_5)|| \
bogdanm 0:9b334a45a8ff 313 ((LEVEL) == PWR_PVDLEVEL_6) || ((LEVEL) == PWR_PVDLEVEL_7))
bogdanm 0:9b334a45a8ff 314
bogdanm 0:9b334a45a8ff 315
bogdanm 0:9b334a45a8ff 316 #define IS_PWR_PVD_MODE(MODE) (((MODE) == PWR_PVD_MODE_IT_RISING)|| ((MODE) == PWR_PVD_MODE_IT_FALLING) || \
bogdanm 0:9b334a45a8ff 317 ((MODE) == PWR_PVD_MODE_IT_RISING_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING) || \
bogdanm 0:9b334a45a8ff 318 ((MODE) == PWR_PVD_MODE_EVENT_FALLING) || ((MODE) == PWR_PVD_MODE_EVENT_RISING_FALLING) || \
bogdanm 0:9b334a45a8ff 319 ((MODE) == PWR_PVD_MODE_NORMAL))
bogdanm 0:9b334a45a8ff 320
bogdanm 0:9b334a45a8ff 321 #define IS_PWR_WAKEUP_PIN(PIN) (((PIN) == PWR_WAKEUP_PIN1))
bogdanm 0:9b334a45a8ff 322
bogdanm 0:9b334a45a8ff 323 #define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_MAINREGULATOR_ON) || \
bogdanm 0:9b334a45a8ff 324 ((REGULATOR) == PWR_LOWPOWERREGULATOR_ON))
bogdanm 0:9b334a45a8ff 325
bogdanm 0:9b334a45a8ff 326 #define IS_PWR_SLEEP_ENTRY(ENTRY) (((ENTRY) == PWR_SLEEPENTRY_WFI) || ((ENTRY) == PWR_SLEEPENTRY_WFE))
bogdanm 0:9b334a45a8ff 327
bogdanm 0:9b334a45a8ff 328 #define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPENTRY_WFI) || ((ENTRY) == PWR_STOPENTRY_WFE))
bogdanm 0:9b334a45a8ff 329
bogdanm 0:9b334a45a8ff 330 /**
bogdanm 0:9b334a45a8ff 331 * @}
bogdanm 0:9b334a45a8ff 332 */
bogdanm 0:9b334a45a8ff 333
bogdanm 0:9b334a45a8ff 334
bogdanm 0:9b334a45a8ff 335
bogdanm 0:9b334a45a8ff 336 /* Exported functions --------------------------------------------------------*/
bogdanm 0:9b334a45a8ff 337
bogdanm 0:9b334a45a8ff 338 /** @addtogroup PWR_Exported_Functions PWR Exported Functions
bogdanm 0:9b334a45a8ff 339 * @{
bogdanm 0:9b334a45a8ff 340 */
bogdanm 0:9b334a45a8ff 341
bogdanm 0:9b334a45a8ff 342 /** @addtogroup PWR_Exported_Functions_Group1 Initialization and de-initialization functions
bogdanm 0:9b334a45a8ff 343 * @{
bogdanm 0:9b334a45a8ff 344 */
bogdanm 0:9b334a45a8ff 345
bogdanm 0:9b334a45a8ff 346 /* Initialization and de-initialization functions *******************************/
bogdanm 0:9b334a45a8ff 347 void HAL_PWR_DeInit(void);
bogdanm 0:9b334a45a8ff 348 void HAL_PWR_EnableBkUpAccess(void);
bogdanm 0:9b334a45a8ff 349 void HAL_PWR_DisableBkUpAccess(void);
bogdanm 0:9b334a45a8ff 350
bogdanm 0:9b334a45a8ff 351 /**
bogdanm 0:9b334a45a8ff 352 * @}
bogdanm 0:9b334a45a8ff 353 */
bogdanm 0:9b334a45a8ff 354
bogdanm 0:9b334a45a8ff 355 /** @addtogroup PWR_Exported_Functions_Group2 Peripheral Control functions
bogdanm 0:9b334a45a8ff 356 * @{
bogdanm 0:9b334a45a8ff 357 */
bogdanm 0:9b334a45a8ff 358
bogdanm 0:9b334a45a8ff 359 /* Peripheral Control functions ************************************************/
bogdanm 0:9b334a45a8ff 360 void HAL_PWR_ConfigPVD(PWR_PVDTypeDef *sConfigPVD);
bogdanm 0:9b334a45a8ff 361 /* #define HAL_PWR_ConfigPVD 12*/
bogdanm 0:9b334a45a8ff 362 void HAL_PWR_EnablePVD(void);
bogdanm 0:9b334a45a8ff 363 void HAL_PWR_DisablePVD(void);
bogdanm 0:9b334a45a8ff 364
bogdanm 0:9b334a45a8ff 365 /* WakeUp pins configuration functions ****************************************/
bogdanm 0:9b334a45a8ff 366 void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 0:9b334a45a8ff 367 void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx);
bogdanm 0:9b334a45a8ff 368
bogdanm 0:9b334a45a8ff 369 /* Low Power modes configuration functions ************************************/
bogdanm 0:9b334a45a8ff 370 void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry);
bogdanm 0:9b334a45a8ff 371 void HAL_PWR_EnterSLEEPMode(uint32_t Regulator, uint8_t SLEEPEntry);
bogdanm 0:9b334a45a8ff 372 void HAL_PWR_EnterSTANDBYMode(void);
bogdanm 0:9b334a45a8ff 373
bogdanm 0:9b334a45a8ff 374 void HAL_PWR_EnableSleepOnExit(void);
bogdanm 0:9b334a45a8ff 375 void HAL_PWR_DisableSleepOnExit(void);
bogdanm 0:9b334a45a8ff 376 void HAL_PWR_EnableSEVOnPend(void);
bogdanm 0:9b334a45a8ff 377 void HAL_PWR_DisableSEVOnPend(void);
bogdanm 0:9b334a45a8ff 378
bogdanm 0:9b334a45a8ff 379
bogdanm 0:9b334a45a8ff 380
bogdanm 0:9b334a45a8ff 381 void HAL_PWR_PVD_IRQHandler(void);
bogdanm 0:9b334a45a8ff 382 void HAL_PWR_PVDCallback(void);
bogdanm 0:9b334a45a8ff 383 /**
bogdanm 0:9b334a45a8ff 384 * @}
bogdanm 0:9b334a45a8ff 385 */
bogdanm 0:9b334a45a8ff 386
bogdanm 0:9b334a45a8ff 387 /**
bogdanm 0:9b334a45a8ff 388 * @}
bogdanm 0:9b334a45a8ff 389 */
bogdanm 0:9b334a45a8ff 390
bogdanm 0:9b334a45a8ff 391 /**
bogdanm 0:9b334a45a8ff 392 * @}
bogdanm 0:9b334a45a8ff 393 */
bogdanm 0:9b334a45a8ff 394
bogdanm 0:9b334a45a8ff 395 /**
bogdanm 0:9b334a45a8ff 396 * @}
bogdanm 0:9b334a45a8ff 397 */
bogdanm 0:9b334a45a8ff 398
bogdanm 0:9b334a45a8ff 399 #ifdef __cplusplus
bogdanm 0:9b334a45a8ff 400 }
bogdanm 0:9b334a45a8ff 401 #endif
bogdanm 0:9b334a45a8ff 402
bogdanm 0:9b334a45a8ff 403
bogdanm 0:9b334a45a8ff 404 #endif /* __STM32F1xx_HAL_PWR_H */
bogdanm 0:9b334a45a8ff 405
bogdanm 0:9b334a45a8ff 406 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/