desp koval / mbed-rtos

Dependents:   Mecatro_Filtre

Committer:
mecatro_prod
Date:
Mon Mar 15 14:18:11 2021 +0000
Revision:
0:4a2c9c1f5b9e
Pas de changement

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mecatro_prod 0:4a2c9c1f5b9e 1 /*----------------------------------------------------------------------------
mecatro_prod 0:4a2c9c1f5b9e 2 * RL-ARM - RTX
mecatro_prod 0:4a2c9c1f5b9e 3 *----------------------------------------------------------------------------
mecatro_prod 0:4a2c9c1f5b9e 4 * Name: HAL_CM.C
mecatro_prod 0:4a2c9c1f5b9e 5 * Purpose: Hardware Abstraction Layer for ARM7TDMI
mecatro_prod 0:4a2c9c1f5b9e 6 * Rev.: V1.0
mecatro_prod 0:4a2c9c1f5b9e 7 *----------------------------------------------------------------------------
mecatro_prod 0:4a2c9c1f5b9e 8 *
mecatro_prod 0:4a2c9c1f5b9e 9 * Copyright (c) 1999-2009 KEIL, 2009-2015 ARM Germany GmbH
mecatro_prod 0:4a2c9c1f5b9e 10 * All rights reserved.
mecatro_prod 0:4a2c9c1f5b9e 11 * Redistribution and use in source and binary forms, with or without
mecatro_prod 0:4a2c9c1f5b9e 12 * modification, are permitted provided that the following conditions are met:
mecatro_prod 0:4a2c9c1f5b9e 13 * - Redistributions of source code must retain the above copyright
mecatro_prod 0:4a2c9c1f5b9e 14 * notice, this list of conditions and the following disclaimer.
mecatro_prod 0:4a2c9c1f5b9e 15 * - Redistributions in binary form must reproduce the above copyright
mecatro_prod 0:4a2c9c1f5b9e 16 * notice, this list of conditions and the following disclaimer in the
mecatro_prod 0:4a2c9c1f5b9e 17 * documentation and/or other materials provided with the distribution.
mecatro_prod 0:4a2c9c1f5b9e 18 * - Neither the name of ARM nor the names of its contributors may be used
mecatro_prod 0:4a2c9c1f5b9e 19 * to endorse or promote products derived from this software without
mecatro_prod 0:4a2c9c1f5b9e 20 * specific prior written permission.
mecatro_prod 0:4a2c9c1f5b9e 21 *
mecatro_prod 0:4a2c9c1f5b9e 22 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
mecatro_prod 0:4a2c9c1f5b9e 23 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
mecatro_prod 0:4a2c9c1f5b9e 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
mecatro_prod 0:4a2c9c1f5b9e 25 * ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
mecatro_prod 0:4a2c9c1f5b9e 26 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
mecatro_prod 0:4a2c9c1f5b9e 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
mecatro_prod 0:4a2c9c1f5b9e 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
mecatro_prod 0:4a2c9c1f5b9e 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
mecatro_prod 0:4a2c9c1f5b9e 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
mecatro_prod 0:4a2c9c1f5b9e 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
mecatro_prod 0:4a2c9c1f5b9e 32 * POSSIBILITY OF SUCH DAMAGE.
mecatro_prod 0:4a2c9c1f5b9e 33 *---------------------------------------------------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 34
mecatro_prod 0:4a2c9c1f5b9e 35 #include "rt_TypeDef.h"
mecatro_prod 0:4a2c9c1f5b9e 36 #include "RTX_Conf.h"
mecatro_prod 0:4a2c9c1f5b9e 37 #include "rt_HAL_CM.h"
mecatro_prod 0:4a2c9c1f5b9e 38
mecatro_prod 0:4a2c9c1f5b9e 39
mecatro_prod 0:4a2c9c1f5b9e 40 /*----------------------------------------------------------------------------
mecatro_prod 0:4a2c9c1f5b9e 41 * Global Variables
mecatro_prod 0:4a2c9c1f5b9e 42 *---------------------------------------------------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 43
mecatro_prod 0:4a2c9c1f5b9e 44 #ifdef DBG_MSG
mecatro_prod 0:4a2c9c1f5b9e 45 BIT dbg_msg;
mecatro_prod 0:4a2c9c1f5b9e 46 #endif
mecatro_prod 0:4a2c9c1f5b9e 47
mecatro_prod 0:4a2c9c1f5b9e 48 /*----------------------------------------------------------------------------
mecatro_prod 0:4a2c9c1f5b9e 49 * Functions
mecatro_prod 0:4a2c9c1f5b9e 50 *---------------------------------------------------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 51
mecatro_prod 0:4a2c9c1f5b9e 52
mecatro_prod 0:4a2c9c1f5b9e 53 /*--------------------------- rt_init_stack ---------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 54
mecatro_prod 0:4a2c9c1f5b9e 55 void rt_init_stack (P_TCB p_TCB, FUNCP task_body) {
mecatro_prod 0:4a2c9c1f5b9e 56 /* Prepare TCB and saved context for a first time start of a task. */
mecatro_prod 0:4a2c9c1f5b9e 57 U32 *stk,i,size;
mecatro_prod 0:4a2c9c1f5b9e 58
mecatro_prod 0:4a2c9c1f5b9e 59 /* Prepare a complete interrupt frame for first task start */
mecatro_prod 0:4a2c9c1f5b9e 60 size = p_TCB->priv_stack >> 2;
mecatro_prod 0:4a2c9c1f5b9e 61
mecatro_prod 0:4a2c9c1f5b9e 62 /* Write to the top of stack. */
mecatro_prod 0:4a2c9c1f5b9e 63 stk = &p_TCB->stack[size];
mecatro_prod 0:4a2c9c1f5b9e 64
mecatro_prod 0:4a2c9c1f5b9e 65 /* Auto correct to 8-byte ARM stack alignment. */
mecatro_prod 0:4a2c9c1f5b9e 66 if ((U32)stk & 0x04) {
mecatro_prod 0:4a2c9c1f5b9e 67 stk--;
mecatro_prod 0:4a2c9c1f5b9e 68 }
mecatro_prod 0:4a2c9c1f5b9e 69
mecatro_prod 0:4a2c9c1f5b9e 70 stk -= 16;
mecatro_prod 0:4a2c9c1f5b9e 71
mecatro_prod 0:4a2c9c1f5b9e 72 /* Default xPSR and initial PC */
mecatro_prod 0:4a2c9c1f5b9e 73 stk[15] = (U32)task_body + 4; /* add 4 byte offset because SUB PC, LR - 4 */
mecatro_prod 0:4a2c9c1f5b9e 74 stk[0] = INITIAL_xPSR;
mecatro_prod 0:4a2c9c1f5b9e 75
mecatro_prod 0:4a2c9c1f5b9e 76 /* Clear R0-R13/LR registers. */
mecatro_prod 0:4a2c9c1f5b9e 77 for (i = 1; i < 14; i++) {
mecatro_prod 0:4a2c9c1f5b9e 78 stk[i] = 0;
mecatro_prod 0:4a2c9c1f5b9e 79 }
mecatro_prod 0:4a2c9c1f5b9e 80
mecatro_prod 0:4a2c9c1f5b9e 81 /* Assign a void pointer to R0. */
mecatro_prod 0:4a2c9c1f5b9e 82 stk[TCB_STACK_R0_OFFSET_DWORDS] = (U32)p_TCB->msg;
mecatro_prod 0:4a2c9c1f5b9e 83
mecatro_prod 0:4a2c9c1f5b9e 84 /* Initial Task stack pointer. */
mecatro_prod 0:4a2c9c1f5b9e 85 p_TCB->tsk_stack = (U32)stk;
mecatro_prod 0:4a2c9c1f5b9e 86
mecatro_prod 0:4a2c9c1f5b9e 87 /* Task entry point. */
mecatro_prod 0:4a2c9c1f5b9e 88 p_TCB->ptask = task_body;
mecatro_prod 0:4a2c9c1f5b9e 89
mecatro_prod 0:4a2c9c1f5b9e 90 /* Set a magic word for checking of stack overflow.
mecatro_prod 0:4a2c9c1f5b9e 91 For the main thread (ID: 0x01) the stack is in a memory area shared with the
mecatro_prod 0:4a2c9c1f5b9e 92 heap, therefore the last word of the stack is a moving target.
mecatro_prod 0:4a2c9c1f5b9e 93 We want to do stack/heap collision detection instead.
mecatro_prod 0:4a2c9c1f5b9e 94 */
mecatro_prod 0:4a2c9c1f5b9e 95 if (p_TCB->task_id != 0x01)
mecatro_prod 0:4a2c9c1f5b9e 96 p_TCB->stack[0] = MAGIC_WORD;
mecatro_prod 0:4a2c9c1f5b9e 97 }
mecatro_prod 0:4a2c9c1f5b9e 98
mecatro_prod 0:4a2c9c1f5b9e 99
mecatro_prod 0:4a2c9c1f5b9e 100 /*--------------------------- rt_ret_val ----------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 101
mecatro_prod 0:4a2c9c1f5b9e 102 static __inline U32 *rt_ret_regs (P_TCB p_TCB) {
mecatro_prod 0:4a2c9c1f5b9e 103 /* Get pointer to task return value registers (R0..R3) in Stack */
mecatro_prod 0:4a2c9c1f5b9e 104
mecatro_prod 0:4a2c9c1f5b9e 105 /* Stack Frame: CPSR,R0-R13,PC */
mecatro_prod 0:4a2c9c1f5b9e 106 return (U32 *)(p_TCB->tsk_stack + TCB_STACK_R0_OFFSET_BYTES);
mecatro_prod 0:4a2c9c1f5b9e 107 }
mecatro_prod 0:4a2c9c1f5b9e 108
mecatro_prod 0:4a2c9c1f5b9e 109 void rt_ret_val (P_TCB p_TCB, U32 v0) {
mecatro_prod 0:4a2c9c1f5b9e 110 U32 *ret;
mecatro_prod 0:4a2c9c1f5b9e 111
mecatro_prod 0:4a2c9c1f5b9e 112 ret = rt_ret_regs(p_TCB);
mecatro_prod 0:4a2c9c1f5b9e 113 ret[0] = v0;
mecatro_prod 0:4a2c9c1f5b9e 114 }
mecatro_prod 0:4a2c9c1f5b9e 115
mecatro_prod 0:4a2c9c1f5b9e 116 void rt_ret_val2(P_TCB p_TCB, U32 v0, U32 v1) {
mecatro_prod 0:4a2c9c1f5b9e 117 U32 *ret;
mecatro_prod 0:4a2c9c1f5b9e 118
mecatro_prod 0:4a2c9c1f5b9e 119 ret = rt_ret_regs(p_TCB);
mecatro_prod 0:4a2c9c1f5b9e 120 ret[0] = v0;
mecatro_prod 0:4a2c9c1f5b9e 121 ret[1] = v1;
mecatro_prod 0:4a2c9c1f5b9e 122 }
mecatro_prod 0:4a2c9c1f5b9e 123
mecatro_prod 0:4a2c9c1f5b9e 124
mecatro_prod 0:4a2c9c1f5b9e 125 /*--------------------------- dbg_init --------------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 126
mecatro_prod 0:4a2c9c1f5b9e 127 #ifdef DBG_MSG
mecatro_prod 0:4a2c9c1f5b9e 128 void dbg_init (void) {
mecatro_prod 0:4a2c9c1f5b9e 129 if ((DEMCR & DEMCR_TRCENA) &&
mecatro_prod 0:4a2c9c1f5b9e 130 (ITM_CONTROL & ITM_ITMENA) &&
mecatro_prod 0:4a2c9c1f5b9e 131 (ITM_ENABLE & (1UL << 31))) {
mecatro_prod 0:4a2c9c1f5b9e 132 dbg_msg = __TRUE;
mecatro_prod 0:4a2c9c1f5b9e 133 }
mecatro_prod 0:4a2c9c1f5b9e 134 }
mecatro_prod 0:4a2c9c1f5b9e 135 #endif
mecatro_prod 0:4a2c9c1f5b9e 136
mecatro_prod 0:4a2c9c1f5b9e 137 /*--------------------------- dbg_task_notify -------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 138
mecatro_prod 0:4a2c9c1f5b9e 139 #ifdef DBG_MSG
mecatro_prod 0:4a2c9c1f5b9e 140 void dbg_task_notify (P_TCB p_tcb, BOOL create) {
mecatro_prod 0:4a2c9c1f5b9e 141 while (ITM_PORT31_U32 == 0);
mecatro_prod 0:4a2c9c1f5b9e 142 ITM_PORT31_U32 = (U32)p_tcb->ptask;
mecatro_prod 0:4a2c9c1f5b9e 143 while (ITM_PORT31_U32 == 0);
mecatro_prod 0:4a2c9c1f5b9e 144 ITM_PORT31_U16 = (create << 8) | p_tcb->task_id;
mecatro_prod 0:4a2c9c1f5b9e 145 }
mecatro_prod 0:4a2c9c1f5b9e 146 #endif
mecatro_prod 0:4a2c9c1f5b9e 147
mecatro_prod 0:4a2c9c1f5b9e 148 /*--------------------------- dbg_task_switch -------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 149
mecatro_prod 0:4a2c9c1f5b9e 150 #ifdef DBG_MSG
mecatro_prod 0:4a2c9c1f5b9e 151 void dbg_task_switch (U32 task_id) {
mecatro_prod 0:4a2c9c1f5b9e 152 while (ITM_PORT31_U32 == 0);
mecatro_prod 0:4a2c9c1f5b9e 153 ITM_PORT31_U8 = task_id;
mecatro_prod 0:4a2c9c1f5b9e 154 }
mecatro_prod 0:4a2c9c1f5b9e 155 #endif
mecatro_prod 0:4a2c9c1f5b9e 156
mecatro_prod 0:4a2c9c1f5b9e 157
mecatro_prod 0:4a2c9c1f5b9e 158 /*----------------------------------------------------------------------------
mecatro_prod 0:4a2c9c1f5b9e 159 * end of file
mecatro_prod 0:4a2c9c1f5b9e 160 *---------------------------------------------------------------------------*/
mecatro_prod 0:4a2c9c1f5b9e 161