3D Low Frequency Wakeup Receiver
AS3933.h@1:944583d4b1de, 2018-03-07 (annotated)
- Committer:
- mcm
- Date:
- Wed Mar 07 13:56:26 2018 +0000
- Revision:
- 1:944583d4b1de
- Parent:
- 0:19b363e50103
- Child:
- 3:2de552c4ffbc
The header file seems to be ready to be tested.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
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mcm | 1:944583d4b1de | 1 | /** |
mcm | 1:944583d4b1de | 2 | * @brief AS3933.h |
mcm | 1:944583d4b1de | 3 | * @details 3D Low Frequency Wakeup Receiver. |
mcm | 1:944583d4b1de | 4 | * Header file. |
mcm | 1:944583d4b1de | 5 | * |
mcm | 1:944583d4b1de | 6 | * |
mcm | 1:944583d4b1de | 7 | * @return N/A |
mcm | 1:944583d4b1de | 8 | * |
mcm | 1:944583d4b1de | 9 | * @author Manuel Caballero |
mcm | 1:944583d4b1de | 10 | * @date 7/March/2018 |
mcm | 1:944583d4b1de | 11 | * @version 7/March/2018 The ORIGIN |
mcm | 1:944583d4b1de | 12 | * @pre N/A. |
mcm | 1:944583d4b1de | 13 | * @warning N/A |
mcm | 1:944583d4b1de | 14 | * @pre This code belongs to Nimbus Centre ( http://unbarquero.blogspot.com ). |
mcm | 1:944583d4b1de | 15 | */ |
mcm | 1:944583d4b1de | 16 | #ifndef AS3933_H |
mcm | 1:944583d4b1de | 17 | #define AS3933_H |
mcm | 1:944583d4b1de | 18 | |
mcm | 1:944583d4b1de | 19 | #include "mbed.h" |
mcm | 1:944583d4b1de | 20 | /** |
mcm | 1:944583d4b1de | 21 | Example: |
mcm | 1:944583d4b1de | 22 | |
mcm | 1:944583d4b1de | 23 | [TODO] |
mcm | 1:944583d4b1de | 24 | |
mcm | 1:944583d4b1de | 25 | */ |
mcm | 1:944583d4b1de | 26 | |
mcm | 1:944583d4b1de | 27 | |
mcm | 1:944583d4b1de | 28 | /*! |
mcm | 1:944583d4b1de | 29 | Library for the AS3933 3D Low Frequency Wakeup Receiver. |
mcm | 1:944583d4b1de | 30 | */ |
mcm | 1:944583d4b1de | 31 | class AS3933 |
mcm | 1:944583d4b1de | 32 | { |
mcm | 1:944583d4b1de | 33 | public: |
mcm | 1:944583d4b1de | 34 | /* SPI COMMAND STRUCTURE */ |
mcm | 1:944583d4b1de | 35 | /** |
mcm | 1:944583d4b1de | 36 | * @brief MODE. ( B15:B14 ) |
mcm | 1:944583d4b1de | 37 | */ |
mcm | 1:944583d4b1de | 38 | typedef enum { |
mcm | 1:944583d4b1de | 39 | AS3933_WRITE = ( 0x00 << 6 ), /*!< WRITE */ |
mcm | 1:944583d4b1de | 40 | AS3933_READ = ( 0x01 << 6 ), /*!< READ */ |
mcm | 1:944583d4b1de | 41 | AS3933_DIRECT_COMMAND = ( 0x03 << 6 ) /*!< DIRECT COMMAND */ |
mcm | 1:944583d4b1de | 42 | } AS3933_spi_command_structure_mode_t; |
mcm | 1:944583d4b1de | 43 | |
mcm | 1:944583d4b1de | 44 | |
mcm | 1:944583d4b1de | 45 | /** |
mcm | 1:944583d4b1de | 46 | * @brief READ/WRITE REGISTER ( B13:B8 ) |
mcm | 1:944583d4b1de | 47 | */ |
mcm | 1:944583d4b1de | 48 | typedef enum { |
mcm | 1:944583d4b1de | 49 | AS3933_R0 = 0x00, /*!< R0 register */ |
mcm | 1:944583d4b1de | 50 | AS3933_R1 = 0x01, /*!< R1 register */ |
mcm | 1:944583d4b1de | 51 | AS3933_R2 = 0x02, /*!< R3 register */ |
mcm | 1:944583d4b1de | 52 | AS3933_R3 = 0x03, /*!< R4 register */ |
mcm | 1:944583d4b1de | 53 | AS3933_R4 = 0x04, /*!< R5 register */ |
mcm | 1:944583d4b1de | 54 | AS3933_R5 = 0x05, /*!< R6 register */ |
mcm | 1:944583d4b1de | 55 | AS3933_R6 = 0x06, /*!< R7 register */ |
mcm | 1:944583d4b1de | 56 | AS3933_R7 = 0x07, /*!< R8 register */ |
mcm | 1:944583d4b1de | 57 | AS3933_R8 = 0x08, /*!< R9 register */ |
mcm | 1:944583d4b1de | 58 | AS3933_R9 = 0x09, /*!< R10 register */ |
mcm | 1:944583d4b1de | 59 | AS3933_R10 = 0x0A, /*!< R11 register */ |
mcm | 1:944583d4b1de | 60 | AS3933_R11 = 0x0B, /*!< R11 register */ |
mcm | 1:944583d4b1de | 61 | AS3933_R12 = 0x0C, /*!< R12 register */ |
mcm | 1:944583d4b1de | 62 | AS3933_R13 = 0x0D, /*!< R13 register */ |
mcm | 1:944583d4b1de | 63 | AS3933_R14 = 0x0E, /*!< R14 register */ |
mcm | 1:944583d4b1de | 64 | AS3933_R15 = 0x0F, /*!< R15 register */ |
mcm | 1:944583d4b1de | 65 | AS3933_R16 = 0x10, /*!< R16 register */ |
mcm | 1:944583d4b1de | 66 | AS3933_R17 = 0x11, /*!< R17 register */ |
mcm | 1:944583d4b1de | 67 | AS3933_R18 = 0x12, /*!< R18 register */ |
mcm | 1:944583d4b1de | 68 | AS3933_R19 = 0x13 /*!< R19 register */ |
mcm | 1:944583d4b1de | 69 | } AS3933_spi_command_structure_registers_t; |
mcm | 1:944583d4b1de | 70 | |
mcm | 1:944583d4b1de | 71 | |
mcm | 1:944583d4b1de | 72 | /* SPI DIRECT COMMANDS */ |
mcm | 1:944583d4b1de | 73 | /** |
mcm | 1:944583d4b1de | 74 | * @brief DIRECT COMMANDS. ( B13:B8 ) |
mcm | 1:944583d4b1de | 75 | */ |
mcm | 1:944583d4b1de | 76 | typedef enum { |
mcm | 1:944583d4b1de | 77 | CLEAR_WAKE = 0x00, /*!< Clears the wake state of the chip. In case the chip has woken up ( WAKE pin is high ) the chip is set back to listening mode */ |
mcm | 1:944583d4b1de | 78 | RESET_RSSI = 0x01, /*!< Resets the RSSI measurement */ |
mcm | 1:944583d4b1de | 79 | CALIB_RC_OSC = 0x02, /*!< Starts the trimming procedure of the internal RC oscillator */ |
mcm | 1:944583d4b1de | 80 | CLEAR_FALSE = 0x03, /*!< Resets the false wakeup register ( R13 = 00 ) */ |
mcm | 1:944583d4b1de | 81 | PRESET_DEFAULT = 0x04, /*!< Sets all register in the default mode */ |
mcm | 1:944583d4b1de | 82 | CALIB_RCO_LC = 0x05 /*!< Calibration of the RC-oscillator with the external LC tank */ |
mcm | 1:944583d4b1de | 83 | } AS3933_spi_direct_commands_t; |
mcm | 1:944583d4b1de | 84 | |
mcm | 1:944583d4b1de | 85 | |
mcm | 1:944583d4b1de | 86 | /* R0 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 87 | /** |
mcm | 1:944583d4b1de | 88 | * @brief PATT32 ( R0<7> ). Pattern extended to 32 bits |
mcm | 1:944583d4b1de | 89 | * |
mcm | 1:944583d4b1de | 90 | * NOTE: Default value: PATT32_16_BITS |
mcm | 1:944583d4b1de | 91 | */ |
mcm | 1:944583d4b1de | 92 | typedef enum { |
mcm | 1:944583d4b1de | 93 | PATT32_MASK = ( 1 << 7 ), /*!< PATT32 mask */ |
mcm | 1:944583d4b1de | 94 | PATT32_16_BITS = ( 0 << 7 ), /*!< 16-bits pattern extended */ |
mcm | 1:944583d4b1de | 95 | PATT32_32_BITS = ( 1 << 7 ) /*!< 32-bits pattern extended */ |
mcm | 1:944583d4b1de | 96 | } AS3933_r0_patt32_value_t; |
mcm | 1:944583d4b1de | 97 | |
mcm | 1:944583d4b1de | 98 | |
mcm | 1:944583d4b1de | 99 | /** |
mcm | 1:944583d4b1de | 100 | * @brief DAT_MASK ( R0<6> ). Masks data on DAT pin before wakeup happens |
mcm | 1:944583d4b1de | 101 | * |
mcm | 1:944583d4b1de | 102 | * NOTE: Default value: DAT_MASK_DISABLED |
mcm | 1:944583d4b1de | 103 | */ |
mcm | 1:944583d4b1de | 104 | typedef enum { |
mcm | 1:944583d4b1de | 105 | DAT_MASK_MASK = ( 1 << 6 ), /*!< DAT_MASK mask */ |
mcm | 1:944583d4b1de | 106 | DAT_MASK_DISABLED = ( 0 << 6 ), /*!< Data is not masked on DAT pin */ |
mcm | 1:944583d4b1de | 107 | DAT_MASK_ENABLED = ( 1 << 6 ) /*!< Data is masked on DAT pin */ |
mcm | 1:944583d4b1de | 108 | } AS3933_r0_dat_mask_value_t; |
mcm | 1:944583d4b1de | 109 | |
mcm | 1:944583d4b1de | 110 | |
mcm | 1:944583d4b1de | 111 | /** |
mcm | 1:944583d4b1de | 112 | * @brief ON_OFF ( R0<5> ). On/Off operation mode. ( Duty-cycle defined in the register R4<7:6> ) |
mcm | 1:944583d4b1de | 113 | * |
mcm | 1:944583d4b1de | 114 | * NOTE: Default value: ON_OFF_DISABLED |
mcm | 1:944583d4b1de | 115 | */ |
mcm | 1:944583d4b1de | 116 | typedef enum { |
mcm | 1:944583d4b1de | 117 | ON_OFF_MASK = ( 1 << 5 ), /*!< ON_OFF mask */ |
mcm | 1:944583d4b1de | 118 | ON_OFF_DISABLED = ( 0 << 5 ), /*!< ON_OFF is disabled */ |
mcm | 1:944583d4b1de | 119 | ON_OFF_ENABLED = ( 1 << 5 ) /*!< ON_OFF is enabled */ |
mcm | 1:944583d4b1de | 120 | } AS3933_r0_on_off_value_t; |
mcm | 1:944583d4b1de | 121 | |
mcm | 1:944583d4b1de | 122 | |
mcm | 1:944583d4b1de | 123 | /** |
mcm | 1:944583d4b1de | 124 | * @brief MUX_123 ( R0<4> ). Scan mode enable |
mcm | 1:944583d4b1de | 125 | * |
mcm | 1:944583d4b1de | 126 | * NOTE: Default value: MUX_123_DISABLED |
mcm | 1:944583d4b1de | 127 | */ |
mcm | 1:944583d4b1de | 128 | typedef enum { |
mcm | 1:944583d4b1de | 129 | MUX_123_MASK = ( 1 << 4 ), /*!< MUX_123 mask */ |
mcm | 1:944583d4b1de | 130 | MUX_123_DISABLED = ( 0 << 4 ), /*!< Scan mode enable is disabled */ |
mcm | 1:944583d4b1de | 131 | MUX_123_ENABLED = ( 1 << 4 ) /*!< Scan mode enable is enabled */ |
mcm | 1:944583d4b1de | 132 | } AS3933_r0_mux_123_value_t; |
mcm | 1:944583d4b1de | 133 | |
mcm | 1:944583d4b1de | 134 | |
mcm | 1:944583d4b1de | 135 | /** |
mcm | 1:944583d4b1de | 136 | * @brief EN_A2 ( R0<3> ). Channel 2 enable |
mcm | 1:944583d4b1de | 137 | * |
mcm | 1:944583d4b1de | 138 | * NOTE: Default value: EN_A2_ENABLED |
mcm | 1:944583d4b1de | 139 | */ |
mcm | 1:944583d4b1de | 140 | typedef enum { |
mcm | 1:944583d4b1de | 141 | EN_A2_MASK = ( 1 << 3 ), /*!< EN_A2 mask */ |
mcm | 1:944583d4b1de | 142 | EN_A2_DISABLED = ( 0 << 3 ), /*!< Channel 2 is disabled */ |
mcm | 1:944583d4b1de | 143 | EN_A2_ENABLED = ( 1 << 3 ) /*!< Channel 2 is enabled */ |
mcm | 1:944583d4b1de | 144 | } AS3933_r0_en_a2_value_t; |
mcm | 1:944583d4b1de | 145 | |
mcm | 1:944583d4b1de | 146 | |
mcm | 1:944583d4b1de | 147 | /** |
mcm | 1:944583d4b1de | 148 | * @brief EN_A3 ( R0<2> ). Channel 3 enable |
mcm | 1:944583d4b1de | 149 | * |
mcm | 1:944583d4b1de | 150 | * NOTE: Default value: EN_A3_ENABLED |
mcm | 1:944583d4b1de | 151 | */ |
mcm | 1:944583d4b1de | 152 | typedef enum { |
mcm | 1:944583d4b1de | 153 | EN_A3_MASK = ( 1 << 2 ), /*!< EN_A3 mask */ |
mcm | 1:944583d4b1de | 154 | EN_A3_DISABLED = ( 0 << 2 ), /*!< Channel 3 is disabled */ |
mcm | 1:944583d4b1de | 155 | EN_A3_ENABLED = ( 1 << 2 ) /*!< Channel 3 is enabled */ |
mcm | 1:944583d4b1de | 156 | } AS3933_r0_en_a3_value_t; |
mcm | 1:944583d4b1de | 157 | |
mcm | 1:944583d4b1de | 158 | |
mcm | 1:944583d4b1de | 159 | /** |
mcm | 1:944583d4b1de | 160 | * @brief EN_A1 ( R0<1> ). Channel 1 enable |
mcm | 1:944583d4b1de | 161 | * |
mcm | 1:944583d4b1de | 162 | * NOTE: Default value: EN_A1_ENABLED |
mcm | 1:944583d4b1de | 163 | */ |
mcm | 1:944583d4b1de | 164 | typedef enum { |
mcm | 1:944583d4b1de | 165 | EN_A1_MASK = ( 1 << 1 ), /*!< EN_A1 mask */ |
mcm | 1:944583d4b1de | 166 | EN_A1_DISABLED = ( 0 << 1 ), /*!< Channel 1 is disabled */ |
mcm | 1:944583d4b1de | 167 | EN_A1_ENABLED = ( 1 << 1 ) /*!< Channel 1 is enabled */ |
mcm | 1:944583d4b1de | 168 | } AS3933_r0_en_a1_value_t; |
mcm | 1:944583d4b1de | 169 | |
mcm | 1:944583d4b1de | 170 | |
mcm | 1:944583d4b1de | 171 | /* R1 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 172 | /** |
mcm | 1:944583d4b1de | 173 | * @brief ABS_HY ( R1<7> ). Enable Data slicer absolute reference |
mcm | 1:944583d4b1de | 174 | * |
mcm | 1:944583d4b1de | 175 | * NOTE: Default value: ABS_HY_DISABLED |
mcm | 1:944583d4b1de | 176 | */ |
mcm | 1:944583d4b1de | 177 | typedef enum { |
mcm | 1:944583d4b1de | 178 | ABS_HY_MASK = ( 1 << 7 ), /*!< ABS_HY mask */ |
mcm | 1:944583d4b1de | 179 | ABS_HY_DISABLED = ( 0 << 7 ), /*!< Data slicer absolute reference is disabled */ |
mcm | 1:944583d4b1de | 180 | ABS_HY_ENABLED = ( 1 << 7 ) /*!< Data slicer absolute reference is enabled */ |
mcm | 1:944583d4b1de | 181 | } AS3933_r1_abs_hy_value_t; |
mcm | 1:944583d4b1de | 182 | |
mcm | 1:944583d4b1de | 183 | |
mcm | 1:944583d4b1de | 184 | /** |
mcm | 1:944583d4b1de | 185 | * @brief AGC_TLIM ( R1<6> ). AGC acting only on the first carrier burst |
mcm | 1:944583d4b1de | 186 | * |
mcm | 1:944583d4b1de | 187 | * NOTE: Default value: AGC_TLIM_DISABLED |
mcm | 1:944583d4b1de | 188 | */ |
mcm | 1:944583d4b1de | 189 | typedef enum { |
mcm | 1:944583d4b1de | 190 | AGC_TLIM_MASK = ( 1 << 6 ), /*!< AGC_TLIM mask */ |
mcm | 1:944583d4b1de | 191 | AGC_TLIM_DISABLED = ( 0 << 6 ), /*!< AGC is disabled */ |
mcm | 1:944583d4b1de | 192 | AGC_TLIM_ENABLED = ( 1 << 6 ) /*!< AGC is enabled */ |
mcm | 1:944583d4b1de | 193 | } AS3933_r1_agc_tlim_value_t; |
mcm | 1:944583d4b1de | 194 | |
mcm | 1:944583d4b1de | 195 | |
mcm | 1:944583d4b1de | 196 | /** |
mcm | 1:944583d4b1de | 197 | * @brief AGC_UD ( R1<5> ). AGC operating in both direction (up-down) |
mcm | 1:944583d4b1de | 198 | * |
mcm | 1:944583d4b1de | 199 | * NOTE: Default value: AGC_UD_UP_DOWN_MODE |
mcm | 1:944583d4b1de | 200 | */ |
mcm | 1:944583d4b1de | 201 | typedef enum { |
mcm | 1:944583d4b1de | 202 | AGC_UD_MASK = ( 1 << 5 ), /*!< AGC_UD mask */ |
mcm | 1:944583d4b1de | 203 | AGC_UD_DOWN_MODE = ( 0 << 5 ), /*!< AGC down mode only */ |
mcm | 1:944583d4b1de | 204 | AGC_UD_UP_DOWN_MODE = ( 1 << 5 ) /*!< AGC up and down mode */ |
mcm | 1:944583d4b1de | 205 | } AS3933_r1_agc_ud_value_t; |
mcm | 1:944583d4b1de | 206 | |
mcm | 1:944583d4b1de | 207 | |
mcm | 1:944583d4b1de | 208 | /** |
mcm | 1:944583d4b1de | 209 | * @brief ATT_ON ( R1<4> ). Antenna damper enable |
mcm | 1:944583d4b1de | 210 | * |
mcm | 1:944583d4b1de | 211 | * NOTE: Default value: ATT_ON_DISABLED |
mcm | 1:944583d4b1de | 212 | */ |
mcm | 1:944583d4b1de | 213 | typedef enum { |
mcm | 1:944583d4b1de | 214 | ATT_ON_MASK = ( 1 << 4 ), /*!< ATT_ON mask */ |
mcm | 1:944583d4b1de | 215 | ATT_ON_DISABLED = ( 0 << 4 ), /*!< Antenna damper disabled */ |
mcm | 1:944583d4b1de | 216 | ATT_ON_ENABLED = ( 1 << 4 ) /*!< Antenna damper enabled */ |
mcm | 1:944583d4b1de | 217 | } AS3933_r1_att_on_value_t; |
mcm | 1:944583d4b1de | 218 | |
mcm | 1:944583d4b1de | 219 | |
mcm | 1:944583d4b1de | 220 | /** |
mcm | 1:944583d4b1de | 221 | * @brief EN_MANCH ( R1<3> ). Manchester decoder enable |
mcm | 1:944583d4b1de | 222 | * |
mcm | 1:944583d4b1de | 223 | * NOTE: Default value: EN_MANCH_DISABLED |
mcm | 1:944583d4b1de | 224 | */ |
mcm | 1:944583d4b1de | 225 | typedef enum { |
mcm | 1:944583d4b1de | 226 | EN_MANCH_MASK = ( 1 << 3 ), /*!< EN_MANCH mask */ |
mcm | 1:944583d4b1de | 227 | EN_MANCH_DISABLED = ( 0 << 3 ), /*!< Manchester decoder disabled */ |
mcm | 1:944583d4b1de | 228 | EN_MANCH_ENABLED = ( 1 << 3 ) /*!< Manchester decoder enabled */ |
mcm | 1:944583d4b1de | 229 | } AS3933_r1_en_manch_value_t; |
mcm | 1:944583d4b1de | 230 | |
mcm | 1:944583d4b1de | 231 | |
mcm | 1:944583d4b1de | 232 | /** |
mcm | 1:944583d4b1de | 233 | * @brief EN_PAT2 ( R1<2> ). Double wakeup pattern correlation |
mcm | 1:944583d4b1de | 234 | * |
mcm | 1:944583d4b1de | 235 | * NOTE: Default value: EN_PAT2_DISABLED |
mcm | 1:944583d4b1de | 236 | */ |
mcm | 1:944583d4b1de | 237 | typedef enum { |
mcm | 1:944583d4b1de | 238 | EN_PAT2_MASK = ( 1 << 2 ), /*!< EN_PAT2 mask */ |
mcm | 1:944583d4b1de | 239 | EN_PAT2_DISABLED = ( 0 << 2 ), /*!< Double wakeup pattern correlation disabled */ |
mcm | 1:944583d4b1de | 240 | EN_PAT2_ENABLED = ( 1 << 2 ) /*!< Double wakeup pattern correlation enabled */ |
mcm | 1:944583d4b1de | 241 | } AS3933_r1_en_pat2_value_t; |
mcm | 1:944583d4b1de | 242 | |
mcm | 1:944583d4b1de | 243 | |
mcm | 1:944583d4b1de | 244 | /** |
mcm | 1:944583d4b1de | 245 | * @brief EN_WPAT ( R1<1> ). Correlator enable |
mcm | 1:944583d4b1de | 246 | * |
mcm | 1:944583d4b1de | 247 | * NOTE: Default value: EN_WPAT_ENABLED |
mcm | 1:944583d4b1de | 248 | */ |
mcm | 1:944583d4b1de | 249 | typedef enum { |
mcm | 1:944583d4b1de | 250 | EN_WPAT_MASK = ( 1 << 1 ), /*!< EN_WPAT mask */ |
mcm | 1:944583d4b1de | 251 | EN_WPAT_DISABLED = ( 0 << 1 ), /*!< Correlator disabled */ |
mcm | 1:944583d4b1de | 252 | EN_WPAT_ENABLED = ( 1 << 1 ) /*!< Correlator enabled */ |
mcm | 1:944583d4b1de | 253 | } AS3933_r1_en_wpat_value_t; |
mcm | 1:944583d4b1de | 254 | |
mcm | 1:944583d4b1de | 255 | |
mcm | 1:944583d4b1de | 256 | /** |
mcm | 1:944583d4b1de | 257 | * @brief EN_XTAL ( R1<0> ). Crystal oscillator enable |
mcm | 1:944583d4b1de | 258 | * |
mcm | 1:944583d4b1de | 259 | * NOTE: Default value: EN_XTAL_ENABLED |
mcm | 1:944583d4b1de | 260 | */ |
mcm | 1:944583d4b1de | 261 | typedef enum { |
mcm | 1:944583d4b1de | 262 | EN_XTAL_MASK = ( 1 << 0 ), /*!< EN_XTAL mask */ |
mcm | 1:944583d4b1de | 263 | EN_XTAL_DISABLED = ( 0 << 0 ), /*!< Crystal oscillator disabled */ |
mcm | 1:944583d4b1de | 264 | EN_XTAL_ENABLED = ( 1 << 0 ) /*!< Crystal oscillator enabled */ |
mcm | 1:944583d4b1de | 265 | } AS3933_r1_en_xtal_value_t; |
mcm | 1:944583d4b1de | 266 | |
mcm | 1:944583d4b1de | 267 | |
mcm | 1:944583d4b1de | 268 | /* R2 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 269 | /** |
mcm | 1:944583d4b1de | 270 | * @brief S_ABSH ( R2<7> ). Data slicer absolute threshold reduction |
mcm | 1:944583d4b1de | 271 | * |
mcm | 1:944583d4b1de | 272 | * NOTE: Default value: S_ABSH_DISABLED |
mcm | 1:944583d4b1de | 273 | */ |
mcm | 1:944583d4b1de | 274 | typedef enum { |
mcm | 1:944583d4b1de | 275 | S_ABSH_MASK = ( 1 << 7 ), /*!< S_ABSH mask */ |
mcm | 1:944583d4b1de | 276 | S_ABSH_DISABLED = ( 0 << 7 ), /*!< Data slicer absolute threshold reduction is disabled */ |
mcm | 1:944583d4b1de | 277 | S_ABSH_ENABLED = ( 1 << 7 ) /*!< Data slicer absolute threshold reduction is enabled */ |
mcm | 1:944583d4b1de | 278 | } AS3933_r2_s_absh_value_t; |
mcm | 1:944583d4b1de | 279 | |
mcm | 1:944583d4b1de | 280 | |
mcm | 1:944583d4b1de | 281 | /** |
mcm | 1:944583d4b1de | 282 | * @brief EN_EXT_CLK ( R2<6> ). Enables external clock generator |
mcm | 1:944583d4b1de | 283 | * |
mcm | 1:944583d4b1de | 284 | * NOTE: Default value: EN_EXT_CLK_DISABLED |
mcm | 1:944583d4b1de | 285 | */ |
mcm | 1:944583d4b1de | 286 | typedef enum { |
mcm | 1:944583d4b1de | 287 | EN_EXT_CLK_MASK = ( 1 << 6 ), /*!< EN_EXT_CLK mask */ |
mcm | 1:944583d4b1de | 288 | EN_EXT_CLK_DISABLED = ( 0 << 6 ), /*!< Enables external clock generator is disabled */ |
mcm | 1:944583d4b1de | 289 | EN_EXT_CLK_ENABLED = ( 1 << 6 ) /*!< Enables external clock generator is enabled */ |
mcm | 1:944583d4b1de | 290 | } AS3933_r2_en_ext_clk_value_t; |
mcm | 1:944583d4b1de | 291 | |
mcm | 1:944583d4b1de | 292 | |
mcm | 1:944583d4b1de | 293 | /** |
mcm | 1:944583d4b1de | 294 | * @brief G_BOOST ( R2<5> ). +3dB Amplifier Gain Boost |
mcm | 1:944583d4b1de | 295 | * |
mcm | 1:944583d4b1de | 296 | * NOTE: Default value: G_BOOST_DISABLED |
mcm | 1:944583d4b1de | 297 | */ |
mcm | 1:944583d4b1de | 298 | typedef enum { |
mcm | 1:944583d4b1de | 299 | G_BOOST_MASK = ( 1 << 5 ), /*!< G_BOOST mask */ |
mcm | 1:944583d4b1de | 300 | G_BOOST_DISABLED = ( 0 << 5 ), /*!< Gain Boost is disabled */ |
mcm | 1:944583d4b1de | 301 | G_BOOST_ENABLED = ( 1 << 5 ) /*!< Gain Boost is enabled */ |
mcm | 1:944583d4b1de | 302 | } AS3933_r2_g_boost_value_t; |
mcm | 1:944583d4b1de | 303 | |
mcm | 1:944583d4b1de | 304 | |
mcm | 1:944583d4b1de | 305 | /** |
mcm | 1:944583d4b1de | 306 | * @brief S_WU1 ( R2<1:0> ). Tolerance setting for the stage wakeup ( 20 to 150 kHz ) |
mcm | 1:944583d4b1de | 307 | * |
mcm | 1:944583d4b1de | 308 | * NOTE: Default value: S_WU1_20_150_KHZ_TOLERANCE_16_3 |
mcm | 1:944583d4b1de | 309 | */ |
mcm | 1:944583d4b1de | 310 | typedef enum { |
mcm | 1:944583d4b1de | 311 | S_WU1_20_150_KHZ_MASK = ( 0b11 << 0 ), /*!< S_WU1 mask ( 20 to 150 kHz ) */ |
mcm | 1:944583d4b1de | 312 | S_WU1_20_150_KHZ_TOLERANCE_16_3 = ( 0b00 << 0 ), /*!< M = 8 +/- 3 */ |
mcm | 1:944583d4b1de | 313 | S_WU1_20_150_KHZ_TOLERANCE_16_2 = ( 0b01 << 0 ), /*!< M = 8 +/- 2 */ |
mcm | 1:944583d4b1de | 314 | S_WU1_20_150_KHZ_TOLERANCE_16_1 = ( 0b10 << 0 ) /*!< M = 8 +/- 1 */ |
mcm | 1:944583d4b1de | 315 | } AS3933_r2_s_wu1_20_150_khz_value_t; |
mcm | 1:944583d4b1de | 316 | |
mcm | 1:944583d4b1de | 317 | |
mcm | 1:944583d4b1de | 318 | |
mcm | 1:944583d4b1de | 319 | /** |
mcm | 1:944583d4b1de | 320 | * @brief S_WU1 ( R2<1:0> ). Tolerance setting for the stage wakeup ( 15 to 20 kHz ) |
mcm | 1:944583d4b1de | 321 | * |
mcm | 1:944583d4b1de | 322 | * NOTE: Default value: S_WU1_15_20_KHZ_TOLERANCE_8_3 |
mcm | 1:944583d4b1de | 323 | */ |
mcm | 1:944583d4b1de | 324 | typedef enum { |
mcm | 1:944583d4b1de | 325 | S_WU1_15_20_KHZ_MASK = ( 0b11 << 0 ), /*!< S_WU1 mask ( 15 to 20 kHz ) */ |
mcm | 1:944583d4b1de | 326 | S_WU1_15_20_KHZ_TOLERANCE_8_3 = ( 0b00 << 0 ), /*!< M = 8 +/- 3 */ |
mcm | 1:944583d4b1de | 327 | S_WU1_15_20_KHZ_TOLERANCE_8_2 = ( 0b01 << 0 ), /*!< M = 8 +/- 2 */ |
mcm | 1:944583d4b1de | 328 | S_WU1_15_20_KHZ_TOLERANCE_8_1 = ( 0b10 << 0 ) /*!< M = 8 +/- 1 */ |
mcm | 1:944583d4b1de | 329 | } AS3933_r2_s_wu1_15_20_khz_value_t; |
mcm | 1:944583d4b1de | 330 | |
mcm | 1:944583d4b1de | 331 | |
mcm | 1:944583d4b1de | 332 | /* R3 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 333 | /** |
mcm | 1:944583d4b1de | 334 | * @brief HY_20m ( R3<7> ). Data slicer hysteresis |
mcm | 1:944583d4b1de | 335 | * |
mcm | 1:944583d4b1de | 336 | * NOTE: Default value: HY_20M_COMPARATOR_HYSTERESIS_40MV |
mcm | 1:944583d4b1de | 337 | */ |
mcm | 1:944583d4b1de | 338 | typedef enum { |
mcm | 1:944583d4b1de | 339 | HY_20M_MASK = ( 1 << 7 ), /*!< HY_20m mask */ |
mcm | 1:944583d4b1de | 340 | HY_20M_COMPARATOR_HYSTERESIS_40MV = ( 0 << 7 ), /*!< Comparator hysteresis = 40mV */ |
mcm | 1:944583d4b1de | 341 | HY_20M_COMPARATOR_HYSTERESIS_20MV = ( 1 << 7 ) /*!< Comparator hysteresis = 20mV */ |
mcm | 1:944583d4b1de | 342 | } AS3933_r3_hy_20m_value_t; |
mcm | 1:944583d4b1de | 343 | |
mcm | 1:944583d4b1de | 344 | |
mcm | 1:944583d4b1de | 345 | /** |
mcm | 1:944583d4b1de | 346 | * @brief HY_POS ( R3<6> ). Data slicer hysteresis |
mcm | 1:944583d4b1de | 347 | * |
mcm | 1:944583d4b1de | 348 | * NOTE: Default value: HY_POS_HYSTERESIS_POSITIVE_EDGES |
mcm | 1:944583d4b1de | 349 | */ |
mcm | 1:944583d4b1de | 350 | typedef enum { |
mcm | 1:944583d4b1de | 351 | HY_POS_MASK = ( 1 << 6 ), /*!< HY_POS mask */ |
mcm | 1:944583d4b1de | 352 | HY_POS_HYSTERESIS_POSITIVE_EDGES = ( 0 << 6 ), /*!< Hysteresis only positive edges */ |
mcm | 1:944583d4b1de | 353 | HY_POS_HYSTERESIS_BOTH_EDGES = ( 1 << 6 ) /*!< Hysteresis positive and negative edges */ |
mcm | 1:944583d4b1de | 354 | } AS3933_r3_hy_pos_value_t; |
mcm | 1:944583d4b1de | 355 | |
mcm | 1:944583d4b1de | 356 | |
mcm | 1:944583d4b1de | 357 | /** |
mcm | 1:944583d4b1de | 358 | * @brief FS_SCL ( R3<3:5> ). Data slices time constant |
mcm | 1:944583d4b1de | 359 | * |
mcm | 1:944583d4b1de | 360 | * NOTE: Default value: FS_SCL_PREAMBLE_LENGTH_2_3 |
mcm | 1:944583d4b1de | 361 | */ |
mcm | 1:944583d4b1de | 362 | typedef enum { |
mcm | 1:944583d4b1de | 363 | FS_SCL_MASK = ( 0b111 << 3 ), /*!< FS_SCL mask */ |
mcm | 1:944583d4b1de | 364 | FS_SCL_PREAMBLE_LENGTH_0_8 = ( 0b000 << 3 ), /*!< Minimum Preamble Length: 0.8ms */ |
mcm | 1:944583d4b1de | 365 | FS_SCL_PREAMBLE_LENGTH_1_15 = ( 0b001 << 3 ), /*!< Minimum Preamble Length: 1.15ms */ |
mcm | 1:944583d4b1de | 366 | FS_SCL_PREAMBLE_LENGTH_1_55 = ( 0b010 << 3 ), /*!< Minimum Preamble Length: 1.55ms */ |
mcm | 1:944583d4b1de | 367 | FS_SCL_PREAMBLE_LENGTH_1_9 = ( 0b011 << 3 ), /*!< Minimum Preamble Length: 1.9ms */ |
mcm | 1:944583d4b1de | 368 | FS_SCL_PREAMBLE_LENGTH_2_3 = ( 0b100 << 3 ), /*!< Minimum Preamble Length: 2.3ms */ |
mcm | 1:944583d4b1de | 369 | FS_SCL_PREAMBLE_LENGTH_2_65 = ( 0b101 << 3 ), /*!< Minimum Preamble Length: 2.65ms */ |
mcm | 1:944583d4b1de | 370 | FS_SCL_PREAMBLE_LENGTH_3 = ( 0b110 << 3 ), /*!< Minimum Preamble Length: 3ms */ |
mcm | 1:944583d4b1de | 371 | FS_SCL_PREAMBLE_LENGTH_3_5 = ( 0b111 << 3 ) /*!< Minimum Preamble Length: 3.5ms */ |
mcm | 1:944583d4b1de | 372 | } AS3933_r3_fs_scl_value_t; |
mcm | 1:944583d4b1de | 373 | |
mcm | 1:944583d4b1de | 374 | |
mcm | 1:944583d4b1de | 375 | /** |
mcm | 1:944583d4b1de | 376 | * @brief FS_ENV ( R3<2:0> ). Envelop detector time constant |
mcm | 1:944583d4b1de | 377 | * |
mcm | 1:944583d4b1de | 378 | * NOTE: Default value: FS_ENV_SYMBOL_RATE_4096 |
mcm | 1:944583d4b1de | 379 | */ |
mcm | 1:944583d4b1de | 380 | typedef enum { |
mcm | 1:944583d4b1de | 381 | FS_ENV_MASK = ( 0b111 << 0 ), /*!< FS_ENV mask */ |
mcm | 1:944583d4b1de | 382 | FS_ENV_SYMBOL_RATE_4096 = ( 0b000 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 4096 */ |
mcm | 1:944583d4b1de | 383 | FS_ENV_SYMBOL_RATE_2184 = ( 0b001 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 2184 */ |
mcm | 1:944583d4b1de | 384 | FS_ENV_SYMBOL_RATE_1490 = ( 0b010 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 1490 */ |
mcm | 1:944583d4b1de | 385 | FS_ENV_SYMBOL_RATE_1130 = ( 0b011 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 1130 */ |
mcm | 1:944583d4b1de | 386 | FS_ENV_SYMBOL_RATE_910 = ( 0b100 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 910 */ |
mcm | 1:944583d4b1de | 387 | FS_ENV_SYMBOL_RATE_762 = ( 0b101 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 762 */ |
mcm | 1:944583d4b1de | 388 | FS_ENV_SYMBOL_RATE_655 = ( 0b110 << 0 ), /*!< Symbol Rate [Manchester symbol/s]: 655 */ |
mcm | 1:944583d4b1de | 389 | FS_ENV_SYMBOL_RATE_512 = ( 0b111 << 0 ) /*!< Symbol Rate [Manchester symbol/s]: 512 */ |
mcm | 1:944583d4b1de | 390 | } AS3933_r3_fs_env_value_t; |
mcm | 1:944583d4b1de | 391 | |
mcm | 1:944583d4b1de | 392 | |
mcm | 1:944583d4b1de | 393 | /* R4 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 394 | /** |
mcm | 1:944583d4b1de | 395 | * @brief T_OFF ( R4<7:6> ). Off time in ON/OFF operation mode |
mcm | 1:944583d4b1de | 396 | * |
mcm | 1:944583d4b1de | 397 | * NOTE: Default value: T_OFF_1_MS |
mcm | 1:944583d4b1de | 398 | */ |
mcm | 1:944583d4b1de | 399 | typedef enum { |
mcm | 1:944583d4b1de | 400 | T_OFF_MASK = ( 0b11 << 6 ), /*!< T_OFF mask */ |
mcm | 1:944583d4b1de | 401 | T_OFF_1_MS = ( 0b00 << 6 ), /*!< Off time: 1ms */ |
mcm | 1:944583d4b1de | 402 | T_OFF_2_MS = ( 0b01 << 6 ), /*!< Off time: 2ms */ |
mcm | 1:944583d4b1de | 403 | T_OFF_4_MS = ( 0b10 << 6 ), /*!< Off time: 4ms */ |
mcm | 1:944583d4b1de | 404 | T_OFF_8_MS = ( 0b11 << 6 ) /*!< Off time: 8ms */ |
mcm | 1:944583d4b1de | 405 | } AS3933_r4_t_off_value_t; |
mcm | 1:944583d4b1de | 406 | |
mcm | 1:944583d4b1de | 407 | |
mcm | 1:944583d4b1de | 408 | /** |
mcm | 1:944583d4b1de | 409 | * @brief D_RES ( R4<5:4> ). Antenna damping resistor ( Shunt Resistor ( parallel to the resonator at 125 kHz ) ) |
mcm | 1:944583d4b1de | 410 | * |
mcm | 1:944583d4b1de | 411 | * NOTE: Default value: D_RES_PARALLEL_SHUNT_RESISTOR_3_KOHM |
mcm | 1:944583d4b1de | 412 | */ |
mcm | 1:944583d4b1de | 413 | typedef enum { |
mcm | 1:944583d4b1de | 414 | D_RES_MASK = ( 0b11 << 4 ), /*!< D_RES mask */ |
mcm | 1:944583d4b1de | 415 | D_RES_PARALLEL_SHUNT_RESISTOR_1_KOHM = ( 0b00 << 4 ), /*!< Shunt Resistor: 1kOhm */ |
mcm | 1:944583d4b1de | 416 | D_RES_PARALLEL_SHUNT_RESISTOR_3_KOHM = ( 0b01 << 4 ), /*!< Shunt Resistor: 3kOhm */ |
mcm | 1:944583d4b1de | 417 | D_RES_PARALLEL_SHUNT_RESISTOR_9_KOHM = ( 0b10 << 4 ), /*!< Shunt Resistor: 9kOhm */ |
mcm | 1:944583d4b1de | 418 | D_RES_PARALLEL_SHUNT_RESISTOR_27_KOHM = ( 0b11 << 4 ) /*!< Shunt Resistor: 27kOhm */ |
mcm | 1:944583d4b1de | 419 | } AS3933_r4_d_res_value_t; |
mcm | 1:944583d4b1de | 420 | |
mcm | 1:944583d4b1de | 421 | |
mcm | 1:944583d4b1de | 422 | /** |
mcm | 1:944583d4b1de | 423 | * @brief GR ( R4<3:0> ). Gain reduction |
mcm | 1:944583d4b1de | 424 | * |
mcm | 1:944583d4b1de | 425 | * NOTE: Default value: GR_GAIN_REDUCTION_NO_GAIN_REDUCTION |
mcm | 1:944583d4b1de | 426 | */ |
mcm | 1:944583d4b1de | 427 | typedef enum { |
mcm | 1:944583d4b1de | 428 | GR_MASK = ( 0b1111 << 0 ), /*!< GR mask */ |
mcm | 1:944583d4b1de | 429 | GR_GAIN_REDUCTION_NO_GAIN_REDUCTION = ( 0b0000 << 0 ), /*!< No Gain Reduction */ |
mcm | 1:944583d4b1de | 430 | GR_GAIN_REDUCTION_MINUS_4_DB = ( 0b0100 << 0 ), /*!< Gain Reduction: -4dB */ |
mcm | 1:944583d4b1de | 431 | GR_GAIN_REDUCTION_MINUS_8_DB = ( 0b0110 << 0 ), /*!< Gain Reduction: -8dB */ |
mcm | 1:944583d4b1de | 432 | GR_GAIN_REDUCTION_MINUS_12_DB = ( 0b1000 << 0 ), /*!< Gain Reduction: -12dB */ |
mcm | 1:944583d4b1de | 433 | GR_GAIN_REDUCTION_MINUS_16_DB = ( 0b1010 << 0 ), /*!< Gain Reduction: -16dB */ |
mcm | 1:944583d4b1de | 434 | GR_GAIN_REDUCTION_MINUS_20_DB = ( 0b1100 << 0 ), /*!< Gain Reduction: -20dB */ |
mcm | 1:944583d4b1de | 435 | GR_GAIN_REDUCTION_MINUS_24_DB = ( 0b1110 << 0 ) /*!< Gain Reduction: -24dB */ |
mcm | 1:944583d4b1de | 436 | } AS3933_r4_gr_value_t; |
mcm | 1:944583d4b1de | 437 | |
mcm | 1:944583d4b1de | 438 | |
mcm | 1:944583d4b1de | 439 | /* R5 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 440 | /** |
mcm | 1:944583d4b1de | 441 | * @brief TS2 ( R5<7:0> ). 2nd Byte of wakeup pattern |
mcm | 1:944583d4b1de | 442 | * |
mcm | 1:944583d4b1de | 443 | * NOTE: Default value: TS2_WAKEUP_PATTERN_MSB |
mcm | 1:944583d4b1de | 444 | */ |
mcm | 1:944583d4b1de | 445 | typedef enum { |
mcm | 1:944583d4b1de | 446 | TS2_PATT2B_MASK = ( 0xFF << 0 ), /*!< TS2 mask */ |
mcm | 1:944583d4b1de | 447 | TS2_WAKEUP_PATTERN_PATT2B = ( 0b01101001 << 0 ) /*!< Default value */ |
mcm | 1:944583d4b1de | 448 | } AS3933_r5_ts2_value_t; |
mcm | 1:944583d4b1de | 449 | |
mcm | 1:944583d4b1de | 450 | |
mcm | 1:944583d4b1de | 451 | /* R6 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 452 | /** |
mcm | 1:944583d4b1de | 453 | * @brief TS1 ( R6<7:0> ). 1st Byte of wakeup pattern |
mcm | 1:944583d4b1de | 454 | * |
mcm | 1:944583d4b1de | 455 | * NOTE: Default value: TS1_WAKEUP_PATTERN_LSB |
mcm | 1:944583d4b1de | 456 | */ |
mcm | 1:944583d4b1de | 457 | typedef enum { |
mcm | 1:944583d4b1de | 458 | TS1_PATT1B_MASK = ( 0xFF << 0 ), /*!< TS1 mask */ |
mcm | 1:944583d4b1de | 459 | TS1_WAKEUP_PATTERN_PATT1B = ( 0b10010110 << 0 ) /*!< Default value */ |
mcm | 1:944583d4b1de | 460 | } AS3933_r6_ts2_value_t; |
mcm | 1:944583d4b1de | 461 | |
mcm | 1:944583d4b1de | 462 | |
mcm | 1:944583d4b1de | 463 | /* R7 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 464 | /** |
mcm | 1:944583d4b1de | 465 | * @brief T_OUT ( R7<7:5> ). Automatic time-out |
mcm | 1:944583d4b1de | 466 | * |
mcm | 1:944583d4b1de | 467 | * NOTE: Default value: T_OUT_0_SEC |
mcm | 1:944583d4b1de | 468 | */ |
mcm | 1:944583d4b1de | 469 | typedef enum { |
mcm | 1:944583d4b1de | 470 | T_OUT_MASK = ( 0b111 << 5 ), /*!< T_OUT mask */ |
mcm | 1:944583d4b1de | 471 | T_OUT_0_SEC = ( 0b000 << 5 ), /*!< Timeout: 0sec */ |
mcm | 1:944583d4b1de | 472 | T_OUT_50_MSEC = ( 0b001 << 5 ), /*!< Timeout: 50msec */ |
mcm | 1:944583d4b1de | 473 | T_OUT_100_MSEC = ( 0b010 << 5 ), /*!< Timeout: 100mecs */ |
mcm | 1:944583d4b1de | 474 | T_OUT_150_MSEC = ( 0b011 << 5 ), /*!< Timeout: 150msec */ |
mcm | 1:944583d4b1de | 475 | T_OUT_200_MSEC = ( 0b100 << 5 ), /*!< Timeout: 200msec */ |
mcm | 1:944583d4b1de | 476 | T_OUT_250_MSEC = ( 0b101 << 5 ), /*!< Timeout: 250msec */ |
mcm | 1:944583d4b1de | 477 | T_OUT_300_MSEC = ( 0b110 << 5 ), /*!< Timeout: 300msec */ |
mcm | 1:944583d4b1de | 478 | T_OUT_350_MSEC = ( 0b111 << 5 ) /*!< Timeout: 350msec */ |
mcm | 1:944583d4b1de | 479 | } AS3933_r7_t_out_value_t; |
mcm | 1:944583d4b1de | 480 | |
mcm | 1:944583d4b1de | 481 | |
mcm | 1:944583d4b1de | 482 | /** |
mcm | 1:944583d4b1de | 483 | * @brief T_HBIT ( R7<4:0> ). Bit rate definition |
mcm | 1:944583d4b1de | 484 | * |
mcm | 1:944583d4b1de | 485 | * NOTE: Default value: T_HBIT_BIT_RATE_12 |
mcm | 1:944583d4b1de | 486 | */ |
mcm | 1:944583d4b1de | 487 | typedef enum { |
mcm | 1:944583d4b1de | 488 | T_HBIT_MASK = ( 0b11111 << 0 ), /*!< T_HBIT mask */ |
mcm | 1:944583d4b1de | 489 | T_HBIT_BIT_RATE_4 = ( 0b00011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 4 */ |
mcm | 1:944583d4b1de | 490 | T_HBIT_BIT_RATE_5 = ( 0b00100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 5 */ |
mcm | 1:944583d4b1de | 491 | T_HBIT_BIT_RATE_6 = ( 0b00101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 6 */ |
mcm | 1:944583d4b1de | 492 | T_HBIT_BIT_RATE_7 = ( 0b00110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 7 */ |
mcm | 1:944583d4b1de | 493 | T_HBIT_BIT_RATE_8 = ( 0b00111 << 0 ), /*!< Bit Duration in Clock Generator Periods: 8 */ |
mcm | 1:944583d4b1de | 494 | T_HBIT_BIT_RATE_9 = ( 0b01000 << 0 ), /*!< Bit Duration in Clock Generator Periods: 9 */ |
mcm | 1:944583d4b1de | 495 | T_HBIT_BIT_RATE_10 = ( 0b01001 << 0 ), /*!< Bit Duration in Clock Generator Periods: 10 */ |
mcm | 1:944583d4b1de | 496 | T_HBIT_BIT_RATE_11 = ( 0b01010 << 0 ), /*!< Bit Duration in Clock Generator Periods: 11 */ |
mcm | 1:944583d4b1de | 497 | T_HBIT_BIT_RATE_12 = ( 0b01011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 12 */ |
mcm | 1:944583d4b1de | 498 | T_HBIT_BIT_RATE_13 = ( 0b01100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 13 */ |
mcm | 1:944583d4b1de | 499 | T_HBIT_BIT_RATE_14 = ( 0b01101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 14 */ |
mcm | 1:944583d4b1de | 500 | T_HBIT_BIT_RATE_15 = ( 0b01110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 15 */ |
mcm | 1:944583d4b1de | 501 | T_HBIT_BIT_RATE_16 = ( 0b01111 << 0 ), /*!< Bit Duration in Clock Generator Periods: 16 */ |
mcm | 1:944583d4b1de | 502 | T_HBIT_BIT_RATE_17 = ( 0b10000 << 0 ), /*!< Bit Duration in Clock Generator Periods: 17 */ |
mcm | 1:944583d4b1de | 503 | T_HBIT_BIT_RATE_18 = ( 0b10001 << 0 ), /*!< Bit Duration in Clock Generator Periods: 18 */ |
mcm | 1:944583d4b1de | 504 | T_HBIT_BIT_RATE_19 = ( 0b10010 << 0 ), /*!< Bit Duration in Clock Generator Periods: 19 */ |
mcm | 1:944583d4b1de | 505 | T_HBIT_BIT_RATE_20 = ( 0b10011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 20 */ |
mcm | 1:944583d4b1de | 506 | T_HBIT_BIT_RATE_21 = ( 0b10100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 21 */ |
mcm | 1:944583d4b1de | 507 | T_HBIT_BIT_RATE_22 = ( 0b10101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 22 */ |
mcm | 1:944583d4b1de | 508 | T_HBIT_BIT_RATE_23 = ( 0b10110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 23 */ |
mcm | 1:944583d4b1de | 509 | T_HBIT_BIT_RATE_24 = ( 0b10111 << 0 ), /*!< Bit Duration in Clock Generator Periods: 24 */ |
mcm | 1:944583d4b1de | 510 | T_HBIT_BIT_RATE_25 = ( 0b11000 << 0 ), /*!< Bit Duration in Clock Generator Periods: 25 */ |
mcm | 1:944583d4b1de | 511 | T_HBIT_BIT_RATE_26 = ( 0b11001 << 0 ), /*!< Bit Duration in Clock Generator Periods: 26 */ |
mcm | 1:944583d4b1de | 512 | T_HBIT_BIT_RATE_27 = ( 0b11010 << 0 ), /*!< Bit Duration in Clock Generator Periods: 27 */ |
mcm | 1:944583d4b1de | 513 | T_HBIT_BIT_RATE_28 = ( 0b11011 << 0 ), /*!< Bit Duration in Clock Generator Periods: 28 */ |
mcm | 1:944583d4b1de | 514 | T_HBIT_BIT_RATE_29 = ( 0b11100 << 0 ), /*!< Bit Duration in Clock Generator Periods: 29 */ |
mcm | 1:944583d4b1de | 515 | T_HBIT_BIT_RATE_30 = ( 0b11101 << 0 ), /*!< Bit Duration in Clock Generator Periods: 30 */ |
mcm | 1:944583d4b1de | 516 | T_HBIT_BIT_RATE_31 = ( 0b11110 << 0 ), /*!< Bit Duration in Clock Generator Periods: 31 */ |
mcm | 1:944583d4b1de | 517 | T_HBIT_BIT_RATE_32 = ( 0b11111 << 0 ) /*!< Bit Duration in Clock Generator Periods: 32 */ |
mcm | 1:944583d4b1de | 518 | } AS3933_r7_t_hbit_value_t; |
mcm | 1:944583d4b1de | 519 | |
mcm | 1:944583d4b1de | 520 | |
mcm | 1:944583d4b1de | 521 | /* R8 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 522 | /** |
mcm | 1:944583d4b1de | 523 | * @brief BAND_SEL ( R8<7:5> ). Band selection |
mcm | 1:944583d4b1de | 524 | * |
mcm | 1:944583d4b1de | 525 | * NOTE: Default value: BAND_SEL_RANGE_95_150_KHZ |
mcm | 1:944583d4b1de | 526 | */ |
mcm | 1:944583d4b1de | 527 | typedef enum { |
mcm | 1:944583d4b1de | 528 | BAND_SEL_MASK = ( 0b111 << 5 ), /*!< BAND_SEL mask */ |
mcm | 1:944583d4b1de | 529 | BAND_SEL_RANGE_95_150_KHZ = ( 0b000 << 5 ), /*!< N = 4, Operating Frequency Range [kHz]: 95-150 */ |
mcm | 1:944583d4b1de | 530 | BAND_SEL_RANGE_65_95_KHZ = ( 0b000 << 5 ), /*!< N = 6, Operating Frequency Range [kHz]: 65-95 */ |
mcm | 1:944583d4b1de | 531 | BAND_SEL_RANGE_40_65_KHZ = ( 0b000 << 5 ), /*!< N = 10, Operating Frequency Range [kHz]: 40-65 */ |
mcm | 1:944583d4b1de | 532 | BAND_SEL_RANGE_23_40_KHZ = ( 0b000 << 5 ), /*!< N = 18, Operating Frequency Range [kHz]: 23-40 */ |
mcm | 1:944583d4b1de | 533 | BAND_SEL_RANGE_15_23_KHZ = ( 0b000 << 5 ) /*!< N = 14, Operating Frequency Range [kHz]: 15-23 */ |
mcm | 1:944583d4b1de | 534 | } AS3933_r8_band_sel_value_t; |
mcm | 1:944583d4b1de | 535 | |
mcm | 1:944583d4b1de | 536 | |
mcm | 1:944583d4b1de | 537 | /** |
mcm | 1:944583d4b1de | 538 | * @brief T_AUTO ( R8<2:0> ). Artificial wake-up |
mcm | 1:944583d4b1de | 539 | * |
mcm | 1:944583d4b1de | 540 | * NOTE: Default value: T_AUTO_NO_ARTIFICIAL_WAKEUP |
mcm | 1:944583d4b1de | 541 | */ |
mcm | 1:944583d4b1de | 542 | typedef enum { |
mcm | 1:944583d4b1de | 543 | T_AUTO_MASK = ( 0b111 << 0 ), /*!< T_AUTO mask */ |
mcm | 1:944583d4b1de | 544 | T_AUTO_NO_ARTIFICIAL_WAKEUP = ( 0b000 << 0 ), /*!< No artificial wake-up */ |
mcm | 1:944583d4b1de | 545 | T_AUTO_ARTIFICIAL_WAKEUP_1_SEC = ( 0b001 << 0 ), /*!< Artificial wake-up 1sec */ |
mcm | 1:944583d4b1de | 546 | T_AUTO_ARTIFICIAL_WAKEUP_5_SEC = ( 0b010 << 0 ), /*!< Artificial wake-up 5sec */ |
mcm | 1:944583d4b1de | 547 | T_AUTO_ARTIFICIAL_WAKEUP_20_SEC = ( 0b011 << 0 ), /*!< Artificial wake-up 20sec */ |
mcm | 1:944583d4b1de | 548 | T_AUTO_ARTIFICIAL_WAKEUP_2_MIN = ( 0b100 << 0 ), /*!< Artificial wake-up 2min */ |
mcm | 1:944583d4b1de | 549 | T_AUTO_ARTIFICIAL_WAKEUP_15_MIN = ( 0b101 << 0 ), /*!< Artificial wake-up 15min */ |
mcm | 1:944583d4b1de | 550 | T_AUTO_ARTIFICIAL_WAKEUP_1_HOUR = ( 0b110 << 0 ), /*!< Artificial wake-up 1hour */ |
mcm | 1:944583d4b1de | 551 | T_AUTO_ARTIFICIAL_WAKEUP_2_HOUR = ( 0b111 << 0 ), /*!< Artificial wake-up 2hour */ |
mcm | 1:944583d4b1de | 552 | } AS3933_r8_t_auto_value_t; |
mcm | 1:944583d4b1de | 553 | |
mcm | 1:944583d4b1de | 554 | |
mcm | 1:944583d4b1de | 555 | /* R9 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 556 | /** |
mcm | 1:944583d4b1de | 557 | * @brief BLOCK_AGC ( R9<7> ). Disables AGC |
mcm | 1:944583d4b1de | 558 | * |
mcm | 1:944583d4b1de | 559 | * NOTE: Default value: BLOCK_AGC_ENABLED |
mcm | 1:944583d4b1de | 560 | */ |
mcm | 1:944583d4b1de | 561 | typedef enum { |
mcm | 1:944583d4b1de | 562 | BLOCK_AGC_MASK = ( 1 << 7 ), /*!< BLOCK_AGC mask */ |
mcm | 1:944583d4b1de | 563 | BLOCK_AGC_DISABLED = ( 1 << 7 ), /*!< AGC is disabled */ |
mcm | 1:944583d4b1de | 564 | BLOCK_AGC_ENABLED = ( 0 << 7 ) /*!< AGC is enabled */ |
mcm | 1:944583d4b1de | 565 | } AS3933_r9_block_agc_value_t; |
mcm | 1:944583d4b1de | 566 | |
mcm | 1:944583d4b1de | 567 | |
mcm | 1:944583d4b1de | 568 | |
mcm | 1:944583d4b1de | 569 | /* R10 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 570 | /** |
mcm | 1:944583d4b1de | 571 | * @brief RSSI1 ( R10<4:0> ). RSSI channel 1 |
mcm | 1:944583d4b1de | 572 | * |
mcm | 1:944583d4b1de | 573 | */ |
mcm | 1:944583d4b1de | 574 | typedef enum { |
mcm | 1:944583d4b1de | 575 | RSSI1_MASK = ( 0b11111 << 0 ) /*!< RSSI1 mask */ |
mcm | 1:944583d4b1de | 576 | } AS3933_r10_rssi1_value_t; |
mcm | 1:944583d4b1de | 577 | |
mcm | 1:944583d4b1de | 578 | |
mcm | 1:944583d4b1de | 579 | /* R11 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 580 | /** |
mcm | 1:944583d4b1de | 581 | * @brief RSSI3 ( R11<4:0> ). RSSI channel 3 |
mcm | 1:944583d4b1de | 582 | * |
mcm | 1:944583d4b1de | 583 | */ |
mcm | 1:944583d4b1de | 584 | typedef enum { |
mcm | 1:944583d4b1de | 585 | RSSI3_MASK = ( 0b11111 << 0 ) /*!< RSSI3 mask */ |
mcm | 1:944583d4b1de | 586 | } AS3933_r11_rssi3_value_t; |
mcm | 1:944583d4b1de | 587 | |
mcm | 1:944583d4b1de | 588 | |
mcm | 1:944583d4b1de | 589 | /* R12 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 590 | /** |
mcm | 1:944583d4b1de | 591 | * @brief RSSI2 ( R11<4:0> ). RSSI channel 2 |
mcm | 1:944583d4b1de | 592 | * |
mcm | 1:944583d4b1de | 593 | */ |
mcm | 1:944583d4b1de | 594 | typedef enum { |
mcm | 1:944583d4b1de | 595 | RSSI2_MASK = ( 0b11111 << 0 ) /*!< RSSI2 mask */ |
mcm | 1:944583d4b1de | 596 | } AS3933_r11_rssi2_value_t; |
mcm | 1:944583d4b1de | 597 | |
mcm | 1:944583d4b1de | 598 | |
mcm | 1:944583d4b1de | 599 | /* R14 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 600 | /** |
mcm | 1:944583d4b1de | 601 | * @brief RC_CAL_KO ( R14<7> ). Unsuccessful RC calibration |
mcm | 1:944583d4b1de | 602 | * |
mcm | 1:944583d4b1de | 603 | */ |
mcm | 1:944583d4b1de | 604 | typedef enum { |
mcm | 1:944583d4b1de | 605 | RC_CAL_KO_MASK = ( 1 << 7 ), /*!< RC_CAL_KO mask */ |
mcm | 1:944583d4b1de | 606 | RC_CAL_KO_HIGH = ( 1 << 7 ), /*!< RC_CAL_KO Unsuccessful RC calibration */ |
mcm | 1:944583d4b1de | 607 | RC_CAL_KO_LOW = ( 0 << 7 ) /*!< RC_CAL_KO Reset state */ |
mcm | 1:944583d4b1de | 608 | } AS3933_r14_rc_cal_ko_value_t; |
mcm | 1:944583d4b1de | 609 | |
mcm | 1:944583d4b1de | 610 | |
mcm | 1:944583d4b1de | 611 | /** |
mcm | 1:944583d4b1de | 612 | * @brief RC_CAL_OK ( R14<6> ). Successful RC calibration |
mcm | 1:944583d4b1de | 613 | * |
mcm | 1:944583d4b1de | 614 | */ |
mcm | 1:944583d4b1de | 615 | typedef enum { |
mcm | 1:944583d4b1de | 616 | RC_CAL_OK_MASK = ( 1 << 6 ), /*!< RC_CAL_OK mask */ |
mcm | 1:944583d4b1de | 617 | RC_CAL_OK_HIGH = ( 1 << 6 ), /*!< RC_CAL_OK Successful RC calibration */ |
mcm | 1:944583d4b1de | 618 | RC_CAL_OK_LOW = ( 0 << 6 ) /*!< RC_CAL_OK Reset state */ |
mcm | 1:944583d4b1de | 619 | } AS3933_r14_rc_cal_ok_value_t; |
mcm | 1:944583d4b1de | 620 | |
mcm | 1:944583d4b1de | 621 | |
mcm | 1:944583d4b1de | 622 | /** |
mcm | 1:944583d4b1de | 623 | * @brief RC_OSC_TAPS ( R14<5:0> ). RC-Oscillator taps setting |
mcm | 1:944583d4b1de | 624 | * |
mcm | 1:944583d4b1de | 625 | */ |
mcm | 1:944583d4b1de | 626 | typedef enum { |
mcm | 1:944583d4b1de | 627 | RC_OSC_TAPS_MASK = ( 0b111111 << 0 ) /*!< RC_OSC_TAPS mask */ |
mcm | 1:944583d4b1de | 628 | } AS3933_r14_rc_osc_taps_value_t; |
mcm | 1:944583d4b1de | 629 | |
mcm | 1:944583d4b1de | 630 | |
mcm | 1:944583d4b1de | 631 | /* R15 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 632 | /** |
mcm | 1:944583d4b1de | 633 | * @brief LC_OSC_KO ( R15<7> ). LC-Oscillator not working |
mcm | 1:944583d4b1de | 634 | * |
mcm | 1:944583d4b1de | 635 | */ |
mcm | 1:944583d4b1de | 636 | typedef enum { |
mcm | 1:944583d4b1de | 637 | LC_OSC_KO_MASK = ( 1 << 7 ), /*!< LC_OSC_KO mask */ |
mcm | 1:944583d4b1de | 638 | LC_OSC_KO_HIGH = ( 1 << 7 ), /*!< LC-Oscillator not working */ |
mcm | 1:944583d4b1de | 639 | LC_OSC_KO_LOW = ( 0 << 7 ) /*!< LC_OSC_KO Reset state */ |
mcm | 1:944583d4b1de | 640 | } AS3933_r15_lc_osc_ko_value_t; |
mcm | 1:944583d4b1de | 641 | |
mcm | 1:944583d4b1de | 642 | |
mcm | 1:944583d4b1de | 643 | /** |
mcm | 1:944583d4b1de | 644 | * @brief LC_OSC_OK ( R15<6> ). LC-Oscillator working |
mcm | 1:944583d4b1de | 645 | * |
mcm | 1:944583d4b1de | 646 | */ |
mcm | 1:944583d4b1de | 647 | typedef enum { |
mcm | 1:944583d4b1de | 648 | LC_OSC_OK_MASK = ( 1 << 6 ), /*!< LC_OSC_OK mask */ |
mcm | 1:944583d4b1de | 649 | LC_OSC_OK_HIGH = ( 1 << 6 ), /*!< LC_OSC_OK LC-Oscillator working */ |
mcm | 1:944583d4b1de | 650 | LC_OSC_OK_LOW = ( 0 << 6 ) /*!< LC_OSC_OK Reset state */ |
mcm | 1:944583d4b1de | 651 | } AS3933_r15_lc_osc_ok_value_t; |
mcm | 1:944583d4b1de | 652 | |
mcm | 1:944583d4b1de | 653 | |
mcm | 1:944583d4b1de | 654 | /* R16 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 655 | /** |
mcm | 1:944583d4b1de | 656 | * @brief CLOCK_GEN_DIS ( R16<7> ). The Clock Generator output signal displayed on CL_DAT pin |
mcm | 1:944583d4b1de | 657 | * |
mcm | 1:944583d4b1de | 658 | * NOTE: Default value: CLOCK_GEN_DIS_DISABLED |
mcm | 1:944583d4b1de | 659 | */ |
mcm | 1:944583d4b1de | 660 | typedef enum { |
mcm | 1:944583d4b1de | 661 | CLOCK_GEN_DIS_MASK = ( 1 << 7 ), /*!< CLOCK_GEN_DIS mask */ |
mcm | 1:944583d4b1de | 662 | CLOCK_GEN_DIS_ENABLED = ( 1 << 7 ), /*!< CLOCK on CL_DAT pin */ |
mcm | 1:944583d4b1de | 663 | CLOCK_GEN_DIS_DISABLED = ( 0 << 7 ) /*!< NO CLOCK on CL_DAT pin */ |
mcm | 1:944583d4b1de | 664 | } AS3933_r16_clock_gen_dis_value_t; |
mcm | 1:944583d4b1de | 665 | |
mcm | 1:944583d4b1de | 666 | |
mcm | 1:944583d4b1de | 667 | /** |
mcm | 1:944583d4b1de | 668 | * @brief LC_OSC_DIS ( R16<6> ). The LC-oscillator output signal displayed on DAT pin |
mcm | 1:944583d4b1de | 669 | * |
mcm | 1:944583d4b1de | 670 | * NOTE: Default value: LC_OSC_DIS_DISABLED |
mcm | 1:944583d4b1de | 671 | */ |
mcm | 1:944583d4b1de | 672 | typedef enum { |
mcm | 1:944583d4b1de | 673 | LC_OSC_DIS_MASK = ( 1 << 6 ), /*!< LC_OSC_DIS mask */ |
mcm | 1:944583d4b1de | 674 | LC_OSC_DIS_ENABLED = ( 1 << 6 ), /*!< LC-CLOCK on CL_DAT pin */ |
mcm | 1:944583d4b1de | 675 | LC_OSC_DIS_DISABLED = ( 0 << 6 ) /*!< NO LC-CLOCK on CL_DAT pin */ |
mcm | 1:944583d4b1de | 676 | } AS3933_r16_lc_osc_dis_value_t; |
mcm | 1:944583d4b1de | 677 | |
mcm | 1:944583d4b1de | 678 | |
mcm | 1:944583d4b1de | 679 | |
mcm | 1:944583d4b1de | 680 | /** |
mcm | 1:944583d4b1de | 681 | * @brief RC_OSC_MIN ( R16<5> ). Sets the RC-oscillator to minimum frequency |
mcm | 1:944583d4b1de | 682 | * |
mcm | 1:944583d4b1de | 683 | * NOTE: Default value: RC_OSC_MIN_DISABLED |
mcm | 1:944583d4b1de | 684 | */ |
mcm | 1:944583d4b1de | 685 | typedef enum { |
mcm | 1:944583d4b1de | 686 | RC_OSC_MIN_MASK = ( 1 << 5 ), /*!< RC_OSC_MIN mask */ |
mcm | 1:944583d4b1de | 687 | RC_OSC_MIN_ENABLED = ( 1 << 5 ), /*!< RC-oscillator to minimum frequency enabled */ |
mcm | 1:944583d4b1de | 688 | RC_OSC_MIN_DISABLED = ( 0 << 5 ) /*!< RC-oscillator to minimum frequency disabled */ |
mcm | 1:944583d4b1de | 689 | } AS3933_r16_rc_osc_min_value_t; |
mcm | 1:944583d4b1de | 690 | |
mcm | 1:944583d4b1de | 691 | |
mcm | 1:944583d4b1de | 692 | /** |
mcm | 1:944583d4b1de | 693 | * @brief RC_OSC_MIN ( R16<4> ). Sets the RC-oscillator to maximum frequency |
mcm | 1:944583d4b1de | 694 | * |
mcm | 1:944583d4b1de | 695 | * NOTE: Default value: RC_OSC_MAX_DISABLED |
mcm | 1:944583d4b1de | 696 | */ |
mcm | 1:944583d4b1de | 697 | typedef enum { |
mcm | 1:944583d4b1de | 698 | RC_OSC_MAX_MASK = ( 1 << 4 ), /*!< RC_OSC_MAX mask */ |
mcm | 1:944583d4b1de | 699 | RC_OSC_MAX_ENABLED = ( 1 << 4 ), /*!< RC-oscillator to maximum frequency enabled */ |
mcm | 1:944583d4b1de | 700 | RC_OSC_MAX_DISABLED = ( 0 << 4 ) /*!< RC-oscillator to maximum frequency disabled */ |
mcm | 1:944583d4b1de | 701 | } AS3933_r16_rc_osc_max_value_t; |
mcm | 1:944583d4b1de | 702 | |
mcm | 1:944583d4b1de | 703 | |
mcm | 1:944583d4b1de | 704 | /** |
mcm | 1:944583d4b1de | 705 | * @brief LC_OSC_MUX3 ( R16<2> ). Connects LF3P to the LCO |
mcm | 1:944583d4b1de | 706 | * |
mcm | 1:944583d4b1de | 707 | * NOTE: Default value: LC_OSC_MUX3_LF3P_AND_LCO_DISCONNECTED |
mcm | 1:944583d4b1de | 708 | */ |
mcm | 1:944583d4b1de | 709 | typedef enum { |
mcm | 1:944583d4b1de | 710 | LC_OSC_MUX3_MASK = ( 1 << 2 ), /*!< LC_OSC_MUX3 mask */ |
mcm | 1:944583d4b1de | 711 | LC_OSC_MUX3_LF3P_AND_LCO_CONNECTED = ( 1 << 2 ), /*!< LF3P and LCO connected */ |
mcm | 1:944583d4b1de | 712 | LC_OSC_MUX3_LF3P_AND_LCO_DISCONNECTED = ( 0 << 2 ) /*!< LF3P and LCO disconnected */ |
mcm | 1:944583d4b1de | 713 | } AS3933_r16_lc_osc_mux3_value_t; |
mcm | 1:944583d4b1de | 714 | |
mcm | 1:944583d4b1de | 715 | |
mcm | 1:944583d4b1de | 716 | /** |
mcm | 1:944583d4b1de | 717 | * @brief LC_OSC_MUX2 ( R16<1> ). Connects LF2P to the LCO |
mcm | 1:944583d4b1de | 718 | * |
mcm | 1:944583d4b1de | 719 | * NOTE: Default value: LC_OSC_MUX2_LF2P_AND_LCO_DISCONNECTED |
mcm | 1:944583d4b1de | 720 | */ |
mcm | 1:944583d4b1de | 721 | typedef enum { |
mcm | 1:944583d4b1de | 722 | LC_OSC_MUX2_MASK = ( 1 << 1 ), /*!< LC_OSC_MUX2 mask */ |
mcm | 1:944583d4b1de | 723 | LC_OSC_MUX2_LF2P_AND_LCO_CONNECTED = ( 1 << 1 ), /*!< LF2P and LCO connected */ |
mcm | 1:944583d4b1de | 724 | LC_OSC_MUX2_LF2P_AND_LCO_DISCONNECTED = ( 0 << 1 ) /*!< LF2P and LCO disconnected */ |
mcm | 1:944583d4b1de | 725 | } AS3933_r16_lc_osc_mux2_value_t; |
mcm | 1:944583d4b1de | 726 | |
mcm | 1:944583d4b1de | 727 | |
mcm | 1:944583d4b1de | 728 | /** |
mcm | 1:944583d4b1de | 729 | * @brief LC_OSC_MUX1 ( R16<0> ). Connects LF1P to the LCO |
mcm | 1:944583d4b1de | 730 | * |
mcm | 1:944583d4b1de | 731 | * NOTE: Default value: LC_OSC_MUX1_LF1P_AND_LCO_DISCONNECTED |
mcm | 1:944583d4b1de | 732 | */ |
mcm | 1:944583d4b1de | 733 | typedef enum { |
mcm | 1:944583d4b1de | 734 | LC_OSC_MUX1_MASK = ( 1 << 0 ), /*!< LC_OSC_MUX1 mask */ |
mcm | 1:944583d4b1de | 735 | LC_OSC_MUX1_LF1P_AND_LCO_CONNECTED = ( 1 << 0 ), /*!< LF1P and LCO connected */ |
mcm | 1:944583d4b1de | 736 | LC_OSC_MUX1_LF1P_AND_LCO_DISCONNECTED = ( 0 << 0 ) /*!< LF1P and LCO disconnected */ |
mcm | 1:944583d4b1de | 737 | } AS3933_r16_lc_osc_mux1_value_t; |
mcm | 1:944583d4b1de | 738 | |
mcm | 1:944583d4b1de | 739 | |
mcm | 1:944583d4b1de | 740 | |
mcm | 1:944583d4b1de | 741 | /* R17 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 742 | /** |
mcm | 1:944583d4b1de | 743 | * @brief CAPS_CH1 ( R17<4:0> ). Capacitor banks on the channel1 |
mcm | 1:944583d4b1de | 744 | * |
mcm | 1:944583d4b1de | 745 | * NOTE: Default value: CAPS_CH1_ADDS_NONE |
mcm | 1:944583d4b1de | 746 | */ |
mcm | 1:944583d4b1de | 747 | typedef enum { |
mcm | 1:944583d4b1de | 748 | CAPS_CH1_MASK = ( 0b11111 << 0 ), /*!< CAPS_CH1 mask */ |
mcm | 1:944583d4b1de | 749 | CAPS_CH1_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to LF1P */ |
mcm | 1:944583d4b1de | 750 | CAPS_CH1_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to LF1P */ |
mcm | 1:944583d4b1de | 751 | CAPS_CH1_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to LF1P */ |
mcm | 1:944583d4b1de | 752 | CAPS_CH1_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to LF1P */ |
mcm | 1:944583d4b1de | 753 | CAPS_CH1_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to LF1P */ |
mcm | 1:944583d4b1de | 754 | CAPS_CH1_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to LF1P */ |
mcm | 1:944583d4b1de | 755 | } AS3933_r17_caps_ch1_value_t; |
mcm | 1:944583d4b1de | 756 | |
mcm | 1:944583d4b1de | 757 | |
mcm | 1:944583d4b1de | 758 | /* R18 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 759 | /** |
mcm | 1:944583d4b1de | 760 | * @brief CAPS_CH2 ( R18<4:0> ). Capacitor banks on the channel2 |
mcm | 1:944583d4b1de | 761 | * |
mcm | 1:944583d4b1de | 762 | * NOTE: Default value: CAPS_CH2_ADDS_NONE |
mcm | 1:944583d4b1de | 763 | */ |
mcm | 1:944583d4b1de | 764 | typedef enum { |
mcm | 1:944583d4b1de | 765 | CAPS_CH2_MASK = ( 0b11111 << 0 ), /*!< CAPS_CH2 mask */ |
mcm | 1:944583d4b1de | 766 | CAPS_CH2_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to LF2P */ |
mcm | 1:944583d4b1de | 767 | CAPS_CH2_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to LF2P */ |
mcm | 1:944583d4b1de | 768 | CAPS_CH2_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to LF2P */ |
mcm | 1:944583d4b1de | 769 | CAPS_CH2_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to LF2P */ |
mcm | 1:944583d4b1de | 770 | CAPS_CH2_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to LF2P */ |
mcm | 1:944583d4b1de | 771 | CAPS_CH2_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to LF2P */ |
mcm | 1:944583d4b1de | 772 | } AS3933_r18_caps_ch2_value_t; |
mcm | 1:944583d4b1de | 773 | |
mcm | 1:944583d4b1de | 774 | |
mcm | 1:944583d4b1de | 775 | /* R19 REGISTER. COMMANDS */ |
mcm | 1:944583d4b1de | 776 | /** |
mcm | 1:944583d4b1de | 777 | * @brief CAPS_CH3 ( R19<4:0> ). Capacitor banks on the channel3 |
mcm | 1:944583d4b1de | 778 | * |
mcm | 1:944583d4b1de | 779 | * NOTE: Default value: CAPS_CH3_ADDS_NONE |
mcm | 1:944583d4b1de | 780 | */ |
mcm | 1:944583d4b1de | 781 | typedef enum { |
mcm | 1:944583d4b1de | 782 | CAPS_CH3_MASK = ( 0b11111 << 0 ), /*!< CAPS_CH3 mask */ |
mcm | 1:944583d4b1de | 783 | CAPS_CH3_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to LF3P */ |
mcm | 1:944583d4b1de | 784 | CAPS_CH3_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to LF3P */ |
mcm | 1:944583d4b1de | 785 | CAPS_CH3_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to LF3P */ |
mcm | 1:944583d4b1de | 786 | CAPS_CH3_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to LF3P */ |
mcm | 1:944583d4b1de | 787 | CAPS_CH3_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to LF3P */ |
mcm | 1:944583d4b1de | 788 | CAPS_CH3_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to LF3P */ |
mcm | 1:944583d4b1de | 789 | } AS3933_r19_caps_ch3_value_t; |
mcm | 1:944583d4b1de | 790 | |
mcm | 1:944583d4b1de | 791 | |
mcm | 1:944583d4b1de | 792 | |
mcm | 1:944583d4b1de | 793 | |
mcm | 1:944583d4b1de | 794 | /* DRIVER COMMANDS */ |
mcm | 1:944583d4b1de | 795 | /** |
mcm | 1:944583d4b1de | 796 | * @brief CHANNEL ENABLED |
mcm | 1:944583d4b1de | 797 | * |
mcm | 1:944583d4b1de | 798 | * NOTE: p.14 8.1.1 Listening Mode |
mcm | 1:944583d4b1de | 799 | */ |
mcm | 1:944583d4b1de | 800 | typedef enum { |
mcm | 1:944583d4b1de | 801 | AS3933_CH1_OFF_CH2_OFF_CH3_OFF = 0, /*!< All channels disabled */ |
mcm | 1:944583d4b1de | 802 | AS3933_CH1_ON_CH2_OFF_CH3_OFF = 1, /*!< Channels 1 enabled */ |
mcm | 1:944583d4b1de | 803 | AS3933_CH1_OFF_CH2_ON_CH3_OFF = 2, /*!< Channel 2 enabled */ |
mcm | 1:944583d4b1de | 804 | AS3933_CH1_ON_CH2_ON_CH3_OFF = 3, /*!< Channels 1 and 2 enabled */ |
mcm | 1:944583d4b1de | 805 | AS3933_CH1_OFF_CH2_OFF_CH3_ON = 4, /*!< Channel 3 enabled */ |
mcm | 1:944583d4b1de | 806 | AS3933_CH1_ON_CH2_OFF_CH3_ON = 5, /*!< Channels 1 and 3 enabled */ |
mcm | 1:944583d4b1de | 807 | AS3933_CH1_OFF_CH2_ON_CH3_ON = 6, /*!< Channels 2 and 3 enabled */ |
mcm | 1:944583d4b1de | 808 | AS3933_CH1_ON_CH2_ON_CH3_ON = 7 /*!< All channels enabled */ |
mcm | 1:944583d4b1de | 809 | } AS3933_channels_enable_t; |
mcm | 1:944583d4b1de | 810 | |
mcm | 1:944583d4b1de | 811 | |
mcm | 1:944583d4b1de | 812 | /** |
mcm | 1:944583d4b1de | 813 | * @brief LISTENING MODE ( LOW POWER MODE ) |
mcm | 1:944583d4b1de | 814 | * |
mcm | 1:944583d4b1de | 815 | * NOTE: p.14 8.1.1 Listening Mode |
mcm | 1:944583d4b1de | 816 | */ |
mcm | 1:944583d4b1de | 817 | typedef enum { |
mcm | 1:944583d4b1de | 818 | AS3933_STANDARD_LISTENING_MODE = 0, /*!< All channels are active at the same time */ |
mcm | 1:944583d4b1de | 819 | AS3933_SCANNING_MODE = 1, /*!< Low Power mode 1 */ |
mcm | 1:944583d4b1de | 820 | AS3933_ON_OFF_MODE = 2 /*!< Low Power mode 2 */ |
mcm | 1:944583d4b1de | 821 | } AS3933_scanning_mode_t; |
mcm | 1:944583d4b1de | 822 | |
mcm | 1:944583d4b1de | 823 | |
mcm | 1:944583d4b1de | 824 | /** |
mcm | 1:944583d4b1de | 825 | * @brief TOLERANCE SETTINGS |
mcm | 1:944583d4b1de | 826 | * |
mcm | 1:944583d4b1de | 827 | * NOTE: p.23 8.3.1 Frequency Detector / RSSI / Channel Selector |
mcm | 1:944583d4b1de | 828 | * The tolerance depends on the frequency detection band. |
mcm | 1:944583d4b1de | 829 | */ |
mcm | 1:944583d4b1de | 830 | typedef enum { |
mcm | 1:944583d4b1de | 831 | AS3933_TOLERANCE_MASK = ( 0b11 << 0 ), /*!< Tolerance mask */ |
mcm | 1:944583d4b1de | 832 | AS3933_TOLERANCE_TIGHT = ( 0b00 << 0 ), |
mcm | 1:944583d4b1de | 833 | AS3933_TOLERANCE_MEDIUM = ( 0b01 << 0 ), |
mcm | 1:944583d4b1de | 834 | AS3933_TOLERANCE_RELAX = ( 0b10 << 0 ) |
mcm | 1:944583d4b1de | 835 | } AS3933_tolerance_settings_t; |
mcm | 1:944583d4b1de | 836 | |
mcm | 1:944583d4b1de | 837 | |
mcm | 1:944583d4b1de | 838 | /** |
mcm | 1:944583d4b1de | 839 | * @brief CHANNELS ( Parallel Tuning Capacitance ) |
mcm | 1:944583d4b1de | 840 | * |
mcm | 1:944583d4b1de | 841 | */ |
mcm | 1:944583d4b1de | 842 | typedef enum { |
mcm | 1:944583d4b1de | 843 | AS3933_CHANNEL_LF1P = 0, /*!< Channel 1 */ |
mcm | 1:944583d4b1de | 844 | AS3933_CHANNEL_LF2P = 1, /*!< Channel 2 */ |
mcm | 1:944583d4b1de | 845 | AS3933_CHANNEL_LF3P = 2 /*!< Channel 3 */ |
mcm | 1:944583d4b1de | 846 | } AS3933_parallel_tuning_channels_t; |
mcm | 1:944583d4b1de | 847 | |
mcm | 1:944583d4b1de | 848 | |
mcm | 1:944583d4b1de | 849 | /** |
mcm | 1:944583d4b1de | 850 | * @brief CAPACITANCE ( Parallel Tuning Capacitance ) |
mcm | 1:944583d4b1de | 851 | * |
mcm | 1:944583d4b1de | 852 | */ |
mcm | 1:944583d4b1de | 853 | typedef enum { |
mcm | 1:944583d4b1de | 854 | AS3933_CAPACITANCE_MASK = ( 0b11111 << 0 ), /*!< AS3933_CAPACITANCE mask */ |
mcm | 1:944583d4b1de | 855 | AS3933_CAPACITANCE_ADDS_NONE = ( 0b00000 << 0 ), /*!< None to chosen channel */ |
mcm | 1:944583d4b1de | 856 | AS3933_CAPACITANCE_ADDS_1PF = ( 0b00001 << 0 ), /*!< Adds 1pF to chosen channel */ |
mcm | 1:944583d4b1de | 857 | AS3933_CAPACITANCE_ADDS_2PF = ( 0b00010 << 0 ), /*!< Adds 2pF to chosen channel */ |
mcm | 1:944583d4b1de | 858 | AS3933_CAPACITANCE_ADDS_4PF = ( 0b00100 << 0 ), /*!< Adds 4pF to chosen channel */ |
mcm | 1:944583d4b1de | 859 | AS3933_CAPACITANCE_ADDS_8PF = ( 0b01000 << 0 ), /*!< Adds 8pF to chosen channel */ |
mcm | 1:944583d4b1de | 860 | AS3933_CAPACITANCE_ADDS_16PF = ( 0b10000 << 0 ) /*!< Adds 16pF to chosen channel */ |
mcm | 1:944583d4b1de | 861 | } AS3933_parallel_tuning_capacitance_t; |
mcm | 1:944583d4b1de | 862 | |
mcm | 1:944583d4b1de | 863 | |
mcm | 1:944583d4b1de | 864 | |
mcm | 1:944583d4b1de | 865 | #ifndef AS3933_VECTOR_STRUCT_H |
mcm | 1:944583d4b1de | 866 | #define AS3933_VECTOR_STRUCT_H |
mcm | 1:944583d4b1de | 867 | /* AS3933 DATA */ |
mcm | 1:944583d4b1de | 868 | typedef struct { |
mcm | 1:944583d4b1de | 869 | int8_t f_wake; /*!< False wakeup register */ |
mcm | 1:944583d4b1de | 870 | uint8_t patt2b; /*!< Wakeup pattern PATT2B ( Manchester ) */ |
mcm | 1:944583d4b1de | 871 | uint8_t patt1b; /*!< Wakeup pattern PATT1B ( Manchester ) */ |
mcm | 1:944583d4b1de | 872 | uint8_t rssi1; /*!< RSSI1 Channel 1 */ |
mcm | 1:944583d4b1de | 873 | uint8_t rssi2; /*!< RSSI2 Channel 2 */ |
mcm | 1:944583d4b1de | 874 | uint8_t rssi3; /*!< RSSI3 Channel 3 */ |
mcm | 1:944583d4b1de | 875 | |
mcm | 1:944583d4b1de | 876 | uint32_t data; /*!< Data */ |
mcm | 1:944583d4b1de | 877 | } AS3933_data_t; |
mcm | 1:944583d4b1de | 878 | #endif |
mcm | 1:944583d4b1de | 879 | |
mcm | 1:944583d4b1de | 880 | |
mcm | 1:944583d4b1de | 881 | |
mcm | 1:944583d4b1de | 882 | /** |
mcm | 1:944583d4b1de | 883 | * @brief INTERNAL CONSTANTS |
mcm | 1:944583d4b1de | 884 | */ |
mcm | 1:944583d4b1de | 885 | typedef enum { |
mcm | 1:944583d4b1de | 886 | AS3933_SUCCESS = 0, |
mcm | 1:944583d4b1de | 887 | AS3933_FAILURE = 1, |
mcm | 1:944583d4b1de | 888 | SPI_SUCCESS = 1 |
mcm | 1:944583d4b1de | 889 | } AS3933_status_t; |
mcm | 1:944583d4b1de | 890 | |
mcm | 1:944583d4b1de | 891 | |
mcm | 1:944583d4b1de | 892 | |
mcm | 1:944583d4b1de | 893 | |
mcm | 1:944583d4b1de | 894 | /** Create an AS3933 object connected to the specified SPI pins. |
mcm | 1:944583d4b1de | 895 | * |
mcm | 1:944583d4b1de | 896 | * @param mosi SPI Master Output Slave Input |
mcm | 1:944583d4b1de | 897 | * @param miso SPI Master Input Slave Output |
mcm | 1:944583d4b1de | 898 | * @param sclk SPI clock |
mcm | 1:944583d4b1de | 899 | * @param cs SPI Chip Select |
mcm | 1:944583d4b1de | 900 | * @param freq SPI frequency in Hz. |
mcm | 1:944583d4b1de | 901 | */ |
mcm | 1:944583d4b1de | 902 | AS3933 ( PinName mosi, PinName miso, PinName sclk, PinName cs, uint32_t freq ); |
mcm | 1:944583d4b1de | 903 | |
mcm | 1:944583d4b1de | 904 | /** Delete AS3933 object. |
mcm | 1:944583d4b1de | 905 | */ |
mcm | 1:944583d4b1de | 906 | ~AS3933(); |
mcm | 1:944583d4b1de | 907 | |
mcm | 1:944583d4b1de | 908 | /** It configures the low power mode. |
mcm | 1:944583d4b1de | 909 | */ |
mcm | 1:944583d4b1de | 910 | AS3933_status_t AS3933_SetLowPowerMode ( AS3933_channels_enable_t myEnabledChannels, AS3933_scanning_mode_t myLowPowerMode, AS3933_r4_t_off_value_t myT_Off ); |
mcm | 1:944583d4b1de | 911 | |
mcm | 1:944583d4b1de | 912 | /** It configures the artificial wakeup. |
mcm | 1:944583d4b1de | 913 | */ |
mcm | 1:944583d4b1de | 914 | AS3933_status_t AS3933_SetArtificialWakeUp ( AS3933_r8_t_auto_value_t myArtificialWakeUp ); |
mcm | 1:944583d4b1de | 915 | |
mcm | 1:944583d4b1de | 916 | /** It gets feedback on the surrounding environment reading the false wakeup register. |
mcm | 1:944583d4b1de | 917 | */ |
mcm | 1:944583d4b1de | 918 | AS3933_status_t AS3933_ReadFalseWakeUpRegister ( AS3933_data_t* myF_WAKE ); |
mcm | 1:944583d4b1de | 919 | |
mcm | 1:944583d4b1de | 920 | /** It configures the clock generator. |
mcm | 1:944583d4b1de | 921 | */ |
mcm | 1:944583d4b1de | 922 | AS3933_status_t AS3933_SetClockGenerator ( AS3933_r1_en_xtal_value_t myClockGenerator, AS3933_r16_clock_gen_dis_value_t myClockGeneratorOutputMode ); |
mcm | 1:944583d4b1de | 923 | |
mcm | 1:944583d4b1de | 924 | /** It calibrates RC oscillator ( Self Calibration only ). |
mcm | 1:944583d4b1de | 925 | */ |
mcm | 1:944583d4b1de | 926 | AS3933_status_t AS3933_CalibrateRC_Oscillator ( void ); |
mcm | 1:944583d4b1de | 927 | |
mcm | 1:944583d4b1de | 928 | /** It configures the antenna damper. |
mcm | 1:944583d4b1de | 929 | */ |
mcm | 1:944583d4b1de | 930 | AS3933_status_t AS3933_SetAntennaDamper ( AS3933_r1_att_on_value_t myAntennaDamperMode, AS3933_r4_d_res_value_t myShuntResistor ); |
mcm | 1:944583d4b1de | 931 | |
mcm | 1:944583d4b1de | 932 | /** It configures the envelop detector for different symbol rates. |
mcm | 1:944583d4b1de | 933 | */ |
mcm | 1:944583d4b1de | 934 | AS3933_status_t AS3933_SetEnvelopDetector ( AS3933_r3_fs_env_value_t mySymbolRates ); |
mcm | 1:944583d4b1de | 935 | |
mcm | 1:944583d4b1de | 936 | /** It configures the data slicer for different preamble length. |
mcm | 1:944583d4b1de | 937 | */ |
mcm | 1:944583d4b1de | 938 | AS3933_status_t AS3933_SetDataSlicer ( AS3933_r1_abs_hy_value_t myAbsoluteThresholdMode, AS3933_r3_fs_scl_value_t myMinimumPreambleLength ); |
mcm | 1:944583d4b1de | 939 | |
mcm | 1:944583d4b1de | 940 | /** It configures the hysteresis on the data slicer comparator. |
mcm | 1:944583d4b1de | 941 | */ |
mcm | 1:944583d4b1de | 942 | AS3933_status_t AS3933_SetComparatorHysteresis ( AS3933_r3_hy_pos_value_t myHysteresisMode, AS3933_r3_hy_20m_value_t myHysteresisRange ); |
mcm | 1:944583d4b1de | 943 | |
mcm | 1:944583d4b1de | 944 | /** It configures the gain reduction. |
mcm | 1:944583d4b1de | 945 | */ |
mcm | 1:944583d4b1de | 946 | AS3933_status_t AS3933_SetGainReduction ( AS3933_r4_gr_value_t myGainReductionValue ); |
mcm | 1:944583d4b1de | 947 | |
mcm | 1:944583d4b1de | 948 | /** It configures the operating frequency range. |
mcm | 1:944583d4b1de | 949 | */ |
mcm | 1:944583d4b1de | 950 | AS3933_status_t AS3933_SetOperatingFrequencyRange ( AS3933_r8_band_sel_value_t myOperatingFrequencyRange ); |
mcm | 1:944583d4b1de | 951 | |
mcm | 1:944583d4b1de | 952 | /** It configures the frequency detection tolerance. |
mcm | 1:944583d4b1de | 953 | */ |
mcm | 1:944583d4b1de | 954 | AS3933_status_t AS3933_SetFrequencyDetectionTolerance ( AS3933_tolerance_settings_t myTolerance ); |
mcm | 1:944583d4b1de | 955 | |
mcm | 1:944583d4b1de | 956 | /** It configures the +3dB gain boost. |
mcm | 1:944583d4b1de | 957 | */ |
mcm | 1:944583d4b1de | 958 | AS3933_status_t AS3933_SetGainBoost ( AS3933_r2_g_boost_value_t myGainBoostMode ); |
mcm | 1:944583d4b1de | 959 | |
mcm | 1:944583d4b1de | 960 | /** It configures the Automatic Gain Control ( AGC ). |
mcm | 1:944583d4b1de | 961 | */ |
mcm | 1:944583d4b1de | 962 | AS3933_status_t AS3933_SetAGC ( AS3933_r1_agc_tlim_value_t myAGC_CarrierBurstMode, AS3933_r1_agc_ud_value_t myAGC_OperatingDirection ); |
mcm | 1:944583d4b1de | 963 | |
mcm | 1:944583d4b1de | 964 | /** It configures the mask data before wakeup. |
mcm | 1:944583d4b1de | 965 | */ |
mcm | 1:944583d4b1de | 966 | AS3933_status_t AS3933_SetDataMask ( AS3933_r0_dat_mask_value_t myDataMaskMode ); |
mcm | 1:944583d4b1de | 967 | |
mcm | 1:944583d4b1de | 968 | /** It configures the correlator and the Manchester Decoder. |
mcm | 1:944583d4b1de | 969 | */ |
mcm | 1:944583d4b1de | 970 | AS3933_status_t AS3933_SetCorrelator ( AS3933_r1_en_wpat_value_t myCorrelatorMode, AS3933_r0_patt32_value_t mySymbolPattern, AS3933_r7_t_hbit_value_t myRate, |
mcm | 1:944583d4b1de | 971 | AS3933_r1_en_manch_value_t myManchesterDecoderMode ); |
mcm | 1:944583d4b1de | 972 | |
mcm | 1:944583d4b1de | 973 | /** It sets the wakeup pattern ( Manchester ). |
mcm | 1:944583d4b1de | 974 | */ |
mcm | 1:944583d4b1de | 975 | AS3933_status_t AS3933_SetWakeUpPattern ( AS3933_data_t myWakeUpPattern ); |
mcm | 1:944583d4b1de | 976 | |
mcm | 1:944583d4b1de | 977 | /** It gets the wakeup pattern ( Manchester ). |
mcm | 1:944583d4b1de | 978 | */ |
mcm | 1:944583d4b1de | 979 | AS3933_status_t AS3933_GetWakeUpPattern ( AS3933_data_t* myWakeUpPattern ); |
mcm | 1:944583d4b1de | 980 | |
mcm | 1:944583d4b1de | 981 | /** It sets the automatic time-out setup. |
mcm | 1:944583d4b1de | 982 | */ |
mcm | 1:944583d4b1de | 983 | AS3933_status_t AS3933_SetAutomaticTimeOut ( AS3933_r7_t_out_value_t myAutomaticTimeOut ); |
mcm | 1:944583d4b1de | 984 | |
mcm | 1:944583d4b1de | 985 | /** It sets the parallel tuning capacitance on the chosen channel. |
mcm | 1:944583d4b1de | 986 | */ |
mcm | 1:944583d4b1de | 987 | AS3933_status_t AS3933_SetParallelTuningCapacitance ( AS3933_parallel_tuning_channels_t myChannel, AS3933_parallel_tuning_capacitance_t myAddedCapacitance ); |
mcm | 1:944583d4b1de | 988 | |
mcm | 1:944583d4b1de | 989 | /** It gets the RSSI for all channels. |
mcm | 1:944583d4b1de | 990 | */ |
mcm | 1:944583d4b1de | 991 | AS3933_status_t AS3933_GetRSSI ( AS3933_data_t* myChannelRSSI ); |
mcm | 1:944583d4b1de | 992 | |
mcm | 1:944583d4b1de | 993 | /** It sends a direct command |
mcm | 1:944583d4b1de | 994 | */ |
mcm | 1:944583d4b1de | 995 | AS3933_status_t AS3933_Send_DirectCommand ( AS3933_spi_direct_commands_t myDirectCommand ); |
mcm | 1:944583d4b1de | 996 | |
mcm | 1:944583d4b1de | 997 | private: |
mcm | 1:944583d4b1de | 998 | SPI _spi; |
mcm | 1:944583d4b1de | 999 | DigitalOut _cs; |
mcm | 1:944583d4b1de | 1000 | }; |
mcm | 1:944583d4b1de | 1001 | |
mcm | 1:944583d4b1de | 1002 | #endif |