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Fork to see if I can get working
Dependencies: BufferedSerial OneWire WinbondSPIFlash libxDot-dev-mbed5-deprecated
Fork of xDotBridge_update_test20180823 by
xDotBridge/manualTest/testPVD/testPVD.cpp@100:0882cf295f8e, 2017-11-29 (annotated)
- Committer:
- mbriggs_vortex
- Date:
- Wed Nov 29 13:54:36 2017 -0700
- Revision:
- 100:0882cf295f8e
- Parent:
- 55:79ab0bbc5008
Adding relaese bin to repo
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Matt Briggs | 51:58d2a1b8f9d2 | 1 | #include "mbed.h" |
Matt Briggs | 51:58d2a1b8f9d2 | 2 | #include "stm32l1xx_hal_pwr.h" |
Matt Briggs | 55:79ab0bbc5008 | 3 | #include "../../config.h" |
Matt Briggs | 51:58d2a1b8f9d2 | 4 | |
Matt Briggs | 51:58d2a1b8f9d2 | 5 | #ifdef __TEST_PVD__ |
Matt Briggs | 51:58d2a1b8f9d2 | 6 | |
Matt Briggs | 51:58d2a1b8f9d2 | 7 | Serial pc(USBTX, USBRX); // Externally defined |
Matt Briggs | 51:58d2a1b8f9d2 | 8 | |
Matt Briggs | 51:58d2a1b8f9d2 | 9 | extern void Error_Handler(void); |
Matt Briggs | 51:58d2a1b8f9d2 | 10 | |
Matt Briggs | 51:58d2a1b8f9d2 | 11 | volatile uint8_t pvdIntCnt; |
Matt Briggs | 51:58d2a1b8f9d2 | 12 | DigitalOut gpio0(GPIO0); |
Matt Briggs | 51:58d2a1b8f9d2 | 13 | |
Matt Briggs | 51:58d2a1b8f9d2 | 14 | void HAL_PWR_PVDCallback(void) { |
Matt Briggs | 51:58d2a1b8f9d2 | 15 | gpio0 = 1; |
Matt Briggs | 51:58d2a1b8f9d2 | 16 | pvdIntCnt++; |
Matt Briggs | 51:58d2a1b8f9d2 | 17 | /* Clear PWR Exti pending bit */ |
Matt Briggs | 51:58d2a1b8f9d2 | 18 | __HAL_PWR_PVD_EXTI_CLEAR_FLAG(); // Just to be extra sure |
Matt Briggs | 51:58d2a1b8f9d2 | 19 | } |
Matt Briggs | 51:58d2a1b8f9d2 | 20 | int main () |
Matt Briggs | 51:58d2a1b8f9d2 | 21 | { |
Matt Briggs | 51:58d2a1b8f9d2 | 22 | HAL_MspInit(); |
Matt Briggs | 51:58d2a1b8f9d2 | 23 | pvdIntCnt = 0; |
Matt Briggs | 51:58d2a1b8f9d2 | 24 | |
Matt Briggs | 51:58d2a1b8f9d2 | 25 | pc.baud(115200); |
Matt Briggs | 51:58d2a1b8f9d2 | 26 | |
Matt Briggs | 51:58d2a1b8f9d2 | 27 | while (true) { |
Matt Briggs | 51:58d2a1b8f9d2 | 28 | pc.printf("PVD_INT_CNT %d, EXTI_GET_FLAG %d\r\n", pvdIntCnt, __HAL_PWR_PVD_EXTI_GET_FLAG()); |
Matt Briggs | 51:58d2a1b8f9d2 | 29 | wait(0.1); |
Matt Briggs | 51:58d2a1b8f9d2 | 30 | } |
Matt Briggs | 51:58d2a1b8f9d2 | 31 | return 0; |
Matt Briggs | 51:58d2a1b8f9d2 | 32 | } |
Matt Briggs | 51:58d2a1b8f9d2 | 33 | void HAL_MspInit(void) |
Matt Briggs | 51:58d2a1b8f9d2 | 34 | { |
Matt Briggs | 51:58d2a1b8f9d2 | 35 | /* USER CODE BEGIN MspInit 0 */ |
Matt Briggs | 51:58d2a1b8f9d2 | 36 | /* USER CODE END MspInit 0 */ |
Matt Briggs | 51:58d2a1b8f9d2 | 37 | PWR_PVDTypeDef sConfigPVD; |
Matt Briggs | 51:58d2a1b8f9d2 | 38 | __HAL_RCC_COMP_CLK_ENABLE(); |
Matt Briggs | 51:58d2a1b8f9d2 | 39 | __HAL_RCC_SYSCFG_CLK_ENABLE(); |
Matt Briggs | 51:58d2a1b8f9d2 | 40 | __HAL_RCC_PWR_CLK_ENABLE(); |
Matt Briggs | 51:58d2a1b8f9d2 | 41 | HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4); |
Matt Briggs | 51:58d2a1b8f9d2 | 42 | /* System interrupt init*/ |
Matt Briggs | 51:58d2a1b8f9d2 | 43 | /* MemoryManagement_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 44 | HAL_NVIC_SetPriority(MemoryManagement_IRQn, 0, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 45 | /* BusFault_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 46 | HAL_NVIC_SetPriority(BusFault_IRQn, 0, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 47 | /* UsageFault_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 48 | HAL_NVIC_SetPriority(UsageFault_IRQn, 0, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 49 | /* SVC_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 50 | HAL_NVIC_SetPriority(SVC_IRQn, 0, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 51 | /* DebugMonitor_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 52 | HAL_NVIC_SetPriority(DebugMonitor_IRQn, 0, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 53 | /* PendSV_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 54 | HAL_NVIC_SetPriority(PendSV_IRQn, 0, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 55 | /* SysTick_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 56 | HAL_NVIC_SetPriority(SysTick_IRQn, 0, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 57 | /* Peripheral interrupt init*/ |
Matt Briggs | 51:58d2a1b8f9d2 | 58 | /* PVD_IRQn interrupt configuration */ |
Matt Briggs | 51:58d2a1b8f9d2 | 59 | HAL_NVIC_SetPriority(PVD_IRQn, 1, 0); |
Matt Briggs | 51:58d2a1b8f9d2 | 60 | HAL_NVIC_EnableIRQ(PVD_IRQn); // If not commented out program will hard fault but does not interrupt |
Matt Briggs | 51:58d2a1b8f9d2 | 61 | /**PVD Configuration |
Matt Briggs | 51:58d2a1b8f9d2 | 62 | */ |
Matt Briggs | 51:58d2a1b8f9d2 | 63 | sConfigPVD.PVDLevel = PWR_PVDLEVEL_5; |
Matt Briggs | 51:58d2a1b8f9d2 | 64 | sConfigPVD.Mode = PWR_PVD_MODE_IT_RISING_FALLING; |
Matt Briggs | 51:58d2a1b8f9d2 | 65 | // sConfigPVD.Mode = PWR_PVD_MODE_EVENT_RISING; |
Matt Briggs | 51:58d2a1b8f9d2 | 66 | HAL_PWR_ConfigPVD(&sConfigPVD); |
Matt Briggs | 51:58d2a1b8f9d2 | 67 | /**Enable the PVD Output |
Matt Briggs | 51:58d2a1b8f9d2 | 68 | */ |
Matt Briggs | 51:58d2a1b8f9d2 | 69 | HAL_PWR_EnablePVD(); |
Matt Briggs | 51:58d2a1b8f9d2 | 70 | /* USER CODE BEGIN MspInit 1 */ |
Matt Briggs | 51:58d2a1b8f9d2 | 71 | /* USER CODE END MspInit 1 */ |
Matt Briggs | 51:58d2a1b8f9d2 | 72 | } |
Matt Briggs | 51:58d2a1b8f9d2 | 73 | |
Matt Briggs | 51:58d2a1b8f9d2 | 74 | #endif |