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Diff: TARGET_NUCLEO_F072RB/mpu_armv8.h
- Revision:
- 169:a7c7b631e539
- Parent:
- 160:5571c4ff569f
diff -r b9e159c1930a -r a7c7b631e539 TARGET_NUCLEO_F072RB/mpu_armv8.h --- a/TARGET_NUCLEO_F072RB/mpu_armv8.h Thu May 24 15:35:55 2018 +0100 +++ b/TARGET_NUCLEO_F072RB/mpu_armv8.h Fri Jun 22 15:38:59 2018 +0100 @@ -1,11 +1,11 @@ /****************************************************************************** * @file mpu_armv8.h - * @brief CMSIS MPU API for ARMv8 MPU - * @version V5.0.3 - * @date 09. August 2017 + * @brief CMSIS MPU API for Armv8-M MPU + * @version V5.0.4 + * @date 10. January 2018 ******************************************************************************/ /* - * Copyright (c) 2017 ARM Limited. All rights reserved. + * Copyright (c) 2017-2018 Arm Limited. All rights reserved. * * SPDX-License-Identifier: Apache-2.0 * @@ -21,7 +21,13 @@ * See the License for the specific language governing permissions and * limitations under the License. */ - + +#if defined ( __ICCARM__ ) + #pragma system_include /* treat file as system include file for MISRA check */ +#elif defined (__clang__) + #pragma clang system_header /* treat file as system include file */ +#endif + #ifndef ARM_MPU_ARMV8_H #define ARM_MPU_ARMV8_H @@ -98,7 +104,7 @@ /** * Struct for a single MPU Region */ -typedef struct _ARM_MPU_Region_t { +typedef struct { uint32_t RBAR; /*!< Region Base Address Register value */ uint32_t RLAR; /*!< Region Limit Address Register value */ } ARM_MPU_Region_t; @@ -166,11 +172,11 @@ const uint32_t pos = ((idx % 4U) * 8U); const uint32_t mask = 0xFFU << pos; - if (reg >= (sizeof(MPU->MAIR) / sizeof(MPU->MAIR[0]))) { + if (reg >= (sizeof(mpu->MAIR) / sizeof(mpu->MAIR[0]))) { return; // invalid index } - MPU->MAIR[reg] = ((MPU->MAIR[reg] & ~mask) | ((attr << pos) & mask)); + mpu->MAIR[reg] = ((mpu->MAIR[reg] & ~mask) | ((attr << pos) & mask)); } /** Set the memory attribute encoding. @@ -199,8 +205,8 @@ */ __STATIC_INLINE void ARM_MPU_ClrRegionEx(MPU_Type* mpu, uint32_t rnr) { - MPU->RNR = rnr; - MPU->RLAR = 0U; + mpu->RNR = rnr; + mpu->RLAR = 0U; } /** Clear and disable the given MPU region. @@ -229,9 +235,9 @@ */ __STATIC_INLINE void ARM_MPU_SetRegionEx(MPU_Type* mpu, uint32_t rnr, uint32_t rbar, uint32_t rlar) { - MPU->RNR = rnr; - MPU->RBAR = rbar; - MPU->RLAR = rlar; + mpu->RNR = rnr; + mpu->RBAR = rbar; + mpu->RLAR = rlar; } /** Configure the given MPU region. @@ -278,7 +284,7 @@ */ __STATIC_INLINE void ARM_MPU_LoadEx(MPU_Type* mpu, uint32_t rnr, ARM_MPU_Region_t const* table, uint32_t cnt) { - static const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; + const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U; if (cnt == 1U) { mpu->RNR = rnr; orderedCpy(&(mpu->RBAR), &(table->RBAR), rowWordSize); @@ -287,13 +293,17 @@ uint32_t rnrOffset = rnr % MPU_TYPE_RALIASES; mpu->RNR = rnrBase; - if ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { + while ((rnrOffset + cnt) > MPU_TYPE_RALIASES) { uint32_t c = MPU_TYPE_RALIASES - rnrOffset; orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), c*rowWordSize); - ARM_MPU_LoadEx(mpu, rnr + c, table + c, cnt - c); - } else { - orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); + table += c; + cnt -= c; + rnrOffset = 0U; + rnrBase += MPU_TYPE_RALIASES; + mpu->RNR = rnrBase; } + + orderedCpy(&(mpu->RBAR)+(rnrOffset*2U), &(table->RBAR), cnt*rowWordSize); } }