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TARGET_NUCLEO_F401RE/stm32f4xx_ll_fmc.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Parent:: 110:165afa46840b

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
emilmont	77:869cf507173a	1	/**
emilmont	77:869cf507173a	2	******************************************************************************
emilmont	77:869cf507173a	3	* @file stm32f4xx_ll_fmc.h
emilmont	77:869cf507173a	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.5.0
Kojto	122:f9eeca106725	6	* @date 06-May-2016
emilmont	77:869cf507173a	7	* @brief Header file of FMC HAL module.
emilmont	77:869cf507173a	8	******************************************************************************
emilmont	77:869cf507173a	9	* @attention
emilmont	77:869cf507173a	10	*
Kojto	122:f9eeca106725	11	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
emilmont	77:869cf507173a	12	*
emilmont	77:869cf507173a	13	* Redistribution and use in source and binary forms, with or without modification,
emilmont	77:869cf507173a	14	* are permitted provided that the following conditions are met:
emilmont	77:869cf507173a	15	* 1. Redistributions of source code must retain the above copyright notice,
emilmont	77:869cf507173a	16	* this list of conditions and the following disclaimer.
emilmont	77:869cf507173a	17	* 2. Redistributions in binary form must reproduce the above copyright notice,
emilmont	77:869cf507173a	18	* this list of conditions and the following disclaimer in the documentation
emilmont	77:869cf507173a	19	* and/or other materials provided with the distribution.
emilmont	77:869cf507173a	20	* 3. Neither the name of STMicroelectronics nor the names of its contributors
emilmont	77:869cf507173a	21	* may be used to endorse or promote products derived from this software
emilmont	77:869cf507173a	22	* without specific prior written permission.
emilmont	77:869cf507173a	23	*
emilmont	77:869cf507173a	24	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
emilmont	77:869cf507173a	25	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
emilmont	77:869cf507173a	26	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
emilmont	77:869cf507173a	27	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
emilmont	77:869cf507173a	28	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
emilmont	77:869cf507173a	29	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
emilmont	77:869cf507173a	30	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
emilmont	77:869cf507173a	31	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
emilmont	77:869cf507173a	32	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
emilmont	77:869cf507173a	33	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
emilmont	77:869cf507173a	34	*
emilmont	77:869cf507173a	35	******************************************************************************
emilmont	77:869cf507173a	36	*/
emilmont	77:869cf507173a	37
emilmont	77:869cf507173a	38	/* Define to prevent recursive inclusion -------------------------------------*/
emilmont	77:869cf507173a	39	#ifndef __STM32F4xx_LL_FMC_H
emilmont	77:869cf507173a	40	#define __STM32F4xx_LL_FMC_H
emilmont	77:869cf507173a	41
emilmont	77:869cf507173a	42	#ifdef __cplusplus
emilmont	77:869cf507173a	43	extern "C" {
emilmont	77:869cf507173a	44	#endif
emilmont	77:869cf507173a	45
emilmont	77:869cf507173a	46	/* Includes ------------------------------------------------------------------*/
emilmont	77:869cf507173a	47	#include "stm32f4xx_hal_def.h"
emilmont	77:869cf507173a	48
emilmont	77:869cf507173a	49	/** @addtogroup STM32F4xx_HAL_Driver
emilmont	77:869cf507173a	50	* @{
emilmont	77:869cf507173a	51	*/
Kojto	99:dbbf35b96557	52
Kojto	99:dbbf35b96557	53	/** @addtogroup FMC_LL
emilmont	77:869cf507173a	54	* @{
emilmont	77:869cf507173a	55	*/
Kojto	110:165afa46840b	56	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) \|\|\
Kojto	110:165afa46840b	57	defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	58	/* Private types -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	59	/** @defgroup FMC_LL_Private_Types FMC Private Types
Kojto	99:dbbf35b96557	60	* @{
Kojto	99:dbbf35b96557	61	*/
emilmont	77:869cf507173a	62
emilmont	77:869cf507173a	63	/**
Kojto	99:dbbf35b96557	64	* @brief FMC NORSRAM Configuration Structure definition
emilmont	77:869cf507173a	65	*/
emilmont	77:869cf507173a	66	typedef struct
emilmont	77:869cf507173a	67	{
emilmont	77:869cf507173a	68	uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
bogdanm	85:024bf7f99721	69	This parameter can be a value of @ref FMC_NORSRAM_Bank */
bogdanm	85:024bf7f99721	70
emilmont	77:869cf507173a	71	uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
emilmont	77:869cf507173a	72	multiplexed on the data bus or not.
emilmont	77:869cf507173a	73	This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
bogdanm	85:024bf7f99721	74
emilmont	77:869cf507173a	75	uint32_t MemoryType; /*!< Specifies the type of external memory attached to
emilmont	77:869cf507173a	76	the corresponding memory device.
emilmont	77:869cf507173a	77	This parameter can be a value of @ref FMC_Memory_Type */
bogdanm	85:024bf7f99721	78
emilmont	77:869cf507173a	79	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	80	This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
bogdanm	85:024bf7f99721	81
emilmont	77:869cf507173a	82	uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
emilmont	77:869cf507173a	83	valid only with synchronous burst Flash memories.
emilmont	77:869cf507173a	84	This parameter can be a value of @ref FMC_Burst_Access_Mode */
bogdanm	85:024bf7f99721	85
emilmont	77:869cf507173a	86	uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
emilmont	77:869cf507173a	87	the Flash memory in burst mode.
emilmont	77:869cf507173a	88	This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
bogdanm	85:024bf7f99721	89
emilmont	77:869cf507173a	90	uint32_t WrapMode; /*!< Enables or disables the Wrapped burst access mode for Flash
emilmont	77:869cf507173a	91	memory, valid only when accessing Flash memories in burst mode.
Kojto	99:dbbf35b96557	92	This parameter can be a value of @ref FMC_Wrap_Mode
Kojto	110:165afa46840b	93	This mode is not available for the STM32F446/467/479xx devices */
bogdanm	85:024bf7f99721	94
emilmont	77:869cf507173a	95	uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
emilmont	77:869cf507173a	96	clock cycle before the wait state or during the wait state,
emilmont	77:869cf507173a	97	valid only when accessing memories in burst mode.
emilmont	77:869cf507173a	98	This parameter can be a value of @ref FMC_Wait_Timing */
bogdanm	85:024bf7f99721	99
emilmont	77:869cf507173a	100	uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
emilmont	77:869cf507173a	101	This parameter can be a value of @ref FMC_Write_Operation */
bogdanm	85:024bf7f99721	102
emilmont	77:869cf507173a	103	uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
emilmont	77:869cf507173a	104	signal, valid for Flash memory access in burst mode.
emilmont	77:869cf507173a	105	This parameter can be a value of @ref FMC_Wait_Signal */
bogdanm	85:024bf7f99721	106
emilmont	77:869cf507173a	107	uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
emilmont	77:869cf507173a	108	This parameter can be a value of @ref FMC_Extended_Mode */
bogdanm	85:024bf7f99721	109
emilmont	77:869cf507173a	110	uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
emilmont	77:869cf507173a	111	valid only with asynchronous Flash memories.
emilmont	77:869cf507173a	112	This parameter can be a value of @ref FMC_AsynchronousWait */
bogdanm	85:024bf7f99721	113
emilmont	77:869cf507173a	114	uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
bogdanm	85:024bf7f99721	115	This parameter can be a value of @ref FMC_Write_Burst */
bogdanm	85:024bf7f99721	116
emilmont	77:869cf507173a	117	uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
emilmont	77:869cf507173a	118	This parameter is only enabled through the FMC_BCR1 register, and don't care
emilmont	77:869cf507173a	119	through FMC_BCR2..4 registers.
bogdanm	85:024bf7f99721	120	This parameter can be a value of @ref FMC_Continous_Clock */
emilmont	77:869cf507173a	121
Kojto	99:dbbf35b96557	122	uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
Kojto	99:dbbf35b96557	123	This parameter is only enabled through the FMC_BCR1 register, and don't care
Kojto	99:dbbf35b96557	124	through FMC_BCR2..4 registers.
Kojto	99:dbbf35b96557	125	This parameter can be a value of @ref FMC_Write_FIFO
Kojto	122:f9eeca106725	126	This mode is available only for the STM32F446/469/479xx devices */
Kojto	99:dbbf35b96557	127
Kojto	99:dbbf35b96557	128	uint32_t PageSize; /*!< Specifies the memory page size.
Kojto	122:f9eeca106725	129	This parameter can be a value of @ref FMC_Page_Size */
emilmont	77:869cf507173a	130	}FMC_NORSRAM_InitTypeDef;
emilmont	77:869cf507173a	131
emilmont	77:869cf507173a	132	/**
Kojto	99:dbbf35b96557	133	* @brief FMC NORSRAM Timing parameters structure definition
emilmont	77:869cf507173a	134	*/
emilmont	77:869cf507173a	135	typedef struct
emilmont	77:869cf507173a	136	{
emilmont	77:869cf507173a	137	uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	138	the duration of the address setup time.
emilmont	77:869cf507173a	139	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	140	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	141
emilmont	77:869cf507173a	142	uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	143	the duration of the address hold time.
emilmont	77:869cf507173a	144	This parameter can be a value between Min_Data = 1 and Max_Data = 15.
emilmont	77:869cf507173a	145	@note This parameter is not used with synchronous NOR Flash memories. */
bogdanm	85:024bf7f99721	146
emilmont	77:869cf507173a	147	uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	148	the duration of the data setup time.
emilmont	77:869cf507173a	149	This parameter can be a value between Min_Data = 1 and Max_Data = 255.
emilmont	77:869cf507173a	150	@note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
emilmont	77:869cf507173a	151	NOR Flash memories. */
bogdanm	85:024bf7f99721	152
emilmont	77:869cf507173a	153	uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
emilmont	77:869cf507173a	154	the duration of the bus turnaround.
emilmont	77:869cf507173a	155	This parameter can be a value between Min_Data = 0 and Max_Data = 15.
emilmont	77:869cf507173a	156	@note This parameter is only used for multiplexed NOR Flash memories. */
bogdanm	85:024bf7f99721	157
emilmont	77:869cf507173a	158	uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
emilmont	77:869cf507173a	159	HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
emilmont	77:869cf507173a	160	@note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
emilmont	77:869cf507173a	161	accesses. */
bogdanm	85:024bf7f99721	162
emilmont	77:869cf507173a	163	uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
emilmont	77:869cf507173a	164	to the memory before getting the first data.
emilmont	77:869cf507173a	165	The parameter value depends on the memory type as shown below:
emilmont	77:869cf507173a	166	- It must be set to 0 in case of a CRAM
emilmont	77:869cf507173a	167	- It is don't care in asynchronous NOR, SRAM or ROM accesses
emilmont	77:869cf507173a	168	- It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
emilmont	77:869cf507173a	169	with synchronous burst mode enable */
bogdanm	85:024bf7f99721	170
emilmont	77:869cf507173a	171	uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
emilmont	77:869cf507173a	172	This parameter can be a value of @ref FMC_Access_Mode */
emilmont	77:869cf507173a	173	}FMC_NORSRAM_TimingTypeDef;
emilmont	77:869cf507173a	174
emilmont	77:869cf507173a	175	/**
Kojto	99:dbbf35b96557	176	* @brief FMC NAND Configuration Structure definition
emilmont	77:869cf507173a	177	*/
emilmont	77:869cf507173a	178	typedef struct
emilmont	77:869cf507173a	179	{
emilmont	77:869cf507173a	180	uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
bogdanm	85:024bf7f99721	181	This parameter can be a value of @ref FMC_NAND_Bank */
bogdanm	85:024bf7f99721	182
emilmont	77:869cf507173a	183	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
emilmont	77:869cf507173a	184	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	85:024bf7f99721	185
emilmont	77:869cf507173a	186	uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
emilmont	77:869cf507173a	187	This parameter can be any value of @ref FMC_NAND_Data_Width */
bogdanm	85:024bf7f99721	188
emilmont	77:869cf507173a	189	uint32_t EccComputation; /*!< Enables or disables the ECC computation.
emilmont	77:869cf507173a	190	This parameter can be any value of @ref FMC_ECC */
bogdanm	85:024bf7f99721	191
emilmont	77:869cf507173a	192	uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
emilmont	77:869cf507173a	193	This parameter can be any value of @ref FMC_ECC_Page_Size */
bogdanm	85:024bf7f99721	194
emilmont	77:869cf507173a	195	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	196	delay between CLE low and RE low.
emilmont	77:869cf507173a	197	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	198
emilmont	77:869cf507173a	199	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	200	delay between ALE low and RE low.
emilmont	77:869cf507173a	201	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	202	}FMC_NAND_InitTypeDef;
emilmont	77:869cf507173a	203
emilmont	77:869cf507173a	204	/**
Kojto	99:dbbf35b96557	205	* @brief FMC NAND/PCCARD Timing parameters structure definition
emilmont	77:869cf507173a	206	*/
emilmont	77:869cf507173a	207	typedef struct
emilmont	77:869cf507173a	208	{
emilmont	77:869cf507173a	209	uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
emilmont	77:869cf507173a	210	the command assertion for NAND-Flash read or write access
emilmont	77:869cf507173a	211	to common/Attribute or I/O memory space (depending on
emilmont	77:869cf507173a	212	the memory space timing to be configured).
emilmont	77:869cf507173a	213	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	214
emilmont	77:869cf507173a	215	uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
emilmont	77:869cf507173a	216	command for NAND-Flash read or write access to
emilmont	77:869cf507173a	217	common/Attribute or I/O memory space (depending on the
emilmont	77:869cf507173a	218	memory space timing to be configured).
emilmont	77:869cf507173a	219	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	220
emilmont	77:869cf507173a	221	uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
emilmont	77:869cf507173a	222	(and data for write access) after the command de-assertion
emilmont	77:869cf507173a	223	for NAND-Flash read or write access to common/Attribute
emilmont	77:869cf507173a	224	or I/O memory space (depending on the memory space timing
emilmont	77:869cf507173a	225	to be configured).
emilmont	77:869cf507173a	226	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	227
emilmont	77:869cf507173a	228	uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
emilmont	77:869cf507173a	229	data bus is kept in HiZ after the start of a NAND-Flash
emilmont	77:869cf507173a	230	write access to common/Attribute or I/O memory space (depending
emilmont	77:869cf507173a	231	on the memory space timing to be configured).
emilmont	77:869cf507173a	232	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
emilmont	77:869cf507173a	233	}FMC_NAND_PCC_TimingTypeDef;
emilmont	77:869cf507173a	234
emilmont	77:869cf507173a	235	/**
Kojto	99:dbbf35b96557	236	* @brief FMC NAND Configuration Structure definition
emilmont	77:869cf507173a	237	*/
emilmont	77:869cf507173a	238	typedef struct
emilmont	77:869cf507173a	239	{
emilmont	77:869cf507173a	240	uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the PCCARD Memory device.
emilmont	77:869cf507173a	241	This parameter can be any value of @ref FMC_Wait_feature */
bogdanm	85:024bf7f99721	242
emilmont	77:869cf507173a	243	uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	244	delay between CLE low and RE low.
emilmont	77:869cf507173a	245	This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	246
emilmont	77:869cf507173a	247	uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
emilmont	77:869cf507173a	248	delay between ALE low and RE low.
emilmont	77:869cf507173a	249	This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
bogdanm	85:024bf7f99721	250	}FMC_PCCARD_InitTypeDef;
emilmont	77:869cf507173a	251
emilmont	77:869cf507173a	252	/**
Kojto	99:dbbf35b96557	253	* @brief FMC SDRAM Configuration Structure definition
emilmont	77:869cf507173a	254	*/
emilmont	77:869cf507173a	255	typedef struct
emilmont	77:869cf507173a	256	{
emilmont	77:869cf507173a	257	uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
bogdanm	85:024bf7f99721	258	This parameter can be a value of @ref FMC_SDRAM_Bank */
bogdanm	85:024bf7f99721	259
emilmont	77:869cf507173a	260	uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
emilmont	77:869cf507173a	261	This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
bogdanm	85:024bf7f99721	262
emilmont	77:869cf507173a	263	uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
emilmont	77:869cf507173a	264	This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
bogdanm	85:024bf7f99721	265
emilmont	77:869cf507173a	266	uint32_t MemoryDataWidth; /*!< Defines the memory device width.
emilmont	77:869cf507173a	267	This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
bogdanm	85:024bf7f99721	268
emilmont	77:869cf507173a	269	uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
emilmont	77:869cf507173a	270	This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
bogdanm	85:024bf7f99721	271
emilmont	77:869cf507173a	272	uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
emilmont	77:869cf507173a	273	This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
bogdanm	85:024bf7f99721	274
emilmont	77:869cf507173a	275	uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
emilmont	77:869cf507173a	276	This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
bogdanm	85:024bf7f99721	277
emilmont	77:869cf507173a	278	uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
emilmont	77:869cf507173a	279	to disable the clock before changing frequency.
emilmont	77:869cf507173a	280	This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
bogdanm	85:024bf7f99721	281
emilmont	77:869cf507173a	282	uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
emilmont	77:869cf507173a	283	commands during the CAS latency and stores data in the Read FIFO.
emilmont	77:869cf507173a	284	This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
bogdanm	85:024bf7f99721	285
emilmont	77:869cf507173a	286	uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
emilmont	77:869cf507173a	287	This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
emilmont	77:869cf507173a	288	}FMC_SDRAM_InitTypeDef;
emilmont	77:869cf507173a	289
emilmont	77:869cf507173a	290	/**
Kojto	99:dbbf35b96557	291	* @brief FMC SDRAM Timing parameters structure definition
emilmont	77:869cf507173a	292	*/
emilmont	77:869cf507173a	293	typedef struct
emilmont	77:869cf507173a	294	{
emilmont	77:869cf507173a	295	uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
emilmont	77:869cf507173a	296	an active or Refresh command in number of memory clock cycles.
emilmont	77:869cf507173a	297	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	298
emilmont	77:869cf507173a	299	uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
emilmont	77:869cf507173a	300	issuing the Activate command in number of memory clock cycles.
emilmont	77:869cf507173a	301	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	302
emilmont	77:869cf507173a	303	uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
emilmont	77:869cf507173a	304	cycles.
emilmont	77:869cf507173a	305	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	306
emilmont	77:869cf507173a	307	uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
emilmont	77:869cf507173a	308	and the delay between two consecutive Refresh commands in number of
emilmont	77:869cf507173a	309	memory clock cycles.
emilmont	77:869cf507173a	310	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	311
emilmont	77:869cf507173a	312	uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
emilmont	77:869cf507173a	313	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	314
emilmont	77:869cf507173a	315	uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
emilmont	77:869cf507173a	316	in number of memory clock cycles.
emilmont	77:869cf507173a	317	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	318
emilmont	77:869cf507173a	319	uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
emilmont	77:869cf507173a	320	command in number of memory clock cycles.
emilmont	77:869cf507173a	321	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	322	}FMC_SDRAM_TimingTypeDef;
emilmont	77:869cf507173a	323
emilmont	77:869cf507173a	324	/**
Kojto	99:dbbf35b96557	325	* @brief SDRAM command parameters structure definition
emilmont	77:869cf507173a	326	*/
emilmont	77:869cf507173a	327	typedef struct
emilmont	77:869cf507173a	328	{
emilmont	77:869cf507173a	329	uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
bogdanm	85:024bf7f99721	330	This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
bogdanm	85:024bf7f99721	331
emilmont	77:869cf507173a	332	uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
bogdanm	85:024bf7f99721	333	This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
bogdanm	85:024bf7f99721	334
emilmont	77:869cf507173a	335	uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
emilmont	77:869cf507173a	336	in auto refresh mode.
bogdanm	85:024bf7f99721	337	This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
bogdanm	85:024bf7f99721	338	uint32_t ModeRegisterDefinition; /!< Defines the SDRAM Mode register content /
emilmont	77:869cf507173a	339	}FMC_SDRAM_CommandTypeDef;
Kojto	99:dbbf35b96557	340	/**
Kojto	99:dbbf35b96557	341	* @}
Kojto	99:dbbf35b96557	342	*/
emilmont	77:869cf507173a	343
Kojto	99:dbbf35b96557	344	/* Private constants ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	345	/** @defgroup FMC_LL_Private_Constants FMC Private Constants
emilmont	77:869cf507173a	346	* @{
bogdanm	85:024bf7f99721	347	*/
bogdanm	85:024bf7f99721	348
Kojto	99:dbbf35b96557	349	/** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
Kojto	99:dbbf35b96557	350	* @{
Kojto	99:dbbf35b96557	351	*/
Kojto	99:dbbf35b96557	352	/** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
emilmont	77:869cf507173a	353	* @{
emilmont	77:869cf507173a	354	*/
Kojto	122:f9eeca106725	355	#define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	356	#define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	357	#define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	358	#define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
emilmont	77:869cf507173a	359	/**
emilmont	77:869cf507173a	360	* @}
emilmont	77:869cf507173a	361	*/
emilmont	77:869cf507173a	362
Kojto	99:dbbf35b96557	363	/** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
emilmont	77:869cf507173a	364	* @{
emilmont	77:869cf507173a	365	*/
Kojto	122:f9eeca106725	366	#define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	367	#define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
emilmont	77:869cf507173a	368	/**
emilmont	77:869cf507173a	369	* @}
emilmont	77:869cf507173a	370	*/
emilmont	77:869cf507173a	371
Kojto	99:dbbf35b96557	372	/** @defgroup FMC_Memory_Type FMC Memory Type
emilmont	77:869cf507173a	373	* @{
emilmont	77:869cf507173a	374	*/
Kojto	122:f9eeca106725	375	#define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	376	#define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	377	#define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
emilmont	77:869cf507173a	378	/**
emilmont	77:869cf507173a	379	* @}
emilmont	77:869cf507173a	380	*/
emilmont	77:869cf507173a	381
Kojto	99:dbbf35b96557	382	/** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
emilmont	77:869cf507173a	383	* @{
emilmont	77:869cf507173a	384	*/
Kojto	122:f9eeca106725	385	#define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	386	#define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	387	#define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
emilmont	77:869cf507173a	388	/**
emilmont	77:869cf507173a	389	* @}
emilmont	77:869cf507173a	390	*/
emilmont	77:869cf507173a	391
Kojto	99:dbbf35b96557	392	/** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
emilmont	77:869cf507173a	393	* @{
emilmont	77:869cf507173a	394	*/
Kojto	122:f9eeca106725	395	#define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
Kojto	122:f9eeca106725	396	#define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
emilmont	77:869cf507173a	397	/**
emilmont	77:869cf507173a	398	* @}
emilmont	77:869cf507173a	399	*/
emilmont	77:869cf507173a	400
Kojto	99:dbbf35b96557	401	/** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
emilmont	77:869cf507173a	402	* @{
emilmont	77:869cf507173a	403	*/
Kojto	122:f9eeca106725	404	#define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	405	#define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
emilmont	77:869cf507173a	406	/**
emilmont	77:869cf507173a	407	* @}
emilmont	77:869cf507173a	408	*/
emilmont	77:869cf507173a	409
Kojto	99:dbbf35b96557	410	/** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
emilmont	77:869cf507173a	411	* @{
emilmont	77:869cf507173a	412	*/
Kojto	122:f9eeca106725	413	#define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	414	#define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
emilmont	77:869cf507173a	415	/**
emilmont	77:869cf507173a	416	* @}
emilmont	77:869cf507173a	417	*/
emilmont	77:869cf507173a	418
Kojto	99:dbbf35b96557	419	/** @defgroup FMC_Wrap_Mode FMC Wrap Mode
emilmont	77:869cf507173a	420	* @{
emilmont	77:869cf507173a	421	*/
Kojto	110:165afa46840b	422	/** @note This mode is not available for the STM32F446/469/479xx devices
Kojto	99:dbbf35b96557	423	*/
Kojto	122:f9eeca106725	424	#define FMC_WRAP_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	425	#define FMC_WRAP_MODE_ENABLE ((uint32_t)0x00000400U)
emilmont	77:869cf507173a	426	/**
emilmont	77:869cf507173a	427	* @}
emilmont	77:869cf507173a	428	*/
emilmont	77:869cf507173a	429
Kojto	99:dbbf35b96557	430	/** @defgroup FMC_Wait_Timing FMC Wait Timing
Kojto	99:dbbf35b96557	431	* @{
Kojto	99:dbbf35b96557	432	*/
Kojto	122:f9eeca106725	433	#define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	434	#define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
Kojto	99:dbbf35b96557	435	/**
Kojto	99:dbbf35b96557	436	* @}
Kojto	99:dbbf35b96557	437	*/
Kojto	99:dbbf35b96557	438
Kojto	99:dbbf35b96557	439	/** @defgroup FMC_Write_Operation FMC Write Operation
emilmont	77:869cf507173a	440	* @{
emilmont	77:869cf507173a	441	*/
Kojto	122:f9eeca106725	442	#define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	443	#define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
emilmont	77:869cf507173a	444	/**
emilmont	77:869cf507173a	445	* @}
emilmont	77:869cf507173a	446	*/
emilmont	77:869cf507173a	447
Kojto	99:dbbf35b96557	448	/** @defgroup FMC_Wait_Signal FMC Wait Signal
emilmont	77:869cf507173a	449	* @{
emilmont	77:869cf507173a	450	*/
Kojto	122:f9eeca106725	451	#define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	452	#define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
emilmont	77:869cf507173a	453	/**
emilmont	77:869cf507173a	454	* @}
emilmont	77:869cf507173a	455	*/
emilmont	77:869cf507173a	456
Kojto	99:dbbf35b96557	457	/** @defgroup FMC_Extended_Mode FMC Extended Mode
Kojto	99:dbbf35b96557	458	* @{
Kojto	99:dbbf35b96557	459	*/
Kojto	122:f9eeca106725	460	#define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	461	#define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
Kojto	99:dbbf35b96557	462	/**
Kojto	99:dbbf35b96557	463	* @}
Kojto	99:dbbf35b96557	464	*/
Kojto	99:dbbf35b96557	465
Kojto	99:dbbf35b96557	466	/** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
emilmont	77:869cf507173a	467	* @{
emilmont	77:869cf507173a	468	*/
Kojto	122:f9eeca106725	469	#define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	470	#define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
emilmont	77:869cf507173a	471	/**
emilmont	77:869cf507173a	472	* @}
emilmont	77:869cf507173a	473	*/
emilmont	77:869cf507173a	474
Kojto	99:dbbf35b96557	475	/** @defgroup FMC_Page_Size FMC Page Size
Kojto	99:dbbf35b96557	476	* @{
Kojto	99:dbbf35b96557	477	*/
Kojto	122:f9eeca106725	478	#define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	479	#define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
Kojto	99:dbbf35b96557	480	#define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
Kojto	122:f9eeca106725	481	#define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 \| FMC_BCR1_CPSIZE_1))
Kojto	99:dbbf35b96557	482	#define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
Kojto	99:dbbf35b96557	483	/**
Kojto	99:dbbf35b96557	484	* @}
Kojto	99:dbbf35b96557	485	*/
Kojto	99:dbbf35b96557	486
Kojto	99:dbbf35b96557	487	/** @defgroup FMC_Write_FIFO FMC Write FIFO
Kojto	110:165afa46840b	488	* @note These values are available only for the STM32F446/469/479xx devices.
Kojto	99:dbbf35b96557	489	* @{
Kojto	99:dbbf35b96557	490	*/
Kojto	122:f9eeca106725	491	#define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
Kojto	122:f9eeca106725	492	#define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
Kojto	99:dbbf35b96557	493	/**
Kojto	99:dbbf35b96557	494	* @}
Kojto	99:dbbf35b96557	495	*/
Kojto	99:dbbf35b96557	496
Kojto	99:dbbf35b96557	497	/** @defgroup FMC_Write_Burst FMC Write Burst
emilmont	77:869cf507173a	498	* @{
emilmont	77:869cf507173a	499	*/
Kojto	122:f9eeca106725	500	#define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	501	#define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
emilmont	77:869cf507173a	502	/**
emilmont	77:869cf507173a	503	* @}
emilmont	77:869cf507173a	504	*/
emilmont	77:869cf507173a	505
Kojto	99:dbbf35b96557	506	/** @defgroup FMC_Continous_Clock FMC Continuous Clock
emilmont	77:869cf507173a	507	* @{
emilmont	77:869cf507173a	508	*/
Kojto	122:f9eeca106725	509	#define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	510	#define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
emilmont	77:869cf507173a	511	/**
emilmont	77:869cf507173a	512	* @}
emilmont	77:869cf507173a	513	*/
Kojto	99:dbbf35b96557	514
Kojto	99:dbbf35b96557	515	/** @defgroup FMC_Access_Mode FMC Access Mode
emilmont	77:869cf507173a	516	* @{
emilmont	77:869cf507173a	517	*/
Kojto	122:f9eeca106725	518	#define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	519	#define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
Kojto	122:f9eeca106725	520	#define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
Kojto	122:f9eeca106725	521	#define FMC_ACCESS_MODE_D ((uint32_t)0x30000000U)
emilmont	77:869cf507173a	522	/**
emilmont	77:869cf507173a	523	* @}
emilmont	77:869cf507173a	524	*/
emilmont	77:869cf507173a	525
emilmont	77:869cf507173a	526	/**
emilmont	77:869cf507173a	527	* @}
Kojto	99:dbbf35b96557	528	*/
emilmont	77:869cf507173a	529
Kojto	99:dbbf35b96557	530	/** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
emilmont	77:869cf507173a	531	* @{
emilmont	77:869cf507173a	532	*/
Kojto	99:dbbf35b96557	533	/** @defgroup FMC_NAND_Bank FMC NAND Bank
emilmont	77:869cf507173a	534	* @{
Kojto	99:dbbf35b96557	535	*/
Kojto	122:f9eeca106725	536	#define FMC_NAND_BANK2 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	537	#define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
emilmont	77:869cf507173a	538	/**
emilmont	77:869cf507173a	539	* @}
emilmont	77:869cf507173a	540	*/
emilmont	77:869cf507173a	541
Kojto	99:dbbf35b96557	542	/** @defgroup FMC_Wait_feature FMC Wait feature
emilmont	77:869cf507173a	543	* @{
emilmont	77:869cf507173a	544	*/
Kojto	122:f9eeca106725	545	#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	546	#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
emilmont	77:869cf507173a	547	/**
emilmont	77:869cf507173a	548	* @}
emilmont	77:869cf507173a	549	*/
emilmont	77:869cf507173a	550
Kojto	99:dbbf35b96557	551	/** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
emilmont	77:869cf507173a	552	* @{
emilmont	77:869cf507173a	553	*/
Kojto	122:f9eeca106725	554	#define FMC_PCR_MEMORY_TYPE_PCCARD ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	555	#define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
emilmont	77:869cf507173a	556	/**
emilmont	77:869cf507173a	557	* @}
emilmont	77:869cf507173a	558	*/
emilmont	77:869cf507173a	559
Kojto	99:dbbf35b96557	560	/** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
emilmont	77:869cf507173a	561	* @{
emilmont	77:869cf507173a	562	*/
Kojto	122:f9eeca106725	563	#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	564	#define FMC_NAND_PCC_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
emilmont	77:869cf507173a	565	/**
emilmont	77:869cf507173a	566	* @}
emilmont	77:869cf507173a	567	*/
emilmont	77:869cf507173a	568
Kojto	99:dbbf35b96557	569	/** @defgroup FMC_ECC FMC ECC
emilmont	77:869cf507173a	570	* @{
emilmont	77:869cf507173a	571	*/
Kojto	122:f9eeca106725	572	#define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	573	#define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
emilmont	77:869cf507173a	574	/**
emilmont	77:869cf507173a	575	* @}
emilmont	77:869cf507173a	576	*/
emilmont	77:869cf507173a	577
Kojto	99:dbbf35b96557	578	/** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
emilmont	77:869cf507173a	579	* @{
emilmont	77:869cf507173a	580	*/
Kojto	122:f9eeca106725	581	#define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	582	#define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
Kojto	122:f9eeca106725	583	#define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
Kojto	122:f9eeca106725	584	#define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
Kojto	122:f9eeca106725	585	#define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
Kojto	122:f9eeca106725	586	#define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
emilmont	77:869cf507173a	587	/**
emilmont	77:869cf507173a	588	* @}
emilmont	77:869cf507173a	589	*/
Kojto	99:dbbf35b96557	590
emilmont	77:869cf507173a	591	/**
emilmont	77:869cf507173a	592	* @}
Kojto	99:dbbf35b96557	593	*/
emilmont	77:869cf507173a	594
Kojto	99:dbbf35b96557	595	/** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
emilmont	77:869cf507173a	596	* @{
emilmont	77:869cf507173a	597	*/
Kojto	99:dbbf35b96557	598	/** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
emilmont	77:869cf507173a	599	* @{
emilmont	77:869cf507173a	600	*/
Kojto	122:f9eeca106725	601	#define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	602	#define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
emilmont	77:869cf507173a	603	/**
emilmont	77:869cf507173a	604	* @}
emilmont	77:869cf507173a	605	*/
emilmont	77:869cf507173a	606
Kojto	99:dbbf35b96557	607	/** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
emilmont	77:869cf507173a	608	* @{
emilmont	77:869cf507173a	609	*/
Kojto	122:f9eeca106725	610	#define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	611	#define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	612	#define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	613	#define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
emilmont	77:869cf507173a	614	/**
emilmont	77:869cf507173a	615	* @}
emilmont	77:869cf507173a	616	*/
emilmont	77:869cf507173a	617
Kojto	99:dbbf35b96557	618	/** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
emilmont	77:869cf507173a	619	* @{
emilmont	77:869cf507173a	620	*/
Kojto	122:f9eeca106725	621	#define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	622	#define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	623	#define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
emilmont	77:869cf507173a	624	/**
emilmont	77:869cf507173a	625	* @}
emilmont	77:869cf507173a	626	*/
emilmont	77:869cf507173a	627
Kojto	99:dbbf35b96557	628	/** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
emilmont	77:869cf507173a	629	* @{
emilmont	77:869cf507173a	630	*/
Kojto	122:f9eeca106725	631	#define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	632	#define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	633	#define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
emilmont	77:869cf507173a	634	/**
emilmont	77:869cf507173a	635	* @}
emilmont	77:869cf507173a	636	*/
emilmont	77:869cf507173a	637
Kojto	99:dbbf35b96557	638	/** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
emilmont	77:869cf507173a	639	* @{
emilmont	77:869cf507173a	640	*/
Kojto	122:f9eeca106725	641	#define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	642	#define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
emilmont	77:869cf507173a	643	/**
emilmont	77:869cf507173a	644	* @}
emilmont	77:869cf507173a	645	*/
emilmont	77:869cf507173a	646
Kojto	99:dbbf35b96557	647	/** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
emilmont	77:869cf507173a	648	* @{
emilmont	77:869cf507173a	649	*/
Kojto	122:f9eeca106725	650	#define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
Kojto	122:f9eeca106725	651	#define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
Kojto	122:f9eeca106725	652	#define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180U)
emilmont	77:869cf507173a	653	/**
emilmont	77:869cf507173a	654	* @}
emilmont	77:869cf507173a	655	*/
emilmont	77:869cf507173a	656
Kojto	99:dbbf35b96557	657	/** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
emilmont	77:869cf507173a	658	* @{
emilmont	77:869cf507173a	659	*/
Kojto	122:f9eeca106725	660	#define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	661	#define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
emilmont	77:869cf507173a	662
emilmont	77:869cf507173a	663	/**
emilmont	77:869cf507173a	664	* @}
emilmont	77:869cf507173a	665	*/
emilmont	77:869cf507173a	666
Kojto	99:dbbf35b96557	667	/** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
emilmont	77:869cf507173a	668	* @{
emilmont	77:869cf507173a	669	*/
Kojto	122:f9eeca106725	670	#define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	671	#define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
Kojto	122:f9eeca106725	672	#define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00U)
emilmont	77:869cf507173a	673	/**
emilmont	77:869cf507173a	674	* @}
emilmont	77:869cf507173a	675	*/
emilmont	77:869cf507173a	676
Kojto	99:dbbf35b96557	677	/** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
emilmont	77:869cf507173a	678	* @{
emilmont	77:869cf507173a	679	*/
Kojto	122:f9eeca106725	680	#define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	681	#define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
emilmont	77:869cf507173a	682	/**
emilmont	77:869cf507173a	683	* @}
emilmont	77:869cf507173a	684	*/
emilmont	77:869cf507173a	685
Kojto	99:dbbf35b96557	686	/** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
emilmont	77:869cf507173a	687	* @{
emilmont	77:869cf507173a	688	*/
Kojto	122:f9eeca106725	689	#define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	690	#define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
Kojto	122:f9eeca106725	691	#define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
emilmont	77:869cf507173a	692	/**
emilmont	77:869cf507173a	693	* @}
emilmont	77:869cf507173a	694	*/
emilmont	77:869cf507173a	695
Kojto	99:dbbf35b96557	696	/** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
emilmont	77:869cf507173a	697	* @{
emilmont	77:869cf507173a	698	*/
Kojto	122:f9eeca106725	699	#define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
Kojto	122:f9eeca106725	700	#define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	701	#define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	702	#define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
Kojto	122:f9eeca106725	703	#define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	704	#define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
Kojto	122:f9eeca106725	705	#define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
emilmont	77:869cf507173a	706	/**
emilmont	77:869cf507173a	707	* @}
emilmont	77:869cf507173a	708	*/
emilmont	77:869cf507173a	709
Kojto	99:dbbf35b96557	710	/** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
emilmont	77:869cf507173a	711	* @{
emilmont	77:869cf507173a	712	*/
emilmont	77:869cf507173a	713	#define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
emilmont	77:869cf507173a	714	#define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
Kojto	122:f9eeca106725	715	#define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
emilmont	77:869cf507173a	716	/**
emilmont	77:869cf507173a	717	* @}
emilmont	77:869cf507173a	718	*/
emilmont	77:869cf507173a	719
Kojto	99:dbbf35b96557	720	/** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
emilmont	77:869cf507173a	721	* @{
emilmont	77:869cf507173a	722	*/
Kojto	122:f9eeca106725	723	#define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
emilmont	77:869cf507173a	724	#define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
emilmont	77:869cf507173a	725	#define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
emilmont	77:869cf507173a	726	/**
emilmont	77:869cf507173a	727	* @}
emilmont	77:869cf507173a	728	*/
Kojto	99:dbbf35b96557	729
emilmont	77:869cf507173a	730	/**
emilmont	77:869cf507173a	731	* @}
emilmont	77:869cf507173a	732	*/
emilmont	77:869cf507173a	733
Kojto	99:dbbf35b96557	734	/** @defgroup FMC_LL_Interrupt_definition FMC Interrupt definition
emilmont	77:869cf507173a	735	* @{
emilmont	77:869cf507173a	736	*/
Kojto	122:f9eeca106725	737	#define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
Kojto	122:f9eeca106725	738	#define FMC_IT_LEVEL ((uint32_t)0x00000010U)
Kojto	122:f9eeca106725	739	#define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
Kojto	122:f9eeca106725	740	#define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
emilmont	77:869cf507173a	741	/**
emilmont	77:869cf507173a	742	* @}
emilmont	77:869cf507173a	743	*/
emilmont	77:869cf507173a	744
Kojto	99:dbbf35b96557	745	/** @defgroup FMC_LL_Flag_definition FMC Flag definition
emilmont	77:869cf507173a	746	* @{
emilmont	77:869cf507173a	747	*/
Kojto	122:f9eeca106725	748	#define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
Kojto	122:f9eeca106725	749	#define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
Kojto	122:f9eeca106725	750	#define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
Kojto	122:f9eeca106725	751	#define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
emilmont	77:869cf507173a	752	#define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
emilmont	77:869cf507173a	753	#define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
emilmont	77:869cf507173a	754	#define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
emilmont	77:869cf507173a	755	/**
emilmont	77:869cf507173a	756	* @}
emilmont	77:869cf507173a	757	*/
emilmont	77:869cf507173a	758
Kojto	99:dbbf35b96557	759	/** @defgroup FMC_LL_Alias_definition FMC Alias definition
Kojto	99:dbbf35b96557	760	* @{
Kojto	99:dbbf35b96557	761	*/
Kojto	110:165afa46840b	762	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	763	#define FMC_NAND_TypeDef FMC_Bank3_TypeDef
Kojto	99:dbbf35b96557	764	#else
Kojto	99:dbbf35b96557	765	#define FMC_NAND_TypeDef FMC_Bank2_3_TypeDef
Kojto	99:dbbf35b96557	766	#define FMC_PCCARD_TypeDef FMC_Bank4_TypeDef
Kojto	110:165afa46840b	767	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	768	#define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
Kojto	99:dbbf35b96557	769	#define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
Kojto	99:dbbf35b96557	770	#define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
Kojto	99:dbbf35b96557	771
emilmont	77:869cf507173a	772
Kojto	110:165afa46840b	773	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	774	#define FMC_NAND_DEVICE FMC_Bank3
Kojto	99:dbbf35b96557	775	#else
Kojto	99:dbbf35b96557	776	#define FMC_NAND_DEVICE FMC_Bank2_3
Kojto	99:dbbf35b96557	777	#define FMC_PCCARD_DEVICE FMC_Bank4
Kojto	110:165afa46840b	778	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	779	#define FMC_NORSRAM_DEVICE FMC_Bank1
Kojto	99:dbbf35b96557	780	#define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
Kojto	99:dbbf35b96557	781	#define FMC_SDRAM_DEVICE FMC_Bank5_6
Kojto	99:dbbf35b96557	782	/**
Kojto	99:dbbf35b96557	783	* @}
Kojto	99:dbbf35b96557	784	*/
Kojto	99:dbbf35b96557	785
Kojto	99:dbbf35b96557	786	/**
Kojto	99:dbbf35b96557	787	* @}
Kojto	99:dbbf35b96557	788	*/
Kojto	99:dbbf35b96557	789
Kojto	99:dbbf35b96557	790	/* Private macro -------------------------------------------------------------*/
Kojto	99:dbbf35b96557	791	/** @defgroup FMC_LL_Private_Macros FMC Private Macros
Kojto	99:dbbf35b96557	792	* @{
Kojto	99:dbbf35b96557	793	*/
Kojto	99:dbbf35b96557	794
Kojto	99:dbbf35b96557	795	/** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
emilmont	77:869cf507173a	796	* @brief macros to handle NOR device enable/disable and read/write operations
emilmont	77:869cf507173a	797	* @{
emilmont	77:869cf507173a	798	*/
emilmont	77:869cf507173a	799	/**
emilmont	77:869cf507173a	800	* @brief Enable the NORSRAM device access.
emilmont	77:869cf507173a	801	* @param __INSTANCE__: FMC_NORSRAM Instance
emilmont	77:869cf507173a	802	* @param __BANK__: FMC_NORSRAM Bank
emilmont	77:869cf507173a	803	* @retval None
emilmont	77:869cf507173a	804	*/
emilmont	77:869cf507173a	805	#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] \|= FMC_BCR1_MBKEN)
emilmont	77:869cf507173a	806
emilmont	77:869cf507173a	807	/**
emilmont	77:869cf507173a	808	* @brief Disable the NORSRAM device access.
emilmont	77:869cf507173a	809	* @param __INSTANCE__: FMC_NORSRAM Instance
emilmont	77:869cf507173a	810	* @param __BANK__: FMC_NORSRAM Bank
emilmont	77:869cf507173a	811	* @retval None
emilmont	77:869cf507173a	812	*/
emilmont	77:869cf507173a	813	#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
emilmont	77:869cf507173a	814	/**
emilmont	77:869cf507173a	815	* @}
emilmont	77:869cf507173a	816	*/
emilmont	77:869cf507173a	817
Kojto	99:dbbf35b96557	818	/** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
emilmont	77:869cf507173a	819	* @brief macros to handle NAND device enable/disable
emilmont	77:869cf507173a	820	* @{
emilmont	77:869cf507173a	821	*/
Kojto	110:165afa46840b	822	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	823	/**
Kojto	99:dbbf35b96557	824	* @brief Enable the NAND device access.
Kojto	99:dbbf35b96557	825	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	826	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	827	* @retval None
Kojto	99:dbbf35b96557	828	*/
Kojto	99:dbbf35b96557	829	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR \|= FMC_PCR_PBKEN)
Kojto	99:dbbf35b96557	830
Kojto	99:dbbf35b96557	831	/**
Kojto	99:dbbf35b96557	832	* @brief Disable the NAND device access.
Kojto	99:dbbf35b96557	833	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	834	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	835	* @retval None
Kojto	99:dbbf35b96557	836	*/
Kojto	99:dbbf35b96557	837	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
Kojto	99:dbbf35b96557	838	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
emilmont	77:869cf507173a	839	/**
emilmont	77:869cf507173a	840	* @brief Enable the NAND device access.
emilmont	77:869cf507173a	841	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	842	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	843	* @retval None
emilmont	77:869cf507173a	844	*/
emilmont	77:869cf507173a	845	#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 \|= FMC_PCR2_PBKEN): \
bogdanm	85:024bf7f99721	846	((__INSTANCE__)->PCR3 \|= FMC_PCR3_PBKEN))
emilmont	77:869cf507173a	847
emilmont	77:869cf507173a	848	/**
emilmont	77:869cf507173a	849	* @brief Disable the NAND device access.
emilmont	77:869cf507173a	850	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	851	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	852	* @retval None
bogdanm	85:024bf7f99721	853	*/
emilmont	77:869cf507173a	854	#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
Kojto	122:f9eeca106725	855	((__INSTANCE__)->PCR3 &= ~FMC_PCR3_PBKEN))
Kojto	99:dbbf35b96557	856
Kojto	110:165afa46840b	857	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
emilmont	77:869cf507173a	858	/**
emilmont	77:869cf507173a	859	* @}
emilmont	77:869cf507173a	860	*/
Kojto	99:dbbf35b96557	861	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	862	/** @defgroup FMC_LL_PCCARD_Macros FMC PCCARD Macros
emilmont	77:869cf507173a	863	* @brief macros to handle SRAM read/write operations
emilmont	77:869cf507173a	864	* @{
emilmont	77:869cf507173a	865	*/
emilmont	77:869cf507173a	866	/**
emilmont	77:869cf507173a	867	* @brief Enable the PCCARD device access.
emilmont	77:869cf507173a	868	* @param __INSTANCE__: FMC_PCCARD Instance
emilmont	77:869cf507173a	869	* @retval None
emilmont	77:869cf507173a	870	*/
emilmont	77:869cf507173a	871	#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 \|= FMC_PCR4_PBKEN)
emilmont	77:869cf507173a	872
emilmont	77:869cf507173a	873	/**
emilmont	77:869cf507173a	874	* @brief Disable the PCCARD device access.
emilmont	77:869cf507173a	875	* @param __INSTANCE__: FMC_PCCARD Instance
emilmont	77:869cf507173a	876	* @retval None
emilmont	77:869cf507173a	877	*/
emilmont	77:869cf507173a	878	#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
emilmont	77:869cf507173a	879	/**
emilmont	77:869cf507173a	880	* @}
emilmont	77:869cf507173a	881	*/
Kojto	99:dbbf35b96557	882	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	883
Kojto	99:dbbf35b96557	884	/** @defgroup FMC_LL_Flag_Interrupt_Macros FMC Flag&Interrupt Macros
Kojto	99:dbbf35b96557	885	* @brief macros to handle FMC flags and interrupts
emilmont	77:869cf507173a	886	* @{
emilmont	77:869cf507173a	887	*/
Kojto	110:165afa46840b	888	#if defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	889	/**
Kojto	99:dbbf35b96557	890	* @brief Enable the NAND device interrupt.
Kojto	99:dbbf35b96557	891	* @param __INSTANCE__: FMC_NAND instance
Kojto	99:dbbf35b96557	892	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	893	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	99:dbbf35b96557	894	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	895	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	99:dbbf35b96557	896	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	99:dbbf35b96557	897	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	99:dbbf35b96557	898	* @retval None
Kojto	99:dbbf35b96557	899	*/
Kojto	99:dbbf35b96557	900	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	901
emilmont	77:869cf507173a	902	/**
Kojto	99:dbbf35b96557	903	* @brief Disable the NAND device interrupt.
Kojto	99:dbbf35b96557	904	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	905	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	906	* @param __INTERRUPT__: FMC_NAND interrupt
Kojto	99:dbbf35b96557	907	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	908	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
Kojto	99:dbbf35b96557	909	* @arg FMC_IT_LEVEL: Interrupt level.
Kojto	99:dbbf35b96557	910	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
Kojto	99:dbbf35b96557	911	* @retval None
Kojto	99:dbbf35b96557	912	*/
Kojto	99:dbbf35b96557	913	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
Kojto	122:f9eeca106725	914
Kojto	99:dbbf35b96557	915	/**
Kojto	99:dbbf35b96557	916	* @brief Get flag status of the NAND device.
Kojto	99:dbbf35b96557	917	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	918	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	919	* @param __FLAG__: FMC_NAND flag
Kojto	99:dbbf35b96557	920	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	921	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	99:dbbf35b96557	922	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	99:dbbf35b96557	923	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	99:dbbf35b96557	924	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	99:dbbf35b96557	925	* @retval The state of FLAG (SET or RESET).
Kojto	99:dbbf35b96557	926	*/
Kojto	99:dbbf35b96557	927	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
Kojto	99:dbbf35b96557	928	/**
Kojto	99:dbbf35b96557	929	* @brief Clear flag status of the NAND device.
Kojto	99:dbbf35b96557	930	* @param __INSTANCE__: FMC_NAND Instance
Kojto	99:dbbf35b96557	931	* @param __BANK__: FMC_NAND Bank
Kojto	99:dbbf35b96557	932	* @param __FLAG__: FMC_NAND flag
Kojto	99:dbbf35b96557	933	* This parameter can be any combination of the following values:
Kojto	99:dbbf35b96557	934	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
Kojto	99:dbbf35b96557	935	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
Kojto	99:dbbf35b96557	936	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
Kojto	99:dbbf35b96557	937	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
Kojto	99:dbbf35b96557	938	* @retval None
Kojto	99:dbbf35b96557	939	*/
Kojto	99:dbbf35b96557	940	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
Kojto	99:dbbf35b96557	941	#else /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	942	/**
emilmont	77:869cf507173a	943	* @brief Enable the NAND device interrupt.
emilmont	77:869cf507173a	944	* @param __INSTANCE__: FMC_NAND instance
emilmont	77:869cf507173a	945	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	946	* @param __INTERRUPT__: FMC_NAND interrupt
emilmont	77:869cf507173a	947	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	948	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	949	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	950	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	951	* @retval None
emilmont	77:869cf507173a	952	*/
emilmont	77:869cf507173a	953	#define __FMC_NAND_ENABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 \|= (__INTERRUPT__)): \
Kojto	122:f9eeca106725	954	((__INSTANCE__)->SR3 \|= (__INTERRUPT__)))
emilmont	77:869cf507173a	955
emilmont	77:869cf507173a	956	/**
emilmont	77:869cf507173a	957	* @brief Disable the NAND device interrupt.
Kojto	99:dbbf35b96557	958	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	959	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	960	* @param __INTERRUPT__: FMC_NAND interrupt
emilmont	77:869cf507173a	961	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	962	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	963	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	964	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	965	* @retval None
emilmont	77:869cf507173a	966	*/
emilmont	77:869cf507173a	967	#define __FMC_NAND_DISABLE_IT(__INSTANCE__, __BANK__, __INTERRUPT__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__INTERRUPT__)): \
Kojto	122:f9eeca106725	968	((__INSTANCE__)->SR3 &= ~(__INTERRUPT__)))
Kojto	122:f9eeca106725	969
emilmont	77:869cf507173a	970	/**
emilmont	77:869cf507173a	971	* @brief Get flag status of the NAND device.
Kojto	99:dbbf35b96557	972	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	973	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	974	* @param __FLAG__: FMC_NAND flag
emilmont	77:869cf507173a	975	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	976	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	977	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	978	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	979	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	980	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	981	*/
emilmont	77:869cf507173a	982	#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? (((__INSTANCE__)->SR2 &(__FLAG__)) == (__FLAG__)): \
Kojto	122:f9eeca106725	983	(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
emilmont	77:869cf507173a	984	/**
emilmont	77:869cf507173a	985	* @brief Clear flag status of the NAND device.
Kojto	99:dbbf35b96557	986	* @param __INSTANCE__: FMC_NAND Instance
emilmont	77:869cf507173a	987	* @param __BANK__: FMC_NAND Bank
emilmont	77:869cf507173a	988	* @param __FLAG__: FMC_NAND flag
emilmont	77:869cf507173a	989	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	990	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	991	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	992	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	993	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	994	* @retval None
emilmont	77:869cf507173a	995	*/
emilmont	77:869cf507173a	996	#define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->SR2 &= ~(__FLAG__)): \
Kojto	122:f9eeca106725	997	((__INSTANCE__)->SR3 &= ~(__FLAG__)))
Kojto	110:165afa46840b	998	#endif /* defined(STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx) */
Kojto	99:dbbf35b96557	999
Kojto	99:dbbf35b96557	1000	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
emilmont	77:869cf507173a	1001	/**
emilmont	77:869cf507173a	1002	* @brief Enable the PCCARD device interrupt.
emilmont	77:869cf507173a	1003	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1004	* @param __INTERRUPT__: FMC_PCCARD interrupt
emilmont	77:869cf507173a	1005	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1006	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1007	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1008	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1009	* @retval None
emilmont	77:869cf507173a	1010	*/
emilmont	77:869cf507173a	1011	#define __FMC_PCCARD_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1012
emilmont	77:869cf507173a	1013	/**
emilmont	77:869cf507173a	1014	* @brief Disable the PCCARD device interrupt.
emilmont	77:869cf507173a	1015	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1016	* @param __INTERRUPT__: FMC_PCCARD interrupt
emilmont	77:869cf507173a	1017	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1018	* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
emilmont	77:869cf507173a	1019	* @arg FMC_IT_LEVEL: Interrupt level.
emilmont	77:869cf507173a	1020	* @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
emilmont	77:869cf507173a	1021	* @retval None
emilmont	77:869cf507173a	1022	*/
emilmont	77:869cf507173a	1023	#define __FMC_PCCARD_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR4 &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1024
emilmont	77:869cf507173a	1025	/**
emilmont	77:869cf507173a	1026	* @brief Get flag status of the PCCARD device.
emilmont	77:869cf507173a	1027	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1028	* @param __FLAG__: FMC_PCCARD flag
emilmont	77:869cf507173a	1029	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1030	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1031	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1032	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1033	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1034	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	1035	*/
emilmont	77:869cf507173a	1036	#define __FMC_PCCARD_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SR4 &(__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	1037
emilmont	77:869cf507173a	1038	/**
emilmont	77:869cf507173a	1039	* @brief Clear flag status of the PCCARD device.
emilmont	77:869cf507173a	1040	* @param __INSTANCE__: FMC_PCCARD instance
emilmont	77:869cf507173a	1041	* @param __FLAG__: FMC_PCCARD flag
emilmont	77:869cf507173a	1042	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1043	* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
emilmont	77:869cf507173a	1044	* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
emilmont	77:869cf507173a	1045	* @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
emilmont	77:869cf507173a	1046	* @arg FMC_FLAG_FEMPT: FIFO empty flag.
emilmont	77:869cf507173a	1047	* @retval None
emilmont	77:869cf507173a	1048	*/
emilmont	77:869cf507173a	1049	#define __FMC_PCCARD_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR4 &= ~(__FLAG__))
Kojto	99:dbbf35b96557	1050	#endif /* defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx) */
Kojto	99:dbbf35b96557	1051
emilmont	77:869cf507173a	1052	/**
emilmont	77:869cf507173a	1053	* @brief Enable the SDRAM device interrupt.
emilmont	77:869cf507173a	1054	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1055	* @param __INTERRUPT__: FMC_SDRAM interrupt
emilmont	77:869cf507173a	1056	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1057	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
emilmont	77:869cf507173a	1058	* @retval None
emilmont	77:869cf507173a	1059	*/
emilmont	77:869cf507173a	1060	#define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR \|= (__INTERRUPT__))
emilmont	77:869cf507173a	1061
emilmont	77:869cf507173a	1062	/**
emilmont	77:869cf507173a	1063	* @brief Disable the SDRAM device interrupt.
emilmont	77:869cf507173a	1064	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1065	* @param __INTERRUPT__: FMC_SDRAM interrupt
emilmont	77:869cf507173a	1066	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1067	* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
emilmont	77:869cf507173a	1068	* @retval None
emilmont	77:869cf507173a	1069	*/
emilmont	77:869cf507173a	1070	#define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
emilmont	77:869cf507173a	1071
emilmont	77:869cf507173a	1072	/**
emilmont	77:869cf507173a	1073	* @brief Get flag status of the SDRAM device.
emilmont	77:869cf507173a	1074	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1075	* @param __FLAG__: FMC_SDRAM flag
emilmont	77:869cf507173a	1076	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1077	* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
emilmont	77:869cf507173a	1078	* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
emilmont	77:869cf507173a	1079	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
emilmont	77:869cf507173a	1080	* @retval The state of FLAG (SET or RESET).
emilmont	77:869cf507173a	1081	*/
emilmont	77:869cf507173a	1082	#define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
emilmont	77:869cf507173a	1083
emilmont	77:869cf507173a	1084	/**
emilmont	77:869cf507173a	1085	* @brief Clear flag status of the SDRAM device.
emilmont	77:869cf507173a	1086	* @param __INSTANCE__: FMC_SDRAM instance
emilmont	77:869cf507173a	1087	* @param __FLAG__: FMC_SDRAM flag
emilmont	77:869cf507173a	1088	* This parameter can be any combination of the following values:
emilmont	77:869cf507173a	1089	* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
emilmont	77:869cf507173a	1090	* @retval None
emilmont	77:869cf507173a	1091	*/
emilmont	77:869cf507173a	1092	#define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR \|= (__FLAG__))
emilmont	77:869cf507173a	1093	/**
emilmont	77:869cf507173a	1094	* @}
Kojto	99:dbbf35b96557	1095	*/
Kojto	99:dbbf35b96557	1096
Kojto	99:dbbf35b96557	1097	/** @defgroup FSMC_LL_Assert_Macros FSMC Assert Macros
Kojto	99:dbbf35b96557	1098	* @{
Kojto	99:dbbf35b96557	1099	*/
Kojto	99:dbbf35b96557	1100	#define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) \|\| \
Kojto	99:dbbf35b96557	1101	((BANK) == FMC_NORSRAM_BANK2) \|\| \
Kojto	99:dbbf35b96557	1102	((BANK) == FMC_NORSRAM_BANK3) \|\| \
Kojto	99:dbbf35b96557	1103	((BANK) == FMC_NORSRAM_BANK4))
Kojto	99:dbbf35b96557	1104
Kojto	99:dbbf35b96557	1105	#define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1106	((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
Kojto	99:dbbf35b96557	1107
Kojto	99:dbbf35b96557	1108	#define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) \|\| \
Kojto	99:dbbf35b96557	1109	((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)\|\| \
Kojto	99:dbbf35b96557	1110	((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
Kojto	99:dbbf35b96557	1111
Kojto	99:dbbf35b96557	1112	#define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1113	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	99:dbbf35b96557	1114	((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
Kojto	99:dbbf35b96557	1115
Kojto	99:dbbf35b96557	1116	#define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) \|\| \
Kojto	99:dbbf35b96557	1117	((__MODE__) == FMC_ACCESS_MODE_B) \|\| \
Kojto	99:dbbf35b96557	1118	((__MODE__) == FMC_ACCESS_MODE_C) \|\| \
Kojto	99:dbbf35b96557	1119	((__MODE__) == FMC_ACCESS_MODE_D))
Kojto	99:dbbf35b96557	1120
Kojto	99:dbbf35b96557	1121	#define IS_FMC_NAND_BANK(BANK) (((BANK) == FMC_NAND_BANK2) \|\| \
Kojto	99:dbbf35b96557	1122	((BANK) == FMC_NAND_BANK3))
Kojto	99:dbbf35b96557	1123
Kojto	99:dbbf35b96557	1124	#define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1125	((FEATURE) == FMC_NAND_PCC_WAIT_FEATURE_ENABLE))
Kojto	99:dbbf35b96557	1126
Kojto	99:dbbf35b96557	1127	#define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1128	((WIDTH) == FMC_NAND_PCC_MEM_BUS_WIDTH_16))
Kojto	99:dbbf35b96557	1129
Kojto	99:dbbf35b96557	1130	#define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1131	((STATE) == FMC_NAND_ECC_ENABLE))
Kojto	99:dbbf35b96557	1132
Kojto	99:dbbf35b96557	1133	#define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) \|\| \
Kojto	99:dbbf35b96557	1134	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) \|\| \
Kojto	99:dbbf35b96557	1135	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) \|\| \
Kojto	99:dbbf35b96557	1136	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) \|\| \
Kojto	99:dbbf35b96557	1137	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) \|\| \
Kojto	99:dbbf35b96557	1138	((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
Kojto	99:dbbf35b96557	1139
Kojto	122:f9eeca106725	1140	#define IS_FMC_TCLR_TIME(TIME) ((TIME) <= 255U)
Kojto	99:dbbf35b96557	1141
Kojto	122:f9eeca106725	1142	#define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255U)
Kojto	99:dbbf35b96557	1143
Kojto	122:f9eeca106725	1144	#define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 255U)
Kojto	99:dbbf35b96557	1145
Kojto	122:f9eeca106725	1146	#define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 255U)
Kojto	99:dbbf35b96557	1147
Kojto	122:f9eeca106725	1148	#define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 255U)
Kojto	99:dbbf35b96557	1149
Kojto	122:f9eeca106725	1150	#define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 255U)
Kojto	99:dbbf35b96557	1151
Kojto	99:dbbf35b96557	1152	#define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
Kojto	99:dbbf35b96557	1153
Kojto	99:dbbf35b96557	1154	#define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
Kojto	99:dbbf35b96557	1155
Kojto	99:dbbf35b96557	1156	#define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
Kojto	99:dbbf35b96557	1157
Kojto	99:dbbf35b96557	1158	#define IS_FMC_PCCARD_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_PCCARD_DEVICE)
Kojto	99:dbbf35b96557	1159
Kojto	99:dbbf35b96557	1160	#define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) \|\| \
Kojto	122:f9eeca106725	1161	((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
Kojto	99:dbbf35b96557	1162
Kojto	99:dbbf35b96557	1163	#define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) \|\| \
Kojto	122:f9eeca106725	1164	((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
Kojto	99:dbbf35b96557	1165
Kojto	122:f9eeca106725	1166	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	1167	#define IS_FMC_WRAP_MODE(__MODE__) (((__MODE__) == FMC_WRAP_MODE_DISABLE) \|\| \
Kojto	110:165afa46840b	1168	((__MODE__) == FMC_WRAP_MODE_ENABLE))
Kojto	122:f9eeca106725	1169	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
Kojto	99:dbbf35b96557	1170
Kojto	99:dbbf35b96557	1171	#define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) \|\| \
Kojto	99:dbbf35b96557	1172	((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
Kojto	99:dbbf35b96557	1173
Kojto	99:dbbf35b96557	1174	#define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1175	((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
Kojto	99:dbbf35b96557	1176
Kojto	99:dbbf35b96557	1177	#define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1178	((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
Kojto	99:dbbf35b96557	1179
Kojto	99:dbbf35b96557	1180	#define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1181	((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
Kojto	99:dbbf35b96557	1182
Kojto	99:dbbf35b96557	1183	#define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1184	((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
Kojto	99:dbbf35b96557	1185
Kojto	99:dbbf35b96557	1186	#define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1187	((__BURST__) == FMC_WRITE_BURST_ENABLE))
Kojto	99:dbbf35b96557	1188
Kojto	99:dbbf35b96557	1189	#define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) \|\| \
Kojto	99:dbbf35b96557	1190	((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
Kojto	99:dbbf35b96557	1191
Kojto	122:f9eeca106725	1192	#define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto	99:dbbf35b96557	1193
Kojto	122:f9eeca106725	1194	#define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 15U))
Kojto	99:dbbf35b96557	1195
Kojto	122:f9eeca106725	1196	#define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0U) && ((__TIME__) <= 255U))
Kojto	99:dbbf35b96557	1197
Kojto	122:f9eeca106725	1198	#define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15U)
Kojto	99:dbbf35b96557	1199
Kojto	122:f9eeca106725	1200	#define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1U) && ((__LATENCY__) <= 17U))
Kojto	99:dbbf35b96557	1201
Kojto	122:f9eeca106725	1202	#define IS_FMC_CLK_DIV(DIV) (((DIV) > 1U) && ((DIV) <= 16U))
Kojto	99:dbbf35b96557	1203
Kojto	99:dbbf35b96557	1204	#define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) \|\| \
Kojto	99:dbbf35b96557	1205	((BANK) == FMC_SDRAM_BANK2))
Kojto	99:dbbf35b96557	1206
Kojto	99:dbbf35b96557	1207	#define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) \|\| \
Kojto	99:dbbf35b96557	1208	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) \|\| \
Kojto	99:dbbf35b96557	1209	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) \|\| \
Kojto	99:dbbf35b96557	1210	((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
Kojto	99:dbbf35b96557	1211
Kojto	99:dbbf35b96557	1212	#define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) \|\| \
Kojto	99:dbbf35b96557	1213	((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) \|\| \
Kojto	99:dbbf35b96557	1214	((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
Kojto	99:dbbf35b96557	1215
Kojto	99:dbbf35b96557	1216	#define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) \|\| \
Kojto	99:dbbf35b96557	1217	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) \|\| \
Kojto	99:dbbf35b96557	1218	((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
Kojto	99:dbbf35b96557	1219
Kojto	99:dbbf35b96557	1220	#define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) \|\| \
Kojto	99:dbbf35b96557	1221	((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
Kojto	99:dbbf35b96557	1222
Kojto	99:dbbf35b96557	1223
Kojto	99:dbbf35b96557	1224	#define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) \|\| \
Kojto	99:dbbf35b96557	1225	((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) \|\| \
Kojto	99:dbbf35b96557	1226	((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
Kojto	99:dbbf35b96557	1227
Kojto	99:dbbf35b96557	1228	#define IS_FMC_SDCLOCK_PERIOD(PERIOD) (((PERIOD) == FMC_SDRAM_CLOCK_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1229	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_2) \|\| \
Kojto	99:dbbf35b96557	1230	((PERIOD) == FMC_SDRAM_CLOCK_PERIOD_3))
Kojto	99:dbbf35b96557	1231
Kojto	99:dbbf35b96557	1232	#define IS_FMC_READ_BURST(RBURST) (((RBURST) == FMC_SDRAM_RBURST_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1233	((RBURST) == FMC_SDRAM_RBURST_ENABLE))
Kojto	99:dbbf35b96557	1234
Kojto	99:dbbf35b96557	1235
Kojto	99:dbbf35b96557	1236	#define IS_FMC_READPIPE_DELAY(DELAY) (((DELAY) == FMC_SDRAM_RPIPE_DELAY_0) \|\| \
Kojto	99:dbbf35b96557	1237	((DELAY) == FMC_SDRAM_RPIPE_DELAY_1) \|\| \
Kojto	99:dbbf35b96557	1238	((DELAY) == FMC_SDRAM_RPIPE_DELAY_2))
Kojto	99:dbbf35b96557	1239
Kojto	122:f9eeca106725	1240	#define IS_FMC_LOADTOACTIVE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	99:dbbf35b96557	1241
Kojto	122:f9eeca106725	1242	#define IS_FMC_EXITSELFREFRESH_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	99:dbbf35b96557	1243
Kojto	122:f9eeca106725	1244	#define IS_FMC_SELFREFRESH_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
Kojto	99:dbbf35b96557	1245
Kojto	122:f9eeca106725	1246	#define IS_FMC_ROWCYCLE_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	99:dbbf35b96557	1247
Kojto	122:f9eeca106725	1248	#define IS_FMC_WRITE_RECOVERY_TIME(TIME) (((TIME) > 0U) && ((TIME) <= 16U))
Kojto	99:dbbf35b96557	1249
Kojto	122:f9eeca106725	1250	#define IS_FMC_RP_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	99:dbbf35b96557	1251
Kojto	122:f9eeca106725	1252	#define IS_FMC_RCD_DELAY(DELAY) (((DELAY) > 0U) && ((DELAY) <= 16U))
Kojto	99:dbbf35b96557	1253
Kojto	99:dbbf35b96557	1254	#define IS_FMC_COMMAND_MODE(COMMAND) (((COMMAND) == FMC_SDRAM_CMD_NORMAL_MODE) \|\| \
Kojto	99:dbbf35b96557	1255	((COMMAND) == FMC_SDRAM_CMD_CLK_ENABLE) \|\| \
Kojto	99:dbbf35b96557	1256	((COMMAND) == FMC_SDRAM_CMD_PALL) \|\| \
Kojto	99:dbbf35b96557	1257	((COMMAND) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) \|\| \
Kojto	99:dbbf35b96557	1258	((COMMAND) == FMC_SDRAM_CMD_LOAD_MODE) \|\| \
Kojto	99:dbbf35b96557	1259	((COMMAND) == FMC_SDRAM_CMD_SELFREFRESH_MODE) \|\| \
Kojto	99:dbbf35b96557	1260	((COMMAND) == FMC_SDRAM_CMD_POWERDOWN_MODE))
Kojto	99:dbbf35b96557	1261
Kojto	99:dbbf35b96557	1262	#define IS_FMC_COMMAND_TARGET(TARGET) (((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1) \|\| \
Kojto	99:dbbf35b96557	1263	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK2) \|\| \
Kojto	99:dbbf35b96557	1264	((TARGET) == FMC_SDRAM_CMD_TARGET_BANK1_2))
Kojto	99:dbbf35b96557	1265
Kojto	122:f9eeca106725	1266	#define IS_FMC_AUTOREFRESH_NUMBER(NUMBER) (((NUMBER) > 0U) && ((NUMBER) <= 16U))
Kojto	99:dbbf35b96557	1267
Kojto	122:f9eeca106725	1268	#define IS_FMC_MODE_REGISTER(CONTENT) ((CONTENT) <= 8191U)
Kojto	99:dbbf35b96557	1269
Kojto	122:f9eeca106725	1270	#define IS_FMC_REFRESH_RATE(RATE) ((RATE) <= 8191U)
Kojto	99:dbbf35b96557	1271
Kojto	99:dbbf35b96557	1272	#define IS_FMC_SDRAM_DEVICE(INSTANCE) ((INSTANCE) == FMC_SDRAM_DEVICE)
Kojto	99:dbbf35b96557	1273
Kojto	99:dbbf35b96557	1274	#define IS_FMC_WRITE_PROTECTION(WRITE) (((WRITE) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1275	((WRITE) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
Kojto	122:f9eeca106725	1276
Kojto	99:dbbf35b96557	1277	#define IS_FMC_PAGESIZE(SIZE) (((SIZE) == FMC_PAGE_SIZE_NONE) \|\| \
Kojto	122:f9eeca106725	1278	((SIZE) == FMC_PAGE_SIZE_128) \|\| \
Kojto	122:f9eeca106725	1279	((SIZE) == FMC_PAGE_SIZE_256) \|\| \
Kojto	122:f9eeca106725	1280	((SIZE) == FMC_PAGE_SIZE_512) \|\| \
Kojto	99:dbbf35b96557	1281	((SIZE) == FMC_PAGE_SIZE_1024))
Kojto	99:dbbf35b96557	1282
Kojto	122:f9eeca106725	1283	#if defined (STM32F446xx) \|\| defined(STM32F469xx) \|\| defined(STM32F479xx)
Kojto	99:dbbf35b96557	1284	#define IS_FMC_WRITE_FIFO(FIFO) (((FIFO) == FMC_WRITE_FIFO_DISABLE) \|\| \
Kojto	99:dbbf35b96557	1285	((FIFO) == FMC_WRITE_FIFO_ENABLE))
Kojto	122:f9eeca106725	1286	#endif /* STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	1287
Kojto	99:dbbf35b96557	1288	/**
Kojto	99:dbbf35b96557	1289	* @}
Kojto	99:dbbf35b96557	1290	*/
Kojto	99:dbbf35b96557	1291
Kojto	99:dbbf35b96557	1292	/**
Kojto	99:dbbf35b96557	1293	* @}
emilmont	77:869cf507173a	1294	*/
emilmont	77:869cf507173a	1295
Kojto	99:dbbf35b96557	1296	/* Private functions ---------------------------------------------------------*/
Kojto	99:dbbf35b96557	1297	/** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
Kojto	99:dbbf35b96557	1298	* @{
Kojto	99:dbbf35b96557	1299	*/
emilmont	77:869cf507173a	1300
Kojto	99:dbbf35b96557	1301	/** @defgroup FMC_LL_NORSRAM NOR SRAM
Kojto	99:dbbf35b96557	1302	* @{
Kojto	99:dbbf35b96557	1303	*/
Kojto	99:dbbf35b96557	1304	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1305	* @{
Kojto	99:dbbf35b96557	1306	*/
emilmont	77:869cf507173a	1307	HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_InitTypeDef Init);
emilmont	77:869cf507173a	1308	HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1309	HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef Device, FMC_NORSRAM_TimingTypeDef Timing, uint32_t Bank, uint32_t ExtendedMode);
emilmont	77:869cf507173a	1310	HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef Device, FMC_NORSRAM_EXTENDED_TypeDef ExDevice, uint32_t Bank);
Kojto	99:dbbf35b96557	1311	/**
Kojto	99:dbbf35b96557	1312	* @}
Kojto	99:dbbf35b96557	1313	*/
emilmont	77:869cf507173a	1314
Kojto	99:dbbf35b96557	1315	/** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
Kojto	99:dbbf35b96557	1316	* @{
Kojto	99:dbbf35b96557	1317	*/
emilmont	77:869cf507173a	1318	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1319	HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1320	/**
Kojto	99:dbbf35b96557	1321	* @}
Kojto	99:dbbf35b96557	1322	*/
Kojto	99:dbbf35b96557	1323	/**
Kojto	99:dbbf35b96557	1324	* @}
Kojto	99:dbbf35b96557	1325	*/
emilmont	77:869cf507173a	1326
Kojto	99:dbbf35b96557	1327	/** @defgroup FMC_LL_NAND NAND
Kojto	99:dbbf35b96557	1328	* @{
Kojto	99:dbbf35b96557	1329	*/
Kojto	99:dbbf35b96557	1330	/** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1331	* @{
Kojto	99:dbbf35b96557	1332	*/
emilmont	77:869cf507173a	1333	HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef Device, FMC_NAND_InitTypeDef Init);
emilmont	77:869cf507173a	1334	HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1335	HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1336	HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1337	/**
Kojto	99:dbbf35b96557	1338	* @}
Kojto	99:dbbf35b96557	1339	*/
emilmont	77:869cf507173a	1340
Kojto	99:dbbf35b96557	1341	/** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
Kojto	99:dbbf35b96557	1342	* @{
Kojto	99:dbbf35b96557	1343	*/
emilmont	77:869cf507173a	1344	HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1345	HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1346	HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef Device, uint32_t ECCval, uint32_t Bank, uint32_t Timeout);
emilmont	77:869cf507173a	1347
Kojto	99:dbbf35b96557	1348	/**
Kojto	99:dbbf35b96557	1349	* @}
Kojto	99:dbbf35b96557	1350	*/
Kojto	99:dbbf35b96557	1351	/**
Kojto	99:dbbf35b96557	1352	* @}
Kojto	99:dbbf35b96557	1353	*/
Kojto	99:dbbf35b96557	1354	#if defined(STM32F427xx) \|\| defined(STM32F437xx) \|\| defined(STM32F429xx) \|\| defined(STM32F439xx)
Kojto	99:dbbf35b96557	1355	/** @defgroup FMC_LL_PCCARD PCCARD
Kojto	99:dbbf35b96557	1356	* @{
Kojto	99:dbbf35b96557	1357	*/
Kojto	99:dbbf35b96557	1358	/** @defgroup FMC_LL_PCCARD_Private_Functions_Group1 PCCARD Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1359	* @{
Kojto	99:dbbf35b96557	1360	*/
emilmont	77:869cf507173a	1361	HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef Device, FMC_PCCARD_InitTypeDef Init);
emilmont	77:869cf507173a	1362	HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1363	HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1364	HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef Device, FMC_NAND_PCC_TimingTypeDef Timing);
emilmont	77:869cf507173a	1365	HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device);
Kojto	99:dbbf35b96557	1366	/**
Kojto	99:dbbf35b96557	1367	* @}
Kojto	99:dbbf35b96557	1368	*/
Kojto	99:dbbf35b96557	1369	/**
Kojto	99:dbbf35b96557	1370	* @}
Kojto	99:dbbf35b96557	1371	*/
Kojto	99:dbbf35b96557	1372	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx */
emilmont	77:869cf507173a	1373
Kojto	99:dbbf35b96557	1374	/** @defgroup FMC_LL_SDRAM SDRAM
Kojto	99:dbbf35b96557	1375	* @{
Kojto	99:dbbf35b96557	1376	*/
Kojto	99:dbbf35b96557	1377	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
Kojto	99:dbbf35b96557	1378	* @{
Kojto	99:dbbf35b96557	1379	*/
emilmont	77:869cf507173a	1380	HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_InitTypeDef Init);
emilmont	77:869cf507173a	1381	HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef Device, FMC_SDRAM_TimingTypeDef Timing, uint32_t Bank);
emilmont	77:869cf507173a	1382	HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
Kojto	99:dbbf35b96557	1383	/**
Kojto	99:dbbf35b96557	1384	* @}
Kojto	99:dbbf35b96557	1385	*/
emilmont	77:869cf507173a	1386
Kojto	99:dbbf35b96557	1387	/** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
Kojto	99:dbbf35b96557	1388	* @{
Kojto	99:dbbf35b96557	1389	*/
emilmont	77:869cf507173a	1390	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1391	HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1392	HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef Device, FMC_SDRAM_CommandTypeDef Command, uint32_t Timeout);
emilmont	77:869cf507173a	1393	HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
emilmont	77:869cf507173a	1394	HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
emilmont	77:869cf507173a	1395	uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
emilmont	77:869cf507173a	1396	/**
emilmont	77:869cf507173a	1397	* @}
Kojto	99:dbbf35b96557	1398	*/
Kojto	99:dbbf35b96557	1399	/**
Kojto	99:dbbf35b96557	1400	* @}
Kojto	99:dbbf35b96557	1401	*/
emilmont	77:869cf507173a	1402
emilmont	77:869cf507173a	1403	/**
emilmont	77:869cf507173a	1404	* @}
emilmont	77:869cf507173a	1405	*/
Kojto	99:dbbf35b96557	1406
Kojto	110:165afa46840b	1407	#endif /* STM32F427xx \|\| STM32F437xx \|\| STM32F429xx \|\| STM32F439xx \|\| STM32F446xx \|\| STM32F469xx \|\| STM32F479xx */
Kojto	99:dbbf35b96557	1408	/**
Kojto	99:dbbf35b96557	1409	* @}
Kojto	99:dbbf35b96557	1410	*/
Kojto	99:dbbf35b96557	1411
Kojto	99:dbbf35b96557	1412	/**
Kojto	99:dbbf35b96557	1413	* @}
Kojto	99:dbbf35b96557	1414	*/
emilmont	77:869cf507173a	1415	#ifdef __cplusplus
emilmont	77:869cf507173a	1416	}
emilmont	77:869cf507173a	1417	#endif
emilmont	77:869cf507173a	1418
emilmont	77:869cf507173a	1419	#endif /* __STM32F4xx_LL_FMC_H */
emilmont	77:869cf507173a	1420
emilmont	77:869cf507173a	1421	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/