mbed official / mbed

Important changes to repositories hosted on mbed.com

Mbed hosted mercurial repositories are deprecated and are due to be permanently deleted in July 2026.

To keep a copy of this software download the repository Zip archive or clone locally using Mercurial.

It is also possible to export all your personal repositories from the account settings page.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_NRF51822/nrf51.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:
Kojto
Date:
Thu Jul 07 14:34:11 2016 +0100
Revision:
122:f9eeca106725
Parent:
97:433970e64889 
Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 122:f9eeca106725 1 /*
Kojto 122:f9eeca106725 2 * Copyright (c) Nordic Semiconductor ASA
Kojto 122:f9eeca106725 3 * All rights reserved.
Kojto 97:433970e64889 4 *
Kojto 122:f9eeca106725 5 * Redistribution and use in source and binary forms, with or without modification,
Kojto 122:f9eeca106725 6 * are permitted provided that the following conditions are met:
Kojto 97:433970e64889 7 *
Kojto 122:f9eeca106725 8 * 1. Redistributions of source code must retain the above copyright notice, this
Kojto 122:f9eeca106725 9 * list of conditions and the following disclaimer.
emilmont 80:8e73be2a2ac1 10 *
Kojto 122:f9eeca106725 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
Kojto 122:f9eeca106725 12 * list of conditions and the following disclaimer in the documentation and/or
Kojto 122:f9eeca106725 13 * other materials provided with the distribution.
Kojto 122:f9eeca106725 14 *
Kojto 122:f9eeca106725 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
Kojto 122:f9eeca106725 16 * contributors to this software may be used to endorse or promote products
Kojto 122:f9eeca106725 17 * derived from this software without specific prior written permission.
Kojto 97:433970e64889 18 *
Kojto 97:433970e64889 19 *
Kojto 122:f9eeca106725 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
Kojto 122:f9eeca106725 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
Kojto 122:f9eeca106725 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 122:f9eeca106725 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
Kojto 122:f9eeca106725 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
Kojto 122:f9eeca106725 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
Kojto 122:f9eeca106725 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
Kojto 122:f9eeca106725 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
Kojto 122:f9eeca106725 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
Kojto 122:f9eeca106725 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 122:f9eeca106725 30 *
Kojto 122:f9eeca106725 31 */
emilmont 80:8e73be2a2ac1 32
emilmont 80:8e73be2a2ac1 33 #ifndef NRF51_H
emilmont 80:8e73be2a2ac1 34 #define NRF51_H
emilmont 80:8e73be2a2ac1 35
emilmont 80:8e73be2a2ac1 36 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 37 extern "C" {
emilmont 80:8e73be2a2ac1 38 #endif
emilmont 80:8e73be2a2ac1 39
emilmont 80:8e73be2a2ac1 40
emilmont 80:8e73be2a2ac1 41 /* ------------------------- Interrupt Number Definition ------------------------ */
emilmont 80:8e73be2a2ac1 42
emilmont 80:8e73be2a2ac1 43 typedef enum {
emilmont 80:8e73be2a2ac1 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
emilmont 80:8e73be2a2ac1 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
emilmont 80:8e73be2a2ac1 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
emilmont 80:8e73be2a2ac1 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
emilmont 80:8e73be2a2ac1 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
emilmont 80:8e73be2a2ac1 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
emilmont 80:8e73be2a2ac1 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
emilmont 80:8e73be2a2ac1 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
Kojto 122:f9eeca106725 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
emilmont 80:8e73be2a2ac1 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
emilmont 80:8e73be2a2ac1 54 RADIO_IRQn = 1, /*!< 1 RADIO */
emilmont 80:8e73be2a2ac1 55 UART0_IRQn = 2, /*!< 2 UART0 */
emilmont 80:8e73be2a2ac1 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
emilmont 80:8e73be2a2ac1 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
emilmont 80:8e73be2a2ac1 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
emilmont 80:8e73be2a2ac1 59 ADC_IRQn = 7, /*!< 7 ADC */
emilmont 80:8e73be2a2ac1 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
emilmont 80:8e73be2a2ac1 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
emilmont 80:8e73be2a2ac1 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
emilmont 80:8e73be2a2ac1 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
emilmont 80:8e73be2a2ac1 64 TEMP_IRQn = 12, /*!< 12 TEMP */
emilmont 80:8e73be2a2ac1 65 RNG_IRQn = 13, /*!< 13 RNG */
emilmont 80:8e73be2a2ac1 66 ECB_IRQn = 14, /*!< 14 ECB */
emilmont 80:8e73be2a2ac1 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
emilmont 80:8e73be2a2ac1 68 WDT_IRQn = 16, /*!< 16 WDT */
emilmont 80:8e73be2a2ac1 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
emilmont 80:8e73be2a2ac1 70 QDEC_IRQn = 18, /*!< 18 QDEC */
Kojto 97:433970e64889 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
emilmont 80:8e73be2a2ac1 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
emilmont 80:8e73be2a2ac1 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
emilmont 80:8e73be2a2ac1 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
emilmont 80:8e73be2a2ac1 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
emilmont 80:8e73be2a2ac1 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
emilmont 80:8e73be2a2ac1 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
emilmont 80:8e73be2a2ac1 78 } IRQn_Type;
emilmont 80:8e73be2a2ac1 79
emilmont 80:8e73be2a2ac1 80
emilmont 80:8e73be2a2ac1 81 /** @addtogroup Configuration_of_CMSIS
emilmont 80:8e73be2a2ac1 82 * @{
emilmont 80:8e73be2a2ac1 83 */
emilmont 80:8e73be2a2ac1 84
emilmont 80:8e73be2a2ac1 85
emilmont 80:8e73be2a2ac1 86 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 87 /* ================ Processor and Core Peripheral Section ================ */
emilmont 80:8e73be2a2ac1 88 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 89
Kojto 97:433970e64889 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
emilmont 80:8e73be2a2ac1 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
emilmont 80:8e73be2a2ac1 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
emilmont 80:8e73be2a2ac1 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
emilmont 80:8e73be2a2ac1 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
emilmont 80:8e73be2a2ac1 95 /** @} */ /* End of group Configuration_of_CMSIS */
emilmont 80:8e73be2a2ac1 96
Kojto 97:433970e64889 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
Kojto 122:f9eeca106725 98 #include "system_nrf51.h" /*!< nrf51 System */
Kojto 122:f9eeca106725 99
emilmont 80:8e73be2a2ac1 100
emilmont 80:8e73be2a2ac1 101 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 102 /* ================ Device Specific Peripheral Section ================ */
emilmont 80:8e73be2a2ac1 103 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 104
emilmont 80:8e73be2a2ac1 105
emilmont 80:8e73be2a2ac1 106 /** @addtogroup Device_Peripheral_Registers
emilmont 80:8e73be2a2ac1 107 * @{
emilmont 80:8e73be2a2ac1 108 */
emilmont 80:8e73be2a2ac1 109
emilmont 80:8e73be2a2ac1 110
emilmont 80:8e73be2a2ac1 111 /* ------------------- Start of section using anonymous unions ------------------ */
emilmont 80:8e73be2a2ac1 112 #if defined(__CC_ARM)
emilmont 80:8e73be2a2ac1 113 #pragma push
emilmont 80:8e73be2a2ac1 114 #pragma anon_unions
emilmont 80:8e73be2a2ac1 115 #elif defined(__ICCARM__)
emilmont 80:8e73be2a2ac1 116 #pragma language=extended
emilmont 80:8e73be2a2ac1 117 #elif defined(__GNUC__)
emilmont 80:8e73be2a2ac1 118 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 119 #elif defined(__TMS470__)
emilmont 80:8e73be2a2ac1 120 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 121 #elif defined(__TASKING__)
emilmont 80:8e73be2a2ac1 122 #pragma warning 586
emilmont 80:8e73be2a2ac1 123 #else
emilmont 80:8e73be2a2ac1 124 #warning Not supported compiler type
emilmont 80:8e73be2a2ac1 125 #endif
emilmont 80:8e73be2a2ac1 126
emilmont 80:8e73be2a2ac1 127
emilmont 80:8e73be2a2ac1 128 typedef struct {
emilmont 80:8e73be2a2ac1 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
emilmont 80:8e73be2a2ac1 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
emilmont 80:8e73be2a2ac1 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
emilmont 80:8e73be2a2ac1 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
emilmont 80:8e73be2a2ac1 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
emilmont 80:8e73be2a2ac1 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
emilmont 80:8e73be2a2ac1 135 } AMLI_RAMPRI_Type;
emilmont 80:8e73be2a2ac1 136
emilmont 80:8e73be2a2ac1 137 typedef struct {
Kojto 97:433970e64889 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
Kojto 97:433970e64889 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
Kojto 97:433970e64889 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
Kojto 97:433970e64889 141 } SPIM_PSEL_Type;
Kojto 97:433970e64889 142
Kojto 97:433970e64889 143 typedef struct {
Kojto 97:433970e64889 144 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
Kojto 97:433970e64889 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
Kojto 97:433970e64889 147 } SPIM_RXD_Type;
Kojto 97:433970e64889 148
Kojto 97:433970e64889 149 typedef struct {
Kojto 97:433970e64889 150 __IO uint32_t PTR; /*!< Data pointer. */
Kojto 97:433970e64889 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
Kojto 97:433970e64889 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
Kojto 97:433970e64889 153 } SPIM_TXD_Type;
Kojto 97:433970e64889 154
Kojto 97:433970e64889 155 typedef struct {
emilmont 80:8e73be2a2ac1 156 __O uint32_t EN; /*!< Enable channel group. */
emilmont 80:8e73be2a2ac1 157 __O uint32_t DIS; /*!< Disable channel group. */
emilmont 80:8e73be2a2ac1 158 } PPI_TASKS_CHG_Type;
emilmont 80:8e73be2a2ac1 159
emilmont 80:8e73be2a2ac1 160 typedef struct {
emilmont 80:8e73be2a2ac1 161 __IO uint32_t EEP; /*!< Channel event end-point. */
emilmont 80:8e73be2a2ac1 162 __IO uint32_t TEP; /*!< Channel task end-point. */
emilmont 80:8e73be2a2ac1 163 } PPI_CH_Type;
emilmont 80:8e73be2a2ac1 164
emilmont 80:8e73be2a2ac1 165
emilmont 80:8e73be2a2ac1 166 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 167 /* ================ POWER ================ */
emilmont 80:8e73be2a2ac1 168 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 169
emilmont 80:8e73be2a2ac1 170
emilmont 80:8e73be2a2ac1 171 /**
emilmont 80:8e73be2a2ac1 172 * @brief Power Control. (POWER)
emilmont 80:8e73be2a2ac1 173 */
emilmont 80:8e73be2a2ac1 174
emilmont 80:8e73be2a2ac1 175 typedef struct { /*!< POWER Structure */
emilmont 80:8e73be2a2ac1 176 __I uint32_t RESERVED0[30];
emilmont 80:8e73be2a2ac1 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
emilmont 80:8e73be2a2ac1 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
emilmont 80:8e73be2a2ac1 179 __I uint32_t RESERVED1[34];
emilmont 80:8e73be2a2ac1 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
emilmont 80:8e73be2a2ac1 181 __I uint32_t RESERVED2[126];
emilmont 80:8e73be2a2ac1 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 184 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
Kojto 97:433970e64889 186 __I uint32_t RESERVED4[9];
Kojto 97:433970e64889 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
Kojto 97:433970e64889 188 __I uint32_t RESERVED5[53];
emilmont 80:8e73be2a2ac1 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
Kojto 97:433970e64889 190 __I uint32_t RESERVED6[3];
emilmont 80:8e73be2a2ac1 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
Kojto 97:433970e64889 192 __I uint32_t RESERVED7[2];
emilmont 80:8e73be2a2ac1 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
emilmont 80:8e73be2a2ac1 194 register. */
Kojto 97:433970e64889 195 __I uint32_t RESERVED8;
emilmont 80:8e73be2a2ac1 196 __IO uint32_t RAMON; /*!< Ram on/off. */
Kojto 97:433970e64889 197 __I uint32_t RESERVED9[7];
emilmont 80:8e73be2a2ac1 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
emilmont 80:8e73be2a2ac1 199 is a retained register. */
Kojto 97:433970e64889 200 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
Kojto 97:433970e64889 202 __I uint32_t RESERVED11[8];
emilmont 80:8e73be2a2ac1 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
Kojto 97:433970e64889 204 __I uint32_t RESERVED12[291];
Kojto 97:433970e64889 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
emilmont 80:8e73be2a2ac1 206 } NRF_POWER_Type;
emilmont 80:8e73be2a2ac1 207
emilmont 80:8e73be2a2ac1 208
emilmont 80:8e73be2a2ac1 209 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 210 /* ================ CLOCK ================ */
emilmont 80:8e73be2a2ac1 211 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 212
emilmont 80:8e73be2a2ac1 213
emilmont 80:8e73be2a2ac1 214 /**
emilmont 80:8e73be2a2ac1 215 * @brief Clock control. (CLOCK)
emilmont 80:8e73be2a2ac1 216 */
emilmont 80:8e73be2a2ac1 217
emilmont 80:8e73be2a2ac1 218 typedef struct { /*!< CLOCK Structure */
emilmont 80:8e73be2a2ac1 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
emilmont 80:8e73be2a2ac1 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
emilmont 80:8e73be2a2ac1 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
emilmont 80:8e73be2a2ac1 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
emilmont 80:8e73be2a2ac1 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
emilmont 80:8e73be2a2ac1 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
emilmont 80:8e73be2a2ac1 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
emilmont 80:8e73be2a2ac1 226 __I uint32_t RESERVED0[57];
emilmont 80:8e73be2a2ac1 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
emilmont 80:8e73be2a2ac1 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
emilmont 80:8e73be2a2ac1 229 __I uint32_t RESERVED1;
Kojto 97:433970e64889 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
Kojto 97:433970e64889 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
emilmont 80:8e73be2a2ac1 232 __I uint32_t RESERVED2[124];
emilmont 80:8e73be2a2ac1 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 235 __I uint32_t RESERVED3[63];
Kojto 97:433970e64889 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
emilmont 80:8e73be2a2ac1 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
Kojto 97:433970e64889 238 __I uint32_t RESERVED4;
Kojto 97:433970e64889 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
emilmont 80:8e73be2a2ac1 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
Kojto 97:433970e64889 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
Kojto 97:433970e64889 242 triggered. */
Kojto 97:433970e64889 243 __I uint32_t RESERVED5[62];
emilmont 80:8e73be2a2ac1 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
emilmont 80:8e73be2a2ac1 245 __I uint32_t RESERVED6[7];
emilmont 80:8e73be2a2ac1 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
emilmont 80:8e73be2a2ac1 247 __I uint32_t RESERVED7[5];
emilmont 80:8e73be2a2ac1 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
emilmont 80:8e73be2a2ac1 249 } NRF_CLOCK_Type;
emilmont 80:8e73be2a2ac1 250
emilmont 80:8e73be2a2ac1 251
emilmont 80:8e73be2a2ac1 252 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 253 /* ================ MPU ================ */
emilmont 80:8e73be2a2ac1 254 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 255
emilmont 80:8e73be2a2ac1 256
emilmont 80:8e73be2a2ac1 257 /**
emilmont 80:8e73be2a2ac1 258 * @brief Memory Protection Unit. (MPU)
emilmont 80:8e73be2a2ac1 259 */
emilmont 80:8e73be2a2ac1 260
emilmont 80:8e73be2a2ac1 261 typedef struct { /*!< MPU Structure */
emilmont 80:8e73be2a2ac1 262 __I uint32_t RESERVED0[330];
emilmont 80:8e73be2a2ac1 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
emilmont 80:8e73be2a2ac1 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
emilmont 80:8e73be2a2ac1 265 __I uint32_t RESERVED1[52];
Kojto 97:433970e64889 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
Kojto 97:433970e64889 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
Kojto 97:433970e64889 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
emilmont 80:8e73be2a2ac1 270 } NRF_MPU_Type;
emilmont 80:8e73be2a2ac1 271
emilmont 80:8e73be2a2ac1 272
emilmont 80:8e73be2a2ac1 273 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 274 /* ================ AMLI ================ */
emilmont 80:8e73be2a2ac1 275 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 276
emilmont 80:8e73be2a2ac1 277
emilmont 80:8e73be2a2ac1 278 /**
emilmont 80:8e73be2a2ac1 279 * @brief AHB Multi-Layer Interface. (AMLI)
emilmont 80:8e73be2a2ac1 280 */
emilmont 80:8e73be2a2ac1 281
emilmont 80:8e73be2a2ac1 282 typedef struct { /*!< AMLI Structure */
emilmont 80:8e73be2a2ac1 283 __I uint32_t RESERVED0[896];
emilmont 80:8e73be2a2ac1 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
emilmont 80:8e73be2a2ac1 285 } NRF_AMLI_Type;
emilmont 80:8e73be2a2ac1 286
emilmont 80:8e73be2a2ac1 287
emilmont 80:8e73be2a2ac1 288 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 289 /* ================ RADIO ================ */
emilmont 80:8e73be2a2ac1 290 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 291
emilmont 80:8e73be2a2ac1 292
emilmont 80:8e73be2a2ac1 293 /**
emilmont 80:8e73be2a2ac1 294 * @brief The radio. (RADIO)
emilmont 80:8e73be2a2ac1 295 */
emilmont 80:8e73be2a2ac1 296
emilmont 80:8e73be2a2ac1 297 typedef struct { /*!< RADIO Structure */
emilmont 80:8e73be2a2ac1 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
emilmont 80:8e73be2a2ac1 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
emilmont 80:8e73be2a2ac1 300 __O uint32_t TASKS_START; /*!< Start radio. */
emilmont 80:8e73be2a2ac1 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
emilmont 80:8e73be2a2ac1 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
emilmont 80:8e73be2a2ac1 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
emilmont 80:8e73be2a2ac1 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
emilmont 80:8e73be2a2ac1 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
emilmont 80:8e73be2a2ac1 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
emilmont 80:8e73be2a2ac1 307 __I uint32_t RESERVED0[55];
emilmont 80:8e73be2a2ac1 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
emilmont 80:8e73be2a2ac1 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
emilmont 80:8e73be2a2ac1 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
emilmont 80:8e73be2a2ac1 311 __IO uint32_t EVENTS_END; /*!< End event. */
emilmont 80:8e73be2a2ac1 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
emilmont 80:8e73be2a2ac1 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
emilmont 80:8e73be2a2ac1 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
emilmont 80:8e73be2a2ac1 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
emilmont 80:8e73be2a2ac1 316 sample is ready for readout at the RSSISAMPLE register. */
emilmont 80:8e73be2a2ac1 317 __I uint32_t RESERVED1[2];
Kojto 122:f9eeca106725 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
emilmont 80:8e73be2a2ac1 319 __I uint32_t RESERVED2[53];
Kojto 97:433970e64889 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
emilmont 80:8e73be2a2ac1 321 __I uint32_t RESERVED3[64];
emilmont 80:8e73be2a2ac1 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 324 __I uint32_t RESERVED4[61];
emilmont 80:8e73be2a2ac1 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
Kojto 122:f9eeca106725 326 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 327 __I uint32_t RXMATCH; /*!< Received address. */
emilmont 80:8e73be2a2ac1 328 __I uint32_t RXCRC; /*!< Received CRC. */
Kojto 97:433970e64889 329 __I uint32_t DAI; /*!< Device address match index. */
Kojto 122:f9eeca106725 330 __I uint32_t RESERVED6[60];
emilmont 80:8e73be2a2ac1 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
emilmont 80:8e73be2a2ac1 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
emilmont 80:8e73be2a2ac1 333 __IO uint32_t TXPOWER; /*!< Output power. */
emilmont 80:8e73be2a2ac1 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
emilmont 80:8e73be2a2ac1 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
emilmont 80:8e73be2a2ac1 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
emilmont 80:8e73be2a2ac1 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
emilmont 80:8e73be2a2ac1 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
emilmont 80:8e73be2a2ac1 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
emilmont 80:8e73be2a2ac1 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
emilmont 80:8e73be2a2ac1 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
emilmont 80:8e73be2a2ac1 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
emilmont 80:8e73be2a2ac1 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
emilmont 80:8e73be2a2ac1 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
emilmont 80:8e73be2a2ac1 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
emilmont 80:8e73be2a2ac1 346 __IO uint32_t TEST; /*!< Test features enable register. */
emilmont 80:8e73be2a2ac1 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
Kojto 97:433970e64889 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
Kojto 122:f9eeca106725 349 __I uint32_t RESERVED7;
emilmont 80:8e73be2a2ac1 350 __I uint32_t STATE; /*!< Current radio state. */
emilmont 80:8e73be2a2ac1 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
Kojto 122:f9eeca106725 352 __I uint32_t RESERVED8[2];
emilmont 80:8e73be2a2ac1 353 __IO uint32_t BCC; /*!< Bit counter compare. */
Kojto 122:f9eeca106725 354 __I uint32_t RESERVED9[39];
emilmont 80:8e73be2a2ac1 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
emilmont 80:8e73be2a2ac1 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
emilmont 80:8e73be2a2ac1 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
Kojto 122:f9eeca106725 358 __I uint32_t RESERVED10[56];
emilmont 80:8e73be2a2ac1 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
emilmont 80:8e73be2a2ac1 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
emilmont 80:8e73be2a2ac1 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
emilmont 80:8e73be2a2ac1 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
emilmont 80:8e73be2a2ac1 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
Kojto 122:f9eeca106725 364 __I uint32_t RESERVED11[561];
emilmont 80:8e73be2a2ac1 365 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 366 } NRF_RADIO_Type;
emilmont 80:8e73be2a2ac1 367
emilmont 80:8e73be2a2ac1 368
emilmont 80:8e73be2a2ac1 369 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 370 /* ================ UART ================ */
emilmont 80:8e73be2a2ac1 371 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 372
emilmont 80:8e73be2a2ac1 373
emilmont 80:8e73be2a2ac1 374 /**
emilmont 80:8e73be2a2ac1 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
emilmont 80:8e73be2a2ac1 376 */
emilmont 80:8e73be2a2ac1 377
emilmont 80:8e73be2a2ac1 378 typedef struct { /*!< UART Structure */
emilmont 80:8e73be2a2ac1 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
emilmont 80:8e73be2a2ac1 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
emilmont 80:8e73be2a2ac1 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
emilmont 80:8e73be2a2ac1 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
emilmont 80:8e73be2a2ac1 383 __I uint32_t RESERVED0[3];
emilmont 80:8e73be2a2ac1 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
emilmont 80:8e73be2a2ac1 385 __I uint32_t RESERVED1[56];
emilmont 80:8e73be2a2ac1 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
emilmont 80:8e73be2a2ac1 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
emilmont 80:8e73be2a2ac1 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
emilmont 80:8e73be2a2ac1 389 __I uint32_t RESERVED2[4];
emilmont 80:8e73be2a2ac1 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
emilmont 80:8e73be2a2ac1 391 __I uint32_t RESERVED3;
emilmont 80:8e73be2a2ac1 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
emilmont 80:8e73be2a2ac1 393 __I uint32_t RESERVED4[7];
emilmont 80:8e73be2a2ac1 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
emilmont 80:8e73be2a2ac1 395 __I uint32_t RESERVED5[46];
Kojto 97:433970e64889 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
Kojto 97:433970e64889 397 __I uint32_t RESERVED6[64];
emilmont 80:8e73be2a2ac1 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 400 __I uint32_t RESERVED7[93];
emilmont 80:8e73be2a2ac1 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
emilmont 80:8e73be2a2ac1 402 __I uint32_t RESERVED8[31];
emilmont 80:8e73be2a2ac1 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
emilmont 80:8e73be2a2ac1 404 __I uint32_t RESERVED9;
emilmont 80:8e73be2a2ac1 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
emilmont 80:8e73be2a2ac1 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
emilmont 80:8e73be2a2ac1 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
emilmont 80:8e73be2a2ac1 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
emilmont 80:8e73be2a2ac1 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
Kojto 97:433970e64889 410 Once read the character is consumed. If read when no character
emilmont 80:8e73be2a2ac1 411 available, the UART will stop working. */
emilmont 80:8e73be2a2ac1 412 __O uint32_t TXD; /*!< TXD register. */
emilmont 80:8e73be2a2ac1 413 __I uint32_t RESERVED10;
emilmont 80:8e73be2a2ac1 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
emilmont 80:8e73be2a2ac1 415 __I uint32_t RESERVED11[17];
emilmont 80:8e73be2a2ac1 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
emilmont 80:8e73be2a2ac1 417 __I uint32_t RESERVED12[675];
emilmont 80:8e73be2a2ac1 418 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 419 } NRF_UART_Type;
emilmont 80:8e73be2a2ac1 420
emilmont 80:8e73be2a2ac1 421
emilmont 80:8e73be2a2ac1 422 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 423 /* ================ SPI ================ */
emilmont 80:8e73be2a2ac1 424 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 425
emilmont 80:8e73be2a2ac1 426
emilmont 80:8e73be2a2ac1 427 /**
emilmont 80:8e73be2a2ac1 428 * @brief SPI master 0. (SPI)
emilmont 80:8e73be2a2ac1 429 */
emilmont 80:8e73be2a2ac1 430
emilmont 80:8e73be2a2ac1 431 typedef struct { /*!< SPI Structure */
emilmont 80:8e73be2a2ac1 432 __I uint32_t RESERVED0[66];
emilmont 80:8e73be2a2ac1 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
emilmont 80:8e73be2a2ac1 434 __I uint32_t RESERVED1[126];
emilmont 80:8e73be2a2ac1 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 437 __I uint32_t RESERVED2[125];
emilmont 80:8e73be2a2ac1 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
emilmont 80:8e73be2a2ac1 439 __I uint32_t RESERVED3;
emilmont 80:8e73be2a2ac1 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
emilmont 80:8e73be2a2ac1 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
emilmont 80:8e73be2a2ac1 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
emilmont 80:8e73be2a2ac1 443 __I uint32_t RESERVED4;
Kojto 97:433970e64889 444 __I uint32_t RXD; /*!< RX data. */
emilmont 80:8e73be2a2ac1 445 __IO uint32_t TXD; /*!< TX data. */
emilmont 80:8e73be2a2ac1 446 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
emilmont 80:8e73be2a2ac1 448 __I uint32_t RESERVED6[11];
emilmont 80:8e73be2a2ac1 449 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 450 __I uint32_t RESERVED7[681];
emilmont 80:8e73be2a2ac1 451 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 452 } NRF_SPI_Type;
emilmont 80:8e73be2a2ac1 453
emilmont 80:8e73be2a2ac1 454
emilmont 80:8e73be2a2ac1 455 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 456 /* ================ TWI ================ */
emilmont 80:8e73be2a2ac1 457 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 458
emilmont 80:8e73be2a2ac1 459
emilmont 80:8e73be2a2ac1 460 /**
emilmont 80:8e73be2a2ac1 461 * @brief Two-wire interface master 0. (TWI)
emilmont 80:8e73be2a2ac1 462 */
emilmont 80:8e73be2a2ac1 463
emilmont 80:8e73be2a2ac1 464 typedef struct { /*!< TWI Structure */
emilmont 80:8e73be2a2ac1 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
emilmont 80:8e73be2a2ac1 466 __I uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
emilmont 80:8e73be2a2ac1 468 __I uint32_t RESERVED1[2];
emilmont 80:8e73be2a2ac1 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
emilmont 80:8e73be2a2ac1 470 __I uint32_t RESERVED2;
emilmont 80:8e73be2a2ac1 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
emilmont 80:8e73be2a2ac1 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
emilmont 80:8e73be2a2ac1 473 __I uint32_t RESERVED3[56];
emilmont 80:8e73be2a2ac1 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
emilmont 80:8e73be2a2ac1 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
emilmont 80:8e73be2a2ac1 476 __I uint32_t RESERVED4[4];
emilmont 80:8e73be2a2ac1 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
emilmont 80:8e73be2a2ac1 478 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
emilmont 80:8e73be2a2ac1 480 __I uint32_t RESERVED6[4];
emilmont 80:8e73be2a2ac1 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
Kojto 97:433970e64889 482 __I uint32_t RESERVED7[3];
Kojto 97:433970e64889 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
Kojto 97:433970e64889 484 __I uint32_t RESERVED8[45];
emilmont 80:8e73be2a2ac1 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
Kojto 97:433970e64889 486 __I uint32_t RESERVED9[64];
emilmont 80:8e73be2a2ac1 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 97:433970e64889 489 __I uint32_t RESERVED10[110];
emilmont 80:8e73be2a2ac1 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
Kojto 97:433970e64889 491 __I uint32_t RESERVED11[14];
emilmont 80:8e73be2a2ac1 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
Kojto 97:433970e64889 493 __I uint32_t RESERVED12;
emilmont 80:8e73be2a2ac1 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
emilmont 80:8e73be2a2ac1 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
Kojto 97:433970e64889 496 __I uint32_t RESERVED13[2];
Kojto 97:433970e64889 497 __I uint32_t RXD; /*!< RX data register. */
emilmont 80:8e73be2a2ac1 498 __IO uint32_t TXD; /*!< TX data register. */
Kojto 97:433970e64889 499 __I uint32_t RESERVED14;
emilmont 80:8e73be2a2ac1 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
Kojto 97:433970e64889 501 __I uint32_t RESERVED15[24];
emilmont 80:8e73be2a2ac1 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
Kojto 97:433970e64889 503 __I uint32_t RESERVED16[668];
emilmont 80:8e73be2a2ac1 504 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 505 } NRF_TWI_Type;
emilmont 80:8e73be2a2ac1 506
emilmont 80:8e73be2a2ac1 507
emilmont 80:8e73be2a2ac1 508 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 509 /* ================ SPIS ================ */
emilmont 80:8e73be2a2ac1 510 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 511
emilmont 80:8e73be2a2ac1 512
emilmont 80:8e73be2a2ac1 513 /**
emilmont 80:8e73be2a2ac1 514 * @brief SPI slave 1. (SPIS)
emilmont 80:8e73be2a2ac1 515 */
emilmont 80:8e73be2a2ac1 516
emilmont 80:8e73be2a2ac1 517 typedef struct { /*!< SPIS Structure */
emilmont 80:8e73be2a2ac1 518 __I uint32_t RESERVED0[9];
emilmont 80:8e73be2a2ac1 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
emilmont 80:8e73be2a2ac1 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
emilmont 80:8e73be2a2ac1 521 __I uint32_t RESERVED1[54];
emilmont 80:8e73be2a2ac1 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
Kojto 122:f9eeca106725 523 __I uint32_t RESERVED2[2];
Kojto 122:f9eeca106725 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
Kojto 122:f9eeca106725 525 __I uint32_t RESERVED3[5];
emilmont 80:8e73be2a2ac1 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
Kojto 122:f9eeca106725 527 __I uint32_t RESERVED4[53];
emilmont 80:8e73be2a2ac1 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
Kojto 122:f9eeca106725 529 __I uint32_t RESERVED5[64];
emilmont 80:8e73be2a2ac1 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 532 __I uint32_t RESERVED6[61];
emilmont 80:8e73be2a2ac1 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
Kojto 122:f9eeca106725 534 __I uint32_t RESERVED7[15];
emilmont 80:8e73be2a2ac1 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
Kojto 122:f9eeca106725 536 __I uint32_t RESERVED8[47];
emilmont 80:8e73be2a2ac1 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
Kojto 122:f9eeca106725 538 __I uint32_t RESERVED9;
emilmont 80:8e73be2a2ac1 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
emilmont 80:8e73be2a2ac1 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
emilmont 80:8e73be2a2ac1 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
emilmont 80:8e73be2a2ac1 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
Kojto 122:f9eeca106725 543 __I uint32_t RESERVED10[7];
emilmont 80:8e73be2a2ac1 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
emilmont 80:8e73be2a2ac1 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
Kojto 97:433970e64889 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
Kojto 122:f9eeca106725 547 __I uint32_t RESERVED11;
emilmont 80:8e73be2a2ac1 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
emilmont 80:8e73be2a2ac1 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
Kojto 97:433970e64889 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
Kojto 122:f9eeca106725 551 __I uint32_t RESERVED12;
emilmont 80:8e73be2a2ac1 552 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 553 __I uint32_t RESERVED13;
emilmont 80:8e73be2a2ac1 554 __IO uint32_t DEF; /*!< Default character. */
Kojto 122:f9eeca106725 555 __I uint32_t RESERVED14[24];
emilmont 80:8e73be2a2ac1 556 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 557 __I uint32_t RESERVED15[654];
emilmont 80:8e73be2a2ac1 558 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 559 } NRF_SPIS_Type;
emilmont 80:8e73be2a2ac1 560
emilmont 80:8e73be2a2ac1 561
emilmont 80:8e73be2a2ac1 562 /* ================================================================================ */
Kojto 97:433970e64889 563 /* ================ SPIM ================ */
Kojto 97:433970e64889 564 /* ================================================================================ */
Kojto 97:433970e64889 565
Kojto 97:433970e64889 566
Kojto 97:433970e64889 567 /**
Kojto 97:433970e64889 568 * @brief SPI master with easyDMA 1. (SPIM)
Kojto 97:433970e64889 569 */
Kojto 97:433970e64889 570
Kojto 97:433970e64889 571 typedef struct { /*!< SPIM Structure */
Kojto 97:433970e64889 572 __I uint32_t RESERVED0[4];
Kojto 97:433970e64889 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
Kojto 97:433970e64889 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
Kojto 97:433970e64889 575 __I uint32_t RESERVED1;
Kojto 97:433970e64889 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
Kojto 97:433970e64889 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
Kojto 97:433970e64889 578 __I uint32_t RESERVED2[56];
Kojto 97:433970e64889 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
Kojto 97:433970e64889 580 __I uint32_t RESERVED3[2];
Kojto 97:433970e64889 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
Kojto 122:f9eeca106725 582 __I uint32_t RESERVED4[3];
Kojto 97:433970e64889 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
Kojto 122:f9eeca106725 584 __I uint32_t RESERVED5[10];
Kojto 97:433970e64889 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
Kojto 122:f9eeca106725 586 __I uint32_t RESERVED6[109];
Kojto 97:433970e64889 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
Kojto 97:433970e64889 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
Kojto 122:f9eeca106725 589 __I uint32_t RESERVED7[125];
Kojto 97:433970e64889 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
Kojto 122:f9eeca106725 591 __I uint32_t RESERVED8;
Kojto 97:433970e64889 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
Kojto 122:f9eeca106725 593 __I uint32_t RESERVED9[4];
Kojto 97:433970e64889 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
Kojto 122:f9eeca106725 595 __I uint32_t RESERVED10[3];
Kojto 97:433970e64889 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 597 __I uint32_t RESERVED11;
Kojto 97:433970e64889 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
Kojto 122:f9eeca106725 599 __I uint32_t RESERVED12;
Kojto 97:433970e64889 600 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 601 __I uint32_t RESERVED13[26];
Kojto 97:433970e64889 602 __IO uint32_t ORC; /*!< Over-read character. */
Kojto 122:f9eeca106725 603 __I uint32_t RESERVED14[654];
Kojto 97:433970e64889 604 __IO uint32_t POWER; /*!< Peripheral power control. */
Kojto 97:433970e64889 605 } NRF_SPIM_Type;
Kojto 97:433970e64889 606
Kojto 97:433970e64889 607
Kojto 97:433970e64889 608 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 609 /* ================ GPIOTE ================ */
emilmont 80:8e73be2a2ac1 610 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 611
emilmont 80:8e73be2a2ac1 612
emilmont 80:8e73be2a2ac1 613 /**
emilmont 80:8e73be2a2ac1 614 * @brief GPIO tasks and events. (GPIOTE)
emilmont 80:8e73be2a2ac1 615 */
emilmont 80:8e73be2a2ac1 616
emilmont 80:8e73be2a2ac1 617 typedef struct { /*!< GPIOTE Structure */
emilmont 80:8e73be2a2ac1 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
emilmont 80:8e73be2a2ac1 619 __I uint32_t RESERVED0[60];
emilmont 80:8e73be2a2ac1 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
emilmont 80:8e73be2a2ac1 621 __I uint32_t RESERVED1[27];
emilmont 80:8e73be2a2ac1 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
emilmont 80:8e73be2a2ac1 623 __I uint32_t RESERVED2[97];
emilmont 80:8e73be2a2ac1 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 626 __I uint32_t RESERVED3[129];
emilmont 80:8e73be2a2ac1 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
emilmont 80:8e73be2a2ac1 628 __I uint32_t RESERVED4[695];
emilmont 80:8e73be2a2ac1 629 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 630 } NRF_GPIOTE_Type;
emilmont 80:8e73be2a2ac1 631
emilmont 80:8e73be2a2ac1 632
emilmont 80:8e73be2a2ac1 633 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 634 /* ================ ADC ================ */
emilmont 80:8e73be2a2ac1 635 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 636
emilmont 80:8e73be2a2ac1 637
emilmont 80:8e73be2a2ac1 638 /**
emilmont 80:8e73be2a2ac1 639 * @brief Analog to digital converter. (ADC)
emilmont 80:8e73be2a2ac1 640 */
emilmont 80:8e73be2a2ac1 641
emilmont 80:8e73be2a2ac1 642 typedef struct { /*!< ADC Structure */
emilmont 80:8e73be2a2ac1 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
emilmont 80:8e73be2a2ac1 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
emilmont 80:8e73be2a2ac1 645 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
emilmont 80:8e73be2a2ac1 647 __I uint32_t RESERVED1[128];
emilmont 80:8e73be2a2ac1 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 650 __I uint32_t RESERVED2[61];
emilmont 80:8e73be2a2ac1 651 __I uint32_t BUSY; /*!< ADC busy register. */
emilmont 80:8e73be2a2ac1 652 __I uint32_t RESERVED3[63];
emilmont 80:8e73be2a2ac1 653 __IO uint32_t ENABLE; /*!< ADC enable. */
emilmont 80:8e73be2a2ac1 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
emilmont 80:8e73be2a2ac1 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
emilmont 80:8e73be2a2ac1 656 __I uint32_t RESERVED4[700];
emilmont 80:8e73be2a2ac1 657 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 658 } NRF_ADC_Type;
emilmont 80:8e73be2a2ac1 659
emilmont 80:8e73be2a2ac1 660
emilmont 80:8e73be2a2ac1 661 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 662 /* ================ TIMER ================ */
emilmont 80:8e73be2a2ac1 663 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 664
emilmont 80:8e73be2a2ac1 665
emilmont 80:8e73be2a2ac1 666 /**
emilmont 80:8e73be2a2ac1 667 * @brief Timer 0. (TIMER)
emilmont 80:8e73be2a2ac1 668 */
emilmont 80:8e73be2a2ac1 669
emilmont 80:8e73be2a2ac1 670 typedef struct { /*!< TIMER Structure */
emilmont 80:8e73be2a2ac1 671 __O uint32_t TASKS_START; /*!< Start Timer. */
emilmont 80:8e73be2a2ac1 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
emilmont 80:8e73be2a2ac1 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
emilmont 80:8e73be2a2ac1 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
Kojto 97:433970e64889 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
Kojto 97:433970e64889 676 __I uint32_t RESERVED0[11];
emilmont 80:8e73be2a2ac1 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
emilmont 80:8e73be2a2ac1 678 __I uint32_t RESERVED1[60];
emilmont 80:8e73be2a2ac1 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
emilmont 80:8e73be2a2ac1 680 __I uint32_t RESERVED2[44];
emilmont 80:8e73be2a2ac1 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
emilmont 80:8e73be2a2ac1 682 __I uint32_t RESERVED3[64];
emilmont 80:8e73be2a2ac1 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 685 __I uint32_t RESERVED4[126];
emilmont 80:8e73be2a2ac1 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
emilmont 80:8e73be2a2ac1 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
emilmont 80:8e73be2a2ac1 688 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
emilmont 80:8e73be2a2ac1 690 clock frequency is divided by 2^SCALE. */
emilmont 80:8e73be2a2ac1 691 __I uint32_t RESERVED6[11];
emilmont 80:8e73be2a2ac1 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
emilmont 80:8e73be2a2ac1 693 __I uint32_t RESERVED7[683];
emilmont 80:8e73be2a2ac1 694 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 695 } NRF_TIMER_Type;
emilmont 80:8e73be2a2ac1 696
emilmont 80:8e73be2a2ac1 697
emilmont 80:8e73be2a2ac1 698 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 699 /* ================ RTC ================ */
emilmont 80:8e73be2a2ac1 700 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 701
emilmont 80:8e73be2a2ac1 702
emilmont 80:8e73be2a2ac1 703 /**
emilmont 80:8e73be2a2ac1 704 * @brief Real time counter 0. (RTC)
emilmont 80:8e73be2a2ac1 705 */
emilmont 80:8e73be2a2ac1 706
emilmont 80:8e73be2a2ac1 707 typedef struct { /*!< RTC Structure */
emilmont 80:8e73be2a2ac1 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
emilmont 80:8e73be2a2ac1 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
emilmont 80:8e73be2a2ac1 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
emilmont 80:8e73be2a2ac1 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
emilmont 80:8e73be2a2ac1 712 __I uint32_t RESERVED0[60];
emilmont 80:8e73be2a2ac1 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
emilmont 80:8e73be2a2ac1 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
emilmont 80:8e73be2a2ac1 715 __I uint32_t RESERVED1[14];
emilmont 80:8e73be2a2ac1 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
emilmont 80:8e73be2a2ac1 717 __I uint32_t RESERVED2[109];
emilmont 80:8e73be2a2ac1 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 720 __I uint32_t RESERVED3[13];
emilmont 80:8e73be2a2ac1 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
emilmont 80:8e73be2a2ac1 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
emilmont 80:8e73be2a2ac1 723 the value of EVTEN. */
emilmont 80:8e73be2a2ac1 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
emilmont 80:8e73be2a2ac1 725 gives the value of EVTEN. */
emilmont 80:8e73be2a2ac1 726 __I uint32_t RESERVED4[110];
Kojto 97:433970e64889 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
emilmont 80:8e73be2a2ac1 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
emilmont 80:8e73be2a2ac1 729 Must be written when RTC is STOPed. */
emilmont 80:8e73be2a2ac1 730 __I uint32_t RESERVED5[13];
emilmont 80:8e73be2a2ac1 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
emilmont 80:8e73be2a2ac1 732 __I uint32_t RESERVED6[683];
emilmont 80:8e73be2a2ac1 733 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 734 } NRF_RTC_Type;
emilmont 80:8e73be2a2ac1 735
emilmont 80:8e73be2a2ac1 736
emilmont 80:8e73be2a2ac1 737 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 738 /* ================ TEMP ================ */
emilmont 80:8e73be2a2ac1 739 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 740
emilmont 80:8e73be2a2ac1 741
emilmont 80:8e73be2a2ac1 742 /**
emilmont 80:8e73be2a2ac1 743 * @brief Temperature Sensor. (TEMP)
emilmont 80:8e73be2a2ac1 744 */
emilmont 80:8e73be2a2ac1 745
emilmont 80:8e73be2a2ac1 746 typedef struct { /*!< TEMP Structure */
emilmont 80:8e73be2a2ac1 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
emilmont 80:8e73be2a2ac1 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
emilmont 80:8e73be2a2ac1 749 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
emilmont 80:8e73be2a2ac1 751 __I uint32_t RESERVED1[128];
emilmont 80:8e73be2a2ac1 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 754 __I uint32_t RESERVED2[127];
emilmont 80:8e73be2a2ac1 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
emilmont 80:8e73be2a2ac1 756 __I uint32_t RESERVED3[700];
emilmont 80:8e73be2a2ac1 757 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 758 } NRF_TEMP_Type;
emilmont 80:8e73be2a2ac1 759
emilmont 80:8e73be2a2ac1 760
emilmont 80:8e73be2a2ac1 761 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 762 /* ================ RNG ================ */
emilmont 80:8e73be2a2ac1 763 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 764
emilmont 80:8e73be2a2ac1 765
emilmont 80:8e73be2a2ac1 766 /**
emilmont 80:8e73be2a2ac1 767 * @brief Random Number Generator. (RNG)
emilmont 80:8e73be2a2ac1 768 */
emilmont 80:8e73be2a2ac1 769
emilmont 80:8e73be2a2ac1 770 typedef struct { /*!< RNG Structure */
emilmont 80:8e73be2a2ac1 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
emilmont 80:8e73be2a2ac1 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
emilmont 80:8e73be2a2ac1 773 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
emilmont 80:8e73be2a2ac1 775 __I uint32_t RESERVED1[63];
Kojto 97:433970e64889 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
emilmont 80:8e73be2a2ac1 777 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
emilmont 80:8e73be2a2ac1 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
emilmont 80:8e73be2a2ac1 780 __I uint32_t RESERVED3[126];
emilmont 80:8e73be2a2ac1 781 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 782 __I uint32_t VALUE; /*!< RNG random number. */
emilmont 80:8e73be2a2ac1 783 __I uint32_t RESERVED4[700];
emilmont 80:8e73be2a2ac1 784 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 785 } NRF_RNG_Type;
emilmont 80:8e73be2a2ac1 786
emilmont 80:8e73be2a2ac1 787
emilmont 80:8e73be2a2ac1 788 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 789 /* ================ ECB ================ */
emilmont 80:8e73be2a2ac1 790 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 791
emilmont 80:8e73be2a2ac1 792
emilmont 80:8e73be2a2ac1 793 /**
emilmont 80:8e73be2a2ac1 794 * @brief AES ECB Mode Encryption. (ECB)
emilmont 80:8e73be2a2ac1 795 */
emilmont 80:8e73be2a2ac1 796
emilmont 80:8e73be2a2ac1 797 typedef struct { /*!< ECB Structure */
emilmont 80:8e73be2a2ac1 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
emilmont 80:8e73be2a2ac1 799 will not initiate a new encryption and the ERRORECB event will
emilmont 80:8e73be2a2ac1 800 be triggered. */
emilmont 80:8e73be2a2ac1 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
emilmont 80:8e73be2a2ac1 802 this will will trigger the ERRORECB event. */
emilmont 80:8e73be2a2ac1 803 __I uint32_t RESERVED0[62];
emilmont 80:8e73be2a2ac1 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
emilmont 80:8e73be2a2ac1 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
emilmont 80:8e73be2a2ac1 806 error. */
emilmont 80:8e73be2a2ac1 807 __I uint32_t RESERVED1[127];
emilmont 80:8e73be2a2ac1 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 810 __I uint32_t RESERVED2[126];
emilmont 80:8e73be2a2ac1 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
emilmont 80:8e73be2a2ac1 812 __I uint32_t RESERVED3[701];
emilmont 80:8e73be2a2ac1 813 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 814 } NRF_ECB_Type;
emilmont 80:8e73be2a2ac1 815
emilmont 80:8e73be2a2ac1 816
emilmont 80:8e73be2a2ac1 817 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 818 /* ================ AAR ================ */
emilmont 80:8e73be2a2ac1 819 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 820
emilmont 80:8e73be2a2ac1 821
emilmont 80:8e73be2a2ac1 822 /**
emilmont 80:8e73be2a2ac1 823 * @brief Accelerated Address Resolver. (AAR)
emilmont 80:8e73be2a2ac1 824 */
emilmont 80:8e73be2a2ac1 825
emilmont 80:8e73be2a2ac1 826 typedef struct { /*!< AAR Structure */
emilmont 80:8e73be2a2ac1 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
emilmont 80:8e73be2a2ac1 828 data structure. */
emilmont 80:8e73be2a2ac1 829 __I uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
emilmont 80:8e73be2a2ac1 831 __I uint32_t RESERVED1[61];
emilmont 80:8e73be2a2ac1 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
emilmont 80:8e73be2a2ac1 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
emilmont 80:8e73be2a2ac1 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
emilmont 80:8e73be2a2ac1 835 __I uint32_t RESERVED2[126];
emilmont 80:8e73be2a2ac1 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 838 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 839 __I uint32_t STATUS; /*!< Resolution status. */
emilmont 80:8e73be2a2ac1 840 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
emilmont 80:8e73be2a2ac1 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
emilmont 80:8e73be2a2ac1 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
emilmont 80:8e73be2a2ac1 844 __I uint32_t RESERVED5;
emilmont 80:8e73be2a2ac1 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
Kojto 97:433970e64889 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 847 during resolution. A minimum of 3 bytes must be reserved. */
emilmont 80:8e73be2a2ac1 848 __I uint32_t RESERVED6[697];
emilmont 80:8e73be2a2ac1 849 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 850 } NRF_AAR_Type;
emilmont 80:8e73be2a2ac1 851
emilmont 80:8e73be2a2ac1 852
emilmont 80:8e73be2a2ac1 853 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 854 /* ================ CCM ================ */
emilmont 80:8e73be2a2ac1 855 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 856
emilmont 80:8e73be2a2ac1 857
emilmont 80:8e73be2a2ac1 858 /**
emilmont 80:8e73be2a2ac1 859 * @brief AES CCM Mode Encryption. (CCM)
emilmont 80:8e73be2a2ac1 860 */
emilmont 80:8e73be2a2ac1 861
emilmont 80:8e73be2a2ac1 862 typedef struct { /*!< CCM Structure */
emilmont 80:8e73be2a2ac1 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
emilmont 80:8e73be2a2ac1 864 itself when completed. */
emilmont 80:8e73be2a2ac1 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
emilmont 80:8e73be2a2ac1 866 completed. */
emilmont 80:8e73be2a2ac1 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
emilmont 80:8e73be2a2ac1 868 __I uint32_t RESERVED0[61];
emilmont 80:8e73be2a2ac1 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
emilmont 80:8e73be2a2ac1 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
emilmont 80:8e73be2a2ac1 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
emilmont 80:8e73be2a2ac1 872 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
emilmont 80:8e73be2a2ac1 874 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 877 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
emilmont 80:8e73be2a2ac1 879 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 880 __IO uint32_t ENABLE; /*!< CCM enable. */
emilmont 80:8e73be2a2ac1 881 __IO uint32_t MODE; /*!< Operation mode. */
Kojto 97:433970e64889 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
Kojto 97:433970e64889 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
Kojto 97:433970e64889 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
Kojto 97:433970e64889 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
Kojto 97:433970e64889 886 during resolution. A minimum of 43 bytes must be reserved. */
emilmont 80:8e73be2a2ac1 887 __I uint32_t RESERVED5[697];
emilmont 80:8e73be2a2ac1 888 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 889 } NRF_CCM_Type;
emilmont 80:8e73be2a2ac1 890
emilmont 80:8e73be2a2ac1 891
emilmont 80:8e73be2a2ac1 892 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 893 /* ================ WDT ================ */
emilmont 80:8e73be2a2ac1 894 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 895
emilmont 80:8e73be2a2ac1 896
emilmont 80:8e73be2a2ac1 897 /**
emilmont 80:8e73be2a2ac1 898 * @brief Watchdog Timer. (WDT)
emilmont 80:8e73be2a2ac1 899 */
emilmont 80:8e73be2a2ac1 900
emilmont 80:8e73be2a2ac1 901 typedef struct { /*!< WDT Structure */
emilmont 80:8e73be2a2ac1 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
emilmont 80:8e73be2a2ac1 903 __I uint32_t RESERVED0[63];
emilmont 80:8e73be2a2ac1 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
emilmont 80:8e73be2a2ac1 905 __I uint32_t RESERVED1[128];
emilmont 80:8e73be2a2ac1 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 908 __I uint32_t RESERVED2[61];
emilmont 80:8e73be2a2ac1 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
emilmont 80:8e73be2a2ac1 910 __I uint32_t REQSTATUS; /*!< Request status. */
emilmont 80:8e73be2a2ac1 911 __I uint32_t RESERVED3[63];
emilmont 80:8e73be2a2ac1 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
emilmont 80:8e73be2a2ac1 913 __IO uint32_t RREN; /*!< Reload request enable. */
emilmont 80:8e73be2a2ac1 914 __IO uint32_t CONFIG; /*!< Configuration register. */
emilmont 80:8e73be2a2ac1 915 __I uint32_t RESERVED4[60];
emilmont 80:8e73be2a2ac1 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
emilmont 80:8e73be2a2ac1 917 __I uint32_t RESERVED5[631];
emilmont 80:8e73be2a2ac1 918 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 919 } NRF_WDT_Type;
emilmont 80:8e73be2a2ac1 920
emilmont 80:8e73be2a2ac1 921
emilmont 80:8e73be2a2ac1 922 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 923 /* ================ QDEC ================ */
emilmont 80:8e73be2a2ac1 924 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 925
emilmont 80:8e73be2a2ac1 926
emilmont 80:8e73be2a2ac1 927 /**
emilmont 80:8e73be2a2ac1 928 * @brief Rotary decoder. (QDEC)
emilmont 80:8e73be2a2ac1 929 */
emilmont 80:8e73be2a2ac1 930
emilmont 80:8e73be2a2ac1 931 typedef struct { /*!< QDEC Structure */
emilmont 80:8e73be2a2ac1 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
emilmont 80:8e73be2a2ac1 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
emilmont 80:8e73be2a2ac1 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
emilmont 80:8e73be2a2ac1 935 and clears the ACC registers. */
emilmont 80:8e73be2a2ac1 936 __I uint32_t RESERVED0[61];
emilmont 80:8e73be2a2ac1 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
emilmont 80:8e73be2a2ac1 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
emilmont 80:8e73be2a2ac1 939 ACC register different than zero. */
emilmont 80:8e73be2a2ac1 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
emilmont 80:8e73be2a2ac1 941 __I uint32_t RESERVED1[61];
Kojto 97:433970e64889 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
emilmont 80:8e73be2a2ac1 943 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 946 __I uint32_t RESERVED3[125];
emilmont 80:8e73be2a2ac1 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
emilmont 80:8e73be2a2ac1 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
emilmont 80:8e73be2a2ac1 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
emilmont 80:8e73be2a2ac1 950 __I int32_t SAMPLE; /*!< Motion sample value. */
emilmont 80:8e73be2a2ac1 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
emilmont 80:8e73be2a2ac1 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
emilmont 80:8e73be2a2ac1 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
emilmont 80:8e73be2a2ac1 954 task. */
emilmont 80:8e73be2a2ac1 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
emilmont 80:8e73be2a2ac1 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
emilmont 80:8e73be2a2ac1 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
emilmont 80:8e73be2a2ac1 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
emilmont 80:8e73be2a2ac1 959 __I uint32_t RESERVED4[5];
emilmont 80:8e73be2a2ac1 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
emilmont 80:8e73be2a2ac1 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
emilmont 80:8e73be2a2ac1 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
emilmont 80:8e73be2a2ac1 963 task. */
emilmont 80:8e73be2a2ac1 964 __I uint32_t RESERVED5[684];
emilmont 80:8e73be2a2ac1 965 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 966 } NRF_QDEC_Type;
emilmont 80:8e73be2a2ac1 967
emilmont 80:8e73be2a2ac1 968
emilmont 80:8e73be2a2ac1 969 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 970 /* ================ LPCOMP ================ */
emilmont 80:8e73be2a2ac1 971 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 972
emilmont 80:8e73be2a2ac1 973
emilmont 80:8e73be2a2ac1 974 /**
Kojto 97:433970e64889 975 * @brief Low power comparator. (LPCOMP)
emilmont 80:8e73be2a2ac1 976 */
emilmont 80:8e73be2a2ac1 977
emilmont 80:8e73be2a2ac1 978 typedef struct { /*!< LPCOMP Structure */
emilmont 80:8e73be2a2ac1 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
emilmont 80:8e73be2a2ac1 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
emilmont 80:8e73be2a2ac1 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
emilmont 80:8e73be2a2ac1 982 __I uint32_t RESERVED0[61];
emilmont 80:8e73be2a2ac1 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
emilmont 80:8e73be2a2ac1 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
emilmont 80:8e73be2a2ac1 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
emilmont 80:8e73be2a2ac1 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
emilmont 80:8e73be2a2ac1 987 __I uint32_t RESERVED1[60];
Kojto 97:433970e64889 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
emilmont 80:8e73be2a2ac1 989 __I uint32_t RESERVED2[64];
emilmont 80:8e73be2a2ac1 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
emilmont 80:8e73be2a2ac1 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
emilmont 80:8e73be2a2ac1 992 __I uint32_t RESERVED3[61];
emilmont 80:8e73be2a2ac1 993 __I uint32_t RESULT; /*!< Result of last compare. */
emilmont 80:8e73be2a2ac1 994 __I uint32_t RESERVED4[63];
emilmont 80:8e73be2a2ac1 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
emilmont 80:8e73be2a2ac1 996 __IO uint32_t PSEL; /*!< Input pin select. */
emilmont 80:8e73be2a2ac1 997 __IO uint32_t REFSEL; /*!< Reference select. */
emilmont 80:8e73be2a2ac1 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
emilmont 80:8e73be2a2ac1 999 __I uint32_t RESERVED5[4];
emilmont 80:8e73be2a2ac1 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
emilmont 80:8e73be2a2ac1 1001 __I uint32_t RESERVED6[694];
emilmont 80:8e73be2a2ac1 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
emilmont 80:8e73be2a2ac1 1003 } NRF_LPCOMP_Type;
emilmont 80:8e73be2a2ac1 1004
emilmont 80:8e73be2a2ac1 1005
emilmont 80:8e73be2a2ac1 1006 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1007 /* ================ SWI ================ */
emilmont 80:8e73be2a2ac1 1008 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1009
emilmont 80:8e73be2a2ac1 1010
emilmont 80:8e73be2a2ac1 1011 /**
emilmont 80:8e73be2a2ac1 1012 * @brief SW Interrupts. (SWI)
emilmont 80:8e73be2a2ac1 1013 */
emilmont 80:8e73be2a2ac1 1014
emilmont 80:8e73be2a2ac1 1015 typedef struct { /*!< SWI Structure */
emilmont 80:8e73be2a2ac1 1016 __I uint32_t UNUSED; /*!< Unused. */
emilmont 80:8e73be2a2ac1 1017 } NRF_SWI_Type;
emilmont 80:8e73be2a2ac1 1018
emilmont 80:8e73be2a2ac1 1019
emilmont 80:8e73be2a2ac1 1020 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1021 /* ================ NVMC ================ */
emilmont 80:8e73be2a2ac1 1022 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1023
emilmont 80:8e73be2a2ac1 1024
emilmont 80:8e73be2a2ac1 1025 /**
emilmont 80:8e73be2a2ac1 1026 * @brief Non Volatile Memory Controller. (NVMC)
emilmont 80:8e73be2a2ac1 1027 */
emilmont 80:8e73be2a2ac1 1028
emilmont 80:8e73be2a2ac1 1029 typedef struct { /*!< NVMC Structure */
emilmont 80:8e73be2a2ac1 1030 __I uint32_t RESERVED0[256];
emilmont 80:8e73be2a2ac1 1031 __I uint32_t READY; /*!< Ready flag. */
emilmont 80:8e73be2a2ac1 1032 __I uint32_t RESERVED1[64];
emilmont 80:8e73be2a2ac1 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
Kojto 122:f9eeca106725 1034
Kojto 122:f9eeca106725 1035 union {
Kojto 122:f9eeca106725 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
Kojto 122:f9eeca106725 1038 };
emilmont 80:8e73be2a2ac1 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
Kojto 122:f9eeca106725 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
emilmont 80:8e73be2a2ac1 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
emilmont 80:8e73be2a2ac1 1042 } NRF_NVMC_Type;
emilmont 80:8e73be2a2ac1 1043
emilmont 80:8e73be2a2ac1 1044
emilmont 80:8e73be2a2ac1 1045 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1046 /* ================ PPI ================ */
emilmont 80:8e73be2a2ac1 1047 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1048
emilmont 80:8e73be2a2ac1 1049
emilmont 80:8e73be2a2ac1 1050 /**
emilmont 80:8e73be2a2ac1 1051 * @brief PPI controller. (PPI)
emilmont 80:8e73be2a2ac1 1052 */
emilmont 80:8e73be2a2ac1 1053
emilmont 80:8e73be2a2ac1 1054 typedef struct { /*!< PPI Structure */
emilmont 80:8e73be2a2ac1 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
emilmont 80:8e73be2a2ac1 1056 __I uint32_t RESERVED0[312];
emilmont 80:8e73be2a2ac1 1057 __IO uint32_t CHEN; /*!< Channel enable. */
emilmont 80:8e73be2a2ac1 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
emilmont 80:8e73be2a2ac1 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
emilmont 80:8e73be2a2ac1 1060 __I uint32_t RESERVED1;
emilmont 80:8e73be2a2ac1 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
emilmont 80:8e73be2a2ac1 1062 __I uint32_t RESERVED2[156];
emilmont 80:8e73be2a2ac1 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
emilmont 80:8e73be2a2ac1 1064 } NRF_PPI_Type;
emilmont 80:8e73be2a2ac1 1065
emilmont 80:8e73be2a2ac1 1066
emilmont 80:8e73be2a2ac1 1067 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1068 /* ================ FICR ================ */
emilmont 80:8e73be2a2ac1 1069 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1070
emilmont 80:8e73be2a2ac1 1071
emilmont 80:8e73be2a2ac1 1072 /**
emilmont 80:8e73be2a2ac1 1073 * @brief Factory Information Configuration. (FICR)
emilmont 80:8e73be2a2ac1 1074 */
emilmont 80:8e73be2a2ac1 1075
emilmont 80:8e73be2a2ac1 1076 typedef struct { /*!< FICR Structure */
emilmont 80:8e73be2a2ac1 1077 __I uint32_t RESERVED0[4];
emilmont 80:8e73be2a2ac1 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
emilmont 80:8e73be2a2ac1 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
emilmont 80:8e73be2a2ac1 1080 __I uint32_t RESERVED1[4];
emilmont 80:8e73be2a2ac1 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
emilmont 80:8e73be2a2ac1 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
emilmont 80:8e73be2a2ac1 1083 __I uint32_t RESERVED2;
emilmont 80:8e73be2a2ac1 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
Kojto 97:433970e64889 1085
Kojto 97:433970e64889 1086 union {
Kojto 97:433970e64889 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
Kojto 97:433970e64889 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
Kojto 97:433970e64889 1089 instead. */
Kojto 97:433970e64889 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
Kojto 97:433970e64889 1091 };
emilmont 80:8e73be2a2ac1 1092 __I uint32_t RESERVED3[5];
emilmont 80:8e73be2a2ac1 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
emilmont 80:8e73be2a2ac1 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
emilmont 80:8e73be2a2ac1 1095 __I uint32_t RESERVED4[6];
emilmont 80:8e73be2a2ac1 1096 __I uint32_t ER[4]; /*!< Encryption root. */
emilmont 80:8e73be2a2ac1 1097 __I uint32_t IR[4]; /*!< Identity root. */
emilmont 80:8e73be2a2ac1 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
emilmont 80:8e73be2a2ac1 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
emilmont 80:8e73be2a2ac1 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
Kojto 97:433970e64889 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
Kojto 97:433970e64889 1102 mode. */
Kojto 97:433970e64889 1103 __I uint32_t RESERVED5[10];
emilmont 80:8e73be2a2ac1 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
emilmont 80:8e73be2a2ac1 1105 mode. */
emilmont 80:8e73be2a2ac1 1106 } NRF_FICR_Type;
emilmont 80:8e73be2a2ac1 1107
emilmont 80:8e73be2a2ac1 1108
emilmont 80:8e73be2a2ac1 1109 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1110 /* ================ UICR ================ */
emilmont 80:8e73be2a2ac1 1111 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1112
emilmont 80:8e73be2a2ac1 1113
emilmont 80:8e73be2a2ac1 1114 /**
emilmont 80:8e73be2a2ac1 1115 * @brief User Information Configuration. (UICR)
emilmont 80:8e73be2a2ac1 1116 */
emilmont 80:8e73be2a2ac1 1117
emilmont 80:8e73be2a2ac1 1118 typedef struct { /*!< UICR Structure */
emilmont 80:8e73be2a2ac1 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
emilmont 80:8e73be2a2ac1 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
emilmont 80:8e73be2a2ac1 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
emilmont 80:8e73be2a2ac1 1122 __I uint32_t RESERVED0;
emilmont 80:8e73be2a2ac1 1123 __I uint32_t FWID; /*!< Firmware ID. */
Kojto 122:f9eeca106725 1124
Kojto 122:f9eeca106725 1125 union {
Kojto 122:f9eeca106725 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
Kojto 122:f9eeca106725 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
Kojto 122:f9eeca106725 1128 };
Kojto 122:f9eeca106725 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
Kojto 122:f9eeca106725 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
emilmont 80:8e73be2a2ac1 1131 } NRF_UICR_Type;
emilmont 80:8e73be2a2ac1 1132
emilmont 80:8e73be2a2ac1 1133
emilmont 80:8e73be2a2ac1 1134 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1135 /* ================ GPIO ================ */
emilmont 80:8e73be2a2ac1 1136 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1137
emilmont 80:8e73be2a2ac1 1138
emilmont 80:8e73be2a2ac1 1139 /**
emilmont 80:8e73be2a2ac1 1140 * @brief General purpose input and output. (GPIO)
emilmont 80:8e73be2a2ac1 1141 */
emilmont 80:8e73be2a2ac1 1142
emilmont 80:8e73be2a2ac1 1143 typedef struct { /*!< GPIO Structure */
emilmont 80:8e73be2a2ac1 1144 __I uint32_t RESERVED0[321];
emilmont 80:8e73be2a2ac1 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
emilmont 80:8e73be2a2ac1 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
emilmont 80:8e73be2a2ac1 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
emilmont 80:8e73be2a2ac1 1148 __I uint32_t IN; /*!< Read GPIO port. */
emilmont 80:8e73be2a2ac1 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
emilmont 80:8e73be2a2ac1 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
emilmont 80:8e73be2a2ac1 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
emilmont 80:8e73be2a2ac1 1152 __I uint32_t RESERVED1[120];
emilmont 80:8e73be2a2ac1 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
emilmont 80:8e73be2a2ac1 1154 } NRF_GPIO_Type;
emilmont 80:8e73be2a2ac1 1155
emilmont 80:8e73be2a2ac1 1156
emilmont 80:8e73be2a2ac1 1157 /* -------------------- End of section using anonymous unions ------------------- */
emilmont 80:8e73be2a2ac1 1158 #if defined(__CC_ARM)
emilmont 80:8e73be2a2ac1 1159 #pragma pop
emilmont 80:8e73be2a2ac1 1160 #elif defined(__ICCARM__)
emilmont 80:8e73be2a2ac1 1161 /* leave anonymous unions enabled */
emilmont 80:8e73be2a2ac1 1162 #elif defined(__GNUC__)
emilmont 80:8e73be2a2ac1 1163 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 1164 #elif defined(__TMS470__)
emilmont 80:8e73be2a2ac1 1165 /* anonymous unions are enabled by default */
emilmont 80:8e73be2a2ac1 1166 #elif defined(__TASKING__)
emilmont 80:8e73be2a2ac1 1167 #pragma warning restore
emilmont 80:8e73be2a2ac1 1168 #else
emilmont 80:8e73be2a2ac1 1169 #warning Not supported compiler type
emilmont 80:8e73be2a2ac1 1170 #endif
emilmont 80:8e73be2a2ac1 1171
emilmont 80:8e73be2a2ac1 1172
emilmont 80:8e73be2a2ac1 1173
emilmont 80:8e73be2a2ac1 1174
emilmont 80:8e73be2a2ac1 1175 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1176 /* ================ Peripheral memory map ================ */
emilmont 80:8e73be2a2ac1 1177 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1178
emilmont 80:8e73be2a2ac1 1179 #define NRF_POWER_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1180 #define NRF_CLOCK_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1181 #define NRF_MPU_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1182 #define NRF_AMLI_BASE 0x40000000UL
emilmont 80:8e73be2a2ac1 1183 #define NRF_RADIO_BASE 0x40001000UL
emilmont 80:8e73be2a2ac1 1184 #define NRF_UART0_BASE 0x40002000UL
emilmont 80:8e73be2a2ac1 1185 #define NRF_SPI0_BASE 0x40003000UL
emilmont 80:8e73be2a2ac1 1186 #define NRF_TWI0_BASE 0x40003000UL
emilmont 80:8e73be2a2ac1 1187 #define NRF_SPI1_BASE 0x40004000UL
emilmont 80:8e73be2a2ac1 1188 #define NRF_TWI1_BASE 0x40004000UL
emilmont 80:8e73be2a2ac1 1189 #define NRF_SPIS1_BASE 0x40004000UL
Kojto 97:433970e64889 1190 #define NRF_SPIM1_BASE 0x40004000UL
emilmont 80:8e73be2a2ac1 1191 #define NRF_GPIOTE_BASE 0x40006000UL
emilmont 80:8e73be2a2ac1 1192 #define NRF_ADC_BASE 0x40007000UL
emilmont 80:8e73be2a2ac1 1193 #define NRF_TIMER0_BASE 0x40008000UL
emilmont 80:8e73be2a2ac1 1194 #define NRF_TIMER1_BASE 0x40009000UL
emilmont 80:8e73be2a2ac1 1195 #define NRF_TIMER2_BASE 0x4000A000UL
emilmont 80:8e73be2a2ac1 1196 #define NRF_RTC0_BASE 0x4000B000UL
emilmont 80:8e73be2a2ac1 1197 #define NRF_TEMP_BASE 0x4000C000UL
emilmont 80:8e73be2a2ac1 1198 #define NRF_RNG_BASE 0x4000D000UL
emilmont 80:8e73be2a2ac1 1199 #define NRF_ECB_BASE 0x4000E000UL
emilmont 80:8e73be2a2ac1 1200 #define NRF_AAR_BASE 0x4000F000UL
emilmont 80:8e73be2a2ac1 1201 #define NRF_CCM_BASE 0x4000F000UL
emilmont 80:8e73be2a2ac1 1202 #define NRF_WDT_BASE 0x40010000UL
emilmont 80:8e73be2a2ac1 1203 #define NRF_RTC1_BASE 0x40011000UL
emilmont 80:8e73be2a2ac1 1204 #define NRF_QDEC_BASE 0x40012000UL
emilmont 80:8e73be2a2ac1 1205 #define NRF_LPCOMP_BASE 0x40013000UL
emilmont 80:8e73be2a2ac1 1206 #define NRF_SWI_BASE 0x40014000UL
emilmont 80:8e73be2a2ac1 1207 #define NRF_NVMC_BASE 0x4001E000UL
emilmont 80:8e73be2a2ac1 1208 #define NRF_PPI_BASE 0x4001F000UL
emilmont 80:8e73be2a2ac1 1209 #define NRF_FICR_BASE 0x10000000UL
emilmont 80:8e73be2a2ac1 1210 #define NRF_UICR_BASE 0x10001000UL
emilmont 80:8e73be2a2ac1 1211 #define NRF_GPIO_BASE 0x50000000UL
emilmont 80:8e73be2a2ac1 1212
emilmont 80:8e73be2a2ac1 1213
emilmont 80:8e73be2a2ac1 1214 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1215 /* ================ Peripheral declaration ================ */
emilmont 80:8e73be2a2ac1 1216 /* ================================================================================ */
emilmont 80:8e73be2a2ac1 1217
emilmont 80:8e73be2a2ac1 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
emilmont 80:8e73be2a2ac1 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
emilmont 80:8e73be2a2ac1 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
emilmont 80:8e73be2a2ac1 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
emilmont 80:8e73be2a2ac1 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
emilmont 80:8e73be2a2ac1 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
emilmont 80:8e73be2a2ac1 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
emilmont 80:8e73be2a2ac1 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
emilmont 80:8e73be2a2ac1 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
emilmont 80:8e73be2a2ac1 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
emilmont 80:8e73be2a2ac1 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
Kojto 97:433970e64889 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
emilmont 80:8e73be2a2ac1 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
emilmont 80:8e73be2a2ac1 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
emilmont 80:8e73be2a2ac1 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
emilmont 80:8e73be2a2ac1 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
emilmont 80:8e73be2a2ac1 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
emilmont 80:8e73be2a2ac1 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
emilmont 80:8e73be2a2ac1 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
emilmont 80:8e73be2a2ac1 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
emilmont 80:8e73be2a2ac1 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
emilmont 80:8e73be2a2ac1 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
emilmont 80:8e73be2a2ac1 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
emilmont 80:8e73be2a2ac1 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
emilmont 80:8e73be2a2ac1 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
emilmont 80:8e73be2a2ac1 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
emilmont 80:8e73be2a2ac1 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
emilmont 80:8e73be2a2ac1 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
emilmont 80:8e73be2a2ac1 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
emilmont 80:8e73be2a2ac1 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
emilmont 80:8e73be2a2ac1 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
emilmont 80:8e73be2a2ac1 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
emilmont 80:8e73be2a2ac1 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
emilmont 80:8e73be2a2ac1 1251
emilmont 80:8e73be2a2ac1 1252
emilmont 80:8e73be2a2ac1 1253 /** @} */ /* End of group Device_Peripheral_Registers */
Kojto 122:f9eeca106725 1254 /** @} */ /* End of group nrf51 */
emilmont 80:8e73be2a2ac1 1255 /** @} */ /* End of group Nordic Semiconductor */
emilmont 80:8e73be2a2ac1 1256
emilmont 80:8e73be2a2ac1 1257 #ifdef __cplusplus
emilmont 80:8e73be2a2ac1 1258 }
emilmont 80:8e73be2a2ac1 1259 #endif
emilmont 80:8e73be2a2ac1 1260
emilmont 80:8e73be2a2ac1 1261
Kojto 122:f9eeca106725 1262 #endif /* nrf51_H */