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TARGET_DISCO_F746NG/stm32f746xx.h@122:f9eeca106725, 2016-07-07 (annotated)

Committer:: Kojto
Date:: Thu Jul 07 14:34:11 2016 +0100
Revision:: 122:f9eeca106725
Parent:: 116:c0f6e94411f5

Release 122 of the mbed library



Changes:

- new targets - Nucleo L432KC, Beetle, Nucleo F446ZE, Nucleo L011K4

- Thread safety addition - mbed API should contain a statement about thread safety

- critical section API addition

- CAS API (core_util_atomic_incr/decr)

- DEVICE_ are generated from targets.json file, device.h deprecated

- Callback replaces FunctionPointer to provide std like interface

- mbed HAL API docs improvements

- toolchain - prexif attributes with MBED_

            - add new attributes - packed, weak, forcedinline, align

- target.json - contains targets definitions

- ST - L1XX - Cube update to 1.5

     - SPI clock selection fix (clock from APB domain)

     - F7 - Cube update v1.4.0

     - L0 -  baudrate init fix

     - L1 - Cube update v1.5

     - F3 - baudrate init fix, 3 targets CAN support

     - F4 - Cube update v1.12.0, 3 targets CAN support

     - L4XX - Cube update v1.5.1

     - F0 - update Cube to v1.5.0

     - L4 - 2 targets (L476RG/VG) CAN support

- NXP - pwm clock fix for KSDK2 MCU

      - LPC2368 - remove ARM toolchain support - due to regression

      - KSDK2 - fix SPI , I2C address and repeat start

- Silabs - some fixes backported from mbed 3

- Renesas - RZ_A1H - SystemCoreClockUpdate addition

Who changed what in which revision?

User	Revision	Line number	New contents of line
Kojto	107:4f6c30876dfa	1	/**
Kojto	107:4f6c30876dfa	2	******************************************************************************
Kojto	107:4f6c30876dfa	3	* @file stm32f746xx.h
Kojto	107:4f6c30876dfa	4	* @author MCD Application Team
Kojto	122:f9eeca106725	5	* @version V1.1.0
Kojto	122:f9eeca106725	6	* @date 22-April-2016
Kojto	122:f9eeca106725	7	* @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File.
Kojto	107:4f6c30876dfa	8	*
Kojto	107:4f6c30876dfa	9	* This file contains:
Kojto	107:4f6c30876dfa	10	* - Data structures and the address mapping for all peripherals
Kojto	107:4f6c30876dfa	11	* - Peripheral's registers declarations and bits definition
Kojto	107:4f6c30876dfa	12	* - Macros to access peripherals registers hardware
Kojto	107:4f6c30876dfa	13	*
Kojto	107:4f6c30876dfa	14	******************************************************************************
Kojto	107:4f6c30876dfa	15	* @attention
Kojto	107:4f6c30876dfa	16	*
Kojto	116:c0f6e94411f5	17	* <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto	107:4f6c30876dfa	18	*
Kojto	107:4f6c30876dfa	19	* Redistribution and use in source and binary forms, with or without modification,
Kojto	107:4f6c30876dfa	20	* are permitted provided that the following conditions are met:
Kojto	107:4f6c30876dfa	21	* 1. Redistributions of source code must retain the above copyright notice,
Kojto	107:4f6c30876dfa	22	* this list of conditions and the following disclaimer.
Kojto	107:4f6c30876dfa	23	* 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto	107:4f6c30876dfa	24	* this list of conditions and the following disclaimer in the documentation
Kojto	107:4f6c30876dfa	25	* and/or other materials provided with the distribution.
Kojto	107:4f6c30876dfa	26	* 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto	107:4f6c30876dfa	27	* may be used to endorse or promote products derived from this software
Kojto	107:4f6c30876dfa	28	* without specific prior written permission.
Kojto	107:4f6c30876dfa	29	*
Kojto	107:4f6c30876dfa	30	* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto	107:4f6c30876dfa	31	* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto	107:4f6c30876dfa	32	* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto	107:4f6c30876dfa	33	* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto	107:4f6c30876dfa	34	* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto	107:4f6c30876dfa	35	* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto	107:4f6c30876dfa	36	* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto	107:4f6c30876dfa	37	* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto	107:4f6c30876dfa	38	* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto	107:4f6c30876dfa	39	* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto	107:4f6c30876dfa	40	*
Kojto	107:4f6c30876dfa	41	******************************************************************************
Kojto	107:4f6c30876dfa	42	*/
Kojto	107:4f6c30876dfa	43
Kojto	107:4f6c30876dfa	44	/** @addtogroup CMSIS_Device
Kojto	107:4f6c30876dfa	45	* @{
Kojto	107:4f6c30876dfa	46	*/
Kojto	107:4f6c30876dfa	47
Kojto	107:4f6c30876dfa	48	/** @addtogroup stm32f746xx
Kojto	107:4f6c30876dfa	49	* @{
Kojto	107:4f6c30876dfa	50	*/
Kojto	107:4f6c30876dfa	51
Kojto	107:4f6c30876dfa	52	#ifndef __STM32F746xx_H
Kojto	107:4f6c30876dfa	53	#define __STM32F746xx_H
Kojto	107:4f6c30876dfa	54
Kojto	107:4f6c30876dfa	55	#ifdef __cplusplus
Kojto	107:4f6c30876dfa	56	extern "C" {
Kojto	107:4f6c30876dfa	57	#endif /* __cplusplus */
Kojto	107:4f6c30876dfa	58
Kojto	107:4f6c30876dfa	59	/** @addtogroup Configuration_section_for_CMSIS
Kojto	107:4f6c30876dfa	60	* @{
Kojto	107:4f6c30876dfa	61	*/
Kojto	107:4f6c30876dfa	62
Kojto	107:4f6c30876dfa	63	/**
Kojto	107:4f6c30876dfa	64	* @brief STM32F7xx Interrupt Number Definition, according to the selected device
Kojto	107:4f6c30876dfa	65	* in @ref Library_configuration_section
Kojto	107:4f6c30876dfa	66	*/
Kojto	116:c0f6e94411f5	67	typedef enum
Kojto	107:4f6c30876dfa	68	{
Kojto	107:4f6c30876dfa	69	/**** Cortex-M7 Processor Exceptions Numbers **************************************************************/
Kojto	107:4f6c30876dfa	70	NonMaskableInt_IRQn = -14, /!< 2 Non Maskable Interrupt /
Kojto	107:4f6c30876dfa	71	MemoryManagement_IRQn = -12, /!< 4 Cortex-M7 Memory Management Interrupt /
Kojto	107:4f6c30876dfa	72	BusFault_IRQn = -11, /!< 5 Cortex-M7 Bus Fault Interrupt /
Kojto	107:4f6c30876dfa	73	UsageFault_IRQn = -10, /!< 6 Cortex-M7 Usage Fault Interrupt /
Kojto	107:4f6c30876dfa	74	SVCall_IRQn = -5, /!< 11 Cortex-M7 SV Call Interrupt /
Kojto	107:4f6c30876dfa	75	DebugMonitor_IRQn = -4, /!< 12 Cortex-M7 Debug Monitor Interrupt /
Kojto	107:4f6c30876dfa	76	PendSV_IRQn = -2, /!< 14 Cortex-M7 Pend SV Interrupt /
Kojto	107:4f6c30876dfa	77	SysTick_IRQn = -1, /!< 15 Cortex-M7 System Tick Interrupt /
Kojto	107:4f6c30876dfa	78	/**** STM32 specific Interrupt Numbers ********************************************************************/
Kojto	107:4f6c30876dfa	79	WWDG_IRQn = 0, /!< Window WatchDog Interrupt /
Kojto	107:4f6c30876dfa	80	PVD_IRQn = 1, /!< PVD through EXTI Line detection Interrupt /
Kojto	107:4f6c30876dfa	81	TAMP_STAMP_IRQn = 2, /!< Tamper and TimeStamp interrupts through the EXTI line /
Kojto	107:4f6c30876dfa	82	RTC_WKUP_IRQn = 3, /!< RTC Wakeup interrupt through the EXTI line /
Kojto	107:4f6c30876dfa	83	FLASH_IRQn = 4, /!< FLASH global Interrupt /
Kojto	107:4f6c30876dfa	84	RCC_IRQn = 5, /!< RCC global Interrupt /
Kojto	107:4f6c30876dfa	85	EXTI0_IRQn = 6, /!< EXTI Line0 Interrupt /
Kojto	107:4f6c30876dfa	86	EXTI1_IRQn = 7, /!< EXTI Line1 Interrupt /
Kojto	107:4f6c30876dfa	87	EXTI2_IRQn = 8, /!< EXTI Line2 Interrupt /
Kojto	107:4f6c30876dfa	88	EXTI3_IRQn = 9, /!< EXTI Line3 Interrupt /
Kojto	107:4f6c30876dfa	89	EXTI4_IRQn = 10, /!< EXTI Line4 Interrupt /
Kojto	107:4f6c30876dfa	90	DMA1_Stream0_IRQn = 11, /!< DMA1 Stream 0 global Interrupt /
Kojto	107:4f6c30876dfa	91	DMA1_Stream1_IRQn = 12, /!< DMA1 Stream 1 global Interrupt /
Kojto	107:4f6c30876dfa	92	DMA1_Stream2_IRQn = 13, /!< DMA1 Stream 2 global Interrupt /
Kojto	107:4f6c30876dfa	93	DMA1_Stream3_IRQn = 14, /!< DMA1 Stream 3 global Interrupt /
Kojto	107:4f6c30876dfa	94	DMA1_Stream4_IRQn = 15, /!< DMA1 Stream 4 global Interrupt /
Kojto	107:4f6c30876dfa	95	DMA1_Stream5_IRQn = 16, /!< DMA1 Stream 5 global Interrupt /
Kojto	107:4f6c30876dfa	96	DMA1_Stream6_IRQn = 17, /!< DMA1 Stream 6 global Interrupt /
Kojto	107:4f6c30876dfa	97	ADC_IRQn = 18, /!< ADC1, ADC2 and ADC3 global Interrupts /
Kojto	107:4f6c30876dfa	98	CAN1_TX_IRQn = 19, /!< CAN1 TX Interrupt /
Kojto	107:4f6c30876dfa	99	CAN1_RX0_IRQn = 20, /!< CAN1 RX0 Interrupt /
Kojto	107:4f6c30876dfa	100	CAN1_RX1_IRQn = 21, /!< CAN1 RX1 Interrupt /
Kojto	107:4f6c30876dfa	101	CAN1_SCE_IRQn = 22, /!< CAN1 SCE Interrupt /
Kojto	107:4f6c30876dfa	102	EXTI9_5_IRQn = 23, /!< External Line[9:5] Interrupts /
Kojto	107:4f6c30876dfa	103	TIM1_BRK_TIM9_IRQn = 24, /!< TIM1 Break interrupt and TIM9 global interrupt /
Kojto	107:4f6c30876dfa	104	TIM1_UP_TIM10_IRQn = 25, /!< TIM1 Update Interrupt and TIM10 global interrupt /
Kojto	107:4f6c30876dfa	105	TIM1_TRG_COM_TIM11_IRQn = 26, /!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt /
Kojto	107:4f6c30876dfa	106	TIM1_CC_IRQn = 27, /!< TIM1 Capture Compare Interrupt /
Kojto	107:4f6c30876dfa	107	TIM2_IRQn = 28, /!< TIM2 global Interrupt /
Kojto	107:4f6c30876dfa	108	TIM3_IRQn = 29, /!< TIM3 global Interrupt /
Kojto	107:4f6c30876dfa	109	TIM4_IRQn = 30, /!< TIM4 global Interrupt /
Kojto	107:4f6c30876dfa	110	I2C1_EV_IRQn = 31, /!< I2C1 Event Interrupt /
Kojto	107:4f6c30876dfa	111	I2C1_ER_IRQn = 32, /!< I2C1 Error Interrupt /
Kojto	107:4f6c30876dfa	112	I2C2_EV_IRQn = 33, /!< I2C2 Event Interrupt /
Kojto	107:4f6c30876dfa	113	I2C2_ER_IRQn = 34, /!< I2C2 Error Interrupt /
Kojto	107:4f6c30876dfa	114	SPI1_IRQn = 35, /!< SPI1 global Interrupt /
Kojto	107:4f6c30876dfa	115	SPI2_IRQn = 36, /!< SPI2 global Interrupt /
Kojto	107:4f6c30876dfa	116	USART1_IRQn = 37, /!< USART1 global Interrupt /
Kojto	107:4f6c30876dfa	117	USART2_IRQn = 38, /!< USART2 global Interrupt /
Kojto	107:4f6c30876dfa	118	USART3_IRQn = 39, /!< USART3 global Interrupt /
Kojto	107:4f6c30876dfa	119	EXTI15_10_IRQn = 40, /!< External Line[15:10] Interrupts /
Kojto	107:4f6c30876dfa	120	RTC_Alarm_IRQn = 41, /!< RTC Alarm (A and B) through EXTI Line Interrupt /
Kojto	107:4f6c30876dfa	121	OTG_FS_WKUP_IRQn = 42, /!< USB OTG FS Wakeup through EXTI line interrupt /
Kojto	107:4f6c30876dfa	122	TIM8_BRK_TIM12_IRQn = 43, /!< TIM8 Break Interrupt and TIM12 global interrupt /
Kojto	107:4f6c30876dfa	123	TIM8_UP_TIM13_IRQn = 44, /!< TIM8 Update Interrupt and TIM13 global interrupt /
Kojto	107:4f6c30876dfa	124	TIM8_TRG_COM_TIM14_IRQn = 45, /!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt /
Kojto	107:4f6c30876dfa	125	TIM8_CC_IRQn = 46, /!< TIM8 Capture Compare Interrupt /
Kojto	107:4f6c30876dfa	126	DMA1_Stream7_IRQn = 47, /!< DMA1 Stream7 Interrupt /
Kojto	107:4f6c30876dfa	127	FMC_IRQn = 48, /!< FMC global Interrupt /
Kojto	116:c0f6e94411f5	128	SDMMC1_IRQn = 49, /!< SDMMC1 global Interrupt /
Kojto	107:4f6c30876dfa	129	TIM5_IRQn = 50, /!< TIM5 global Interrupt /
Kojto	107:4f6c30876dfa	130	SPI3_IRQn = 51, /!< SPI3 global Interrupt /
Kojto	107:4f6c30876dfa	131	UART4_IRQn = 52, /!< UART4 global Interrupt /
Kojto	107:4f6c30876dfa	132	UART5_IRQn = 53, /!< UART5 global Interrupt /
Kojto	107:4f6c30876dfa	133	TIM6_DAC_IRQn = 54, /!< TIM6 global and DAC1&2 underrun error interrupts /
Kojto	107:4f6c30876dfa	134	TIM7_IRQn = 55, /!< TIM7 global interrupt /
Kojto	107:4f6c30876dfa	135	DMA2_Stream0_IRQn = 56, /!< DMA2 Stream 0 global Interrupt /
Kojto	107:4f6c30876dfa	136	DMA2_Stream1_IRQn = 57, /!< DMA2 Stream 1 global Interrupt /
Kojto	107:4f6c30876dfa	137	DMA2_Stream2_IRQn = 58, /!< DMA2 Stream 2 global Interrupt /
Kojto	107:4f6c30876dfa	138	DMA2_Stream3_IRQn = 59, /!< DMA2 Stream 3 global Interrupt /
Kojto	107:4f6c30876dfa	139	DMA2_Stream4_IRQn = 60, /!< DMA2 Stream 4 global Interrupt /
Kojto	107:4f6c30876dfa	140	ETH_IRQn = 61, /!< Ethernet global Interrupt /
Kojto	107:4f6c30876dfa	141	ETH_WKUP_IRQn = 62, /!< Ethernet Wakeup through EXTI line Interrupt /
Kojto	107:4f6c30876dfa	142	CAN2_TX_IRQn = 63, /!< CAN2 TX Interrupt /
Kojto	107:4f6c30876dfa	143	CAN2_RX0_IRQn = 64, /!< CAN2 RX0 Interrupt /
Kojto	107:4f6c30876dfa	144	CAN2_RX1_IRQn = 65, /!< CAN2 RX1 Interrupt /
Kojto	107:4f6c30876dfa	145	CAN2_SCE_IRQn = 66, /!< CAN2 SCE Interrupt /
Kojto	107:4f6c30876dfa	146	OTG_FS_IRQn = 67, /!< USB OTG FS global Interrupt /
Kojto	107:4f6c30876dfa	147	DMA2_Stream5_IRQn = 68, /!< DMA2 Stream 5 global interrupt /
Kojto	107:4f6c30876dfa	148	DMA2_Stream6_IRQn = 69, /!< DMA2 Stream 6 global interrupt /
Kojto	107:4f6c30876dfa	149	DMA2_Stream7_IRQn = 70, /!< DMA2 Stream 7 global interrupt /
Kojto	107:4f6c30876dfa	150	USART6_IRQn = 71, /!< USART6 global interrupt /
Kojto	107:4f6c30876dfa	151	I2C3_EV_IRQn = 72, /!< I2C3 event interrupt /
Kojto	107:4f6c30876dfa	152	I2C3_ER_IRQn = 73, /!< I2C3 error interrupt /
Kojto	107:4f6c30876dfa	153	OTG_HS_EP1_OUT_IRQn = 74, /!< USB OTG HS End Point 1 Out global interrupt /
Kojto	107:4f6c30876dfa	154	OTG_HS_EP1_IN_IRQn = 75, /!< USB OTG HS End Point 1 In global interrupt /
Kojto	107:4f6c30876dfa	155	OTG_HS_WKUP_IRQn = 76, /!< USB OTG HS Wakeup through EXTI interrupt /
Kojto	107:4f6c30876dfa	156	OTG_HS_IRQn = 77, /!< USB OTG HS global interrupt /
Kojto	107:4f6c30876dfa	157	DCMI_IRQn = 78, /!< DCMI global interrupt /
Kojto	107:4f6c30876dfa	158	RNG_IRQn = 80, /!< RNG global interrupt /
Kojto	107:4f6c30876dfa	159	FPU_IRQn = 81, /!< FPU global interrupt /
Kojto	107:4f6c30876dfa	160	UART7_IRQn = 82, /!< UART7 global interrupt /
Kojto	107:4f6c30876dfa	161	UART8_IRQn = 83, /!< UART8 global interrupt /
Kojto	107:4f6c30876dfa	162	SPI4_IRQn = 84, /!< SPI4 global Interrupt /
Kojto	107:4f6c30876dfa	163	SPI5_IRQn = 85, /!< SPI5 global Interrupt /
Kojto	107:4f6c30876dfa	164	SPI6_IRQn = 86, /!< SPI6 global Interrupt /
Kojto	107:4f6c30876dfa	165	SAI1_IRQn = 87, /!< SAI1 global Interrupt /
Kojto	107:4f6c30876dfa	166	LTDC_IRQn = 88, /!< LTDC global Interrupt /
Kojto	107:4f6c30876dfa	167	LTDC_ER_IRQn = 89, /!< LTDC Error global Interrupt /
Kojto	107:4f6c30876dfa	168	DMA2D_IRQn = 90, /!< DMA2D global Interrupt /
Kojto	107:4f6c30876dfa	169	SAI2_IRQn = 91, /!< SAI2 global Interrupt /
Kojto	107:4f6c30876dfa	170	QUADSPI_IRQn = 92, /!< Quad SPI global interrupt /
Kojto	107:4f6c30876dfa	171	LPTIM1_IRQn = 93, /!< LP TIM1 interrupt /
Kojto	107:4f6c30876dfa	172	CEC_IRQn = 94, /!< HDMI-CEC global Interrupt /
Kojto	107:4f6c30876dfa	173	I2C4_EV_IRQn = 95, /!< I2C4 Event Interrupt /
Kojto	107:4f6c30876dfa	174	I2C4_ER_IRQn = 96, /!< I2C4 Error Interrupt /
Kojto	122:f9eeca106725	175	SPDIF_RX_IRQn = 97, /!< SPDIF-RX global Interrupt /
Kojto	107:4f6c30876dfa	176	} IRQn_Type;
Kojto	107:4f6c30876dfa	177
Kojto	107:4f6c30876dfa	178	/**
Kojto	107:4f6c30876dfa	179	* @}
Kojto	107:4f6c30876dfa	180	*/
Kojto	107:4f6c30876dfa	181
Kojto	107:4f6c30876dfa	182	/**
Kojto	107:4f6c30876dfa	183	* @brief Configuration of the Cortex-M7 Processor and Core Peripherals
Kojto	107:4f6c30876dfa	184	*/
Kojto	122:f9eeca106725	185	#define __CM7_REV 0x0001U /!< Cortex-M7 revision r0p1 /
Kojto	107:4f6c30876dfa	186	#define __MPU_PRESENT 1 /!< CM7 provides an MPU /
Kojto	107:4f6c30876dfa	187	#define __NVIC_PRIO_BITS 4 /!< CM7 uses 4 Bits for the Priority Levels /
Kojto	107:4f6c30876dfa	188	#define __Vendor_SysTickConfig 0 /!< Set to 1 if different SysTick Config is used /
Kojto	107:4f6c30876dfa	189	#define __FPU_PRESENT 1 /!< FPU present /
Kojto	107:4f6c30876dfa	190	#define __ICACHE_PRESENT 1 /!< CM7 instruction cache present /
Kojto	107:4f6c30876dfa	191	#define __DCACHE_PRESENT 1 /!< CM7 data cache present /
Kojto	116:c0f6e94411f5	192	#include "core_cm7.h" /!< Cortex-M7 processor and core peripherals /
Kojto	107:4f6c30876dfa	193
Kojto	107:4f6c30876dfa	194
Kojto	107:4f6c30876dfa	195	#include "system_stm32f7xx.h"
Kojto	107:4f6c30876dfa	196	#include <stdint.h>
Kojto	107:4f6c30876dfa	197
Kojto	107:4f6c30876dfa	198	/** @addtogroup Peripheral_registers_structures
Kojto	107:4f6c30876dfa	199	* @{
Kojto	107:4f6c30876dfa	200	*/
Kojto	107:4f6c30876dfa	201
Kojto	107:4f6c30876dfa	202	/**
Kojto	107:4f6c30876dfa	203	* @brief Analog to Digital Converter
Kojto	107:4f6c30876dfa	204	*/
Kojto	107:4f6c30876dfa	205
Kojto	107:4f6c30876dfa	206	typedef struct
Kojto	107:4f6c30876dfa	207	{
Kojto	107:4f6c30876dfa	208	__IO uint32_t SR; /!< ADC status register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	209	__IO uint32_t CR1; /!< ADC control register 1, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	210	__IO uint32_t CR2; /!< ADC control register 2, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	211	__IO uint32_t SMPR1; /!< ADC sample time register 1, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	212	__IO uint32_t SMPR2; /!< ADC sample time register 2, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	213	__IO uint32_t JOFR1; /!< ADC injected channel data offset register 1, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	214	__IO uint32_t JOFR2; /!< ADC injected channel data offset register 2, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	215	__IO uint32_t JOFR3; /!< ADC injected channel data offset register 3, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	216	__IO uint32_t JOFR4; /!< ADC injected channel data offset register 4, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	217	__IO uint32_t HTR; /!< ADC watchdog higher threshold register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	218	__IO uint32_t LTR; /!< ADC watchdog lower threshold register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	219	__IO uint32_t SQR1; /!< ADC regular sequence register 1, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	220	__IO uint32_t SQR2; /!< ADC regular sequence register 2, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	221	__IO uint32_t SQR3; /!< ADC regular sequence register 3, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	222	__IO uint32_t JSQR; /!< ADC injected sequence register, Address offset: 0x38/
Kojto	107:4f6c30876dfa	223	__IO uint32_t JDR1; /!< ADC injected data register 1, Address offset: 0x3C /
Kojto	107:4f6c30876dfa	224	__IO uint32_t JDR2; /!< ADC injected data register 2, Address offset: 0x40 /
Kojto	107:4f6c30876dfa	225	__IO uint32_t JDR3; /!< ADC injected data register 3, Address offset: 0x44 /
Kojto	107:4f6c30876dfa	226	__IO uint32_t JDR4; /!< ADC injected data register 4, Address offset: 0x48 /
Kojto	107:4f6c30876dfa	227	__IO uint32_t DR; /!< ADC regular data register, Address offset: 0x4C /
Kojto	107:4f6c30876dfa	228	} ADC_TypeDef;
Kojto	107:4f6c30876dfa	229
Kojto	107:4f6c30876dfa	230	typedef struct
Kojto	107:4f6c30876dfa	231	{
Kojto	107:4f6c30876dfa	232	__IO uint32_t CSR; /!< ADC Common status register, Address offset: ADC1 base address + 0x300 /
Kojto	107:4f6c30876dfa	233	__IO uint32_t CCR; /!< ADC common control register, Address offset: ADC1 base address + 0x304 /
Kojto	107:4f6c30876dfa	234	__IO uint32_t CDR; /*!< ADC common regular data register for dual
Kojto	107:4f6c30876dfa	235	AND triple modes, Address offset: ADC1 base address + 0x308 */
Kojto	107:4f6c30876dfa	236	} ADC_Common_TypeDef;
Kojto	107:4f6c30876dfa	237
Kojto	107:4f6c30876dfa	238
Kojto	107:4f6c30876dfa	239	/**
Kojto	107:4f6c30876dfa	240	* @brief Controller Area Network TxMailBox
Kojto	107:4f6c30876dfa	241	*/
Kojto	107:4f6c30876dfa	242
Kojto	107:4f6c30876dfa	243	typedef struct
Kojto	107:4f6c30876dfa	244	{
Kojto	107:4f6c30876dfa	245	__IO uint32_t TIR; /!< CAN TX mailbox identifier register /
Kojto	107:4f6c30876dfa	246	__IO uint32_t TDTR; /!< CAN mailbox data length control and time stamp register /
Kojto	107:4f6c30876dfa	247	__IO uint32_t TDLR; /!< CAN mailbox data low register /
Kojto	107:4f6c30876dfa	248	__IO uint32_t TDHR; /!< CAN mailbox data high register /
Kojto	107:4f6c30876dfa	249	} CAN_TxMailBox_TypeDef;
Kojto	107:4f6c30876dfa	250
Kojto	107:4f6c30876dfa	251	/**
Kojto	107:4f6c30876dfa	252	* @brief Controller Area Network FIFOMailBox
Kojto	107:4f6c30876dfa	253	*/
Kojto	107:4f6c30876dfa	254
Kojto	107:4f6c30876dfa	255	typedef struct
Kojto	107:4f6c30876dfa	256	{
Kojto	107:4f6c30876dfa	257	__IO uint32_t RIR; /!< CAN receive FIFO mailbox identifier register /
Kojto	107:4f6c30876dfa	258	__IO uint32_t RDTR; /!< CAN receive FIFO mailbox data length control and time stamp register /
Kojto	107:4f6c30876dfa	259	__IO uint32_t RDLR; /!< CAN receive FIFO mailbox data low register /
Kojto	107:4f6c30876dfa	260	__IO uint32_t RDHR; /!< CAN receive FIFO mailbox data high register /
Kojto	107:4f6c30876dfa	261	} CAN_FIFOMailBox_TypeDef;
Kojto	107:4f6c30876dfa	262
Kojto	107:4f6c30876dfa	263	/**
Kojto	107:4f6c30876dfa	264	* @brief Controller Area Network FilterRegister
Kojto	107:4f6c30876dfa	265	*/
Kojto	107:4f6c30876dfa	266
Kojto	107:4f6c30876dfa	267	typedef struct
Kojto	107:4f6c30876dfa	268	{
Kojto	107:4f6c30876dfa	269	__IO uint32_t FR1; /!< CAN Filter bank register 1 /
Kojto	107:4f6c30876dfa	270	__IO uint32_t FR2; /!< CAN Filter bank register 1 /
Kojto	107:4f6c30876dfa	271	} CAN_FilterRegister_TypeDef;
Kojto	107:4f6c30876dfa	272
Kojto	107:4f6c30876dfa	273	/**
Kojto	107:4f6c30876dfa	274	* @brief Controller Area Network
Kojto	107:4f6c30876dfa	275	*/
Kojto	107:4f6c30876dfa	276
Kojto	107:4f6c30876dfa	277	typedef struct
Kojto	107:4f6c30876dfa	278	{
Kojto	107:4f6c30876dfa	279	__IO uint32_t MCR; /!< CAN master control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	280	__IO uint32_t MSR; /!< CAN master status register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	281	__IO uint32_t TSR; /!< CAN transmit status register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	282	__IO uint32_t RF0R; /!< CAN receive FIFO 0 register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	283	__IO uint32_t RF1R; /!< CAN receive FIFO 1 register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	284	__IO uint32_t IER; /!< CAN interrupt enable register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	285	__IO uint32_t ESR; /!< CAN error status register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	286	__IO uint32_t BTR; /!< CAN bit timing register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	287	uint32_t RESERVED0[88]; /!< Reserved, 0x020 - 0x17F /
Kojto	107:4f6c30876dfa	288	CAN_TxMailBox_TypeDef sTxMailBox[3]; /!< CAN Tx MailBox, Address offset: 0x180 - 0x1AC /
Kojto	107:4f6c30876dfa	289	CAN_FIFOMailBox_TypeDef sFIFOMailBox[2]; /!< CAN FIFO MailBox, Address offset: 0x1B0 - 0x1CC /
Kojto	107:4f6c30876dfa	290	uint32_t RESERVED1[12]; /!< Reserved, 0x1D0 - 0x1FF /
Kojto	107:4f6c30876dfa	291	__IO uint32_t FMR; /!< CAN filter master register, Address offset: 0x200 /
Kojto	107:4f6c30876dfa	292	__IO uint32_t FM1R; /!< CAN filter mode register, Address offset: 0x204 /
Kojto	107:4f6c30876dfa	293	uint32_t RESERVED2; /!< Reserved, 0x208 /
Kojto	107:4f6c30876dfa	294	__IO uint32_t FS1R; /!< CAN filter scale register, Address offset: 0x20C /
Kojto	107:4f6c30876dfa	295	uint32_t RESERVED3; /!< Reserved, 0x210 /
Kojto	107:4f6c30876dfa	296	__IO uint32_t FFA1R; /!< CAN filter FIFO assignment register, Address offset: 0x214 /
Kojto	107:4f6c30876dfa	297	uint32_t RESERVED4; /!< Reserved, 0x218 /
Kojto	107:4f6c30876dfa	298	__IO uint32_t FA1R; /!< CAN filter activation register, Address offset: 0x21C /
Kojto	107:4f6c30876dfa	299	uint32_t RESERVED5[8]; /!< Reserved, 0x220-0x23F /
Kojto	107:4f6c30876dfa	300	CAN_FilterRegister_TypeDef sFilterRegister[28]; /!< CAN Filter Register, Address offset: 0x240-0x31C /
Kojto	107:4f6c30876dfa	301	} CAN_TypeDef;
Kojto	107:4f6c30876dfa	302
Kojto	107:4f6c30876dfa	303	/**
Kojto	107:4f6c30876dfa	304	* @brief HDMI-CEC
Kojto	107:4f6c30876dfa	305	*/
Kojto	107:4f6c30876dfa	306
Kojto	107:4f6c30876dfa	307	typedef struct
Kojto	107:4f6c30876dfa	308	{
Kojto	107:4f6c30876dfa	309	__IO uint32_t CR; /!< CEC control register, Address offset:0x00 /
Kojto	107:4f6c30876dfa	310	__IO uint32_t CFGR; /!< CEC configuration register, Address offset:0x04 /
Kojto	107:4f6c30876dfa	311	__IO uint32_t TXDR; /!< CEC Tx data register , Address offset:0x08 /
Kojto	107:4f6c30876dfa	312	__IO uint32_t RXDR; /!< CEC Rx Data Register, Address offset:0x0C /
Kojto	107:4f6c30876dfa	313	__IO uint32_t ISR; /!< CEC Interrupt and Status Register, Address offset:0x10 /
Kojto	107:4f6c30876dfa	314	__IO uint32_t IER; /!< CEC interrupt enable register, Address offset:0x14 /
Kojto	107:4f6c30876dfa	315	}CEC_TypeDef;
Kojto	107:4f6c30876dfa	316
Kojto	107:4f6c30876dfa	317
Kojto	107:4f6c30876dfa	318	/**
Kojto	107:4f6c30876dfa	319	* @brief CRC calculation unit
Kojto	107:4f6c30876dfa	320	*/
Kojto	107:4f6c30876dfa	321
Kojto	107:4f6c30876dfa	322	typedef struct
Kojto	107:4f6c30876dfa	323	{
Kojto	107:4f6c30876dfa	324	__IO uint32_t DR; /!< CRC Data register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	325	__IO uint8_t IDR; /!< CRC Independent data register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	326	uint8_t RESERVED0; /!< Reserved, 0x05 /
Kojto	107:4f6c30876dfa	327	uint16_t RESERVED1; /!< Reserved, 0x06 /
Kojto	107:4f6c30876dfa	328	__IO uint32_t CR; /!< CRC Control register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	329	uint32_t RESERVED2; /!< Reserved, 0x0C /
Kojto	107:4f6c30876dfa	330	__IO uint32_t INIT; /!< Initial CRC value register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	331	__IO uint32_t POL; /!< CRC polynomial register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	332	} CRC_TypeDef;
Kojto	107:4f6c30876dfa	333
Kojto	107:4f6c30876dfa	334	/**
Kojto	107:4f6c30876dfa	335	* @brief Digital to Analog Converter
Kojto	107:4f6c30876dfa	336	*/
Kojto	107:4f6c30876dfa	337
Kojto	107:4f6c30876dfa	338	typedef struct
Kojto	107:4f6c30876dfa	339	{
Kojto	107:4f6c30876dfa	340	__IO uint32_t CR; /!< DAC control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	341	__IO uint32_t SWTRIGR; /!< DAC software trigger register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	342	__IO uint32_t DHR12R1; /!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	343	__IO uint32_t DHR12L1; /!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	344	__IO uint32_t DHR8R1; /!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	345	__IO uint32_t DHR12R2; /!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	346	__IO uint32_t DHR12L2; /!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	347	__IO uint32_t DHR8R2; /!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	348	__IO uint32_t DHR12RD; /!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	349	__IO uint32_t DHR12LD; /!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	350	__IO uint32_t DHR8RD; /!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	351	__IO uint32_t DOR1; /!< DAC channel1 data output register, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	352	__IO uint32_t DOR2; /!< DAC channel2 data output register, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	353	__IO uint32_t SR; /!< DAC status register, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	354	} DAC_TypeDef;
Kojto	107:4f6c30876dfa	355
Kojto	116:c0f6e94411f5	356
Kojto	107:4f6c30876dfa	357	/**
Kojto	107:4f6c30876dfa	358	* @brief Debug MCU
Kojto	107:4f6c30876dfa	359	*/
Kojto	107:4f6c30876dfa	360
Kojto	107:4f6c30876dfa	361	typedef struct
Kojto	107:4f6c30876dfa	362	{
Kojto	107:4f6c30876dfa	363	__IO uint32_t IDCODE; /!< MCU device ID code, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	364	__IO uint32_t CR; /!< Debug MCU configuration register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	365	__IO uint32_t APB1FZ; /!< Debug MCU APB1 freeze register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	366	__IO uint32_t APB2FZ; /!< Debug MCU APB2 freeze register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	367	}DBGMCU_TypeDef;
Kojto	107:4f6c30876dfa	368
Kojto	107:4f6c30876dfa	369	/**
Kojto	107:4f6c30876dfa	370	* @brief DCMI
Kojto	107:4f6c30876dfa	371	*/
Kojto	107:4f6c30876dfa	372
Kojto	107:4f6c30876dfa	373	typedef struct
Kojto	107:4f6c30876dfa	374	{
Kojto	107:4f6c30876dfa	375	__IO uint32_t CR; /!< DCMI control register 1, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	376	__IO uint32_t SR; /!< DCMI status register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	377	__IO uint32_t RISR; /!< DCMI raw interrupt status register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	378	__IO uint32_t IER; /!< DCMI interrupt enable register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	379	__IO uint32_t MISR; /!< DCMI masked interrupt status register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	380	__IO uint32_t ICR; /!< DCMI interrupt clear register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	381	__IO uint32_t ESCR; /!< DCMI embedded synchronization code register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	382	__IO uint32_t ESUR; /!< DCMI embedded synchronization unmask register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	383	__IO uint32_t CWSTRTR; /!< DCMI crop window start, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	384	__IO uint32_t CWSIZER; /!< DCMI crop window size, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	385	__IO uint32_t DR; /!< DCMI data register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	386	} DCMI_TypeDef;
Kojto	107:4f6c30876dfa	387
Kojto	107:4f6c30876dfa	388	/**
Kojto	107:4f6c30876dfa	389	* @brief DMA Controller
Kojto	107:4f6c30876dfa	390	*/
Kojto	107:4f6c30876dfa	391
Kojto	107:4f6c30876dfa	392	typedef struct
Kojto	107:4f6c30876dfa	393	{
Kojto	107:4f6c30876dfa	394	__IO uint32_t CR; /!< DMA stream x configuration register /
Kojto	107:4f6c30876dfa	395	__IO uint32_t NDTR; /!< DMA stream x number of data register /
Kojto	107:4f6c30876dfa	396	__IO uint32_t PAR; /!< DMA stream x peripheral address register /
Kojto	107:4f6c30876dfa	397	__IO uint32_t M0AR; /!< DMA stream x memory 0 address register /
Kojto	107:4f6c30876dfa	398	__IO uint32_t M1AR; /!< DMA stream x memory 1 address register /
Kojto	107:4f6c30876dfa	399	__IO uint32_t FCR; /!< DMA stream x FIFO control register /
Kojto	107:4f6c30876dfa	400	} DMA_Stream_TypeDef;
Kojto	107:4f6c30876dfa	401
Kojto	107:4f6c30876dfa	402	typedef struct
Kojto	107:4f6c30876dfa	403	{
Kojto	107:4f6c30876dfa	404	__IO uint32_t LISR; /!< DMA low interrupt status register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	405	__IO uint32_t HISR; /!< DMA high interrupt status register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	406	__IO uint32_t LIFCR; /!< DMA low interrupt flag clear register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	407	__IO uint32_t HIFCR; /!< DMA high interrupt flag clear register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	408	} DMA_TypeDef;
Kojto	107:4f6c30876dfa	409
Kojto	107:4f6c30876dfa	410
Kojto	107:4f6c30876dfa	411	/**
Kojto	107:4f6c30876dfa	412	* @brief DMA2D Controller
Kojto	107:4f6c30876dfa	413	*/
Kojto	107:4f6c30876dfa	414
Kojto	107:4f6c30876dfa	415	typedef struct
Kojto	107:4f6c30876dfa	416	{
Kojto	107:4f6c30876dfa	417	__IO uint32_t CR; /!< DMA2D Control Register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	418	__IO uint32_t ISR; /!< DMA2D Interrupt Status Register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	419	__IO uint32_t IFCR; /!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	420	__IO uint32_t FGMAR; /!< DMA2D Foreground Memory Address Register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	421	__IO uint32_t FGOR; /!< DMA2D Foreground Offset Register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	422	__IO uint32_t BGMAR; /!< DMA2D Background Memory Address Register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	423	__IO uint32_t BGOR; /!< DMA2D Background Offset Register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	424	__IO uint32_t FGPFCCR; /!< DMA2D Foreground PFC Control Register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	425	__IO uint32_t FGCOLR; /!< DMA2D Foreground Color Register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	426	__IO uint32_t BGPFCCR; /!< DMA2D Background PFC Control Register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	427	__IO uint32_t BGCOLR; /!< DMA2D Background Color Register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	428	__IO uint32_t FGCMAR; /!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	429	__IO uint32_t BGCMAR; /!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	430	__IO uint32_t OPFCCR; /!< DMA2D Output PFC Control Register, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	431	__IO uint32_t OCOLR; /!< DMA2D Output Color Register, Address offset: 0x38 /
Kojto	107:4f6c30876dfa	432	__IO uint32_t OMAR; /!< DMA2D Output Memory Address Register, Address offset: 0x3C /
Kojto	107:4f6c30876dfa	433	__IO uint32_t OOR; /!< DMA2D Output Offset Register, Address offset: 0x40 /
Kojto	107:4f6c30876dfa	434	__IO uint32_t NLR; /!< DMA2D Number of Line Register, Address offset: 0x44 /
Kojto	107:4f6c30876dfa	435	__IO uint32_t LWR; /!< DMA2D Line Watermark Register, Address offset: 0x48 /
Kojto	107:4f6c30876dfa	436	__IO uint32_t AMTCR; /!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C /
Kojto	107:4f6c30876dfa	437	uint32_t RESERVED[236]; /!< Reserved, 0x50-0x3FF /
Kojto	107:4f6c30876dfa	438	__IO uint32_t FGCLUT[256]; /!< DMA2D Foreground CLUT, Address offset:400-7FF /
Kojto	107:4f6c30876dfa	439	__IO uint32_t BGCLUT[256]; /!< DMA2D Background CLUT, Address offset:800-BFF /
Kojto	107:4f6c30876dfa	440	} DMA2D_TypeDef;
Kojto	107:4f6c30876dfa	441
Kojto	107:4f6c30876dfa	442
Kojto	107:4f6c30876dfa	443	/**
Kojto	107:4f6c30876dfa	444	* @brief Ethernet MAC
Kojto	107:4f6c30876dfa	445	*/
Kojto	107:4f6c30876dfa	446
Kojto	107:4f6c30876dfa	447	typedef struct
Kojto	107:4f6c30876dfa	448	{
Kojto	107:4f6c30876dfa	449	__IO uint32_t MACCR;
Kojto	107:4f6c30876dfa	450	__IO uint32_t MACFFR;
Kojto	107:4f6c30876dfa	451	__IO uint32_t MACHTHR;
Kojto	107:4f6c30876dfa	452	__IO uint32_t MACHTLR;
Kojto	107:4f6c30876dfa	453	__IO uint32_t MACMIIAR;
Kojto	107:4f6c30876dfa	454	__IO uint32_t MACMIIDR;
Kojto	107:4f6c30876dfa	455	__IO uint32_t MACFCR;
Kojto	107:4f6c30876dfa	456	__IO uint32_t MACVLANTR; /* 8 */
Kojto	107:4f6c30876dfa	457	uint32_t RESERVED0[2];
Kojto	107:4f6c30876dfa	458	__IO uint32_t MACRWUFFR; /* 11 */
Kojto	107:4f6c30876dfa	459	__IO uint32_t MACPMTCSR;
Kojto	107:4f6c30876dfa	460	uint32_t RESERVED1[2];
Kojto	107:4f6c30876dfa	461	__IO uint32_t MACSR; /* 15 */
Kojto	107:4f6c30876dfa	462	__IO uint32_t MACIMR;
Kojto	107:4f6c30876dfa	463	__IO uint32_t MACA0HR;
Kojto	107:4f6c30876dfa	464	__IO uint32_t MACA0LR;
Kojto	107:4f6c30876dfa	465	__IO uint32_t MACA1HR;
Kojto	107:4f6c30876dfa	466	__IO uint32_t MACA1LR;
Kojto	107:4f6c30876dfa	467	__IO uint32_t MACA2HR;
Kojto	107:4f6c30876dfa	468	__IO uint32_t MACA2LR;
Kojto	107:4f6c30876dfa	469	__IO uint32_t MACA3HR;
Kojto	107:4f6c30876dfa	470	__IO uint32_t MACA3LR; /* 24 */
Kojto	107:4f6c30876dfa	471	uint32_t RESERVED2[40];
Kojto	107:4f6c30876dfa	472	__IO uint32_t MMCCR; /* 65 */
Kojto	107:4f6c30876dfa	473	__IO uint32_t MMCRIR;
Kojto	107:4f6c30876dfa	474	__IO uint32_t MMCTIR;
Kojto	107:4f6c30876dfa	475	__IO uint32_t MMCRIMR;
Kojto	107:4f6c30876dfa	476	__IO uint32_t MMCTIMR; /* 69 */
Kojto	107:4f6c30876dfa	477	uint32_t RESERVED3[14];
Kojto	107:4f6c30876dfa	478	__IO uint32_t MMCTGFSCCR; /* 84 */
Kojto	107:4f6c30876dfa	479	__IO uint32_t MMCTGFMSCCR;
Kojto	107:4f6c30876dfa	480	uint32_t RESERVED4[5];
Kojto	107:4f6c30876dfa	481	__IO uint32_t MMCTGFCR;
Kojto	107:4f6c30876dfa	482	uint32_t RESERVED5[10];
Kojto	107:4f6c30876dfa	483	__IO uint32_t MMCRFCECR;
Kojto	107:4f6c30876dfa	484	__IO uint32_t MMCRFAECR;
Kojto	107:4f6c30876dfa	485	uint32_t RESERVED6[10];
Kojto	107:4f6c30876dfa	486	__IO uint32_t MMCRGUFCR;
Kojto	107:4f6c30876dfa	487	uint32_t RESERVED7[334];
Kojto	107:4f6c30876dfa	488	__IO uint32_t PTPTSCR;
Kojto	107:4f6c30876dfa	489	__IO uint32_t PTPSSIR;
Kojto	107:4f6c30876dfa	490	__IO uint32_t PTPTSHR;
Kojto	107:4f6c30876dfa	491	__IO uint32_t PTPTSLR;
Kojto	107:4f6c30876dfa	492	__IO uint32_t PTPTSHUR;
Kojto	107:4f6c30876dfa	493	__IO uint32_t PTPTSLUR;
Kojto	107:4f6c30876dfa	494	__IO uint32_t PTPTSAR;
Kojto	107:4f6c30876dfa	495	__IO uint32_t PTPTTHR;
Kojto	107:4f6c30876dfa	496	__IO uint32_t PTPTTLR;
Kojto	107:4f6c30876dfa	497	__IO uint32_t RESERVED8;
Kojto	107:4f6c30876dfa	498	__IO uint32_t PTPTSSR;
Kojto	107:4f6c30876dfa	499	uint32_t RESERVED9[565];
Kojto	107:4f6c30876dfa	500	__IO uint32_t DMABMR;
Kojto	107:4f6c30876dfa	501	__IO uint32_t DMATPDR;
Kojto	107:4f6c30876dfa	502	__IO uint32_t DMARPDR;
Kojto	107:4f6c30876dfa	503	__IO uint32_t DMARDLAR;
Kojto	107:4f6c30876dfa	504	__IO uint32_t DMATDLAR;
Kojto	107:4f6c30876dfa	505	__IO uint32_t DMASR;
Kojto	107:4f6c30876dfa	506	__IO uint32_t DMAOMR;
Kojto	107:4f6c30876dfa	507	__IO uint32_t DMAIER;
Kojto	107:4f6c30876dfa	508	__IO uint32_t DMAMFBOCR;
Kojto	107:4f6c30876dfa	509	__IO uint32_t DMARSWTR;
Kojto	107:4f6c30876dfa	510	uint32_t RESERVED10[8];
Kojto	107:4f6c30876dfa	511	__IO uint32_t DMACHTDR;
Kojto	107:4f6c30876dfa	512	__IO uint32_t DMACHRDR;
Kojto	107:4f6c30876dfa	513	__IO uint32_t DMACHTBAR;
Kojto	107:4f6c30876dfa	514	__IO uint32_t DMACHRBAR;
Kojto	107:4f6c30876dfa	515	} ETH_TypeDef;
Kojto	107:4f6c30876dfa	516
Kojto	107:4f6c30876dfa	517	/**
Kojto	107:4f6c30876dfa	518	* @brief External Interrupt/Event Controller
Kojto	107:4f6c30876dfa	519	*/
Kojto	107:4f6c30876dfa	520
Kojto	107:4f6c30876dfa	521	typedef struct
Kojto	107:4f6c30876dfa	522	{
Kojto	107:4f6c30876dfa	523	__IO uint32_t IMR; /!< EXTI Interrupt mask register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	524	__IO uint32_t EMR; /!< EXTI Event mask register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	525	__IO uint32_t RTSR; /!< EXTI Rising trigger selection register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	526	__IO uint32_t FTSR; /!< EXTI Falling trigger selection register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	527	__IO uint32_t SWIER; /!< EXTI Software interrupt event register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	528	__IO uint32_t PR; /!< EXTI Pending register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	529	} EXTI_TypeDef;
Kojto	107:4f6c30876dfa	530
Kojto	107:4f6c30876dfa	531	/**
Kojto	107:4f6c30876dfa	532	* @brief FLASH Registers
Kojto	107:4f6c30876dfa	533	*/
Kojto	107:4f6c30876dfa	534
Kojto	107:4f6c30876dfa	535	typedef struct
Kojto	107:4f6c30876dfa	536	{
Kojto	107:4f6c30876dfa	537	__IO uint32_t ACR; /!< FLASH access control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	538	__IO uint32_t KEYR; /!< FLASH key register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	539	__IO uint32_t OPTKEYR; /!< FLASH option key register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	540	__IO uint32_t SR; /!< FLASH status register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	541	__IO uint32_t CR; /!< FLASH control register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	542	__IO uint32_t OPTCR; /!< FLASH option control register , Address offset: 0x14 /
Kojto	107:4f6c30876dfa	543	__IO uint32_t OPTCR1; /!< FLASH option control register 1 , Address offset: 0x18 /
Kojto	107:4f6c30876dfa	544	} FLASH_TypeDef;
Kojto	107:4f6c30876dfa	545
Kojto	107:4f6c30876dfa	546
Kojto	107:4f6c30876dfa	547
Kojto	107:4f6c30876dfa	548	/**
Kojto	107:4f6c30876dfa	549	* @brief Flexible Memory Controller
Kojto	107:4f6c30876dfa	550	*/
Kojto	107:4f6c30876dfa	551
Kojto	107:4f6c30876dfa	552	typedef struct
Kojto	107:4f6c30876dfa	553	{
Kojto	107:4f6c30876dfa	554	__IO uint32_t BTCR[8]; /!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C /
Kojto	107:4f6c30876dfa	555	} FMC_Bank1_TypeDef;
Kojto	107:4f6c30876dfa	556
Kojto	107:4f6c30876dfa	557	/**
Kojto	107:4f6c30876dfa	558	* @brief Flexible Memory Controller Bank1E
Kojto	107:4f6c30876dfa	559	*/
Kojto	107:4f6c30876dfa	560
Kojto	107:4f6c30876dfa	561	typedef struct
Kojto	107:4f6c30876dfa	562	{
Kojto	107:4f6c30876dfa	563	__IO uint32_t BWTR[7]; /!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C /
Kojto	107:4f6c30876dfa	564	} FMC_Bank1E_TypeDef;
Kojto	107:4f6c30876dfa	565
Kojto	107:4f6c30876dfa	566	/**
Kojto	107:4f6c30876dfa	567	* @brief Flexible Memory Controller Bank3
Kojto	107:4f6c30876dfa	568	*/
Kojto	107:4f6c30876dfa	569
Kojto	107:4f6c30876dfa	570	typedef struct
Kojto	107:4f6c30876dfa	571	{
Kojto	107:4f6c30876dfa	572	__IO uint32_t PCR; /!< NAND Flash control register, Address offset: 0x80 /
Kojto	107:4f6c30876dfa	573	__IO uint32_t SR; /!< NAND Flash FIFO status and interrupt register, Address offset: 0x84 /
Kojto	107:4f6c30876dfa	574	__IO uint32_t PMEM; /!< NAND Flash Common memory space timing register, Address offset: 0x88 /
Kojto	107:4f6c30876dfa	575	__IO uint32_t PATT; /!< NAND Flash Attribute memory space timing register, Address offset: 0x8C /
Kojto	107:4f6c30876dfa	576	uint32_t RESERVED0; /!< Reserved, 0x90 /
Kojto	107:4f6c30876dfa	577	__IO uint32_t ECCR; /!< NAND Flash ECC result registers, Address offset: 0x94 /
Kojto	107:4f6c30876dfa	578	} FMC_Bank3_TypeDef;
Kojto	107:4f6c30876dfa	579
Kojto	107:4f6c30876dfa	580	/**
Kojto	107:4f6c30876dfa	581	* @brief Flexible Memory Controller Bank5_6
Kojto	107:4f6c30876dfa	582	*/
Kojto	107:4f6c30876dfa	583
Kojto	107:4f6c30876dfa	584	typedef struct
Kojto	107:4f6c30876dfa	585	{
Kojto	107:4f6c30876dfa	586	__IO uint32_t SDCR[2]; /!< SDRAM Control registers , Address offset: 0x140-0x144 /
Kojto	107:4f6c30876dfa	587	__IO uint32_t SDTR[2]; /!< SDRAM Timing registers , Address offset: 0x148-0x14C /
Kojto	107:4f6c30876dfa	588	__IO uint32_t SDCMR; /!< SDRAM Command Mode register, Address offset: 0x150 /
Kojto	107:4f6c30876dfa	589	__IO uint32_t SDRTR; /!< SDRAM Refresh Timer register, Address offset: 0x154 /
Kojto	107:4f6c30876dfa	590	__IO uint32_t SDSR; /!< SDRAM Status register, Address offset: 0x158 /
Kojto	107:4f6c30876dfa	591	} FMC_Bank5_6_TypeDef;
Kojto	107:4f6c30876dfa	592
Kojto	107:4f6c30876dfa	593
Kojto	107:4f6c30876dfa	594	/**
Kojto	107:4f6c30876dfa	595	* @brief General Purpose I/O
Kojto	107:4f6c30876dfa	596	*/
Kojto	107:4f6c30876dfa	597
Kojto	107:4f6c30876dfa	598	typedef struct
Kojto	107:4f6c30876dfa	599	{
Kojto	107:4f6c30876dfa	600	__IO uint32_t MODER; /!< GPIO port mode register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	601	__IO uint32_t OTYPER; /!< GPIO port output type register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	602	__IO uint32_t OSPEEDR; /!< GPIO port output speed register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	603	__IO uint32_t PUPDR; /!< GPIO port pull-up/pull-down register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	604	__IO uint32_t IDR; /!< GPIO port input data register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	605	__IO uint32_t ODR; /!< GPIO port output data register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	606	__IO uint32_t BSRR; /!< GPIO port bit set/reset register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	607	__IO uint32_t LCKR; /!< GPIO port configuration lock register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	608	__IO uint32_t AFR[2]; /!< GPIO alternate function registers, Address offset: 0x20-0x24 /
Kojto	107:4f6c30876dfa	609	} GPIO_TypeDef;
Kojto	107:4f6c30876dfa	610
Kojto	107:4f6c30876dfa	611	/**
Kojto	107:4f6c30876dfa	612	* @brief System configuration controller
Kojto	107:4f6c30876dfa	613	*/
Kojto	107:4f6c30876dfa	614
Kojto	107:4f6c30876dfa	615	typedef struct
Kojto	107:4f6c30876dfa	616	{
Kojto	107:4f6c30876dfa	617	__IO uint32_t MEMRMP; /!< SYSCFG memory remap register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	618	__IO uint32_t PMC; /!< SYSCFG peripheral mode configuration register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	619	__IO uint32_t EXTICR[4]; /!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 /
Kojto	122:f9eeca106725	620	uint32_t RESERVED[2]; /!< Reserved, 0x18-0x1C /
Kojto	107:4f6c30876dfa	621	__IO uint32_t CMPCR; /!< SYSCFG Compensation cell control register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	622	} SYSCFG_TypeDef;
Kojto	107:4f6c30876dfa	623
Kojto	107:4f6c30876dfa	624	/**
Kojto	107:4f6c30876dfa	625	* @brief Inter-integrated Circuit Interface
Kojto	107:4f6c30876dfa	626	*/
Kojto	107:4f6c30876dfa	627
Kojto	107:4f6c30876dfa	628	typedef struct
Kojto	107:4f6c30876dfa	629	{
Kojto	107:4f6c30876dfa	630	__IO uint32_t CR1; /!< I2C Control register 1, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	631	__IO uint32_t CR2; /!< I2C Control register 2, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	632	__IO uint32_t OAR1; /!< I2C Own address 1 register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	633	__IO uint32_t OAR2; /!< I2C Own address 2 register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	634	__IO uint32_t TIMINGR; /!< I2C Timing register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	635	__IO uint32_t TIMEOUTR; /!< I2C Timeout register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	636	__IO uint32_t ISR; /!< I2C Interrupt and status register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	637	__IO uint32_t ICR; /!< I2C Interrupt clear register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	638	__IO uint32_t PECR; /!< I2C PEC register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	639	__IO uint32_t RXDR; /!< I2C Receive data register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	640	__IO uint32_t TXDR; /!< I2C Transmit data register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	641	} I2C_TypeDef;
Kojto	107:4f6c30876dfa	642
Kojto	107:4f6c30876dfa	643	/**
Kojto	107:4f6c30876dfa	644	* @brief Independent WATCHDOG
Kojto	107:4f6c30876dfa	645	*/
Kojto	107:4f6c30876dfa	646
Kojto	107:4f6c30876dfa	647	typedef struct
Kojto	107:4f6c30876dfa	648	{
Kojto	107:4f6c30876dfa	649	__IO uint32_t KR; /!< IWDG Key register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	650	__IO uint32_t PR; /!< IWDG Prescaler register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	651	__IO uint32_t RLR; /!< IWDG Reload register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	652	__IO uint32_t SR; /!< IWDG Status register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	653	__IO uint32_t WINR; /!< IWDG Window register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	654	} IWDG_TypeDef;
Kojto	107:4f6c30876dfa	655
Kojto	107:4f6c30876dfa	656
Kojto	107:4f6c30876dfa	657	/**
Kojto	107:4f6c30876dfa	658	* @brief LCD-TFT Display Controller
Kojto	107:4f6c30876dfa	659	*/
Kojto	107:4f6c30876dfa	660
Kojto	107:4f6c30876dfa	661	typedef struct
Kojto	107:4f6c30876dfa	662	{
Kojto	107:4f6c30876dfa	663	uint32_t RESERVED0[2]; /!< Reserved, 0x00-0x04 /
Kojto	107:4f6c30876dfa	664	__IO uint32_t SSCR; /!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	665	__IO uint32_t BPCR; /!< LTDC Back Porch Configuration Register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	666	__IO uint32_t AWCR; /!< LTDC Active Width Configuration Register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	667	__IO uint32_t TWCR; /!< LTDC Total Width Configuration Register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	668	__IO uint32_t GCR; /!< LTDC Global Control Register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	669	uint32_t RESERVED1[2]; /!< Reserved, 0x1C-0x20 /
Kojto	107:4f6c30876dfa	670	__IO uint32_t SRCR; /!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	671	uint32_t RESERVED2[1]; /!< Reserved, 0x28 /
Kojto	107:4f6c30876dfa	672	__IO uint32_t BCCR; /!< LTDC Background Color Configuration Register, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	673	uint32_t RESERVED3[1]; /!< Reserved, 0x30 /
Kojto	107:4f6c30876dfa	674	__IO uint32_t IER; /!< LTDC Interrupt Enable Register, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	675	__IO uint32_t ISR; /!< LTDC Interrupt Status Register, Address offset: 0x38 /
Kojto	107:4f6c30876dfa	676	__IO uint32_t ICR; /!< LTDC Interrupt Clear Register, Address offset: 0x3C /
Kojto	107:4f6c30876dfa	677	__IO uint32_t LIPCR; /!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 /
Kojto	107:4f6c30876dfa	678	__IO uint32_t CPSR; /!< LTDC Current Position Status Register, Address offset: 0x44 /
Kojto	107:4f6c30876dfa	679	__IO uint32_t CDSR; /!< LTDC Current Display Status Register, Address offset: 0x48 /
Kojto	107:4f6c30876dfa	680	} LTDC_TypeDef;
Kojto	107:4f6c30876dfa	681
Kojto	107:4f6c30876dfa	682	/**
Kojto	107:4f6c30876dfa	683	* @brief LCD-TFT Display layer x Controller
Kojto	107:4f6c30876dfa	684	*/
Kojto	107:4f6c30876dfa	685
Kojto	107:4f6c30876dfa	686	typedef struct
Kojto	107:4f6c30876dfa	687	{
Kojto	107:4f6c30876dfa	688	__IO uint32_t CR; /!< LTDC Layerx Control Register Address offset: 0x84 /
Kojto	107:4f6c30876dfa	689	__IO uint32_t WHPCR; /!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 /
Kojto	107:4f6c30876dfa	690	__IO uint32_t WVPCR; /!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C /
Kojto	107:4f6c30876dfa	691	__IO uint32_t CKCR; /!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 /
Kojto	107:4f6c30876dfa	692	__IO uint32_t PFCR; /!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 /
Kojto	107:4f6c30876dfa	693	__IO uint32_t CACR; /!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 /
Kojto	107:4f6c30876dfa	694	__IO uint32_t DCCR; /!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C /
Kojto	107:4f6c30876dfa	695	__IO uint32_t BFCR; /!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 /
Kojto	107:4f6c30876dfa	696	uint32_t RESERVED0[2]; /!< Reserved /
Kojto	107:4f6c30876dfa	697	__IO uint32_t CFBAR; /!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC /
Kojto	107:4f6c30876dfa	698	__IO uint32_t CFBLR; /!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 /
Kojto	107:4f6c30876dfa	699	__IO uint32_t CFBLNR; /!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 /
Kojto	107:4f6c30876dfa	700	uint32_t RESERVED1[3]; /!< Reserved /
Kojto	116:c0f6e94411f5	701	__IO uint32_t CLUTWR; /!< LTDC Layerx CLUT Write Register Address offset: 0x144 /
Kojto	107:4f6c30876dfa	702
Kojto	107:4f6c30876dfa	703	} LTDC_Layer_TypeDef;
Kojto	107:4f6c30876dfa	704
Kojto	107:4f6c30876dfa	705	/**
Kojto	107:4f6c30876dfa	706	* @brief Power Control
Kojto	107:4f6c30876dfa	707	*/
Kojto	107:4f6c30876dfa	708
Kojto	107:4f6c30876dfa	709	typedef struct
Kojto	107:4f6c30876dfa	710	{
Kojto	107:4f6c30876dfa	711	__IO uint32_t CR1; /!< PWR power control register 1, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	712	__IO uint32_t CSR1; /!< PWR power control/status register 2, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	713	__IO uint32_t CR2; /!< PWR power control register 2, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	714	__IO uint32_t CSR2; /!< PWR power control/status register 2, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	715	} PWR_TypeDef;
Kojto	107:4f6c30876dfa	716
Kojto	107:4f6c30876dfa	717
Kojto	107:4f6c30876dfa	718	/**
Kojto	107:4f6c30876dfa	719	* @brief Reset and Clock Control
Kojto	107:4f6c30876dfa	720	*/
Kojto	107:4f6c30876dfa	721
Kojto	107:4f6c30876dfa	722	typedef struct
Kojto	107:4f6c30876dfa	723	{
Kojto	107:4f6c30876dfa	724	__IO uint32_t CR; /!< RCC clock control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	725	__IO uint32_t PLLCFGR; /!< RCC PLL configuration register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	726	__IO uint32_t CFGR; /!< RCC clock configuration register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	727	__IO uint32_t CIR; /!< RCC clock interrupt register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	728	__IO uint32_t AHB1RSTR; /!< RCC AHB1 peripheral reset register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	729	__IO uint32_t AHB2RSTR; /!< RCC AHB2 peripheral reset register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	730	__IO uint32_t AHB3RSTR; /!< RCC AHB3 peripheral reset register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	731	uint32_t RESERVED0; /!< Reserved, 0x1C /
Kojto	107:4f6c30876dfa	732	__IO uint32_t APB1RSTR; /!< RCC APB1 peripheral reset register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	733	__IO uint32_t APB2RSTR; /!< RCC APB2 peripheral reset register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	734	uint32_t RESERVED1[2]; /!< Reserved, 0x28-0x2C /
Kojto	107:4f6c30876dfa	735	__IO uint32_t AHB1ENR; /!< RCC AHB1 peripheral clock register, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	736	__IO uint32_t AHB2ENR; /!< RCC AHB2 peripheral clock register, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	737	__IO uint32_t AHB3ENR; /!< RCC AHB3 peripheral clock register, Address offset: 0x38 /
Kojto	107:4f6c30876dfa	738	uint32_t RESERVED2; /!< Reserved, 0x3C /
Kojto	107:4f6c30876dfa	739	__IO uint32_t APB1ENR; /!< RCC APB1 peripheral clock enable register, Address offset: 0x40 /
Kojto	107:4f6c30876dfa	740	__IO uint32_t APB2ENR; /!< RCC APB2 peripheral clock enable register, Address offset: 0x44 /
Kojto	107:4f6c30876dfa	741	uint32_t RESERVED3[2]; /!< Reserved, 0x48-0x4C /
Kojto	107:4f6c30876dfa	742	__IO uint32_t AHB1LPENR; /!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 /
Kojto	107:4f6c30876dfa	743	__IO uint32_t AHB2LPENR; /!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 /
Kojto	107:4f6c30876dfa	744	__IO uint32_t AHB3LPENR; /!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 /
Kojto	107:4f6c30876dfa	745	uint32_t RESERVED4; /!< Reserved, 0x5C /
Kojto	107:4f6c30876dfa	746	__IO uint32_t APB1LPENR; /!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 /
Kojto	107:4f6c30876dfa	747	__IO uint32_t APB2LPENR; /!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 /
Kojto	107:4f6c30876dfa	748	uint32_t RESERVED5[2]; /!< Reserved, 0x68-0x6C /
Kojto	107:4f6c30876dfa	749	__IO uint32_t BDCR; /!< RCC Backup domain control register, Address offset: 0x70 /
Kojto	107:4f6c30876dfa	750	__IO uint32_t CSR; /!< RCC clock control & status register, Address offset: 0x74 /
Kojto	107:4f6c30876dfa	751	uint32_t RESERVED6[2]; /!< Reserved, 0x78-0x7C /
Kojto	107:4f6c30876dfa	752	__IO uint32_t SSCGR; /!< RCC spread spectrum clock generation register, Address offset: 0x80 /
Kojto	107:4f6c30876dfa	753	__IO uint32_t PLLI2SCFGR; /!< RCC PLLI2S configuration register, Address offset: 0x84 /
Kojto	107:4f6c30876dfa	754	__IO uint32_t PLLSAICFGR; /!< RCC PLLSAI configuration register, Address offset: 0x88 /
Kojto	107:4f6c30876dfa	755	__IO uint32_t DCKCFGR1; /!< RCC Dedicated Clocks configuration register1, Address offset: 0x8C /
Kojto	107:4f6c30876dfa	756	__IO uint32_t DCKCFGR2; /!< RCC Dedicated Clocks configuration register 2, Address offset: 0x90 /
Kojto	107:4f6c30876dfa	757
Kojto	107:4f6c30876dfa	758	} RCC_TypeDef;
Kojto	107:4f6c30876dfa	759
Kojto	107:4f6c30876dfa	760	/**
Kojto	107:4f6c30876dfa	761	* @brief Real-Time Clock
Kojto	107:4f6c30876dfa	762	*/
Kojto	107:4f6c30876dfa	763
Kojto	107:4f6c30876dfa	764	typedef struct
Kojto	107:4f6c30876dfa	765	{
Kojto	107:4f6c30876dfa	766	__IO uint32_t TR; /!< RTC time register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	767	__IO uint32_t DR; /!< RTC date register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	768	__IO uint32_t CR; /!< RTC control register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	769	__IO uint32_t ISR; /!< RTC initialization and status register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	770	__IO uint32_t PRER; /!< RTC prescaler register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	771	__IO uint32_t WUTR; /!< RTC wakeup timer register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	772	uint32_t reserved; /!< Reserved /
Kojto	107:4f6c30876dfa	773	__IO uint32_t ALRMAR; /!< RTC alarm A register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	774	__IO uint32_t ALRMBR; /!< RTC alarm B register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	775	__IO uint32_t WPR; /!< RTC write protection register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	776	__IO uint32_t SSR; /!< RTC sub second register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	777	__IO uint32_t SHIFTR; /!< RTC shift control register, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	778	__IO uint32_t TSTR; /!< RTC time stamp time register, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	779	__IO uint32_t TSDR; /!< RTC time stamp date register, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	780	__IO uint32_t TSSSR; /!< RTC time-stamp sub second register, Address offset: 0x38 /
Kojto	107:4f6c30876dfa	781	__IO uint32_t CALR; /!< RTC calibration register, Address offset: 0x3C /
Kojto	107:4f6c30876dfa	782	__IO uint32_t TAMPCR; /!< RTC tamper configuration register, Address offset: 0x40 /
Kojto	107:4f6c30876dfa	783	__IO uint32_t ALRMASSR; /!< RTC alarm A sub second register, Address offset: 0x44 /
Kojto	107:4f6c30876dfa	784	__IO uint32_t ALRMBSSR; /!< RTC alarm B sub second register, Address offset: 0x48 /
Kojto	107:4f6c30876dfa	785	__IO uint32_t OR; /!< RTC option register, Address offset: 0x4C /
Kojto	107:4f6c30876dfa	786	__IO uint32_t BKP0R; /!< RTC backup register 0, Address offset: 0x50 /
Kojto	107:4f6c30876dfa	787	__IO uint32_t BKP1R; /!< RTC backup register 1, Address offset: 0x54 /
Kojto	107:4f6c30876dfa	788	__IO uint32_t BKP2R; /!< RTC backup register 2, Address offset: 0x58 /
Kojto	107:4f6c30876dfa	789	__IO uint32_t BKP3R; /!< RTC backup register 3, Address offset: 0x5C /
Kojto	107:4f6c30876dfa	790	__IO uint32_t BKP4R; /!< RTC backup register 4, Address offset: 0x60 /
Kojto	107:4f6c30876dfa	791	__IO uint32_t BKP5R; /!< RTC backup register 5, Address offset: 0x64 /
Kojto	107:4f6c30876dfa	792	__IO uint32_t BKP6R; /!< RTC backup register 6, Address offset: 0x68 /
Kojto	107:4f6c30876dfa	793	__IO uint32_t BKP7R; /!< RTC backup register 7, Address offset: 0x6C /
Kojto	107:4f6c30876dfa	794	__IO uint32_t BKP8R; /!< RTC backup register 8, Address offset: 0x70 /
Kojto	107:4f6c30876dfa	795	__IO uint32_t BKP9R; /!< RTC backup register 9, Address offset: 0x74 /
Kojto	107:4f6c30876dfa	796	__IO uint32_t BKP10R; /!< RTC backup register 10, Address offset: 0x78 /
Kojto	107:4f6c30876dfa	797	__IO uint32_t BKP11R; /!< RTC backup register 11, Address offset: 0x7C /
Kojto	107:4f6c30876dfa	798	__IO uint32_t BKP12R; /!< RTC backup register 12, Address offset: 0x80 /
Kojto	107:4f6c30876dfa	799	__IO uint32_t BKP13R; /!< RTC backup register 13, Address offset: 0x84 /
Kojto	107:4f6c30876dfa	800	__IO uint32_t BKP14R; /!< RTC backup register 14, Address offset: 0x88 /
Kojto	107:4f6c30876dfa	801	__IO uint32_t BKP15R; /!< RTC backup register 15, Address offset: 0x8C /
Kojto	107:4f6c30876dfa	802	__IO uint32_t BKP16R; /!< RTC backup register 16, Address offset: 0x90 /
Kojto	107:4f6c30876dfa	803	__IO uint32_t BKP17R; /!< RTC backup register 17, Address offset: 0x94 /
Kojto	107:4f6c30876dfa	804	__IO uint32_t BKP18R; /!< RTC backup register 18, Address offset: 0x98 /
Kojto	107:4f6c30876dfa	805	__IO uint32_t BKP19R; /!< RTC backup register 19, Address offset: 0x9C /
Kojto	107:4f6c30876dfa	806	__IO uint32_t BKP20R; /!< RTC backup register 20, Address offset: 0xA0 /
Kojto	107:4f6c30876dfa	807	__IO uint32_t BKP21R; /!< RTC backup register 21, Address offset: 0xA4 /
Kojto	107:4f6c30876dfa	808	__IO uint32_t BKP22R; /!< RTC backup register 22, Address offset: 0xA8 /
Kojto	107:4f6c30876dfa	809	__IO uint32_t BKP23R; /!< RTC backup register 23, Address offset: 0xAC /
Kojto	107:4f6c30876dfa	810	__IO uint32_t BKP24R; /!< RTC backup register 24, Address offset: 0xB0 /
Kojto	107:4f6c30876dfa	811	__IO uint32_t BKP25R; /!< RTC backup register 25, Address offset: 0xB4 /
Kojto	107:4f6c30876dfa	812	__IO uint32_t BKP26R; /!< RTC backup register 26, Address offset: 0xB8 /
Kojto	107:4f6c30876dfa	813	__IO uint32_t BKP27R; /!< RTC backup register 27, Address offset: 0xBC /
Kojto	107:4f6c30876dfa	814	__IO uint32_t BKP28R; /!< RTC backup register 28, Address offset: 0xC0 /
Kojto	107:4f6c30876dfa	815	__IO uint32_t BKP29R; /!< RTC backup register 29, Address offset: 0xC4 /
Kojto	107:4f6c30876dfa	816	__IO uint32_t BKP30R; /!< RTC backup register 30, Address offset: 0xC8 /
Kojto	107:4f6c30876dfa	817	__IO uint32_t BKP31R; /!< RTC backup register 31, Address offset: 0xCC /
Kojto	107:4f6c30876dfa	818	} RTC_TypeDef;
Kojto	107:4f6c30876dfa	819
Kojto	107:4f6c30876dfa	820
Kojto	107:4f6c30876dfa	821	/**
Kojto	107:4f6c30876dfa	822	* @brief Serial Audio Interface
Kojto	107:4f6c30876dfa	823	*/
Kojto	107:4f6c30876dfa	824
Kojto	107:4f6c30876dfa	825	typedef struct
Kojto	107:4f6c30876dfa	826	{
Kojto	107:4f6c30876dfa	827	__IO uint32_t GCR; /!< SAI global configuration register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	828	} SAI_TypeDef;
Kojto	107:4f6c30876dfa	829
Kojto	107:4f6c30876dfa	830	typedef struct
Kojto	107:4f6c30876dfa	831	{
Kojto	107:4f6c30876dfa	832	__IO uint32_t CR1; /!< SAI block x configuration register 1, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	833	__IO uint32_t CR2; /!< SAI block x configuration register 2, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	834	__IO uint32_t FRCR; /!< SAI block x frame configuration register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	835	__IO uint32_t SLOTR; /!< SAI block x slot register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	836	__IO uint32_t IMR; /!< SAI block x interrupt mask register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	837	__IO uint32_t SR; /!< SAI block x status register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	838	__IO uint32_t CLRFR; /!< SAI block x clear flag register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	839	__IO uint32_t DR; /!< SAI block x data register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	840	} SAI_Block_TypeDef;
Kojto	107:4f6c30876dfa	841
Kojto	107:4f6c30876dfa	842	/**
Kojto	107:4f6c30876dfa	843	* @brief SPDIF-RX Interface
Kojto	107:4f6c30876dfa	844	*/
Kojto	107:4f6c30876dfa	845
Kojto	107:4f6c30876dfa	846	typedef struct
Kojto	107:4f6c30876dfa	847	{
Kojto	107:4f6c30876dfa	848	__IO uint32_t CR; /!< Control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	849	__IO uint32_t IMR; /!< Interrupt mask register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	850	__IO uint32_t SR; /!< Status register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	851	__IO uint32_t IFCR; /!< Interrupt Flag Clear register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	852	__IO uint32_t DR; /!< Data input register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	853	__IO uint32_t CSR; /!< Channel Status register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	854	__IO uint32_t DIR; /!< Debug Information register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	855	} SPDIFRX_TypeDef;
Kojto	107:4f6c30876dfa	856
Kojto	107:4f6c30876dfa	857
Kojto	107:4f6c30876dfa	858	/**
Kojto	107:4f6c30876dfa	859	* @brief SD host Interface
Kojto	107:4f6c30876dfa	860	*/
Kojto	107:4f6c30876dfa	861
Kojto	107:4f6c30876dfa	862	typedef struct
Kojto	107:4f6c30876dfa	863	{
Kojto	107:4f6c30876dfa	864	__IO uint32_t POWER; /!< SDMMC power control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	865	__IO uint32_t CLKCR; /!< SDMMClock control register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	866	__IO uint32_t ARG; /!< SDMMC argument register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	867	__IO uint32_t CMD; /!< SDMMC command register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	868	__I uint32_t RESPCMD; /!< SDMMC command response register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	869	__I uint32_t RESP1; /!< SDMMC response 1 register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	870	__I uint32_t RESP2; /!< SDMMC response 2 register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	871	__I uint32_t RESP3; /!< SDMMC response 3 register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	872	__I uint32_t RESP4; /!< SDMMC response 4 register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	873	__IO uint32_t DTIMER; /!< SDMMC data timer register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	874	__IO uint32_t DLEN; /!< SDMMC data length register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	875	__IO uint32_t DCTRL; /!< SDMMC data control register, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	876	__I uint32_t DCOUNT; /!< SDMMC data counter register, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	877	__I uint32_t STA; /!< SDMMC status register, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	878	__IO uint32_t ICR; /!< SDMMC interrupt clear register, Address offset: 0x38 /
Kojto	107:4f6c30876dfa	879	__IO uint32_t MASK; /!< SDMMC mask register, Address offset: 0x3C /
Kojto	107:4f6c30876dfa	880	uint32_t RESERVED0[2]; /!< Reserved, 0x40-0x44 /
Kojto	107:4f6c30876dfa	881	__I uint32_t FIFOCNT; /!< SDMMC FIFO counter register, Address offset: 0x48 /
Kojto	107:4f6c30876dfa	882	uint32_t RESERVED1[13]; /!< Reserved, 0x4C-0x7C /
Kojto	107:4f6c30876dfa	883	__IO uint32_t FIFO; /!< SDMMC data FIFO register, Address offset: 0x80 /
Kojto	107:4f6c30876dfa	884	} SDMMC_TypeDef;
Kojto	107:4f6c30876dfa	885
Kojto	107:4f6c30876dfa	886	/**
Kojto	107:4f6c30876dfa	887	* @brief Serial Peripheral Interface
Kojto	107:4f6c30876dfa	888	*/
Kojto	107:4f6c30876dfa	889
Kojto	107:4f6c30876dfa	890	typedef struct
Kojto	107:4f6c30876dfa	891	{
Kojto	107:4f6c30876dfa	892	__IO uint32_t CR1; /!< SPI control register 1 (not used in I2S mode), Address offset: 0x00 /
Kojto	107:4f6c30876dfa	893	__IO uint32_t CR2; /!< SPI control register 2, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	894	__IO uint32_t SR; /!< SPI status register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	895	__IO uint32_t DR; /!< SPI data register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	896	__IO uint32_t CRCPR; /!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 /
Kojto	107:4f6c30876dfa	897	__IO uint32_t RXCRCR; /!< SPI RX CRC register (not used in I2S mode), Address offset: 0x14 /
Kojto	107:4f6c30876dfa	898	__IO uint32_t TXCRCR; /!< SPI TX CRC register (not used in I2S mode), Address offset: 0x18 /
Kojto	107:4f6c30876dfa	899	__IO uint32_t I2SCFGR; /!< SPI_I2S configuration register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	900	__IO uint32_t I2SPR; /!< SPI_I2S prescaler register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	901	} SPI_TypeDef;
Kojto	107:4f6c30876dfa	902
Kojto	107:4f6c30876dfa	903	/**
Kojto	107:4f6c30876dfa	904	* @brief QUAD Serial Peripheral Interface
Kojto	107:4f6c30876dfa	905	*/
Kojto	107:4f6c30876dfa	906
Kojto	107:4f6c30876dfa	907	typedef struct
Kojto	107:4f6c30876dfa	908	{
Kojto	107:4f6c30876dfa	909	__IO uint32_t CR; /!< QUADSPI Control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	910	__IO uint32_t DCR; /!< QUADSPI Device Configuration register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	911	__IO uint32_t SR; /!< QUADSPI Status register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	912	__IO uint32_t FCR; /!< QUADSPI Flag Clear register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	913	__IO uint32_t DLR; /!< QUADSPI Data Length register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	914	__IO uint32_t CCR; /!< QUADSPI Communication Configuration register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	915	__IO uint32_t AR; /!< QUADSPI Address register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	916	__IO uint32_t ABR; /!< QUADSPI Alternate Bytes register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	917	__IO uint32_t DR; /!< QUADSPI Data register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	918	__IO uint32_t PSMKR; /!< QUADSPI Polling Status Mask register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	919	__IO uint32_t PSMAR; /!< QUADSPI Polling Status Match register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	920	__IO uint32_t PIR; /!< QUADSPI Polling Interval register, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	921	__IO uint32_t LPTR; /!< QUADSPI Low Power Timeout register, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	922	} QUADSPI_TypeDef;
Kojto	107:4f6c30876dfa	923
Kojto	107:4f6c30876dfa	924	/**
Kojto	107:4f6c30876dfa	925	* @brief TIM
Kojto	107:4f6c30876dfa	926	*/
Kojto	107:4f6c30876dfa	927
Kojto	107:4f6c30876dfa	928	typedef struct
Kojto	107:4f6c30876dfa	929	{
Kojto	107:4f6c30876dfa	930	__IO uint32_t CR1; /!< TIM control register 1, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	931	__IO uint32_t CR2; /!< TIM control register 2, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	932	__IO uint32_t SMCR; /!< TIM slave mode control register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	933	__IO uint32_t DIER; /!< TIM DMA/interrupt enable register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	934	__IO uint32_t SR; /!< TIM status register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	935	__IO uint32_t EGR; /!< TIM event generation register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	936	__IO uint32_t CCMR1; /!< TIM capture/compare mode register 1, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	937	__IO uint32_t CCMR2; /!< TIM capture/compare mode register 2, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	938	__IO uint32_t CCER; /!< TIM capture/compare enable register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	939	__IO uint32_t CNT; /!< TIM counter register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	940	__IO uint32_t PSC; /!< TIM prescaler, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	941	__IO uint32_t ARR; /!< TIM auto-reload register, Address offset: 0x2C /
Kojto	107:4f6c30876dfa	942	__IO uint32_t RCR; /!< TIM repetition counter register, Address offset: 0x30 /
Kojto	107:4f6c30876dfa	943	__IO uint32_t CCR1; /!< TIM capture/compare register 1, Address offset: 0x34 /
Kojto	107:4f6c30876dfa	944	__IO uint32_t CCR2; /!< TIM capture/compare register 2, Address offset: 0x38 /
Kojto	107:4f6c30876dfa	945	__IO uint32_t CCR3; /!< TIM capture/compare register 3, Address offset: 0x3C /
Kojto	107:4f6c30876dfa	946	__IO uint32_t CCR4; /!< TIM capture/compare register 4, Address offset: 0x40 /
Kojto	107:4f6c30876dfa	947	__IO uint32_t BDTR; /!< TIM break and dead-time register, Address offset: 0x44 /
Kojto	107:4f6c30876dfa	948	__IO uint32_t DCR; /!< TIM DMA control register, Address offset: 0x48 /
Kojto	107:4f6c30876dfa	949	__IO uint32_t DMAR; /!< TIM DMA address for full transfer, Address offset: 0x4C /
Kojto	107:4f6c30876dfa	950	__IO uint32_t OR; /!< TIM option register, Address offset: 0x50 /
Kojto	107:4f6c30876dfa	951	__IO uint32_t CCMR3; /!< TIM capture/compare mode register 3, Address offset: 0x54 /
Kojto	107:4f6c30876dfa	952	__IO uint32_t CCR5; /!< TIM capture/compare mode register5, Address offset: 0x58 /
Kojto	107:4f6c30876dfa	953	__IO uint32_t CCR6; /!< TIM capture/compare mode register6, Address offset: 0x5C /
Kojto	107:4f6c30876dfa	954
Kojto	107:4f6c30876dfa	955	} TIM_TypeDef;
Kojto	107:4f6c30876dfa	956
Kojto	107:4f6c30876dfa	957	/**
Kojto	107:4f6c30876dfa	958	* @brief LPTIMIMER
Kojto	107:4f6c30876dfa	959	*/
Kojto	107:4f6c30876dfa	960	typedef struct
Kojto	107:4f6c30876dfa	961	{
Kojto	107:4f6c30876dfa	962	__IO uint32_t ISR; /!< LPTIM Interrupt and Status register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	963	__IO uint32_t ICR; /!< LPTIM Interrupt Clear register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	964	__IO uint32_t IER; /!< LPTIM Interrupt Enable register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	965	__IO uint32_t CFGR; /!< LPTIM Configuration register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	966	__IO uint32_t CR; /!< LPTIM Control register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	967	__IO uint32_t CMP; /!< LPTIM Compare register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	968	__IO uint32_t ARR; /!< LPTIM Autoreload register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	969	__IO uint32_t CNT; /!< LPTIM Counter register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	970	} LPTIM_TypeDef;
Kojto	107:4f6c30876dfa	971
Kojto	107:4f6c30876dfa	972
Kojto	107:4f6c30876dfa	973	/**
Kojto	107:4f6c30876dfa	974	* @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto	107:4f6c30876dfa	975	*/
Kojto	107:4f6c30876dfa	976
Kojto	107:4f6c30876dfa	977	typedef struct
Kojto	107:4f6c30876dfa	978	{
Kojto	107:4f6c30876dfa	979	__IO uint32_t CR1; /!< USART Control register 1, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	980	__IO uint32_t CR2; /!< USART Control register 2, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	981	__IO uint32_t CR3; /!< USART Control register 3, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	982	__IO uint32_t BRR; /!< USART Baud rate register, Address offset: 0x0C /
Kojto	107:4f6c30876dfa	983	__IO uint32_t GTPR; /!< USART Guard time and prescaler register, Address offset: 0x10 /
Kojto	107:4f6c30876dfa	984	__IO uint32_t RTOR; /!< USART Receiver Time Out register, Address offset: 0x14 /
Kojto	107:4f6c30876dfa	985	__IO uint32_t RQR; /!< USART Request register, Address offset: 0x18 /
Kojto	107:4f6c30876dfa	986	__IO uint32_t ISR; /!< USART Interrupt and status register, Address offset: 0x1C /
Kojto	107:4f6c30876dfa	987	__IO uint32_t ICR; /!< USART Interrupt flag Clear register, Address offset: 0x20 /
Kojto	107:4f6c30876dfa	988	__IO uint32_t RDR; /!< USART Receive Data register, Address offset: 0x24 /
Kojto	107:4f6c30876dfa	989	__IO uint32_t TDR; /!< USART Transmit Data register, Address offset: 0x28 /
Kojto	107:4f6c30876dfa	990	} USART_TypeDef;
Kojto	107:4f6c30876dfa	991
Kojto	107:4f6c30876dfa	992
Kojto	107:4f6c30876dfa	993	/**
Kojto	107:4f6c30876dfa	994	* @brief Window WATCHDOG
Kojto	107:4f6c30876dfa	995	*/
Kojto	107:4f6c30876dfa	996
Kojto	107:4f6c30876dfa	997	typedef struct
Kojto	107:4f6c30876dfa	998	{
Kojto	107:4f6c30876dfa	999	__IO uint32_t CR; /!< WWDG Control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	1000	__IO uint32_t CFR; /!< WWDG Configuration register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	1001	__IO uint32_t SR; /!< WWDG Status register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	1002	} WWDG_TypeDef;
Kojto	107:4f6c30876dfa	1003
Kojto	116:c0f6e94411f5	1004
Kojto	107:4f6c30876dfa	1005	/**
Kojto	107:4f6c30876dfa	1006	* @brief RNG
Kojto	107:4f6c30876dfa	1007	*/
Kojto	107:4f6c30876dfa	1008
Kojto	107:4f6c30876dfa	1009	typedef struct
Kojto	107:4f6c30876dfa	1010	{
Kojto	107:4f6c30876dfa	1011	__IO uint32_t CR; /!< RNG control register, Address offset: 0x00 /
Kojto	107:4f6c30876dfa	1012	__IO uint32_t SR; /!< RNG status register, Address offset: 0x04 /
Kojto	107:4f6c30876dfa	1013	__IO uint32_t DR; /!< RNG data register, Address offset: 0x08 /
Kojto	107:4f6c30876dfa	1014	} RNG_TypeDef;
Kojto	107:4f6c30876dfa	1015
Kojto	107:4f6c30876dfa	1016	/**
Kojto	107:4f6c30876dfa	1017	* @}
Kojto	107:4f6c30876dfa	1018	*/
Kojto	107:4f6c30876dfa	1019
Kojto	107:4f6c30876dfa	1020	/**
Kojto	107:4f6c30876dfa	1021	* @brief USB_OTG_Core_Registers
Kojto	107:4f6c30876dfa	1022	*/
Kojto	107:4f6c30876dfa	1023	typedef struct
Kojto	107:4f6c30876dfa	1024	{
Kojto	107:4f6c30876dfa	1025	__IO uint32_t GOTGCTL; /!< USB_OTG Control and Status Register 000h /
Kojto	107:4f6c30876dfa	1026	__IO uint32_t GOTGINT; /!< USB_OTG Interrupt Register 004h /
Kojto	107:4f6c30876dfa	1027	__IO uint32_t GAHBCFG; /!< Core AHB Configuration Register 008h /
Kojto	107:4f6c30876dfa	1028	__IO uint32_t GUSBCFG; /!< Core USB Configuration Register 00Ch /
Kojto	107:4f6c30876dfa	1029	__IO uint32_t GRSTCTL; /!< Core Reset Register 010h /
Kojto	107:4f6c30876dfa	1030	__IO uint32_t GINTSTS; /!< Core Interrupt Register 014h /
Kojto	107:4f6c30876dfa	1031	__IO uint32_t GINTMSK; /!< Core Interrupt Mask Register 018h /
Kojto	107:4f6c30876dfa	1032	__IO uint32_t GRXSTSR; /!< Receive Sts Q Read Register 01Ch /
Kojto	107:4f6c30876dfa	1033	__IO uint32_t GRXSTSP; /!< Receive Sts Q Read & POP Register 020h /
Kojto	107:4f6c30876dfa	1034	__IO uint32_t GRXFSIZ; /!< Receive FIFO Size Register 024h /
Kojto	107:4f6c30876dfa	1035	__IO uint32_t DIEPTXF0_HNPTXFSIZ; /!< EP0 / Non Periodic Tx FIFO Size Register 028h /
Kojto	107:4f6c30876dfa	1036	__IO uint32_t HNPTXSTS; /!< Non Periodic Tx FIFO/Queue Sts reg 02Ch /
Kojto	107:4f6c30876dfa	1037	uint32_t Reserved30[2]; /!< Reserved 030h /
Kojto	107:4f6c30876dfa	1038	__IO uint32_t GCCFG; /!< General Purpose IO Register 038h /
Kojto	107:4f6c30876dfa	1039	__IO uint32_t CID; /!< User ID Register 03Ch /
Kojto	107:4f6c30876dfa	1040	uint32_t Reserved5[3]; /!< Reserved 040h-048h /
Kojto	107:4f6c30876dfa	1041	__IO uint32_t GHWCFG3; /!< User HW config3 04Ch /
Kojto	107:4f6c30876dfa	1042	uint32_t Reserved6; /!< Reserved 050h /
Kojto	107:4f6c30876dfa	1043	__IO uint32_t GLPMCFG; /!< LPM Register 054h /
Kojto	107:4f6c30876dfa	1044	__IO uint32_t GPWRDN; /!< Power Down Register 058h /
Kojto	107:4f6c30876dfa	1045	__IO uint32_t GDFIFOCFG; /!< DFIFO Software Config Register 05Ch /
Kojto	107:4f6c30876dfa	1046	__IO uint32_t GADPCTL; /!< ADP Timer, Control and Status Register 60Ch /
Kojto	107:4f6c30876dfa	1047	uint32_t Reserved43[39]; /!< Reserved 058h-0FFh /
Kojto	107:4f6c30876dfa	1048	__IO uint32_t HPTXFSIZ; /!< Host Periodic Tx FIFO Size Reg 100h /
Kojto	107:4f6c30876dfa	1049	__IO uint32_t DIEPTXF[0x0F]; /!< dev Periodic Transmit FIFO /
Kojto	107:4f6c30876dfa	1050	} USB_OTG_GlobalTypeDef;
Kojto	107:4f6c30876dfa	1051
Kojto	107:4f6c30876dfa	1052
Kojto	107:4f6c30876dfa	1053	/**
Kojto	107:4f6c30876dfa	1054	* @brief USB_OTG_device_Registers
Kojto	107:4f6c30876dfa	1055	*/
Kojto	107:4f6c30876dfa	1056	typedef struct
Kojto	107:4f6c30876dfa	1057	{
Kojto	107:4f6c30876dfa	1058	__IO uint32_t DCFG; /!< dev Configuration Register 800h /
Kojto	107:4f6c30876dfa	1059	__IO uint32_t DCTL; /!< dev Control Register 804h /
Kojto	107:4f6c30876dfa	1060	__IO uint32_t DSTS; /!< dev Status Register (RO) 808h /
Kojto	107:4f6c30876dfa	1061	uint32_t Reserved0C; /!< Reserved 80Ch /
Kojto	107:4f6c30876dfa	1062	__IO uint32_t DIEPMSK; /!< dev IN Endpoint Mask 810h /
Kojto	107:4f6c30876dfa	1063	__IO uint32_t DOEPMSK; /!< dev OUT Endpoint Mask 814h /
Kojto	107:4f6c30876dfa	1064	__IO uint32_t DAINT; /!< dev All Endpoints Itr Reg 818h /
Kojto	107:4f6c30876dfa	1065	__IO uint32_t DAINTMSK; /!< dev All Endpoints Itr Mask 81Ch /
Kojto	107:4f6c30876dfa	1066	uint32_t Reserved20; /!< Reserved 820h /
Kojto	107:4f6c30876dfa	1067	uint32_t Reserved9; /!< Reserved 824h /
Kojto	107:4f6c30876dfa	1068	__IO uint32_t DVBUSDIS; /!< dev VBUS discharge Register 828h /
Kojto	107:4f6c30876dfa	1069	__IO uint32_t DVBUSPULSE; /!< dev VBUS Pulse Register 82Ch /
Kojto	107:4f6c30876dfa	1070	__IO uint32_t DTHRCTL; /!< dev threshold 830h /
Kojto	107:4f6c30876dfa	1071	__IO uint32_t DIEPEMPMSK; /!< dev empty msk 834h /
Kojto	107:4f6c30876dfa	1072	__IO uint32_t DEACHINT; /!< dedicated EP interrupt 838h /
Kojto	107:4f6c30876dfa	1073	__IO uint32_t DEACHMSK; /!< dedicated EP msk 83Ch /
Kojto	107:4f6c30876dfa	1074	uint32_t Reserved40; /!< dedicated EP mask 840h /
Kojto	107:4f6c30876dfa	1075	__IO uint32_t DINEP1MSK; /!< dedicated EP mask 844h /
Kojto	107:4f6c30876dfa	1076	uint32_t Reserved44[15]; /!< Reserved 844-87Ch /
Kojto	107:4f6c30876dfa	1077	__IO uint32_t DOUTEP1MSK; /!< dedicated EP msk 884h /
Kojto	107:4f6c30876dfa	1078	} USB_OTG_DeviceTypeDef;
Kojto	107:4f6c30876dfa	1079
Kojto	107:4f6c30876dfa	1080
Kojto	107:4f6c30876dfa	1081	/**
Kojto	107:4f6c30876dfa	1082	* @brief USB_OTG_IN_Endpoint-Specific_Register
Kojto	107:4f6c30876dfa	1083	*/
Kojto	107:4f6c30876dfa	1084	typedef struct
Kojto	107:4f6c30876dfa	1085	{
Kojto	107:4f6c30876dfa	1086	__IO uint32_t DIEPCTL; /!< dev IN Endpoint Control Reg 900h + (ep_num 20h) + 00h */
Kojto	107:4f6c30876dfa	1087	uint32_t Reserved04; /!< Reserved 900h + (ep_num 20h) + 04h */
Kojto	107:4f6c30876dfa	1088	__IO uint32_t DIEPINT; /!< dev IN Endpoint Itr Reg 900h + (ep_num 20h) + 08h */
Kojto	107:4f6c30876dfa	1089	uint32_t Reserved0C; /!< Reserved 900h + (ep_num 20h) + 0Ch */
Kojto	107:4f6c30876dfa	1090	__IO uint32_t DIEPTSIZ; /!< IN Endpoint Txfer Size 900h + (ep_num 20h) + 10h */
Kojto	107:4f6c30876dfa	1091	__IO uint32_t DIEPDMA; /!< IN Endpoint DMA Address Reg 900h + (ep_num 20h) + 14h */
Kojto	107:4f6c30876dfa	1092	__IO uint32_t DTXFSTS; /!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num 20h) + 18h */
Kojto	107:4f6c30876dfa	1093	uint32_t Reserved18; /!< Reserved 900h+(ep_num20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
Kojto	107:4f6c30876dfa	1094	} USB_OTG_INEndpointTypeDef;
Kojto	107:4f6c30876dfa	1095
Kojto	107:4f6c30876dfa	1096
Kojto	107:4f6c30876dfa	1097	/**
Kojto	107:4f6c30876dfa	1098	* @brief USB_OTG_OUT_Endpoint-Specific_Registers
Kojto	107:4f6c30876dfa	1099	*/
Kojto	107:4f6c30876dfa	1100	typedef struct
Kojto	107:4f6c30876dfa	1101	{
Kojto	107:4f6c30876dfa	1102	__IO uint32_t DOEPCTL; /!< dev OUT Endpoint Control Reg B00h + (ep_num 20h) + 00h */
Kojto	107:4f6c30876dfa	1103	uint32_t Reserved04; /!< Reserved B00h + (ep_num 20h) + 04h */
Kojto	107:4f6c30876dfa	1104	__IO uint32_t DOEPINT; /!< dev OUT Endpoint Itr Reg B00h + (ep_num 20h) + 08h */
Kojto	107:4f6c30876dfa	1105	uint32_t Reserved0C; /!< Reserved B00h + (ep_num 20h) + 0Ch */
Kojto	107:4f6c30876dfa	1106	__IO uint32_t DOEPTSIZ; /!< dev OUT Endpoint Txfer Size B00h + (ep_num 20h) + 10h */
Kojto	107:4f6c30876dfa	1107	__IO uint32_t DOEPDMA; /!< dev OUT Endpoint DMA Address B00h + (ep_num 20h) + 14h */
Kojto	107:4f6c30876dfa	1108	uint32_t Reserved18[2]; /!< Reserved B00h + (ep_num 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
Kojto	107:4f6c30876dfa	1109	} USB_OTG_OUTEndpointTypeDef;
Kojto	107:4f6c30876dfa	1110
Kojto	107:4f6c30876dfa	1111
Kojto	107:4f6c30876dfa	1112	/**
Kojto	107:4f6c30876dfa	1113	* @brief USB_OTG_Host_Mode_Register_Structures
Kojto	107:4f6c30876dfa	1114	*/
Kojto	107:4f6c30876dfa	1115	typedef struct
Kojto	107:4f6c30876dfa	1116	{
Kojto	107:4f6c30876dfa	1117	__IO uint32_t HCFG; /!< Host Configuration Register 400h /
Kojto	107:4f6c30876dfa	1118	__IO uint32_t HFIR; /!< Host Frame Interval Register 404h /
Kojto	107:4f6c30876dfa	1119	__IO uint32_t HFNUM; /!< Host Frame Nbr/Frame Remaining 408h /
Kojto	107:4f6c30876dfa	1120	uint32_t Reserved40C; /!< Reserved 40Ch /
Kojto	107:4f6c30876dfa	1121	__IO uint32_t HPTXSTS; /!< Host Periodic Tx FIFO/ Queue Status 410h /
Kojto	107:4f6c30876dfa	1122	__IO uint32_t HAINT; /!< Host All Channels Interrupt Register 414h /
Kojto	107:4f6c30876dfa	1123	__IO uint32_t HAINTMSK; /!< Host All Channels Interrupt Mask 418h /
Kojto	107:4f6c30876dfa	1124	} USB_OTG_HostTypeDef;
Kojto	107:4f6c30876dfa	1125
Kojto	107:4f6c30876dfa	1126	/**
Kojto	107:4f6c30876dfa	1127	* @brief USB_OTG_Host_Channel_Specific_Registers
Kojto	107:4f6c30876dfa	1128	*/
Kojto	107:4f6c30876dfa	1129	typedef struct
Kojto	107:4f6c30876dfa	1130	{
Kojto	107:4f6c30876dfa	1131	__IO uint32_t HCCHAR; /!< Host Channel Characteristics Register 500h /
Kojto	107:4f6c30876dfa	1132	__IO uint32_t HCSPLT; /!< Host Channel Split Control Register 504h /
Kojto	107:4f6c30876dfa	1133	__IO uint32_t HCINT; /!< Host Channel Interrupt Register 508h /
Kojto	107:4f6c30876dfa	1134	__IO uint32_t HCINTMSK; /!< Host Channel Interrupt Mask Register 50Ch /
Kojto	107:4f6c30876dfa	1135	__IO uint32_t HCTSIZ; /!< Host Channel Transfer Size Register 510h /
Kojto	107:4f6c30876dfa	1136	__IO uint32_t HCDMA; /!< Host Channel DMA Address Register 514h /
Kojto	107:4f6c30876dfa	1137	uint32_t Reserved[2]; /!< Reserved /
Kojto	107:4f6c30876dfa	1138	} USB_OTG_HostChannelTypeDef;
Kojto	107:4f6c30876dfa	1139	/**
Kojto	107:4f6c30876dfa	1140	* @}
Kojto	107:4f6c30876dfa	1141	*/
Kojto	107:4f6c30876dfa	1142
Kojto	116:c0f6e94411f5	1143
Kojto	116:c0f6e94411f5	1144
Kojto	122:f9eeca106725	1145
Kojto	107:4f6c30876dfa	1146	/** @addtogroup Peripheral_memory_map
Kojto	107:4f6c30876dfa	1147	* @{
Kojto	107:4f6c30876dfa	1148	*/
Kojto	122:f9eeca106725	1149	#define RAMITCM_BASE 0x00000000U /!< Base address of : 16KB RAM reserved for CPU execution/instruction accessible over ITCM /
Kojto	122:f9eeca106725	1150	#define FLASHITCM_BASE 0x00200000U /!< Base address of : (up to 1 MB) embedded FLASH memory accessible over ITCM /
Kojto	122:f9eeca106725	1151	#define FLASHAXI_BASE 0x08000000U /!< Base address of : (up to 1 MB) embedded FLASH memory accessible over AXI /
Kojto	122:f9eeca106725	1152	#define RAMDTCM_BASE 0x20000000U /!< Base address of : 64KB system data RAM accessible over DTCM /
Kojto	122:f9eeca106725	1153	#define PERIPH_BASE 0x40000000U /!< Base address of : AHB/ABP Peripherals /
Kojto	122:f9eeca106725	1154	#define BKPSRAM_BASE 0x40024000U /!< Base address of : Backup SRAM(4 KB) /
Kojto	122:f9eeca106725	1155	#define QSPI_BASE 0x90000000U /!< Base address of : QSPI memories accessible over AXI /
Kojto	122:f9eeca106725	1156	#define FMC_R_BASE 0xA0000000U /!< Base address of : FMC Control registers /
Kojto	122:f9eeca106725	1157	#define QSPI_R_BASE 0xA0001000U /!< Base address of : QSPI Control registers /
Kojto	122:f9eeca106725	1158	#define SRAM1_BASE 0x20010000U /!< Base address of : 240KB RAM1 accessible over AXI/AHB /
Kojto	122:f9eeca106725	1159	#define SRAM2_BASE 0x2004C000U /!< Base address of : 16KB RAM2 accessible over AXI/AHB /
Kojto	122:f9eeca106725	1160	#define FLASH_END 0x080FFFFFU /!< FLASH end address /
Kojto	107:4f6c30876dfa	1161
Kojto	107:4f6c30876dfa	1162	/* Legacy define */
Kojto	107:4f6c30876dfa	1163	#define FLASH_BASE FLASHAXI_BASE
Kojto	107:4f6c30876dfa	1164
Kojto	107:4f6c30876dfa	1165	/!< Peripheral memory map /
Kojto	107:4f6c30876dfa	1166	#define APB1PERIPH_BASE PERIPH_BASE
Kojto	122:f9eeca106725	1167	#define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000U)
Kojto	122:f9eeca106725	1168	#define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000U)
Kojto	122:f9eeca106725	1169	#define AHB2PERIPH_BASE (PERIPH_BASE + 0x10000000U)
Kojto	107:4f6c30876dfa	1170
Kojto	107:4f6c30876dfa	1171	/!< APB1 peripherals /
Kojto	122:f9eeca106725	1172	#define TIM2_BASE (APB1PERIPH_BASE + 0x0000U)
Kojto	122:f9eeca106725	1173	#define TIM3_BASE (APB1PERIPH_BASE + 0x0400U)
Kojto	122:f9eeca106725	1174	#define TIM4_BASE (APB1PERIPH_BASE + 0x0800U)
Kojto	122:f9eeca106725	1175	#define TIM5_BASE (APB1PERIPH_BASE + 0x0C00U)
Kojto	122:f9eeca106725	1176	#define TIM6_BASE (APB1PERIPH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1177	#define TIM7_BASE (APB1PERIPH_BASE + 0x1400U)
Kojto	122:f9eeca106725	1178	#define TIM12_BASE (APB1PERIPH_BASE + 0x1800U)
Kojto	122:f9eeca106725	1179	#define TIM13_BASE (APB1PERIPH_BASE + 0x1C00U)
Kojto	122:f9eeca106725	1180	#define TIM14_BASE (APB1PERIPH_BASE + 0x2000U)
Kojto	122:f9eeca106725	1181	#define LPTIM1_BASE (APB1PERIPH_BASE + 0x2400U)
Kojto	122:f9eeca106725	1182	#define RTC_BASE (APB1PERIPH_BASE + 0x2800U)
Kojto	122:f9eeca106725	1183	#define WWDG_BASE (APB1PERIPH_BASE + 0x2C00U)
Kojto	122:f9eeca106725	1184	#define IWDG_BASE (APB1PERIPH_BASE + 0x3000U)
Kojto	122:f9eeca106725	1185	#define SPI2_BASE (APB1PERIPH_BASE + 0x3800U)
Kojto	122:f9eeca106725	1186	#define SPI3_BASE (APB1PERIPH_BASE + 0x3C00U)
Kojto	122:f9eeca106725	1187	#define SPDIFRX_BASE (APB1PERIPH_BASE + 0x4000U)
Kojto	122:f9eeca106725	1188	#define USART2_BASE (APB1PERIPH_BASE + 0x4400U)
Kojto	122:f9eeca106725	1189	#define USART3_BASE (APB1PERIPH_BASE + 0x4800U)
Kojto	122:f9eeca106725	1190	#define UART4_BASE (APB1PERIPH_BASE + 0x4C00U)
Kojto	122:f9eeca106725	1191	#define UART5_BASE (APB1PERIPH_BASE + 0x5000U)
Kojto	122:f9eeca106725	1192	#define I2C1_BASE (APB1PERIPH_BASE + 0x5400U)
Kojto	122:f9eeca106725	1193	#define I2C2_BASE (APB1PERIPH_BASE + 0x5800U)
Kojto	122:f9eeca106725	1194	#define I2C3_BASE (APB1PERIPH_BASE + 0x5C00U)
Kojto	122:f9eeca106725	1195	#define I2C4_BASE (APB1PERIPH_BASE + 0x6000U)
Kojto	122:f9eeca106725	1196	#define CAN1_BASE (APB1PERIPH_BASE + 0x6400U)
Kojto	122:f9eeca106725	1197	#define CAN2_BASE (APB1PERIPH_BASE + 0x6800U)
Kojto	122:f9eeca106725	1198	#define CEC_BASE (APB1PERIPH_BASE + 0x6C00U)
Kojto	122:f9eeca106725	1199	#define PWR_BASE (APB1PERIPH_BASE + 0x7000U)
Kojto	122:f9eeca106725	1200	#define DAC_BASE (APB1PERIPH_BASE + 0x7400U)
Kojto	122:f9eeca106725	1201	#define UART7_BASE (APB1PERIPH_BASE + 0x7800U)
Kojto	122:f9eeca106725	1202	#define UART8_BASE (APB1PERIPH_BASE + 0x7C00U)
Kojto	107:4f6c30876dfa	1203
Kojto	107:4f6c30876dfa	1204	/!< APB2 peripherals /
Kojto	122:f9eeca106725	1205	#define TIM1_BASE (APB2PERIPH_BASE + 0x0000U)
Kojto	122:f9eeca106725	1206	#define TIM8_BASE (APB2PERIPH_BASE + 0x0400U)
Kojto	122:f9eeca106725	1207	#define USART1_BASE (APB2PERIPH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1208	#define USART6_BASE (APB2PERIPH_BASE + 0x1400U)
Kojto	122:f9eeca106725	1209	#define ADC1_BASE (APB2PERIPH_BASE + 0x2000U)
Kojto	122:f9eeca106725	1210	#define ADC2_BASE (APB2PERIPH_BASE + 0x2100U)
Kojto	122:f9eeca106725	1211	#define ADC3_BASE (APB2PERIPH_BASE + 0x2200U)
Kojto	122:f9eeca106725	1212	#define ADC_BASE (APB2PERIPH_BASE + 0x2300U)
Kojto	122:f9eeca106725	1213	#define SDMMC1_BASE (APB2PERIPH_BASE + 0x2C00U)
Kojto	122:f9eeca106725	1214	#define SPI1_BASE (APB2PERIPH_BASE + 0x3000U)
Kojto	122:f9eeca106725	1215	#define SPI4_BASE (APB2PERIPH_BASE + 0x3400U)
Kojto	122:f9eeca106725	1216	#define SYSCFG_BASE (APB2PERIPH_BASE + 0x3800U)
Kojto	122:f9eeca106725	1217	#define EXTI_BASE (APB2PERIPH_BASE + 0x3C00U)
Kojto	122:f9eeca106725	1218	#define TIM9_BASE (APB2PERIPH_BASE + 0x4000U)
Kojto	122:f9eeca106725	1219	#define TIM10_BASE (APB2PERIPH_BASE + 0x4400U)
Kojto	122:f9eeca106725	1220	#define TIM11_BASE (APB2PERIPH_BASE + 0x4800U)
Kojto	122:f9eeca106725	1221	#define SPI5_BASE (APB2PERIPH_BASE + 0x5000U)
Kojto	122:f9eeca106725	1222	#define SPI6_BASE (APB2PERIPH_BASE + 0x5400U)
Kojto	122:f9eeca106725	1223	#define SAI1_BASE (APB2PERIPH_BASE + 0x5800U)
Kojto	122:f9eeca106725	1224	#define SAI2_BASE (APB2PERIPH_BASE + 0x5C00U)
Kojto	122:f9eeca106725	1225	#define SAI1_Block_A_BASE (SAI1_BASE + 0x004U)
Kojto	122:f9eeca106725	1226	#define SAI1_Block_B_BASE (SAI1_BASE + 0x024U)
Kojto	122:f9eeca106725	1227	#define SAI2_Block_A_BASE (SAI2_BASE + 0x004U)
Kojto	122:f9eeca106725	1228	#define SAI2_Block_B_BASE (SAI2_BASE + 0x024U)
Kojto	122:f9eeca106725	1229	#define LTDC_BASE (APB2PERIPH_BASE + 0x6800U)
Kojto	122:f9eeca106725	1230	#define LTDC_Layer1_BASE (LTDC_BASE + 0x84U)
Kojto	122:f9eeca106725	1231	#define LTDC_Layer2_BASE (LTDC_BASE + 0x104U)
Kojto	107:4f6c30876dfa	1232	/!< AHB1 peripherals /
Kojto	122:f9eeca106725	1233	#define GPIOA_BASE (AHB1PERIPH_BASE + 0x0000U)
Kojto	122:f9eeca106725	1234	#define GPIOB_BASE (AHB1PERIPH_BASE + 0x0400U)
Kojto	122:f9eeca106725	1235	#define GPIOC_BASE (AHB1PERIPH_BASE + 0x0800U)
Kojto	122:f9eeca106725	1236	#define GPIOD_BASE (AHB1PERIPH_BASE + 0x0C00U)
Kojto	122:f9eeca106725	1237	#define GPIOE_BASE (AHB1PERIPH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1238	#define GPIOF_BASE (AHB1PERIPH_BASE + 0x1400U)
Kojto	122:f9eeca106725	1239	#define GPIOG_BASE (AHB1PERIPH_BASE + 0x1800U)
Kojto	122:f9eeca106725	1240	#define GPIOH_BASE (AHB1PERIPH_BASE + 0x1C00U)
Kojto	122:f9eeca106725	1241	#define GPIOI_BASE (AHB1PERIPH_BASE + 0x2000U)
Kojto	122:f9eeca106725	1242	#define GPIOJ_BASE (AHB1PERIPH_BASE + 0x2400U)
Kojto	122:f9eeca106725	1243	#define GPIOK_BASE (AHB1PERIPH_BASE + 0x2800U)
Kojto	122:f9eeca106725	1244	#define CRC_BASE (AHB1PERIPH_BASE + 0x3000U)
Kojto	122:f9eeca106725	1245	#define RCC_BASE (AHB1PERIPH_BASE + 0x3800U)
Kojto	122:f9eeca106725	1246	#define FLASH_R_BASE (AHB1PERIPH_BASE + 0x3C00U)
Kojto	122:f9eeca106725	1247	#define UID_BASE 0x1FF0F420U /!< Unique device ID register base address /
Kojto	122:f9eeca106725	1248	#define FLASHSIZE_BASE 0x1FF0F442U /!< FLASH Size register base address /
Kojto	122:f9eeca106725	1249	#define PACKAGESIZE_BASE 0x1FFF7BF0U /!< Package size register base address /
Kojto	122:f9eeca106725	1250	#define DMA1_BASE (AHB1PERIPH_BASE + 0x6000U)
Kojto	122:f9eeca106725	1251	#define DMA1_Stream0_BASE (DMA1_BASE + 0x010U)
Kojto	122:f9eeca106725	1252	#define DMA1_Stream1_BASE (DMA1_BASE + 0x028U)
Kojto	122:f9eeca106725	1253	#define DMA1_Stream2_BASE (DMA1_BASE + 0x040U)
Kojto	122:f9eeca106725	1254	#define DMA1_Stream3_BASE (DMA1_BASE + 0x058U)
Kojto	122:f9eeca106725	1255	#define DMA1_Stream4_BASE (DMA1_BASE + 0x070U)
Kojto	122:f9eeca106725	1256	#define DMA1_Stream5_BASE (DMA1_BASE + 0x088U)
Kojto	122:f9eeca106725	1257	#define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0U)
Kojto	122:f9eeca106725	1258	#define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8U)
Kojto	122:f9eeca106725	1259	#define DMA2_BASE (AHB1PERIPH_BASE + 0x6400U)
Kojto	122:f9eeca106725	1260	#define DMA2_Stream0_BASE (DMA2_BASE + 0x010U)
Kojto	122:f9eeca106725	1261	#define DMA2_Stream1_BASE (DMA2_BASE + 0x028U)
Kojto	122:f9eeca106725	1262	#define DMA2_Stream2_BASE (DMA2_BASE + 0x040U)
Kojto	122:f9eeca106725	1263	#define DMA2_Stream3_BASE (DMA2_BASE + 0x058U)
Kojto	122:f9eeca106725	1264	#define DMA2_Stream4_BASE (DMA2_BASE + 0x070U)
Kojto	122:f9eeca106725	1265	#define DMA2_Stream5_BASE (DMA2_BASE + 0x088U)
Kojto	122:f9eeca106725	1266	#define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0U)
Kojto	122:f9eeca106725	1267	#define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8U)
Kojto	122:f9eeca106725	1268	#define ETH_BASE (AHB1PERIPH_BASE + 0x8000U)
Kojto	107:4f6c30876dfa	1269	#define ETH_MAC_BASE (ETH_BASE)
Kojto	122:f9eeca106725	1270	#define ETH_MMC_BASE (ETH_BASE + 0x0100U)
Kojto	122:f9eeca106725	1271	#define ETH_PTP_BASE (ETH_BASE + 0x0700U)
Kojto	122:f9eeca106725	1272	#define ETH_DMA_BASE (ETH_BASE + 0x1000U)
Kojto	122:f9eeca106725	1273	#define DMA2D_BASE (AHB1PERIPH_BASE + 0xB000U)
Kojto	107:4f6c30876dfa	1274	/!< AHB2 peripherals /
Kojto	122:f9eeca106725	1275	#define DCMI_BASE (AHB2PERIPH_BASE + 0x50000U)
Kojto	122:f9eeca106725	1276	#define RNG_BASE (AHB2PERIPH_BASE + 0x60800U)
Kojto	107:4f6c30876dfa	1277	/!< FMC Bankx registers base address /
Kojto	122:f9eeca106725	1278	#define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000U)
Kojto	122:f9eeca106725	1279	#define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104U)
Kojto	122:f9eeca106725	1280	#define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080U)
Kojto	122:f9eeca106725	1281	#define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140U)
Kojto	107:4f6c30876dfa	1282
Kojto	107:4f6c30876dfa	1283	/* Debug MCU registers base address */
Kojto	122:f9eeca106725	1284	#define DBGMCU_BASE 0xE0042000U
Kojto	107:4f6c30876dfa	1285
Kojto	107:4f6c30876dfa	1286	/!< USB registers base address /
Kojto	122:f9eeca106725	1287	#define USB_OTG_HS_PERIPH_BASE 0x40040000U
Kojto	122:f9eeca106725	1288	#define USB_OTG_FS_PERIPH_BASE 0x50000000U
Kojto	122:f9eeca106725	1289
Kojto	122:f9eeca106725	1290	#define USB_OTG_GLOBAL_BASE 0x000U
Kojto	122:f9eeca106725	1291	#define USB_OTG_DEVICE_BASE 0x800U
Kojto	122:f9eeca106725	1292	#define USB_OTG_IN_ENDPOINT_BASE 0x900U
Kojto	122:f9eeca106725	1293	#define USB_OTG_OUT_ENDPOINT_BASE 0xB00U
Kojto	122:f9eeca106725	1294	#define USB_OTG_EP_REG_SIZE 0x20U
Kojto	122:f9eeca106725	1295	#define USB_OTG_HOST_BASE 0x400U
Kojto	122:f9eeca106725	1296	#define USB_OTG_HOST_PORT_BASE 0x440U
Kojto	122:f9eeca106725	1297	#define USB_OTG_HOST_CHANNEL_BASE 0x500U
Kojto	122:f9eeca106725	1298	#define USB_OTG_HOST_CHANNEL_SIZE 0x20U
Kojto	122:f9eeca106725	1299	#define USB_OTG_PCGCCTL_BASE 0xE00U
Kojto	122:f9eeca106725	1300	#define USB_OTG_FIFO_BASE 0x1000U
Kojto	122:f9eeca106725	1301	#define USB_OTG_FIFO_SIZE 0x1000U
Kojto	107:4f6c30876dfa	1302
Kojto	107:4f6c30876dfa	1303	/**
Kojto	107:4f6c30876dfa	1304	* @}
Kojto	107:4f6c30876dfa	1305	*/
Kojto	107:4f6c30876dfa	1306
Kojto	107:4f6c30876dfa	1307	/** @addtogroup Peripheral_declaration
Kojto	107:4f6c30876dfa	1308	* @{
Kojto	107:4f6c30876dfa	1309	*/
Kojto	107:4f6c30876dfa	1310	#define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto	107:4f6c30876dfa	1311	#define TIM3 ((TIM_TypeDef *) TIM3_BASE)
Kojto	107:4f6c30876dfa	1312	#define TIM4 ((TIM_TypeDef *) TIM4_BASE)
Kojto	107:4f6c30876dfa	1313	#define TIM5 ((TIM_TypeDef *) TIM5_BASE)
Kojto	107:4f6c30876dfa	1314	#define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto	107:4f6c30876dfa	1315	#define TIM7 ((TIM_TypeDef *) TIM7_BASE)
Kojto	107:4f6c30876dfa	1316	#define TIM12 ((TIM_TypeDef *) TIM12_BASE)
Kojto	107:4f6c30876dfa	1317	#define TIM13 ((TIM_TypeDef *) TIM13_BASE)
Kojto	107:4f6c30876dfa	1318	#define TIM14 ((TIM_TypeDef *) TIM14_BASE)
Kojto	107:4f6c30876dfa	1319	#define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
Kojto	107:4f6c30876dfa	1320	#define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto	107:4f6c30876dfa	1321	#define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto	107:4f6c30876dfa	1322	#define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto	107:4f6c30876dfa	1323	#define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto	107:4f6c30876dfa	1324	#define SPI3 ((SPI_TypeDef *) SPI3_BASE)
Kojto	107:4f6c30876dfa	1325	#define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
Kojto	107:4f6c30876dfa	1326	#define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto	107:4f6c30876dfa	1327	#define USART3 ((USART_TypeDef *) USART3_BASE)
Kojto	107:4f6c30876dfa	1328	#define UART4 ((USART_TypeDef *) UART4_BASE)
Kojto	107:4f6c30876dfa	1329	#define UART5 ((USART_TypeDef *) UART5_BASE)
Kojto	107:4f6c30876dfa	1330	#define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto	107:4f6c30876dfa	1331	#define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto	107:4f6c30876dfa	1332	#define I2C3 ((I2C_TypeDef *) I2C3_BASE)
Kojto	107:4f6c30876dfa	1333	#define I2C4 ((I2C_TypeDef *) I2C4_BASE)
Kojto	107:4f6c30876dfa	1334	#define CAN1 ((CAN_TypeDef *) CAN1_BASE)
Kojto	107:4f6c30876dfa	1335	#define CAN2 ((CAN_TypeDef *) CAN2_BASE)
Kojto	107:4f6c30876dfa	1336	#define CEC ((CEC_TypeDef *) CEC_BASE)
Kojto	107:4f6c30876dfa	1337	#define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto	107:4f6c30876dfa	1338	#define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto	107:4f6c30876dfa	1339	#define UART7 ((USART_TypeDef *) UART7_BASE)
Kojto	107:4f6c30876dfa	1340	#define UART8 ((USART_TypeDef *) UART8_BASE)
Kojto	107:4f6c30876dfa	1341	#define TIM1 ((TIM_TypeDef *) TIM1_BASE)
Kojto	107:4f6c30876dfa	1342	#define TIM8 ((TIM_TypeDef *) TIM8_BASE)
Kojto	107:4f6c30876dfa	1343	#define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto	107:4f6c30876dfa	1344	#define USART6 ((USART_TypeDef *) USART6_BASE)
Kojto	107:4f6c30876dfa	1345	#define ADC ((ADC_Common_TypeDef *) ADC_BASE)
Kojto	107:4f6c30876dfa	1346	#define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto	107:4f6c30876dfa	1347	#define ADC2 ((ADC_TypeDef *) ADC2_BASE)
Kojto	107:4f6c30876dfa	1348	#define ADC3 ((ADC_TypeDef *) ADC3_BASE)
Kojto	107:4f6c30876dfa	1349	#define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
Kojto	107:4f6c30876dfa	1350	#define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto	107:4f6c30876dfa	1351	#define SPI4 ((SPI_TypeDef *) SPI4_BASE)
Kojto	107:4f6c30876dfa	1352	#define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto	107:4f6c30876dfa	1353	#define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto	107:4f6c30876dfa	1354	#define TIM9 ((TIM_TypeDef *) TIM9_BASE)
Kojto	107:4f6c30876dfa	1355	#define TIM10 ((TIM_TypeDef *) TIM10_BASE)
Kojto	107:4f6c30876dfa	1356	#define TIM11 ((TIM_TypeDef *) TIM11_BASE)
Kojto	107:4f6c30876dfa	1357	#define SPI5 ((SPI_TypeDef *) SPI5_BASE)
Kojto	107:4f6c30876dfa	1358	#define SPI6 ((SPI_TypeDef *) SPI6_BASE)
Kojto	107:4f6c30876dfa	1359	#define SAI1 ((SAI_TypeDef *) SAI1_BASE)
Kojto	107:4f6c30876dfa	1360	#define SAI2 ((SAI_TypeDef *) SAI2_BASE)
Kojto	107:4f6c30876dfa	1361	#define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
Kojto	107:4f6c30876dfa	1362	#define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
Kojto	107:4f6c30876dfa	1363	#define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
Kojto	107:4f6c30876dfa	1364	#define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
Kojto	107:4f6c30876dfa	1365	#define LTDC ((LTDC_TypeDef *)LTDC_BASE)
Kojto	107:4f6c30876dfa	1366	#define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
Kojto	107:4f6c30876dfa	1367	#define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
Kojto	107:4f6c30876dfa	1368	#define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto	107:4f6c30876dfa	1369	#define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto	107:4f6c30876dfa	1370	#define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto	107:4f6c30876dfa	1371	#define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto	107:4f6c30876dfa	1372	#define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
Kojto	107:4f6c30876dfa	1373	#define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
Kojto	107:4f6c30876dfa	1374	#define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
Kojto	107:4f6c30876dfa	1375	#define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto	107:4f6c30876dfa	1376	#define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
Kojto	107:4f6c30876dfa	1377	#define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
Kojto	107:4f6c30876dfa	1378	#define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
Kojto	107:4f6c30876dfa	1379	#define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto	107:4f6c30876dfa	1380	#define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto	107:4f6c30876dfa	1381	#define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto	107:4f6c30876dfa	1382	#define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto	107:4f6c30876dfa	1383	#define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
Kojto	107:4f6c30876dfa	1384	#define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
Kojto	107:4f6c30876dfa	1385	#define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
Kojto	107:4f6c30876dfa	1386	#define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
Kojto	107:4f6c30876dfa	1387	#define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
Kojto	107:4f6c30876dfa	1388	#define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
Kojto	107:4f6c30876dfa	1389	#define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
Kojto	107:4f6c30876dfa	1390	#define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
Kojto	107:4f6c30876dfa	1391	#define DMA2 ((DMA_TypeDef *) DMA2_BASE)
Kojto	107:4f6c30876dfa	1392	#define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
Kojto	107:4f6c30876dfa	1393	#define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
Kojto	107:4f6c30876dfa	1394	#define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
Kojto	107:4f6c30876dfa	1395	#define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
Kojto	107:4f6c30876dfa	1396	#define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
Kojto	107:4f6c30876dfa	1397	#define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
Kojto	107:4f6c30876dfa	1398	#define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
Kojto	107:4f6c30876dfa	1399	#define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
Kojto	107:4f6c30876dfa	1400	#define ETH ((ETH_TypeDef *) ETH_BASE)
Kojto	107:4f6c30876dfa	1401	#define DMA2D ((DMA2D_TypeDef *)DMA2D_BASE)
Kojto	107:4f6c30876dfa	1402	#define DCMI ((DCMI_TypeDef *) DCMI_BASE)
Kojto	107:4f6c30876dfa	1403	#define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto	107:4f6c30876dfa	1404	#define FMC_Bank1 ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
Kojto	107:4f6c30876dfa	1405	#define FMC_Bank1E ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
Kojto	107:4f6c30876dfa	1406	#define FMC_Bank3 ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
Kojto	107:4f6c30876dfa	1407	#define FMC_Bank5_6 ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
Kojto	107:4f6c30876dfa	1408	#define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
Kojto	107:4f6c30876dfa	1409	#define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto	107:4f6c30876dfa	1410	#define USB_OTG_FS ((USB_OTG_GlobalTypeDef *) USB_OTG_FS_PERIPH_BASE)
Kojto	107:4f6c30876dfa	1411	#define USB_OTG_HS ((USB_OTG_GlobalTypeDef *) USB_OTG_HS_PERIPH_BASE)
Kojto	107:4f6c30876dfa	1412
Kojto	107:4f6c30876dfa	1413	/**
Kojto	107:4f6c30876dfa	1414	* @}
Kojto	107:4f6c30876dfa	1415	*/
Kojto	107:4f6c30876dfa	1416
Kojto	107:4f6c30876dfa	1417	/** @addtogroup Exported_constants
Kojto	107:4f6c30876dfa	1418	* @{
Kojto	107:4f6c30876dfa	1419	*/
Kojto	107:4f6c30876dfa	1420
Kojto	107:4f6c30876dfa	1421	/** @addtogroup Peripheral_Registers_Bits_Definition
Kojto	107:4f6c30876dfa	1422	* @{
Kojto	107:4f6c30876dfa	1423	*/
Kojto	107:4f6c30876dfa	1424
Kojto	107:4f6c30876dfa	1425	/******************************************************************************/
Kojto	107:4f6c30876dfa	1426	/* Peripheral Registers_Bits_Definition */
Kojto	107:4f6c30876dfa	1427	/******************************************************************************/
Kojto	107:4f6c30876dfa	1428
Kojto	107:4f6c30876dfa	1429	/******************************************************************************/
Kojto	107:4f6c30876dfa	1430	/* */
Kojto	107:4f6c30876dfa	1431	/* Analog to Digital Converter */
Kojto	107:4f6c30876dfa	1432	/* */
Kojto	107:4f6c30876dfa	1433	/******************************************************************************/
Kojto	107:4f6c30876dfa	1434	/****************** Bit definition for ADC_SR register ******************/
Kojto	122:f9eeca106725	1435	#define ADC_SR_AWD 0x00000001U /!<Analog watchdog flag /
Kojto	122:f9eeca106725	1436	#define ADC_SR_EOC 0x00000002U /!<End of conversion /
Kojto	122:f9eeca106725	1437	#define ADC_SR_JEOC 0x00000004U /!<Injected channel end of conversion /
Kojto	122:f9eeca106725	1438	#define ADC_SR_JSTRT 0x00000008U /!<Injected channel Start flag /
Kojto	122:f9eeca106725	1439	#define ADC_SR_STRT 0x00000010U /!<Regular channel Start flag /
Kojto	122:f9eeca106725	1440	#define ADC_SR_OVR 0x00000020U /!<Overrun flag /
Kojto	107:4f6c30876dfa	1441
Kojto	107:4f6c30876dfa	1442	/***************** Bit definition for ADC_CR1 register ******************/
Kojto	122:f9eeca106725	1443	#define ADC_CR1_AWDCH 0x0000001FU /!<AWDCH[4:0] bits (Analog watchdog channel select bits) /
Kojto	122:f9eeca106725	1444	#define ADC_CR1_AWDCH_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1445	#define ADC_CR1_AWDCH_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1446	#define ADC_CR1_AWDCH_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1447	#define ADC_CR1_AWDCH_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1448	#define ADC_CR1_AWDCH_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1449	#define ADC_CR1_EOCIE 0x00000020U /!<Interrupt enable for EOC /
Kojto	122:f9eeca106725	1450	#define ADC_CR1_AWDIE 0x00000040U /!<AAnalog Watchdog interrupt enable /
Kojto	122:f9eeca106725	1451	#define ADC_CR1_JEOCIE 0x00000080U /!<Interrupt enable for injected channels /
Kojto	122:f9eeca106725	1452	#define ADC_CR1_SCAN 0x00000100U /!<Scan mode /
Kojto	122:f9eeca106725	1453	#define ADC_CR1_AWDSGL 0x00000200U /!<Enable the watchdog on a single channel in scan mode /
Kojto	122:f9eeca106725	1454	#define ADC_CR1_JAUTO 0x00000400U /!<Automatic injected group conversion /
Kojto	122:f9eeca106725	1455	#define ADC_CR1_DISCEN 0x00000800U /!<Discontinuous mode on regular channels /
Kojto	122:f9eeca106725	1456	#define ADC_CR1_JDISCEN 0x00001000U /!<Discontinuous mode on injected channels /
Kojto	122:f9eeca106725	1457	#define ADC_CR1_DISCNUM 0x0000E000U /!<DISCNUM[2:0] bits (Discontinuous mode channel count) /
Kojto	122:f9eeca106725	1458	#define ADC_CR1_DISCNUM_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	1459	#define ADC_CR1_DISCNUM_1 0x00004000U /!<Bit 1 /
Kojto	122:f9eeca106725	1460	#define ADC_CR1_DISCNUM_2 0x00008000U /!<Bit 2 /
Kojto	122:f9eeca106725	1461	#define ADC_CR1_JAWDEN 0x00400000U /!<Analog watchdog enable on injected channels /
Kojto	122:f9eeca106725	1462	#define ADC_CR1_AWDEN 0x00800000U /!<Analog watchdog enable on regular channels /
Kojto	122:f9eeca106725	1463	#define ADC_CR1_RES 0x03000000U /!<RES[2:0] bits (Resolution) /
Kojto	122:f9eeca106725	1464	#define ADC_CR1_RES_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1465	#define ADC_CR1_RES_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1466	#define ADC_CR1_OVRIE 0x04000000U /!<overrun interrupt enable /
Kojto	107:4f6c30876dfa	1467
Kojto	107:4f6c30876dfa	1468	/***************** Bit definition for ADC_CR2 register ******************/
Kojto	122:f9eeca106725	1469	#define ADC_CR2_ADON 0x00000001U /!<A/D Converter ON / OFF /
Kojto	122:f9eeca106725	1470	#define ADC_CR2_CONT 0x00000002U /!<Continuous Conversion /
Kojto	122:f9eeca106725	1471	#define ADC_CR2_DMA 0x00000100U /!<Direct Memory access mode /
Kojto	122:f9eeca106725	1472	#define ADC_CR2_DDS 0x00000200U /!<DMA disable selection (Single ADC) /
Kojto	122:f9eeca106725	1473	#define ADC_CR2_EOCS 0x00000400U /!<End of conversion selection /
Kojto	122:f9eeca106725	1474	#define ADC_CR2_ALIGN 0x00000800U /!<Data Alignment /
Kojto	122:f9eeca106725	1475	#define ADC_CR2_JEXTSEL 0x000F0000U /!<JEXTSEL[3:0] bits (External event select for injected group) /
Kojto	122:f9eeca106725	1476	#define ADC_CR2_JEXTSEL_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	1477	#define ADC_CR2_JEXTSEL_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	1478	#define ADC_CR2_JEXTSEL_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	1479	#define ADC_CR2_JEXTSEL_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	1480	#define ADC_CR2_JEXTEN 0x00300000U /!<JEXTEN[1:0] bits (External Trigger Conversion mode for injected channelsp) /
Kojto	122:f9eeca106725	1481	#define ADC_CR2_JEXTEN_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1482	#define ADC_CR2_JEXTEN_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1483	#define ADC_CR2_JSWSTART 0x00400000U /!<Start Conversion of injected channels /
Kojto	122:f9eeca106725	1484	#define ADC_CR2_EXTSEL 0x0F000000U /!<EXTSEL[3:0] bits (External Event Select for regular group) /
Kojto	122:f9eeca106725	1485	#define ADC_CR2_EXTSEL_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1486	#define ADC_CR2_EXTSEL_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1487	#define ADC_CR2_EXTSEL_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1488	#define ADC_CR2_EXTSEL_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	1489	#define ADC_CR2_EXTEN 0x30000000U /!<EXTEN[1:0] bits (External Trigger Conversion mode for regular channelsp) /
Kojto	122:f9eeca106725	1490	#define ADC_CR2_EXTEN_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1491	#define ADC_CR2_EXTEN_1 0x20000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1492	#define ADC_CR2_SWSTART 0x40000000U /!<Start Conversion of regular channels /
Kojto	107:4f6c30876dfa	1493
Kojto	107:4f6c30876dfa	1494	/**************** Bit definition for ADC_SMPR1 register *****************/
Kojto	122:f9eeca106725	1495	#define ADC_SMPR1_SMP10 0x00000007U /!<SMP10[2:0] bits (Channel 10 Sample time selection) /
Kojto	122:f9eeca106725	1496	#define ADC_SMPR1_SMP10_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1497	#define ADC_SMPR1_SMP10_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1498	#define ADC_SMPR1_SMP10_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1499	#define ADC_SMPR1_SMP11 0x00000038U /!<SMP11[2:0] bits (Channel 11 Sample time selection) /
Kojto	122:f9eeca106725	1500	#define ADC_SMPR1_SMP11_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	1501	#define ADC_SMPR1_SMP11_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	1502	#define ADC_SMPR1_SMP11_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	1503	#define ADC_SMPR1_SMP12 0x000001C0U /!<SMP12[2:0] bits (Channel 12 Sample time selection) /
Kojto	122:f9eeca106725	1504	#define ADC_SMPR1_SMP12_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	1505	#define ADC_SMPR1_SMP12_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	1506	#define ADC_SMPR1_SMP12_2 0x00000100U /!<Bit 2 /
Kojto	122:f9eeca106725	1507	#define ADC_SMPR1_SMP13 0x00000E00U /!<SMP13[2:0] bits (Channel 13 Sample time selection) /
Kojto	122:f9eeca106725	1508	#define ADC_SMPR1_SMP13_0 0x00000200U /!<Bit 0 /
Kojto	122:f9eeca106725	1509	#define ADC_SMPR1_SMP13_1 0x00000400U /!<Bit 1 /
Kojto	122:f9eeca106725	1510	#define ADC_SMPR1_SMP13_2 0x00000800U /!<Bit 2 /
Kojto	122:f9eeca106725	1511	#define ADC_SMPR1_SMP14 0x00007000U /!<SMP14[2:0] bits (Channel 14 Sample time selection) /
Kojto	122:f9eeca106725	1512	#define ADC_SMPR1_SMP14_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	1513	#define ADC_SMPR1_SMP14_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	1514	#define ADC_SMPR1_SMP14_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	1515	#define ADC_SMPR1_SMP15 0x00038000U /!<SMP15[2:0] bits (Channel 15 Sample time selection) /
Kojto	122:f9eeca106725	1516	#define ADC_SMPR1_SMP15_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1517	#define ADC_SMPR1_SMP15_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1518	#define ADC_SMPR1_SMP15_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1519	#define ADC_SMPR1_SMP16 0x001C0000U /!<SMP16[2:0] bits (Channel 16 Sample time selection) /
Kojto	122:f9eeca106725	1520	#define ADC_SMPR1_SMP16_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	1521	#define ADC_SMPR1_SMP16_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	1522	#define ADC_SMPR1_SMP16_2 0x00100000U /!<Bit 2 /
Kojto	122:f9eeca106725	1523	#define ADC_SMPR1_SMP17 0x00E00000U /!<SMP17[2:0] bits (Channel 17 Sample time selection) /
Kojto	122:f9eeca106725	1524	#define ADC_SMPR1_SMP17_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	1525	#define ADC_SMPR1_SMP17_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	1526	#define ADC_SMPR1_SMP17_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	1527	#define ADC_SMPR1_SMP18 0x07000000U /!<SMP18[2:0] bits (Channel 18 Sample time selection) /
Kojto	122:f9eeca106725	1528	#define ADC_SMPR1_SMP18_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1529	#define ADC_SMPR1_SMP18_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1530	#define ADC_SMPR1_SMP18_2 0x04000000U /!<Bit 2 /
Kojto	107:4f6c30876dfa	1531
Kojto	107:4f6c30876dfa	1532	/**************** Bit definition for ADC_SMPR2 register *****************/
Kojto	122:f9eeca106725	1533	#define ADC_SMPR2_SMP0 0x00000007U /!<SMP0[2:0] bits (Channel 0 Sample time selection) /
Kojto	122:f9eeca106725	1534	#define ADC_SMPR2_SMP0_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1535	#define ADC_SMPR2_SMP0_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1536	#define ADC_SMPR2_SMP0_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1537	#define ADC_SMPR2_SMP1 0x00000038U /!<SMP1[2:0] bits (Channel 1 Sample time selection) /
Kojto	122:f9eeca106725	1538	#define ADC_SMPR2_SMP1_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	1539	#define ADC_SMPR2_SMP1_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	1540	#define ADC_SMPR2_SMP1_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	1541	#define ADC_SMPR2_SMP2 0x000001C0U /!<SMP2[2:0] bits (Channel 2 Sample time selection) /
Kojto	122:f9eeca106725	1542	#define ADC_SMPR2_SMP2_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	1543	#define ADC_SMPR2_SMP2_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	1544	#define ADC_SMPR2_SMP2_2 0x00000100U /!<Bit 2 /
Kojto	122:f9eeca106725	1545	#define ADC_SMPR2_SMP3 0x00000E00U /!<SMP3[2:0] bits (Channel 3 Sample time selection) /
Kojto	122:f9eeca106725	1546	#define ADC_SMPR2_SMP3_0 0x00000200U /!<Bit 0 /
Kojto	122:f9eeca106725	1547	#define ADC_SMPR2_SMP3_1 0x00000400U /!<Bit 1 /
Kojto	122:f9eeca106725	1548	#define ADC_SMPR2_SMP3_2 0x00000800U /!<Bit 2 /
Kojto	122:f9eeca106725	1549	#define ADC_SMPR2_SMP4 0x00007000U /!<SMP4[2:0] bits (Channel 4 Sample time selection) /
Kojto	122:f9eeca106725	1550	#define ADC_SMPR2_SMP4_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	1551	#define ADC_SMPR2_SMP4_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	1552	#define ADC_SMPR2_SMP4_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	1553	#define ADC_SMPR2_SMP5 0x00038000U /!<SMP5[2:0] bits (Channel 5 Sample time selection) /
Kojto	122:f9eeca106725	1554	#define ADC_SMPR2_SMP5_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1555	#define ADC_SMPR2_SMP5_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1556	#define ADC_SMPR2_SMP5_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1557	#define ADC_SMPR2_SMP6 0x001C0000U /!<SMP6[2:0] bits (Channel 6 Sample time selection) /
Kojto	122:f9eeca106725	1558	#define ADC_SMPR2_SMP6_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	1559	#define ADC_SMPR2_SMP6_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	1560	#define ADC_SMPR2_SMP6_2 0x00100000U /!<Bit 2 /
Kojto	122:f9eeca106725	1561	#define ADC_SMPR2_SMP7 0x00E00000U /!<SMP7[2:0] bits (Channel 7 Sample time selection) /
Kojto	122:f9eeca106725	1562	#define ADC_SMPR2_SMP7_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	1563	#define ADC_SMPR2_SMP7_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	1564	#define ADC_SMPR2_SMP7_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	1565	#define ADC_SMPR2_SMP8 0x07000000U /!<SMP8[2:0] bits (Channel 8 Sample time selection) /
Kojto	122:f9eeca106725	1566	#define ADC_SMPR2_SMP8_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1567	#define ADC_SMPR2_SMP8_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1568	#define ADC_SMPR2_SMP8_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1569	#define ADC_SMPR2_SMP9 0x38000000U /!<SMP9[2:0] bits (Channel 9 Sample time selection) /
Kojto	122:f9eeca106725	1570	#define ADC_SMPR2_SMP9_0 0x08000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1571	#define ADC_SMPR2_SMP9_1 0x10000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1572	#define ADC_SMPR2_SMP9_2 0x20000000U /!<Bit 2 /
Kojto	107:4f6c30876dfa	1573
Kojto	107:4f6c30876dfa	1574	/**************** Bit definition for ADC_JOFR1 register *****************/
Kojto	122:f9eeca106725	1575	#define ADC_JOFR1_JOFFSET1 0x0FFFU /!<Data offset for injected channel 1 /
Kojto	107:4f6c30876dfa	1576
Kojto	107:4f6c30876dfa	1577	/**************** Bit definition for ADC_JOFR2 register *****************/
Kojto	122:f9eeca106725	1578	#define ADC_JOFR2_JOFFSET2 0x0FFFU /!<Data offset for injected channel 2 /
Kojto	107:4f6c30876dfa	1579
Kojto	107:4f6c30876dfa	1580	/**************** Bit definition for ADC_JOFR3 register *****************/
Kojto	122:f9eeca106725	1581	#define ADC_JOFR3_JOFFSET3 0x0FFFU /!<Data offset for injected channel 3 /
Kojto	107:4f6c30876dfa	1582
Kojto	107:4f6c30876dfa	1583	/**************** Bit definition for ADC_JOFR4 register *****************/
Kojto	122:f9eeca106725	1584	#define ADC_JOFR4_JOFFSET4 0x0FFFU /!<Data offset for injected channel 4 /
Kojto	107:4f6c30876dfa	1585
Kojto	107:4f6c30876dfa	1586	/***************** Bit definition for ADC_HTR register ******************/
Kojto	122:f9eeca106725	1587	#define ADC_HTR_HT 0x0FFFU /!<Analog watchdog high threshold /
Kojto	107:4f6c30876dfa	1588
Kojto	107:4f6c30876dfa	1589	/***************** Bit definition for ADC_LTR register ******************/
Kojto	122:f9eeca106725	1590	#define ADC_LTR_LT 0x0FFFU /!<Analog watchdog low threshold /
Kojto	107:4f6c30876dfa	1591
Kojto	107:4f6c30876dfa	1592	/***************** Bit definition for ADC_SQR1 register *****************/
Kojto	122:f9eeca106725	1593	#define ADC_SQR1_SQ13 0x0000001FU /!<SQ13[4:0] bits (13th conversion in regular sequence) /
Kojto	122:f9eeca106725	1594	#define ADC_SQR1_SQ13_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1595	#define ADC_SQR1_SQ13_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1596	#define ADC_SQR1_SQ13_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1597	#define ADC_SQR1_SQ13_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1598	#define ADC_SQR1_SQ13_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1599	#define ADC_SQR1_SQ14 0x000003E0U /!<SQ14[4:0] bits (14th conversion in regular sequence) /
Kojto	122:f9eeca106725	1600	#define ADC_SQR1_SQ14_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1601	#define ADC_SQR1_SQ14_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1602	#define ADC_SQR1_SQ14_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1603	#define ADC_SQR1_SQ14_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1604	#define ADC_SQR1_SQ14_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1605	#define ADC_SQR1_SQ15 0x00007C00U /!<SQ15[4:0] bits (15th conversion in regular sequence) /
Kojto	122:f9eeca106725	1606	#define ADC_SQR1_SQ15_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1607	#define ADC_SQR1_SQ15_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1608	#define ADC_SQR1_SQ15_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1609	#define ADC_SQR1_SQ15_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1610	#define ADC_SQR1_SQ15_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1611	#define ADC_SQR1_SQ16 0x000F8000U /!<SQ16[4:0] bits (16th conversion in regular sequence) /
Kojto	122:f9eeca106725	1612	#define ADC_SQR1_SQ16_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1613	#define ADC_SQR1_SQ16_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1614	#define ADC_SQR1_SQ16_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1615	#define ADC_SQR1_SQ16_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1616	#define ADC_SQR1_SQ16_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1617	#define ADC_SQR1_L 0x00F00000U /!<L[3:0] bits (Regular channel sequence length) /
Kojto	122:f9eeca106725	1618	#define ADC_SQR1_L_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1619	#define ADC_SQR1_L_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1620	#define ADC_SQR1_L_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1621	#define ADC_SQR1_L_3 0x00800000U /!<Bit 3 /
Kojto	107:4f6c30876dfa	1622
Kojto	107:4f6c30876dfa	1623	/***************** Bit definition for ADC_SQR2 register *****************/
Kojto	122:f9eeca106725	1624	#define ADC_SQR2_SQ7 0x0000001FU /!<SQ7[4:0] bits (7th conversion in regular sequence) /
Kojto	122:f9eeca106725	1625	#define ADC_SQR2_SQ7_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1626	#define ADC_SQR2_SQ7_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1627	#define ADC_SQR2_SQ7_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1628	#define ADC_SQR2_SQ7_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1629	#define ADC_SQR2_SQ7_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1630	#define ADC_SQR2_SQ8 0x000003E0U /!<SQ8[4:0] bits (8th conversion in regular sequence) /
Kojto	122:f9eeca106725	1631	#define ADC_SQR2_SQ8_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1632	#define ADC_SQR2_SQ8_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1633	#define ADC_SQR2_SQ8_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1634	#define ADC_SQR2_SQ8_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1635	#define ADC_SQR2_SQ8_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1636	#define ADC_SQR2_SQ9 0x00007C00U /!<SQ9[4:0] bits (9th conversion in regular sequence) /
Kojto	122:f9eeca106725	1637	#define ADC_SQR2_SQ9_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1638	#define ADC_SQR2_SQ9_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1639	#define ADC_SQR2_SQ9_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1640	#define ADC_SQR2_SQ9_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1641	#define ADC_SQR2_SQ9_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1642	#define ADC_SQR2_SQ10 0x000F8000U /!<SQ10[4:0] bits (10th conversion in regular sequence) /
Kojto	122:f9eeca106725	1643	#define ADC_SQR2_SQ10_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1644	#define ADC_SQR2_SQ10_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1645	#define ADC_SQR2_SQ10_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1646	#define ADC_SQR2_SQ10_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1647	#define ADC_SQR2_SQ10_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1648	#define ADC_SQR2_SQ11 0x01F00000U /!<SQ11[4:0] bits (11th conversion in regular sequence) /
Kojto	122:f9eeca106725	1649	#define ADC_SQR2_SQ11_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1650	#define ADC_SQR2_SQ11_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1651	#define ADC_SQR2_SQ11_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1652	#define ADC_SQR2_SQ11_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	1653	#define ADC_SQR2_SQ11_4 0x01000000U /!<Bit 4 /
Kojto	122:f9eeca106725	1654	#define ADC_SQR2_SQ12 0x3E000000U /!<SQ12[4:0] bits (12th conversion in regular sequence) /
Kojto	122:f9eeca106725	1655	#define ADC_SQR2_SQ12_0 0x02000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1656	#define ADC_SQR2_SQ12_1 0x04000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1657	#define ADC_SQR2_SQ12_2 0x08000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1658	#define ADC_SQR2_SQ12_3 0x10000000U /!<Bit 3 /
Kojto	122:f9eeca106725	1659	#define ADC_SQR2_SQ12_4 0x20000000U /!<Bit 4 /
Kojto	107:4f6c30876dfa	1660
Kojto	107:4f6c30876dfa	1661	/***************** Bit definition for ADC_SQR3 register *****************/
Kojto	122:f9eeca106725	1662	#define ADC_SQR3_SQ1 0x0000001FU /!<SQ1[4:0] bits (1st conversion in regular sequence) /
Kojto	122:f9eeca106725	1663	#define ADC_SQR3_SQ1_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1664	#define ADC_SQR3_SQ1_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1665	#define ADC_SQR3_SQ1_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1666	#define ADC_SQR3_SQ1_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1667	#define ADC_SQR3_SQ1_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1668	#define ADC_SQR3_SQ2 0x000003E0U /!<SQ2[4:0] bits (2nd conversion in regular sequence) /
Kojto	122:f9eeca106725	1669	#define ADC_SQR3_SQ2_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1670	#define ADC_SQR3_SQ2_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1671	#define ADC_SQR3_SQ2_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1672	#define ADC_SQR3_SQ2_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1673	#define ADC_SQR3_SQ2_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1674	#define ADC_SQR3_SQ3 0x00007C00U /!<SQ3[4:0] bits (3rd conversion in regular sequence) /
Kojto	122:f9eeca106725	1675	#define ADC_SQR3_SQ3_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1676	#define ADC_SQR3_SQ3_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1677	#define ADC_SQR3_SQ3_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1678	#define ADC_SQR3_SQ3_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1679	#define ADC_SQR3_SQ3_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1680	#define ADC_SQR3_SQ4 0x000F8000U /!<SQ4[4:0] bits (4th conversion in regular sequence) /
Kojto	122:f9eeca106725	1681	#define ADC_SQR3_SQ4_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1682	#define ADC_SQR3_SQ4_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1683	#define ADC_SQR3_SQ4_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1684	#define ADC_SQR3_SQ4_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1685	#define ADC_SQR3_SQ4_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1686	#define ADC_SQR3_SQ5 0x01F00000U /!<SQ5[4:0] bits (5th conversion in regular sequence) /
Kojto	122:f9eeca106725	1687	#define ADC_SQR3_SQ5_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1688	#define ADC_SQR3_SQ5_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1689	#define ADC_SQR3_SQ5_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1690	#define ADC_SQR3_SQ5_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	1691	#define ADC_SQR3_SQ5_4 0x01000000U /!<Bit 4 /
Kojto	122:f9eeca106725	1692	#define ADC_SQR3_SQ6 0x3E000000U /!<SQ6[4:0] bits (6th conversion in regular sequence) /
Kojto	122:f9eeca106725	1693	#define ADC_SQR3_SQ6_0 0x02000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1694	#define ADC_SQR3_SQ6_1 0x04000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1695	#define ADC_SQR3_SQ6_2 0x08000000U /!<Bit 2 /
Kojto	122:f9eeca106725	1696	#define ADC_SQR3_SQ6_3 0x10000000U /!<Bit 3 /
Kojto	122:f9eeca106725	1697	#define ADC_SQR3_SQ6_4 0x20000000U /!<Bit 4 /
Kojto	107:4f6c30876dfa	1698
Kojto	107:4f6c30876dfa	1699	/***************** Bit definition for ADC_JSQR register *****************/
Kojto	122:f9eeca106725	1700	#define ADC_JSQR_JSQ1 0x0000001FU /!<JSQ1[4:0] bits (1st conversion in injected sequence) /
Kojto	122:f9eeca106725	1701	#define ADC_JSQR_JSQ1_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1702	#define ADC_JSQR_JSQ1_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1703	#define ADC_JSQR_JSQ1_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1704	#define ADC_JSQR_JSQ1_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1705	#define ADC_JSQR_JSQ1_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1706	#define ADC_JSQR_JSQ2 0x000003E0U /!<JSQ2[4:0] bits (2nd conversion in injected sequence) /
Kojto	122:f9eeca106725	1707	#define ADC_JSQR_JSQ2_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	1708	#define ADC_JSQR_JSQ2_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	1709	#define ADC_JSQR_JSQ2_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	1710	#define ADC_JSQR_JSQ2_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	1711	#define ADC_JSQR_JSQ2_4 0x00000200U /!<Bit 4 /
Kojto	122:f9eeca106725	1712	#define ADC_JSQR_JSQ3 0x00007C00U /!<JSQ3[4:0] bits (3rd conversion in injected sequence) /
Kojto	122:f9eeca106725	1713	#define ADC_JSQR_JSQ3_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	1714	#define ADC_JSQR_JSQ3_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	1715	#define ADC_JSQR_JSQ3_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	1716	#define ADC_JSQR_JSQ3_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	1717	#define ADC_JSQR_JSQ3_4 0x00004000U /!<Bit 4 /
Kojto	122:f9eeca106725	1718	#define ADC_JSQR_JSQ4 0x000F8000U /!<JSQ4[4:0] bits (4th conversion in injected sequence) /
Kojto	122:f9eeca106725	1719	#define ADC_JSQR_JSQ4_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	1720	#define ADC_JSQR_JSQ4_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	1721	#define ADC_JSQR_JSQ4_2 0x00020000U /!<Bit 2 /
Kojto	122:f9eeca106725	1722	#define ADC_JSQR_JSQ4_3 0x00040000U /!<Bit 3 /
Kojto	122:f9eeca106725	1723	#define ADC_JSQR_JSQ4_4 0x00080000U /!<Bit 4 /
Kojto	122:f9eeca106725	1724	#define ADC_JSQR_JL 0x00300000U /!<JL[1:0] bits (Injected Sequence length) /
Kojto	122:f9eeca106725	1725	#define ADC_JSQR_JL_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1726	#define ADC_JSQR_JL_1 0x00200000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	1727
Kojto	107:4f6c30876dfa	1728	/***************** Bit definition for ADC_JDR1 register *****************/
Kojto	122:f9eeca106725	1729	#define ADC_JDR1_JDATA ((uint16_t)0xFFFFU) /!<Injected data /
Kojto	107:4f6c30876dfa	1730
Kojto	107:4f6c30876dfa	1731	/***************** Bit definition for ADC_JDR2 register *****************/
Kojto	122:f9eeca106725	1732	#define ADC_JDR2_JDATA ((uint16_t)0xFFFFU) /!<Injected data /
Kojto	107:4f6c30876dfa	1733
Kojto	107:4f6c30876dfa	1734	/***************** Bit definition for ADC_JDR3 register *****************/
Kojto	122:f9eeca106725	1735	#define ADC_JDR3_JDATA ((uint16_t)0xFFFFU) /!<Injected data /
Kojto	107:4f6c30876dfa	1736
Kojto	107:4f6c30876dfa	1737	/***************** Bit definition for ADC_JDR4 register *****************/
Kojto	122:f9eeca106725	1738	#define ADC_JDR4_JDATA ((uint16_t)0xFFFFU) /!<Injected data /
Kojto	107:4f6c30876dfa	1739
Kojto	107:4f6c30876dfa	1740	/****************** Bit definition for ADC_DR register ******************/
Kojto	122:f9eeca106725	1741	#define ADC_DR_DATA 0x0000FFFFU /!<Regular data /
Kojto	122:f9eeca106725	1742	#define ADC_DR_ADC2DATA 0xFFFF0000U /!<ADC2 data /
Kojto	107:4f6c30876dfa	1743
Kojto	107:4f6c30876dfa	1744	/***************** Bit definition for ADC_CSR register ******************/
Kojto	122:f9eeca106725	1745	#define ADC_CSR_AWD1 0x00000001U /!<ADC1 Analog watchdog flag /
Kojto	122:f9eeca106725	1746	#define ADC_CSR_EOC1 0x00000002U /!<ADC1 End of conversion /
Kojto	122:f9eeca106725	1747	#define ADC_CSR_JEOC1 0x00000004U /!<ADC1 Injected channel end of conversion /
Kojto	122:f9eeca106725	1748	#define ADC_CSR_JSTRT1 0x00000008U /!<ADC1 Injected channel Start flag /
Kojto	122:f9eeca106725	1749	#define ADC_CSR_STRT1 0x00000010U /!<ADC1 Regular channel Start flag /
Kojto	122:f9eeca106725	1750	#define ADC_CSR_OVR1 0x00000020U /!<ADC1 Overrun flag /
Kojto	122:f9eeca106725	1751	#define ADC_CSR_AWD2 0x00000100U /!<ADC2 Analog watchdog flag /
Kojto	122:f9eeca106725	1752	#define ADC_CSR_EOC2 0x00000200U /!<ADC2 End of conversion /
Kojto	122:f9eeca106725	1753	#define ADC_CSR_JEOC2 0x00000400U /!<ADC2 Injected channel end of conversion /
Kojto	122:f9eeca106725	1754	#define ADC_CSR_JSTRT2 0x00000800U /!<ADC2 Injected channel Start flag /
Kojto	122:f9eeca106725	1755	#define ADC_CSR_STRT2 0x00001000U /!<ADC2 Regular channel Start flag /
Kojto	122:f9eeca106725	1756	#define ADC_CSR_OVR2 0x00002000U /!<ADC2 Overrun flag /
Kojto	122:f9eeca106725	1757	#define ADC_CSR_AWD3 0x00010000U /!<ADC3 Analog watchdog flag /
Kojto	122:f9eeca106725	1758	#define ADC_CSR_EOC3 0x00020000U /!<ADC3 End of conversion /
Kojto	122:f9eeca106725	1759	#define ADC_CSR_JEOC3 0x00040000U /!<ADC3 Injected channel end of conversion /
Kojto	122:f9eeca106725	1760	#define ADC_CSR_JSTRT3 0x00080000U /!<ADC3 Injected channel Start flag /
Kojto	122:f9eeca106725	1761	#define ADC_CSR_STRT3 0x00100000U /!<ADC3 Regular channel Start flag /
Kojto	122:f9eeca106725	1762	#define ADC_CSR_OVR3 0x00200000U /!<ADC3 Overrun flag /
Kojto	122:f9eeca106725	1763
Kojto	122:f9eeca106725	1764	/* Legacy defines */
Kojto	122:f9eeca106725	1765	#define ADC_CSR_DOVR1 ADC_CSR_OVR1
Kojto	122:f9eeca106725	1766	#define ADC_CSR_DOVR2 ADC_CSR_OVR2
Kojto	122:f9eeca106725	1767	#define ADC_CSR_DOVR3 ADC_CSR_OVR3
Kojto	122:f9eeca106725	1768
Kojto	107:4f6c30876dfa	1769
Kojto	107:4f6c30876dfa	1770	/***************** Bit definition for ADC_CCR register ******************/
Kojto	122:f9eeca106725	1771	#define ADC_CCR_MULTI 0x0000001FU /!<MULTI[4:0] bits (Multi-ADC mode selection) /
Kojto	122:f9eeca106725	1772	#define ADC_CCR_MULTI_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	1773	#define ADC_CCR_MULTI_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	1774	#define ADC_CCR_MULTI_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	1775	#define ADC_CCR_MULTI_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	1776	#define ADC_CCR_MULTI_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	1777	#define ADC_CCR_DELAY 0x00000F00U /!<DELAY[3:0] bits (Delay between 2 sampling phases) /
Kojto	122:f9eeca106725	1778	#define ADC_CCR_DELAY_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	1779	#define ADC_CCR_DELAY_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	1780	#define ADC_CCR_DELAY_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	1781	#define ADC_CCR_DELAY_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	1782	#define ADC_CCR_DDS 0x00002000U /!<DMA disable selection (Multi-ADC mode) /
Kojto	122:f9eeca106725	1783	#define ADC_CCR_DMA 0x0000C000U /!<DMA[1:0] bits (Direct Memory Access mode for multimode) /
Kojto	122:f9eeca106725	1784	#define ADC_CCR_DMA_0 0x00004000U /!<Bit 0 /
Kojto	122:f9eeca106725	1785	#define ADC_CCR_DMA_1 0x00008000U /!<Bit 1 /
Kojto	122:f9eeca106725	1786	#define ADC_CCR_ADCPRE 0x00030000U /!<ADCPRE[1:0] bits (ADC prescaler) /
Kojto	122:f9eeca106725	1787	#define ADC_CCR_ADCPRE_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	1788	#define ADC_CCR_ADCPRE_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	1789	#define ADC_CCR_VBATE 0x00400000U /!<VBAT Enable /
Kojto	122:f9eeca106725	1790	#define ADC_CCR_TSVREFE 0x00800000U /!<Temperature Sensor and VREFINT Enable /
Kojto	107:4f6c30876dfa	1791
Kojto	107:4f6c30876dfa	1792	/***************** Bit definition for ADC_CDR register ******************/
Kojto	122:f9eeca106725	1793	#define ADC_CDR_DATA1 0x0000FFFFU /!<1st data of a pair of regular conversions /
Kojto	122:f9eeca106725	1794	#define ADC_CDR_DATA2 0xFFFF0000U /!<2nd data of a pair of regular conversions /
Kojto	107:4f6c30876dfa	1795
Kojto	107:4f6c30876dfa	1796	/******************************************************************************/
Kojto	107:4f6c30876dfa	1797	/* */
Kojto	107:4f6c30876dfa	1798	/* Controller Area Network */
Kojto	107:4f6c30876dfa	1799	/* */
Kojto	107:4f6c30876dfa	1800	/******************************************************************************/
Kojto	107:4f6c30876dfa	1801	/!<CAN control and status registers /
Kojto	107:4f6c30876dfa	1802	/***************** Bit definition for CAN_MCR register ******************/
Kojto	122:f9eeca106725	1803	#define CAN_MCR_INRQ 0x00000001U /!<Initialization Request /
Kojto	122:f9eeca106725	1804	#define CAN_MCR_SLEEP 0x00000002U /!<Sleep Mode Request /
Kojto	122:f9eeca106725	1805	#define CAN_MCR_TXFP 0x00000004U /!<Transmit FIFO Priority /
Kojto	122:f9eeca106725	1806	#define CAN_MCR_RFLM 0x00000008U /!<Receive FIFO Locked Mode /
Kojto	122:f9eeca106725	1807	#define CAN_MCR_NART 0x00000010U /!<No Automatic Retransmission /
Kojto	122:f9eeca106725	1808	#define CAN_MCR_AWUM 0x00000020U /!<Automatic Wakeup Mode /
Kojto	122:f9eeca106725	1809	#define CAN_MCR_ABOM 0x00000040U /!<Automatic Bus-Off Management /
Kojto	122:f9eeca106725	1810	#define CAN_MCR_TTCM 0x00000080U /!<Time Triggered Communication Mode /
Kojto	122:f9eeca106725	1811	#define CAN_MCR_RESET 0x00008000U /!<bxCAN software master reset /
Kojto	107:4f6c30876dfa	1812
Kojto	107:4f6c30876dfa	1813	/***************** Bit definition for CAN_MSR register ******************/
Kojto	122:f9eeca106725	1814	#define CAN_MSR_INAK 0x00000001U /!<Initialization Acknowledge /
Kojto	122:f9eeca106725	1815	#define CAN_MSR_SLAK 0x00000002U /!<Sleep Acknowledge /
Kojto	122:f9eeca106725	1816	#define CAN_MSR_ERRI 0x00000004U /!<Error Interrupt /
Kojto	122:f9eeca106725	1817	#define CAN_MSR_WKUI 0x00000008U /!<Wakeup Interrupt /
Kojto	122:f9eeca106725	1818	#define CAN_MSR_SLAKI 0x00000010U /!<Sleep Acknowledge Interrupt /
Kojto	122:f9eeca106725	1819	#define CAN_MSR_TXM 0x00000100U /!<Transmit Mode /
Kojto	122:f9eeca106725	1820	#define CAN_MSR_RXM 0x00000200U /!<Receive Mode /
Kojto	122:f9eeca106725	1821	#define CAN_MSR_SAMP 0x00000400U /!<Last Sample Point /
Kojto	122:f9eeca106725	1822	#define CAN_MSR_RX 0x00000800U /!<CAN Rx Signal /
Kojto	107:4f6c30876dfa	1823
Kojto	107:4f6c30876dfa	1824	/***************** Bit definition for CAN_TSR register ******************/
Kojto	122:f9eeca106725	1825	#define CAN_TSR_RQCP0 0x00000001U /!<Request Completed Mailbox0 /
Kojto	122:f9eeca106725	1826	#define CAN_TSR_TXOK0 0x00000002U /!<Transmission OK of Mailbox0 /
Kojto	122:f9eeca106725	1827	#define CAN_TSR_ALST0 0x00000004U /!<Arbitration Lost for Mailbox0 /
Kojto	122:f9eeca106725	1828	#define CAN_TSR_TERR0 0x00000008U /!<Transmission Error of Mailbox0 /
Kojto	122:f9eeca106725	1829	#define CAN_TSR_ABRQ0 0x00000080U /!<Abort Request for Mailbox0 /
Kojto	122:f9eeca106725	1830	#define CAN_TSR_RQCP1 0x00000100U /!<Request Completed Mailbox1 /
Kojto	122:f9eeca106725	1831	#define CAN_TSR_TXOK1 0x00000200U /!<Transmission OK of Mailbox1 /
Kojto	122:f9eeca106725	1832	#define CAN_TSR_ALST1 0x00000400U /!<Arbitration Lost for Mailbox1 /
Kojto	122:f9eeca106725	1833	#define CAN_TSR_TERR1 0x00000800U /!<Transmission Error of Mailbox1 /
Kojto	122:f9eeca106725	1834	#define CAN_TSR_ABRQ1 0x00008000U /!<Abort Request for Mailbox 1 /
Kojto	122:f9eeca106725	1835	#define CAN_TSR_RQCP2 0x00010000U /!<Request Completed Mailbox2 /
Kojto	122:f9eeca106725	1836	#define CAN_TSR_TXOK2 0x00020000U /!<Transmission OK of Mailbox 2 /
Kojto	122:f9eeca106725	1837	#define CAN_TSR_ALST2 0x00040000U /!<Arbitration Lost for mailbox 2 /
Kojto	122:f9eeca106725	1838	#define CAN_TSR_TERR2 0x00080000U /!<Transmission Error of Mailbox 2 /
Kojto	122:f9eeca106725	1839	#define CAN_TSR_ABRQ2 0x00800000U /!<Abort Request for Mailbox 2 /
Kojto	122:f9eeca106725	1840	#define CAN_TSR_CODE 0x03000000U /!<Mailbox Code /
Kojto	122:f9eeca106725	1841
Kojto	122:f9eeca106725	1842	#define CAN_TSR_TME 0x1C000000U /!<TME[2:0] bits /
Kojto	122:f9eeca106725	1843	#define CAN_TSR_TME0 0x04000000U /!<Transmit Mailbox 0 Empty /
Kojto	122:f9eeca106725	1844	#define CAN_TSR_TME1 0x08000000U /!<Transmit Mailbox 1 Empty /
Kojto	122:f9eeca106725	1845	#define CAN_TSR_TME2 0x10000000U /!<Transmit Mailbox 2 Empty /
Kojto	122:f9eeca106725	1846
Kojto	122:f9eeca106725	1847	#define CAN_TSR_LOW 0xE0000000U /!<LOW[2:0] bits /
Kojto	122:f9eeca106725	1848	#define CAN_TSR_LOW0 0x20000000U /!<Lowest Priority Flag for Mailbox 0 /
Kojto	122:f9eeca106725	1849	#define CAN_TSR_LOW1 0x40000000U /!<Lowest Priority Flag for Mailbox 1 /
Kojto	122:f9eeca106725	1850	#define CAN_TSR_LOW2 0x80000000U /!<Lowest Priority Flag for Mailbox 2 /
Kojto	107:4f6c30876dfa	1851
Kojto	107:4f6c30876dfa	1852	/***************** Bit definition for CAN_RF0R register *****************/
Kojto	122:f9eeca106725	1853	#define CAN_RF0R_FMP0 0x00000003U /!<FIFO 0 Message Pending /
Kojto	122:f9eeca106725	1854	#define CAN_RF0R_FULL0 0x00000008U /!<FIFO 0 Full /
Kojto	122:f9eeca106725	1855	#define CAN_RF0R_FOVR0 0x00000010U /!<FIFO 0 Overrun /
Kojto	122:f9eeca106725	1856	#define CAN_RF0R_RFOM0 0x00000020U /!<Release FIFO 0 Output Mailbox /
Kojto	107:4f6c30876dfa	1857
Kojto	107:4f6c30876dfa	1858	/***************** Bit definition for CAN_RF1R register *****************/
Kojto	122:f9eeca106725	1859	#define CAN_RF1R_FMP1 0x00000003U /!<FIFO 1 Message Pending /
Kojto	122:f9eeca106725	1860	#define CAN_RF1R_FULL1 0x00000008U /!<FIFO 1 Full /
Kojto	122:f9eeca106725	1861	#define CAN_RF1R_FOVR1 0x00000010U /!<FIFO 1 Overrun /
Kojto	122:f9eeca106725	1862	#define CAN_RF1R_RFOM1 0x00000020U /!<Release FIFO 1 Output Mailbox /
Kojto	107:4f6c30876dfa	1863
Kojto	107:4f6c30876dfa	1864	/****************** Bit definition for CAN_IER register *****************/
Kojto	122:f9eeca106725	1865	#define CAN_IER_TMEIE 0x00000001U /!<Transmit Mailbox Empty Interrupt Enable /
Kojto	122:f9eeca106725	1866	#define CAN_IER_FMPIE0 0x00000002U /!<FIFO Message Pending Interrupt Enable /
Kojto	122:f9eeca106725	1867	#define CAN_IER_FFIE0 0x00000004U /!<FIFO Full Interrupt Enable /
Kojto	122:f9eeca106725	1868	#define CAN_IER_FOVIE0 0x00000008U /!<FIFO Overrun Interrupt Enable /
Kojto	122:f9eeca106725	1869	#define CAN_IER_FMPIE1 0x00000010U /!<FIFO Message Pending Interrupt Enable /
Kojto	122:f9eeca106725	1870	#define CAN_IER_FFIE1 0x00000020U /!<FIFO Full Interrupt Enable /
Kojto	122:f9eeca106725	1871	#define CAN_IER_FOVIE1 0x00000040U /!<FIFO Overrun Interrupt Enable /
Kojto	122:f9eeca106725	1872	#define CAN_IER_EWGIE 0x00000100U /!<Error Warning Interrupt Enable /
Kojto	122:f9eeca106725	1873	#define CAN_IER_EPVIE 0x00000200U /!<Error Passive Interrupt Enable /
Kojto	122:f9eeca106725	1874	#define CAN_IER_BOFIE 0x00000400U /!<Bus-Off Interrupt Enable /
Kojto	122:f9eeca106725	1875	#define CAN_IER_LECIE 0x00000800U /!<Last Error Code Interrupt Enable /
Kojto	122:f9eeca106725	1876	#define CAN_IER_ERRIE 0x00008000U /!<Error Interrupt Enable /
Kojto	122:f9eeca106725	1877	#define CAN_IER_WKUIE 0x00010000U /!<Wakeup Interrupt Enable /
Kojto	122:f9eeca106725	1878	#define CAN_IER_SLKIE 0x00020000U /!<Sleep Interrupt Enable /
Kojto	107:4f6c30876dfa	1879
Kojto	107:4f6c30876dfa	1880	/****************** Bit definition for CAN_ESR register *****************/
Kojto	122:f9eeca106725	1881	#define CAN_ESR_EWGF 0x00000001U /!<Error Warning Flag /
Kojto	122:f9eeca106725	1882	#define CAN_ESR_EPVF 0x00000002U /!<Error Passive Flag /
Kojto	122:f9eeca106725	1883	#define CAN_ESR_BOFF 0x00000004U /!<Bus-Off Flag /
Kojto	122:f9eeca106725	1884
Kojto	122:f9eeca106725	1885	#define CAN_ESR_LEC 0x00000070U /!<LEC[2:0] bits (Last Error Code) /
Kojto	122:f9eeca106725	1886	#define CAN_ESR_LEC_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	1887	#define CAN_ESR_LEC_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	1888	#define CAN_ESR_LEC_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	1889
Kojto	122:f9eeca106725	1890	#define CAN_ESR_TEC 0x00FF0000U /!<Least significant byte of the 9-bit Transmit Error Counter /
Kojto	122:f9eeca106725	1891	#define CAN_ESR_REC 0xFF000000U /!<Receive Error Counter /
Kojto	107:4f6c30876dfa	1892
Kojto	107:4f6c30876dfa	1893	/***************** Bit definition for CAN_BTR register ******************/
Kojto	122:f9eeca106725	1894	#define CAN_BTR_BRP 0x000003FFU /!<Baud Rate Prescaler /
Kojto	122:f9eeca106725	1895	#define CAN_BTR_TS1 0x000F0000U /!<Time Segment 1 /
Kojto	122:f9eeca106725	1896	#define CAN_BTR_TS1_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	1897	#define CAN_BTR_TS1_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	1898	#define CAN_BTR_TS1_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	1899	#define CAN_BTR_TS1_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	1900	#define CAN_BTR_TS2 0x00700000U /!<Time Segment 2 /
Kojto	122:f9eeca106725	1901	#define CAN_BTR_TS2_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	1902	#define CAN_BTR_TS2_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	1903	#define CAN_BTR_TS2_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	1904	#define CAN_BTR_SJW 0x03000000U /!<Resynchronization Jump Width /
Kojto	122:f9eeca106725	1905	#define CAN_BTR_SJW_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	1906	#define CAN_BTR_SJW_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	1907	#define CAN_BTR_LBKM 0x40000000U /!<Loop Back Mode (Debug) /
Kojto	122:f9eeca106725	1908	#define CAN_BTR_SILM 0x80000000U /!<Silent Mode /
Kojto	107:4f6c30876dfa	1909
Kojto	107:4f6c30876dfa	1910	/!<Mailbox registers /
Kojto	107:4f6c30876dfa	1911	/**************** Bit definition for CAN_TI0R register ******************/
Kojto	122:f9eeca106725	1912	#define CAN_TI0R_TXRQ 0x00000001U /!<Transmit Mailbox Request /
Kojto	122:f9eeca106725	1913	#define CAN_TI0R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1914	#define CAN_TI0R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1915	#define CAN_TI0R_EXID 0x001FFFF8U /!<Extended Identifier /
Kojto	122:f9eeca106725	1916	#define CAN_TI0R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	107:4f6c30876dfa	1917
Kojto	107:4f6c30876dfa	1918	/**************** Bit definition for CAN_TDT0R register *****************/
Kojto	122:f9eeca106725	1919	#define CAN_TDT0R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1920	#define CAN_TDT0R_TGT 0x00000100U /!<Transmit Global Time /
Kojto	122:f9eeca106725	1921	#define CAN_TDT0R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	107:4f6c30876dfa	1922
Kojto	107:4f6c30876dfa	1923	/**************** Bit definition for CAN_TDL0R register *****************/
Kojto	122:f9eeca106725	1924	#define CAN_TDL0R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1925	#define CAN_TDL0R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1926	#define CAN_TDL0R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1927	#define CAN_TDL0R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	107:4f6c30876dfa	1928
Kojto	107:4f6c30876dfa	1929	/**************** Bit definition for CAN_TDH0R register *****************/
Kojto	122:f9eeca106725	1930	#define CAN_TDH0R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	1931	#define CAN_TDH0R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	1932	#define CAN_TDH0R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	1933	#define CAN_TDH0R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	107:4f6c30876dfa	1934
Kojto	107:4f6c30876dfa	1935	/***************** Bit definition for CAN_TI1R register *****************/
Kojto	122:f9eeca106725	1936	#define CAN_TI1R_TXRQ 0x00000001U /!<Transmit Mailbox Request /
Kojto	122:f9eeca106725	1937	#define CAN_TI1R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1938	#define CAN_TI1R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1939	#define CAN_TI1R_EXID 0x001FFFF8U /!<Extended Identifier /
Kojto	122:f9eeca106725	1940	#define CAN_TI1R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	107:4f6c30876dfa	1941
Kojto	107:4f6c30876dfa	1942	/***************** Bit definition for CAN_TDT1R register ****************/
Kojto	122:f9eeca106725	1943	#define CAN_TDT1R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1944	#define CAN_TDT1R_TGT 0x00000100U /!<Transmit Global Time /
Kojto	122:f9eeca106725	1945	#define CAN_TDT1R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	107:4f6c30876dfa	1946
Kojto	107:4f6c30876dfa	1947	/***************** Bit definition for CAN_TDL1R register ****************/
Kojto	122:f9eeca106725	1948	#define CAN_TDL1R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1949	#define CAN_TDL1R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1950	#define CAN_TDL1R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1951	#define CAN_TDL1R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	107:4f6c30876dfa	1952
Kojto	107:4f6c30876dfa	1953	/***************** Bit definition for CAN_TDH1R register ****************/
Kojto	122:f9eeca106725	1954	#define CAN_TDH1R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	1955	#define CAN_TDH1R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	1956	#define CAN_TDH1R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	1957	#define CAN_TDH1R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	107:4f6c30876dfa	1958
Kojto	107:4f6c30876dfa	1959	/***************** Bit definition for CAN_TI2R register *****************/
Kojto	122:f9eeca106725	1960	#define CAN_TI2R_TXRQ 0x00000001U /!<Transmit Mailbox Request /
Kojto	122:f9eeca106725	1961	#define CAN_TI2R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1962	#define CAN_TI2R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1963	#define CAN_TI2R_EXID 0x001FFFF8U /!<Extended identifier /
Kojto	122:f9eeca106725	1964	#define CAN_TI2R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	107:4f6c30876dfa	1965
Kojto	107:4f6c30876dfa	1966	/***************** Bit definition for CAN_TDT2R register ****************/
Kojto	122:f9eeca106725	1967	#define CAN_TDT2R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1968	#define CAN_TDT2R_TGT 0x00000100U /!<Transmit Global Time /
Kojto	122:f9eeca106725	1969	#define CAN_TDT2R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	107:4f6c30876dfa	1970
Kojto	107:4f6c30876dfa	1971	/***************** Bit definition for CAN_TDL2R register ****************/
Kojto	122:f9eeca106725	1972	#define CAN_TDL2R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1973	#define CAN_TDL2R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1974	#define CAN_TDL2R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1975	#define CAN_TDL2R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	107:4f6c30876dfa	1976
Kojto	107:4f6c30876dfa	1977	/***************** Bit definition for CAN_TDH2R register ****************/
Kojto	122:f9eeca106725	1978	#define CAN_TDH2R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	1979	#define CAN_TDH2R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	1980	#define CAN_TDH2R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	1981	#define CAN_TDH2R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	107:4f6c30876dfa	1982
Kojto	107:4f6c30876dfa	1983	/***************** Bit definition for CAN_RI0R register *****************/
Kojto	122:f9eeca106725	1984	#define CAN_RI0R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	1985	#define CAN_RI0R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	1986	#define CAN_RI0R_EXID 0x001FFFF8U /!<Extended Identifier /
Kojto	122:f9eeca106725	1987	#define CAN_RI0R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	107:4f6c30876dfa	1988
Kojto	107:4f6c30876dfa	1989	/***************** Bit definition for CAN_RDT0R register ****************/
Kojto	122:f9eeca106725	1990	#define CAN_RDT0R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	1991	#define CAN_RDT0R_FMI 0x0000FF00U /!<Filter Match Index /
Kojto	122:f9eeca106725	1992	#define CAN_RDT0R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	107:4f6c30876dfa	1993
Kojto	107:4f6c30876dfa	1994	/***************** Bit definition for CAN_RDL0R register ****************/
Kojto	122:f9eeca106725	1995	#define CAN_RDL0R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	1996	#define CAN_RDL0R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	1997	#define CAN_RDL0R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	1998	#define CAN_RDL0R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	107:4f6c30876dfa	1999
Kojto	107:4f6c30876dfa	2000	/***************** Bit definition for CAN_RDH0R register ****************/
Kojto	122:f9eeca106725	2001	#define CAN_RDH0R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	2002	#define CAN_RDH0R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	2003	#define CAN_RDH0R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	2004	#define CAN_RDH0R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	107:4f6c30876dfa	2005
Kojto	107:4f6c30876dfa	2006	/***************** Bit definition for CAN_RI1R register *****************/
Kojto	122:f9eeca106725	2007	#define CAN_RI1R_RTR 0x00000002U /!<Remote Transmission Request /
Kojto	122:f9eeca106725	2008	#define CAN_RI1R_IDE 0x00000004U /!<Identifier Extension /
Kojto	122:f9eeca106725	2009	#define CAN_RI1R_EXID 0x001FFFF8U /!<Extended identifier /
Kojto	122:f9eeca106725	2010	#define CAN_RI1R_STID 0xFFE00000U /!<Standard Identifier or Extended Identifier /
Kojto	107:4f6c30876dfa	2011
Kojto	107:4f6c30876dfa	2012	/***************** Bit definition for CAN_RDT1R register ****************/
Kojto	122:f9eeca106725	2013	#define CAN_RDT1R_DLC 0x0000000FU /!<Data Length Code /
Kojto	122:f9eeca106725	2014	#define CAN_RDT1R_FMI 0x0000FF00U /!<Filter Match Index /
Kojto	122:f9eeca106725	2015	#define CAN_RDT1R_TIME 0xFFFF0000U /!<Message Time Stamp /
Kojto	107:4f6c30876dfa	2016
Kojto	107:4f6c30876dfa	2017	/***************** Bit definition for CAN_RDL1R register ****************/
Kojto	122:f9eeca106725	2018	#define CAN_RDL1R_DATA0 0x000000FFU /!<Data byte 0 /
Kojto	122:f9eeca106725	2019	#define CAN_RDL1R_DATA1 0x0000FF00U /!<Data byte 1 /
Kojto	122:f9eeca106725	2020	#define CAN_RDL1R_DATA2 0x00FF0000U /!<Data byte 2 /
Kojto	122:f9eeca106725	2021	#define CAN_RDL1R_DATA3 0xFF000000U /!<Data byte 3 /
Kojto	107:4f6c30876dfa	2022
Kojto	107:4f6c30876dfa	2023	/***************** Bit definition for CAN_RDH1R register ****************/
Kojto	122:f9eeca106725	2024	#define CAN_RDH1R_DATA4 0x000000FFU /!<Data byte 4 /
Kojto	122:f9eeca106725	2025	#define CAN_RDH1R_DATA5 0x0000FF00U /!<Data byte 5 /
Kojto	122:f9eeca106725	2026	#define CAN_RDH1R_DATA6 0x00FF0000U /!<Data byte 6 /
Kojto	122:f9eeca106725	2027	#define CAN_RDH1R_DATA7 0xFF000000U /!<Data byte 7 /
Kojto	107:4f6c30876dfa	2028
Kojto	107:4f6c30876dfa	2029	/!<CAN filter registers /
Kojto	107:4f6c30876dfa	2030	/***************** Bit definition for CAN_FMR register ******************/
Kojto	122:f9eeca106725	2031	#define CAN_FMR_FINIT ((uint8_t)0x01U) /!<Filter Init Mode /
Kojto	122:f9eeca106725	2032	#define CAN_FMR_CAN2SB 0x00003F00U /!<CAN2 start bank /
Kojto	107:4f6c30876dfa	2033
Kojto	107:4f6c30876dfa	2034	/***************** Bit definition for CAN_FM1R register *****************/
Kojto	122:f9eeca106725	2035	#define CAN_FM1R_FBM 0x3FFFU /!<Filter Mode /
Kojto	122:f9eeca106725	2036	#define CAN_FM1R_FBM0 0x0001U /!<Filter Init Mode bit 0 /
Kojto	122:f9eeca106725	2037	#define CAN_FM1R_FBM1 0x0002U /!<Filter Init Mode bit 1 /
Kojto	122:f9eeca106725	2038	#define CAN_FM1R_FBM2 0x0004U /!<Filter Init Mode bit 2 /
Kojto	122:f9eeca106725	2039	#define CAN_FM1R_FBM3 0x0008U /!<Filter Init Mode bit 3 /
Kojto	122:f9eeca106725	2040	#define CAN_FM1R_FBM4 0x0010U /!<Filter Init Mode bit 4 /
Kojto	122:f9eeca106725	2041	#define CAN_FM1R_FBM5 0x0020U /!<Filter Init Mode bit 5 /
Kojto	122:f9eeca106725	2042	#define CAN_FM1R_FBM6 0x0040U /!<Filter Init Mode bit 6 /
Kojto	122:f9eeca106725	2043	#define CAN_FM1R_FBM7 0x0080U /!<Filter Init Mode bit 7 /
Kojto	122:f9eeca106725	2044	#define CAN_FM1R_FBM8 0x0100U /!<Filter Init Mode bit 8 /
Kojto	122:f9eeca106725	2045	#define CAN_FM1R_FBM9 0x0200U /!<Filter Init Mode bit 9 /
Kojto	122:f9eeca106725	2046	#define CAN_FM1R_FBM10 0x0400U /!<Filter Init Mode bit 10 /
Kojto	122:f9eeca106725	2047	#define CAN_FM1R_FBM11 0x0800U /!<Filter Init Mode bit 11 /
Kojto	122:f9eeca106725	2048	#define CAN_FM1R_FBM12 0x1000U /!<Filter Init Mode bit 12 /
Kojto	122:f9eeca106725	2049	#define CAN_FM1R_FBM13 0x2000U /!<Filter Init Mode bit 13 /
Kojto	107:4f6c30876dfa	2050
Kojto	107:4f6c30876dfa	2051	/***************** Bit definition for CAN_FS1R register *****************/
Kojto	122:f9eeca106725	2052	#define CAN_FS1R_FSC 0x00003FFFU /!<Filter Scale Configuration /
Kojto	122:f9eeca106725	2053	#define CAN_FS1R_FSC0 0x00000001U /!<Filter Scale Configuration bit 0 /
Kojto	122:f9eeca106725	2054	#define CAN_FS1R_FSC1 0x00000002U /!<Filter Scale Configuration bit 1 /
Kojto	122:f9eeca106725	2055	#define CAN_FS1R_FSC2 0x00000004U /!<Filter Scale Configuration bit 2 /
Kojto	122:f9eeca106725	2056	#define CAN_FS1R_FSC3 0x00000008U /!<Filter Scale Configuration bit 3 /
Kojto	122:f9eeca106725	2057	#define CAN_FS1R_FSC4 0x00000010U /!<Filter Scale Configuration bit 4 /
Kojto	122:f9eeca106725	2058	#define CAN_FS1R_FSC5 0x00000020U /!<Filter Scale Configuration bit 5 /
Kojto	122:f9eeca106725	2059	#define CAN_FS1R_FSC6 0x00000040U /!<Filter Scale Configuration bit 6 /
Kojto	122:f9eeca106725	2060	#define CAN_FS1R_FSC7 0x00000080U /!<Filter Scale Configuration bit 7 /
Kojto	122:f9eeca106725	2061	#define CAN_FS1R_FSC8 0x00000100U /!<Filter Scale Configuration bit 8 /
Kojto	122:f9eeca106725	2062	#define CAN_FS1R_FSC9 0x00000200U /!<Filter Scale Configuration bit 9 /
Kojto	122:f9eeca106725	2063	#define CAN_FS1R_FSC10 0x00000400U /!<Filter Scale Configuration bit 10 /
Kojto	122:f9eeca106725	2064	#define CAN_FS1R_FSC11 0x00000800U /!<Filter Scale Configuration bit 11 /
Kojto	122:f9eeca106725	2065	#define CAN_FS1R_FSC12 0x00001000U /!<Filter Scale Configuration bit 12 /
Kojto	122:f9eeca106725	2066	#define CAN_FS1R_FSC13 0x00002000U /!<Filter Scale Configuration bit 13 /
Kojto	107:4f6c30876dfa	2067
Kojto	107:4f6c30876dfa	2068	/**************** Bit definition for CAN_FFA1R register *****************/
Kojto	122:f9eeca106725	2069	#define CAN_FFA1R_FFA 0x00003FFFU /!<Filter FIFO Assignment /
Kojto	122:f9eeca106725	2070	#define CAN_FFA1R_FFA0 0x00000001U /!<Filter FIFO Assignment for Filter 0 /
Kojto	122:f9eeca106725	2071	#define CAN_FFA1R_FFA1 0x00000002U /!<Filter FIFO Assignment for Filter 1 /
Kojto	122:f9eeca106725	2072	#define CAN_FFA1R_FFA2 0x00000004U /!<Filter FIFO Assignment for Filter 2 /
Kojto	122:f9eeca106725	2073	#define CAN_FFA1R_FFA3 0x00000008U /!<Filter FIFO Assignment for Filter 3 /
Kojto	122:f9eeca106725	2074	#define CAN_FFA1R_FFA4 0x00000010U /!<Filter FIFO Assignment for Filter 4 /
Kojto	122:f9eeca106725	2075	#define CAN_FFA1R_FFA5 0x00000020U /!<Filter FIFO Assignment for Filter 5 /
Kojto	122:f9eeca106725	2076	#define CAN_FFA1R_FFA6 0x00000040U /!<Filter FIFO Assignment for Filter 6 /
Kojto	122:f9eeca106725	2077	#define CAN_FFA1R_FFA7 0x00000080U /!<Filter FIFO Assignment for Filter 7 /
Kojto	122:f9eeca106725	2078	#define CAN_FFA1R_FFA8 0x00000100U /!<Filter FIFO Assignment for Filter 8 /
Kojto	122:f9eeca106725	2079	#define CAN_FFA1R_FFA9 0x00000200U /!<Filter FIFO Assignment for Filter 9 /
Kojto	122:f9eeca106725	2080	#define CAN_FFA1R_FFA10 0x00000400U /!<Filter FIFO Assignment for Filter 10 /
Kojto	122:f9eeca106725	2081	#define CAN_FFA1R_FFA11 0x00000800U /!<Filter FIFO Assignment for Filter 11 /
Kojto	122:f9eeca106725	2082	#define CAN_FFA1R_FFA12 0x00001000U /!<Filter FIFO Assignment for Filter 12 /
Kojto	122:f9eeca106725	2083	#define CAN_FFA1R_FFA13 0x00002000U /!<Filter FIFO Assignment for Filter 13 /
Kojto	107:4f6c30876dfa	2084
Kojto	107:4f6c30876dfa	2085	/***************** Bit definition for CAN_FA1R register *****************/
Kojto	122:f9eeca106725	2086	#define CAN_FA1R_FACT 0x00003FFFU /!<Filter Active /
Kojto	122:f9eeca106725	2087	#define CAN_FA1R_FACT0 0x00000001U /!<Filter 0 Active /
Kojto	122:f9eeca106725	2088	#define CAN_FA1R_FACT1 0x00000002U /!<Filter 1 Active /
Kojto	122:f9eeca106725	2089	#define CAN_FA1R_FACT2 0x00000004U /!<Filter 2 Active /
Kojto	122:f9eeca106725	2090	#define CAN_FA1R_FACT3 0x00000008U /!<Filter 3 Active /
Kojto	122:f9eeca106725	2091	#define CAN_FA1R_FACT4 0x00000010U /!<Filter 4 Active /
Kojto	122:f9eeca106725	2092	#define CAN_FA1R_FACT5 0x00000020U /!<Filter 5 Active /
Kojto	122:f9eeca106725	2093	#define CAN_FA1R_FACT6 0x00000040U /!<Filter 6 Active /
Kojto	122:f9eeca106725	2094	#define CAN_FA1R_FACT7 0x00000080U /!<Filter 7 Active /
Kojto	122:f9eeca106725	2095	#define CAN_FA1R_FACT8 0x00000100U /!<Filter 8 Active /
Kojto	122:f9eeca106725	2096	#define CAN_FA1R_FACT9 0x00000200U /!<Filter 9 Active /
Kojto	122:f9eeca106725	2097	#define CAN_FA1R_FACT10 0x00000400U /!<Filter 10 Active /
Kojto	122:f9eeca106725	2098	#define CAN_FA1R_FACT11 0x00000800U /!<Filter 11 Active /
Kojto	122:f9eeca106725	2099	#define CAN_FA1R_FACT12 0x00001000U /!<Filter 12 Active /
Kojto	122:f9eeca106725	2100	#define CAN_FA1R_FACT13 0x00002000U /!<Filter 13 Active /
Kojto	107:4f6c30876dfa	2101
Kojto	107:4f6c30876dfa	2102	/***************** Bit definition for CAN_F0R1 register *****************/
Kojto	122:f9eeca106725	2103	#define CAN_F0R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2104	#define CAN_F0R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2105	#define CAN_F0R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2106	#define CAN_F0R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2107	#define CAN_F0R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2108	#define CAN_F0R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2109	#define CAN_F0R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2110	#define CAN_F0R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2111	#define CAN_F0R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2112	#define CAN_F0R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2113	#define CAN_F0R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2114	#define CAN_F0R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2115	#define CAN_F0R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2116	#define CAN_F0R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2117	#define CAN_F0R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2118	#define CAN_F0R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2119	#define CAN_F0R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2120	#define CAN_F0R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2121	#define CAN_F0R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2122	#define CAN_F0R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2123	#define CAN_F0R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2124	#define CAN_F0R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2125	#define CAN_F0R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2126	#define CAN_F0R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2127	#define CAN_F0R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2128	#define CAN_F0R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2129	#define CAN_F0R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2130	#define CAN_F0R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2131	#define CAN_F0R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2132	#define CAN_F0R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2133	#define CAN_F0R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2134	#define CAN_F0R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2135
Kojto	107:4f6c30876dfa	2136	/***************** Bit definition for CAN_F1R1 register *****************/
Kojto	122:f9eeca106725	2137	#define CAN_F1R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2138	#define CAN_F1R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2139	#define CAN_F1R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2140	#define CAN_F1R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2141	#define CAN_F1R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2142	#define CAN_F1R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2143	#define CAN_F1R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2144	#define CAN_F1R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2145	#define CAN_F1R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2146	#define CAN_F1R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2147	#define CAN_F1R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2148	#define CAN_F1R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2149	#define CAN_F1R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2150	#define CAN_F1R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2151	#define CAN_F1R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2152	#define CAN_F1R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2153	#define CAN_F1R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2154	#define CAN_F1R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2155	#define CAN_F1R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2156	#define CAN_F1R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2157	#define CAN_F1R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2158	#define CAN_F1R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2159	#define CAN_F1R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2160	#define CAN_F1R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2161	#define CAN_F1R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2162	#define CAN_F1R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2163	#define CAN_F1R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2164	#define CAN_F1R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2165	#define CAN_F1R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2166	#define CAN_F1R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2167	#define CAN_F1R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2168	#define CAN_F1R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2169
Kojto	107:4f6c30876dfa	2170	/***************** Bit definition for CAN_F2R1 register *****************/
Kojto	122:f9eeca106725	2171	#define CAN_F2R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2172	#define CAN_F2R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2173	#define CAN_F2R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2174	#define CAN_F2R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2175	#define CAN_F2R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2176	#define CAN_F2R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2177	#define CAN_F2R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2178	#define CAN_F2R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2179	#define CAN_F2R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2180	#define CAN_F2R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2181	#define CAN_F2R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2182	#define CAN_F2R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2183	#define CAN_F2R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2184	#define CAN_F2R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2185	#define CAN_F2R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2186	#define CAN_F2R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2187	#define CAN_F2R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2188	#define CAN_F2R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2189	#define CAN_F2R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2190	#define CAN_F2R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2191	#define CAN_F2R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2192	#define CAN_F2R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2193	#define CAN_F2R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2194	#define CAN_F2R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2195	#define CAN_F2R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2196	#define CAN_F2R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2197	#define CAN_F2R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2198	#define CAN_F2R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2199	#define CAN_F2R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2200	#define CAN_F2R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2201	#define CAN_F2R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2202	#define CAN_F2R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2203
Kojto	107:4f6c30876dfa	2204	/***************** Bit definition for CAN_F3R1 register *****************/
Kojto	122:f9eeca106725	2205	#define CAN_F3R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2206	#define CAN_F3R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2207	#define CAN_F3R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2208	#define CAN_F3R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2209	#define CAN_F3R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2210	#define CAN_F3R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2211	#define CAN_F3R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2212	#define CAN_F3R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2213	#define CAN_F3R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2214	#define CAN_F3R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2215	#define CAN_F3R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2216	#define CAN_F3R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2217	#define CAN_F3R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2218	#define CAN_F3R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2219	#define CAN_F3R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2220	#define CAN_F3R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2221	#define CAN_F3R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2222	#define CAN_F3R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2223	#define CAN_F3R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2224	#define CAN_F3R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2225	#define CAN_F3R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2226	#define CAN_F3R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2227	#define CAN_F3R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2228	#define CAN_F3R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2229	#define CAN_F3R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2230	#define CAN_F3R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2231	#define CAN_F3R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2232	#define CAN_F3R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2233	#define CAN_F3R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2234	#define CAN_F3R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2235	#define CAN_F3R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2236	#define CAN_F3R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2237
Kojto	107:4f6c30876dfa	2238	/***************** Bit definition for CAN_F4R1 register *****************/
Kojto	122:f9eeca106725	2239	#define CAN_F4R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2240	#define CAN_F4R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2241	#define CAN_F4R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2242	#define CAN_F4R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2243	#define CAN_F4R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2244	#define CAN_F4R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2245	#define CAN_F4R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2246	#define CAN_F4R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2247	#define CAN_F4R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2248	#define CAN_F4R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2249	#define CAN_F4R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2250	#define CAN_F4R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2251	#define CAN_F4R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2252	#define CAN_F4R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2253	#define CAN_F4R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2254	#define CAN_F4R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2255	#define CAN_F4R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2256	#define CAN_F4R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2257	#define CAN_F4R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2258	#define CAN_F4R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2259	#define CAN_F4R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2260	#define CAN_F4R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2261	#define CAN_F4R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2262	#define CAN_F4R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2263	#define CAN_F4R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2264	#define CAN_F4R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2265	#define CAN_F4R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2266	#define CAN_F4R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2267	#define CAN_F4R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2268	#define CAN_F4R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2269	#define CAN_F4R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2270	#define CAN_F4R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2271
Kojto	107:4f6c30876dfa	2272	/***************** Bit definition for CAN_F5R1 register *****************/
Kojto	122:f9eeca106725	2273	#define CAN_F5R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2274	#define CAN_F5R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2275	#define CAN_F5R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2276	#define CAN_F5R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2277	#define CAN_F5R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2278	#define CAN_F5R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2279	#define CAN_F5R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2280	#define CAN_F5R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2281	#define CAN_F5R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2282	#define CAN_F5R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2283	#define CAN_F5R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2284	#define CAN_F5R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2285	#define CAN_F5R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2286	#define CAN_F5R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2287	#define CAN_F5R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2288	#define CAN_F5R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2289	#define CAN_F5R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2290	#define CAN_F5R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2291	#define CAN_F5R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2292	#define CAN_F5R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2293	#define CAN_F5R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2294	#define CAN_F5R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2295	#define CAN_F5R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2296	#define CAN_F5R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2297	#define CAN_F5R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2298	#define CAN_F5R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2299	#define CAN_F5R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2300	#define CAN_F5R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2301	#define CAN_F5R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2302	#define CAN_F5R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2303	#define CAN_F5R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2304	#define CAN_F5R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2305
Kojto	107:4f6c30876dfa	2306	/***************** Bit definition for CAN_F6R1 register *****************/
Kojto	122:f9eeca106725	2307	#define CAN_F6R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2308	#define CAN_F6R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2309	#define CAN_F6R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2310	#define CAN_F6R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2311	#define CAN_F6R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2312	#define CAN_F6R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2313	#define CAN_F6R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2314	#define CAN_F6R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2315	#define CAN_F6R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2316	#define CAN_F6R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2317	#define CAN_F6R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2318	#define CAN_F6R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2319	#define CAN_F6R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2320	#define CAN_F6R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2321	#define CAN_F6R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2322	#define CAN_F6R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2323	#define CAN_F6R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2324	#define CAN_F6R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2325	#define CAN_F6R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2326	#define CAN_F6R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2327	#define CAN_F6R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2328	#define CAN_F6R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2329	#define CAN_F6R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2330	#define CAN_F6R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2331	#define CAN_F6R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2332	#define CAN_F6R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2333	#define CAN_F6R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2334	#define CAN_F6R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2335	#define CAN_F6R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2336	#define CAN_F6R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2337	#define CAN_F6R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2338	#define CAN_F6R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2339
Kojto	107:4f6c30876dfa	2340	/***************** Bit definition for CAN_F7R1 register *****************/
Kojto	122:f9eeca106725	2341	#define CAN_F7R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2342	#define CAN_F7R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2343	#define CAN_F7R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2344	#define CAN_F7R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2345	#define CAN_F7R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2346	#define CAN_F7R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2347	#define CAN_F7R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2348	#define CAN_F7R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2349	#define CAN_F7R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2350	#define CAN_F7R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2351	#define CAN_F7R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2352	#define CAN_F7R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2353	#define CAN_F7R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2354	#define CAN_F7R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2355	#define CAN_F7R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2356	#define CAN_F7R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2357	#define CAN_F7R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2358	#define CAN_F7R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2359	#define CAN_F7R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2360	#define CAN_F7R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2361	#define CAN_F7R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2362	#define CAN_F7R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2363	#define CAN_F7R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2364	#define CAN_F7R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2365	#define CAN_F7R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2366	#define CAN_F7R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2367	#define CAN_F7R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2368	#define CAN_F7R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2369	#define CAN_F7R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2370	#define CAN_F7R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2371	#define CAN_F7R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2372	#define CAN_F7R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2373
Kojto	107:4f6c30876dfa	2374	/***************** Bit definition for CAN_F8R1 register *****************/
Kojto	122:f9eeca106725	2375	#define CAN_F8R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2376	#define CAN_F8R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2377	#define CAN_F8R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2378	#define CAN_F8R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2379	#define CAN_F8R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2380	#define CAN_F8R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2381	#define CAN_F8R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2382	#define CAN_F8R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2383	#define CAN_F8R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2384	#define CAN_F8R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2385	#define CAN_F8R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2386	#define CAN_F8R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2387	#define CAN_F8R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2388	#define CAN_F8R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2389	#define CAN_F8R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2390	#define CAN_F8R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2391	#define CAN_F8R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2392	#define CAN_F8R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2393	#define CAN_F8R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2394	#define CAN_F8R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2395	#define CAN_F8R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2396	#define CAN_F8R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2397	#define CAN_F8R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2398	#define CAN_F8R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2399	#define CAN_F8R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2400	#define CAN_F8R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2401	#define CAN_F8R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2402	#define CAN_F8R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2403	#define CAN_F8R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2404	#define CAN_F8R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2405	#define CAN_F8R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2406	#define CAN_F8R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2407
Kojto	107:4f6c30876dfa	2408	/***************** Bit definition for CAN_F9R1 register *****************/
Kojto	122:f9eeca106725	2409	#define CAN_F9R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2410	#define CAN_F9R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2411	#define CAN_F9R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2412	#define CAN_F9R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2413	#define CAN_F9R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2414	#define CAN_F9R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2415	#define CAN_F9R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2416	#define CAN_F9R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2417	#define CAN_F9R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2418	#define CAN_F9R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2419	#define CAN_F9R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2420	#define CAN_F9R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2421	#define CAN_F9R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2422	#define CAN_F9R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2423	#define CAN_F9R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2424	#define CAN_F9R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2425	#define CAN_F9R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2426	#define CAN_F9R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2427	#define CAN_F9R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2428	#define CAN_F9R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2429	#define CAN_F9R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2430	#define CAN_F9R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2431	#define CAN_F9R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2432	#define CAN_F9R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2433	#define CAN_F9R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2434	#define CAN_F9R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2435	#define CAN_F9R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2436	#define CAN_F9R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2437	#define CAN_F9R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2438	#define CAN_F9R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2439	#define CAN_F9R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2440	#define CAN_F9R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2441
Kojto	107:4f6c30876dfa	2442	/***************** Bit definition for CAN_F10R1 register ****************/
Kojto	122:f9eeca106725	2443	#define CAN_F10R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2444	#define CAN_F10R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2445	#define CAN_F10R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2446	#define CAN_F10R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2447	#define CAN_F10R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2448	#define CAN_F10R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2449	#define CAN_F10R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2450	#define CAN_F10R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2451	#define CAN_F10R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2452	#define CAN_F10R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2453	#define CAN_F10R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2454	#define CAN_F10R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2455	#define CAN_F10R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2456	#define CAN_F10R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2457	#define CAN_F10R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2458	#define CAN_F10R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2459	#define CAN_F10R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2460	#define CAN_F10R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2461	#define CAN_F10R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2462	#define CAN_F10R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2463	#define CAN_F10R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2464	#define CAN_F10R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2465	#define CAN_F10R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2466	#define CAN_F10R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2467	#define CAN_F10R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2468	#define CAN_F10R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2469	#define CAN_F10R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2470	#define CAN_F10R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2471	#define CAN_F10R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2472	#define CAN_F10R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2473	#define CAN_F10R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2474	#define CAN_F10R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2475
Kojto	107:4f6c30876dfa	2476	/***************** Bit definition for CAN_F11R1 register ****************/
Kojto	122:f9eeca106725	2477	#define CAN_F11R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2478	#define CAN_F11R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2479	#define CAN_F11R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2480	#define CAN_F11R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2481	#define CAN_F11R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2482	#define CAN_F11R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2483	#define CAN_F11R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2484	#define CAN_F11R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2485	#define CAN_F11R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2486	#define CAN_F11R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2487	#define CAN_F11R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2488	#define CAN_F11R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2489	#define CAN_F11R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2490	#define CAN_F11R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2491	#define CAN_F11R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2492	#define CAN_F11R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2493	#define CAN_F11R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2494	#define CAN_F11R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2495	#define CAN_F11R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2496	#define CAN_F11R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2497	#define CAN_F11R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2498	#define CAN_F11R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2499	#define CAN_F11R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2500	#define CAN_F11R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2501	#define CAN_F11R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2502	#define CAN_F11R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2503	#define CAN_F11R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2504	#define CAN_F11R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2505	#define CAN_F11R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2506	#define CAN_F11R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2507	#define CAN_F11R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2508	#define CAN_F11R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2509
Kojto	107:4f6c30876dfa	2510	/***************** Bit definition for CAN_F12R1 register ****************/
Kojto	122:f9eeca106725	2511	#define CAN_F12R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2512	#define CAN_F12R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2513	#define CAN_F12R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2514	#define CAN_F12R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2515	#define CAN_F12R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2516	#define CAN_F12R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2517	#define CAN_F12R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2518	#define CAN_F12R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2519	#define CAN_F12R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2520	#define CAN_F12R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2521	#define CAN_F12R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2522	#define CAN_F12R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2523	#define CAN_F12R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2524	#define CAN_F12R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2525	#define CAN_F12R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2526	#define CAN_F12R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2527	#define CAN_F12R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2528	#define CAN_F12R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2529	#define CAN_F12R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2530	#define CAN_F12R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2531	#define CAN_F12R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2532	#define CAN_F12R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2533	#define CAN_F12R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2534	#define CAN_F12R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2535	#define CAN_F12R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2536	#define CAN_F12R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2537	#define CAN_F12R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2538	#define CAN_F12R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2539	#define CAN_F12R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2540	#define CAN_F12R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2541	#define CAN_F12R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2542	#define CAN_F12R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2543
Kojto	107:4f6c30876dfa	2544	/***************** Bit definition for CAN_F13R1 register ****************/
Kojto	122:f9eeca106725	2545	#define CAN_F13R1_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2546	#define CAN_F13R1_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2547	#define CAN_F13R1_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2548	#define CAN_F13R1_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2549	#define CAN_F13R1_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2550	#define CAN_F13R1_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2551	#define CAN_F13R1_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2552	#define CAN_F13R1_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2553	#define CAN_F13R1_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2554	#define CAN_F13R1_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2555	#define CAN_F13R1_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2556	#define CAN_F13R1_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2557	#define CAN_F13R1_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2558	#define CAN_F13R1_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2559	#define CAN_F13R1_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2560	#define CAN_F13R1_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2561	#define CAN_F13R1_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2562	#define CAN_F13R1_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2563	#define CAN_F13R1_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2564	#define CAN_F13R1_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2565	#define CAN_F13R1_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2566	#define CAN_F13R1_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2567	#define CAN_F13R1_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2568	#define CAN_F13R1_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2569	#define CAN_F13R1_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2570	#define CAN_F13R1_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2571	#define CAN_F13R1_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2572	#define CAN_F13R1_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2573	#define CAN_F13R1_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2574	#define CAN_F13R1_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2575	#define CAN_F13R1_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2576	#define CAN_F13R1_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2577
Kojto	107:4f6c30876dfa	2578	/***************** Bit definition for CAN_F0R2 register *****************/
Kojto	122:f9eeca106725	2579	#define CAN_F0R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2580	#define CAN_F0R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2581	#define CAN_F0R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2582	#define CAN_F0R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2583	#define CAN_F0R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2584	#define CAN_F0R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2585	#define CAN_F0R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2586	#define CAN_F0R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2587	#define CAN_F0R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2588	#define CAN_F0R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2589	#define CAN_F0R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2590	#define CAN_F0R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2591	#define CAN_F0R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2592	#define CAN_F0R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2593	#define CAN_F0R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2594	#define CAN_F0R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2595	#define CAN_F0R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2596	#define CAN_F0R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2597	#define CAN_F0R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2598	#define CAN_F0R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2599	#define CAN_F0R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2600	#define CAN_F0R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2601	#define CAN_F0R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2602	#define CAN_F0R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2603	#define CAN_F0R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2604	#define CAN_F0R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2605	#define CAN_F0R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2606	#define CAN_F0R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2607	#define CAN_F0R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2608	#define CAN_F0R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2609	#define CAN_F0R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2610	#define CAN_F0R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2611
Kojto	107:4f6c30876dfa	2612	/***************** Bit definition for CAN_F1R2 register *****************/
Kojto	122:f9eeca106725	2613	#define CAN_F1R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2614	#define CAN_F1R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2615	#define CAN_F1R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2616	#define CAN_F1R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2617	#define CAN_F1R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2618	#define CAN_F1R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2619	#define CAN_F1R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2620	#define CAN_F1R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2621	#define CAN_F1R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2622	#define CAN_F1R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2623	#define CAN_F1R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2624	#define CAN_F1R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2625	#define CAN_F1R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2626	#define CAN_F1R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2627	#define CAN_F1R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2628	#define CAN_F1R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2629	#define CAN_F1R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2630	#define CAN_F1R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2631	#define CAN_F1R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2632	#define CAN_F1R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2633	#define CAN_F1R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2634	#define CAN_F1R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2635	#define CAN_F1R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2636	#define CAN_F1R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2637	#define CAN_F1R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2638	#define CAN_F1R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2639	#define CAN_F1R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2640	#define CAN_F1R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2641	#define CAN_F1R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2642	#define CAN_F1R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2643	#define CAN_F1R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2644	#define CAN_F1R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2645
Kojto	107:4f6c30876dfa	2646	/***************** Bit definition for CAN_F2R2 register *****************/
Kojto	122:f9eeca106725	2647	#define CAN_F2R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2648	#define CAN_F2R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2649	#define CAN_F2R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2650	#define CAN_F2R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2651	#define CAN_F2R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2652	#define CAN_F2R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2653	#define CAN_F2R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2654	#define CAN_F2R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2655	#define CAN_F2R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2656	#define CAN_F2R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2657	#define CAN_F2R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2658	#define CAN_F2R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2659	#define CAN_F2R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2660	#define CAN_F2R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2661	#define CAN_F2R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2662	#define CAN_F2R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2663	#define CAN_F2R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2664	#define CAN_F2R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2665	#define CAN_F2R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2666	#define CAN_F2R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2667	#define CAN_F2R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2668	#define CAN_F2R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2669	#define CAN_F2R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2670	#define CAN_F2R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2671	#define CAN_F2R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2672	#define CAN_F2R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2673	#define CAN_F2R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2674	#define CAN_F2R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2675	#define CAN_F2R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2676	#define CAN_F2R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2677	#define CAN_F2R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2678	#define CAN_F2R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2679
Kojto	107:4f6c30876dfa	2680	/***************** Bit definition for CAN_F3R2 register *****************/
Kojto	122:f9eeca106725	2681	#define CAN_F3R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2682	#define CAN_F3R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2683	#define CAN_F3R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2684	#define CAN_F3R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2685	#define CAN_F3R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2686	#define CAN_F3R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2687	#define CAN_F3R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2688	#define CAN_F3R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2689	#define CAN_F3R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2690	#define CAN_F3R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2691	#define CAN_F3R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2692	#define CAN_F3R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2693	#define CAN_F3R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2694	#define CAN_F3R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2695	#define CAN_F3R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2696	#define CAN_F3R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2697	#define CAN_F3R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2698	#define CAN_F3R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2699	#define CAN_F3R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2700	#define CAN_F3R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2701	#define CAN_F3R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2702	#define CAN_F3R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2703	#define CAN_F3R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2704	#define CAN_F3R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2705	#define CAN_F3R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2706	#define CAN_F3R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2707	#define CAN_F3R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2708	#define CAN_F3R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2709	#define CAN_F3R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2710	#define CAN_F3R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2711	#define CAN_F3R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2712	#define CAN_F3R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2713
Kojto	107:4f6c30876dfa	2714	/***************** Bit definition for CAN_F4R2 register *****************/
Kojto	122:f9eeca106725	2715	#define CAN_F4R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2716	#define CAN_F4R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2717	#define CAN_F4R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2718	#define CAN_F4R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2719	#define CAN_F4R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2720	#define CAN_F4R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2721	#define CAN_F4R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2722	#define CAN_F4R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2723	#define CAN_F4R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2724	#define CAN_F4R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2725	#define CAN_F4R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2726	#define CAN_F4R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2727	#define CAN_F4R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2728	#define CAN_F4R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2729	#define CAN_F4R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2730	#define CAN_F4R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2731	#define CAN_F4R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2732	#define CAN_F4R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2733	#define CAN_F4R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2734	#define CAN_F4R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2735	#define CAN_F4R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2736	#define CAN_F4R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2737	#define CAN_F4R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2738	#define CAN_F4R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2739	#define CAN_F4R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2740	#define CAN_F4R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2741	#define CAN_F4R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2742	#define CAN_F4R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2743	#define CAN_F4R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2744	#define CAN_F4R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2745	#define CAN_F4R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2746	#define CAN_F4R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2747
Kojto	107:4f6c30876dfa	2748	/***************** Bit definition for CAN_F5R2 register *****************/
Kojto	122:f9eeca106725	2749	#define CAN_F5R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2750	#define CAN_F5R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2751	#define CAN_F5R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2752	#define CAN_F5R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2753	#define CAN_F5R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2754	#define CAN_F5R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2755	#define CAN_F5R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2756	#define CAN_F5R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2757	#define CAN_F5R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2758	#define CAN_F5R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2759	#define CAN_F5R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2760	#define CAN_F5R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2761	#define CAN_F5R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2762	#define CAN_F5R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2763	#define CAN_F5R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2764	#define CAN_F5R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2765	#define CAN_F5R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2766	#define CAN_F5R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2767	#define CAN_F5R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2768	#define CAN_F5R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2769	#define CAN_F5R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2770	#define CAN_F5R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2771	#define CAN_F5R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2772	#define CAN_F5R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2773	#define CAN_F5R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2774	#define CAN_F5R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2775	#define CAN_F5R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2776	#define CAN_F5R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2777	#define CAN_F5R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2778	#define CAN_F5R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2779	#define CAN_F5R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2780	#define CAN_F5R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2781
Kojto	107:4f6c30876dfa	2782	/***************** Bit definition for CAN_F6R2 register *****************/
Kojto	122:f9eeca106725	2783	#define CAN_F6R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2784	#define CAN_F6R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2785	#define CAN_F6R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2786	#define CAN_F6R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2787	#define CAN_F6R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2788	#define CAN_F6R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2789	#define CAN_F6R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2790	#define CAN_F6R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2791	#define CAN_F6R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2792	#define CAN_F6R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2793	#define CAN_F6R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2794	#define CAN_F6R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2795	#define CAN_F6R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2796	#define CAN_F6R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2797	#define CAN_F6R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2798	#define CAN_F6R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2799	#define CAN_F6R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2800	#define CAN_F6R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2801	#define CAN_F6R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2802	#define CAN_F6R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2803	#define CAN_F6R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2804	#define CAN_F6R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2805	#define CAN_F6R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2806	#define CAN_F6R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2807	#define CAN_F6R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2808	#define CAN_F6R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2809	#define CAN_F6R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2810	#define CAN_F6R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2811	#define CAN_F6R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2812	#define CAN_F6R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2813	#define CAN_F6R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2814	#define CAN_F6R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2815
Kojto	107:4f6c30876dfa	2816	/***************** Bit definition for CAN_F7R2 register *****************/
Kojto	122:f9eeca106725	2817	#define CAN_F7R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2818	#define CAN_F7R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2819	#define CAN_F7R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2820	#define CAN_F7R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2821	#define CAN_F7R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2822	#define CAN_F7R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2823	#define CAN_F7R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2824	#define CAN_F7R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2825	#define CAN_F7R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2826	#define CAN_F7R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2827	#define CAN_F7R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2828	#define CAN_F7R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2829	#define CAN_F7R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2830	#define CAN_F7R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2831	#define CAN_F7R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2832	#define CAN_F7R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2833	#define CAN_F7R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2834	#define CAN_F7R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2835	#define CAN_F7R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2836	#define CAN_F7R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2837	#define CAN_F7R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2838	#define CAN_F7R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2839	#define CAN_F7R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2840	#define CAN_F7R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2841	#define CAN_F7R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2842	#define CAN_F7R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2843	#define CAN_F7R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2844	#define CAN_F7R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2845	#define CAN_F7R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2846	#define CAN_F7R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2847	#define CAN_F7R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2848	#define CAN_F7R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2849
Kojto	107:4f6c30876dfa	2850	/***************** Bit definition for CAN_F8R2 register *****************/
Kojto	122:f9eeca106725	2851	#define CAN_F8R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2852	#define CAN_F8R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2853	#define CAN_F8R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2854	#define CAN_F8R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2855	#define CAN_F8R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2856	#define CAN_F8R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2857	#define CAN_F8R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2858	#define CAN_F8R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2859	#define CAN_F8R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2860	#define CAN_F8R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2861	#define CAN_F8R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2862	#define CAN_F8R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2863	#define CAN_F8R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2864	#define CAN_F8R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2865	#define CAN_F8R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2866	#define CAN_F8R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2867	#define CAN_F8R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2868	#define CAN_F8R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2869	#define CAN_F8R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2870	#define CAN_F8R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2871	#define CAN_F8R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2872	#define CAN_F8R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2873	#define CAN_F8R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2874	#define CAN_F8R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2875	#define CAN_F8R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2876	#define CAN_F8R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2877	#define CAN_F8R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2878	#define CAN_F8R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2879	#define CAN_F8R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2880	#define CAN_F8R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2881	#define CAN_F8R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2882	#define CAN_F8R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2883
Kojto	107:4f6c30876dfa	2884	/***************** Bit definition for CAN_F9R2 register *****************/
Kojto	122:f9eeca106725	2885	#define CAN_F9R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2886	#define CAN_F9R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2887	#define CAN_F9R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2888	#define CAN_F9R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2889	#define CAN_F9R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2890	#define CAN_F9R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2891	#define CAN_F9R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2892	#define CAN_F9R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2893	#define CAN_F9R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2894	#define CAN_F9R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2895	#define CAN_F9R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2896	#define CAN_F9R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2897	#define CAN_F9R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2898	#define CAN_F9R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2899	#define CAN_F9R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2900	#define CAN_F9R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2901	#define CAN_F9R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2902	#define CAN_F9R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2903	#define CAN_F9R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2904	#define CAN_F9R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2905	#define CAN_F9R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2906	#define CAN_F9R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2907	#define CAN_F9R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2908	#define CAN_F9R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2909	#define CAN_F9R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2910	#define CAN_F9R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2911	#define CAN_F9R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2912	#define CAN_F9R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2913	#define CAN_F9R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2914	#define CAN_F9R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2915	#define CAN_F9R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2916	#define CAN_F9R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2917
Kojto	107:4f6c30876dfa	2918	/***************** Bit definition for CAN_F10R2 register ****************/
Kojto	122:f9eeca106725	2919	#define CAN_F10R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2920	#define CAN_F10R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2921	#define CAN_F10R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2922	#define CAN_F10R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2923	#define CAN_F10R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2924	#define CAN_F10R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2925	#define CAN_F10R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2926	#define CAN_F10R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2927	#define CAN_F10R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2928	#define CAN_F10R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2929	#define CAN_F10R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2930	#define CAN_F10R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2931	#define CAN_F10R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2932	#define CAN_F10R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2933	#define CAN_F10R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2934	#define CAN_F10R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2935	#define CAN_F10R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2936	#define CAN_F10R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2937	#define CAN_F10R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2938	#define CAN_F10R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2939	#define CAN_F10R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2940	#define CAN_F10R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2941	#define CAN_F10R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2942	#define CAN_F10R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2943	#define CAN_F10R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2944	#define CAN_F10R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2945	#define CAN_F10R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2946	#define CAN_F10R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2947	#define CAN_F10R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2948	#define CAN_F10R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2949	#define CAN_F10R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2950	#define CAN_F10R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2951
Kojto	107:4f6c30876dfa	2952	/***************** Bit definition for CAN_F11R2 register ****************/
Kojto	122:f9eeca106725	2953	#define CAN_F11R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2954	#define CAN_F11R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2955	#define CAN_F11R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2956	#define CAN_F11R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2957	#define CAN_F11R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2958	#define CAN_F11R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2959	#define CAN_F11R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2960	#define CAN_F11R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2961	#define CAN_F11R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2962	#define CAN_F11R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2963	#define CAN_F11R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2964	#define CAN_F11R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2965	#define CAN_F11R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	2966	#define CAN_F11R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	2967	#define CAN_F11R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	2968	#define CAN_F11R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	2969	#define CAN_F11R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	2970	#define CAN_F11R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	2971	#define CAN_F11R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	2972	#define CAN_F11R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	2973	#define CAN_F11R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	2974	#define CAN_F11R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	2975	#define CAN_F11R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	2976	#define CAN_F11R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	2977	#define CAN_F11R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	2978	#define CAN_F11R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	2979	#define CAN_F11R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	2980	#define CAN_F11R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	2981	#define CAN_F11R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	2982	#define CAN_F11R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	2983	#define CAN_F11R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	2984	#define CAN_F11R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	2985
Kojto	107:4f6c30876dfa	2986	/***************** Bit definition for CAN_F12R2 register ****************/
Kojto	122:f9eeca106725	2987	#define CAN_F12R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	2988	#define CAN_F12R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	2989	#define CAN_F12R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	2990	#define CAN_F12R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	2991	#define CAN_F12R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	2992	#define CAN_F12R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	2993	#define CAN_F12R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	2994	#define CAN_F12R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	2995	#define CAN_F12R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	2996	#define CAN_F12R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	2997	#define CAN_F12R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	2998	#define CAN_F12R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	2999	#define CAN_F12R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	3000	#define CAN_F12R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	3001	#define CAN_F12R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	3002	#define CAN_F12R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	3003	#define CAN_F12R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	3004	#define CAN_F12R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	3005	#define CAN_F12R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	3006	#define CAN_F12R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	3007	#define CAN_F12R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	3008	#define CAN_F12R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	3009	#define CAN_F12R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	3010	#define CAN_F12R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	3011	#define CAN_F12R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	3012	#define CAN_F12R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	3013	#define CAN_F12R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	3014	#define CAN_F12R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	3015	#define CAN_F12R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	3016	#define CAN_F12R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	3017	#define CAN_F12R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	3018	#define CAN_F12R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	3019
Kojto	107:4f6c30876dfa	3020	/***************** Bit definition for CAN_F13R2 register ****************/
Kojto	122:f9eeca106725	3021	#define CAN_F13R2_FB0 0x00000001U /!<Filter bit 0 /
Kojto	122:f9eeca106725	3022	#define CAN_F13R2_FB1 0x00000002U /!<Filter bit 1 /
Kojto	122:f9eeca106725	3023	#define CAN_F13R2_FB2 0x00000004U /!<Filter bit 2 /
Kojto	122:f9eeca106725	3024	#define CAN_F13R2_FB3 0x00000008U /!<Filter bit 3 /
Kojto	122:f9eeca106725	3025	#define CAN_F13R2_FB4 0x00000010U /!<Filter bit 4 /
Kojto	122:f9eeca106725	3026	#define CAN_F13R2_FB5 0x00000020U /!<Filter bit 5 /
Kojto	122:f9eeca106725	3027	#define CAN_F13R2_FB6 0x00000040U /!<Filter bit 6 /
Kojto	122:f9eeca106725	3028	#define CAN_F13R2_FB7 0x00000080U /!<Filter bit 7 /
Kojto	122:f9eeca106725	3029	#define CAN_F13R2_FB8 0x00000100U /!<Filter bit 8 /
Kojto	122:f9eeca106725	3030	#define CAN_F13R2_FB9 0x00000200U /!<Filter bit 9 /
Kojto	122:f9eeca106725	3031	#define CAN_F13R2_FB10 0x00000400U /!<Filter bit 10 /
Kojto	122:f9eeca106725	3032	#define CAN_F13R2_FB11 0x00000800U /!<Filter bit 11 /
Kojto	122:f9eeca106725	3033	#define CAN_F13R2_FB12 0x00001000U /!<Filter bit 12 /
Kojto	122:f9eeca106725	3034	#define CAN_F13R2_FB13 0x00002000U /!<Filter bit 13 /
Kojto	122:f9eeca106725	3035	#define CAN_F13R2_FB14 0x00004000U /!<Filter bit 14 /
Kojto	122:f9eeca106725	3036	#define CAN_F13R2_FB15 0x00008000U /!<Filter bit 15 /
Kojto	122:f9eeca106725	3037	#define CAN_F13R2_FB16 0x00010000U /!<Filter bit 16 /
Kojto	122:f9eeca106725	3038	#define CAN_F13R2_FB17 0x00020000U /!<Filter bit 17 /
Kojto	122:f9eeca106725	3039	#define CAN_F13R2_FB18 0x00040000U /!<Filter bit 18 /
Kojto	122:f9eeca106725	3040	#define CAN_F13R2_FB19 0x00080000U /!<Filter bit 19 /
Kojto	122:f9eeca106725	3041	#define CAN_F13R2_FB20 0x00100000U /!<Filter bit 20 /
Kojto	122:f9eeca106725	3042	#define CAN_F13R2_FB21 0x00200000U /!<Filter bit 21 /
Kojto	122:f9eeca106725	3043	#define CAN_F13R2_FB22 0x00400000U /!<Filter bit 22 /
Kojto	122:f9eeca106725	3044	#define CAN_F13R2_FB23 0x00800000U /!<Filter bit 23 /
Kojto	122:f9eeca106725	3045	#define CAN_F13R2_FB24 0x01000000U /!<Filter bit 24 /
Kojto	122:f9eeca106725	3046	#define CAN_F13R2_FB25 0x02000000U /!<Filter bit 25 /
Kojto	122:f9eeca106725	3047	#define CAN_F13R2_FB26 0x04000000U /!<Filter bit 26 /
Kojto	122:f9eeca106725	3048	#define CAN_F13R2_FB27 0x08000000U /!<Filter bit 27 /
Kojto	122:f9eeca106725	3049	#define CAN_F13R2_FB28 0x10000000U /!<Filter bit 28 /
Kojto	122:f9eeca106725	3050	#define CAN_F13R2_FB29 0x20000000U /!<Filter bit 29 /
Kojto	122:f9eeca106725	3051	#define CAN_F13R2_FB30 0x40000000U /!<Filter bit 30 /
Kojto	122:f9eeca106725	3052	#define CAN_F13R2_FB31 0x80000000U /!<Filter bit 31 /
Kojto	107:4f6c30876dfa	3053
Kojto	107:4f6c30876dfa	3054	/******************************************************************************/
Kojto	107:4f6c30876dfa	3055	/* */
Kojto	107:4f6c30876dfa	3056	/* HDMI-CEC (CEC) */
Kojto	107:4f6c30876dfa	3057	/* */
Kojto	107:4f6c30876dfa	3058	/******************************************************************************/
Kojto	107:4f6c30876dfa	3059
Kojto	107:4f6c30876dfa	3060	/***************** Bit definition for CEC_CR register *******************/
Kojto	122:f9eeca106725	3061	#define CEC_CR_CECEN 0x00000001U /!< CEC Enable /
Kojto	122:f9eeca106725	3062	#define CEC_CR_TXSOM 0x00000002U /!< CEC Tx Start Of Message /
Kojto	122:f9eeca106725	3063	#define CEC_CR_TXEOM 0x00000004U /!< CEC Tx End Of Message /
Kojto	107:4f6c30876dfa	3064
Kojto	107:4f6c30876dfa	3065	/***************** Bit definition for CEC_CFGR register *****************/
Kojto	122:f9eeca106725	3066	#define CEC_CFGR_SFT 0x00000007U /!< CEC Signal Free Time /
Kojto	122:f9eeca106725	3067	#define CEC_CFGR_RXTOL 0x00000008U /!< CEC Tolerance /
Kojto	122:f9eeca106725	3068	#define CEC_CFGR_BRESTP 0x00000010U /!< CEC Rx Stop /
Kojto	122:f9eeca106725	3069	#define CEC_CFGR_BREGEN 0x00000020U /!< CEC Bit Rising Error generation /
Kojto	122:f9eeca106725	3070	#define CEC_CFGR_LBPEGEN 0x00000040U /!< CEC Long Period Error generation /
Kojto	122:f9eeca106725	3071	#define CEC_CFGR_BRDNOGEN 0x00000080U /!< CEC Broadcast no Error generation /
Kojto	122:f9eeca106725	3072	#define CEC_CFGR_SFTOPT 0x00000100U /!< CEC Signal Free Time optional /
Kojto	122:f9eeca106725	3073	#define CEC_CFGR_OAR 0x7FFF0000U /!< CEC Own Address /
Kojto	122:f9eeca106725	3074	#define CEC_CFGR_LSTN 0x80000000U /!< CEC Listen mode /
Kojto	107:4f6c30876dfa	3075
Kojto	107:4f6c30876dfa	3076	/***************** Bit definition for CEC_TXDR register *****************/
Kojto	122:f9eeca106725	3077	#define CEC_TXDR_TXD 0x000000FFU /!< CEC Tx Data /
Kojto	107:4f6c30876dfa	3078
Kojto	107:4f6c30876dfa	3079	/***************** Bit definition for CEC_RXDR register *****************/
Kojto	122:f9eeca106725	3080	#define CEC_TXDR_RXD 0x000000FFU /!< CEC Rx Data /
Kojto	107:4f6c30876dfa	3081
Kojto	107:4f6c30876dfa	3082	/***************** Bit definition for CEC_ISR register ******************/
Kojto	122:f9eeca106725	3083	#define CEC_ISR_RXBR 0x00000001U /!< CEC Rx-Byte Received /
Kojto	122:f9eeca106725	3084	#define CEC_ISR_RXEND 0x00000002U /!< CEC End Of Reception /
Kojto	122:f9eeca106725	3085	#define CEC_ISR_RXOVR 0x00000004U /!< CEC Rx-Overrun /
Kojto	122:f9eeca106725	3086	#define CEC_ISR_BRE 0x00000008U /!< CEC Rx Bit Rising Error /
Kojto	122:f9eeca106725	3087	#define CEC_ISR_SBPE 0x00000010U /!< CEC Rx Short Bit period Error /
Kojto	122:f9eeca106725	3088	#define CEC_ISR_LBPE 0x00000020U /!< CEC Rx Long Bit period Error /
Kojto	122:f9eeca106725	3089	#define CEC_ISR_RXACKE 0x00000040U /!< CEC Rx Missing Acknowledge /
Kojto	122:f9eeca106725	3090	#define CEC_ISR_ARBLST 0x00000080U /!< CEC Arbitration Lost /
Kojto	122:f9eeca106725	3091	#define CEC_ISR_TXBR 0x00000100U /!< CEC Tx Byte Request /
Kojto	122:f9eeca106725	3092	#define CEC_ISR_TXEND 0x00000200U /!< CEC End of Transmission /
Kojto	122:f9eeca106725	3093	#define CEC_ISR_TXUDR 0x00000400U /!< CEC Tx-Buffer Underrun /
Kojto	122:f9eeca106725	3094	#define CEC_ISR_TXERR 0x00000800U /!< CEC Tx-Error /
Kojto	122:f9eeca106725	3095	#define CEC_ISR_TXACKE 0x00001000U /!< CEC Tx Missing Acknowledge /
Kojto	107:4f6c30876dfa	3096
Kojto	107:4f6c30876dfa	3097	/***************** Bit definition for CEC_IER register ******************/
Kojto	122:f9eeca106725	3098	#define CEC_IER_RXBRIE 0x00000001U /!< CEC Rx-Byte Received IT Enable /
Kojto	122:f9eeca106725	3099	#define CEC_IER_RXENDIE 0x00000002U /!< CEC End Of Reception IT Enable /
Kojto	122:f9eeca106725	3100	#define CEC_IER_RXOVRIE 0x00000004U /!< CEC Rx-Overrun IT Enable /
Kojto	122:f9eeca106725	3101	#define CEC_IER_BREIE 0x00000008U /!< CEC Rx Bit Rising Error IT Enable /
Kojto	122:f9eeca106725	3102	#define CEC_IER_SBPEIE 0x00000010U /!< CEC Rx Short Bit period Error IT Enable/
Kojto	122:f9eeca106725	3103	#define CEC_IER_LBPEIE 0x00000020U /!< CEC Rx Long Bit period Error IT Enable /
Kojto	122:f9eeca106725	3104	#define CEC_IER_RXACKEIE 0x00000040U /!< CEC Rx Missing Acknowledge IT Enable /
Kojto	122:f9eeca106725	3105	#define CEC_IER_ARBLSTIE 0x00000080U /!< CEC Arbitration Lost IT Enable /
Kojto	122:f9eeca106725	3106	#define CEC_IER_TXBRIE 0x00000100U /!< CEC Tx Byte Request IT Enable /
Kojto	122:f9eeca106725	3107	#define CEC_IER_TXENDIE 0x00000200U /!< CEC End of Transmission IT Enable /
Kojto	122:f9eeca106725	3108	#define CEC_IER_TXUDRIE 0x00000400U /!< CEC Tx-Buffer Underrun IT Enable /
Kojto	122:f9eeca106725	3109	#define CEC_IER_TXERRIE 0x00000800U /!< CEC Tx-Error IT Enable /
Kojto	122:f9eeca106725	3110	#define CEC_IER_TXACKEIE 0x00001000U /!< CEC Tx Missing Acknowledge IT Enable /
Kojto	107:4f6c30876dfa	3111
Kojto	107:4f6c30876dfa	3112	/******************************************************************************/
Kojto	107:4f6c30876dfa	3113	/* */
Kojto	107:4f6c30876dfa	3114	/* CRC calculation unit */
Kojto	107:4f6c30876dfa	3115	/* */
Kojto	107:4f6c30876dfa	3116	/******************************************************************************/
Kojto	107:4f6c30876dfa	3117	/***************** Bit definition for CRC_DR register *******************/
Kojto	122:f9eeca106725	3118	#define CRC_DR_DR 0xFFFFFFFFU /!< Data register bits /
Kojto	107:4f6c30876dfa	3119
Kojto	107:4f6c30876dfa	3120	/***************** Bit definition for CRC_IDR register ******************/
Kojto	122:f9eeca106725	3121	#define CRC_IDR_IDR 0x000000FFU /!< General-purpose 8-bit data register bits /
Kojto	107:4f6c30876dfa	3122
Kojto	107:4f6c30876dfa	3123	/****************** Bit definition for CRC_CR register ******************/
Kojto	122:f9eeca106725	3124	#define CRC_CR_RESET 0x00000001U /!< RESET the CRC computation unit bit /
Kojto	122:f9eeca106725	3125	#define CRC_CR_POLYSIZE 0x00000018U /!< Polynomial size bits /
Kojto	122:f9eeca106725	3126	#define CRC_CR_POLYSIZE_0 0x00000008U /!< Polynomial size bit 0 /
Kojto	122:f9eeca106725	3127	#define CRC_CR_POLYSIZE_1 0x00000010U /!< Polynomial size bit 1 /
Kojto	122:f9eeca106725	3128	#define CRC_CR_REV_IN 0x00000060U /!< REV_IN Reverse Input Data bits /
Kojto	122:f9eeca106725	3129	#define CRC_CR_REV_IN_0 0x00000020U /!< Bit 0 /
Kojto	122:f9eeca106725	3130	#define CRC_CR_REV_IN_1 0x00000040U /!< Bit 1 /
Kojto	122:f9eeca106725	3131	#define CRC_CR_REV_OUT 0x00000080U /!< REV_OUT Reverse Output Data bits /
Kojto	107:4f6c30876dfa	3132
Kojto	107:4f6c30876dfa	3133	/***************** Bit definition for CRC_INIT register *****************/
Kojto	122:f9eeca106725	3134	#define CRC_INIT_INIT 0xFFFFFFFFU /!< Initial CRC value bits /
Kojto	107:4f6c30876dfa	3135
Kojto	107:4f6c30876dfa	3136	/***************** Bit definition for CRC_POL register ******************/
Kojto	122:f9eeca106725	3137	#define CRC_POL_POL 0xFFFFFFFFU /!< Coefficients of the polynomial /
Kojto	107:4f6c30876dfa	3138
Kojto	116:c0f6e94411f5	3139
Kojto	107:4f6c30876dfa	3140	/******************************************************************************/
Kojto	107:4f6c30876dfa	3141	/* */
Kojto	107:4f6c30876dfa	3142	/* Digital to Analog Converter */
Kojto	107:4f6c30876dfa	3143	/* */
Kojto	107:4f6c30876dfa	3144	/******************************************************************************/
Kojto	107:4f6c30876dfa	3145	/****************** Bit definition for DAC_CR register ******************/
Kojto	122:f9eeca106725	3146	#define DAC_CR_EN1 0x00000001U /!<DAC channel1 enable /
Kojto	122:f9eeca106725	3147	#define DAC_CR_BOFF1 0x00000002U /!<DAC channel1 output buffer disable /
Kojto	122:f9eeca106725	3148	#define DAC_CR_TEN1 0x00000004U /!<DAC channel1 Trigger enable /
Kojto	122:f9eeca106725	3149	#define DAC_CR_TSEL1 0x00000038U /!<TSEL1[2:0] (DAC channel1 Trigger selection) /
Kojto	122:f9eeca106725	3150	#define DAC_CR_TSEL1_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	3151	#define DAC_CR_TSEL1_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	3152	#define DAC_CR_TSEL1_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	3153	#define DAC_CR_WAVE1 0x000000C0U /!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enablEU) /
Kojto	122:f9eeca106725	3154	#define DAC_CR_WAVE1_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	3155	#define DAC_CR_WAVE1_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	3156	#define DAC_CR_MAMP1 0x00000F00U /!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) /
Kojto	122:f9eeca106725	3157	#define DAC_CR_MAMP1_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	3158	#define DAC_CR_MAMP1_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	3159	#define DAC_CR_MAMP1_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	3160	#define DAC_CR_MAMP1_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	3161	#define DAC_CR_DMAEN1 0x00001000U /!<DAC channel1 DMA enable /
Kojto	122:f9eeca106725	3162	#define DAC_CR_DMAUDRIE1 0x00002000U /!<DAC channel1 DMA underrun interrupt enable /
Kojto	122:f9eeca106725	3163	#define DAC_CR_EN2 0x00010000U /!<DAC channel2 enable /
Kojto	122:f9eeca106725	3164	#define DAC_CR_BOFF2 0x00020000U /!<DAC channel2 output buffer disable /
Kojto	122:f9eeca106725	3165	#define DAC_CR_TEN2 0x00040000U /!<DAC channel2 Trigger enable /
Kojto	122:f9eeca106725	3166	#define DAC_CR_TSEL2 0x00380000U /!<TSEL2[2:0] (DAC channel2 Trigger selection) /
Kojto	122:f9eeca106725	3167	#define DAC_CR_TSEL2_0 0x00080000U /!<Bit 0 /
Kojto	122:f9eeca106725	3168	#define DAC_CR_TSEL2_1 0x00100000U /!<Bit 1 /
Kojto	122:f9eeca106725	3169	#define DAC_CR_TSEL2_2 0x00200000U /!<Bit 2 /
Kojto	122:f9eeca106725	3170	#define DAC_CR_WAVE2 0x00C00000U /!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) /
Kojto	122:f9eeca106725	3171	#define DAC_CR_WAVE2_0 0x00400000U /!<Bit 0 /
Kojto	122:f9eeca106725	3172	#define DAC_CR_WAVE2_1 0x00800000U /!<Bit 1 /
Kojto	122:f9eeca106725	3173	#define DAC_CR_MAMP2 0x0F000000U /!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) /
Kojto	122:f9eeca106725	3174	#define DAC_CR_MAMP2_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	3175	#define DAC_CR_MAMP2_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	3176	#define DAC_CR_MAMP2_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	3177	#define DAC_CR_MAMP2_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	3178	#define DAC_CR_DMAEN2 0x10000000U /!<DAC channel2 DMA enable /
Kojto	122:f9eeca106725	3179	#define DAC_CR_DMAUDRIE2 0x20000000U /!<DAC channel2 DMA underrun interrupt enable /
Kojto	107:4f6c30876dfa	3180
Kojto	107:4f6c30876dfa	3181	/*************** Bit definition for DAC_SWTRIGR register ****************/
Kojto	122:f9eeca106725	3182	#define DAC_SWTRIGR_SWTRIG1 0x01U /!<DAC channel1 software trigger /
Kojto	122:f9eeca106725	3183	#define DAC_SWTRIGR_SWTRIG2 0x02U /!<DAC channel2 software trigger /
Kojto	107:4f6c30876dfa	3184
Kojto	107:4f6c30876dfa	3185	/*************** Bit definition for DAC_DHR12R1 register ****************/
Kojto	122:f9eeca106725	3186	#define DAC_DHR12R1_DACC1DHR 0x0FFFU /!<DAC channel1 12-bit Right aligned data /
Kojto	107:4f6c30876dfa	3187
Kojto	107:4f6c30876dfa	3188	/*************** Bit definition for DAC_DHR12L1 register ****************/
Kojto	122:f9eeca106725	3189	#define DAC_DHR12L1_DACC1DHR 0xFFF0U /!<DAC channel1 12-bit Left aligned data /
Kojto	107:4f6c30876dfa	3190
Kojto	107:4f6c30876dfa	3191	/**************** Bit definition for DAC_DHR8R1 register ****************/
Kojto	122:f9eeca106725	3192	#define DAC_DHR8R1_DACC1DHR 0xFFU /!<DAC channel1 8-bit Right aligned data /
Kojto	107:4f6c30876dfa	3193
Kojto	107:4f6c30876dfa	3194	/*************** Bit definition for DAC_DHR12R2 register ****************/
Kojto	122:f9eeca106725	3195	#define DAC_DHR12R2_DACC2DHR 0x0FFFU /!<DAC channel2 12-bit Right aligned data /
Kojto	107:4f6c30876dfa	3196
Kojto	107:4f6c30876dfa	3197	/*************** Bit definition for DAC_DHR12L2 register ****************/
Kojto	122:f9eeca106725	3198	#define DAC_DHR12L2_DACC2DHR 0xFFF0U /!<DAC channel2 12-bit Left aligned data /
Kojto	107:4f6c30876dfa	3199
Kojto	107:4f6c30876dfa	3200	/**************** Bit definition for DAC_DHR8R2 register ****************/
Kojto	122:f9eeca106725	3201	#define DAC_DHR8R2_DACC2DHR 0xFFU /!<DAC channel2 8-bit Right aligned data /
Kojto	107:4f6c30876dfa	3202
Kojto	107:4f6c30876dfa	3203	/*************** Bit definition for DAC_DHR12RD register ****************/
Kojto	122:f9eeca106725	3204	#define DAC_DHR12RD_DACC1DHR 0x00000FFFU /!<DAC channel1 12-bit Right aligned data /
Kojto	122:f9eeca106725	3205	#define DAC_DHR12RD_DACC2DHR 0x0FFF0000U /!<DAC channel2 12-bit Right aligned data /
Kojto	107:4f6c30876dfa	3206
Kojto	107:4f6c30876dfa	3207	/*************** Bit definition for DAC_DHR12LD register ****************/
Kojto	122:f9eeca106725	3208	#define DAC_DHR12LD_DACC1DHR 0x0000FFF0U /!<DAC channel1 12-bit Left aligned data /
Kojto	122:f9eeca106725	3209	#define DAC_DHR12LD_DACC2DHR 0xFFF00000U /!<DAC channel2 12-bit Left aligned data /
Kojto	107:4f6c30876dfa	3210
Kojto	107:4f6c30876dfa	3211	/**************** Bit definition for DAC_DHR8RD register ****************/
Kojto	122:f9eeca106725	3212	#define DAC_DHR8RD_DACC1DHR 0x00FFU /!<DAC channel1 8-bit Right aligned data /
Kojto	122:f9eeca106725	3213	#define DAC_DHR8RD_DACC2DHR 0xFF00U /!<DAC channel2 8-bit Right aligned data /
Kojto	107:4f6c30876dfa	3214
Kojto	107:4f6c30876dfa	3215	/***************** Bit definition for DAC_DOR1 register *****************/
Kojto	122:f9eeca106725	3216	#define DAC_DOR1_DACC1DOR 0x0FFFU /!<DAC channel1 data output /
Kojto	107:4f6c30876dfa	3217
Kojto	107:4f6c30876dfa	3218	/***************** Bit definition for DAC_DOR2 register *****************/
Kojto	122:f9eeca106725	3219	#define DAC_DOR2_DACC2DOR 0x0FFFU /!<DAC channel2 data output /
Kojto	107:4f6c30876dfa	3220
Kojto	107:4f6c30876dfa	3221	/****************** Bit definition for DAC_SR register ******************/
Kojto	122:f9eeca106725	3222	#define DAC_SR_DMAUDR1 0x00002000U /!<DAC channel1 DMA underrun flag /
Kojto	122:f9eeca106725	3223	#define DAC_SR_DMAUDR2 0x20000000U /!<DAC channel2 DMA underrun flag /
Kojto	107:4f6c30876dfa	3224
Kojto	116:c0f6e94411f5	3225
Kojto	107:4f6c30876dfa	3226	/******************************************************************************/
Kojto	107:4f6c30876dfa	3227	/* */
Kojto	107:4f6c30876dfa	3228	/* Debug MCU */
Kojto	107:4f6c30876dfa	3229	/* */
Kojto	107:4f6c30876dfa	3230	/******************************************************************************/
Kojto	107:4f6c30876dfa	3231
Kojto	107:4f6c30876dfa	3232	/******************************************************************************/
Kojto	107:4f6c30876dfa	3233	/* */
Kojto	107:4f6c30876dfa	3234	/* DCMI */
Kojto	107:4f6c30876dfa	3235	/* */
Kojto	107:4f6c30876dfa	3236	/******************************************************************************/
Kojto	107:4f6c30876dfa	3237	/****************** Bits definition for DCMI_CR register ****************/
Kojto	122:f9eeca106725	3238	#define DCMI_CR_CAPTURE 0x00000001U
Kojto	122:f9eeca106725	3239	#define DCMI_CR_CM 0x00000002U
Kojto	122:f9eeca106725	3240	#define DCMI_CR_CROP 0x00000004U
Kojto	122:f9eeca106725	3241	#define DCMI_CR_JPEG 0x00000008U
Kojto	122:f9eeca106725	3242	#define DCMI_CR_ESS 0x00000010U
Kojto	122:f9eeca106725	3243	#define DCMI_CR_PCKPOL 0x00000020U
Kojto	122:f9eeca106725	3244	#define DCMI_CR_HSPOL 0x00000040U
Kojto	122:f9eeca106725	3245	#define DCMI_CR_VSPOL 0x00000080U
Kojto	122:f9eeca106725	3246	#define DCMI_CR_FCRC_0 0x00000100U
Kojto	122:f9eeca106725	3247	#define DCMI_CR_FCRC_1 0x00000200U
Kojto	122:f9eeca106725	3248	#define DCMI_CR_EDM_0 0x00000400U
Kojto	122:f9eeca106725	3249	#define DCMI_CR_EDM_1 0x00000800U
Kojto	122:f9eeca106725	3250	#define DCMI_CR_CRE 0x00001000U
Kojto	122:f9eeca106725	3251	#define DCMI_CR_ENABLE 0x00004000U
Kojto	122:f9eeca106725	3252	#define DCMI_CR_BSM 0x00030000U
Kojto	122:f9eeca106725	3253	#define DCMI_CR_BSM_0 0x00010000U
Kojto	122:f9eeca106725	3254	#define DCMI_CR_BSM_1 0x00020000U
Kojto	122:f9eeca106725	3255	#define DCMI_CR_OEBS 0x00040000U
Kojto	122:f9eeca106725	3256	#define DCMI_CR_LSM 0x00080000U
Kojto	122:f9eeca106725	3257	#define DCMI_CR_OELS 0x00100000U
Kojto	107:4f6c30876dfa	3258
Kojto	107:4f6c30876dfa	3259	/****************** Bits definition for DCMI_SR register ****************/
Kojto	122:f9eeca106725	3260	#define DCMI_SR_HSYNC 0x00000001U
Kojto	122:f9eeca106725	3261	#define DCMI_SR_VSYNC 0x00000002U
Kojto	122:f9eeca106725	3262	#define DCMI_SR_FNE 0x00000004U
Kojto	122:f9eeca106725	3263
Kojto	122:f9eeca106725	3264	/****************** Bits definition for DCMI_RIS register **************/
Kojto	122:f9eeca106725	3265	#define DCMI_RIS_FRAME_RIS 0x00000001U
Kojto	122:f9eeca106725	3266	#define DCMI_RIS_OVR_RIS 0x00000002U
Kojto	122:f9eeca106725	3267	#define DCMI_RIS_ERR_RIS 0x00000004U
Kojto	122:f9eeca106725	3268	#define DCMI_RIS_VSYNC_RIS 0x00000008U
Kojto	122:f9eeca106725	3269	#define DCMI_RIS_LINE_RIS 0x00000010U
Kojto	122:f9eeca106725	3270
Kojto	122:f9eeca106725	3271	/* Legacy defines */
Kojto	122:f9eeca106725	3272	#define DCMI_RISR_FRAME_RIS DCMI_RIS_FRAME_RIS
Kojto	122:f9eeca106725	3273	#define DCMI_RISR_OVF_RIS DCMI_RIS_OVR_RIS
Kojto	122:f9eeca106725	3274	#define DCMI_RISR_ERR_RIS DCMI_RIS_ERR_RIS
Kojto	122:f9eeca106725	3275	#define DCMI_RISR_VSYNC_RIS DCMI_RIS_VSYNC_RIS
Kojto	122:f9eeca106725	3276	#define DCMI_RISR_LINE_RIS DCMI_RIS_LINE_RIS
Kojto	107:4f6c30876dfa	3277
Kojto	107:4f6c30876dfa	3278	/****************** Bits definition for DCMI_IER register ***************/
Kojto	122:f9eeca106725	3279	#define DCMI_IER_FRAME_IE 0x00000001U
Kojto	122:f9eeca106725	3280	#define DCMI_IER_OVR_IE 0x00000002U
Kojto	122:f9eeca106725	3281	#define DCMI_IER_ERR_IE 0x00000004U
Kojto	122:f9eeca106725	3282	#define DCMI_IER_VSYNC_IE 0x00000008U
Kojto	122:f9eeca106725	3283	#define DCMI_IER_LINE_IE 0x00000010U
Kojto	122:f9eeca106725	3284
Kojto	122:f9eeca106725	3285	/* Legacy define */
Kojto	122:f9eeca106725	3286	#define DCMI_IER_OVF_IE DCMI_IER_OVR_IE
Kojto	122:f9eeca106725	3287
Kojto	122:f9eeca106725	3288	/****************** Bits definition for DCMI_MIS register ***************/
Kojto	122:f9eeca106725	3289	#define DCMI_MIS_FRAME_MIS 0x00000001U
Kojto	122:f9eeca106725	3290	#define DCMI_MIS_OVR_MIS 0x00000002U
Kojto	122:f9eeca106725	3291	#define DCMI_MIS_ERR_MIS 0x00000004U
Kojto	122:f9eeca106725	3292	#define DCMI_MIS_VSYNC_MIS 0x00000008U
Kojto	122:f9eeca106725	3293	#define DCMI_MIS_LINE_MIS 0x00000010U
Kojto	122:f9eeca106725	3294
Kojto	122:f9eeca106725	3295	/* Legacy defines */
Kojto	122:f9eeca106725	3296	#define DCMI_MISR_FRAME_MIS DCMI_MIS_FRAME_MIS
Kojto	122:f9eeca106725	3297	#define DCMI_MISR_OVF_MIS DCMI_MIS_OVR_MIS
Kojto	122:f9eeca106725	3298	#define DCMI_MISR_ERR_MIS DCMI_MIS_ERR_MIS
Kojto	122:f9eeca106725	3299	#define DCMI_MISR_VSYNC_MIS DCMI_MIS_VSYNC_MIS
Kojto	122:f9eeca106725	3300	#define DCMI_MISR_LINE_MIS DCMI_MIS_LINE_MIS
Kojto	107:4f6c30876dfa	3301
Kojto	107:4f6c30876dfa	3302	/****************** Bits definition for DCMI_ICR register ***************/
Kojto	122:f9eeca106725	3303	#define DCMI_ICR_FRAME_ISC 0x00000001U
Kojto	122:f9eeca106725	3304	#define DCMI_ICR_OVR_ISC 0x00000002U
Kojto	122:f9eeca106725	3305	#define DCMI_ICR_ERR_ISC 0x00000004U
Kojto	122:f9eeca106725	3306	#define DCMI_ICR_VSYNC_ISC 0x00000008U
Kojto	122:f9eeca106725	3307	#define DCMI_ICR_LINE_ISC 0x00000010U
Kojto	122:f9eeca106725	3308
Kojto	122:f9eeca106725	3309	/* Legacy defines */
Kojto	122:f9eeca106725	3310	#define DCMI_ICR_OVF_ISC DCMI_ICR_OVR_ISC
Kojto	122:f9eeca106725	3311
Kojto	122:f9eeca106725	3312	/****************** Bits definition for DCMI_ESCR register ****************/
Kojto	122:f9eeca106725	3313	#define DCMI_ESCR_FSC 0x000000FFU
Kojto	122:f9eeca106725	3314	#define DCMI_ESCR_LSC 0x0000FF00U
Kojto	122:f9eeca106725	3315	#define DCMI_ESCR_LEC 0x00FF0000U
Kojto	122:f9eeca106725	3316	#define DCMI_ESCR_FEC 0xFF000000U
Kojto	122:f9eeca106725	3317
Kojto	122:f9eeca106725	3318	/****************** Bits definition for DCMI_ESUR register ****************/
Kojto	122:f9eeca106725	3319	#define DCMI_ESUR_FSU 0x000000FFU
Kojto	122:f9eeca106725	3320	#define DCMI_ESUR_LSU 0x0000FF00U
Kojto	122:f9eeca106725	3321	#define DCMI_ESUR_LEU 0x00FF0000U
Kojto	122:f9eeca106725	3322	#define DCMI_ESUR_FEU 0xFF000000U
Kojto	122:f9eeca106725	3323
Kojto	122:f9eeca106725	3324	/****************** Bits definition for DCMI_CWSTRT register ****************/
Kojto	122:f9eeca106725	3325	#define DCMI_CWSTRT_HOFFCNT 0x00003FFFU
Kojto	122:f9eeca106725	3326	#define DCMI_CWSTRT_VST 0x1FFF0000U
Kojto	122:f9eeca106725	3327
Kojto	122:f9eeca106725	3328	/****************** Bits definition for DCMI_CWSIZE register ****************/
Kojto	122:f9eeca106725	3329	#define DCMI_CWSIZE_CAPCNT 0x00003FFFU
Kojto	122:f9eeca106725	3330	#define DCMI_CWSIZE_VLINE 0x3FFF0000U
Kojto	122:f9eeca106725	3331
Kojto	122:f9eeca106725	3332	/****************** Bits definition for DCMI_DR register ****************/
Kojto	122:f9eeca106725	3333	#define DCMI_DR_BYTE0 0x000000FFU
Kojto	122:f9eeca106725	3334	#define DCMI_DR_BYTE1 0x0000FF00U
Kojto	122:f9eeca106725	3335	#define DCMI_DR_BYTE2 0x00FF0000U
Kojto	122:f9eeca106725	3336	#define DCMI_DR_BYTE3 0xFF000000U
Kojto	107:4f6c30876dfa	3337
Kojto	107:4f6c30876dfa	3338	/******************************************************************************/
Kojto	107:4f6c30876dfa	3339	/* */
Kojto	107:4f6c30876dfa	3340	/* DMA Controller */
Kojto	107:4f6c30876dfa	3341	/* */
Kojto	107:4f6c30876dfa	3342	/******************************************************************************/
Kojto	107:4f6c30876dfa	3343	/****************** Bits definition for DMA_SxCR register ***************/
Kojto	122:f9eeca106725	3344	#define DMA_SxCR_CHSEL 0x0E000000U
Kojto	122:f9eeca106725	3345	#define DMA_SxCR_CHSEL_0 0x02000000U
Kojto	122:f9eeca106725	3346	#define DMA_SxCR_CHSEL_1 0x04000000U
Kojto	122:f9eeca106725	3347	#define DMA_SxCR_CHSEL_2 0x08000000U
Kojto	122:f9eeca106725	3348	#define DMA_SxCR_MBURST 0x01800000U
Kojto	122:f9eeca106725	3349	#define DMA_SxCR_MBURST_0 0x00800000U
Kojto	122:f9eeca106725	3350	#define DMA_SxCR_MBURST_1 0x01000000U
Kojto	122:f9eeca106725	3351	#define DMA_SxCR_PBURST 0x00600000U
Kojto	122:f9eeca106725	3352	#define DMA_SxCR_PBURST_0 0x00200000U
Kojto	122:f9eeca106725	3353	#define DMA_SxCR_PBURST_1 0x00400000U
Kojto	122:f9eeca106725	3354	#define DMA_SxCR_CT 0x00080000U
Kojto	122:f9eeca106725	3355	#define DMA_SxCR_DBM 0x00040000U
Kojto	122:f9eeca106725	3356	#define DMA_SxCR_PL 0x00030000U
Kojto	122:f9eeca106725	3357	#define DMA_SxCR_PL_0 0x00010000U
Kojto	122:f9eeca106725	3358	#define DMA_SxCR_PL_1 0x00020000U
Kojto	122:f9eeca106725	3359	#define DMA_SxCR_PINCOS 0x00008000U
Kojto	122:f9eeca106725	3360	#define DMA_SxCR_MSIZE 0x00006000U
Kojto	122:f9eeca106725	3361	#define DMA_SxCR_MSIZE_0 0x00002000U
Kojto	122:f9eeca106725	3362	#define DMA_SxCR_MSIZE_1 0x00004000U
Kojto	122:f9eeca106725	3363	#define DMA_SxCR_PSIZE 0x00001800U
Kojto	122:f9eeca106725	3364	#define DMA_SxCR_PSIZE_0 0x00000800U
Kojto	122:f9eeca106725	3365	#define DMA_SxCR_PSIZE_1 0x00001000U
Kojto	122:f9eeca106725	3366	#define DMA_SxCR_MINC 0x00000400U
Kojto	122:f9eeca106725	3367	#define DMA_SxCR_PINC 0x00000200U
Kojto	122:f9eeca106725	3368	#define DMA_SxCR_CIRC 0x00000100U
Kojto	122:f9eeca106725	3369	#define DMA_SxCR_DIR 0x000000C0U
Kojto	122:f9eeca106725	3370	#define DMA_SxCR_DIR_0 0x00000040U
Kojto	122:f9eeca106725	3371	#define DMA_SxCR_DIR_1 0x00000080U
Kojto	122:f9eeca106725	3372	#define DMA_SxCR_PFCTRL 0x00000020U
Kojto	122:f9eeca106725	3373	#define DMA_SxCR_TCIE 0x00000010U
Kojto	122:f9eeca106725	3374	#define DMA_SxCR_HTIE 0x00000008U
Kojto	122:f9eeca106725	3375	#define DMA_SxCR_TEIE 0x00000004U
Kojto	122:f9eeca106725	3376	#define DMA_SxCR_DMEIE 0x00000002U
Kojto	122:f9eeca106725	3377	#define DMA_SxCR_EN 0x00000001U
Kojto	107:4f6c30876dfa	3378
Kojto	107:4f6c30876dfa	3379	/****************** Bits definition for DMA_SxCNDTR register ************/
Kojto	122:f9eeca106725	3380	#define DMA_SxNDT 0x0000FFFFU
Kojto	122:f9eeca106725	3381	#define DMA_SxNDT_0 0x00000001U
Kojto	122:f9eeca106725	3382	#define DMA_SxNDT_1 0x00000002U
Kojto	122:f9eeca106725	3383	#define DMA_SxNDT_2 0x00000004U
Kojto	122:f9eeca106725	3384	#define DMA_SxNDT_3 0x00000008U
Kojto	122:f9eeca106725	3385	#define DMA_SxNDT_4 0x00000010U
Kojto	122:f9eeca106725	3386	#define DMA_SxNDT_5 0x00000020U
Kojto	122:f9eeca106725	3387	#define DMA_SxNDT_6 0x00000040U
Kojto	122:f9eeca106725	3388	#define DMA_SxNDT_7 0x00000080U
Kojto	122:f9eeca106725	3389	#define DMA_SxNDT_8 0x00000100U
Kojto	122:f9eeca106725	3390	#define DMA_SxNDT_9 0x00000200U
Kojto	122:f9eeca106725	3391	#define DMA_SxNDT_10 0x00000400U
Kojto	122:f9eeca106725	3392	#define DMA_SxNDT_11 0x00000800U
Kojto	122:f9eeca106725	3393	#define DMA_SxNDT_12 0x00001000U
Kojto	122:f9eeca106725	3394	#define DMA_SxNDT_13 0x00002000U
Kojto	122:f9eeca106725	3395	#define DMA_SxNDT_14 0x00004000U
Kojto	122:f9eeca106725	3396	#define DMA_SxNDT_15 0x00008000U
Kojto	107:4f6c30876dfa	3397
Kojto	107:4f6c30876dfa	3398	/****************** Bits definition for DMA_SxFCR register **************/
Kojto	122:f9eeca106725	3399	#define DMA_SxFCR_FEIE 0x00000080U
Kojto	122:f9eeca106725	3400	#define DMA_SxFCR_FS 0x00000038U
Kojto	122:f9eeca106725	3401	#define DMA_SxFCR_FS_0 0x00000008U
Kojto	122:f9eeca106725	3402	#define DMA_SxFCR_FS_1 0x00000010U
Kojto	122:f9eeca106725	3403	#define DMA_SxFCR_FS_2 0x00000020U
Kojto	122:f9eeca106725	3404	#define DMA_SxFCR_DMDIS 0x00000004U
Kojto	122:f9eeca106725	3405	#define DMA_SxFCR_FTH 0x00000003U
Kojto	122:f9eeca106725	3406	#define DMA_SxFCR_FTH_0 0x00000001U
Kojto	122:f9eeca106725	3407	#define DMA_SxFCR_FTH_1 0x00000002U
Kojto	107:4f6c30876dfa	3408
Kojto	107:4f6c30876dfa	3409	/****************** Bits definition for DMA_LISR register ***************/
Kojto	122:f9eeca106725	3410	#define DMA_LISR_TCIF3 0x08000000U
Kojto	122:f9eeca106725	3411	#define DMA_LISR_HTIF3 0x04000000U
Kojto	122:f9eeca106725	3412	#define DMA_LISR_TEIF3 0x02000000U
Kojto	122:f9eeca106725	3413	#define DMA_LISR_DMEIF3 0x01000000U
Kojto	122:f9eeca106725	3414	#define DMA_LISR_FEIF3 0x00400000U
Kojto	122:f9eeca106725	3415	#define DMA_LISR_TCIF2 0x00200000U
Kojto	122:f9eeca106725	3416	#define DMA_LISR_HTIF2 0x00100000U
Kojto	122:f9eeca106725	3417	#define DMA_LISR_TEIF2 0x00080000U
Kojto	122:f9eeca106725	3418	#define DMA_LISR_DMEIF2 0x00040000U
Kojto	122:f9eeca106725	3419	#define DMA_LISR_FEIF2 0x00010000U
Kojto	122:f9eeca106725	3420	#define DMA_LISR_TCIF1 0x00000800U
Kojto	122:f9eeca106725	3421	#define DMA_LISR_HTIF1 0x00000400U
Kojto	122:f9eeca106725	3422	#define DMA_LISR_TEIF1 0x00000200U
Kojto	122:f9eeca106725	3423	#define DMA_LISR_DMEIF1 0x00000100U
Kojto	122:f9eeca106725	3424	#define DMA_LISR_FEIF1 0x00000040U
Kojto	122:f9eeca106725	3425	#define DMA_LISR_TCIF0 0x00000020U
Kojto	122:f9eeca106725	3426	#define DMA_LISR_HTIF0 0x00000010U
Kojto	122:f9eeca106725	3427	#define DMA_LISR_TEIF0 0x00000008U
Kojto	122:f9eeca106725	3428	#define DMA_LISR_DMEIF0 0x00000004U
Kojto	122:f9eeca106725	3429	#define DMA_LISR_FEIF0 0x00000001U
Kojto	107:4f6c30876dfa	3430
Kojto	107:4f6c30876dfa	3431	/****************** Bits definition for DMA_HISR register ***************/
Kojto	122:f9eeca106725	3432	#define DMA_HISR_TCIF7 0x08000000U
Kojto	122:f9eeca106725	3433	#define DMA_HISR_HTIF7 0x04000000U
Kojto	122:f9eeca106725	3434	#define DMA_HISR_TEIF7 0x02000000U
Kojto	122:f9eeca106725	3435	#define DMA_HISR_DMEIF7 0x01000000U
Kojto	122:f9eeca106725	3436	#define DMA_HISR_FEIF7 0x00400000U
Kojto	122:f9eeca106725	3437	#define DMA_HISR_TCIF6 0x00200000U
Kojto	122:f9eeca106725	3438	#define DMA_HISR_HTIF6 0x00100000U
Kojto	122:f9eeca106725	3439	#define DMA_HISR_TEIF6 0x00080000U
Kojto	122:f9eeca106725	3440	#define DMA_HISR_DMEIF6 0x00040000U
Kojto	122:f9eeca106725	3441	#define DMA_HISR_FEIF6 0x00010000U
Kojto	122:f9eeca106725	3442	#define DMA_HISR_TCIF5 0x00000800U
Kojto	122:f9eeca106725	3443	#define DMA_HISR_HTIF5 0x00000400U
Kojto	122:f9eeca106725	3444	#define DMA_HISR_TEIF5 0x00000200U
Kojto	122:f9eeca106725	3445	#define DMA_HISR_DMEIF5 0x00000100U
Kojto	122:f9eeca106725	3446	#define DMA_HISR_FEIF5 0x00000040U
Kojto	122:f9eeca106725	3447	#define DMA_HISR_TCIF4 0x00000020U
Kojto	122:f9eeca106725	3448	#define DMA_HISR_HTIF4 0x00000010U
Kojto	122:f9eeca106725	3449	#define DMA_HISR_TEIF4 0x00000008U
Kojto	122:f9eeca106725	3450	#define DMA_HISR_DMEIF4 0x00000004U
Kojto	122:f9eeca106725	3451	#define DMA_HISR_FEIF4 0x00000001U
Kojto	107:4f6c30876dfa	3452
Kojto	107:4f6c30876dfa	3453	/****************** Bits definition for DMA_LIFCR register **************/
Kojto	122:f9eeca106725	3454	#define DMA_LIFCR_CTCIF3 0x08000000U
Kojto	122:f9eeca106725	3455	#define DMA_LIFCR_CHTIF3 0x04000000U
Kojto	122:f9eeca106725	3456	#define DMA_LIFCR_CTEIF3 0x02000000U
Kojto	122:f9eeca106725	3457	#define DMA_LIFCR_CDMEIF3 0x01000000U
Kojto	122:f9eeca106725	3458	#define DMA_LIFCR_CFEIF3 0x00400000U
Kojto	122:f9eeca106725	3459	#define DMA_LIFCR_CTCIF2 0x00200000U
Kojto	122:f9eeca106725	3460	#define DMA_LIFCR_CHTIF2 0x00100000U
Kojto	122:f9eeca106725	3461	#define DMA_LIFCR_CTEIF2 0x00080000U
Kojto	122:f9eeca106725	3462	#define DMA_LIFCR_CDMEIF2 0x00040000U
Kojto	122:f9eeca106725	3463	#define DMA_LIFCR_CFEIF2 0x00010000U
Kojto	122:f9eeca106725	3464	#define DMA_LIFCR_CTCIF1 0x00000800U
Kojto	122:f9eeca106725	3465	#define DMA_LIFCR_CHTIF1 0x00000400U
Kojto	122:f9eeca106725	3466	#define DMA_LIFCR_CTEIF1 0x00000200U
Kojto	122:f9eeca106725	3467	#define DMA_LIFCR_CDMEIF1 0x00000100U
Kojto	122:f9eeca106725	3468	#define DMA_LIFCR_CFEIF1 0x00000040U
Kojto	122:f9eeca106725	3469	#define DMA_LIFCR_CTCIF0 0x00000020U
Kojto	122:f9eeca106725	3470	#define DMA_LIFCR_CHTIF0 0x00000010U
Kojto	122:f9eeca106725	3471	#define DMA_LIFCR_CTEIF0 0x00000008U
Kojto	122:f9eeca106725	3472	#define DMA_LIFCR_CDMEIF0 0x00000004U
Kojto	122:f9eeca106725	3473	#define DMA_LIFCR_CFEIF0 0x00000001U
Kojto	107:4f6c30876dfa	3474
Kojto	107:4f6c30876dfa	3475	/****************** Bits definition for DMA_HIFCR register **************/
Kojto	122:f9eeca106725	3476	#define DMA_HIFCR_CTCIF7 0x08000000U
Kojto	122:f9eeca106725	3477	#define DMA_HIFCR_CHTIF7 0x04000000U
Kojto	122:f9eeca106725	3478	#define DMA_HIFCR_CTEIF7 0x02000000U
Kojto	122:f9eeca106725	3479	#define DMA_HIFCR_CDMEIF7 0x01000000U
Kojto	122:f9eeca106725	3480	#define DMA_HIFCR_CFEIF7 0x00400000U
Kojto	122:f9eeca106725	3481	#define DMA_HIFCR_CTCIF6 0x00200000U
Kojto	122:f9eeca106725	3482	#define DMA_HIFCR_CHTIF6 0x00100000U
Kojto	122:f9eeca106725	3483	#define DMA_HIFCR_CTEIF6 0x00080000U
Kojto	122:f9eeca106725	3484	#define DMA_HIFCR_CDMEIF6 0x00040000U
Kojto	122:f9eeca106725	3485	#define DMA_HIFCR_CFEIF6 0x00010000U
Kojto	122:f9eeca106725	3486	#define DMA_HIFCR_CTCIF5 0x00000800U
Kojto	122:f9eeca106725	3487	#define DMA_HIFCR_CHTIF5 0x00000400U
Kojto	122:f9eeca106725	3488	#define DMA_HIFCR_CTEIF5 0x00000200U
Kojto	122:f9eeca106725	3489	#define DMA_HIFCR_CDMEIF5 0x00000100U
Kojto	122:f9eeca106725	3490	#define DMA_HIFCR_CFEIF5 0x00000040U
Kojto	122:f9eeca106725	3491	#define DMA_HIFCR_CTCIF4 0x00000020U
Kojto	122:f9eeca106725	3492	#define DMA_HIFCR_CHTIF4 0x00000010U
Kojto	122:f9eeca106725	3493	#define DMA_HIFCR_CTEIF4 0x00000008U
Kojto	122:f9eeca106725	3494	#define DMA_HIFCR_CDMEIF4 0x00000004U
Kojto	122:f9eeca106725	3495	#define DMA_HIFCR_CFEIF4 0x00000001U
Kojto	107:4f6c30876dfa	3496
Kojto	107:4f6c30876dfa	3497	/******************************************************************************/
Kojto	107:4f6c30876dfa	3498	/* */
Kojto	107:4f6c30876dfa	3499	/* AHB Master DMA2D Controller (DMA2D) */
Kojto	107:4f6c30876dfa	3500	/* */
Kojto	107:4f6c30876dfa	3501	/******************************************************************************/
Kojto	107:4f6c30876dfa	3502
Kojto	107:4f6c30876dfa	3503	/****************** Bit definition for DMA2D_CR register ****************/
Kojto	107:4f6c30876dfa	3504
Kojto	122:f9eeca106725	3505	#define DMA2D_CR_START 0x00000001U /!< Start transfer /
Kojto	122:f9eeca106725	3506	#define DMA2D_CR_SUSP 0x00000002U /!< Suspend transfer /
Kojto	122:f9eeca106725	3507	#define DMA2D_CR_ABORT 0x00000004U /!< Abort transfer /
Kojto	122:f9eeca106725	3508	#define DMA2D_CR_TEIE 0x00000100U /!< Transfer Error Interrupt Enable /
Kojto	122:f9eeca106725	3509	#define DMA2D_CR_TCIE 0x00000200U /!< Transfer Complete Interrupt Enable /
Kojto	122:f9eeca106725	3510	#define DMA2D_CR_TWIE 0x00000400U /!< Transfer Watermark Interrupt Enable /
Kojto	122:f9eeca106725	3511	#define DMA2D_CR_CAEIE 0x00000800U /!< CLUT Access Error Interrupt Enable /
Kojto	122:f9eeca106725	3512	#define DMA2D_CR_CTCIE 0x00001000U /!< CLUT Transfer Complete Interrupt Enable /
Kojto	122:f9eeca106725	3513	#define DMA2D_CR_CEIE 0x00002000U /!< Configuration Error Interrupt Enable /
Kojto	122:f9eeca106725	3514	#define DMA2D_CR_MODE 0x00030000U /!< DMA2D Mode[1:0] /
Kojto	122:f9eeca106725	3515	#define DMA2D_CR_MODE_0 0x00010000U /!< DMA2D Mode bit 0 /
Kojto	122:f9eeca106725	3516	#define DMA2D_CR_MODE_1 0x00020000U /!< DMA2D Mode bit 1 /
Kojto	107:4f6c30876dfa	3517
Kojto	107:4f6c30876dfa	3518	/****************** Bit definition for DMA2D_ISR register ***************/
Kojto	107:4f6c30876dfa	3519
Kojto	122:f9eeca106725	3520	#define DMA2D_ISR_TEIF 0x00000001U /!< Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	3521	#define DMA2D_ISR_TCIF 0x00000002U /!< Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3522	#define DMA2D_ISR_TWIF 0x00000004U /!< Transfer Watermark Interrupt Flag /
Kojto	122:f9eeca106725	3523	#define DMA2D_ISR_CAEIF 0x00000008U /!< CLUT Access Error Interrupt Flag /
Kojto	122:f9eeca106725	3524	#define DMA2D_ISR_CTCIF 0x00000010U /!< CLUT Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3525	#define DMA2D_ISR_CEIF 0x00000020U /!< Configuration Error Interrupt Flag /
Kojto	122:f9eeca106725	3526
Kojto	122:f9eeca106725	3527	/****************** Bit definition for DMA2D_IFCR register **************/
Kojto	122:f9eeca106725	3528
Kojto	122:f9eeca106725	3529	#define DMA2D_IFCR_CTEIF 0x00000001U /!< Clears Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	3530	#define DMA2D_IFCR_CTCIF 0x00000002U /!< Clears Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3531	#define DMA2D_IFCR_CTWIF 0x00000004U /!< Clears Transfer Watermark Interrupt Flag /
Kojto	122:f9eeca106725	3532	#define DMA2D_IFCR_CAECIF 0x00000008U /!< Clears CLUT Access Error Interrupt Flag /
Kojto	122:f9eeca106725	3533	#define DMA2D_IFCR_CCTCIF 0x00000010U /!< Clears CLUT Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3534	#define DMA2D_IFCR_CCEIF 0x00000020U /!< Clears Configuration Error Interrupt Flag /
Kojto	122:f9eeca106725	3535
Kojto	122:f9eeca106725	3536	/* Legacy defines */
Kojto	122:f9eeca106725	3537	#define DMA2D_IFSR_CTEIF DMA2D_IFCR_CTEIF /!< Clears Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	3538	#define DMA2D_IFSR_CTCIF DMA2D_IFCR_CTCIF /!< Clears Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3539	#define DMA2D_IFSR_CTWIF DMA2D_IFCR_CTWIF /!< Clears Transfer Watermark Interrupt Flag /
Kojto	122:f9eeca106725	3540	#define DMA2D_IFSR_CCAEIF DMA2D_IFCR_CAECIF /!< Clears CLUT Access Error Interrupt Flag /
Kojto	122:f9eeca106725	3541	#define DMA2D_IFSR_CCTCIF DMA2D_IFCR_CCTCIF /!< Clears CLUT Transfer Complete Interrupt Flag /
Kojto	122:f9eeca106725	3542	#define DMA2D_IFSR_CCEIF DMA2D_IFCR_CCEIF /!< Clears Configuration Error Interrupt Flag /
Kojto	107:4f6c30876dfa	3543
Kojto	107:4f6c30876dfa	3544	/****************** Bit definition for DMA2D_FGMAR register *************/
Kojto	107:4f6c30876dfa	3545
Kojto	122:f9eeca106725	3546	#define DMA2D_FGMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	107:4f6c30876dfa	3547
Kojto	107:4f6c30876dfa	3548	/****************** Bit definition for DMA2D_FGOR register **************/
Kojto	107:4f6c30876dfa	3549
Kojto	122:f9eeca106725	3550	#define DMA2D_FGOR_LO 0x00003FFFU /!< Line Offset /
Kojto	107:4f6c30876dfa	3551
Kojto	107:4f6c30876dfa	3552	/****************** Bit definition for DMA2D_BGMAR register *************/
Kojto	107:4f6c30876dfa	3553
Kojto	122:f9eeca106725	3554	#define DMA2D_BGMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	107:4f6c30876dfa	3555
Kojto	107:4f6c30876dfa	3556	/****************** Bit definition for DMA2D_BGOR register **************/
Kojto	107:4f6c30876dfa	3557
Kojto	122:f9eeca106725	3558	#define DMA2D_BGOR_LO 0x00003FFFU /!< Line Offset /
Kojto	107:4f6c30876dfa	3559
Kojto	107:4f6c30876dfa	3560	/****************** Bit definition for DMA2D_FGPFCCR register ***********/
Kojto	107:4f6c30876dfa	3561
Kojto	122:f9eeca106725	3562	#define DMA2D_FGPFCCR_CM 0x0000000FU /!< Input color mode CM[3:0] /
Kojto	122:f9eeca106725	3563	#define DMA2D_FGPFCCR_CM_0 0x00000001U /!< Input color mode CM bit 0 /
Kojto	122:f9eeca106725	3564	#define DMA2D_FGPFCCR_CM_1 0x00000002U /!< Input color mode CM bit 1 /
Kojto	122:f9eeca106725	3565	#define DMA2D_FGPFCCR_CM_2 0x00000004U /!< Input color mode CM bit 2 /
Kojto	122:f9eeca106725	3566	#define DMA2D_FGPFCCR_CM_3 0x00000008U /!< Input color mode CM bit 3 /
Kojto	122:f9eeca106725	3567	#define DMA2D_FGPFCCR_CCM 0x00000010U /!< CLUT Color mode /
Kojto	122:f9eeca106725	3568	#define DMA2D_FGPFCCR_START 0x00000020U /!< Start /
Kojto	122:f9eeca106725	3569	#define DMA2D_FGPFCCR_CS 0x0000FF00U /!< CLUT size /
Kojto	122:f9eeca106725	3570	#define DMA2D_FGPFCCR_AM 0x00030000U /!< Alpha mode AM[1:0] /
Kojto	122:f9eeca106725	3571	#define DMA2D_FGPFCCR_AM_0 0x00010000U /!< Alpha mode AM bit 0 /
Kojto	122:f9eeca106725	3572	#define DMA2D_FGPFCCR_AM_1 0x00020000U /!< Alpha mode AM bit 1 /
Kojto	122:f9eeca106725	3573	#define DMA2D_FGPFCCR_ALPHA 0xFF000000U /!< Alpha value /
Kojto	107:4f6c30876dfa	3574
Kojto	107:4f6c30876dfa	3575	/****************** Bit definition for DMA2D_FGCOLR register ************/
Kojto	107:4f6c30876dfa	3576
Kojto	122:f9eeca106725	3577	#define DMA2D_FGCOLR_BLUE 0x000000FFU /!< Blue Value /
Kojto	122:f9eeca106725	3578	#define DMA2D_FGCOLR_GREEN 0x0000FF00U /!< Green Value /
Kojto	122:f9eeca106725	3579	#define DMA2D_FGCOLR_RED 0x00FF0000U /!< Red Value /
Kojto	107:4f6c30876dfa	3580
Kojto	107:4f6c30876dfa	3581	/****************** Bit definition for DMA2D_BGPFCCR register ***********/
Kojto	107:4f6c30876dfa	3582
Kojto	122:f9eeca106725	3583	#define DMA2D_BGPFCCR_CM 0x0000000FU /!< Input color mode CM[3:0] /
Kojto	122:f9eeca106725	3584	#define DMA2D_BGPFCCR_CM_0 0x00000001U /!< Input color mode CM bit 0 /
Kojto	122:f9eeca106725	3585	#define DMA2D_BGPFCCR_CM_1 0x00000002U /!< Input color mode CM bit 1 /
Kojto	122:f9eeca106725	3586	#define DMA2D_BGPFCCR_CM_2 0x00000004U /!< Input color mode CM bit 2 /
Kojto	122:f9eeca106725	3587	#define DMA2D_FGPFCCR_CM_3 0x00000008U /!< Input color mode CM bit 3 /
Kojto	122:f9eeca106725	3588	#define DMA2D_BGPFCCR_CCM 0x00000010U /!< CLUT Color mode /
Kojto	122:f9eeca106725	3589	#define DMA2D_BGPFCCR_START 0x00000020U /!< Start /
Kojto	122:f9eeca106725	3590	#define DMA2D_BGPFCCR_CS 0x0000FF00U /!< CLUT size /
Kojto	122:f9eeca106725	3591	#define DMA2D_BGPFCCR_AM 0x00030000U /!< Alpha mode AM[1:0] /
Kojto	122:f9eeca106725	3592	#define DMA2D_BGPFCCR_AM_0 0x00010000U /!< Alpha mode AM bit 0 /
Kojto	122:f9eeca106725	3593	#define DMA2D_BGPFCCR_AM_1 0x00020000U /!< Alpha mode AM bit 1 /
Kojto	122:f9eeca106725	3594	#define DMA2D_BGPFCCR_ALPHA 0xFF000000U /!< background Input Alpha value /
Kojto	107:4f6c30876dfa	3595
Kojto	107:4f6c30876dfa	3596	/****************** Bit definition for DMA2D_BGCOLR register ************/
Kojto	107:4f6c30876dfa	3597
Kojto	122:f9eeca106725	3598	#define DMA2D_BGCOLR_BLUE 0x000000FFU /!< Blue Value /
Kojto	122:f9eeca106725	3599	#define DMA2D_BGCOLR_GREEN 0x0000FF00U /!< Green Value /
Kojto	122:f9eeca106725	3600	#define DMA2D_BGCOLR_RED 0x00FF0000U /!< Red Value /
Kojto	107:4f6c30876dfa	3601
Kojto	107:4f6c30876dfa	3602	/****************** Bit definition for DMA2D_FGCMAR register ************/
Kojto	107:4f6c30876dfa	3603
Kojto	122:f9eeca106725	3604	#define DMA2D_FGCMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	107:4f6c30876dfa	3605
Kojto	107:4f6c30876dfa	3606	/****************** Bit definition for DMA2D_BGCMAR register ************/
Kojto	107:4f6c30876dfa	3607
Kojto	122:f9eeca106725	3608	#define DMA2D_BGCMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	107:4f6c30876dfa	3609
Kojto	107:4f6c30876dfa	3610	/****************** Bit definition for DMA2D_OPFCCR register ************/
Kojto	107:4f6c30876dfa	3611
Kojto	122:f9eeca106725	3612	#define DMA2D_OPFCCR_CM 0x00000007U /!< Color mode CM[2:0] /
Kojto	122:f9eeca106725	3613	#define DMA2D_OPFCCR_CM_0 0x00000001U /!< Color mode CM bit 0 /
Kojto	122:f9eeca106725	3614	#define DMA2D_OPFCCR_CM_1 0x00000002U /!< Color mode CM bit 1 /
Kojto	122:f9eeca106725	3615	#define DMA2D_OPFCCR_CM_2 0x00000004U /!< Color mode CM bit 2 /
Kojto	107:4f6c30876dfa	3616
Kojto	107:4f6c30876dfa	3617	/****************** Bit definition for DMA2D_OCOLR register *************/
Kojto	107:4f6c30876dfa	3618
Kojto	107:4f6c30876dfa	3619	/!<Mode_ARGB8888/RGB888 /
Kojto	107:4f6c30876dfa	3620
Kojto	122:f9eeca106725	3621	#define DMA2D_OCOLR_BLUE_1 0x000000FFU /!< BLUE Value /
Kojto	122:f9eeca106725	3622	#define DMA2D_OCOLR_GREEN_1 0x0000FF00U /!< GREEN Value /
Kojto	122:f9eeca106725	3623	#define DMA2D_OCOLR_RED_1 0x00FF0000U /!< Red Value /
Kojto	122:f9eeca106725	3624	#define DMA2D_OCOLR_ALPHA_1 0xFF000000U /!< Alpha Channel Value /
Kojto	107:4f6c30876dfa	3625
Kojto	107:4f6c30876dfa	3626	/!<Mode_RGB565 /
Kojto	122:f9eeca106725	3627	#define DMA2D_OCOLR_BLUE_2 0x0000001FU /!< BLUE Value /
Kojto	122:f9eeca106725	3628	#define DMA2D_OCOLR_GREEN_2 0x000007E0U /!< GREEN Value /
Kojto	122:f9eeca106725	3629	#define DMA2D_OCOLR_RED_2 0x0000F800U /!< Red Value /
Kojto	107:4f6c30876dfa	3630
Kojto	107:4f6c30876dfa	3631	/!<Mode_ARGB1555 /
Kojto	122:f9eeca106725	3632	#define DMA2D_OCOLR_BLUE_3 0x0000001FU /!< BLUE Value /
Kojto	122:f9eeca106725	3633	#define DMA2D_OCOLR_GREEN_3 0x000003E0U /!< GREEN Value /
Kojto	122:f9eeca106725	3634	#define DMA2D_OCOLR_RED_3 0x00007C00U /!< Red Value /
Kojto	122:f9eeca106725	3635	#define DMA2D_OCOLR_ALPHA_3 0x00008000U /!< Alpha Channel Value /
Kojto	107:4f6c30876dfa	3636
Kojto	107:4f6c30876dfa	3637	/!<Mode_ARGB4444 /
Kojto	122:f9eeca106725	3638	#define DMA2D_OCOLR_BLUE_4 0x0000000FU /!< BLUE Value /
Kojto	122:f9eeca106725	3639	#define DMA2D_OCOLR_GREEN_4 0x000000F0U /!< GREEN Value /
Kojto	122:f9eeca106725	3640	#define DMA2D_OCOLR_RED_4 0x00000F00U /!< Red Value /
Kojto	122:f9eeca106725	3641	#define DMA2D_OCOLR_ALPHA_4 0x0000F000U /!< Alpha Channel Value /
Kojto	107:4f6c30876dfa	3642
Kojto	107:4f6c30876dfa	3643	/****************** Bit definition for DMA2D_OMAR register **************/
Kojto	107:4f6c30876dfa	3644
Kojto	122:f9eeca106725	3645	#define DMA2D_OMAR_MA 0xFFFFFFFFU /!< Memory Address /
Kojto	107:4f6c30876dfa	3646
Kojto	107:4f6c30876dfa	3647	/****************** Bit definition for DMA2D_OOR register ***************/
Kojto	107:4f6c30876dfa	3648
Kojto	122:f9eeca106725	3649	#define DMA2D_OOR_LO 0x00003FFFU /!< Line Offset /
Kojto	107:4f6c30876dfa	3650
Kojto	107:4f6c30876dfa	3651	/****************** Bit definition for DMA2D_NLR register ***************/
Kojto	107:4f6c30876dfa	3652
Kojto	122:f9eeca106725	3653	#define DMA2D_NLR_NL 0x0000FFFFU /!< Number of Lines /
Kojto	122:f9eeca106725	3654	#define DMA2D_NLR_PL 0x3FFF0000U /!< Pixel per Lines /
Kojto	107:4f6c30876dfa	3655
Kojto	107:4f6c30876dfa	3656	/****************** Bit definition for DMA2D_LWR register ***************/
Kojto	107:4f6c30876dfa	3657
Kojto	122:f9eeca106725	3658	#define DMA2D_LWR_LW 0x0000FFFFU /!< Line Watermark /
Kojto	107:4f6c30876dfa	3659
Kojto	107:4f6c30876dfa	3660	/****************** Bit definition for DMA2D_AMTCR register *************/
Kojto	107:4f6c30876dfa	3661
Kojto	122:f9eeca106725	3662	#define DMA2D_AMTCR_EN 0x00000001U /!< Enable /
Kojto	122:f9eeca106725	3663	#define DMA2D_AMTCR_DT 0x0000FF00U /!< Dead Time /
Kojto	107:4f6c30876dfa	3664
Kojto	107:4f6c30876dfa	3665
Kojto	107:4f6c30876dfa	3666	/****************** Bit definition for DMA2D_FGCLUT register ************/
Kojto	107:4f6c30876dfa	3667
Kojto	107:4f6c30876dfa	3668	/****************** Bit definition for DMA2D_BGCLUT register ************/
Kojto	107:4f6c30876dfa	3669
Kojto	107:4f6c30876dfa	3670
Kojto	107:4f6c30876dfa	3671	/******************************************************************************/
Kojto	107:4f6c30876dfa	3672	/* */
Kojto	107:4f6c30876dfa	3673	/* External Interrupt/Event Controller */
Kojto	107:4f6c30876dfa	3674	/* */
Kojto	107:4f6c30876dfa	3675	/******************************************************************************/
Kojto	107:4f6c30876dfa	3676	/***************** Bit definition for EXTI_IMR register *****************/
Kojto	122:f9eeca106725	3677	#define EXTI_IMR_MR0 0x00000001U /!< Interrupt Mask on line 0 /
Kojto	122:f9eeca106725	3678	#define EXTI_IMR_MR1 0x00000002U /!< Interrupt Mask on line 1 /
Kojto	122:f9eeca106725	3679	#define EXTI_IMR_MR2 0x00000004U /!< Interrupt Mask on line 2 /
Kojto	122:f9eeca106725	3680	#define EXTI_IMR_MR3 0x00000008U /!< Interrupt Mask on line 3 /
Kojto	122:f9eeca106725	3681	#define EXTI_IMR_MR4 0x00000010U /!< Interrupt Mask on line 4 /
Kojto	122:f9eeca106725	3682	#define EXTI_IMR_MR5 0x00000020U /!< Interrupt Mask on line 5 /
Kojto	122:f9eeca106725	3683	#define EXTI_IMR_MR6 0x00000040U /!< Interrupt Mask on line 6 /
Kojto	122:f9eeca106725	3684	#define EXTI_IMR_MR7 0x00000080U /!< Interrupt Mask on line 7 /
Kojto	122:f9eeca106725	3685	#define EXTI_IMR_MR8 0x00000100U /!< Interrupt Mask on line 8 /
Kojto	122:f9eeca106725	3686	#define EXTI_IMR_MR9 0x00000200U /!< Interrupt Mask on line 9 /
Kojto	122:f9eeca106725	3687	#define EXTI_IMR_MR10 0x00000400U /!< Interrupt Mask on line 10 /
Kojto	122:f9eeca106725	3688	#define EXTI_IMR_MR11 0x00000800U /!< Interrupt Mask on line 11 /
Kojto	122:f9eeca106725	3689	#define EXTI_IMR_MR12 0x00001000U /!< Interrupt Mask on line 12 /
Kojto	122:f9eeca106725	3690	#define EXTI_IMR_MR13 0x00002000U /!< Interrupt Mask on line 13 /
Kojto	122:f9eeca106725	3691	#define EXTI_IMR_MR14 0x00004000U /!< Interrupt Mask on line 14 /
Kojto	122:f9eeca106725	3692	#define EXTI_IMR_MR15 0x00008000U /!< Interrupt Mask on line 15 /
Kojto	122:f9eeca106725	3693	#define EXTI_IMR_MR16 0x00010000U /!< Interrupt Mask on line 16 /
Kojto	122:f9eeca106725	3694	#define EXTI_IMR_MR17 0x00020000U /!< Interrupt Mask on line 17 /
Kojto	122:f9eeca106725	3695	#define EXTI_IMR_MR18 0x00040000U /!< Interrupt Mask on line 18 /
Kojto	122:f9eeca106725	3696	#define EXTI_IMR_MR19 0x00080000U /!< Interrupt Mask on line 19 /
Kojto	122:f9eeca106725	3697	#define EXTI_IMR_MR20 0x00100000U /!< Interrupt Mask on line 20 /
Kojto	122:f9eeca106725	3698	#define EXTI_IMR_MR21 0x00200000U /!< Interrupt Mask on line 21 /
Kojto	122:f9eeca106725	3699	#define EXTI_IMR_MR22 0x00400000U /!< Interrupt Mask on line 22 /
Kojto	122:f9eeca106725	3700	#define EXTI_IMR_MR23 0x00800000U /!< Interrupt Mask on line 23 /
Kojto	122:f9eeca106725	3701
Kojto	122:f9eeca106725	3702	/* Reference Defines */
Kojto	122:f9eeca106725	3703	#define EXTI_IMR_IM0 EXTI_IMR_MR0
Kojto	122:f9eeca106725	3704	#define EXTI_IMR_IM1 EXTI_IMR_MR1
Kojto	122:f9eeca106725	3705	#define EXTI_IMR_IM2 EXTI_IMR_MR2
Kojto	122:f9eeca106725	3706	#define EXTI_IMR_IM3 EXTI_IMR_MR3
Kojto	122:f9eeca106725	3707	#define EXTI_IMR_IM4 EXTI_IMR_MR4
Kojto	122:f9eeca106725	3708	#define EXTI_IMR_IM5 EXTI_IMR_MR5
Kojto	122:f9eeca106725	3709	#define EXTI_IMR_IM6 EXTI_IMR_MR6
Kojto	122:f9eeca106725	3710	#define EXTI_IMR_IM7 EXTI_IMR_MR7
Kojto	122:f9eeca106725	3711	#define EXTI_IMR_IM8 EXTI_IMR_MR8
Kojto	122:f9eeca106725	3712	#define EXTI_IMR_IM9 EXTI_IMR_MR9
Kojto	122:f9eeca106725	3713	#define EXTI_IMR_IM10 EXTI_IMR_MR10
Kojto	122:f9eeca106725	3714	#define EXTI_IMR_IM11 EXTI_IMR_MR11
Kojto	122:f9eeca106725	3715	#define EXTI_IMR_IM12 EXTI_IMR_MR12
Kojto	122:f9eeca106725	3716	#define EXTI_IMR_IM13 EXTI_IMR_MR13
Kojto	122:f9eeca106725	3717	#define EXTI_IMR_IM14 EXTI_IMR_MR14
Kojto	122:f9eeca106725	3718	#define EXTI_IMR_IM15 EXTI_IMR_MR15
Kojto	122:f9eeca106725	3719	#define EXTI_IMR_IM16 EXTI_IMR_MR16
Kojto	122:f9eeca106725	3720	#define EXTI_IMR_IM17 EXTI_IMR_MR17
Kojto	122:f9eeca106725	3721	#define EXTI_IMR_IM18 EXTI_IMR_MR18
Kojto	122:f9eeca106725	3722	#define EXTI_IMR_IM19 EXTI_IMR_MR19
Kojto	122:f9eeca106725	3723	#define EXTI_IMR_IM20 EXTI_IMR_MR20
Kojto	122:f9eeca106725	3724	#define EXTI_IMR_IM21 EXTI_IMR_MR21
Kojto	122:f9eeca106725	3725	#define EXTI_IMR_IM22 EXTI_IMR_MR22
Kojto	122:f9eeca106725	3726	#define EXTI_IMR_IM23 EXTI_IMR_MR23
Kojto	122:f9eeca106725	3727
Kojto	122:f9eeca106725	3728	#define EXTI_IMR_IM 0x00FFFFFFU /!< Interrupt Mask All /
Kojto	107:4f6c30876dfa	3729
Kojto	107:4f6c30876dfa	3730	/***************** Bit definition for EXTI_EMR register *****************/
Kojto	122:f9eeca106725	3731	#define EXTI_EMR_MR0 0x00000001U /!< Event Mask on line 0 /
Kojto	122:f9eeca106725	3732	#define EXTI_EMR_MR1 0x00000002U /!< Event Mask on line 1 /
Kojto	122:f9eeca106725	3733	#define EXTI_EMR_MR2 0x00000004U /!< Event Mask on line 2 /
Kojto	122:f9eeca106725	3734	#define EXTI_EMR_MR3 0x00000008U /!< Event Mask on line 3 /
Kojto	122:f9eeca106725	3735	#define EXTI_EMR_MR4 0x00000010U /!< Event Mask on line 4 /
Kojto	122:f9eeca106725	3736	#define EXTI_EMR_MR5 0x00000020U /!< Event Mask on line 5 /
Kojto	122:f9eeca106725	3737	#define EXTI_EMR_MR6 0x00000040U /!< Event Mask on line 6 /
Kojto	122:f9eeca106725	3738	#define EXTI_EMR_MR7 0x00000080U /!< Event Mask on line 7 /
Kojto	122:f9eeca106725	3739	#define EXTI_EMR_MR8 0x00000100U /!< Event Mask on line 8 /
Kojto	122:f9eeca106725	3740	#define EXTI_EMR_MR9 0x00000200U /!< Event Mask on line 9 /
Kojto	122:f9eeca106725	3741	#define EXTI_EMR_MR10 0x00000400U /!< Event Mask on line 10 /
Kojto	122:f9eeca106725	3742	#define EXTI_EMR_MR11 0x00000800U /!< Event Mask on line 11 /
Kojto	122:f9eeca106725	3743	#define EXTI_EMR_MR12 0x00001000U /!< Event Mask on line 12 /
Kojto	122:f9eeca106725	3744	#define EXTI_EMR_MR13 0x00002000U /!< Event Mask on line 13 /
Kojto	122:f9eeca106725	3745	#define EXTI_EMR_MR14 0x00004000U /!< Event Mask on line 14 /
Kojto	122:f9eeca106725	3746	#define EXTI_EMR_MR15 0x00008000U /!< Event Mask on line 15 /
Kojto	122:f9eeca106725	3747	#define EXTI_EMR_MR16 0x00010000U /!< Event Mask on line 16 /
Kojto	122:f9eeca106725	3748	#define EXTI_EMR_MR17 0x00020000U /!< Event Mask on line 17 /
Kojto	122:f9eeca106725	3749	#define EXTI_EMR_MR18 0x00040000U /!< Event Mask on line 18 /
Kojto	122:f9eeca106725	3750	#define EXTI_EMR_MR19 0x00080000U /!< Event Mask on line 19 /
Kojto	122:f9eeca106725	3751	#define EXTI_EMR_MR20 0x00100000U /!< Event Mask on line 20 /
Kojto	122:f9eeca106725	3752	#define EXTI_EMR_MR21 0x00200000U /!< Event Mask on line 21 /
Kojto	122:f9eeca106725	3753	#define EXTI_EMR_MR22 0x00400000U /!< Event Mask on line 22 /
Kojto	122:f9eeca106725	3754	#define EXTI_EMR_MR23 0x00800000U /!< Event Mask on line 23 /
Kojto	122:f9eeca106725	3755
Kojto	122:f9eeca106725	3756	/* Reference Defines */
Kojto	122:f9eeca106725	3757	#define EXTI_EMR_EM0 EXTI_EMR_MR0
Kojto	122:f9eeca106725	3758	#define EXTI_EMR_EM1 EXTI_EMR_MR1
Kojto	122:f9eeca106725	3759	#define EXTI_EMR_EM2 EXTI_EMR_MR2
Kojto	122:f9eeca106725	3760	#define EXTI_EMR_EM3 EXTI_EMR_MR3
Kojto	122:f9eeca106725	3761	#define EXTI_EMR_EM4 EXTI_EMR_MR4
Kojto	122:f9eeca106725	3762	#define EXTI_EMR_EM5 EXTI_EMR_MR5
Kojto	122:f9eeca106725	3763	#define EXTI_EMR_EM6 EXTI_EMR_MR6
Kojto	122:f9eeca106725	3764	#define EXTI_EMR_EM7 EXTI_EMR_MR7
Kojto	122:f9eeca106725	3765	#define EXTI_EMR_EM8 EXTI_EMR_MR8
Kojto	122:f9eeca106725	3766	#define EXTI_EMR_EM9 EXTI_EMR_MR9
Kojto	122:f9eeca106725	3767	#define EXTI_EMR_EM10 EXTI_EMR_MR10
Kojto	122:f9eeca106725	3768	#define EXTI_EMR_EM11 EXTI_EMR_MR11
Kojto	122:f9eeca106725	3769	#define EXTI_EMR_EM12 EXTI_EMR_MR12
Kojto	122:f9eeca106725	3770	#define EXTI_EMR_EM13 EXTI_EMR_MR13
Kojto	122:f9eeca106725	3771	#define EXTI_EMR_EM14 EXTI_EMR_MR14
Kojto	122:f9eeca106725	3772	#define EXTI_EMR_EM15 EXTI_EMR_MR15
Kojto	122:f9eeca106725	3773	#define EXTI_EMR_EM16 EXTI_EMR_MR16
Kojto	122:f9eeca106725	3774	#define EXTI_EMR_EM17 EXTI_EMR_MR17
Kojto	122:f9eeca106725	3775	#define EXTI_EMR_EM18 EXTI_EMR_MR18
Kojto	122:f9eeca106725	3776	#define EXTI_EMR_EM19 EXTI_EMR_MR19
Kojto	122:f9eeca106725	3777	#define EXTI_EMR_EM20 EXTI_EMR_MR20
Kojto	122:f9eeca106725	3778	#define EXTI_EMR_EM21 EXTI_EMR_MR21
Kojto	122:f9eeca106725	3779	#define EXTI_EMR_EM22 EXTI_EMR_MR22
Kojto	122:f9eeca106725	3780	#define EXTI_EMR_EM23 EXTI_EMR_MR23
Kojto	122:f9eeca106725	3781
Kojto	107:4f6c30876dfa	3782
Kojto	107:4f6c30876dfa	3783	/**************** Bit definition for EXTI_RTSR register *****************/
Kojto	122:f9eeca106725	3784	#define EXTI_RTSR_TR0 0x00000001U /!< Rising trigger event configuration bit of line 0 /
Kojto	122:f9eeca106725	3785	#define EXTI_RTSR_TR1 0x00000002U /!< Rising trigger event configuration bit of line 1 /
Kojto	122:f9eeca106725	3786	#define EXTI_RTSR_TR2 0x00000004U /!< Rising trigger event configuration bit of line 2 /
Kojto	122:f9eeca106725	3787	#define EXTI_RTSR_TR3 0x00000008U /!< Rising trigger event configuration bit of line 3 /
Kojto	122:f9eeca106725	3788	#define EXTI_RTSR_TR4 0x00000010U /!< Rising trigger event configuration bit of line 4 /
Kojto	122:f9eeca106725	3789	#define EXTI_RTSR_TR5 0x00000020U /!< Rising trigger event configuration bit of line 5 /
Kojto	122:f9eeca106725	3790	#define EXTI_RTSR_TR6 0x00000040U /!< Rising trigger event configuration bit of line 6 /
Kojto	122:f9eeca106725	3791	#define EXTI_RTSR_TR7 0x00000080U /!< Rising trigger event configuration bit of line 7 /
Kojto	122:f9eeca106725	3792	#define EXTI_RTSR_TR8 0x00000100U /!< Rising trigger event configuration bit of line 8 /
Kojto	122:f9eeca106725	3793	#define EXTI_RTSR_TR9 0x00000200U /!< Rising trigger event configuration bit of line 9 /
Kojto	122:f9eeca106725	3794	#define EXTI_RTSR_TR10 0x00000400U /!< Rising trigger event configuration bit of line 10 /
Kojto	122:f9eeca106725	3795	#define EXTI_RTSR_TR11 0x00000800U /!< Rising trigger event configuration bit of line 11 /
Kojto	122:f9eeca106725	3796	#define EXTI_RTSR_TR12 0x00001000U /!< Rising trigger event configuration bit of line 12 /
Kojto	122:f9eeca106725	3797	#define EXTI_RTSR_TR13 0x00002000U /!< Rising trigger event configuration bit of line 13 /
Kojto	122:f9eeca106725	3798	#define EXTI_RTSR_TR14 0x00004000U /!< Rising trigger event configuration bit of line 14 /
Kojto	122:f9eeca106725	3799	#define EXTI_RTSR_TR15 0x00008000U /!< Rising trigger event configuration bit of line 15 /
Kojto	122:f9eeca106725	3800	#define EXTI_RTSR_TR16 0x00010000U /!< Rising trigger event configuration bit of line 16 /
Kojto	122:f9eeca106725	3801	#define EXTI_RTSR_TR17 0x00020000U /!< Rising trigger event configuration bit of line 17 /
Kojto	122:f9eeca106725	3802	#define EXTI_RTSR_TR18 0x00040000U /!< Rising trigger event configuration bit of line 18 /
Kojto	122:f9eeca106725	3803	#define EXTI_RTSR_TR19 0x00080000U /!< Rising trigger event configuration bit of line 19 /
Kojto	122:f9eeca106725	3804	#define EXTI_RTSR_TR20 0x00100000U /!< Rising trigger event configuration bit of line 20 /
Kojto	122:f9eeca106725	3805	#define EXTI_RTSR_TR21 0x00200000U /!< Rising trigger event configuration bit of line 21 /
Kojto	122:f9eeca106725	3806	#define EXTI_RTSR_TR22 0x00400000U /!< Rising trigger event configuration bit of line 22 /
Kojto	122:f9eeca106725	3807	#define EXTI_RTSR_TR23 0x00800000U /!< Rising trigger event configuration bit of line 23 /
Kojto	107:4f6c30876dfa	3808
Kojto	107:4f6c30876dfa	3809	/**************** Bit definition for EXTI_FTSR register *****************/
Kojto	122:f9eeca106725	3810	#define EXTI_FTSR_TR0 0x00000001U /!< Falling trigger event configuration bit of line 0 /
Kojto	122:f9eeca106725	3811	#define EXTI_FTSR_TR1 0x00000002U /!< Falling trigger event configuration bit of line 1 /
Kojto	122:f9eeca106725	3812	#define EXTI_FTSR_TR2 0x00000004U /!< Falling trigger event configuration bit of line 2 /
Kojto	122:f9eeca106725	3813	#define EXTI_FTSR_TR3 0x00000008U /!< Falling trigger event configuration bit of line 3 /
Kojto	122:f9eeca106725	3814	#define EXTI_FTSR_TR4 0x00000010U /!< Falling trigger event configuration bit of line 4 /
Kojto	122:f9eeca106725	3815	#define EXTI_FTSR_TR5 0x00000020U /!< Falling trigger event configuration bit of line 5 /
Kojto	122:f9eeca106725	3816	#define EXTI_FTSR_TR6 0x00000040U /!< Falling trigger event configuration bit of line 6 /
Kojto	122:f9eeca106725	3817	#define EXTI_FTSR_TR7 0x00000080U /!< Falling trigger event configuration bit of line 7 /
Kojto	122:f9eeca106725	3818	#define EXTI_FTSR_TR8 0x00000100U /!< Falling trigger event configuration bit of line 8 /
Kojto	122:f9eeca106725	3819	#define EXTI_FTSR_TR9 0x00000200U /!< Falling trigger event configuration bit of line 9 /
Kojto	122:f9eeca106725	3820	#define EXTI_FTSR_TR10 0x00000400U /!< Falling trigger event configuration bit of line 10 /
Kojto	122:f9eeca106725	3821	#define EXTI_FTSR_TR11 0x00000800U /!< Falling trigger event configuration bit of line 11 /
Kojto	122:f9eeca106725	3822	#define EXTI_FTSR_TR12 0x00001000U /!< Falling trigger event configuration bit of line 12 /
Kojto	122:f9eeca106725	3823	#define EXTI_FTSR_TR13 0x00002000U /!< Falling trigger event configuration bit of line 13 /
Kojto	122:f9eeca106725	3824	#define EXTI_FTSR_TR14 0x00004000U /!< Falling trigger event configuration bit of line 14 /
Kojto	122:f9eeca106725	3825	#define EXTI_FTSR_TR15 0x00008000U /!< Falling trigger event configuration bit of line 15 /
Kojto	122:f9eeca106725	3826	#define EXTI_FTSR_TR16 0x00010000U /!< Falling trigger event configuration bit of line 16 /
Kojto	122:f9eeca106725	3827	#define EXTI_FTSR_TR17 0x00020000U /!< Falling trigger event configuration bit of line 17 /
Kojto	122:f9eeca106725	3828	#define EXTI_FTSR_TR18 0x00040000U /!< Falling trigger event configuration bit of line 18 /
Kojto	122:f9eeca106725	3829	#define EXTI_FTSR_TR19 0x00080000U /!< Falling trigger event configuration bit of line 19 /
Kojto	122:f9eeca106725	3830	#define EXTI_FTSR_TR20 0x00100000U /!< Falling trigger event configuration bit of line 20 /
Kojto	122:f9eeca106725	3831	#define EXTI_FTSR_TR21 0x00200000U /!< Falling trigger event configuration bit of line 21 /
Kojto	122:f9eeca106725	3832	#define EXTI_FTSR_TR22 0x00400000U /!< Falling trigger event configuration bit of line 22 /
Kojto	122:f9eeca106725	3833	#define EXTI_FTSR_TR23 0x00800000U /!< Falling trigger event configuration bit of line 23 /
Kojto	107:4f6c30876dfa	3834
Kojto	107:4f6c30876dfa	3835	/**************** Bit definition for EXTI_SWIER register ****************/
Kojto	122:f9eeca106725	3836	#define EXTI_SWIER_SWIER0 0x00000001U /!< Software Interrupt on line 0 /
Kojto	122:f9eeca106725	3837	#define EXTI_SWIER_SWIER1 0x00000002U /!< Software Interrupt on line 1 /
Kojto	122:f9eeca106725	3838	#define EXTI_SWIER_SWIER2 0x00000004U /!< Software Interrupt on line 2 /
Kojto	122:f9eeca106725	3839	#define EXTI_SWIER_SWIER3 0x00000008U /!< Software Interrupt on line 3 /
Kojto	122:f9eeca106725	3840	#define EXTI_SWIER_SWIER4 0x00000010U /!< Software Interrupt on line 4 /
Kojto	122:f9eeca106725	3841	#define EXTI_SWIER_SWIER5 0x00000020U /!< Software Interrupt on line 5 /
Kojto	122:f9eeca106725	3842	#define EXTI_SWIER_SWIER6 0x00000040U /!< Software Interrupt on line 6 /
Kojto	122:f9eeca106725	3843	#define EXTI_SWIER_SWIER7 0x00000080U /!< Software Interrupt on line 7 /
Kojto	122:f9eeca106725	3844	#define EXTI_SWIER_SWIER8 0x00000100U /!< Software Interrupt on line 8 /
Kojto	122:f9eeca106725	3845	#define EXTI_SWIER_SWIER9 0x00000200U /!< Software Interrupt on line 9 /
Kojto	122:f9eeca106725	3846	#define EXTI_SWIER_SWIER10 0x00000400U /!< Software Interrupt on line 10 /
Kojto	122:f9eeca106725	3847	#define EXTI_SWIER_SWIER11 0x00000800U /!< Software Interrupt on line 11 /
Kojto	122:f9eeca106725	3848	#define EXTI_SWIER_SWIER12 0x00001000U /!< Software Interrupt on line 12 /
Kojto	122:f9eeca106725	3849	#define EXTI_SWIER_SWIER13 0x00002000U /!< Software Interrupt on line 13 /
Kojto	122:f9eeca106725	3850	#define EXTI_SWIER_SWIER14 0x00004000U /!< Software Interrupt on line 14 /
Kojto	122:f9eeca106725	3851	#define EXTI_SWIER_SWIER15 0x00008000U /!< Software Interrupt on line 15 /
Kojto	122:f9eeca106725	3852	#define EXTI_SWIER_SWIER16 0x00010000U /!< Software Interrupt on line 16 /
Kojto	122:f9eeca106725	3853	#define EXTI_SWIER_SWIER17 0x00020000U /!< Software Interrupt on line 17 /
Kojto	122:f9eeca106725	3854	#define EXTI_SWIER_SWIER18 0x00040000U /!< Software Interrupt on line 18 /
Kojto	122:f9eeca106725	3855	#define EXTI_SWIER_SWIER19 0x00080000U /!< Software Interrupt on line 19 /
Kojto	122:f9eeca106725	3856	#define EXTI_SWIER_SWIER20 0x00100000U /!< Software Interrupt on line 20 /
Kojto	122:f9eeca106725	3857	#define EXTI_SWIER_SWIER21 0x00200000U /!< Software Interrupt on line 21 /
Kojto	122:f9eeca106725	3858	#define EXTI_SWIER_SWIER22 0x00400000U /!< Software Interrupt on line 22 /
Kojto	122:f9eeca106725	3859	#define EXTI_SWIER_SWIER23 0x00800000U /!< Software Interrupt on line 23 /
Kojto	107:4f6c30876dfa	3860
Kojto	107:4f6c30876dfa	3861	/***************** Bit definition for EXTI_PR register ******************/
Kojto	122:f9eeca106725	3862	#define EXTI_PR_PR0 0x00000001U /!< Pending bit for line 0 /
Kojto	122:f9eeca106725	3863	#define EXTI_PR_PR1 0x00000002U /!< Pending bit for line 1 /
Kojto	122:f9eeca106725	3864	#define EXTI_PR_PR2 0x00000004U /!< Pending bit for line 2 /
Kojto	122:f9eeca106725	3865	#define EXTI_PR_PR3 0x00000008U /!< Pending bit for line 3 /
Kojto	122:f9eeca106725	3866	#define EXTI_PR_PR4 0x00000010U /!< Pending bit for line 4 /
Kojto	122:f9eeca106725	3867	#define EXTI_PR_PR5 0x00000020U /!< Pending bit for line 5 /
Kojto	122:f9eeca106725	3868	#define EXTI_PR_PR6 0x00000040U /!< Pending bit for line 6 /
Kojto	122:f9eeca106725	3869	#define EXTI_PR_PR7 0x00000080U /!< Pending bit for line 7 /
Kojto	122:f9eeca106725	3870	#define EXTI_PR_PR8 0x00000100U /!< Pending bit for line 8 /
Kojto	122:f9eeca106725	3871	#define EXTI_PR_PR9 0x00000200U /!< Pending bit for line 9 /
Kojto	122:f9eeca106725	3872	#define EXTI_PR_PR10 0x00000400U /!< Pending bit for line 10 /
Kojto	122:f9eeca106725	3873	#define EXTI_PR_PR11 0x00000800U /!< Pending bit for line 11 /
Kojto	122:f9eeca106725	3874	#define EXTI_PR_PR12 0x00001000U /!< Pending bit for line 12 /
Kojto	122:f9eeca106725	3875	#define EXTI_PR_PR13 0x00002000U /!< Pending bit for line 13 /
Kojto	122:f9eeca106725	3876	#define EXTI_PR_PR14 0x00004000U /!< Pending bit for line 14 /
Kojto	122:f9eeca106725	3877	#define EXTI_PR_PR15 0x00008000U /!< Pending bit for line 15 /
Kojto	122:f9eeca106725	3878	#define EXTI_PR_PR16 0x00010000U /!< Pending bit for line 16 /
Kojto	122:f9eeca106725	3879	#define EXTI_PR_PR17 0x00020000U /!< Pending bit for line 17 /
Kojto	122:f9eeca106725	3880	#define EXTI_PR_PR18 0x00040000U /!< Pending bit for line 18 /
Kojto	122:f9eeca106725	3881	#define EXTI_PR_PR19 0x00080000U /!< Pending bit for line 19 /
Kojto	122:f9eeca106725	3882	#define EXTI_PR_PR20 0x00100000U /!< Pending bit for line 20 /
Kojto	122:f9eeca106725	3883	#define EXTI_PR_PR21 0x00200000U /!< Pending bit for line 21 /
Kojto	122:f9eeca106725	3884	#define EXTI_PR_PR22 0x00400000U /!< Pending bit for line 22 /
Kojto	122:f9eeca106725	3885	#define EXTI_PR_PR23 0x00800000U /!< Pending bit for line 23 /
Kojto	107:4f6c30876dfa	3886
Kojto	107:4f6c30876dfa	3887	/******************************************************************************/
Kojto	107:4f6c30876dfa	3888	/* */
Kojto	107:4f6c30876dfa	3889	/* FLASH */
Kojto	107:4f6c30876dfa	3890	/* */
Kojto	107:4f6c30876dfa	3891	/******************************************************************************/
Kojto	122:f9eeca106725	3892	/*
Kojto	122:f9eeca106725	3893	* @brief FLASH Total Sectors Number
Kojto	122:f9eeca106725	3894	*/
Kojto	122:f9eeca106725	3895	#define FLASH_SECTOR_TOTAL 8
Kojto	122:f9eeca106725	3896
Kojto	107:4f6c30876dfa	3897	/***************** Bits definition for FLASH_ACR register ***************/
Kojto	122:f9eeca106725	3898	#define FLASH_ACR_LATENCY 0x0000000FU
Kojto	122:f9eeca106725	3899	#define FLASH_ACR_LATENCY_0WS 0x00000000U
Kojto	122:f9eeca106725	3900	#define FLASH_ACR_LATENCY_1WS 0x00000001U
Kojto	122:f9eeca106725	3901	#define FLASH_ACR_LATENCY_2WS 0x00000002U
Kojto	122:f9eeca106725	3902	#define FLASH_ACR_LATENCY_3WS 0x00000003U
Kojto	122:f9eeca106725	3903	#define FLASH_ACR_LATENCY_4WS 0x00000004U
Kojto	122:f9eeca106725	3904	#define FLASH_ACR_LATENCY_5WS 0x00000005U
Kojto	122:f9eeca106725	3905	#define FLASH_ACR_LATENCY_6WS 0x00000006U
Kojto	122:f9eeca106725	3906	#define FLASH_ACR_LATENCY_7WS 0x00000007U
Kojto	122:f9eeca106725	3907	#define FLASH_ACR_LATENCY_8WS 0x00000008U
Kojto	122:f9eeca106725	3908	#define FLASH_ACR_LATENCY_9WS 0x00000009U
Kojto	122:f9eeca106725	3909	#define FLASH_ACR_LATENCY_10WS 0x0000000AU
Kojto	122:f9eeca106725	3910	#define FLASH_ACR_LATENCY_11WS 0x0000000BU
Kojto	122:f9eeca106725	3911	#define FLASH_ACR_LATENCY_12WS 0x0000000CU
Kojto	122:f9eeca106725	3912	#define FLASH_ACR_LATENCY_13WS 0x0000000DU
Kojto	122:f9eeca106725	3913	#define FLASH_ACR_LATENCY_14WS 0x0000000EU
Kojto	122:f9eeca106725	3914	#define FLASH_ACR_LATENCY_15WS 0x0000000FU
Kojto	122:f9eeca106725	3915	#define FLASH_ACR_PRFTEN 0x00000100U
Kojto	122:f9eeca106725	3916	#define FLASH_ACR_ARTEN 0x00000200U
Kojto	122:f9eeca106725	3917	#define FLASH_ACR_ARTRST 0x00000800U
Kojto	107:4f6c30876dfa	3918
Kojto	107:4f6c30876dfa	3919	/***************** Bits definition for FLASH_SR register ****************/
Kojto	122:f9eeca106725	3920	#define FLASH_SR_EOP 0x00000001U
Kojto	122:f9eeca106725	3921	#define FLASH_SR_OPERR 0x00000002U
Kojto	122:f9eeca106725	3922	#define FLASH_SR_WRPERR 0x00000010U
Kojto	122:f9eeca106725	3923	#define FLASH_SR_PGAERR 0x00000020U
Kojto	122:f9eeca106725	3924	#define FLASH_SR_PGPERR 0x00000040U
Kojto	122:f9eeca106725	3925	#define FLASH_SR_ERSERR 0x00000080U
Kojto	122:f9eeca106725	3926	#define FLASH_SR_BSY 0x00010000U
Kojto	107:4f6c30876dfa	3927
Kojto	107:4f6c30876dfa	3928	/***************** Bits definition for FLASH_CR register ****************/
Kojto	122:f9eeca106725	3929	#define FLASH_CR_PG 0x00000001U
Kojto	122:f9eeca106725	3930	#define FLASH_CR_SER 0x00000002U
Kojto	122:f9eeca106725	3931	#define FLASH_CR_MER 0x00000004U
Kojto	122:f9eeca106725	3932	#define FLASH_CR_SNB 0x00000078U
Kojto	122:f9eeca106725	3933	#define FLASH_CR_SNB_0 0x00000008U
Kojto	122:f9eeca106725	3934	#define FLASH_CR_SNB_1 0x00000010U
Kojto	122:f9eeca106725	3935	#define FLASH_CR_SNB_2 0x00000020U
Kojto	122:f9eeca106725	3936	#define FLASH_CR_SNB_3 0x00000040U
Kojto	122:f9eeca106725	3937	#define FLASH_CR_PSIZE 0x00000300U
Kojto	122:f9eeca106725	3938	#define FLASH_CR_PSIZE_0 0x00000100U
Kojto	122:f9eeca106725	3939	#define FLASH_CR_PSIZE_1 0x00000200U
Kojto	122:f9eeca106725	3940	#define FLASH_CR_STRT 0x00010000U
Kojto	122:f9eeca106725	3941	#define FLASH_CR_EOPIE 0x01000000U
Kojto	122:f9eeca106725	3942	#define FLASH_CR_ERRIE 0x02000000U
Kojto	122:f9eeca106725	3943	#define FLASH_CR_LOCK 0x80000000U
Kojto	107:4f6c30876dfa	3944
Kojto	107:4f6c30876dfa	3945	/***************** Bits definition for FLASH_OPTCR register *************/
Kojto	122:f9eeca106725	3946	#define FLASH_OPTCR_OPTLOCK 0x00000001U
Kojto	122:f9eeca106725	3947	#define FLASH_OPTCR_OPTSTRT 0x00000002U
Kojto	122:f9eeca106725	3948	#define FLASH_OPTCR_BOR_LEV 0x0000000CU
Kojto	122:f9eeca106725	3949	#define FLASH_OPTCR_BOR_LEV_0 0x00000004U
Kojto	122:f9eeca106725	3950	#define FLASH_OPTCR_BOR_LEV_1 0x00000008U
Kojto	122:f9eeca106725	3951	#define FLASH_OPTCR_WWDG_SW 0x00000010U
Kojto	122:f9eeca106725	3952	#define FLASH_OPTCR_IWDG_SW 0x00000020U
Kojto	122:f9eeca106725	3953	#define FLASH_OPTCR_nRST_STOP 0x00000040U
Kojto	122:f9eeca106725	3954	#define FLASH_OPTCR_nRST_STDBY 0x00000080U
Kojto	122:f9eeca106725	3955	#define FLASH_OPTCR_RDP 0x0000FF00U
Kojto	122:f9eeca106725	3956	#define FLASH_OPTCR_RDP_0 0x00000100U
Kojto	122:f9eeca106725	3957	#define FLASH_OPTCR_RDP_1 0x00000200U
Kojto	122:f9eeca106725	3958	#define FLASH_OPTCR_RDP_2 0x00000400U
Kojto	122:f9eeca106725	3959	#define FLASH_OPTCR_RDP_3 0x00000800U
Kojto	122:f9eeca106725	3960	#define FLASH_OPTCR_RDP_4 0x00001000U
Kojto	122:f9eeca106725	3961	#define FLASH_OPTCR_RDP_5 0x00002000U
Kojto	122:f9eeca106725	3962	#define FLASH_OPTCR_RDP_6 0x00004000U
Kojto	122:f9eeca106725	3963	#define FLASH_OPTCR_RDP_7 0x00008000U
Kojto	122:f9eeca106725	3964	#define FLASH_OPTCR_nWRP 0x00FF0000U
Kojto	122:f9eeca106725	3965	#define FLASH_OPTCR_nWRP_0 0x00010000U
Kojto	122:f9eeca106725	3966	#define FLASH_OPTCR_nWRP_1 0x00020000U
Kojto	122:f9eeca106725	3967	#define FLASH_OPTCR_nWRP_2 0x00040000U
Kojto	122:f9eeca106725	3968	#define FLASH_OPTCR_nWRP_3 0x00080000U
Kojto	122:f9eeca106725	3969	#define FLASH_OPTCR_nWRP_4 0x00100000U
Kojto	122:f9eeca106725	3970	#define FLASH_OPTCR_nWRP_5 0x00200000U
Kojto	122:f9eeca106725	3971	#define FLASH_OPTCR_nWRP_6 0x00400000U
Kojto	122:f9eeca106725	3972	#define FLASH_OPTCR_nWRP_7 0x00800000U
Kojto	122:f9eeca106725	3973	#define FLASH_OPTCR_IWDG_STDBY 0x40000000U
Kojto	122:f9eeca106725	3974	#define FLASH_OPTCR_IWDG_STOP 0x80000000U
Kojto	107:4f6c30876dfa	3975
Kojto	107:4f6c30876dfa	3976	/***************** Bits definition for FLASH_OPTCR1 register *************/
Kojto	122:f9eeca106725	3977	#define FLASH_OPTCR1_BOOT_ADD0 0x0000FFFFU
Kojto	122:f9eeca106725	3978	#define FLASH_OPTCR1_BOOT_ADD1 0xFFFF0000U
Kojto	107:4f6c30876dfa	3979
Kojto	107:4f6c30876dfa	3980	/******************************************************************************/
Kojto	107:4f6c30876dfa	3981	/* */
Kojto	107:4f6c30876dfa	3982	/* Flexible Memory Controller */
Kojto	107:4f6c30876dfa	3983	/* */
Kojto	107:4f6c30876dfa	3984	/******************************************************************************/
Kojto	107:4f6c30876dfa	3985	/**************** Bit definition for FMC_BCR1 register *****************/
Kojto	122:f9eeca106725	3986	#define FMC_BCR1_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	3987	#define FMC_BCR1_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	3988	#define FMC_BCR1_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	3989	#define FMC_BCR1_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	3990	#define FMC_BCR1_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	3991	#define FMC_BCR1_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	3992	#define FMC_BCR1_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	3993	#define FMC_BCR1_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	3994	#define FMC_BCR1_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	3995	#define FMC_BCR1_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	3996	#define FMC_BCR1_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	3997	#define FMC_BCR1_WRAPMOD 0x00000400U /!<Wrapped burst mode support /
Kojto	122:f9eeca106725	3998	#define FMC_BCR1_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	3999	#define FMC_BCR1_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	4000	#define FMC_BCR1_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	4001	#define FMC_BCR1_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	4002	#define FMC_BCR1_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	4003	#define FMC_BCR1_CPSIZE 0x00070000U /!<CRAM page size /
Kojto	122:f9eeca106725	4004	#define FMC_BCR1_CPSIZE_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4005	#define FMC_BCR1_CPSIZE_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4006	#define FMC_BCR1_CPSIZE_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4007	#define FMC_BCR1_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	122:f9eeca106725	4008	#define FMC_BCR1_CCLKEN 0x00100000U /!<Continous clock enable /
Kojto	122:f9eeca106725	4009	#define FMC_BCR1_WFDIS 0x00200000U /!<Write FIFO Disable /
Kojto	107:4f6c30876dfa	4010
Kojto	107:4f6c30876dfa	4011	/**************** Bit definition for FMC_BCR2 register *****************/
Kojto	122:f9eeca106725	4012	#define FMC_BCR2_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	4013	#define FMC_BCR2_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	4014	#define FMC_BCR2_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	4015	#define FMC_BCR2_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	4016	#define FMC_BCR2_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	4017	#define FMC_BCR2_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	4018	#define FMC_BCR2_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4019	#define FMC_BCR2_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4020	#define FMC_BCR2_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	4021	#define FMC_BCR2_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	4022	#define FMC_BCR2_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	4023	#define FMC_BCR2_WRAPMOD 0x00000400U /!<Wrapped burst mode support /
Kojto	122:f9eeca106725	4024	#define FMC_BCR2_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	4025	#define FMC_BCR2_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	4026	#define FMC_BCR2_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	4027	#define FMC_BCR2_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	4028	#define FMC_BCR2_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	4029	#define FMC_BCR2_CPSIZE 0x00070000U /!<CRAM page size /
Kojto	122:f9eeca106725	4030	#define FMC_BCR2_CPSIZE_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4031	#define FMC_BCR2_CPSIZE_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4032	#define FMC_BCR2_CPSIZE_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4033	#define FMC_BCR2_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	107:4f6c30876dfa	4034
Kojto	107:4f6c30876dfa	4035	/**************** Bit definition for FMC_BCR3 register *****************/
Kojto	122:f9eeca106725	4036	#define FMC_BCR3_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	4037	#define FMC_BCR3_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	4038	#define FMC_BCR3_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	4039	#define FMC_BCR3_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	4040	#define FMC_BCR3_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	4041	#define FMC_BCR3_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	4042	#define FMC_BCR3_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4043	#define FMC_BCR3_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4044	#define FMC_BCR3_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	4045	#define FMC_BCR3_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	4046	#define FMC_BCR3_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	4047	#define FMC_BCR3_WRAPMOD 0x00000400U /!<Wrapped burst mode support /
Kojto	122:f9eeca106725	4048	#define FMC_BCR3_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	4049	#define FMC_BCR3_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	4050	#define FMC_BCR3_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	4051	#define FMC_BCR3_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	4052	#define FMC_BCR3_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	4053	#define FMC_BCR3_CPSIZE 0x00070000U /!<CRAM page size /
Kojto	122:f9eeca106725	4054	#define FMC_BCR3_CPSIZE_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4055	#define FMC_BCR3_CPSIZE_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4056	#define FMC_BCR3_CPSIZE_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4057	#define FMC_BCR3_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	107:4f6c30876dfa	4058
Kojto	107:4f6c30876dfa	4059	/**************** Bit definition for FMC_BCR4 register *****************/
Kojto	122:f9eeca106725	4060	#define FMC_BCR4_MBKEN 0x00000001U /!<Memory bank enable bit /
Kojto	122:f9eeca106725	4061	#define FMC_BCR4_MUXEN 0x00000002U /!<Address/data multiplexing enable bit /
Kojto	122:f9eeca106725	4062	#define FMC_BCR4_MTYP 0x0000000CU /!<MTYP[1:0] bits (Memory type) /
Kojto	122:f9eeca106725	4063	#define FMC_BCR4_MTYP_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	4064	#define FMC_BCR4_MTYP_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	4065	#define FMC_BCR4_MWID 0x00000030U /!<MWID[1:0] bits (Memory data bus width) /
Kojto	122:f9eeca106725	4066	#define FMC_BCR4_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4067	#define FMC_BCR4_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4068	#define FMC_BCR4_FACCEN 0x00000040U /!<Flash access enable /
Kojto	122:f9eeca106725	4069	#define FMC_BCR4_BURSTEN 0x00000100U /!<Burst enable bit /
Kojto	122:f9eeca106725	4070	#define FMC_BCR4_WAITPOL 0x00000200U /!<Wait signal polarity bit /
Kojto	122:f9eeca106725	4071	#define FMC_BCR4_WRAPMOD 0x00000400U /!<Wrapped burst mode support /
Kojto	122:f9eeca106725	4072	#define FMC_BCR4_WAITCFG 0x00000800U /!<Wait timing configuration /
Kojto	122:f9eeca106725	4073	#define FMC_BCR4_WREN 0x00001000U /!<Write enable bit /
Kojto	122:f9eeca106725	4074	#define FMC_BCR4_WAITEN 0x00002000U /!<Wait enable bit /
Kojto	122:f9eeca106725	4075	#define FMC_BCR4_EXTMOD 0x00004000U /!<Extended mode enable /
Kojto	122:f9eeca106725	4076	#define FMC_BCR4_ASYNCWAIT 0x00008000U /!<Asynchronous wait /
Kojto	122:f9eeca106725	4077	#define FMC_BCR4_CPSIZE 0x00070000U /!<CRAM page size /
Kojto	122:f9eeca106725	4078	#define FMC_BCR4_CPSIZE_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4079	#define FMC_BCR4_CPSIZE_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4080	#define FMC_BCR4_CPSIZE_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4081	#define FMC_BCR4_CBURSTRW 0x00080000U /!<Write burst enable /
Kojto	107:4f6c30876dfa	4082
Kojto	107:4f6c30876dfa	4083	/**************** Bit definition for FMC_BTR1 register ****************/
Kojto	122:f9eeca106725	4084	#define FMC_BTR1_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4085	#define FMC_BTR1_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4086	#define FMC_BTR1_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4087	#define FMC_BTR1_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4088	#define FMC_BTR1_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4089	#define FMC_BTR1_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4090	#define FMC_BTR1_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4091	#define FMC_BTR1_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4092	#define FMC_BTR1_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4093	#define FMC_BTR1_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4094	#define FMC_BTR1_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4095	#define FMC_BTR1_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4096	#define FMC_BTR1_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4097	#define FMC_BTR1_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4098	#define FMC_BTR1_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4099	#define FMC_BTR1_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4100	#define FMC_BTR1_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4101	#define FMC_BTR1_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4102	#define FMC_BTR1_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4103	#define FMC_BTR1_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4104	#define FMC_BTR1_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4105	#define FMC_BTR1_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4106	#define FMC_BTR1_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4107	#define FMC_BTR1_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4108	#define FMC_BTR1_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	4109	#define FMC_BTR1_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	4110	#define FMC_BTR1_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	4111	#define FMC_BTR1_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	4112	#define FMC_BTR1_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	4113	#define FMC_BTR1_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	4114	#define FMC_BTR1_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4115	#define FMC_BTR1_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4116	#define FMC_BTR1_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	4117	#define FMC_BTR1_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	4118	#define FMC_BTR1_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4119	#define FMC_BTR1_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4120	#define FMC_BTR1_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4121
Kojto	107:4f6c30876dfa	4122	/**************** Bit definition for FMC_BTR2 register *****************/
Kojto	122:f9eeca106725	4123	#define FMC_BTR2_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4124	#define FMC_BTR2_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4125	#define FMC_BTR2_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4126	#define FMC_BTR2_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4127	#define FMC_BTR2_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4128	#define FMC_BTR2_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4129	#define FMC_BTR2_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4130	#define FMC_BTR2_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4131	#define FMC_BTR2_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4132	#define FMC_BTR2_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4133	#define FMC_BTR2_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4134	#define FMC_BTR2_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4135	#define FMC_BTR2_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4136	#define FMC_BTR2_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4137	#define FMC_BTR2_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4138	#define FMC_BTR2_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4139	#define FMC_BTR2_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4140	#define FMC_BTR2_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4141	#define FMC_BTR2_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4142	#define FMC_BTR2_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4143	#define FMC_BTR2_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4144	#define FMC_BTR2_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4145	#define FMC_BTR2_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4146	#define FMC_BTR2_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4147	#define FMC_BTR2_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	4148	#define FMC_BTR2_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	4149	#define FMC_BTR2_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	4150	#define FMC_BTR2_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	4151	#define FMC_BTR2_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	4152	#define FMC_BTR2_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	4153	#define FMC_BTR2_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4154	#define FMC_BTR2_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4155	#define FMC_BTR2_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	4156	#define FMC_BTR2_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	4157	#define FMC_BTR2_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4158	#define FMC_BTR2_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4159	#define FMC_BTR2_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4160
Kojto	107:4f6c30876dfa	4161	/***************** Bit definition for FMC_BTR3 register *****************/
Kojto	122:f9eeca106725	4162	#define FMC_BTR3_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4163	#define FMC_BTR3_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4164	#define FMC_BTR3_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4165	#define FMC_BTR3_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4166	#define FMC_BTR3_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4167	#define FMC_BTR3_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4168	#define FMC_BTR3_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4169	#define FMC_BTR3_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4170	#define FMC_BTR3_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4171	#define FMC_BTR3_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4172	#define FMC_BTR3_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4173	#define FMC_BTR3_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4174	#define FMC_BTR3_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4175	#define FMC_BTR3_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4176	#define FMC_BTR3_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4177	#define FMC_BTR3_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4178	#define FMC_BTR3_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4179	#define FMC_BTR3_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4180	#define FMC_BTR3_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4181	#define FMC_BTR3_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4182	#define FMC_BTR3_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4183	#define FMC_BTR3_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4184	#define FMC_BTR3_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4185	#define FMC_BTR3_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4186	#define FMC_BTR3_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	4187	#define FMC_BTR3_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	4188	#define FMC_BTR3_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	4189	#define FMC_BTR3_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	4190	#define FMC_BTR3_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	4191	#define FMC_BTR3_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	4192	#define FMC_BTR3_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4193	#define FMC_BTR3_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4194	#define FMC_BTR3_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	4195	#define FMC_BTR3_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	4196	#define FMC_BTR3_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4197	#define FMC_BTR3_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4198	#define FMC_BTR3_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4199
Kojto	107:4f6c30876dfa	4200	/**************** Bit definition for FMC_BTR4 register *****************/
Kojto	122:f9eeca106725	4201	#define FMC_BTR4_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4202	#define FMC_BTR4_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4203	#define FMC_BTR4_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4204	#define FMC_BTR4_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4205	#define FMC_BTR4_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4206	#define FMC_BTR4_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4207	#define FMC_BTR4_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4208	#define FMC_BTR4_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4209	#define FMC_BTR4_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4210	#define FMC_BTR4_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4211	#define FMC_BTR4_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4212	#define FMC_BTR4_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4213	#define FMC_BTR4_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4214	#define FMC_BTR4_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4215	#define FMC_BTR4_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4216	#define FMC_BTR4_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4217	#define FMC_BTR4_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4218	#define FMC_BTR4_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4219	#define FMC_BTR4_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4220	#define FMC_BTR4_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4221	#define FMC_BTR4_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4222	#define FMC_BTR4_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4223	#define FMC_BTR4_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4224	#define FMC_BTR4_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4225	#define FMC_BTR4_CLKDIV 0x00F00000U /!<CLKDIV[3:0] bits (Clock divide ratio) /
Kojto	122:f9eeca106725	4226	#define FMC_BTR4_CLKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	4227	#define FMC_BTR4_CLKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	4228	#define FMC_BTR4_CLKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	4229	#define FMC_BTR4_CLKDIV_3 0x00800000U /!<Bit 3 /
Kojto	122:f9eeca106725	4230	#define FMC_BTR4_DATLAT 0x0F000000U /!<DATLA[3:0] bits (Data latency) /
Kojto	122:f9eeca106725	4231	#define FMC_BTR4_DATLAT_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4232	#define FMC_BTR4_DATLAT_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4233	#define FMC_BTR4_DATLAT_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	4234	#define FMC_BTR4_DATLAT_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	4235	#define FMC_BTR4_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4236	#define FMC_BTR4_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4237	#define FMC_BTR4_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4238
Kojto	107:4f6c30876dfa	4239	/**************** Bit definition for FMC_BWTR1 register ****************/
Kojto	122:f9eeca106725	4240	#define FMC_BWTR1_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4241	#define FMC_BWTR1_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4242	#define FMC_BWTR1_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4243	#define FMC_BWTR1_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4244	#define FMC_BWTR1_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4245	#define FMC_BWTR1_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4246	#define FMC_BWTR1_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4247	#define FMC_BWTR1_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4248	#define FMC_BWTR1_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4249	#define FMC_BWTR1_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4250	#define FMC_BWTR1_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4251	#define FMC_BWTR1_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4252	#define FMC_BWTR1_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4253	#define FMC_BWTR1_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4254	#define FMC_BWTR1_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4255	#define FMC_BWTR1_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4256	#define FMC_BWTR1_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4257	#define FMC_BWTR1_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4258	#define FMC_BWTR1_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4259	#define FMC_BWTR1_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4260	#define FMC_BWTR1_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4261	#define FMC_BWTR1_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4262	#define FMC_BWTR1_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4263	#define FMC_BWTR1_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4264	#define FMC_BWTR1_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4265	#define FMC_BWTR1_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4266	#define FMC_BWTR1_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4267
Kojto	107:4f6c30876dfa	4268	/**************** Bit definition for FMC_BWTR2 register ****************/
Kojto	122:f9eeca106725	4269	#define FMC_BWTR2_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4270	#define FMC_BWTR2_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4271	#define FMC_BWTR2_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4272	#define FMC_BWTR2_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4273	#define FMC_BWTR2_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4274	#define FMC_BWTR2_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4275	#define FMC_BWTR2_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4276	#define FMC_BWTR2_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4277	#define FMC_BWTR2_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4278	#define FMC_BWTR2_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4279	#define FMC_BWTR2_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4280	#define FMC_BWTR2_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4281	#define FMC_BWTR2_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4282	#define FMC_BWTR2_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4283	#define FMC_BWTR2_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4284	#define FMC_BWTR2_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4285	#define FMC_BWTR2_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4286	#define FMC_BWTR2_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4287	#define FMC_BWTR2_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4288	#define FMC_BWTR2_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4289	#define FMC_BWTR2_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4290	#define FMC_BWTR2_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4291	#define FMC_BWTR2_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4292	#define FMC_BWTR2_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4293	#define FMC_BWTR2_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4294	#define FMC_BWTR2_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4295	#define FMC_BWTR2_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4296
Kojto	107:4f6c30876dfa	4297	/**************** Bit definition for FMC_BWTR3 register ****************/
Kojto	122:f9eeca106725	4298	#define FMC_BWTR3_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4299	#define FMC_BWTR3_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4300	#define FMC_BWTR3_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4301	#define FMC_BWTR3_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4302	#define FMC_BWTR3_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4303	#define FMC_BWTR3_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4304	#define FMC_BWTR3_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4305	#define FMC_BWTR3_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4306	#define FMC_BWTR3_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4307	#define FMC_BWTR3_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4308	#define FMC_BWTR3_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4309	#define FMC_BWTR3_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4310	#define FMC_BWTR3_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4311	#define FMC_BWTR3_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4312	#define FMC_BWTR3_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4313	#define FMC_BWTR3_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4314	#define FMC_BWTR3_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4315	#define FMC_BWTR3_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4316	#define FMC_BWTR3_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4317	#define FMC_BWTR3_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4318	#define FMC_BWTR3_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4319	#define FMC_BWTR3_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4320	#define FMC_BWTR3_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4321	#define FMC_BWTR3_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4322	#define FMC_BWTR3_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4323	#define FMC_BWTR3_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4324	#define FMC_BWTR3_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4325
Kojto	107:4f6c30876dfa	4326	/**************** Bit definition for FMC_BWTR4 register ****************/
Kojto	122:f9eeca106725	4327	#define FMC_BWTR4_ADDSET 0x0000000FU /!<ADDSET[3:0] bits (Address setup phase duration) /
Kojto	122:f9eeca106725	4328	#define FMC_BWTR4_ADDSET_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4329	#define FMC_BWTR4_ADDSET_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4330	#define FMC_BWTR4_ADDSET_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4331	#define FMC_BWTR4_ADDSET_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4332	#define FMC_BWTR4_ADDHLD 0x000000F0U /!<ADDHLD[3:0] bits (Address-hold phase duration) /
Kojto	122:f9eeca106725	4333	#define FMC_BWTR4_ADDHLD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4334	#define FMC_BWTR4_ADDHLD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4335	#define FMC_BWTR4_ADDHLD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4336	#define FMC_BWTR4_ADDHLD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4337	#define FMC_BWTR4_DATAST 0x0000FF00U /!<DATAST [3:0] bits (Data-phase duration) /
Kojto	122:f9eeca106725	4338	#define FMC_BWTR4_DATAST_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4339	#define FMC_BWTR4_DATAST_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4340	#define FMC_BWTR4_DATAST_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4341	#define FMC_BWTR4_DATAST_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4342	#define FMC_BWTR4_DATAST_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4343	#define FMC_BWTR4_DATAST_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4344	#define FMC_BWTR4_DATAST_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4345	#define FMC_BWTR4_DATAST_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4346	#define FMC_BWTR4_BUSTURN 0x000F0000U /!<BUSTURN[3:0] bits (Bus turnaround phase duration) /
Kojto	122:f9eeca106725	4347	#define FMC_BWTR4_BUSTURN_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4348	#define FMC_BWTR4_BUSTURN_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4349	#define FMC_BWTR4_BUSTURN_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4350	#define FMC_BWTR4_BUSTURN_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4351	#define FMC_BWTR4_ACCMOD 0x30000000U /!<ACCMOD[1:0] bits (Access mode) /
Kojto	122:f9eeca106725	4352	#define FMC_BWTR4_ACCMOD_0 0x10000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4353	#define FMC_BWTR4_ACCMOD_1 0x20000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4354
Kojto	107:4f6c30876dfa	4355	/**************** Bit definition for FMC_PCR register *****************/
Kojto	122:f9eeca106725	4356	#define FMC_PCR_PWAITEN 0x00000002U /!<Wait feature enable bit /
Kojto	122:f9eeca106725	4357	#define FMC_PCR_PBKEN 0x00000004U /!<PC Card/NAND Flash memory bank enable bit /
Kojto	122:f9eeca106725	4358	#define FMC_PCR_PTYP 0x00000008U /!<Memory type /
Kojto	122:f9eeca106725	4359	#define FMC_PCR_PWID 0x00000030U /!<PWID[1:0] bits (NAND Flash databus width) /
Kojto	122:f9eeca106725	4360	#define FMC_PCR_PWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4361	#define FMC_PCR_PWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4362	#define FMC_PCR_ECCEN 0x00000040U /!<ECC computation logic enable bit /
Kojto	122:f9eeca106725	4363	#define FMC_PCR_TCLR 0x00001E00U /!<TCLR[3:0] bits (CLE to RE delay) /
Kojto	122:f9eeca106725	4364	#define FMC_PCR_TCLR_0 0x00000200U /!<Bit 0 /
Kojto	122:f9eeca106725	4365	#define FMC_PCR_TCLR_1 0x00000400U /!<Bit 1 /
Kojto	122:f9eeca106725	4366	#define FMC_PCR_TCLR_2 0x00000800U /!<Bit 2 /
Kojto	122:f9eeca106725	4367	#define FMC_PCR_TCLR_3 0x00001000U /!<Bit 3 /
Kojto	122:f9eeca106725	4368	#define FMC_PCR_TAR 0x0001E000U /!<TAR[3:0] bits (ALE to RE delay) /
Kojto	122:f9eeca106725	4369	#define FMC_PCR_TAR_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	4370	#define FMC_PCR_TAR_1 0x00004000U /!<Bit 1 /
Kojto	122:f9eeca106725	4371	#define FMC_PCR_TAR_2 0x00008000U /!<Bit 2 /
Kojto	122:f9eeca106725	4372	#define FMC_PCR_TAR_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	4373	#define FMC_PCR_ECCPS 0x000E0000U /!<ECCPS[2:0] bits (ECC page size) /
Kojto	122:f9eeca106725	4374	#define FMC_PCR_ECCPS_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	4375	#define FMC_PCR_ECCPS_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	4376	#define FMC_PCR_ECCPS_2 0x00080000U /!<Bit 2 /
Kojto	107:4f6c30876dfa	4377
Kojto	107:4f6c30876dfa	4378	/***************** Bit definition for FMC_SR register *****************/
Kojto	122:f9eeca106725	4379	#define FMC_SR_IRS 0x01U /!<Interrupt Rising Edge status /
Kojto	122:f9eeca106725	4380	#define FMC_SR_ILS 0x02U /!<Interrupt Level status /
Kojto	122:f9eeca106725	4381	#define FMC_SR_IFS 0x04U /!<Interrupt Falling Edge status /
Kojto	122:f9eeca106725	4382	#define FMC_SR_IREN 0x08U /!<Interrupt Rising Edge detection Enable bit /
Kojto	122:f9eeca106725	4383	#define FMC_SR_ILEN 0x10U /!<Interrupt Level detection Enable bit /
Kojto	122:f9eeca106725	4384	#define FMC_SR_IFEN 0x20U /!<Interrupt Falling Edge detection Enable bit /
Kojto	122:f9eeca106725	4385	#define FMC_SR_FEMPT 0x40U /!<FIFO empty /
Kojto	107:4f6c30876dfa	4386
Kojto	107:4f6c30876dfa	4387	/**************** Bit definition for FMC_PMEM register ****************/
Kojto	122:f9eeca106725	4388	#define FMC_PMEM_MEMSET3 0x000000FFU /!<MEMSET3[7:0] bits (Common memory 3 setup time) /
Kojto	122:f9eeca106725	4389	#define FMC_PMEM_MEMSET3_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4390	#define FMC_PMEM_MEMSET3_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4391	#define FMC_PMEM_MEMSET3_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4392	#define FMC_PMEM_MEMSET3_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4393	#define FMC_PMEM_MEMSET3_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	4394	#define FMC_PMEM_MEMSET3_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	4395	#define FMC_PMEM_MEMSET3_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	4396	#define FMC_PMEM_MEMSET3_7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	4397	#define FMC_PMEM_MEMWAIT3 0x0000FF00U /!<MEMWAIT3[7:0] bits (Common memory 3 wait time) /
Kojto	122:f9eeca106725	4398	#define FMC_PMEM_MEMWAIT3_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4399	#define FMC_PMEM_MEMWAIT3_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4400	#define FMC_PMEM_MEMWAIT3_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4401	#define FMC_PMEM_MEMWAIT3_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4402	#define FMC_PMEM_MEMWAIT3_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4403	#define FMC_PMEM_MEMWAIT3_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4404	#define FMC_PMEM_MEMWAIT3_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4405	#define FMC_PMEM_MEMWAIT3_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4406	#define FMC_PMEM_MEMHOLD3 0x00FF0000U /!<MEMHOLD3[7:0] bits (Common memory 3 hold time) /
Kojto	122:f9eeca106725	4407	#define FMC_PMEM_MEMHOLD3_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4408	#define FMC_PMEM_MEMHOLD3_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4409	#define FMC_PMEM_MEMHOLD3_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4410	#define FMC_PMEM_MEMHOLD3_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4411	#define FMC_PMEM_MEMHOLD3_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	4412	#define FMC_PMEM_MEMHOLD3_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	4413	#define FMC_PMEM_MEMHOLD3_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	4414	#define FMC_PMEM_MEMHOLD3_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	4415	#define FMC_PMEM_MEMHIZ3 0xFF000000U /!<MEMHIZ3[7:0] bits (Common memory 3 databus HiZ time) /
Kojto	122:f9eeca106725	4416	#define FMC_PMEM_MEMHIZ3_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4417	#define FMC_PMEM_MEMHIZ3_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4418	#define FMC_PMEM_MEMHIZ3_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	4419	#define FMC_PMEM_MEMHIZ3_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	4420	#define FMC_PMEM_MEMHIZ3_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	4421	#define FMC_PMEM_MEMHIZ3_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	4422	#define FMC_PMEM_MEMHIZ3_6 0x40000000U /!<Bit 6 /
Kojto	122:f9eeca106725	4423	#define FMC_PMEM_MEMHIZ3_7 0x80000000U /!<Bit 7 /
Kojto	107:4f6c30876dfa	4424
Kojto	107:4f6c30876dfa	4425	/**************** Bit definition for FMC_PATT register ****************/
Kojto	122:f9eeca106725	4426	#define FMC_PATT_ATTSET3 0x000000FFU /!<ATTSET3[7:0] bits (Attribute memory 3 setup time) /
Kojto	122:f9eeca106725	4427	#define FMC_PATT_ATTSET3_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4428	#define FMC_PATT_ATTSET3_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4429	#define FMC_PATT_ATTSET3_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4430	#define FMC_PATT_ATTSET3_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4431	#define FMC_PATT_ATTSET3_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	4432	#define FMC_PATT_ATTSET3_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	4433	#define FMC_PATT_ATTSET3_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	4434	#define FMC_PATT_ATTSET3_7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	4435	#define FMC_PATT_ATTWAIT3 0x0000FF00U /!<ATTWAIT3[7:0] bits (Attribute memory 3 wait time) /
Kojto	122:f9eeca106725	4436	#define FMC_PATT_ATTWAIT3_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4437	#define FMC_PATT_ATTWAIT3_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4438	#define FMC_PATT_ATTWAIT3_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4439	#define FMC_PATT_ATTWAIT3_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4440	#define FMC_PATT_ATTWAIT3_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	4441	#define FMC_PATT_ATTWAIT3_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	4442	#define FMC_PATT_ATTWAIT3_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	4443	#define FMC_PATT_ATTWAIT3_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	4444	#define FMC_PATT_ATTHOLD3 0x00FF0000U /!<ATTHOLD3[7:0] bits (Attribute memory 3 hold time) /
Kojto	122:f9eeca106725	4445	#define FMC_PATT_ATTHOLD3_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4446	#define FMC_PATT_ATTHOLD3_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4447	#define FMC_PATT_ATTHOLD3_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4448	#define FMC_PATT_ATTHOLD3_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	4449	#define FMC_PATT_ATTHOLD3_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	4450	#define FMC_PATT_ATTHOLD3_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	4451	#define FMC_PATT_ATTHOLD3_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	4452	#define FMC_PATT_ATTHOLD3_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	4453	#define FMC_PATT_ATTHIZ3 0xFF000000U /!<ATTHIZ3[7:0] bits (Attribute memory 3 databus HiZ time) /
Kojto	122:f9eeca106725	4454	#define FMC_PATT_ATTHIZ3_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4455	#define FMC_PATT_ATTHIZ3_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4456	#define FMC_PATT_ATTHIZ3_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	4457	#define FMC_PATT_ATTHIZ3_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	4458	#define FMC_PATT_ATTHIZ3_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	4459	#define FMC_PATT_ATTHIZ3_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	4460	#define FMC_PATT_ATTHIZ3_6 0x40000000U /!<Bit 6 /
Kojto	122:f9eeca106725	4461	#define FMC_PATT_ATTHIZ3_7 0x80000000U /!<Bit 7 /
Kojto	107:4f6c30876dfa	4462
Kojto	107:4f6c30876dfa	4463	/**************** Bit definition for FMC_ECCR register ****************/
Kojto	122:f9eeca106725	4464	#define FMC_ECCR_ECC3 0xFFFFFFFFU /!<ECC result /
Kojto	107:4f6c30876dfa	4465
Kojto	107:4f6c30876dfa	4466	/**************** Bit definition for FMC_SDCR1 register ****************/
Kojto	122:f9eeca106725	4467	#define FMC_SDCR1_NC 0x00000003U /!<NC[1:0] bits (Number of column bits) /
Kojto	122:f9eeca106725	4468	#define FMC_SDCR1_NC_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4469	#define FMC_SDCR1_NC_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4470	#define FMC_SDCR1_NR 0x0000000CU /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	4471	#define FMC_SDCR1_NR_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	4472	#define FMC_SDCR1_NR_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	4473	#define FMC_SDCR1_MWID 0x00000030U /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	4474	#define FMC_SDCR1_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4475	#define FMC_SDCR1_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4476	#define FMC_SDCR1_NB 0x00000040U /!<Number of internal bank /
Kojto	122:f9eeca106725	4477	#define FMC_SDCR1_CAS 0x00000180U /!<CAS[1:0] bits (CAS latency) /
Kojto	122:f9eeca106725	4478	#define FMC_SDCR1_CAS_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	4479	#define FMC_SDCR1_CAS_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	4480	#define FMC_SDCR1_WP 0x00000200U /!<Write protection /
Kojto	122:f9eeca106725	4481	#define FMC_SDCR1_SDCLK 0x00000C00U /!<SDRAM clock configuration /
Kojto	122:f9eeca106725	4482	#define FMC_SDCR1_SDCLK_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	4483	#define FMC_SDCR1_SDCLK_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	4484	#define FMC_SDCR1_RBURST 0x00001000U /!<Read burst /
Kojto	122:f9eeca106725	4485	#define FMC_SDCR1_RPIPE 0x00006000U /!<Write protection /
Kojto	122:f9eeca106725	4486	#define FMC_SDCR1_RPIPE_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	4487	#define FMC_SDCR1_RPIPE_1 0x00004000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4488
Kojto	107:4f6c30876dfa	4489	/**************** Bit definition for FMC_SDCR2 register ****************/
Kojto	122:f9eeca106725	4490	#define FMC_SDCR2_NC 0x00000003U /!<NC[1:0] bits (Number of column bits) /
Kojto	122:f9eeca106725	4491	#define FMC_SDCR2_NC_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4492	#define FMC_SDCR2_NC_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4493	#define FMC_SDCR2_NR 0x0000000CU /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	4494	#define FMC_SDCR2_NR_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	4495	#define FMC_SDCR2_NR_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	4496	#define FMC_SDCR2_MWID 0x00000030U /!<NR[1:0] bits (Number of row bits) /
Kojto	122:f9eeca106725	4497	#define FMC_SDCR2_MWID_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4498	#define FMC_SDCR2_MWID_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4499	#define FMC_SDCR2_NB 0x00000040U /!<Number of internal bank /
Kojto	122:f9eeca106725	4500	#define FMC_SDCR2_CAS 0x00000180U /!<CAS[1:0] bits (CAS latency) /
Kojto	122:f9eeca106725	4501	#define FMC_SDCR2_CAS_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	4502	#define FMC_SDCR2_CAS_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	4503	#define FMC_SDCR2_WP 0x00000200U /!<Write protection /
Kojto	122:f9eeca106725	4504	#define FMC_SDCR2_SDCLK 0x00000C00U /!<SDCLK[1:0] (SDRAM clock configuration) /
Kojto	122:f9eeca106725	4505	#define FMC_SDCR2_SDCLK_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	4506	#define FMC_SDCR2_SDCLK_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	4507	#define FMC_SDCR2_RBURST 0x00001000U /!<Read burst /
Kojto	122:f9eeca106725	4508	#define FMC_SDCR2_RPIPE 0x00006000U /!<RPIPE[1:0](Read pipe) /
Kojto	122:f9eeca106725	4509	#define FMC_SDCR2_RPIPE_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	4510	#define FMC_SDCR2_RPIPE_1 0x00004000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	4511
Kojto	107:4f6c30876dfa	4512	/**************** Bit definition for FMC_SDTR1 register ****************/
Kojto	122:f9eeca106725	4513	#define FMC_SDTR1_TMRD 0x0000000FU /!<TMRD[3:0] bits (Load mode register to active) /
Kojto	122:f9eeca106725	4514	#define FMC_SDTR1_TMRD_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4515	#define FMC_SDTR1_TMRD_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4516	#define FMC_SDTR1_TMRD_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4517	#define FMC_SDTR1_TMRD_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4518	#define FMC_SDTR1_TXSR 0x000000F0U /!<TXSR[3:0] bits (Exit self refresh) /
Kojto	122:f9eeca106725	4519	#define FMC_SDTR1_TXSR_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4520	#define FMC_SDTR1_TXSR_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4521	#define FMC_SDTR1_TXSR_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4522	#define FMC_SDTR1_TXSR_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4523	#define FMC_SDTR1_TRAS 0x00000F00U /!<TRAS[3:0] bits (Self refresh time) /
Kojto	122:f9eeca106725	4524	#define FMC_SDTR1_TRAS_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4525	#define FMC_SDTR1_TRAS_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4526	#define FMC_SDTR1_TRAS_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4527	#define FMC_SDTR1_TRAS_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4528	#define FMC_SDTR1_TRC 0x0000F000U /!<TRC[2:0] bits (Row cycle delay) /
Kojto	122:f9eeca106725	4529	#define FMC_SDTR1_TRC_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	4530	#define FMC_SDTR1_TRC_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	4531	#define FMC_SDTR1_TRC_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	4532	#define FMC_SDTR1_TWR 0x000F0000U /!<TRC[2:0] bits (Write recovery delay) /
Kojto	122:f9eeca106725	4533	#define FMC_SDTR1_TWR_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4534	#define FMC_SDTR1_TWR_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4535	#define FMC_SDTR1_TWR_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4536	#define FMC_SDTR1_TRP 0x00F00000U /!<TRP[2:0] bits (Row precharge delay) /
Kojto	122:f9eeca106725	4537	#define FMC_SDTR1_TRP_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	4538	#define FMC_SDTR1_TRP_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	4539	#define FMC_SDTR1_TRP_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	4540	#define FMC_SDTR1_TRCD 0x0F000000U /!<TRP[2:0] bits (Row to column delay) /
Kojto	122:f9eeca106725	4541	#define FMC_SDTR1_TRCD_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4542	#define FMC_SDTR1_TRCD_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4543	#define FMC_SDTR1_TRCD_2 0x04000000U /!<Bit 2 /
Kojto	107:4f6c30876dfa	4544
Kojto	107:4f6c30876dfa	4545	/**************** Bit definition for FMC_SDTR2 register ****************/
Kojto	122:f9eeca106725	4546	#define FMC_SDTR2_TMRD 0x0000000FU /!<TMRD[3:0] bits (Load mode register to active) /
Kojto	122:f9eeca106725	4547	#define FMC_SDTR2_TMRD_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4548	#define FMC_SDTR2_TMRD_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4549	#define FMC_SDTR2_TMRD_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	4550	#define FMC_SDTR2_TMRD_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	4551	#define FMC_SDTR2_TXSR 0x000000F0U /!<TXSR[3:0] bits (Exit self refresh) /
Kojto	122:f9eeca106725	4552	#define FMC_SDTR2_TXSR_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	4553	#define FMC_SDTR2_TXSR_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	4554	#define FMC_SDTR2_TXSR_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	4555	#define FMC_SDTR2_TXSR_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	4556	#define FMC_SDTR2_TRAS 0x00000F00U /!<TRAS[3:0] bits (Self refresh time) /
Kojto	122:f9eeca106725	4557	#define FMC_SDTR2_TRAS_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	4558	#define FMC_SDTR2_TRAS_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	4559	#define FMC_SDTR2_TRAS_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	4560	#define FMC_SDTR2_TRAS_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	4561	#define FMC_SDTR2_TRC 0x0000F000U /!<TRC[2:0] bits (Row cycle delay) /
Kojto	122:f9eeca106725	4562	#define FMC_SDTR2_TRC_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	4563	#define FMC_SDTR2_TRC_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	4564	#define FMC_SDTR2_TRC_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	4565	#define FMC_SDTR2_TWR 0x000F0000U /!<TRC[2:0] bits (Write recovery delay) /
Kojto	122:f9eeca106725	4566	#define FMC_SDTR2_TWR_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	4567	#define FMC_SDTR2_TWR_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	4568	#define FMC_SDTR2_TWR_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	4569	#define FMC_SDTR2_TRP 0x00F00000U /!<TRP[2:0] bits (Row precharge delay) /
Kojto	122:f9eeca106725	4570	#define FMC_SDTR2_TRP_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	4571	#define FMC_SDTR2_TRP_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	4572	#define FMC_SDTR2_TRP_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	4573	#define FMC_SDTR2_TRCD 0x0F000000U /!<TRP[2:0] bits (Row to column delay) /
Kojto	122:f9eeca106725	4574	#define FMC_SDTR2_TRCD_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	4575	#define FMC_SDTR2_TRCD_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	4576	#define FMC_SDTR2_TRCD_2 0x04000000U /!<Bit 2 /
Kojto	107:4f6c30876dfa	4577
Kojto	107:4f6c30876dfa	4578	/**************** Bit definition for FMC_SDCMR register ****************/
Kojto	122:f9eeca106725	4579	#define FMC_SDCMR_MODE 0x00000007U /!<MODE[2:0] bits (Command mode) /
Kojto	122:f9eeca106725	4580	#define FMC_SDCMR_MODE_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	4581	#define FMC_SDCMR_MODE_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	4582	#define FMC_SDCMR_MODE_2 0x00000003U /!<Bit 2 /
Kojto	122:f9eeca106725	4583	#define FMC_SDCMR_CTB2 0x00000008U /!<Command target 2 /
Kojto	122:f9eeca106725	4584	#define FMC_SDCMR_CTB1 0x00000010U /!<Command target 1 /
Kojto	122:f9eeca106725	4585	#define FMC_SDCMR_NRFS 0x000001E0U /!<NRFS[3:0] bits (Number of auto-refresh) /
Kojto	122:f9eeca106725	4586	#define FMC_SDCMR_NRFS_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	4587	#define FMC_SDCMR_NRFS_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	4588	#define FMC_SDCMR_NRFS_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	4589	#define FMC_SDCMR_NRFS_3 0x00000100U /!<Bit 3 /
Kojto	122:f9eeca106725	4590	#define FMC_SDCMR_MRD 0x003FFE00U /!<MRD[12:0] bits (Mode register definition) /
Kojto	107:4f6c30876dfa	4591
Kojto	107:4f6c30876dfa	4592	/**************** Bit definition for FMC_SDRTR register ****************/
Kojto	122:f9eeca106725	4593	#define FMC_SDRTR_CRE 0x00000001U /!<Clear refresh error flag /
Kojto	122:f9eeca106725	4594	#define FMC_SDRTR_COUNT 0x00003FFEU /!<COUNT[12:0] bits (Refresh timer count) /
Kojto	122:f9eeca106725	4595	#define FMC_SDRTR_REIE 0x00004000U /!<RES interupt enable /
Kojto	107:4f6c30876dfa	4596
Kojto	107:4f6c30876dfa	4597	/**************** Bit definition for FMC_SDSR register ****************/
Kojto	122:f9eeca106725	4598	#define FMC_SDSR_RE 0x00000001U /!<Refresh error flag /
Kojto	122:f9eeca106725	4599	#define FMC_SDSR_MODES1 0x00000006U /!<MODES1[1:0]bits (Status mode for bank 1) /
Kojto	122:f9eeca106725	4600	#define FMC_SDSR_MODES1_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	4601	#define FMC_SDSR_MODES1_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	4602	#define FMC_SDSR_MODES2 0x00000018U /!<MODES2[1:0]bits (Status mode for bank 2) /
Kojto	122:f9eeca106725	4603	#define FMC_SDSR_MODES2_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	4604	#define FMC_SDSR_MODES2_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	4605	#define FMC_SDSR_BUSY 0x00000020U /!<Busy status /
Kojto	107:4f6c30876dfa	4606
Kojto	107:4f6c30876dfa	4607	/******************************************************************************/
Kojto	107:4f6c30876dfa	4608	/* */
Kojto	107:4f6c30876dfa	4609	/* General Purpose I/O */
Kojto	107:4f6c30876dfa	4610	/* */
Kojto	107:4f6c30876dfa	4611	/******************************************************************************/
Kojto	107:4f6c30876dfa	4612	/**************** Bits definition for GPIO_MODER register ***************/
Kojto	122:f9eeca106725	4613	#define GPIO_MODER_MODER0 0x00000003U
Kojto	122:f9eeca106725	4614	#define GPIO_MODER_MODER0_0 0x00000001U
Kojto	122:f9eeca106725	4615	#define GPIO_MODER_MODER0_1 0x00000002U
Kojto	122:f9eeca106725	4616	#define GPIO_MODER_MODER1 0x0000000CU
Kojto	122:f9eeca106725	4617	#define GPIO_MODER_MODER1_0 0x00000004U
Kojto	122:f9eeca106725	4618	#define GPIO_MODER_MODER1_1 0x00000008U
Kojto	122:f9eeca106725	4619	#define GPIO_MODER_MODER2 0x00000030U
Kojto	122:f9eeca106725	4620	#define GPIO_MODER_MODER2_0 0x00000010U
Kojto	122:f9eeca106725	4621	#define GPIO_MODER_MODER2_1 0x00000020U
Kojto	122:f9eeca106725	4622	#define GPIO_MODER_MODER3 0x000000C0U
Kojto	122:f9eeca106725	4623	#define GPIO_MODER_MODER3_0 0x00000040U
Kojto	122:f9eeca106725	4624	#define GPIO_MODER_MODER3_1 0x00000080U
Kojto	122:f9eeca106725	4625	#define GPIO_MODER_MODER4 0x00000300U
Kojto	122:f9eeca106725	4626	#define GPIO_MODER_MODER4_0 0x00000100U
Kojto	122:f9eeca106725	4627	#define GPIO_MODER_MODER4_1 0x00000200U
Kojto	122:f9eeca106725	4628	#define GPIO_MODER_MODER5 0x00000C00U
Kojto	122:f9eeca106725	4629	#define GPIO_MODER_MODER5_0 0x00000400U
Kojto	122:f9eeca106725	4630	#define GPIO_MODER_MODER5_1 0x00000800U
Kojto	122:f9eeca106725	4631	#define GPIO_MODER_MODER6 0x00003000U
Kojto	122:f9eeca106725	4632	#define GPIO_MODER_MODER6_0 0x00001000U
Kojto	122:f9eeca106725	4633	#define GPIO_MODER_MODER6_1 0x00002000U
Kojto	122:f9eeca106725	4634	#define GPIO_MODER_MODER7 0x0000C000U
Kojto	122:f9eeca106725	4635	#define GPIO_MODER_MODER7_0 0x00004000U
Kojto	122:f9eeca106725	4636	#define GPIO_MODER_MODER7_1 0x00008000U
Kojto	122:f9eeca106725	4637	#define GPIO_MODER_MODER8 0x00030000U
Kojto	122:f9eeca106725	4638	#define GPIO_MODER_MODER8_0 0x00010000U
Kojto	122:f9eeca106725	4639	#define GPIO_MODER_MODER8_1 0x00020000U
Kojto	122:f9eeca106725	4640	#define GPIO_MODER_MODER9 0x000C0000U
Kojto	122:f9eeca106725	4641	#define GPIO_MODER_MODER9_0 0x00040000U
Kojto	122:f9eeca106725	4642	#define GPIO_MODER_MODER9_1 0x00080000U
Kojto	122:f9eeca106725	4643	#define GPIO_MODER_MODER10 0x00300000U
Kojto	122:f9eeca106725	4644	#define GPIO_MODER_MODER10_0 0x00100000U
Kojto	122:f9eeca106725	4645	#define GPIO_MODER_MODER10_1 0x00200000U
Kojto	122:f9eeca106725	4646	#define GPIO_MODER_MODER11 0x00C00000U
Kojto	122:f9eeca106725	4647	#define GPIO_MODER_MODER11_0 0x00400000U
Kojto	122:f9eeca106725	4648	#define GPIO_MODER_MODER11_1 0x00800000U
Kojto	122:f9eeca106725	4649	#define GPIO_MODER_MODER12 0x03000000U
Kojto	122:f9eeca106725	4650	#define GPIO_MODER_MODER12_0 0x01000000U
Kojto	122:f9eeca106725	4651	#define GPIO_MODER_MODER12_1 0x02000000U
Kojto	122:f9eeca106725	4652	#define GPIO_MODER_MODER13 0x0C000000U
Kojto	122:f9eeca106725	4653	#define GPIO_MODER_MODER13_0 0x04000000U
Kojto	122:f9eeca106725	4654	#define GPIO_MODER_MODER13_1 0x08000000U
Kojto	122:f9eeca106725	4655	#define GPIO_MODER_MODER14 0x30000000U
Kojto	122:f9eeca106725	4656	#define GPIO_MODER_MODER14_0 0x10000000U
Kojto	122:f9eeca106725	4657	#define GPIO_MODER_MODER14_1 0x20000000U
Kojto	122:f9eeca106725	4658	#define GPIO_MODER_MODER15 0xC0000000U
Kojto	122:f9eeca106725	4659	#define GPIO_MODER_MODER15_0 0x40000000U
Kojto	122:f9eeca106725	4660	#define GPIO_MODER_MODER15_1 0x80000000U
Kojto	107:4f6c30876dfa	4661
Kojto	107:4f6c30876dfa	4662	/**************** Bits definition for GPIO_OTYPER register **************/
Kojto	122:f9eeca106725	4663	#define GPIO_OTYPER_OT_0 0x00000001U
Kojto	122:f9eeca106725	4664	#define GPIO_OTYPER_OT_1 0x00000002U
Kojto	122:f9eeca106725	4665	#define GPIO_OTYPER_OT_2 0x00000004U
Kojto	122:f9eeca106725	4666	#define GPIO_OTYPER_OT_3 0x00000008U
Kojto	122:f9eeca106725	4667	#define GPIO_OTYPER_OT_4 0x00000010U
Kojto	122:f9eeca106725	4668	#define GPIO_OTYPER_OT_5 0x00000020U
Kojto	122:f9eeca106725	4669	#define GPIO_OTYPER_OT_6 0x00000040U
Kojto	122:f9eeca106725	4670	#define GPIO_OTYPER_OT_7 0x00000080U
Kojto	122:f9eeca106725	4671	#define GPIO_OTYPER_OT_8 0x00000100U
Kojto	122:f9eeca106725	4672	#define GPIO_OTYPER_OT_9 0x00000200U
Kojto	122:f9eeca106725	4673	#define GPIO_OTYPER_OT_10 0x00000400U
Kojto	122:f9eeca106725	4674	#define GPIO_OTYPER_OT_11 0x00000800U
Kojto	122:f9eeca106725	4675	#define GPIO_OTYPER_OT_12 0x00001000U
Kojto	122:f9eeca106725	4676	#define GPIO_OTYPER_OT_13 0x00002000U
Kojto	122:f9eeca106725	4677	#define GPIO_OTYPER_OT_14 0x00004000U
Kojto	122:f9eeca106725	4678	#define GPIO_OTYPER_OT_15 0x00008000U
Kojto	107:4f6c30876dfa	4679
Kojto	107:4f6c30876dfa	4680	/**************** Bits definition for GPIO_OSPEEDR register *************/
Kojto	122:f9eeca106725	4681	#define GPIO_OSPEEDER_OSPEEDR0 0x00000003U
Kojto	122:f9eeca106725	4682	#define GPIO_OSPEEDER_OSPEEDR0_0 0x00000001U
Kojto	122:f9eeca106725	4683	#define GPIO_OSPEEDER_OSPEEDR0_1 0x00000002U
Kojto	122:f9eeca106725	4684	#define GPIO_OSPEEDER_OSPEEDR1 0x0000000CU
Kojto	122:f9eeca106725	4685	#define GPIO_OSPEEDER_OSPEEDR1_0 0x00000004U
Kojto	122:f9eeca106725	4686	#define GPIO_OSPEEDER_OSPEEDR1_1 0x00000008U
Kojto	122:f9eeca106725	4687	#define GPIO_OSPEEDER_OSPEEDR2 0x00000030U
Kojto	122:f9eeca106725	4688	#define GPIO_OSPEEDER_OSPEEDR2_0 0x00000010U
Kojto	122:f9eeca106725	4689	#define GPIO_OSPEEDER_OSPEEDR2_1 0x00000020U
Kojto	122:f9eeca106725	4690	#define GPIO_OSPEEDER_OSPEEDR3 0x000000C0U
Kojto	122:f9eeca106725	4691	#define GPIO_OSPEEDER_OSPEEDR3_0 0x00000040U
Kojto	122:f9eeca106725	4692	#define GPIO_OSPEEDER_OSPEEDR3_1 0x00000080U
Kojto	122:f9eeca106725	4693	#define GPIO_OSPEEDER_OSPEEDR4 0x00000300U
Kojto	122:f9eeca106725	4694	#define GPIO_OSPEEDER_OSPEEDR4_0 0x00000100U
Kojto	122:f9eeca106725	4695	#define GPIO_OSPEEDER_OSPEEDR4_1 0x00000200U
Kojto	122:f9eeca106725	4696	#define GPIO_OSPEEDER_OSPEEDR5 0x00000C00U
Kojto	122:f9eeca106725	4697	#define GPIO_OSPEEDER_OSPEEDR5_0 0x00000400U
Kojto	122:f9eeca106725	4698	#define GPIO_OSPEEDER_OSPEEDR5_1 0x00000800U
Kojto	122:f9eeca106725	4699	#define GPIO_OSPEEDER_OSPEEDR6 0x00003000U
Kojto	122:f9eeca106725	4700	#define GPIO_OSPEEDER_OSPEEDR6_0 0x00001000U
Kojto	122:f9eeca106725	4701	#define GPIO_OSPEEDER_OSPEEDR6_1 0x00002000U
Kojto	122:f9eeca106725	4702	#define GPIO_OSPEEDER_OSPEEDR7 0x0000C000U
Kojto	122:f9eeca106725	4703	#define GPIO_OSPEEDER_OSPEEDR7_0 0x00004000U
Kojto	122:f9eeca106725	4704	#define GPIO_OSPEEDER_OSPEEDR7_1 0x00008000U
Kojto	122:f9eeca106725	4705	#define GPIO_OSPEEDER_OSPEEDR8 0x00030000U
Kojto	122:f9eeca106725	4706	#define GPIO_OSPEEDER_OSPEEDR8_0 0x00010000U
Kojto	122:f9eeca106725	4707	#define GPIO_OSPEEDER_OSPEEDR8_1 0x00020000U
Kojto	122:f9eeca106725	4708	#define GPIO_OSPEEDER_OSPEEDR9 0x000C0000U
Kojto	122:f9eeca106725	4709	#define GPIO_OSPEEDER_OSPEEDR9_0 0x00040000U
Kojto	122:f9eeca106725	4710	#define GPIO_OSPEEDER_OSPEEDR9_1 0x00080000U
Kojto	122:f9eeca106725	4711	#define GPIO_OSPEEDER_OSPEEDR10 0x00300000U
Kojto	122:f9eeca106725	4712	#define GPIO_OSPEEDER_OSPEEDR10_0 0x00100000U
Kojto	122:f9eeca106725	4713	#define GPIO_OSPEEDER_OSPEEDR10_1 0x00200000U
Kojto	122:f9eeca106725	4714	#define GPIO_OSPEEDER_OSPEEDR11 0x00C00000U
Kojto	122:f9eeca106725	4715	#define GPIO_OSPEEDER_OSPEEDR11_0 0x00400000U
Kojto	122:f9eeca106725	4716	#define GPIO_OSPEEDER_OSPEEDR11_1 0x00800000U
Kojto	122:f9eeca106725	4717	#define GPIO_OSPEEDER_OSPEEDR12 0x03000000U
Kojto	122:f9eeca106725	4718	#define GPIO_OSPEEDER_OSPEEDR12_0 0x01000000U
Kojto	122:f9eeca106725	4719	#define GPIO_OSPEEDER_OSPEEDR12_1 0x02000000U
Kojto	122:f9eeca106725	4720	#define GPIO_OSPEEDER_OSPEEDR13 0x0C000000U
Kojto	122:f9eeca106725	4721	#define GPIO_OSPEEDER_OSPEEDR13_0 0x04000000U
Kojto	122:f9eeca106725	4722	#define GPIO_OSPEEDER_OSPEEDR13_1 0x08000000U
Kojto	122:f9eeca106725	4723	#define GPIO_OSPEEDER_OSPEEDR14 0x30000000U
Kojto	122:f9eeca106725	4724	#define GPIO_OSPEEDER_OSPEEDR14_0 0x10000000U
Kojto	122:f9eeca106725	4725	#define GPIO_OSPEEDER_OSPEEDR14_1 0x20000000U
Kojto	122:f9eeca106725	4726	#define GPIO_OSPEEDER_OSPEEDR15 0xC0000000U
Kojto	122:f9eeca106725	4727	#define GPIO_OSPEEDER_OSPEEDR15_0 0x40000000U
Kojto	122:f9eeca106725	4728	#define GPIO_OSPEEDER_OSPEEDR15_1 0x80000000U
Kojto	107:4f6c30876dfa	4729
Kojto	107:4f6c30876dfa	4730	/**************** Bits definition for GPIO_PUPDR register ***************/
Kojto	122:f9eeca106725	4731	#define GPIO_PUPDR_PUPDR0 0x00000003U
Kojto	122:f9eeca106725	4732	#define GPIO_PUPDR_PUPDR0_0 0x00000001U
Kojto	122:f9eeca106725	4733	#define GPIO_PUPDR_PUPDR0_1 0x00000002U
Kojto	122:f9eeca106725	4734	#define GPIO_PUPDR_PUPDR1 0x0000000CU
Kojto	122:f9eeca106725	4735	#define GPIO_PUPDR_PUPDR1_0 0x00000004U
Kojto	122:f9eeca106725	4736	#define GPIO_PUPDR_PUPDR1_1 0x00000008U
Kojto	122:f9eeca106725	4737	#define GPIO_PUPDR_PUPDR2 0x00000030U
Kojto	122:f9eeca106725	4738	#define GPIO_PUPDR_PUPDR2_0 0x00000010U
Kojto	122:f9eeca106725	4739	#define GPIO_PUPDR_PUPDR2_1 0x00000020U
Kojto	122:f9eeca106725	4740	#define GPIO_PUPDR_PUPDR3 0x000000C0U
Kojto	122:f9eeca106725	4741	#define GPIO_PUPDR_PUPDR3_0 0x00000040U
Kojto	122:f9eeca106725	4742	#define GPIO_PUPDR_PUPDR3_1 0x00000080U
Kojto	122:f9eeca106725	4743	#define GPIO_PUPDR_PUPDR4 0x00000300U
Kojto	122:f9eeca106725	4744	#define GPIO_PUPDR_PUPDR4_0 0x00000100U
Kojto	122:f9eeca106725	4745	#define GPIO_PUPDR_PUPDR4_1 0x00000200U
Kojto	122:f9eeca106725	4746	#define GPIO_PUPDR_PUPDR5 0x00000C00U
Kojto	122:f9eeca106725	4747	#define GPIO_PUPDR_PUPDR5_0 0x00000400U
Kojto	122:f9eeca106725	4748	#define GPIO_PUPDR_PUPDR5_1 0x00000800U
Kojto	122:f9eeca106725	4749	#define GPIO_PUPDR_PUPDR6 0x00003000U
Kojto	122:f9eeca106725	4750	#define GPIO_PUPDR_PUPDR6_0 0x00001000U
Kojto	122:f9eeca106725	4751	#define GPIO_PUPDR_PUPDR6_1 0x00002000U
Kojto	122:f9eeca106725	4752	#define GPIO_PUPDR_PUPDR7 0x0000C000U
Kojto	122:f9eeca106725	4753	#define GPIO_PUPDR_PUPDR7_0 0x00004000U
Kojto	122:f9eeca106725	4754	#define GPIO_PUPDR_PUPDR7_1 0x00008000U
Kojto	122:f9eeca106725	4755	#define GPIO_PUPDR_PUPDR8 0x00030000U
Kojto	122:f9eeca106725	4756	#define GPIO_PUPDR_PUPDR8_0 0x00010000U
Kojto	122:f9eeca106725	4757	#define GPIO_PUPDR_PUPDR8_1 0x00020000U
Kojto	122:f9eeca106725	4758	#define GPIO_PUPDR_PUPDR9 0x000C0000U
Kojto	122:f9eeca106725	4759	#define GPIO_PUPDR_PUPDR9_0 0x00040000U
Kojto	122:f9eeca106725	4760	#define GPIO_PUPDR_PUPDR9_1 0x00080000U
Kojto	122:f9eeca106725	4761	#define GPIO_PUPDR_PUPDR10 0x00300000U
Kojto	122:f9eeca106725	4762	#define GPIO_PUPDR_PUPDR10_0 0x00100000U
Kojto	122:f9eeca106725	4763	#define GPIO_PUPDR_PUPDR10_1 0x00200000U
Kojto	122:f9eeca106725	4764	#define GPIO_PUPDR_PUPDR11 0x00C00000U
Kojto	122:f9eeca106725	4765	#define GPIO_PUPDR_PUPDR11_0 0x00400000U
Kojto	122:f9eeca106725	4766	#define GPIO_PUPDR_PUPDR11_1 0x00800000U
Kojto	122:f9eeca106725	4767	#define GPIO_PUPDR_PUPDR12 0x03000000U
Kojto	122:f9eeca106725	4768	#define GPIO_PUPDR_PUPDR12_0 0x01000000U
Kojto	122:f9eeca106725	4769	#define GPIO_PUPDR_PUPDR12_1 0x02000000U
Kojto	122:f9eeca106725	4770	#define GPIO_PUPDR_PUPDR13 0x0C000000U
Kojto	122:f9eeca106725	4771	#define GPIO_PUPDR_PUPDR13_0 0x04000000U
Kojto	122:f9eeca106725	4772	#define GPIO_PUPDR_PUPDR13_1 0x08000000U
Kojto	122:f9eeca106725	4773	#define GPIO_PUPDR_PUPDR14 0x30000000U
Kojto	122:f9eeca106725	4774	#define GPIO_PUPDR_PUPDR14_0 0x10000000U
Kojto	122:f9eeca106725	4775	#define GPIO_PUPDR_PUPDR14_1 0x20000000U
Kojto	122:f9eeca106725	4776	#define GPIO_PUPDR_PUPDR15 0xC0000000U
Kojto	122:f9eeca106725	4777	#define GPIO_PUPDR_PUPDR15_0 0x40000000U
Kojto	122:f9eeca106725	4778	#define GPIO_PUPDR_PUPDR15_1 0x80000000U
Kojto	107:4f6c30876dfa	4779
Kojto	107:4f6c30876dfa	4780	/**************** Bits definition for GPIO_IDR register *****************/
Kojto	122:f9eeca106725	4781	#define GPIO_IDR_IDR_0 0x00000001U
Kojto	122:f9eeca106725	4782	#define GPIO_IDR_IDR_1 0x00000002U
Kojto	122:f9eeca106725	4783	#define GPIO_IDR_IDR_2 0x00000004U
Kojto	122:f9eeca106725	4784	#define GPIO_IDR_IDR_3 0x00000008U
Kojto	122:f9eeca106725	4785	#define GPIO_IDR_IDR_4 0x00000010U
Kojto	122:f9eeca106725	4786	#define GPIO_IDR_IDR_5 0x00000020U
Kojto	122:f9eeca106725	4787	#define GPIO_IDR_IDR_6 0x00000040U
Kojto	122:f9eeca106725	4788	#define GPIO_IDR_IDR_7 0x00000080U
Kojto	122:f9eeca106725	4789	#define GPIO_IDR_IDR_8 0x00000100U
Kojto	122:f9eeca106725	4790	#define GPIO_IDR_IDR_9 0x00000200U
Kojto	122:f9eeca106725	4791	#define GPIO_IDR_IDR_10 0x00000400U
Kojto	122:f9eeca106725	4792	#define GPIO_IDR_IDR_11 0x00000800U
Kojto	122:f9eeca106725	4793	#define GPIO_IDR_IDR_12 0x00001000U
Kojto	122:f9eeca106725	4794	#define GPIO_IDR_IDR_13 0x00002000U
Kojto	122:f9eeca106725	4795	#define GPIO_IDR_IDR_14 0x00004000U
Kojto	122:f9eeca106725	4796	#define GPIO_IDR_IDR_15 0x00008000U
Kojto	107:4f6c30876dfa	4797
Kojto	107:4f6c30876dfa	4798	/**************** Bits definition for GPIO_ODR register *****************/
Kojto	122:f9eeca106725	4799	#define GPIO_ODR_ODR_0 0x00000001U
Kojto	122:f9eeca106725	4800	#define GPIO_ODR_ODR_1 0x00000002U
Kojto	122:f9eeca106725	4801	#define GPIO_ODR_ODR_2 0x00000004U
Kojto	122:f9eeca106725	4802	#define GPIO_ODR_ODR_3 0x00000008U
Kojto	122:f9eeca106725	4803	#define GPIO_ODR_ODR_4 0x00000010U
Kojto	122:f9eeca106725	4804	#define GPIO_ODR_ODR_5 0x00000020U
Kojto	122:f9eeca106725	4805	#define GPIO_ODR_ODR_6 0x00000040U
Kojto	122:f9eeca106725	4806	#define GPIO_ODR_ODR_7 0x00000080U
Kojto	122:f9eeca106725	4807	#define GPIO_ODR_ODR_8 0x00000100U
Kojto	122:f9eeca106725	4808	#define GPIO_ODR_ODR_9 0x00000200U
Kojto	122:f9eeca106725	4809	#define GPIO_ODR_ODR_10 0x00000400U
Kojto	122:f9eeca106725	4810	#define GPIO_ODR_ODR_11 0x00000800U
Kojto	122:f9eeca106725	4811	#define GPIO_ODR_ODR_12 0x00001000U
Kojto	122:f9eeca106725	4812	#define GPIO_ODR_ODR_13 0x00002000U
Kojto	122:f9eeca106725	4813	#define GPIO_ODR_ODR_14 0x00004000U
Kojto	122:f9eeca106725	4814	#define GPIO_ODR_ODR_15 0x00008000U
Kojto	107:4f6c30876dfa	4815
Kojto	107:4f6c30876dfa	4816	/**************** Bits definition for GPIO_BSRR register ****************/
Kojto	122:f9eeca106725	4817	#define GPIO_BSRR_BS_0 0x00000001U
Kojto	122:f9eeca106725	4818	#define GPIO_BSRR_BS_1 0x00000002U
Kojto	122:f9eeca106725	4819	#define GPIO_BSRR_BS_2 0x00000004U
Kojto	122:f9eeca106725	4820	#define GPIO_BSRR_BS_3 0x00000008U
Kojto	122:f9eeca106725	4821	#define GPIO_BSRR_BS_4 0x00000010U
Kojto	122:f9eeca106725	4822	#define GPIO_BSRR_BS_5 0x00000020U
Kojto	122:f9eeca106725	4823	#define GPIO_BSRR_BS_6 0x00000040U
Kojto	122:f9eeca106725	4824	#define GPIO_BSRR_BS_7 0x00000080U
Kojto	122:f9eeca106725	4825	#define GPIO_BSRR_BS_8 0x00000100U
Kojto	122:f9eeca106725	4826	#define GPIO_BSRR_BS_9 0x00000200U
Kojto	122:f9eeca106725	4827	#define GPIO_BSRR_BS_10 0x00000400U
Kojto	122:f9eeca106725	4828	#define GPIO_BSRR_BS_11 0x00000800U
Kojto	122:f9eeca106725	4829	#define GPIO_BSRR_BS_12 0x00001000U
Kojto	122:f9eeca106725	4830	#define GPIO_BSRR_BS_13 0x00002000U
Kojto	122:f9eeca106725	4831	#define GPIO_BSRR_BS_14 0x00004000U
Kojto	122:f9eeca106725	4832	#define GPIO_BSRR_BS_15 0x00008000U
Kojto	122:f9eeca106725	4833	#define GPIO_BSRR_BR_0 0x00010000U
Kojto	122:f9eeca106725	4834	#define GPIO_BSRR_BR_1 0x00020000U
Kojto	122:f9eeca106725	4835	#define GPIO_BSRR_BR_2 0x00040000U
Kojto	122:f9eeca106725	4836	#define GPIO_BSRR_BR_3 0x00080000U
Kojto	122:f9eeca106725	4837	#define GPIO_BSRR_BR_4 0x00100000U
Kojto	122:f9eeca106725	4838	#define GPIO_BSRR_BR_5 0x00200000U
Kojto	122:f9eeca106725	4839	#define GPIO_BSRR_BR_6 0x00400000U
Kojto	122:f9eeca106725	4840	#define GPIO_BSRR_BR_7 0x00800000U
Kojto	122:f9eeca106725	4841	#define GPIO_BSRR_BR_8 0x01000000U
Kojto	122:f9eeca106725	4842	#define GPIO_BSRR_BR_9 0x02000000U
Kojto	122:f9eeca106725	4843	#define GPIO_BSRR_BR_10 0x04000000U
Kojto	122:f9eeca106725	4844	#define GPIO_BSRR_BR_11 0x08000000U
Kojto	122:f9eeca106725	4845	#define GPIO_BSRR_BR_12 0x10000000U
Kojto	122:f9eeca106725	4846	#define GPIO_BSRR_BR_13 0x20000000U
Kojto	122:f9eeca106725	4847	#define GPIO_BSRR_BR_14 0x40000000U
Kojto	122:f9eeca106725	4848	#define GPIO_BSRR_BR_15 0x80000000U
Kojto	107:4f6c30876dfa	4849
Kojto	107:4f6c30876dfa	4850	/**************** Bit definition for GPIO_LCKR register *******************/
Kojto	122:f9eeca106725	4851	#define GPIO_LCKR_LCK0 0x00000001U
Kojto	122:f9eeca106725	4852	#define GPIO_LCKR_LCK1 0x00000002U
Kojto	122:f9eeca106725	4853	#define GPIO_LCKR_LCK2 0x00000004U
Kojto	122:f9eeca106725	4854	#define GPIO_LCKR_LCK3 0x00000008U
Kojto	122:f9eeca106725	4855	#define GPIO_LCKR_LCK4 0x00000010U
Kojto	122:f9eeca106725	4856	#define GPIO_LCKR_LCK5 0x00000020U
Kojto	122:f9eeca106725	4857	#define GPIO_LCKR_LCK6 0x00000040U
Kojto	122:f9eeca106725	4858	#define GPIO_LCKR_LCK7 0x00000080U
Kojto	122:f9eeca106725	4859	#define GPIO_LCKR_LCK8 0x00000100U
Kojto	122:f9eeca106725	4860	#define GPIO_LCKR_LCK9 0x00000200U
Kojto	122:f9eeca106725	4861	#define GPIO_LCKR_LCK10 0x00000400U
Kojto	122:f9eeca106725	4862	#define GPIO_LCKR_LCK11 0x00000800U
Kojto	122:f9eeca106725	4863	#define GPIO_LCKR_LCK12 0x00001000U
Kojto	122:f9eeca106725	4864	#define GPIO_LCKR_LCK13 0x00002000U
Kojto	122:f9eeca106725	4865	#define GPIO_LCKR_LCK14 0x00004000U
Kojto	122:f9eeca106725	4866	#define GPIO_LCKR_LCK15 0x00008000U
Kojto	122:f9eeca106725	4867	#define GPIO_LCKR_LCKK 0x00010000U
Kojto	107:4f6c30876dfa	4868
Kojto	116:c0f6e94411f5	4869
Kojto	107:4f6c30876dfa	4870	/******************************************************************************/
Kojto	107:4f6c30876dfa	4871	/* */
Kojto	107:4f6c30876dfa	4872	/* Inter-integrated Circuit Interface (I2C) */
Kojto	107:4f6c30876dfa	4873	/* */
Kojto	107:4f6c30876dfa	4874	/******************************************************************************/
Kojto	107:4f6c30876dfa	4875	/***************** Bit definition for I2C_CR1 register *****************/
Kojto	122:f9eeca106725	4876	#define I2C_CR1_PE 0x00000001U /!< Peripheral enable /
Kojto	122:f9eeca106725	4877	#define I2C_CR1_TXIE 0x00000002U /!< TX interrupt enable /
Kojto	122:f9eeca106725	4878	#define I2C_CR1_RXIE 0x00000004U /!< RX interrupt enable /
Kojto	122:f9eeca106725	4879	#define I2C_CR1_ADDRIE 0x00000008U /!< Address match interrupt enable /
Kojto	122:f9eeca106725	4880	#define I2C_CR1_NACKIE 0x00000010U /!< NACK received interrupt enable /
Kojto	122:f9eeca106725	4881	#define I2C_CR1_STOPIE 0x00000020U /!< STOP detection interrupt enable /
Kojto	122:f9eeca106725	4882	#define I2C_CR1_TCIE 0x00000040U /!< Transfer complete interrupt enable /
Kojto	122:f9eeca106725	4883	#define I2C_CR1_ERRIE 0x00000080U /!< Errors interrupt enable /
Kojto	122:f9eeca106725	4884	#define I2C_CR1_DNF 0x00000F00U /!< Digital noise filter /
Kojto	122:f9eeca106725	4885	#define I2C_CR1_ANFOFF 0x00001000U /!< Analog noise filter OFF /
Kojto	122:f9eeca106725	4886	#define I2C_CR1_TXDMAEN 0x00004000U /!< DMA transmission requests enable /
Kojto	122:f9eeca106725	4887	#define I2C_CR1_RXDMAEN 0x00008000U /!< DMA reception requests enable /
Kojto	122:f9eeca106725	4888	#define I2C_CR1_SBC 0x00010000U /!< Slave byte control /
Kojto	122:f9eeca106725	4889	#define I2C_CR1_NOSTRETCH 0x00020000U /!< Clock stretching disable /
Kojto	122:f9eeca106725	4890	#define I2C_CR1_GCEN 0x00080000U /!< General call enable /
Kojto	122:f9eeca106725	4891	#define I2C_CR1_SMBHEN 0x00100000U /!< SMBus host address enable /
Kojto	122:f9eeca106725	4892	#define I2C_CR1_SMBDEN 0x00200000U /!< SMBus device default address enable /
Kojto	122:f9eeca106725	4893	#define I2C_CR1_ALERTEN 0x00400000U /!< SMBus alert enable /
Kojto	122:f9eeca106725	4894	#define I2C_CR1_PECEN 0x00800000U /!< PEC enable /
Kojto	107:4f6c30876dfa	4895
Kojto	116:c0f6e94411f5	4896	/* Legacy define */
Kojto	116:c0f6e94411f5	4897	#define I2C_CR1_DFN I2C_CR1_DNF /!< Digital noise filter /
Kojto	116:c0f6e94411f5	4898
Kojto	107:4f6c30876dfa	4899	/**************** Bit definition for I2C_CR2 register ******************/
Kojto	122:f9eeca106725	4900	#define I2C_CR2_SADD 0x000003FFU /!< Slave address (master mode) /
Kojto	122:f9eeca106725	4901	#define I2C_CR2_RD_WRN 0x00000400U /!< Transfer direction (master mode) /
Kojto	122:f9eeca106725	4902	#define I2C_CR2_ADD10 0x00000800U /!< 10-bit addressing mode (master mode) /
Kojto	122:f9eeca106725	4903	#define I2C_CR2_HEAD10R 0x00001000U /!< 10-bit address header only read direction (master mode) /
Kojto	122:f9eeca106725	4904	#define I2C_CR2_START 0x00002000U /!< START generation /
Kojto	122:f9eeca106725	4905	#define I2C_CR2_STOP 0x00004000U /!< STOP generation (master mode) /
Kojto	122:f9eeca106725	4906	#define I2C_CR2_NACK 0x00008000U /!< NACK generation (slave mode) /
Kojto	122:f9eeca106725	4907	#define I2C_CR2_NBYTES 0x00FF0000U /!< Number of bytes /
Kojto	122:f9eeca106725	4908	#define I2C_CR2_RELOAD 0x01000000U /!< NBYTES reload mode /
Kojto	122:f9eeca106725	4909	#define I2C_CR2_AUTOEND 0x02000000U /!< Automatic end mode (master mode) /
Kojto	122:f9eeca106725	4910	#define I2C_CR2_PECBYTE 0x04000000U /!< Packet error checking byte /
Kojto	107:4f6c30876dfa	4911
Kojto	107:4f6c30876dfa	4912	/***************** Bit definition for I2C_OAR1 register ****************/
Kojto	122:f9eeca106725	4913	#define I2C_OAR1_OA1 0x000003FFU /!< Interface own address 1 /
Kojto	122:f9eeca106725	4914	#define I2C_OAR1_OA1MODE 0x00000400U /!< Own address 1 10-bit mode /
Kojto	122:f9eeca106725	4915	#define I2C_OAR1_OA1EN 0x00008000U /!< Own address 1 enable /
Kojto	107:4f6c30876dfa	4916
Kojto	107:4f6c30876dfa	4917	/***************** Bit definition for I2C_OAR2 register ****************/
Kojto	122:f9eeca106725	4918	#define I2C_OAR2_OA2 0x000000FEU /!< Interface own address 2 /
Kojto	122:f9eeca106725	4919	#define I2C_OAR2_OA2MSK 0x00000700U /!< Own address 2 masks /
Kojto	122:f9eeca106725	4920	#define I2C_OAR2_OA2NOMASK 0x00000000U /!< No mask /
Kojto	122:f9eeca106725	4921	#define I2C_OAR2_OA2MASK01 0x00000100U /!< OA2[1] is masked, Only OA2[7:2] are compared /
Kojto	122:f9eeca106725	4922	#define I2C_OAR2_OA2MASK02 0x00000200U /!< OA2[2:1] is masked, Only OA2[7:3] are compared /
Kojto	122:f9eeca106725	4923	#define I2C_OAR2_OA2MASK03 0x00000300U /!< OA2[3:1] is masked, Only OA2[7:4] are compared /
Kojto	122:f9eeca106725	4924	#define I2C_OAR2_OA2MASK04 0x00000400U /!< OA2[4:1] is masked, Only OA2[7:5] are compared /
Kojto	122:f9eeca106725	4925	#define I2C_OAR2_OA2MASK05 0x00000500U /!< OA2[5:1] is masked, Only OA2[7:6] are compared /
Kojto	122:f9eeca106725	4926	#define I2C_OAR2_OA2MASK06 0x00000600U /!< OA2[6:1] is masked, Only OA2[7] are compared /
Kojto	122:f9eeca106725	4927	#define I2C_OAR2_OA2MASK07 0x00000700U /!< OA2[7:1] is masked, No comparison is done /
Kojto	122:f9eeca106725	4928	#define I2C_OAR2_OA2EN 0x00008000U /!< Own address 2 enable /
Kojto	107:4f6c30876dfa	4929
Kojto	107:4f6c30876dfa	4930	/***************** Bit definition for I2C_TIMINGR register *****************/
Kojto	122:f9eeca106725	4931	#define I2C_TIMINGR_SCLL 0x000000FFU /!< SCL low period (master mode) /
Kojto	122:f9eeca106725	4932	#define I2C_TIMINGR_SCLH 0x0000FF00U /!< SCL high period (master mode) /
Kojto	122:f9eeca106725	4933	#define I2C_TIMINGR_SDADEL 0x000F0000U /!< Data hold time /
Kojto	122:f9eeca106725	4934	#define I2C_TIMINGR_SCLDEL 0x00F00000U /!< Data setup time /
Kojto	122:f9eeca106725	4935	#define I2C_TIMINGR_PRESC 0xF0000000U /!< Timings prescaler /
Kojto	107:4f6c30876dfa	4936
Kojto	107:4f6c30876dfa	4937	/***************** Bit definition for I2C_TIMEOUTR register *****************/
Kojto	122:f9eeca106725	4938	#define I2C_TIMEOUTR_TIMEOUTA 0x00000FFFU /!< Bus timeout A /
Kojto	122:f9eeca106725	4939	#define I2C_TIMEOUTR_TIDLE 0x00001000U /!< Idle clock timeout detection /
Kojto	122:f9eeca106725	4940	#define I2C_TIMEOUTR_TIMOUTEN 0x00008000U /!< Clock timeout enable /
Kojto	122:f9eeca106725	4941	#define I2C_TIMEOUTR_TIMEOUTB 0x0FFF0000U /!< Bus timeout B /
Kojto	122:f9eeca106725	4942	#define I2C_TIMEOUTR_TEXTEN 0x80000000U /!< Extended clock timeout enable /
Kojto	107:4f6c30876dfa	4943
Kojto	107:4f6c30876dfa	4944	/**************** Bit definition for I2C_ISR register *******************/
Kojto	122:f9eeca106725	4945	#define I2C_ISR_TXE 0x00000001U /!< Transmit data register empty /
Kojto	122:f9eeca106725	4946	#define I2C_ISR_TXIS 0x00000002U /!< Transmit interrupt status /
Kojto	122:f9eeca106725	4947	#define I2C_ISR_RXNE 0x00000004U /!< Receive data register not empty /
Kojto	122:f9eeca106725	4948	#define I2C_ISR_ADDR 0x00000008U /!< Address matched (slave mode) /
Kojto	122:f9eeca106725	4949	#define I2C_ISR_NACKF 0x00000010U /!< NACK received flag /
Kojto	122:f9eeca106725	4950	#define I2C_ISR_STOPF 0x00000020U /!< STOP detection flag /
Kojto	122:f9eeca106725	4951	#define I2C_ISR_TC 0x00000040U /!< Transfer complete (master mode) /
Kojto	122:f9eeca106725	4952	#define I2C_ISR_TCR 0x00000080U /!< Transfer complete reload /
Kojto	122:f9eeca106725	4953	#define I2C_ISR_BERR 0x00000100U /!< Bus error /
Kojto	122:f9eeca106725	4954	#define I2C_ISR_ARLO 0x00000200U /!< Arbitration lost /
Kojto	122:f9eeca106725	4955	#define I2C_ISR_OVR 0x00000400U /!< Overrun/Underrun /
Kojto	122:f9eeca106725	4956	#define I2C_ISR_PECERR 0x00000800U /!< PEC error in reception /
Kojto	122:f9eeca106725	4957	#define I2C_ISR_TIMEOUT 0x00001000U /!< Timeout or Tlow detection flag /
Kojto	122:f9eeca106725	4958	#define I2C_ISR_ALERT 0x00002000U /!< SMBus alert /
Kojto	122:f9eeca106725	4959	#define I2C_ISR_BUSY 0x00008000U /!< Bus busy /
Kojto	122:f9eeca106725	4960	#define I2C_ISR_DIR 0x00010000U /!< Transfer direction (slave mode) /
Kojto	122:f9eeca106725	4961	#define I2C_ISR_ADDCODE 0x00FE0000U /!< Address match code (slave mode) /
Kojto	107:4f6c30876dfa	4962
Kojto	107:4f6c30876dfa	4963	/**************** Bit definition for I2C_ICR register *******************/
Kojto	122:f9eeca106725	4964	#define I2C_ICR_ADDRCF 0x00000008U /!< Address matched clear flag /
Kojto	122:f9eeca106725	4965	#define I2C_ICR_NACKCF 0x00000010U /!< NACK clear flag /
Kojto	122:f9eeca106725	4966	#define I2C_ICR_STOPCF 0x00000020U /!< STOP detection clear flag /
Kojto	122:f9eeca106725	4967	#define I2C_ICR_BERRCF 0x00000100U /!< Bus error clear flag /
Kojto	122:f9eeca106725	4968	#define I2C_ICR_ARLOCF 0x00000200U /!< Arbitration lost clear flag /
Kojto	122:f9eeca106725	4969	#define I2C_ICR_OVRCF 0x00000400U /!< Overrun/Underrun clear flag /
Kojto	122:f9eeca106725	4970	#define I2C_ICR_PECCF 0x00000800U /!< PAC error clear flag /
Kojto	122:f9eeca106725	4971	#define I2C_ICR_TIMOUTCF 0x00001000U /!< Timeout clear flag /
Kojto	122:f9eeca106725	4972	#define I2C_ICR_ALERTCF 0x00002000U /!< Alert clear flag /
Kojto	107:4f6c30876dfa	4973
Kojto	107:4f6c30876dfa	4974	/**************** Bit definition for I2C_PECR register *******************/
Kojto	122:f9eeca106725	4975	#define I2C_PECR_PEC 0x000000FFU /!< PEC register /
Kojto	107:4f6c30876dfa	4976
Kojto	107:4f6c30876dfa	4977	/**************** Bit definition for I2C_RXDR register *******************/
Kojto	122:f9eeca106725	4978	#define I2C_RXDR_RXDATA 0x000000FFU /!< 8-bit receive data /
Kojto	107:4f6c30876dfa	4979
Kojto	107:4f6c30876dfa	4980	/**************** Bit definition for I2C_TXDR register *******************/
Kojto	122:f9eeca106725	4981	#define I2C_TXDR_TXDATA 0x000000FFU /!< 8-bit transmit data /
Kojto	107:4f6c30876dfa	4982
Kojto	107:4f6c30876dfa	4983
Kojto	107:4f6c30876dfa	4984	/******************************************************************************/
Kojto	107:4f6c30876dfa	4985	/* */
Kojto	107:4f6c30876dfa	4986	/* Independent WATCHDOG */
Kojto	107:4f6c30876dfa	4987	/* */
Kojto	107:4f6c30876dfa	4988	/******************************************************************************/
Kojto	107:4f6c30876dfa	4989	/***************** Bit definition for IWDG_KR register ******************/
Kojto	122:f9eeca106725	4990	#define IWDG_KR_KEY 0xFFFFU /!<Key value (write only, read 0000h) /
Kojto	107:4f6c30876dfa	4991
Kojto	107:4f6c30876dfa	4992	/***************** Bit definition for IWDG_PR register ******************/
Kojto	122:f9eeca106725	4993	#define IWDG_PR_PR 0x07U /!<PR[2:0] (Prescaler divider) /
Kojto	122:f9eeca106725	4994	#define IWDG_PR_PR_0 0x01U /!<Bit 0 /
Kojto	122:f9eeca106725	4995	#define IWDG_PR_PR_1 0x02U /!<Bit 1 /
Kojto	122:f9eeca106725	4996	#define IWDG_PR_PR_2 0x04U /!<Bit 2 /
Kojto	107:4f6c30876dfa	4997
Kojto	107:4f6c30876dfa	4998	/***************** Bit definition for IWDG_RLR register *****************/
Kojto	122:f9eeca106725	4999	#define IWDG_RLR_RL 0x0FFFU /!<Watchdog counter reload value /
Kojto	107:4f6c30876dfa	5000
Kojto	107:4f6c30876dfa	5001	/***************** Bit definition for IWDG_SR register ******************/
Kojto	122:f9eeca106725	5002	#define IWDG_SR_PVU 0x01U /!< Watchdog prescaler value update /
Kojto	122:f9eeca106725	5003	#define IWDG_SR_RVU 0x02U /!< Watchdog counter reload value update /
Kojto	122:f9eeca106725	5004	#define IWDG_SR_WVU 0x04U /!< Watchdog counter window value update /
Kojto	107:4f6c30876dfa	5005
Kojto	107:4f6c30876dfa	5006	/***************** Bit definition for IWDG_KR register ******************/
Kojto	122:f9eeca106725	5007	#define IWDG_WINR_WIN 0x0FFFU /!< Watchdog counter window value /
Kojto	107:4f6c30876dfa	5008
Kojto	107:4f6c30876dfa	5009	/******************************************************************************/
Kojto	107:4f6c30876dfa	5010	/* */
Kojto	107:4f6c30876dfa	5011	/* LCD-TFT Display Controller (LTDC) */
Kojto	107:4f6c30876dfa	5012	/* */
Kojto	107:4f6c30876dfa	5013	/******************************************************************************/
Kojto	107:4f6c30876dfa	5014
Kojto	107:4f6c30876dfa	5015	/****************** Bit definition for LTDC_SSCR register ***************/
Kojto	107:4f6c30876dfa	5016
Kojto	122:f9eeca106725	5017	#define LTDC_SSCR_VSH 0x000007FFU /!< Vertical Synchronization Height /
Kojto	122:f9eeca106725	5018	#define LTDC_SSCR_HSW 0x0FFF0000U /!< Horizontal Synchronization Width /
Kojto	107:4f6c30876dfa	5019
Kojto	107:4f6c30876dfa	5020	/****************** Bit definition for LTDC_BPCR register ***************/
Kojto	107:4f6c30876dfa	5021
Kojto	122:f9eeca106725	5022	#define LTDC_BPCR_AVBP 0x000007FFU /!< Accumulated Vertical Back Porch /
Kojto	122:f9eeca106725	5023	#define LTDC_BPCR_AHBP 0x0FFF0000U /!< Accumulated Horizontal Back Porch /
Kojto	107:4f6c30876dfa	5024
Kojto	107:4f6c30876dfa	5025	/****************** Bit definition for LTDC_AWCR register ***************/
Kojto	107:4f6c30876dfa	5026
Kojto	122:f9eeca106725	5027	#define LTDC_AWCR_AAH 0x000007FFU /!< Accumulated Active heigh /
Kojto	122:f9eeca106725	5028	#define LTDC_AWCR_AAW 0x0FFF0000U /!< Accumulated Active Width /
Kojto	107:4f6c30876dfa	5029
Kojto	107:4f6c30876dfa	5030	/****************** Bit definition for LTDC_TWCR register ***************/
Kojto	107:4f6c30876dfa	5031
Kojto	122:f9eeca106725	5032	#define LTDC_TWCR_TOTALH 0x000007FFU /!< Total Heigh /
Kojto	122:f9eeca106725	5033	#define LTDC_TWCR_TOTALW 0x0FFF0000U /!< Total Width /
Kojto	107:4f6c30876dfa	5034
Kojto	107:4f6c30876dfa	5035	/****************** Bit definition for LTDC_GCR register ****************/
Kojto	107:4f6c30876dfa	5036
Kojto	122:f9eeca106725	5037	#define LTDC_GCR_LTDCEN 0x00000001U /!< LCD-TFT controller enable bit /
Kojto	122:f9eeca106725	5038	#define LTDC_GCR_DBW 0x00000070U /!< Dither Blue Width /
Kojto	122:f9eeca106725	5039	#define LTDC_GCR_DGW 0x00000700U /!< Dither Green Width /
Kojto	122:f9eeca106725	5040	#define LTDC_GCR_DRW 0x00007000U /!< Dither Red Width /
Kojto	122:f9eeca106725	5041	#define LTDC_GCR_DEN 0x00010000U /!< Dither Enable /
Kojto	122:f9eeca106725	5042	#define LTDC_GCR_PCPOL 0x10000000U /!< Pixel Clock Polarity /
Kojto	122:f9eeca106725	5043	#define LTDC_GCR_DEPOL 0x20000000U /!< Data Enable Polarity /
Kojto	122:f9eeca106725	5044	#define LTDC_GCR_VSPOL 0x40000000U /!< Vertical Synchronization Polarity /
Kojto	122:f9eeca106725	5045	#define LTDC_GCR_HSPOL 0x80000000U /!< Horizontal Synchronization Polarity /
Kojto	122:f9eeca106725	5046
Kojto	122:f9eeca106725	5047	/* Legacy define */
Kojto	122:f9eeca106725	5048	#define LTDC_GCR_DTEN LTDC_GCR_DEN
Kojto	107:4f6c30876dfa	5049
Kojto	107:4f6c30876dfa	5050	/****************** Bit definition for LTDC_SRCR register ***************/
Kojto	107:4f6c30876dfa	5051
Kojto	122:f9eeca106725	5052	#define LTDC_SRCR_IMR 0x00000001U /!< Immediate Reload /
Kojto	122:f9eeca106725	5053	#define LTDC_SRCR_VBR 0x00000002U /!< Vertical Blanking Reload /
Kojto	107:4f6c30876dfa	5054
Kojto	107:4f6c30876dfa	5055	/****************** Bit definition for LTDC_BCCR register ***************/
Kojto	107:4f6c30876dfa	5056
Kojto	122:f9eeca106725	5057	#define LTDC_BCCR_BCBLUE 0x000000FFU /!< Background Blue value /
Kojto	122:f9eeca106725	5058	#define LTDC_BCCR_BCGREEN 0x0000FF00U /!< Background Green value /
Kojto	122:f9eeca106725	5059	#define LTDC_BCCR_BCRED 0x00FF0000U /!< Background Red value /
Kojto	107:4f6c30876dfa	5060
Kojto	107:4f6c30876dfa	5061	/****************** Bit definition for LTDC_IER register ****************/
Kojto	107:4f6c30876dfa	5062
Kojto	122:f9eeca106725	5063	#define LTDC_IER_LIE 0x00000001U /!< Line Interrupt Enable /
Kojto	122:f9eeca106725	5064	#define LTDC_IER_FUIE 0x00000002U /!< FIFO Underrun Interrupt Enable /
Kojto	122:f9eeca106725	5065	#define LTDC_IER_TERRIE 0x00000004U /!< Transfer Error Interrupt Enable /
Kojto	122:f9eeca106725	5066	#define LTDC_IER_RRIE 0x00000008U /!< Register Reload interrupt enable /
Kojto	107:4f6c30876dfa	5067
Kojto	107:4f6c30876dfa	5068	/****************** Bit definition for LTDC_ISR register ****************/
Kojto	107:4f6c30876dfa	5069
Kojto	122:f9eeca106725	5070	#define LTDC_ISR_LIF 0x00000001U /!< Line Interrupt Flag /
Kojto	122:f9eeca106725	5071	#define LTDC_ISR_FUIF 0x00000002U /!< FIFO Underrun Interrupt Flag /
Kojto	122:f9eeca106725	5072	#define LTDC_ISR_TERRIF 0x00000004U /!< Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	5073	#define LTDC_ISR_RRIF 0x00000008U /!< Register Reload interrupt Flag /
Kojto	107:4f6c30876dfa	5074
Kojto	107:4f6c30876dfa	5075	/****************** Bit definition for LTDC_ICR register ****************/
Kojto	107:4f6c30876dfa	5076
Kojto	122:f9eeca106725	5077	#define LTDC_ICR_CLIF 0x00000001U /!< Clears the Line Interrupt Flag /
Kojto	122:f9eeca106725	5078	#define LTDC_ICR_CFUIF 0x00000002U /!< Clears the FIFO Underrun Interrupt Flag /
Kojto	122:f9eeca106725	5079	#define LTDC_ICR_CTERRIF 0x00000004U /!< Clears the Transfer Error Interrupt Flag /
Kojto	122:f9eeca106725	5080	#define LTDC_ICR_CRRIF 0x00000008U /!< Clears Register Reload interrupt Flag /
Kojto	107:4f6c30876dfa	5081
Kojto	107:4f6c30876dfa	5082	/****************** Bit definition for LTDC_LIPCR register **************/
Kojto	107:4f6c30876dfa	5083
Kojto	122:f9eeca106725	5084	#define LTDC_LIPCR_LIPOS 0x000007FFU /!< Line Interrupt Position /
Kojto	107:4f6c30876dfa	5085
Kojto	107:4f6c30876dfa	5086	/****************** Bit definition for LTDC_CPSR register ***************/
Kojto	107:4f6c30876dfa	5087
Kojto	122:f9eeca106725	5088	#define LTDC_CPSR_CYPOS 0x0000FFFFU /!< Current Y Position /
Kojto	122:f9eeca106725	5089	#define LTDC_CPSR_CXPOS 0xFFFF0000U /!< Current X Position /
Kojto	107:4f6c30876dfa	5090
Kojto	107:4f6c30876dfa	5091	/****************** Bit definition for LTDC_CDSR register ***************/
Kojto	107:4f6c30876dfa	5092
Kojto	122:f9eeca106725	5093	#define LTDC_CDSR_VDES 0x00000001U /!< Vertical Data Enable Status /
Kojto	122:f9eeca106725	5094	#define LTDC_CDSR_HDES 0x00000002U /!< Horizontal Data Enable Status /
Kojto	122:f9eeca106725	5095	#define LTDC_CDSR_VSYNCS 0x00000004U /!< Vertical Synchronization Status /
Kojto	122:f9eeca106725	5096	#define LTDC_CDSR_HSYNCS 0x00000008U /!< Horizontal Synchronization Status /
Kojto	107:4f6c30876dfa	5097
Kojto	107:4f6c30876dfa	5098	/****************** Bit definition for LTDC_LxCR register ***************/
Kojto	107:4f6c30876dfa	5099
Kojto	122:f9eeca106725	5100	#define LTDC_LxCR_LEN 0x00000001U /!< Layer Enable /
Kojto	122:f9eeca106725	5101	#define LTDC_LxCR_COLKEN 0x00000002U /!< Color Keying Enable /
Kojto	122:f9eeca106725	5102	#define LTDC_LxCR_CLUTEN 0x00000010U /!< Color Lockup Table Enable /
Kojto	107:4f6c30876dfa	5103
Kojto	107:4f6c30876dfa	5104	/****************** Bit definition for LTDC_LxWHPCR register ************/
Kojto	107:4f6c30876dfa	5105
Kojto	122:f9eeca106725	5106	#define LTDC_LxWHPCR_WHSTPOS 0x00000FFFU /!< Window Horizontal Start Position /
Kojto	122:f9eeca106725	5107	#define LTDC_LxWHPCR_WHSPPOS 0xFFFF0000U /!< Window Horizontal Stop Position /
Kojto	107:4f6c30876dfa	5108
Kojto	107:4f6c30876dfa	5109	/****************** Bit definition for LTDC_LxWVPCR register ************/
Kojto	107:4f6c30876dfa	5110
Kojto	122:f9eeca106725	5111	#define LTDC_LxWVPCR_WVSTPOS 0x00000FFFU /!< Window Vertical Start Position /
Kojto	122:f9eeca106725	5112	#define LTDC_LxWVPCR_WVSPPOS 0xFFFF0000U /!< Window Vertical Stop Position /
Kojto	107:4f6c30876dfa	5113
Kojto	107:4f6c30876dfa	5114	/****************** Bit definition for LTDC_LxCKCR register *************/
Kojto	107:4f6c30876dfa	5115
Kojto	122:f9eeca106725	5116	#define LTDC_LxCKCR_CKBLUE 0x000000FFU /!< Color Key Blue value /
Kojto	122:f9eeca106725	5117	#define LTDC_LxCKCR_CKGREEN 0x0000FF00U /!< Color Key Green value /
Kojto	122:f9eeca106725	5118	#define LTDC_LxCKCR_CKRED 0x00FF0000U /!< Color Key Red value /
Kojto	107:4f6c30876dfa	5119
Kojto	107:4f6c30876dfa	5120	/****************** Bit definition for LTDC_LxPFCR register *************/
Kojto	107:4f6c30876dfa	5121
Kojto	122:f9eeca106725	5122	#define LTDC_LxPFCR_PF 0x00000007U /!< Pixel Format /
Kojto	107:4f6c30876dfa	5123
Kojto	107:4f6c30876dfa	5124	/****************** Bit definition for LTDC_LxCACR register *************/
Kojto	107:4f6c30876dfa	5125
Kojto	122:f9eeca106725	5126	#define LTDC_LxCACR_CONSTA 0x000000FFU /!< Constant Alpha /
Kojto	107:4f6c30876dfa	5127
Kojto	107:4f6c30876dfa	5128	/****************** Bit definition for LTDC_LxDCCR register *************/
Kojto	107:4f6c30876dfa	5129
Kojto	122:f9eeca106725	5130	#define LTDC_LxDCCR_DCBLUE 0x000000FFU /!< Default Color Blue /
Kojto	122:f9eeca106725	5131	#define LTDC_LxDCCR_DCGREEN 0x0000FF00U /!< Default Color Green /
Kojto	122:f9eeca106725	5132	#define LTDC_LxDCCR_DCRED 0x00FF0000U /!< Default Color Red /
Kojto	122:f9eeca106725	5133	#define LTDC_LxDCCR_DCALPHA 0xFF000000U /!< Default Color Alpha /
Kojto	107:4f6c30876dfa	5134
Kojto	107:4f6c30876dfa	5135	/****************** Bit definition for LTDC_LxBFCR register *************/
Kojto	107:4f6c30876dfa	5136
Kojto	122:f9eeca106725	5137	#define LTDC_LxBFCR_BF2 0x00000007U /!< Blending Factor 2 /
Kojto	122:f9eeca106725	5138	#define LTDC_LxBFCR_BF1 0x00000700U /!< Blending Factor 1 /
Kojto	107:4f6c30876dfa	5139
Kojto	107:4f6c30876dfa	5140	/****************** Bit definition for LTDC_LxCFBAR register ************/
Kojto	107:4f6c30876dfa	5141
Kojto	122:f9eeca106725	5142	#define LTDC_LxCFBAR_CFBADD 0xFFFFFFFFU /!< Color Frame Buffer Start Address /
Kojto	107:4f6c30876dfa	5143
Kojto	107:4f6c30876dfa	5144	/****************** Bit definition for LTDC_LxCFBLR register ************/
Kojto	107:4f6c30876dfa	5145
Kojto	122:f9eeca106725	5146	#define LTDC_LxCFBLR_CFBLL 0x00001FFFU /!< Color Frame Buffer Line Length /
Kojto	122:f9eeca106725	5147	#define LTDC_LxCFBLR_CFBP 0x1FFF0000U /!< Color Frame Buffer Pitch in bytes /
Kojto	107:4f6c30876dfa	5148
Kojto	107:4f6c30876dfa	5149	/****************** Bit definition for LTDC_LxCFBLNR register ***********/
Kojto	107:4f6c30876dfa	5150
Kojto	122:f9eeca106725	5151	#define LTDC_LxCFBLNR_CFBLNBR 0x000007FFU /!< Frame Buffer Line Number /
Kojto	107:4f6c30876dfa	5152
Kojto	107:4f6c30876dfa	5153	/****************** Bit definition for LTDC_LxCLUTWR register ***********/
Kojto	107:4f6c30876dfa	5154
Kojto	122:f9eeca106725	5155	#define LTDC_LxCLUTWR_BLUE 0x000000FFU /!< Blue value /
Kojto	122:f9eeca106725	5156	#define LTDC_LxCLUTWR_GREEN 0x0000FF00U /!< Green value /
Kojto	122:f9eeca106725	5157	#define LTDC_LxCLUTWR_RED 0x00FF0000U /!< Red value /
Kojto	122:f9eeca106725	5158	#define LTDC_LxCLUTWR_CLUTADD 0xFF000000U /!< CLUT address /
Kojto	107:4f6c30876dfa	5159
Kojto	107:4f6c30876dfa	5160	/******************************************************************************/
Kojto	107:4f6c30876dfa	5161	/* */
Kojto	107:4f6c30876dfa	5162	/* Power Control */
Kojto	107:4f6c30876dfa	5163	/* */
Kojto	107:4f6c30876dfa	5164	/******************************************************************************/
Kojto	107:4f6c30876dfa	5165	/****************** Bit definition for PWR_CR1 register ******************/
Kojto	122:f9eeca106725	5166	#define PWR_CR1_LPDS 0x00000001U /!< Low-Power Deepsleep /
Kojto	122:f9eeca106725	5167	#define PWR_CR1_PDDS 0x00000002U /!< Power Down Deepsleep /
Kojto	122:f9eeca106725	5168	#define PWR_CR1_CSBF 0x00000008U /!< Clear Standby Flag /
Kojto	122:f9eeca106725	5169	#define PWR_CR1_PVDE 0x00000010U /!< Power Voltage Detector Enable /
Kojto	122:f9eeca106725	5170	#define PWR_CR1_PLS 0x000000E0U /!< PLS[2:0] bits (PVD Level Selection) /
Kojto	122:f9eeca106725	5171	#define PWR_CR1_PLS_0 0x00000020U /!< Bit 0 /
Kojto	122:f9eeca106725	5172	#define PWR_CR1_PLS_1 0x00000040U /!< Bit 1 /
Kojto	122:f9eeca106725	5173	#define PWR_CR1_PLS_2 0x00000080U /!< Bit 2 /
Kojto	107:4f6c30876dfa	5174
Kojto	107:4f6c30876dfa	5175	/!< PVD level configuration /
Kojto	122:f9eeca106725	5176	#define PWR_CR1_PLS_LEV0 0x00000000U /!< PVD level 0 /
Kojto	122:f9eeca106725	5177	#define PWR_CR1_PLS_LEV1 0x00000020U /!< PVD level 1 /
Kojto	122:f9eeca106725	5178	#define PWR_CR1_PLS_LEV2 0x00000040U /!< PVD level 2 /
Kojto	122:f9eeca106725	5179	#define PWR_CR1_PLS_LEV3 0x00000060U /!< PVD level 3 /
Kojto	122:f9eeca106725	5180	#define PWR_CR1_PLS_LEV4 0x00000080U /!< PVD level 4 /
Kojto	122:f9eeca106725	5181	#define PWR_CR1_PLS_LEV5 0x000000A0U /!< PVD level 5 /
Kojto	122:f9eeca106725	5182	#define PWR_CR1_PLS_LEV6 0x000000C0U /!< PVD level 6 /
Kojto	122:f9eeca106725	5183	#define PWR_CR1_PLS_LEV7 0x000000E0U /!< PVD level 7 /
Kojto	122:f9eeca106725	5184	#define PWR_CR1_DBP 0x00000100U /!< Disable Backup Domain write protection /
Kojto	122:f9eeca106725	5185	#define PWR_CR1_FPDS 0x00000200U /!< Flash power down in Stop mode /
Kojto	122:f9eeca106725	5186	#define PWR_CR1_LPUDS 0x00000400U /!< Low-power regulator in deepsleep under-drive mode /
Kojto	122:f9eeca106725	5187	#define PWR_CR1_MRUDS 0x00000800U /!< Main regulator in deepsleep under-drive mode /
Kojto	122:f9eeca106725	5188	#define PWR_CR1_ADCDC1 0x00002000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	5189	#define PWR_CR1_VOS 0x0000C000U /!< VOS[1:0] bits (Regulator voltage scaling output selection) /
Kojto	122:f9eeca106725	5190	#define PWR_CR1_VOS_0 0x00004000U /!< Bit 0 /
Kojto	122:f9eeca106725	5191	#define PWR_CR1_VOS_1 0x00008000U /!< Bit 1 /
Kojto	122:f9eeca106725	5192	#define PWR_CR1_ODEN 0x00010000U /!< Over Drive enable /
Kojto	122:f9eeca106725	5193	#define PWR_CR1_ODSWEN 0x00020000U /!< Over Drive switch enabled /
Kojto	122:f9eeca106725	5194	#define PWR_CR1_UDEN 0x000C0000U /!< Under Drive enable in stop mode /
Kojto	122:f9eeca106725	5195	#define PWR_CR1_UDEN_0 0x00040000U /!< Bit 0 /
Kojto	122:f9eeca106725	5196	#define PWR_CR1_UDEN_1 0x00080000U /!< Bit 1 /
Kojto	107:4f6c30876dfa	5197
Kojto	107:4f6c30876dfa	5198	/***************** Bit definition for PWR_CSR1 register ******************/
Kojto	122:f9eeca106725	5199	#define PWR_CSR1_WUIF 0x00000001U /!< Wake up internal Flag /
Kojto	122:f9eeca106725	5200	#define PWR_CSR1_SBF 0x00000002U /!< Standby Flag /
Kojto	122:f9eeca106725	5201	#define PWR_CSR1_PVDO 0x00000004U /!< PVD Output /
Kojto	122:f9eeca106725	5202	#define PWR_CSR1_BRR 0x00000008U /!< Backup regulator ready /
Kojto	122:f9eeca106725	5203	#define PWR_CSR1_EIWUP 0x00000100U /!< Enable internal wakeup /
Kojto	122:f9eeca106725	5204	#define PWR_CSR1_BRE 0x00000200U /!< Backup regulator enable /
Kojto	122:f9eeca106725	5205	#define PWR_CSR1_VOSRDY 0x00004000U /!< Regulator voltage scaling output selection ready /
Kojto	122:f9eeca106725	5206	#define PWR_CSR1_ODRDY 0x00010000U /!< Over Drive generator ready /
Kojto	122:f9eeca106725	5207	#define PWR_CSR1_ODSWRDY 0x00020000U /!< Over Drive Switch ready /
Kojto	122:f9eeca106725	5208	#define PWR_CSR1_UDRDY 0x000C0000U /!< Under Drive ready /
Kojto	122:f9eeca106725	5209
Kojto	122:f9eeca106725	5210	/* Legacy define */
Kojto	122:f9eeca106725	5211	#define PWR_CSR1_UDSWRDY PWR_CSR1_UDRDY
Kojto	107:4f6c30876dfa	5212
Kojto	107:4f6c30876dfa	5213	/****************** Bit definition for PWR_CR2 register ******************/
Kojto	122:f9eeca106725	5214	#define PWR_CR2_CWUPF1 0x00000001U /!< Clear Wakeup Pin Flag for PA0 /
Kojto	122:f9eeca106725	5215	#define PWR_CR2_CWUPF2 0x00000002U /!< Clear Wakeup Pin Flag for PA2 /
Kojto	122:f9eeca106725	5216	#define PWR_CR2_CWUPF3 0x00000004U /!< Clear Wakeup Pin Flag for PC1 /
Kojto	122:f9eeca106725	5217	#define PWR_CR2_CWUPF4 0x00000008U /!< Clear Wakeup Pin Flag for PC13 /
Kojto	122:f9eeca106725	5218	#define PWR_CR2_CWUPF5 0x00000010U /!< Clear Wakeup Pin Flag for PI8 /
Kojto	122:f9eeca106725	5219	#define PWR_CR2_CWUPF6 0x00000020U /!< Clear Wakeup Pin Flag for PI11 /
Kojto	122:f9eeca106725	5220	#define PWR_CR2_WUPP1 0x00000100U /!< Wakeup Pin Polarity bit for PA0 /
Kojto	122:f9eeca106725	5221	#define PWR_CR2_WUPP2 0x00000200U /!< Wakeup Pin Polarity bit for PA2 /
Kojto	122:f9eeca106725	5222	#define PWR_CR2_WUPP3 0x00000400U /!< Wakeup Pin Polarity bit for PC1 /
Kojto	122:f9eeca106725	5223	#define PWR_CR2_WUPP4 0x00000800U /!< Wakeup Pin Polarity bit for PC13 /
Kojto	122:f9eeca106725	5224	#define PWR_CR2_WUPP5 0x00001000U /!< Wakeup Pin Polarity bit for PI8 /
Kojto	122:f9eeca106725	5225	#define PWR_CR2_WUPP6 0x00002000U /!< Wakeup Pin Polarity bit for PI11 /
Kojto	107:4f6c30876dfa	5226
Kojto	107:4f6c30876dfa	5227	/***************** Bit definition for PWR_CSR2 register ******************/
Kojto	122:f9eeca106725	5228	#define PWR_CSR2_WUPF1 0x00000001U /!< Wakeup Pin Flag for PA0 /
Kojto	122:f9eeca106725	5229	#define PWR_CSR2_WUPF2 0x00000002U /!< Wakeup Pin Flag for PA2 /
Kojto	122:f9eeca106725	5230	#define PWR_CSR2_WUPF3 0x00000004U /!< Wakeup Pin Flag for PC1 /
Kojto	122:f9eeca106725	5231	#define PWR_CSR2_WUPF4 0x00000008U /!< Wakeup Pin Flag for PC13 /
Kojto	122:f9eeca106725	5232	#define PWR_CSR2_WUPF5 0x00000010U /!< Wakeup Pin Flag for PI8 /
Kojto	122:f9eeca106725	5233	#define PWR_CSR2_WUPF6 0x00000020U /!< Wakeup Pin Flag for PI11 /
Kojto	122:f9eeca106725	5234	#define PWR_CSR2_EWUP1 0x00000100U /!< Enable Wakeup Pin PA0 /
Kojto	122:f9eeca106725	5235	#define PWR_CSR2_EWUP2 0x00000200U /!< Enable Wakeup Pin PA2 /
Kojto	122:f9eeca106725	5236	#define PWR_CSR2_EWUP3 0x00000400U /!< Enable Wakeup Pin PC1 /
Kojto	122:f9eeca106725	5237	#define PWR_CSR2_EWUP4 0x00000800U /!< Enable Wakeup Pin PC13 /
Kojto	122:f9eeca106725	5238	#define PWR_CSR2_EWUP5 0x00001000U /!< Enable Wakeup Pin PI8 /
Kojto	122:f9eeca106725	5239	#define PWR_CSR2_EWUP6 0x00002000U /!< Enable Wakeup Pin PI11 /
Kojto	107:4f6c30876dfa	5240
Kojto	107:4f6c30876dfa	5241	/******************************************************************************/
Kojto	107:4f6c30876dfa	5242	/* */
Kojto	107:4f6c30876dfa	5243	/* QUADSPI */
Kojto	107:4f6c30876dfa	5244	/* */
Kojto	107:4f6c30876dfa	5245	/******************************************************************************/
Kojto	122:f9eeca106725	5246	/* QUADSPI IP version */
Kojto	122:f9eeca106725	5247	#define QSPI1_V1_0
Kojto	107:4f6c30876dfa	5248	/*************** Bit definition for QUADSPI_CR register *****************/
Kojto	122:f9eeca106725	5249	#define QUADSPI_CR_EN 0x00000001U /!< Enable /
Kojto	122:f9eeca106725	5250	#define QUADSPI_CR_ABORT 0x00000002U /!< Abort request /
Kojto	122:f9eeca106725	5251	#define QUADSPI_CR_DMAEN 0x00000004U /!< DMA Enable /
Kojto	122:f9eeca106725	5252	#define QUADSPI_CR_TCEN 0x00000008U /!< Timeout Counter Enable /
Kojto	122:f9eeca106725	5253	#define QUADSPI_CR_SSHIFT 0x00000010U /!< Sample Shift /
Kojto	122:f9eeca106725	5254	#define QUADSPI_CR_DFM 0x00000040U /!< Dual Flash Mode /
Kojto	122:f9eeca106725	5255	#define QUADSPI_CR_FSEL 0x00000080U /!< Flash Select /
Kojto	122:f9eeca106725	5256	#define QUADSPI_CR_FTHRES 0x00001F00U /!< FTHRES[4:0] FIFO Level /
Kojto	122:f9eeca106725	5257	#define QUADSPI_CR_FTHRES_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	5258	#define QUADSPI_CR_FTHRES_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	5259	#define QUADSPI_CR_FTHRES_2 0x00000400U /!< Bit 2 /
Kojto	122:f9eeca106725	5260	#define QUADSPI_CR_FTHRES_3 0x00000800U /!< Bit 3 /
Kojto	122:f9eeca106725	5261	#define QUADSPI_CR_FTHRES_4 0x00001000U /!< Bit 4 /
Kojto	122:f9eeca106725	5262	#define QUADSPI_CR_TEIE 0x00010000U /!< Transfer Error Interrupt Enable /
Kojto	122:f9eeca106725	5263	#define QUADSPI_CR_TCIE 0x00020000U /!< Transfer Complete Interrupt Enable /
Kojto	122:f9eeca106725	5264	#define QUADSPI_CR_FTIE 0x00040000U /!< FIFO Threshold Interrupt Enable /
Kojto	122:f9eeca106725	5265	#define QUADSPI_CR_SMIE 0x00080000U /!< Status Match Interrupt Enable /
Kojto	122:f9eeca106725	5266	#define QUADSPI_CR_TOIE 0x00100000U /!< TimeOut Interrupt Enable /
Kojto	122:f9eeca106725	5267	#define QUADSPI_CR_APMS 0x00400000U /!< Bit 1 /
Kojto	122:f9eeca106725	5268	#define QUADSPI_CR_PMM 0x00800000U /!< Polling Match Mode /
Kojto	122:f9eeca106725	5269	#define QUADSPI_CR_PRESCALER 0xFF000000U /!< PRESCALER[7:0] Clock prescaler /
Kojto	122:f9eeca106725	5270	#define QUADSPI_CR_PRESCALER_0 0x01000000U /!< Bit 0 /
Kojto	122:f9eeca106725	5271	#define QUADSPI_CR_PRESCALER_1 0x02000000U /!< Bit 1 /
Kojto	122:f9eeca106725	5272	#define QUADSPI_CR_PRESCALER_2 0x04000000U /!< Bit 2 /
Kojto	122:f9eeca106725	5273	#define QUADSPI_CR_PRESCALER_3 0x08000000U /!< Bit 3 /
Kojto	122:f9eeca106725	5274	#define QUADSPI_CR_PRESCALER_4 0x10000000U /!< Bit 4 /
Kojto	122:f9eeca106725	5275	#define QUADSPI_CR_PRESCALER_5 0x20000000U /!< Bit 5 /
Kojto	122:f9eeca106725	5276	#define QUADSPI_CR_PRESCALER_6 0x40000000U /!< Bit 6 /
Kojto	122:f9eeca106725	5277	#define QUADSPI_CR_PRESCALER_7 0x80000000U /!< Bit 7 /
Kojto	107:4f6c30876dfa	5278
Kojto	107:4f6c30876dfa	5279	/*************** Bit definition for QUADSPI_DCR register ****************/
Kojto	122:f9eeca106725	5280	#define QUADSPI_DCR_CKMODE 0x00000001U /!< Mode 0 / Mode 3 /
Kojto	122:f9eeca106725	5281	#define QUADSPI_DCR_CSHT 0x00000700U /!< CSHT[2:0]: ChipSelect High Time /
Kojto	122:f9eeca106725	5282	#define QUADSPI_DCR_CSHT_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	5283	#define QUADSPI_DCR_CSHT_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	5284	#define QUADSPI_DCR_CSHT_2 0x00000400U /!< Bit 2 /
Kojto	122:f9eeca106725	5285	#define QUADSPI_DCR_FSIZE 0x001F0000U /!< FSIZE[4:0]: Flash Size /
Kojto	122:f9eeca106725	5286	#define QUADSPI_DCR_FSIZE_0 0x00010000U /!< Bit 0 /
Kojto	122:f9eeca106725	5287	#define QUADSPI_DCR_FSIZE_1 0x00020000U /!< Bit 1 /
Kojto	122:f9eeca106725	5288	#define QUADSPI_DCR_FSIZE_2 0x00040000U /!< Bit 2 /
Kojto	122:f9eeca106725	5289	#define QUADSPI_DCR_FSIZE_3 0x00080000U /!< Bit 3 /
Kojto	122:f9eeca106725	5290	#define QUADSPI_DCR_FSIZE_4 0x00100000U /!< Bit 4 /
Kojto	107:4f6c30876dfa	5291
Kojto	107:4f6c30876dfa	5292	/**************** Bit definition for QUADSPI_SR register *****************/
Kojto	122:f9eeca106725	5293	#define QUADSPI_SR_TEF 0x00000001U /!< Transfer Error Flag /
Kojto	122:f9eeca106725	5294	#define QUADSPI_SR_TCF 0x00000002U /!< Transfer Complete Flag /
Kojto	122:f9eeca106725	5295	#define QUADSPI_SR_FTF 0x00000004U /!< FIFO Threshlod Flag /
Kojto	122:f9eeca106725	5296	#define QUADSPI_SR_SMF 0x00000008U /!< Status Match Flag /
Kojto	122:f9eeca106725	5297	#define QUADSPI_SR_TOF 0x00000010U /!< Timeout Flag /
Kojto	122:f9eeca106725	5298	#define QUADSPI_SR_BUSY 0x00000020U /!< Busy /
Kojto	122:f9eeca106725	5299	#define QUADSPI_SR_FLEVEL 0x00001F00U /!< FIFO Threshlod Flag /
Kojto	122:f9eeca106725	5300	#define QUADSPI_SR_FLEVEL_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	5301	#define QUADSPI_SR_FLEVEL_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	5302	#define QUADSPI_SR_FLEVEL_2 0x00000400U /!< Bit 2 /
Kojto	122:f9eeca106725	5303	#define QUADSPI_SR_FLEVEL_3 0x00000800U /!< Bit 3 /
Kojto	122:f9eeca106725	5304	#define QUADSPI_SR_FLEVEL_4 0x00001000U /!< Bit 4 /
Kojto	107:4f6c30876dfa	5305
Kojto	107:4f6c30876dfa	5306	/**************** Bit definition for QUADSPI_FCR register ****************/
Kojto	122:f9eeca106725	5307	#define QUADSPI_FCR_CTEF 0x00000001U /!< Clear Transfer Error Flag /
Kojto	122:f9eeca106725	5308	#define QUADSPI_FCR_CTCF 0x00000002U /!< Clear Transfer Complete Flag /
Kojto	122:f9eeca106725	5309	#define QUADSPI_FCR_CSMF 0x00000008U /!< Clear Status Match Flag /
Kojto	122:f9eeca106725	5310	#define QUADSPI_FCR_CTOF 0x00000010U /!< Clear Timeout Flag /
Kojto	107:4f6c30876dfa	5311
Kojto	107:4f6c30876dfa	5312	/**************** Bit definition for QUADSPI_DLR register ****************/
Kojto	122:f9eeca106725	5313	#define QUADSPI_DLR_DL 0xFFFFFFFFU /!< DL[31:0]: Data Length /
Kojto	107:4f6c30876dfa	5314
Kojto	107:4f6c30876dfa	5315	/**************** Bit definition for QUADSPI_CCR register ****************/
Kojto	122:f9eeca106725	5316	#define QUADSPI_CCR_INSTRUCTION 0x000000FFU /!< INSTRUCTION[7:0]: Instruction /
Kojto	122:f9eeca106725	5317	#define QUADSPI_CCR_INSTRUCTION_0 0x00000001U /!< Bit 0 /
Kojto	122:f9eeca106725	5318	#define QUADSPI_CCR_INSTRUCTION_1 0x00000002U /!< Bit 1 /
Kojto	122:f9eeca106725	5319	#define QUADSPI_CCR_INSTRUCTION_2 0x00000004U /!< Bit 2 /
Kojto	122:f9eeca106725	5320	#define QUADSPI_CCR_INSTRUCTION_3 0x00000008U /!< Bit 3 /
Kojto	122:f9eeca106725	5321	#define QUADSPI_CCR_INSTRUCTION_4 0x00000010U /!< Bit 4 /
Kojto	122:f9eeca106725	5322	#define QUADSPI_CCR_INSTRUCTION_5 0x00000020U /!< Bit 5 /
Kojto	122:f9eeca106725	5323	#define QUADSPI_CCR_INSTRUCTION_6 0x00000040U /!< Bit 6 /
Kojto	122:f9eeca106725	5324	#define QUADSPI_CCR_INSTRUCTION_7 0x00000080U /!< Bit 7 /
Kojto	122:f9eeca106725	5325	#define QUADSPI_CCR_IMODE 0x00000300U /!< IMODE[1:0]: Instruction Mode /
Kojto	122:f9eeca106725	5326	#define QUADSPI_CCR_IMODE_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	5327	#define QUADSPI_CCR_IMODE_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	5328	#define QUADSPI_CCR_ADMODE 0x00000C00U /!< ADMODE[1:0]: Address Mode /
Kojto	122:f9eeca106725	5329	#define QUADSPI_CCR_ADMODE_0 0x00000400U /!< Bit 0 /
Kojto	122:f9eeca106725	5330	#define QUADSPI_CCR_ADMODE_1 0x00000800U /!< Bit 1 /
Kojto	122:f9eeca106725	5331	#define QUADSPI_CCR_ADSIZE 0x00003000U /!< ADSIZE[1:0]: Address Size /
Kojto	122:f9eeca106725	5332	#define QUADSPI_CCR_ADSIZE_0 0x00001000U /!< Bit 0 /
Kojto	122:f9eeca106725	5333	#define QUADSPI_CCR_ADSIZE_1 0x00002000U /!< Bit 1 /
Kojto	122:f9eeca106725	5334	#define QUADSPI_CCR_ABMODE 0x0000C000U /!< ABMODE[1:0]: Alternate Bytes Mode /
Kojto	122:f9eeca106725	5335	#define QUADSPI_CCR_ABMODE_0 0x00004000U /!< Bit 0 /
Kojto	122:f9eeca106725	5336	#define QUADSPI_CCR_ABMODE_1 0x00008000U /!< Bit 1 /
Kojto	122:f9eeca106725	5337	#define QUADSPI_CCR_ABSIZE 0x00030000U /!< ABSIZE[1:0]: Instruction Mode /
Kojto	122:f9eeca106725	5338	#define QUADSPI_CCR_ABSIZE_0 0x00010000U /!< Bit 0 /
Kojto	122:f9eeca106725	5339	#define QUADSPI_CCR_ABSIZE_1 0x00020000U /!< Bit 1 /
Kojto	122:f9eeca106725	5340	#define QUADSPI_CCR_DCYC 0x007C0000U /!< DCYC[4:0]: Dummy Cycles /
Kojto	122:f9eeca106725	5341	#define QUADSPI_CCR_DCYC_0 0x00040000U /!< Bit 0 /
Kojto	122:f9eeca106725	5342	#define QUADSPI_CCR_DCYC_1 0x00080000U /!< Bit 1 /
Kojto	122:f9eeca106725	5343	#define QUADSPI_CCR_DCYC_2 0x00100000U /!< Bit 2 /
Kojto	122:f9eeca106725	5344	#define QUADSPI_CCR_DCYC_3 0x00200000U /!< Bit 3 /
Kojto	122:f9eeca106725	5345	#define QUADSPI_CCR_DCYC_4 0x00400000U /!< Bit 4 /
Kojto	122:f9eeca106725	5346	#define QUADSPI_CCR_DMODE 0x03000000U /!< DMODE[1:0]: Data Mode /
Kojto	122:f9eeca106725	5347	#define QUADSPI_CCR_DMODE_0 0x01000000U /!< Bit 0 /
Kojto	122:f9eeca106725	5348	#define QUADSPI_CCR_DMODE_1 0x02000000U /!< Bit 1 /
Kojto	122:f9eeca106725	5349	#define QUADSPI_CCR_FMODE 0x0C000000U /!< FMODE[1:0]: Functional Mode /
Kojto	122:f9eeca106725	5350	#define QUADSPI_CCR_FMODE_0 0x04000000U /!< Bit 0 /
Kojto	122:f9eeca106725	5351	#define QUADSPI_CCR_FMODE_1 0x08000000U /!< Bit 1 /
Kojto	122:f9eeca106725	5352	#define QUADSPI_CCR_SIOO 0x10000000U /!< SIOO: Send Instruction Only Once Mode /
Kojto	122:f9eeca106725	5353	#define QUADSPI_CCR_DHHC 0x40000000U /!< DHHC: Delay Half Hclk Cycle /
Kojto	122:f9eeca106725	5354	#define QUADSPI_CCR_DDRM 0x80000000U /!< DDRM: Double Data Rate Mode /
Kojto	107:4f6c30876dfa	5355	/**************** Bit definition for QUADSPI_AR register *****************/
Kojto	122:f9eeca106725	5356	#define QUADSPI_AR_ADDRESS 0xFFFFFFFFU /!< ADDRESS[31:0]: Address /
Kojto	107:4f6c30876dfa	5357
Kojto	107:4f6c30876dfa	5358	/**************** Bit definition for QUADSPI_ABR register ****************/
Kojto	122:f9eeca106725	5359	#define QUADSPI_ABR_ALTERNATE 0xFFFFFFFFU /!< ALTERNATE[31:0]: Alternate Bytes /
Kojto	107:4f6c30876dfa	5360
Kojto	107:4f6c30876dfa	5361	/**************** Bit definition for QUADSPI_DR register *****************/
Kojto	122:f9eeca106725	5362	#define QUADSPI_DR_DATA 0xFFFFFFFFU /!< DATA[31:0]: Data /
Kojto	107:4f6c30876dfa	5363
Kojto	107:4f6c30876dfa	5364	/**************** Bit definition for QUADSPI_PSMKR register **************/
Kojto	122:f9eeca106725	5365	#define QUADSPI_PSMKR_MASK 0xFFFFFFFFU /!< MASK[31:0]: Status Mask /
Kojto	107:4f6c30876dfa	5366
Kojto	107:4f6c30876dfa	5367	/**************** Bit definition for QUADSPI_PSMAR register **************/
Kojto	122:f9eeca106725	5368	#define QUADSPI_PSMAR_MATCH 0xFFFFFFFFU /!< MATCH[31:0]: Status Match /
Kojto	107:4f6c30876dfa	5369
Kojto	107:4f6c30876dfa	5370	/**************** Bit definition for QUADSPI_PIR register ***************/
Kojto	122:f9eeca106725	5371	#define QUADSPI_PIR_INTERVAL 0x0000FFFFU /!< INTERVAL[15:0]: Polling Interval /
Kojto	107:4f6c30876dfa	5372
Kojto	107:4f6c30876dfa	5373	/**************** Bit definition for QUADSPI_LPTR register ***************/
Kojto	122:f9eeca106725	5374	#define QUADSPI_LPTR_TIMEOUT 0x0000FFFFU /!< TIMEOUT[15:0]: Timeout period /
Kojto	107:4f6c30876dfa	5375
Kojto	107:4f6c30876dfa	5376	/******************************************************************************/
Kojto	107:4f6c30876dfa	5377	/* */
Kojto	107:4f6c30876dfa	5378	/* Reset and Clock Control */
Kojto	107:4f6c30876dfa	5379	/* */
Kojto	107:4f6c30876dfa	5380	/******************************************************************************/
Kojto	107:4f6c30876dfa	5381	/****************** Bit definition for RCC_CR register ******************/
Kojto	122:f9eeca106725	5382	#define RCC_CR_HSION 0x00000001U
Kojto	122:f9eeca106725	5383	#define RCC_CR_HSIRDY 0x00000002U
Kojto	122:f9eeca106725	5384	#define RCC_CR_HSITRIM 0x000000F8U
Kojto	122:f9eeca106725	5385	#define RCC_CR_HSITRIM_0 0x00000008U /!<Bit 0 /
Kojto	122:f9eeca106725	5386	#define RCC_CR_HSITRIM_1 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	5387	#define RCC_CR_HSITRIM_2 0x00000020U /!<Bit 2 /
Kojto	122:f9eeca106725	5388	#define RCC_CR_HSITRIM_3 0x00000040U /!<Bit 3 /
Kojto	122:f9eeca106725	5389	#define RCC_CR_HSITRIM_4 0x00000080U /!<Bit 4 /
Kojto	122:f9eeca106725	5390	#define RCC_CR_HSICAL 0x0000FF00U
Kojto	122:f9eeca106725	5391	#define RCC_CR_HSICAL_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	5392	#define RCC_CR_HSICAL_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	5393	#define RCC_CR_HSICAL_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	5394	#define RCC_CR_HSICAL_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	5395	#define RCC_CR_HSICAL_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	5396	#define RCC_CR_HSICAL_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	5397	#define RCC_CR_HSICAL_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	5398	#define RCC_CR_HSICAL_7 0x00008000U /!<Bit 7 /
Kojto	122:f9eeca106725	5399	#define RCC_CR_HSEON 0x00010000U
Kojto	122:f9eeca106725	5400	#define RCC_CR_HSERDY 0x00020000U
Kojto	122:f9eeca106725	5401	#define RCC_CR_HSEBYP 0x00040000U
Kojto	122:f9eeca106725	5402	#define RCC_CR_CSSON 0x00080000U
Kojto	122:f9eeca106725	5403	#define RCC_CR_PLLON 0x01000000U
Kojto	122:f9eeca106725	5404	#define RCC_CR_PLLRDY 0x02000000U
Kojto	122:f9eeca106725	5405	#define RCC_CR_PLLI2SON 0x04000000U
Kojto	122:f9eeca106725	5406	#define RCC_CR_PLLI2SRDY 0x08000000U
Kojto	122:f9eeca106725	5407	#define RCC_CR_PLLSAION 0x10000000U
Kojto	122:f9eeca106725	5408	#define RCC_CR_PLLSAIRDY 0x20000000U
Kojto	107:4f6c30876dfa	5409
Kojto	107:4f6c30876dfa	5410	/****************** Bit definition for RCC_PLLCFGR register *************/
Kojto	122:f9eeca106725	5411	#define RCC_PLLCFGR_PLLM 0x0000003FU
Kojto	122:f9eeca106725	5412	#define RCC_PLLCFGR_PLLM_0 0x00000001U
Kojto	122:f9eeca106725	5413	#define RCC_PLLCFGR_PLLM_1 0x00000002U
Kojto	122:f9eeca106725	5414	#define RCC_PLLCFGR_PLLM_2 0x00000004U
Kojto	122:f9eeca106725	5415	#define RCC_PLLCFGR_PLLM_3 0x00000008U
Kojto	122:f9eeca106725	5416	#define RCC_PLLCFGR_PLLM_4 0x00000010U
Kojto	122:f9eeca106725	5417	#define RCC_PLLCFGR_PLLM_5 0x00000020U
Kojto	122:f9eeca106725	5418	#define RCC_PLLCFGR_PLLN 0x00007FC0U
Kojto	122:f9eeca106725	5419	#define RCC_PLLCFGR_PLLN_0 0x00000040U
Kojto	122:f9eeca106725	5420	#define RCC_PLLCFGR_PLLN_1 0x00000080U
Kojto	122:f9eeca106725	5421	#define RCC_PLLCFGR_PLLN_2 0x00000100U
Kojto	122:f9eeca106725	5422	#define RCC_PLLCFGR_PLLN_3 0x00000200U
Kojto	122:f9eeca106725	5423	#define RCC_PLLCFGR_PLLN_4 0x00000400U
Kojto	122:f9eeca106725	5424	#define RCC_PLLCFGR_PLLN_5 0x00000800U
Kojto	122:f9eeca106725	5425	#define RCC_PLLCFGR_PLLN_6 0x00001000U
Kojto	122:f9eeca106725	5426	#define RCC_PLLCFGR_PLLN_7 0x00002000U
Kojto	122:f9eeca106725	5427	#define RCC_PLLCFGR_PLLN_8 0x00004000U
Kojto	122:f9eeca106725	5428	#define RCC_PLLCFGR_PLLP 0x00030000U
Kojto	122:f9eeca106725	5429	#define RCC_PLLCFGR_PLLP_0 0x00010000U
Kojto	122:f9eeca106725	5430	#define RCC_PLLCFGR_PLLP_1 0x00020000U
Kojto	122:f9eeca106725	5431	#define RCC_PLLCFGR_PLLSRC 0x00400000U
Kojto	122:f9eeca106725	5432	#define RCC_PLLCFGR_PLLSRC_HSE 0x00400000U
Kojto	122:f9eeca106725	5433	#define RCC_PLLCFGR_PLLSRC_HSI 0x00000000U
Kojto	122:f9eeca106725	5434	#define RCC_PLLCFGR_PLLQ 0x0F000000U
Kojto	122:f9eeca106725	5435	#define RCC_PLLCFGR_PLLQ_0 0x01000000U
Kojto	122:f9eeca106725	5436	#define RCC_PLLCFGR_PLLQ_1 0x02000000U
Kojto	122:f9eeca106725	5437	#define RCC_PLLCFGR_PLLQ_2 0x04000000U
Kojto	122:f9eeca106725	5438	#define RCC_PLLCFGR_PLLQ_3 0x08000000U
Kojto	107:4f6c30876dfa	5439
Kojto	116:c0f6e94411f5	5440
Kojto	107:4f6c30876dfa	5441	/****************** Bit definition for RCC_CFGR register ****************/
Kojto	107:4f6c30876dfa	5442	/!< SW configuration /
Kojto	122:f9eeca106725	5443	#define RCC_CFGR_SW 0x00000003U /!< SW[1:0] bits (System clock Switch) /
Kojto	122:f9eeca106725	5444	#define RCC_CFGR_SW_0 0x00000001U /!< Bit 0 /
Kojto	122:f9eeca106725	5445	#define RCC_CFGR_SW_1 0x00000002U /!< Bit 1 /
Kojto	122:f9eeca106725	5446	#define RCC_CFGR_SW_HSI 0x00000000U /!< HSI selected as system clock /
Kojto	122:f9eeca106725	5447	#define RCC_CFGR_SW_HSE 0x00000001U /!< HSE selected as system clock /
Kojto	122:f9eeca106725	5448	#define RCC_CFGR_SW_PLL 0x00000002U /!< PLL selected as system clock /
Kojto	107:4f6c30876dfa	5449
Kojto	107:4f6c30876dfa	5450	/!< SWS configuration /
Kojto	122:f9eeca106725	5451	#define RCC_CFGR_SWS 0x0000000CU /!< SWS[1:0] bits (System Clock Switch Status) /
Kojto	122:f9eeca106725	5452	#define RCC_CFGR_SWS_0 0x00000004U /!< Bit 0 /
Kojto	122:f9eeca106725	5453	#define RCC_CFGR_SWS_1 0x00000008U /!< Bit 1 /
Kojto	122:f9eeca106725	5454	#define RCC_CFGR_SWS_HSI 0x00000000U /!< HSI oscillator used as system clock /
Kojto	122:f9eeca106725	5455	#define RCC_CFGR_SWS_HSE 0x00000004U /!< HSE oscillator used as system clock /
Kojto	122:f9eeca106725	5456	#define RCC_CFGR_SWS_PLL 0x00000008U /!< PLL used as system clock /
Kojto	107:4f6c30876dfa	5457
Kojto	107:4f6c30876dfa	5458	/!< HPRE configuration /
Kojto	122:f9eeca106725	5459	#define RCC_CFGR_HPRE 0x000000F0U /!< HPRE[3:0] bits (AHB prescaler) /
Kojto	122:f9eeca106725	5460	#define RCC_CFGR_HPRE_0 0x00000010U /!< Bit 0 /
Kojto	122:f9eeca106725	5461	#define RCC_CFGR_HPRE_1 0x00000020U /!< Bit 1 /
Kojto	122:f9eeca106725	5462	#define RCC_CFGR_HPRE_2 0x00000040U /!< Bit 2 /
Kojto	122:f9eeca106725	5463	#define RCC_CFGR_HPRE_3 0x00000080U /!< Bit 3 /
Kojto	122:f9eeca106725	5464
Kojto	122:f9eeca106725	5465	#define RCC_CFGR_HPRE_DIV1 0x00000000U /!< SYSCLK not divided /
Kojto	122:f9eeca106725	5466	#define RCC_CFGR_HPRE_DIV2 0x00000080U /!< SYSCLK divided by 2 /
Kojto	122:f9eeca106725	5467	#define RCC_CFGR_HPRE_DIV4 0x00000090U /!< SYSCLK divided by 4 /
Kojto	122:f9eeca106725	5468	#define RCC_CFGR_HPRE_DIV8 0x000000A0U /!< SYSCLK divided by 8 /
Kojto	122:f9eeca106725	5469	#define RCC_CFGR_HPRE_DIV16 0x000000B0U /!< SYSCLK divided by 16 /
Kojto	122:f9eeca106725	5470	#define RCC_CFGR_HPRE_DIV64 0x000000C0U /!< SYSCLK divided by 64 /
Kojto	122:f9eeca106725	5471	#define RCC_CFGR_HPRE_DIV128 0x000000D0U /!< SYSCLK divided by 128 /
Kojto	122:f9eeca106725	5472	#define RCC_CFGR_HPRE_DIV256 0x000000E0U /!< SYSCLK divided by 256 /
Kojto	122:f9eeca106725	5473	#define RCC_CFGR_HPRE_DIV512 0x000000F0U /!< SYSCLK divided by 512 /
Kojto	107:4f6c30876dfa	5474
Kojto	107:4f6c30876dfa	5475	/!< PPRE1 configuration /
Kojto	122:f9eeca106725	5476	#define RCC_CFGR_PPRE1 0x00001C00U /!< PRE1[2:0] bits (APB1 prescaler) /
Kojto	122:f9eeca106725	5477	#define RCC_CFGR_PPRE1_0 0x00000400U /!< Bit 0 /
Kojto	122:f9eeca106725	5478	#define RCC_CFGR_PPRE1_1 0x00000800U /!< Bit 1 /
Kojto	122:f9eeca106725	5479	#define RCC_CFGR_PPRE1_2 0x00001000U /!< Bit 2 /
Kojto	122:f9eeca106725	5480
Kojto	122:f9eeca106725	5481	#define RCC_CFGR_PPRE1_DIV1 0x00000000U /!< HCLK not divided /
Kojto	122:f9eeca106725	5482	#define RCC_CFGR_PPRE1_DIV2 0x00001000U /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	5483	#define RCC_CFGR_PPRE1_DIV4 0x00001400U /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	5484	#define RCC_CFGR_PPRE1_DIV8 0x00001800U /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	5485	#define RCC_CFGR_PPRE1_DIV16 0x00001C00U /!< HCLK divided by 16 /
Kojto	107:4f6c30876dfa	5486
Kojto	107:4f6c30876dfa	5487	/!< PPRE2 configuration /
Kojto	122:f9eeca106725	5488	#define RCC_CFGR_PPRE2 0x0000E000U /!< PRE2[2:0] bits (APB2 prescaler) /
Kojto	122:f9eeca106725	5489	#define RCC_CFGR_PPRE2_0 0x00002000U /!< Bit 0 /
Kojto	122:f9eeca106725	5490	#define RCC_CFGR_PPRE2_1 0x00004000U /!< Bit 1 /
Kojto	122:f9eeca106725	5491	#define RCC_CFGR_PPRE2_2 0x00008000U /!< Bit 2 /
Kojto	122:f9eeca106725	5492
Kojto	122:f9eeca106725	5493	#define RCC_CFGR_PPRE2_DIV1 0x00000000U /!< HCLK not divided /
Kojto	122:f9eeca106725	5494	#define RCC_CFGR_PPRE2_DIV2 0x00008000U /!< HCLK divided by 2 /
Kojto	122:f9eeca106725	5495	#define RCC_CFGR_PPRE2_DIV4 0x0000A000U /!< HCLK divided by 4 /
Kojto	122:f9eeca106725	5496	#define RCC_CFGR_PPRE2_DIV8 0x0000C000U /!< HCLK divided by 8 /
Kojto	122:f9eeca106725	5497	#define RCC_CFGR_PPRE2_DIV16 0x0000E000U /!< HCLK divided by 16 /
Kojto	107:4f6c30876dfa	5498
Kojto	107:4f6c30876dfa	5499	/!< RTCPRE configuration /
Kojto	122:f9eeca106725	5500	#define RCC_CFGR_RTCPRE 0x001F0000U
Kojto	122:f9eeca106725	5501	#define RCC_CFGR_RTCPRE_0 0x00010000U
Kojto	122:f9eeca106725	5502	#define RCC_CFGR_RTCPRE_1 0x00020000U
Kojto	122:f9eeca106725	5503	#define RCC_CFGR_RTCPRE_2 0x00040000U
Kojto	122:f9eeca106725	5504	#define RCC_CFGR_RTCPRE_3 0x00080000U
Kojto	122:f9eeca106725	5505	#define RCC_CFGR_RTCPRE_4 0x00100000U
Kojto	107:4f6c30876dfa	5506
Kojto	107:4f6c30876dfa	5507	/!< MCO1 configuration /
Kojto	122:f9eeca106725	5508	#define RCC_CFGR_MCO1 0x00600000U
Kojto	122:f9eeca106725	5509	#define RCC_CFGR_MCO1_0 0x00200000U
Kojto	122:f9eeca106725	5510	#define RCC_CFGR_MCO1_1 0x00400000U
Kojto	122:f9eeca106725	5511
Kojto	122:f9eeca106725	5512	#define RCC_CFGR_I2SSRC 0x00800000U
Kojto	122:f9eeca106725	5513
Kojto	122:f9eeca106725	5514	#define RCC_CFGR_MCO1PRE 0x07000000U
Kojto	122:f9eeca106725	5515	#define RCC_CFGR_MCO1PRE_0 0x01000000U
Kojto	122:f9eeca106725	5516	#define RCC_CFGR_MCO1PRE_1 0x02000000U
Kojto	122:f9eeca106725	5517	#define RCC_CFGR_MCO1PRE_2 0x04000000U
Kojto	122:f9eeca106725	5518
Kojto	122:f9eeca106725	5519	#define RCC_CFGR_MCO2PRE 0x38000000U
Kojto	122:f9eeca106725	5520	#define RCC_CFGR_MCO2PRE_0 0x08000000U
Kojto	122:f9eeca106725	5521	#define RCC_CFGR_MCO2PRE_1 0x10000000U
Kojto	122:f9eeca106725	5522	#define RCC_CFGR_MCO2PRE_2 0x20000000U
Kojto	122:f9eeca106725	5523
Kojto	122:f9eeca106725	5524	#define RCC_CFGR_MCO2 0xC0000000U
Kojto	122:f9eeca106725	5525	#define RCC_CFGR_MCO2_0 0x40000000U
Kojto	122:f9eeca106725	5526	#define RCC_CFGR_MCO2_1 0x80000000U
Kojto	107:4f6c30876dfa	5527
Kojto	107:4f6c30876dfa	5528	/****************** Bit definition for RCC_CIR register *****************/
Kojto	122:f9eeca106725	5529	#define RCC_CIR_LSIRDYF 0x00000001U
Kojto	122:f9eeca106725	5530	#define RCC_CIR_LSERDYF 0x00000002U
Kojto	122:f9eeca106725	5531	#define RCC_CIR_HSIRDYF 0x00000004U
Kojto	122:f9eeca106725	5532	#define RCC_CIR_HSERDYF 0x00000008U
Kojto	122:f9eeca106725	5533	#define RCC_CIR_PLLRDYF 0x00000010U
Kojto	122:f9eeca106725	5534	#define RCC_CIR_PLLI2SRDYF 0x00000020U
Kojto	122:f9eeca106725	5535	#define RCC_CIR_PLLSAIRDYF 0x00000040U
Kojto	122:f9eeca106725	5536	#define RCC_CIR_CSSF 0x00000080U
Kojto	122:f9eeca106725	5537	#define RCC_CIR_LSIRDYIE 0x00000100U
Kojto	122:f9eeca106725	5538	#define RCC_CIR_LSERDYIE 0x00000200U
Kojto	122:f9eeca106725	5539	#define RCC_CIR_HSIRDYIE 0x00000400U
Kojto	122:f9eeca106725	5540	#define RCC_CIR_HSERDYIE 0x00000800U
Kojto	122:f9eeca106725	5541	#define RCC_CIR_PLLRDYIE 0x00001000U
Kojto	122:f9eeca106725	5542	#define RCC_CIR_PLLI2SRDYIE 0x00002000U
Kojto	122:f9eeca106725	5543	#define RCC_CIR_PLLSAIRDYIE 0x00004000U
Kojto	122:f9eeca106725	5544	#define RCC_CIR_LSIRDYC 0x00010000U
Kojto	122:f9eeca106725	5545	#define RCC_CIR_LSERDYC 0x00020000U
Kojto	122:f9eeca106725	5546	#define RCC_CIR_HSIRDYC 0x00040000U
Kojto	122:f9eeca106725	5547	#define RCC_CIR_HSERDYC 0x00080000U
Kojto	122:f9eeca106725	5548	#define RCC_CIR_PLLRDYC 0x00100000U
Kojto	122:f9eeca106725	5549	#define RCC_CIR_PLLI2SRDYC 0x00200000U
Kojto	122:f9eeca106725	5550	#define RCC_CIR_PLLSAIRDYC 0x00400000U
Kojto	122:f9eeca106725	5551	#define RCC_CIR_CSSC 0x00800000U
Kojto	107:4f6c30876dfa	5552
Kojto	107:4f6c30876dfa	5553	/****************** Bit definition for RCC_AHB1RSTR register ************/
Kojto	122:f9eeca106725	5554	#define RCC_AHB1RSTR_GPIOARST 0x00000001U
Kojto	122:f9eeca106725	5555	#define RCC_AHB1RSTR_GPIOBRST 0x00000002U
Kojto	122:f9eeca106725	5556	#define RCC_AHB1RSTR_GPIOCRST 0x00000004U
Kojto	122:f9eeca106725	5557	#define RCC_AHB1RSTR_GPIODRST 0x00000008U
Kojto	122:f9eeca106725	5558	#define RCC_AHB1RSTR_GPIOERST 0x00000010U
Kojto	122:f9eeca106725	5559	#define RCC_AHB1RSTR_GPIOFRST 0x00000020U
Kojto	122:f9eeca106725	5560	#define RCC_AHB1RSTR_GPIOGRST 0x00000040U
Kojto	122:f9eeca106725	5561	#define RCC_AHB1RSTR_GPIOHRST 0x00000080U
Kojto	122:f9eeca106725	5562	#define RCC_AHB1RSTR_GPIOIRST 0x00000100U
Kojto	122:f9eeca106725	5563	#define RCC_AHB1RSTR_GPIOJRST 0x00000200U
Kojto	122:f9eeca106725	5564	#define RCC_AHB1RSTR_GPIOKRST 0x00000400U
Kojto	122:f9eeca106725	5565	#define RCC_AHB1RSTR_CRCRST 0x00001000U
Kojto	122:f9eeca106725	5566	#define RCC_AHB1RSTR_DMA1RST 0x00200000U
Kojto	122:f9eeca106725	5567	#define RCC_AHB1RSTR_DMA2RST 0x00400000U
Kojto	122:f9eeca106725	5568	#define RCC_AHB1RSTR_DMA2DRST 0x00800000U
Kojto	122:f9eeca106725	5569	#define RCC_AHB1RSTR_ETHMACRST 0x02000000U
Kojto	122:f9eeca106725	5570	#define RCC_AHB1RSTR_OTGHRST 0x20000000U
Kojto	107:4f6c30876dfa	5571
Kojto	107:4f6c30876dfa	5572	/****************** Bit definition for RCC_AHB2RSTR register ************/
Kojto	122:f9eeca106725	5573	#define RCC_AHB2RSTR_DCMIRST 0x00000001U
Kojto	122:f9eeca106725	5574	#define RCC_AHB2RSTR_RNGRST 0x00000040U
Kojto	122:f9eeca106725	5575	#define RCC_AHB2RSTR_OTGFSRST 0x00000080U
Kojto	107:4f6c30876dfa	5576
Kojto	107:4f6c30876dfa	5577	/****************** Bit definition for RCC_AHB3RSTR register ************/
Kojto	107:4f6c30876dfa	5578
Kojto	122:f9eeca106725	5579	#define RCC_AHB3RSTR_FMCRST 0x00000001U
Kojto	122:f9eeca106725	5580	#define RCC_AHB3RSTR_QSPIRST 0x00000002U
Kojto	107:4f6c30876dfa	5581
Kojto	107:4f6c30876dfa	5582	/****************** Bit definition for RCC_APB1RSTR register ************/
Kojto	122:f9eeca106725	5583	#define RCC_APB1RSTR_TIM2RST 0x00000001U
Kojto	122:f9eeca106725	5584	#define RCC_APB1RSTR_TIM3RST 0x00000002U
Kojto	122:f9eeca106725	5585	#define RCC_APB1RSTR_TIM4RST 0x00000004U
Kojto	122:f9eeca106725	5586	#define RCC_APB1RSTR_TIM5RST 0x00000008U
Kojto	122:f9eeca106725	5587	#define RCC_APB1RSTR_TIM6RST 0x00000010U
Kojto	122:f9eeca106725	5588	#define RCC_APB1RSTR_TIM7RST 0x00000020U
Kojto	122:f9eeca106725	5589	#define RCC_APB1RSTR_TIM12RST 0x00000040U
Kojto	122:f9eeca106725	5590	#define RCC_APB1RSTR_TIM13RST 0x00000080U
Kojto	122:f9eeca106725	5591	#define RCC_APB1RSTR_TIM14RST 0x00000100U
Kojto	122:f9eeca106725	5592	#define RCC_APB1RSTR_LPTIM1RST 0x00000200U
Kojto	122:f9eeca106725	5593	#define RCC_APB1RSTR_WWDGRST 0x00000800U
Kojto	122:f9eeca106725	5594	#define RCC_APB1RSTR_SPI2RST 0x00004000U
Kojto	122:f9eeca106725	5595	#define RCC_APB1RSTR_SPI3RST 0x00008000U
Kojto	122:f9eeca106725	5596	#define RCC_APB1RSTR_SPDIFRXRST 0x00010000U
Kojto	122:f9eeca106725	5597	#define RCC_APB1RSTR_USART2RST 0x00020000U
Kojto	122:f9eeca106725	5598	#define RCC_APB1RSTR_USART3RST 0x00040000U
Kojto	122:f9eeca106725	5599	#define RCC_APB1RSTR_UART4RST 0x00080000U
Kojto	122:f9eeca106725	5600	#define RCC_APB1RSTR_UART5RST 0x00100000U
Kojto	122:f9eeca106725	5601	#define RCC_APB1RSTR_I2C1RST 0x00200000U
Kojto	122:f9eeca106725	5602	#define RCC_APB1RSTR_I2C2RST 0x00400000U
Kojto	122:f9eeca106725	5603	#define RCC_APB1RSTR_I2C3RST 0x00800000U
Kojto	122:f9eeca106725	5604	#define RCC_APB1RSTR_I2C4RST 0x01000000U
Kojto	122:f9eeca106725	5605	#define RCC_APB1RSTR_CAN1RST 0x02000000U
Kojto	122:f9eeca106725	5606	#define RCC_APB1RSTR_CAN2RST 0x04000000U
Kojto	122:f9eeca106725	5607	#define RCC_APB1RSTR_CECRST 0x08000000U
Kojto	122:f9eeca106725	5608	#define RCC_APB1RSTR_PWRRST 0x10000000U
Kojto	122:f9eeca106725	5609	#define RCC_APB1RSTR_DACRST 0x20000000U
Kojto	122:f9eeca106725	5610	#define RCC_APB1RSTR_UART7RST 0x40000000U
Kojto	122:f9eeca106725	5611	#define RCC_APB1RSTR_UART8RST 0x80000000U
Kojto	107:4f6c30876dfa	5612
Kojto	107:4f6c30876dfa	5613	/****************** Bit definition for RCC_APB2RSTR register ************/
Kojto	122:f9eeca106725	5614	#define RCC_APB2RSTR_TIM1RST 0x00000001U
Kojto	122:f9eeca106725	5615	#define RCC_APB2RSTR_TIM8RST 0x00000002U
Kojto	122:f9eeca106725	5616	#define RCC_APB2RSTR_USART1RST 0x00000010U
Kojto	122:f9eeca106725	5617	#define RCC_APB2RSTR_USART6RST 0x00000020U
Kojto	122:f9eeca106725	5618	#define RCC_APB2RSTR_ADCRST 0x00000100U
Kojto	122:f9eeca106725	5619	#define RCC_APB2RSTR_SDMMC1RST 0x00000800U
Kojto	122:f9eeca106725	5620	#define RCC_APB2RSTR_SPI1RST 0x00001000U
Kojto	122:f9eeca106725	5621	#define RCC_APB2RSTR_SPI4RST 0x00002000U
Kojto	122:f9eeca106725	5622	#define RCC_APB2RSTR_SYSCFGRST 0x00004000U
Kojto	122:f9eeca106725	5623	#define RCC_APB2RSTR_TIM9RST 0x00010000U
Kojto	122:f9eeca106725	5624	#define RCC_APB2RSTR_TIM10RST 0x00020000U
Kojto	122:f9eeca106725	5625	#define RCC_APB2RSTR_TIM11RST 0x00040000U
Kojto	122:f9eeca106725	5626	#define RCC_APB2RSTR_SPI5RST 0x00100000U
Kojto	122:f9eeca106725	5627	#define RCC_APB2RSTR_SPI6RST 0x00200000U
Kojto	122:f9eeca106725	5628	#define RCC_APB2RSTR_SAI1RST 0x00400000U
Kojto	122:f9eeca106725	5629	#define RCC_APB2RSTR_SAI2RST 0x00800000U
Kojto	122:f9eeca106725	5630	#define RCC_APB2RSTR_LTDCRST 0x04000000U
Kojto	107:4f6c30876dfa	5631
Kojto	107:4f6c30876dfa	5632	/****************** Bit definition for RCC_AHB1ENR register *************/
Kojto	122:f9eeca106725	5633	#define RCC_AHB1ENR_GPIOAEN 0x00000001U
Kojto	122:f9eeca106725	5634	#define RCC_AHB1ENR_GPIOBEN 0x00000002U
Kojto	122:f9eeca106725	5635	#define RCC_AHB1ENR_GPIOCEN 0x00000004U
Kojto	122:f9eeca106725	5636	#define RCC_AHB1ENR_GPIODEN 0x00000008U
Kojto	122:f9eeca106725	5637	#define RCC_AHB1ENR_GPIOEEN 0x00000010U
Kojto	122:f9eeca106725	5638	#define RCC_AHB1ENR_GPIOFEN 0x00000020U
Kojto	122:f9eeca106725	5639	#define RCC_AHB1ENR_GPIOGEN 0x00000040U
Kojto	122:f9eeca106725	5640	#define RCC_AHB1ENR_GPIOHEN 0x00000080U
Kojto	122:f9eeca106725	5641	#define RCC_AHB1ENR_GPIOIEN 0x00000100U
Kojto	122:f9eeca106725	5642	#define RCC_AHB1ENR_GPIOJEN 0x00000200U
Kojto	122:f9eeca106725	5643	#define RCC_AHB1ENR_GPIOKEN 0x00000400U
Kojto	122:f9eeca106725	5644	#define RCC_AHB1ENR_CRCEN 0x00001000U
Kojto	122:f9eeca106725	5645	#define RCC_AHB1ENR_BKPSRAMEN 0x00040000U
Kojto	122:f9eeca106725	5646	#define RCC_AHB1ENR_DTCMRAMEN 0x00100000U
Kojto	122:f9eeca106725	5647	#define RCC_AHB1ENR_DMA1EN 0x00200000U
Kojto	122:f9eeca106725	5648	#define RCC_AHB1ENR_DMA2EN 0x00400000U
Kojto	122:f9eeca106725	5649	#define RCC_AHB1ENR_DMA2DEN 0x00800000U
Kojto	122:f9eeca106725	5650	#define RCC_AHB1ENR_ETHMACEN 0x02000000U
Kojto	122:f9eeca106725	5651	#define RCC_AHB1ENR_ETHMACTXEN 0x04000000U
Kojto	122:f9eeca106725	5652	#define RCC_AHB1ENR_ETHMACRXEN 0x08000000U
Kojto	122:f9eeca106725	5653	#define RCC_AHB1ENR_ETHMACPTPEN 0x10000000U
Kojto	122:f9eeca106725	5654	#define RCC_AHB1ENR_OTGHSEN 0x20000000U
Kojto	122:f9eeca106725	5655	#define RCC_AHB1ENR_OTGHSULPIEN 0x40000000U
Kojto	107:4f6c30876dfa	5656
Kojto	107:4f6c30876dfa	5657	/****************** Bit definition for RCC_AHB2ENR register *************/
Kojto	122:f9eeca106725	5658	#define RCC_AHB2ENR_DCMIEN 0x00000001U
Kojto	122:f9eeca106725	5659	#define RCC_AHB2ENR_RNGEN 0x00000040U
Kojto	122:f9eeca106725	5660	#define RCC_AHB2ENR_OTGFSEN 0x00000080U
Kojto	107:4f6c30876dfa	5661
Kojto	107:4f6c30876dfa	5662	/****************** Bit definition for RCC_AHB3ENR register *************/
Kojto	122:f9eeca106725	5663	#define RCC_AHB3ENR_FMCEN 0x00000001U
Kojto	122:f9eeca106725	5664	#define RCC_AHB3ENR_QSPIEN 0x00000002U
Kojto	107:4f6c30876dfa	5665
Kojto	107:4f6c30876dfa	5666	/****************** Bit definition for RCC_APB1ENR register *************/
Kojto	122:f9eeca106725	5667	#define RCC_APB1ENR_TIM2EN 0x00000001U
Kojto	122:f9eeca106725	5668	#define RCC_APB1ENR_TIM3EN 0x00000002U
Kojto	122:f9eeca106725	5669	#define RCC_APB1ENR_TIM4EN 0x00000004U
Kojto	122:f9eeca106725	5670	#define RCC_APB1ENR_TIM5EN 0x00000008U
Kojto	122:f9eeca106725	5671	#define RCC_APB1ENR_TIM6EN 0x00000010U
Kojto	122:f9eeca106725	5672	#define RCC_APB1ENR_TIM7EN 0x00000020U
Kojto	122:f9eeca106725	5673	#define RCC_APB1ENR_TIM12EN 0x00000040U
Kojto	122:f9eeca106725	5674	#define RCC_APB1ENR_TIM13EN 0x00000080U
Kojto	122:f9eeca106725	5675	#define RCC_APB1ENR_TIM14EN 0x00000100U
Kojto	122:f9eeca106725	5676	#define RCC_APB1ENR_LPTIM1EN 0x00000200U
Kojto	122:f9eeca106725	5677	#define RCC_APB1ENR_WWDGEN 0x00000800U
Kojto	122:f9eeca106725	5678	#define RCC_APB1ENR_SPI2EN 0x00004000U
Kojto	122:f9eeca106725	5679	#define RCC_APB1ENR_SPI3EN 0x00008000U
Kojto	122:f9eeca106725	5680	#define RCC_APB1ENR_SPDIFRXEN 0x00010000U
Kojto	122:f9eeca106725	5681	#define RCC_APB1ENR_USART2EN 0x00020000U
Kojto	122:f9eeca106725	5682	#define RCC_APB1ENR_USART3EN 0x00040000U
Kojto	122:f9eeca106725	5683	#define RCC_APB1ENR_UART4EN 0x00080000U
Kojto	122:f9eeca106725	5684	#define RCC_APB1ENR_UART5EN 0x00100000U
Kojto	122:f9eeca106725	5685	#define RCC_APB1ENR_I2C1EN 0x00200000U
Kojto	122:f9eeca106725	5686	#define RCC_APB1ENR_I2C2EN 0x00400000U
Kojto	122:f9eeca106725	5687	#define RCC_APB1ENR_I2C3EN 0x00800000U
Kojto	122:f9eeca106725	5688	#define RCC_APB1ENR_I2C4EN 0x01000000U
Kojto	122:f9eeca106725	5689	#define RCC_APB1ENR_CAN1EN 0x02000000U
Kojto	122:f9eeca106725	5690	#define RCC_APB1ENR_CAN2EN 0x04000000U
Kojto	122:f9eeca106725	5691	#define RCC_APB1ENR_CECEN 0x08000000U
Kojto	122:f9eeca106725	5692	#define RCC_APB1ENR_PWREN 0x10000000U
Kojto	122:f9eeca106725	5693	#define RCC_APB1ENR_DACEN 0x20000000U
Kojto	122:f9eeca106725	5694	#define RCC_APB1ENR_UART7EN 0x40000000U
Kojto	122:f9eeca106725	5695	#define RCC_APB1ENR_UART8EN 0x80000000U
Kojto	107:4f6c30876dfa	5696
Kojto	107:4f6c30876dfa	5697	/****************** Bit definition for RCC_APB2ENR register *************/
Kojto	122:f9eeca106725	5698	#define RCC_APB2ENR_TIM1EN 0x00000001U
Kojto	122:f9eeca106725	5699	#define RCC_APB2ENR_TIM8EN 0x00000002U
Kojto	122:f9eeca106725	5700	#define RCC_APB2ENR_USART1EN 0x00000010U
Kojto	122:f9eeca106725	5701	#define RCC_APB2ENR_USART6EN 0x00000020U
Kojto	122:f9eeca106725	5702	#define RCC_APB2ENR_ADC1EN 0x00000100U
Kojto	122:f9eeca106725	5703	#define RCC_APB2ENR_ADC2EN 0x00000200U
Kojto	122:f9eeca106725	5704	#define RCC_APB2ENR_ADC3EN 0x00000400U
Kojto	122:f9eeca106725	5705	#define RCC_APB2ENR_SDMMC1EN 0x00000800U
Kojto	122:f9eeca106725	5706	#define RCC_APB2ENR_SPI1EN 0x00001000U
Kojto	122:f9eeca106725	5707	#define RCC_APB2ENR_SPI4EN 0x00002000U
Kojto	122:f9eeca106725	5708	#define RCC_APB2ENR_SYSCFGEN 0x00004000U
Kojto	122:f9eeca106725	5709	#define RCC_APB2ENR_TIM9EN 0x00010000U
Kojto	122:f9eeca106725	5710	#define RCC_APB2ENR_TIM10EN 0x00020000U
Kojto	122:f9eeca106725	5711	#define RCC_APB2ENR_TIM11EN 0x00040000U
Kojto	122:f9eeca106725	5712	#define RCC_APB2ENR_SPI5EN 0x00100000U
Kojto	122:f9eeca106725	5713	#define RCC_APB2ENR_SPI6EN 0x00200000U
Kojto	122:f9eeca106725	5714	#define RCC_APB2ENR_SAI1EN 0x00400000U
Kojto	122:f9eeca106725	5715	#define RCC_APB2ENR_SAI2EN 0x00800000U
Kojto	122:f9eeca106725	5716	#define RCC_APB2ENR_LTDCEN 0x04000000U
Kojto	107:4f6c30876dfa	5717
Kojto	107:4f6c30876dfa	5718	/****************** Bit definition for RCC_AHB1LPENR register ***********/
Kojto	122:f9eeca106725	5719	#define RCC_AHB1LPENR_GPIOALPEN 0x00000001U
Kojto	122:f9eeca106725	5720	#define RCC_AHB1LPENR_GPIOBLPEN 0x00000002U
Kojto	122:f9eeca106725	5721	#define RCC_AHB1LPENR_GPIOCLPEN 0x00000004U
Kojto	122:f9eeca106725	5722	#define RCC_AHB1LPENR_GPIODLPEN 0x00000008U
Kojto	122:f9eeca106725	5723	#define RCC_AHB1LPENR_GPIOELPEN 0x00000010U
Kojto	122:f9eeca106725	5724	#define RCC_AHB1LPENR_GPIOFLPEN 0x00000020U
Kojto	122:f9eeca106725	5725	#define RCC_AHB1LPENR_GPIOGLPEN 0x00000040U
Kojto	122:f9eeca106725	5726	#define RCC_AHB1LPENR_GPIOHLPEN 0x00000080U
Kojto	122:f9eeca106725	5727	#define RCC_AHB1LPENR_GPIOILPEN 0x00000100U
Kojto	122:f9eeca106725	5728	#define RCC_AHB1LPENR_GPIOJLPEN 0x00000200U
Kojto	122:f9eeca106725	5729	#define RCC_AHB1LPENR_GPIOKLPEN 0x00000400U
Kojto	122:f9eeca106725	5730	#define RCC_AHB1LPENR_CRCLPEN 0x00001000U
Kojto	122:f9eeca106725	5731	#define RCC_AHB1LPENR_AXILPEN 0x00002000U
Kojto	122:f9eeca106725	5732	#define RCC_AHB1LPENR_FLITFLPEN 0x00008000U
Kojto	122:f9eeca106725	5733	#define RCC_AHB1LPENR_SRAM1LPEN 0x00010000U
Kojto	122:f9eeca106725	5734	#define RCC_AHB1LPENR_SRAM2LPEN 0x00020000U
Kojto	122:f9eeca106725	5735	#define RCC_AHB1LPENR_BKPSRAMLPEN 0x00040000U
Kojto	122:f9eeca106725	5736	#define RCC_AHB1LPENR_DTCMLPEN 0x00100000U
Kojto	122:f9eeca106725	5737	#define RCC_AHB1LPENR_DMA1LPEN 0x00200000U
Kojto	122:f9eeca106725	5738	#define RCC_AHB1LPENR_DMA2LPEN 0x00400000U
Kojto	122:f9eeca106725	5739	#define RCC_AHB1LPENR_DMA2DLPEN 0x00800000U
Kojto	122:f9eeca106725	5740	#define RCC_AHB1LPENR_ETHMACLPEN 0x02000000U
Kojto	122:f9eeca106725	5741	#define RCC_AHB1LPENR_ETHMACTXLPEN 0x04000000U
Kojto	122:f9eeca106725	5742	#define RCC_AHB1LPENR_ETHMACRXLPEN 0x08000000U
Kojto	122:f9eeca106725	5743	#define RCC_AHB1LPENR_ETHMACPTPLPEN 0x10000000U
Kojto	122:f9eeca106725	5744	#define RCC_AHB1LPENR_OTGHSLPEN 0x20000000U
Kojto	122:f9eeca106725	5745	#define RCC_AHB1LPENR_OTGHSULPILPEN 0x40000000U
Kojto	107:4f6c30876dfa	5746
Kojto	107:4f6c30876dfa	5747	/****************** Bit definition for RCC_AHB2LPENR register ***********/
Kojto	122:f9eeca106725	5748	#define RCC_AHB2LPENR_DCMILPEN 0x00000001U
Kojto	122:f9eeca106725	5749	#define RCC_AHB2LPENR_RNGLPEN 0x00000040U
Kojto	122:f9eeca106725	5750	#define RCC_AHB2LPENR_OTGFSLPEN 0x00000080U
Kojto	107:4f6c30876dfa	5751
Kojto	107:4f6c30876dfa	5752	/****************** Bit definition for RCC_AHB3LPENR register ***********/
Kojto	122:f9eeca106725	5753	#define RCC_AHB3LPENR_FMCLPEN 0x00000001U
Kojto	122:f9eeca106725	5754	#define RCC_AHB3LPENR_QSPILPEN 0x00000002U
Kojto	107:4f6c30876dfa	5755	/****************** Bit definition for RCC_APB1LPENR register ***********/
Kojto	122:f9eeca106725	5756	#define RCC_APB1LPENR_TIM2LPEN 0x00000001U
Kojto	122:f9eeca106725	5757	#define RCC_APB1LPENR_TIM3LPEN 0x00000002U
Kojto	122:f9eeca106725	5758	#define RCC_APB1LPENR_TIM4LPEN 0x00000004U
Kojto	122:f9eeca106725	5759	#define RCC_APB1LPENR_TIM5LPEN 0x00000008U
Kojto	122:f9eeca106725	5760	#define RCC_APB1LPENR_TIM6LPEN 0x00000010U
Kojto	122:f9eeca106725	5761	#define RCC_APB1LPENR_TIM7LPEN 0x00000020U
Kojto	122:f9eeca106725	5762	#define RCC_APB1LPENR_TIM12LPEN 0x00000040U
Kojto	122:f9eeca106725	5763	#define RCC_APB1LPENR_TIM13LPEN 0x00000080U
Kojto	122:f9eeca106725	5764	#define RCC_APB1LPENR_TIM14LPEN 0x00000100U
Kojto	122:f9eeca106725	5765	#define RCC_APB1LPENR_LPTIM1LPEN 0x00000200U
Kojto	122:f9eeca106725	5766	#define RCC_APB1LPENR_WWDGLPEN 0x00000800U
Kojto	122:f9eeca106725	5767	#define RCC_APB1LPENR_SPI2LPEN 0x00004000U
Kojto	122:f9eeca106725	5768	#define RCC_APB1LPENR_SPI3LPEN 0x00008000U
Kojto	122:f9eeca106725	5769	#define RCC_APB1LPENR_SPDIFRXLPEN 0x00010000U
Kojto	122:f9eeca106725	5770	#define RCC_APB1LPENR_USART2LPEN 0x00020000U
Kojto	122:f9eeca106725	5771	#define RCC_APB1LPENR_USART3LPEN 0x00040000U
Kojto	122:f9eeca106725	5772	#define RCC_APB1LPENR_UART4LPEN 0x00080000U
Kojto	122:f9eeca106725	5773	#define RCC_APB1LPENR_UART5LPEN 0x00100000U
Kojto	122:f9eeca106725	5774	#define RCC_APB1LPENR_I2C1LPEN 0x00200000U
Kojto	122:f9eeca106725	5775	#define RCC_APB1LPENR_I2C2LPEN 0x00400000U
Kojto	122:f9eeca106725	5776	#define RCC_APB1LPENR_I2C3LPEN 0x00800000U
Kojto	122:f9eeca106725	5777	#define RCC_APB1LPENR_I2C4LPEN 0x01000000U
Kojto	122:f9eeca106725	5778	#define RCC_APB1LPENR_CAN1LPEN 0x02000000U
Kojto	122:f9eeca106725	5779	#define RCC_APB1LPENR_CAN2LPEN 0x04000000U
Kojto	122:f9eeca106725	5780	#define RCC_APB1LPENR_CECLPEN 0x08000000U
Kojto	122:f9eeca106725	5781	#define RCC_APB1LPENR_PWRLPEN 0x10000000U
Kojto	122:f9eeca106725	5782	#define RCC_APB1LPENR_DACLPEN 0x20000000U
Kojto	122:f9eeca106725	5783	#define RCC_APB1LPENR_UART7LPEN 0x40000000U
Kojto	122:f9eeca106725	5784	#define RCC_APB1LPENR_UART8LPEN 0x80000000U
Kojto	107:4f6c30876dfa	5785
Kojto	107:4f6c30876dfa	5786	/****************** Bit definition for RCC_APB2LPENR register ***********/
Kojto	122:f9eeca106725	5787	#define RCC_APB2LPENR_TIM1LPEN 0x00000001U
Kojto	122:f9eeca106725	5788	#define RCC_APB2LPENR_TIM8LPEN 0x00000002U
Kojto	122:f9eeca106725	5789	#define RCC_APB2LPENR_USART1LPEN 0x00000010U
Kojto	122:f9eeca106725	5790	#define RCC_APB2LPENR_USART6LPEN 0x00000020U
Kojto	122:f9eeca106725	5791	#define RCC_APB2LPENR_ADC1LPEN 0x00000100U
Kojto	122:f9eeca106725	5792	#define RCC_APB2LPENR_ADC2LPEN 0x00000200U
Kojto	122:f9eeca106725	5793	#define RCC_APB2LPENR_ADC3LPEN 0x00000400U
Kojto	122:f9eeca106725	5794	#define RCC_APB2LPENR_SDMMC1LPEN 0x00000800U
Kojto	122:f9eeca106725	5795	#define RCC_APB2LPENR_SPI1LPEN 0x00001000U
Kojto	122:f9eeca106725	5796	#define RCC_APB2LPENR_SPI4LPEN 0x00002000U
Kojto	122:f9eeca106725	5797	#define RCC_APB2LPENR_SYSCFGLPEN 0x00004000U
Kojto	122:f9eeca106725	5798	#define RCC_APB2LPENR_TIM9LPEN 0x00010000U
Kojto	122:f9eeca106725	5799	#define RCC_APB2LPENR_TIM10LPEN 0x00020000U
Kojto	122:f9eeca106725	5800	#define RCC_APB2LPENR_TIM11LPEN 0x00040000U
Kojto	122:f9eeca106725	5801	#define RCC_APB2LPENR_SPI5LPEN 0x00100000U
Kojto	122:f9eeca106725	5802	#define RCC_APB2LPENR_SPI6LPEN 0x00200000U
Kojto	122:f9eeca106725	5803	#define RCC_APB2LPENR_SAI1LPEN 0x00400000U
Kojto	122:f9eeca106725	5804	#define RCC_APB2LPENR_SAI2LPEN 0x00800000U
Kojto	122:f9eeca106725	5805	#define RCC_APB2LPENR_LTDCLPEN 0x04000000U
Kojto	107:4f6c30876dfa	5806
Kojto	107:4f6c30876dfa	5807	/****************** Bit definition for RCC_BDCR register ****************/
Kojto	122:f9eeca106725	5808	#define RCC_BDCR_LSEON 0x00000001U
Kojto	122:f9eeca106725	5809	#define RCC_BDCR_LSERDY 0x00000002U
Kojto	122:f9eeca106725	5810	#define RCC_BDCR_LSEBYP 0x00000004U
Kojto	122:f9eeca106725	5811	#define RCC_BDCR_LSEDRV 0x00000018U
Kojto	122:f9eeca106725	5812	#define RCC_BDCR_LSEDRV_0 0x00000008U
Kojto	122:f9eeca106725	5813	#define RCC_BDCR_LSEDRV_1 0x00000010U
Kojto	122:f9eeca106725	5814	#define RCC_BDCR_RTCSEL 0x00000300U
Kojto	122:f9eeca106725	5815	#define RCC_BDCR_RTCSEL_0 0x00000100U
Kojto	122:f9eeca106725	5816	#define RCC_BDCR_RTCSEL_1 0x00000200U
Kojto	122:f9eeca106725	5817	#define RCC_BDCR_RTCEN 0x00008000U
Kojto	122:f9eeca106725	5818	#define RCC_BDCR_BDRST 0x00010000U
Kojto	107:4f6c30876dfa	5819
Kojto	107:4f6c30876dfa	5820	/****************** Bit definition for RCC_CSR register *****************/
Kojto	122:f9eeca106725	5821	#define RCC_CSR_LSION 0x00000001U
Kojto	122:f9eeca106725	5822	#define RCC_CSR_LSIRDY 0x00000002U
Kojto	122:f9eeca106725	5823	#define RCC_CSR_RMVF 0x01000000U
Kojto	122:f9eeca106725	5824	#define RCC_CSR_BORRSTF 0x02000000U
Kojto	122:f9eeca106725	5825	#define RCC_CSR_PINRSTF 0x04000000U
Kojto	122:f9eeca106725	5826	#define RCC_CSR_PORRSTF 0x08000000U
Kojto	122:f9eeca106725	5827	#define RCC_CSR_SFTRSTF 0x10000000U
Kojto	122:f9eeca106725	5828	#define RCC_CSR_IWDGRSTF 0x20000000U
Kojto	122:f9eeca106725	5829	#define RCC_CSR_WWDGRSTF 0x40000000U
Kojto	122:f9eeca106725	5830	#define RCC_CSR_LPWRRSTF 0x80000000U
Kojto	107:4f6c30876dfa	5831
Kojto	107:4f6c30876dfa	5832	/****************** Bit definition for RCC_SSCGR register ***************/
Kojto	122:f9eeca106725	5833	#define RCC_SSCGR_MODPER 0x00001FFFU
Kojto	122:f9eeca106725	5834	#define RCC_SSCGR_INCSTEP 0x0FFFE000U
Kojto	122:f9eeca106725	5835	#define RCC_SSCGR_SPREADSEL 0x40000000U
Kojto	122:f9eeca106725	5836	#define RCC_SSCGR_SSCGEN 0x80000000U
Kojto	107:4f6c30876dfa	5837
Kojto	107:4f6c30876dfa	5838	/****************** Bit definition for RCC_PLLI2SCFGR register **********/
Kojto	122:f9eeca106725	5839	#define RCC_PLLI2SCFGR_PLLI2SN 0x00007FC0U
Kojto	122:f9eeca106725	5840	#define RCC_PLLI2SCFGR_PLLI2SN_0 0x00000040U
Kojto	122:f9eeca106725	5841	#define RCC_PLLI2SCFGR_PLLI2SN_1 0x00000080U
Kojto	122:f9eeca106725	5842	#define RCC_PLLI2SCFGR_PLLI2SN_2 0x00000100U
Kojto	122:f9eeca106725	5843	#define RCC_PLLI2SCFGR_PLLI2SN_3 0x00000200U
Kojto	122:f9eeca106725	5844	#define RCC_PLLI2SCFGR_PLLI2SN_4 0x00000400U
Kojto	122:f9eeca106725	5845	#define RCC_PLLI2SCFGR_PLLI2SN_5 0x00000800U
Kojto	122:f9eeca106725	5846	#define RCC_PLLI2SCFGR_PLLI2SN_6 0x00001000U
Kojto	122:f9eeca106725	5847	#define RCC_PLLI2SCFGR_PLLI2SN_7 0x00002000U
Kojto	122:f9eeca106725	5848	#define RCC_PLLI2SCFGR_PLLI2SN_8 0x00004000U
Kojto	122:f9eeca106725	5849	#define RCC_PLLI2SCFGR_PLLI2SP 0x00030000U
Kojto	122:f9eeca106725	5850	#define RCC_PLLI2SCFGR_PLLI2SP_0 0x00010000U
Kojto	122:f9eeca106725	5851	#define RCC_PLLI2SCFGR_PLLI2SP_1 0x00020000U
Kojto	122:f9eeca106725	5852	#define RCC_PLLI2SCFGR_PLLI2SQ 0x0F000000U
Kojto	122:f9eeca106725	5853	#define RCC_PLLI2SCFGR_PLLI2SQ_0 0x01000000U
Kojto	122:f9eeca106725	5854	#define RCC_PLLI2SCFGR_PLLI2SQ_1 0x02000000U
Kojto	122:f9eeca106725	5855	#define RCC_PLLI2SCFGR_PLLI2SQ_2 0x04000000U
Kojto	122:f9eeca106725	5856	#define RCC_PLLI2SCFGR_PLLI2SQ_3 0x08000000U
Kojto	122:f9eeca106725	5857	#define RCC_PLLI2SCFGR_PLLI2SR 0x70000000U
Kojto	122:f9eeca106725	5858	#define RCC_PLLI2SCFGR_PLLI2SR_0 0x10000000U
Kojto	122:f9eeca106725	5859	#define RCC_PLLI2SCFGR_PLLI2SR_1 0x20000000U
Kojto	122:f9eeca106725	5860	#define RCC_PLLI2SCFGR_PLLI2SR_2 0x40000000U
Kojto	107:4f6c30876dfa	5861
Kojto	107:4f6c30876dfa	5862	/****************** Bit definition for RCC_PLLSAICFGR register **********/
Kojto	122:f9eeca106725	5863	#define RCC_PLLSAICFGR_PLLSAIN 0x00007FC0U
Kojto	122:f9eeca106725	5864	#define RCC_PLLSAICFGR_PLLSAIN_0 0x00000040U
Kojto	122:f9eeca106725	5865	#define RCC_PLLSAICFGR_PLLSAIN_1 0x00000080U
Kojto	122:f9eeca106725	5866	#define RCC_PLLSAICFGR_PLLSAIN_2 0x00000100U
Kojto	122:f9eeca106725	5867	#define RCC_PLLSAICFGR_PLLSAIN_3 0x00000200U
Kojto	122:f9eeca106725	5868	#define RCC_PLLSAICFGR_PLLSAIN_4 0x00000400U
Kojto	122:f9eeca106725	5869	#define RCC_PLLSAICFGR_PLLSAIN_5 0x00000800U
Kojto	122:f9eeca106725	5870	#define RCC_PLLSAICFGR_PLLSAIN_6 0x00001000U
Kojto	122:f9eeca106725	5871	#define RCC_PLLSAICFGR_PLLSAIN_7 0x00002000U
Kojto	122:f9eeca106725	5872	#define RCC_PLLSAICFGR_PLLSAIN_8 0x00004000U
Kojto	122:f9eeca106725	5873	#define RCC_PLLSAICFGR_PLLSAIP 0x00030000U
Kojto	122:f9eeca106725	5874	#define RCC_PLLSAICFGR_PLLSAIP_0 0x00010000U
Kojto	122:f9eeca106725	5875	#define RCC_PLLSAICFGR_PLLSAIP_1 0x00020000U
Kojto	122:f9eeca106725	5876	#define RCC_PLLSAICFGR_PLLSAIQ 0x0F000000U
Kojto	122:f9eeca106725	5877	#define RCC_PLLSAICFGR_PLLSAIQ_0 0x01000000U
Kojto	122:f9eeca106725	5878	#define RCC_PLLSAICFGR_PLLSAIQ_1 0x02000000U
Kojto	122:f9eeca106725	5879	#define RCC_PLLSAICFGR_PLLSAIQ_2 0x04000000U
Kojto	122:f9eeca106725	5880	#define RCC_PLLSAICFGR_PLLSAIQ_3 0x08000000U
Kojto	122:f9eeca106725	5881	#define RCC_PLLSAICFGR_PLLSAIR 0x70000000U
Kojto	122:f9eeca106725	5882	#define RCC_PLLSAICFGR_PLLSAIR_0 0x10000000U
Kojto	122:f9eeca106725	5883	#define RCC_PLLSAICFGR_PLLSAIR_1 0x20000000U
Kojto	122:f9eeca106725	5884	#define RCC_PLLSAICFGR_PLLSAIR_2 0x40000000U
Kojto	107:4f6c30876dfa	5885
Kojto	107:4f6c30876dfa	5886	/****************** Bit definition for RCC_DCKCFGR1 register *************/
Kojto	122:f9eeca106725	5887	#define RCC_DCKCFGR1_PLLI2SDIVQ 0x0000001FU
Kojto	122:f9eeca106725	5888	#define RCC_DCKCFGR1_PLLI2SDIVQ_0 0x00000001U
Kojto	122:f9eeca106725	5889	#define RCC_DCKCFGR1_PLLI2SDIVQ_1 0x00000002U
Kojto	122:f9eeca106725	5890	#define RCC_DCKCFGR1_PLLI2SDIVQ_2 0x00000004U
Kojto	122:f9eeca106725	5891	#define RCC_DCKCFGR1_PLLI2SDIVQ_3 0x00000008U
Kojto	122:f9eeca106725	5892	#define RCC_DCKCFGR1_PLLI2SDIVQ_4 0x00000010U
Kojto	122:f9eeca106725	5893
Kojto	122:f9eeca106725	5894	#define RCC_DCKCFGR1_PLLSAIDIVQ 0x00001F00U
Kojto	122:f9eeca106725	5895	#define RCC_DCKCFGR1_PLLSAIDIVQ_0 0x00000100U
Kojto	122:f9eeca106725	5896	#define RCC_DCKCFGR1_PLLSAIDIVQ_1 0x00000200U
Kojto	122:f9eeca106725	5897	#define RCC_DCKCFGR1_PLLSAIDIVQ_2 0x00000400U
Kojto	122:f9eeca106725	5898	#define RCC_DCKCFGR1_PLLSAIDIVQ_3 0x00000800U
Kojto	122:f9eeca106725	5899	#define RCC_DCKCFGR1_PLLSAIDIVQ_4 0x00001000U
Kojto	122:f9eeca106725	5900
Kojto	122:f9eeca106725	5901	#define RCC_DCKCFGR1_PLLSAIDIVR 0x00030000U
Kojto	122:f9eeca106725	5902	#define RCC_DCKCFGR1_PLLSAIDIVR_0 0x00010000U
Kojto	122:f9eeca106725	5903	#define RCC_DCKCFGR1_PLLSAIDIVR_1 0x00020000U
Kojto	122:f9eeca106725	5904
Kojto	122:f9eeca106725	5905	#define RCC_DCKCFGR1_SAI1SEL 0x00300000U
Kojto	122:f9eeca106725	5906	#define RCC_DCKCFGR1_SAI1SEL_0 0x00100000U
Kojto	122:f9eeca106725	5907	#define RCC_DCKCFGR1_SAI1SEL_1 0x00200000U
Kojto	122:f9eeca106725	5908
Kojto	122:f9eeca106725	5909	#define RCC_DCKCFGR1_SAI2SEL 0x00C00000U
Kojto	122:f9eeca106725	5910	#define RCC_DCKCFGR1_SAI2SEL_0 0x00400000U
Kojto	122:f9eeca106725	5911	#define RCC_DCKCFGR1_SAI2SEL_1 0x00800000U
Kojto	122:f9eeca106725	5912
Kojto	122:f9eeca106725	5913	#define RCC_DCKCFGR1_TIMPRE 0x01000000U
Kojto	107:4f6c30876dfa	5914
Kojto	107:4f6c30876dfa	5915	/****************** Bit definition for RCC_DCKCFGR2 register *************/
Kojto	122:f9eeca106725	5916	#define RCC_DCKCFGR2_USART1SEL 0x00000003U
Kojto	122:f9eeca106725	5917	#define RCC_DCKCFGR2_USART1SEL_0 0x00000001U
Kojto	122:f9eeca106725	5918	#define RCC_DCKCFGR2_USART1SEL_1 0x00000002U
Kojto	122:f9eeca106725	5919	#define RCC_DCKCFGR2_USART2SEL 0x0000000CU
Kojto	122:f9eeca106725	5920	#define RCC_DCKCFGR2_USART2SEL_0 0x00000004U
Kojto	122:f9eeca106725	5921	#define RCC_DCKCFGR2_USART2SEL_1 0x00000008U
Kojto	122:f9eeca106725	5922	#define RCC_DCKCFGR2_USART3SEL 0x00000030U
Kojto	122:f9eeca106725	5923	#define RCC_DCKCFGR2_USART3SEL_0 0x00000010U
Kojto	122:f9eeca106725	5924	#define RCC_DCKCFGR2_USART3SEL_1 0x00000020U
Kojto	122:f9eeca106725	5925	#define RCC_DCKCFGR2_UART4SEL 0x000000C0U
Kojto	122:f9eeca106725	5926	#define RCC_DCKCFGR2_UART4SEL_0 0x00000040U
Kojto	122:f9eeca106725	5927	#define RCC_DCKCFGR2_UART4SEL_1 0x00000080U
Kojto	122:f9eeca106725	5928	#define RCC_DCKCFGR2_UART5SEL 0x00000300U
Kojto	122:f9eeca106725	5929	#define RCC_DCKCFGR2_UART5SEL_0 0x00000100U
Kojto	122:f9eeca106725	5930	#define RCC_DCKCFGR2_UART5SEL_1 0x00000200U
Kojto	122:f9eeca106725	5931	#define RCC_DCKCFGR2_USART6SEL 0x00000C00U
Kojto	122:f9eeca106725	5932	#define RCC_DCKCFGR2_USART6SEL_0 0x00000400U
Kojto	122:f9eeca106725	5933	#define RCC_DCKCFGR2_USART6SEL_1 0x00000800U
Kojto	122:f9eeca106725	5934	#define RCC_DCKCFGR2_UART7SEL 0x00003000U
Kojto	122:f9eeca106725	5935	#define RCC_DCKCFGR2_UART7SEL_0 0x00001000U
Kojto	122:f9eeca106725	5936	#define RCC_DCKCFGR2_UART7SEL_1 0x00002000U
Kojto	122:f9eeca106725	5937	#define RCC_DCKCFGR2_UART8SEL 0x0000C000U
Kojto	122:f9eeca106725	5938	#define RCC_DCKCFGR2_UART8SEL_0 0x00004000U
Kojto	122:f9eeca106725	5939	#define RCC_DCKCFGR2_UART8SEL_1 0x00008000U
Kojto	122:f9eeca106725	5940	#define RCC_DCKCFGR2_I2C1SEL 0x00030000U
Kojto	122:f9eeca106725	5941	#define RCC_DCKCFGR2_I2C1SEL_0 0x00010000U
Kojto	122:f9eeca106725	5942	#define RCC_DCKCFGR2_I2C1SEL_1 0x00020000U
Kojto	122:f9eeca106725	5943	#define RCC_DCKCFGR2_I2C2SEL 0x000C0000U
Kojto	122:f9eeca106725	5944	#define RCC_DCKCFGR2_I2C2SEL_0 0x00040000U
Kojto	122:f9eeca106725	5945	#define RCC_DCKCFGR2_I2C2SEL_1 0x00080000U
Kojto	122:f9eeca106725	5946	#define RCC_DCKCFGR2_I2C3SEL 0x00300000U
Kojto	122:f9eeca106725	5947	#define RCC_DCKCFGR2_I2C3SEL_0 0x00100000U
Kojto	122:f9eeca106725	5948	#define RCC_DCKCFGR2_I2C3SEL_1 0x00200000U
Kojto	122:f9eeca106725	5949	#define RCC_DCKCFGR2_I2C4SEL 0x00C00000U
Kojto	122:f9eeca106725	5950	#define RCC_DCKCFGR2_I2C4SEL_0 0x00400000U
Kojto	122:f9eeca106725	5951	#define RCC_DCKCFGR2_I2C4SEL_1 0x00800000U
Kojto	122:f9eeca106725	5952	#define RCC_DCKCFGR2_LPTIM1SEL 0x03000000U
Kojto	122:f9eeca106725	5953	#define RCC_DCKCFGR2_LPTIM1SEL_0 0x01000000U
Kojto	122:f9eeca106725	5954	#define RCC_DCKCFGR2_LPTIM1SEL_1 0x02000000U
Kojto	122:f9eeca106725	5955	#define RCC_DCKCFGR2_CECSEL 0x04000000U
Kojto	122:f9eeca106725	5956	#define RCC_DCKCFGR2_CK48MSEL 0x08000000U
Kojto	122:f9eeca106725	5957	#define RCC_DCKCFGR2_SDMMC1SEL 0x10000000U
Kojto	107:4f6c30876dfa	5958
Kojto	107:4f6c30876dfa	5959	/******************************************************************************/
Kojto	107:4f6c30876dfa	5960	/* */
Kojto	107:4f6c30876dfa	5961	/* RNG */
Kojto	107:4f6c30876dfa	5962	/* */
Kojto	107:4f6c30876dfa	5963	/******************************************************************************/
Kojto	107:4f6c30876dfa	5964	/****************** Bits definition for RNG_CR register *****************/
Kojto	122:f9eeca106725	5965	#define RNG_CR_RNGEN 0x00000004U
Kojto	122:f9eeca106725	5966	#define RNG_CR_IE 0x00000008U
Kojto	107:4f6c30876dfa	5967
Kojto	107:4f6c30876dfa	5968	/****************** Bits definition for RNG_SR register *****************/
Kojto	122:f9eeca106725	5969	#define RNG_SR_DRDY 0x00000001U
Kojto	122:f9eeca106725	5970	#define RNG_SR_CECS 0x00000002U
Kojto	122:f9eeca106725	5971	#define RNG_SR_SECS 0x00000004U
Kojto	122:f9eeca106725	5972	#define RNG_SR_CEIS 0x00000020U
Kojto	122:f9eeca106725	5973	#define RNG_SR_SEIS 0x00000040U
Kojto	107:4f6c30876dfa	5974
Kojto	107:4f6c30876dfa	5975	/******************************************************************************/
Kojto	107:4f6c30876dfa	5976	/* */
Kojto	107:4f6c30876dfa	5977	/* Real-Time Clock (RTC) */
Kojto	107:4f6c30876dfa	5978	/* */
Kojto	107:4f6c30876dfa	5979	/******************************************************************************/
Kojto	107:4f6c30876dfa	5980	/****************** Bits definition for RTC_TR register *****************/
Kojto	122:f9eeca106725	5981	#define RTC_TR_PM 0x00400000U
Kojto	122:f9eeca106725	5982	#define RTC_TR_HT 0x00300000U
Kojto	122:f9eeca106725	5983	#define RTC_TR_HT_0 0x00100000U
Kojto	122:f9eeca106725	5984	#define RTC_TR_HT_1 0x00200000U
Kojto	122:f9eeca106725	5985	#define RTC_TR_HU 0x000F0000U
Kojto	122:f9eeca106725	5986	#define RTC_TR_HU_0 0x00010000U
Kojto	122:f9eeca106725	5987	#define RTC_TR_HU_1 0x00020000U
Kojto	122:f9eeca106725	5988	#define RTC_TR_HU_2 0x00040000U
Kojto	122:f9eeca106725	5989	#define RTC_TR_HU_3 0x00080000U
Kojto	122:f9eeca106725	5990	#define RTC_TR_MNT 0x00007000U
Kojto	122:f9eeca106725	5991	#define RTC_TR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	5992	#define RTC_TR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	5993	#define RTC_TR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	5994	#define RTC_TR_MNU 0x00000F00U
Kojto	122:f9eeca106725	5995	#define RTC_TR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	5996	#define RTC_TR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	5997	#define RTC_TR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	5998	#define RTC_TR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	5999	#define RTC_TR_ST 0x00000070U
Kojto	122:f9eeca106725	6000	#define RTC_TR_ST_0 0x00000010U
Kojto	122:f9eeca106725	6001	#define RTC_TR_ST_1 0x00000020U
Kojto	122:f9eeca106725	6002	#define RTC_TR_ST_2 0x00000040U
Kojto	122:f9eeca106725	6003	#define RTC_TR_SU 0x0000000FU
Kojto	122:f9eeca106725	6004	#define RTC_TR_SU_0 0x00000001U
Kojto	122:f9eeca106725	6005	#define RTC_TR_SU_1 0x00000002U
Kojto	122:f9eeca106725	6006	#define RTC_TR_SU_2 0x00000004U
Kojto	122:f9eeca106725	6007	#define RTC_TR_SU_3 0x00000008U
Kojto	107:4f6c30876dfa	6008
Kojto	107:4f6c30876dfa	6009	/****************** Bits definition for RTC_DR register *****************/
Kojto	122:f9eeca106725	6010	#define RTC_DR_YT 0x00F00000U
Kojto	122:f9eeca106725	6011	#define RTC_DR_YT_0 0x00100000U
Kojto	122:f9eeca106725	6012	#define RTC_DR_YT_1 0x00200000U
Kojto	122:f9eeca106725	6013	#define RTC_DR_YT_2 0x00400000U
Kojto	122:f9eeca106725	6014	#define RTC_DR_YT_3 0x00800000U
Kojto	122:f9eeca106725	6015	#define RTC_DR_YU 0x000F0000U
Kojto	122:f9eeca106725	6016	#define RTC_DR_YU_0 0x00010000U
Kojto	122:f9eeca106725	6017	#define RTC_DR_YU_1 0x00020000U
Kojto	122:f9eeca106725	6018	#define RTC_DR_YU_2 0x00040000U
Kojto	122:f9eeca106725	6019	#define RTC_DR_YU_3 0x00080000U
Kojto	122:f9eeca106725	6020	#define RTC_DR_WDU 0x0000E000U
Kojto	122:f9eeca106725	6021	#define RTC_DR_WDU_0 0x00002000U
Kojto	122:f9eeca106725	6022	#define RTC_DR_WDU_1 0x00004000U
Kojto	122:f9eeca106725	6023	#define RTC_DR_WDU_2 0x00008000U
Kojto	122:f9eeca106725	6024	#define RTC_DR_MT 0x00001000U
Kojto	122:f9eeca106725	6025	#define RTC_DR_MU 0x00000F00U
Kojto	122:f9eeca106725	6026	#define RTC_DR_MU_0 0x00000100U
Kojto	122:f9eeca106725	6027	#define RTC_DR_MU_1 0x00000200U
Kojto	122:f9eeca106725	6028	#define RTC_DR_MU_2 0x00000400U
Kojto	122:f9eeca106725	6029	#define RTC_DR_MU_3 0x00000800U
Kojto	122:f9eeca106725	6030	#define RTC_DR_DT 0x00000030U
Kojto	122:f9eeca106725	6031	#define RTC_DR_DT_0 0x00000010U
Kojto	122:f9eeca106725	6032	#define RTC_DR_DT_1 0x00000020U
Kojto	122:f9eeca106725	6033	#define RTC_DR_DU 0x0000000FU
Kojto	122:f9eeca106725	6034	#define RTC_DR_DU_0 0x00000001U
Kojto	122:f9eeca106725	6035	#define RTC_DR_DU_1 0x00000002U
Kojto	122:f9eeca106725	6036	#define RTC_DR_DU_2 0x00000004U
Kojto	122:f9eeca106725	6037	#define RTC_DR_DU_3 0x00000008U
Kojto	107:4f6c30876dfa	6038
Kojto	107:4f6c30876dfa	6039	/****************** Bits definition for RTC_CR register *****************/
Kojto	122:f9eeca106725	6040	#define RTC_CR_ITSE 0x01000000U
Kojto	122:f9eeca106725	6041	#define RTC_CR_COE 0x00800000U
Kojto	122:f9eeca106725	6042	#define RTC_CR_OSEL 0x00600000U
Kojto	122:f9eeca106725	6043	#define RTC_CR_OSEL_0 0x00200000U
Kojto	122:f9eeca106725	6044	#define RTC_CR_OSEL_1 0x00400000U
Kojto	122:f9eeca106725	6045	#define RTC_CR_POL 0x00100000U
Kojto	122:f9eeca106725	6046	#define RTC_CR_COSEL 0x00080000U
Kojto	122:f9eeca106725	6047	#define RTC_CR_BCK 0x00040000U
Kojto	122:f9eeca106725	6048	#define RTC_CR_SUB1H 0x00020000U
Kojto	122:f9eeca106725	6049	#define RTC_CR_ADD1H 0x00010000U
Kojto	122:f9eeca106725	6050	#define RTC_CR_TSIE 0x00008000U
Kojto	122:f9eeca106725	6051	#define RTC_CR_WUTIE 0x00004000U
Kojto	122:f9eeca106725	6052	#define RTC_CR_ALRBIE 0x00002000U
Kojto	122:f9eeca106725	6053	#define RTC_CR_ALRAIE 0x00001000U
Kojto	122:f9eeca106725	6054	#define RTC_CR_TSE 0x00000800U
Kojto	122:f9eeca106725	6055	#define RTC_CR_WUTE 0x00000400U
Kojto	122:f9eeca106725	6056	#define RTC_CR_ALRBE 0x00000200U
Kojto	122:f9eeca106725	6057	#define RTC_CR_ALRAE 0x00000100U
Kojto	122:f9eeca106725	6058	#define RTC_CR_FMT 0x00000040U
Kojto	122:f9eeca106725	6059	#define RTC_CR_BYPSHAD 0x00000020U
Kojto	122:f9eeca106725	6060	#define RTC_CR_REFCKON 0x00000010U
Kojto	122:f9eeca106725	6061	#define RTC_CR_TSEDGE 0x00000008U
Kojto	122:f9eeca106725	6062	#define RTC_CR_WUCKSEL 0x00000007U
Kojto	122:f9eeca106725	6063	#define RTC_CR_WUCKSEL_0 0x00000001U
Kojto	122:f9eeca106725	6064	#define RTC_CR_WUCKSEL_1 0x00000002U
Kojto	122:f9eeca106725	6065	#define RTC_CR_WUCKSEL_2 0x00000004U
Kojto	107:4f6c30876dfa	6066
Kojto	107:4f6c30876dfa	6067	/****************** Bits definition for RTC_ISR register ****************/
Kojto	122:f9eeca106725	6068	#define RTC_ISR_ITSF 0x00020000U
Kojto	122:f9eeca106725	6069	#define RTC_ISR_RECALPF 0x00010000U
Kojto	122:f9eeca106725	6070	#define RTC_ISR_TAMP3F 0x00008000U
Kojto	122:f9eeca106725	6071	#define RTC_ISR_TAMP2F 0x00004000U
Kojto	122:f9eeca106725	6072	#define RTC_ISR_TAMP1F 0x00002000U
Kojto	122:f9eeca106725	6073	#define RTC_ISR_TSOVF 0x00001000U
Kojto	122:f9eeca106725	6074	#define RTC_ISR_TSF 0x00000800U
Kojto	122:f9eeca106725	6075	#define RTC_ISR_WUTF 0x00000400U
Kojto	122:f9eeca106725	6076	#define RTC_ISR_ALRBF 0x00000200U
Kojto	122:f9eeca106725	6077	#define RTC_ISR_ALRAF 0x00000100U
Kojto	122:f9eeca106725	6078	#define RTC_ISR_INIT 0x00000080U
Kojto	122:f9eeca106725	6079	#define RTC_ISR_INITF 0x00000040U
Kojto	122:f9eeca106725	6080	#define RTC_ISR_RSF 0x00000020U
Kojto	122:f9eeca106725	6081	#define RTC_ISR_INITS 0x00000010U
Kojto	122:f9eeca106725	6082	#define RTC_ISR_SHPF 0x00000008U
Kojto	122:f9eeca106725	6083	#define RTC_ISR_WUTWF 0x00000004U
Kojto	122:f9eeca106725	6084	#define RTC_ISR_ALRBWF 0x00000002U
Kojto	122:f9eeca106725	6085	#define RTC_ISR_ALRAWF 0x00000001U
Kojto	107:4f6c30876dfa	6086
Kojto	107:4f6c30876dfa	6087	/****************** Bits definition for RTC_PRER register ***************/
Kojto	122:f9eeca106725	6088	#define RTC_PRER_PREDIV_A 0x007F0000U
Kojto	122:f9eeca106725	6089	#define RTC_PRER_PREDIV_S 0x00007FFFU
Kojto	107:4f6c30876dfa	6090
Kojto	107:4f6c30876dfa	6091	/****************** Bits definition for RTC_WUTR register ***************/
Kojto	122:f9eeca106725	6092	#define RTC_WUTR_WUT 0x0000FFFFU
Kojto	107:4f6c30876dfa	6093
Kojto	107:4f6c30876dfa	6094	/****************** Bits definition for RTC_ALRMAR register *************/
Kojto	122:f9eeca106725	6095	#define RTC_ALRMAR_MSK4 0x80000000U
Kojto	122:f9eeca106725	6096	#define RTC_ALRMAR_WDSEL 0x40000000U
Kojto	122:f9eeca106725	6097	#define RTC_ALRMAR_DT 0x30000000U
Kojto	122:f9eeca106725	6098	#define RTC_ALRMAR_DT_0 0x10000000U
Kojto	122:f9eeca106725	6099	#define RTC_ALRMAR_DT_1 0x20000000U
Kojto	122:f9eeca106725	6100	#define RTC_ALRMAR_DU 0x0F000000U
Kojto	122:f9eeca106725	6101	#define RTC_ALRMAR_DU_0 0x01000000U
Kojto	122:f9eeca106725	6102	#define RTC_ALRMAR_DU_1 0x02000000U
Kojto	122:f9eeca106725	6103	#define RTC_ALRMAR_DU_2 0x04000000U
Kojto	122:f9eeca106725	6104	#define RTC_ALRMAR_DU_3 0x08000000U
Kojto	122:f9eeca106725	6105	#define RTC_ALRMAR_MSK3 0x00800000U
Kojto	122:f9eeca106725	6106	#define RTC_ALRMAR_PM 0x00400000U
Kojto	122:f9eeca106725	6107	#define RTC_ALRMAR_HT 0x00300000U
Kojto	122:f9eeca106725	6108	#define RTC_ALRMAR_HT_0 0x00100000U
Kojto	122:f9eeca106725	6109	#define RTC_ALRMAR_HT_1 0x00200000U
Kojto	122:f9eeca106725	6110	#define RTC_ALRMAR_HU 0x000F0000U
Kojto	122:f9eeca106725	6111	#define RTC_ALRMAR_HU_0 0x00010000U
Kojto	122:f9eeca106725	6112	#define RTC_ALRMAR_HU_1 0x00020000U
Kojto	122:f9eeca106725	6113	#define RTC_ALRMAR_HU_2 0x00040000U
Kojto	122:f9eeca106725	6114	#define RTC_ALRMAR_HU_3 0x00080000U
Kojto	122:f9eeca106725	6115	#define RTC_ALRMAR_MSK2 0x00008000U
Kojto	122:f9eeca106725	6116	#define RTC_ALRMAR_MNT 0x00007000U
Kojto	122:f9eeca106725	6117	#define RTC_ALRMAR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	6118	#define RTC_ALRMAR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	6119	#define RTC_ALRMAR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	6120	#define RTC_ALRMAR_MNU 0x00000F00U
Kojto	122:f9eeca106725	6121	#define RTC_ALRMAR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	6122	#define RTC_ALRMAR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	6123	#define RTC_ALRMAR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	6124	#define RTC_ALRMAR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	6125	#define RTC_ALRMAR_MSK1 0x00000080U
Kojto	122:f9eeca106725	6126	#define RTC_ALRMAR_ST 0x00000070U
Kojto	122:f9eeca106725	6127	#define RTC_ALRMAR_ST_0 0x00000010U
Kojto	122:f9eeca106725	6128	#define RTC_ALRMAR_ST_1 0x00000020U
Kojto	122:f9eeca106725	6129	#define RTC_ALRMAR_ST_2 0x00000040U
Kojto	122:f9eeca106725	6130	#define RTC_ALRMAR_SU 0x0000000FU
Kojto	122:f9eeca106725	6131	#define RTC_ALRMAR_SU_0 0x00000001U
Kojto	122:f9eeca106725	6132	#define RTC_ALRMAR_SU_1 0x00000002U
Kojto	122:f9eeca106725	6133	#define RTC_ALRMAR_SU_2 0x00000004U
Kojto	122:f9eeca106725	6134	#define RTC_ALRMAR_SU_3 0x00000008U
Kojto	107:4f6c30876dfa	6135
Kojto	107:4f6c30876dfa	6136	/****************** Bits definition for RTC_ALRMBR register *************/
Kojto	122:f9eeca106725	6137	#define RTC_ALRMBR_MSK4 0x80000000U
Kojto	122:f9eeca106725	6138	#define RTC_ALRMBR_WDSEL 0x40000000U
Kojto	122:f9eeca106725	6139	#define RTC_ALRMBR_DT 0x30000000U
Kojto	122:f9eeca106725	6140	#define RTC_ALRMBR_DT_0 0x10000000U
Kojto	122:f9eeca106725	6141	#define RTC_ALRMBR_DT_1 0x20000000U
Kojto	122:f9eeca106725	6142	#define RTC_ALRMBR_DU 0x0F000000U
Kojto	122:f9eeca106725	6143	#define RTC_ALRMBR_DU_0 0x01000000U
Kojto	122:f9eeca106725	6144	#define RTC_ALRMBR_DU_1 0x02000000U
Kojto	122:f9eeca106725	6145	#define RTC_ALRMBR_DU_2 0x04000000U
Kojto	122:f9eeca106725	6146	#define RTC_ALRMBR_DU_3 0x08000000U
Kojto	122:f9eeca106725	6147	#define RTC_ALRMBR_MSK3 0x00800000U
Kojto	122:f9eeca106725	6148	#define RTC_ALRMBR_PM 0x00400000U
Kojto	122:f9eeca106725	6149	#define RTC_ALRMBR_HT 0x00300000U
Kojto	122:f9eeca106725	6150	#define RTC_ALRMBR_HT_0 0x00100000U
Kojto	122:f9eeca106725	6151	#define RTC_ALRMBR_HT_1 0x00200000U
Kojto	122:f9eeca106725	6152	#define RTC_ALRMBR_HU 0x000F0000U
Kojto	122:f9eeca106725	6153	#define RTC_ALRMBR_HU_0 0x00010000U
Kojto	122:f9eeca106725	6154	#define RTC_ALRMBR_HU_1 0x00020000U
Kojto	122:f9eeca106725	6155	#define RTC_ALRMBR_HU_2 0x00040000U
Kojto	122:f9eeca106725	6156	#define RTC_ALRMBR_HU_3 0x00080000U
Kojto	122:f9eeca106725	6157	#define RTC_ALRMBR_MSK2 0x00008000U
Kojto	122:f9eeca106725	6158	#define RTC_ALRMBR_MNT 0x00007000U
Kojto	122:f9eeca106725	6159	#define RTC_ALRMBR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	6160	#define RTC_ALRMBR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	6161	#define RTC_ALRMBR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	6162	#define RTC_ALRMBR_MNU 0x00000F00U
Kojto	122:f9eeca106725	6163	#define RTC_ALRMBR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	6164	#define RTC_ALRMBR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	6165	#define RTC_ALRMBR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	6166	#define RTC_ALRMBR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	6167	#define RTC_ALRMBR_MSK1 0x00000080U
Kojto	122:f9eeca106725	6168	#define RTC_ALRMBR_ST 0x00000070U
Kojto	122:f9eeca106725	6169	#define RTC_ALRMBR_ST_0 0x00000010U
Kojto	122:f9eeca106725	6170	#define RTC_ALRMBR_ST_1 0x00000020U
Kojto	122:f9eeca106725	6171	#define RTC_ALRMBR_ST_2 0x00000040U
Kojto	122:f9eeca106725	6172	#define RTC_ALRMBR_SU 0x0000000FU
Kojto	122:f9eeca106725	6173	#define RTC_ALRMBR_SU_0 0x00000001U
Kojto	122:f9eeca106725	6174	#define RTC_ALRMBR_SU_1 0x00000002U
Kojto	122:f9eeca106725	6175	#define RTC_ALRMBR_SU_2 0x00000004U
Kojto	122:f9eeca106725	6176	#define RTC_ALRMBR_SU_3 0x00000008U
Kojto	107:4f6c30876dfa	6177
Kojto	107:4f6c30876dfa	6178	/****************** Bits definition for RTC_WPR register ****************/
Kojto	122:f9eeca106725	6179	#define RTC_WPR_KEY 0x000000FFU
Kojto	107:4f6c30876dfa	6180
Kojto	107:4f6c30876dfa	6181	/****************** Bits definition for RTC_SSR register ****************/
Kojto	122:f9eeca106725	6182	#define RTC_SSR_SS 0x0000FFFFU
Kojto	107:4f6c30876dfa	6183
Kojto	107:4f6c30876dfa	6184	/****************** Bits definition for RTC_SHIFTR register *************/
Kojto	122:f9eeca106725	6185	#define RTC_SHIFTR_SUBFS 0x00007FFFU
Kojto	122:f9eeca106725	6186	#define RTC_SHIFTR_ADD1S 0x80000000U
Kojto	107:4f6c30876dfa	6187
Kojto	107:4f6c30876dfa	6188	/****************** Bits definition for RTC_TSTR register ***************/
Kojto	122:f9eeca106725	6189	#define RTC_TSTR_PM 0x00400000U
Kojto	122:f9eeca106725	6190	#define RTC_TSTR_HT 0x00300000U
Kojto	122:f9eeca106725	6191	#define RTC_TSTR_HT_0 0x00100000U
Kojto	122:f9eeca106725	6192	#define RTC_TSTR_HT_1 0x00200000U
Kojto	122:f9eeca106725	6193	#define RTC_TSTR_HU 0x000F0000U
Kojto	122:f9eeca106725	6194	#define RTC_TSTR_HU_0 0x00010000U
Kojto	122:f9eeca106725	6195	#define RTC_TSTR_HU_1 0x00020000U
Kojto	122:f9eeca106725	6196	#define RTC_TSTR_HU_2 0x00040000U
Kojto	122:f9eeca106725	6197	#define RTC_TSTR_HU_3 0x00080000U
Kojto	122:f9eeca106725	6198	#define RTC_TSTR_MNT 0x00007000U
Kojto	122:f9eeca106725	6199	#define RTC_TSTR_MNT_0 0x00001000U
Kojto	122:f9eeca106725	6200	#define RTC_TSTR_MNT_1 0x00002000U
Kojto	122:f9eeca106725	6201	#define RTC_TSTR_MNT_2 0x00004000U
Kojto	122:f9eeca106725	6202	#define RTC_TSTR_MNU 0x00000F00U
Kojto	122:f9eeca106725	6203	#define RTC_TSTR_MNU_0 0x00000100U
Kojto	122:f9eeca106725	6204	#define RTC_TSTR_MNU_1 0x00000200U
Kojto	122:f9eeca106725	6205	#define RTC_TSTR_MNU_2 0x00000400U
Kojto	122:f9eeca106725	6206	#define RTC_TSTR_MNU_3 0x00000800U
Kojto	122:f9eeca106725	6207	#define RTC_TSTR_ST 0x00000070U
Kojto	122:f9eeca106725	6208	#define RTC_TSTR_ST_0 0x00000010U
Kojto	122:f9eeca106725	6209	#define RTC_TSTR_ST_1 0x00000020U
Kojto	122:f9eeca106725	6210	#define RTC_TSTR_ST_2 0x00000040U
Kojto	122:f9eeca106725	6211	#define RTC_TSTR_SU 0x0000000FU
Kojto	122:f9eeca106725	6212	#define RTC_TSTR_SU_0 0x00000001U
Kojto	122:f9eeca106725	6213	#define RTC_TSTR_SU_1 0x00000002U
Kojto	122:f9eeca106725	6214	#define RTC_TSTR_SU_2 0x00000004U
Kojto	122:f9eeca106725	6215	#define RTC_TSTR_SU_3 0x00000008U
Kojto	107:4f6c30876dfa	6216
Kojto	107:4f6c30876dfa	6217	/****************** Bits definition for RTC_TSDR register ***************/
Kojto	122:f9eeca106725	6218	#define RTC_TSDR_WDU 0x0000E000U
Kojto	122:f9eeca106725	6219	#define RTC_TSDR_WDU_0 0x00002000U
Kojto	122:f9eeca106725	6220	#define RTC_TSDR_WDU_1 0x00004000U
Kojto	122:f9eeca106725	6221	#define RTC_TSDR_WDU_2 0x00008000U
Kojto	122:f9eeca106725	6222	#define RTC_TSDR_MT 0x00001000U
Kojto	122:f9eeca106725	6223	#define RTC_TSDR_MU 0x00000F00U
Kojto	122:f9eeca106725	6224	#define RTC_TSDR_MU_0 0x00000100U
Kojto	122:f9eeca106725	6225	#define RTC_TSDR_MU_1 0x00000200U
Kojto	122:f9eeca106725	6226	#define RTC_TSDR_MU_2 0x00000400U
Kojto	122:f9eeca106725	6227	#define RTC_TSDR_MU_3 0x00000800U
Kojto	122:f9eeca106725	6228	#define RTC_TSDR_DT 0x00000030U
Kojto	122:f9eeca106725	6229	#define RTC_TSDR_DT_0 0x00000010U
Kojto	122:f9eeca106725	6230	#define RTC_TSDR_DT_1 0x00000020U
Kojto	122:f9eeca106725	6231	#define RTC_TSDR_DU 0x0000000FU
Kojto	122:f9eeca106725	6232	#define RTC_TSDR_DU_0 0x00000001U
Kojto	122:f9eeca106725	6233	#define RTC_TSDR_DU_1 0x00000002U
Kojto	122:f9eeca106725	6234	#define RTC_TSDR_DU_2 0x00000004U
Kojto	122:f9eeca106725	6235	#define RTC_TSDR_DU_3 0x00000008U
Kojto	107:4f6c30876dfa	6236
Kojto	107:4f6c30876dfa	6237	/****************** Bits definition for RTC_TSSSR register **************/
Kojto	122:f9eeca106725	6238	#define RTC_TSSSR_SS 0x0000FFFFU
Kojto	107:4f6c30876dfa	6239
Kojto	107:4f6c30876dfa	6240	/****************** Bits definition for RTC_CAL register ***************/
Kojto	122:f9eeca106725	6241	#define RTC_CALR_CALP 0x00008000U
Kojto	122:f9eeca106725	6242	#define RTC_CALR_CALW8 0x00004000U
Kojto	122:f9eeca106725	6243	#define RTC_CALR_CALW16 0x00002000U
Kojto	122:f9eeca106725	6244	#define RTC_CALR_CALM 0x000001FFU
Kojto	122:f9eeca106725	6245	#define RTC_CALR_CALM_0 0x00000001U
Kojto	122:f9eeca106725	6246	#define RTC_CALR_CALM_1 0x00000002U
Kojto	122:f9eeca106725	6247	#define RTC_CALR_CALM_2 0x00000004U
Kojto	122:f9eeca106725	6248	#define RTC_CALR_CALM_3 0x00000008U
Kojto	122:f9eeca106725	6249	#define RTC_CALR_CALM_4 0x00000010U
Kojto	122:f9eeca106725	6250	#define RTC_CALR_CALM_5 0x00000020U
Kojto	122:f9eeca106725	6251	#define RTC_CALR_CALM_6 0x00000040U
Kojto	122:f9eeca106725	6252	#define RTC_CALR_CALM_7 0x00000080U
Kojto	122:f9eeca106725	6253	#define RTC_CALR_CALM_8 0x00000100U
Kojto	107:4f6c30876dfa	6254
Kojto	107:4f6c30876dfa	6255	/****************** Bits definition for RTC_TAMPCR register **************/
Kojto	122:f9eeca106725	6256	#define RTC_TAMPCR_TAMP3MF 0x01000000U
Kojto	122:f9eeca106725	6257	#define RTC_TAMPCR_TAMP3NOERASE 0x00800000U
Kojto	122:f9eeca106725	6258	#define RTC_TAMPCR_TAMP3IE 0x00400000U
Kojto	122:f9eeca106725	6259	#define RTC_TAMPCR_TAMP2MF 0x00200000U
Kojto	122:f9eeca106725	6260	#define RTC_TAMPCR_TAMP2NOERASE 0x00100000U
Kojto	122:f9eeca106725	6261	#define RTC_TAMPCR_TAMP2IE 0x00080000U
Kojto	122:f9eeca106725	6262	#define RTC_TAMPCR_TAMP1MF 0x00040000U
Kojto	122:f9eeca106725	6263	#define RTC_TAMPCR_TAMP1NOERASE 0x00020000U
Kojto	122:f9eeca106725	6264	#define RTC_TAMPCR_TAMP1IE 0x00010000U
Kojto	122:f9eeca106725	6265	#define RTC_TAMPCR_TAMPPUDIS 0x00008000U
Kojto	122:f9eeca106725	6266	#define RTC_TAMPCR_TAMPPRCH 0x00006000U
Kojto	122:f9eeca106725	6267	#define RTC_TAMPCR_TAMPPRCH_0 0x00002000U
Kojto	122:f9eeca106725	6268	#define RTC_TAMPCR_TAMPPRCH_1 0x00004000U
Kojto	122:f9eeca106725	6269	#define RTC_TAMPCR_TAMPFLT 0x00001800U
Kojto	122:f9eeca106725	6270	#define RTC_TAMPCR_TAMPFLT_0 0x00000800U
Kojto	122:f9eeca106725	6271	#define RTC_TAMPCR_TAMPFLT_1 0x00001000U
Kojto	122:f9eeca106725	6272	#define RTC_TAMPCR_TAMPFREQ 0x00000700U
Kojto	122:f9eeca106725	6273	#define RTC_TAMPCR_TAMPFREQ_0 0x00000100U
Kojto	122:f9eeca106725	6274	#define RTC_TAMPCR_TAMPFREQ_1 0x00000200U
Kojto	122:f9eeca106725	6275	#define RTC_TAMPCR_TAMPFREQ_2 0x00000400U
Kojto	122:f9eeca106725	6276	#define RTC_TAMPCR_TAMPTS 0x00000080U
Kojto	122:f9eeca106725	6277	#define RTC_TAMPCR_TAMP3TRG 0x00000040U
Kojto	122:f9eeca106725	6278	#define RTC_TAMPCR_TAMP3E 0x00000020U
Kojto	122:f9eeca106725	6279	#define RTC_TAMPCR_TAMP2TRG 0x00000010U
Kojto	122:f9eeca106725	6280	#define RTC_TAMPCR_TAMP2E 0x00000008U
Kojto	122:f9eeca106725	6281	#define RTC_TAMPCR_TAMPIE 0x00000004U
Kojto	122:f9eeca106725	6282	#define RTC_TAMPCR_TAMP1TRG 0x00000002U
Kojto	122:f9eeca106725	6283	#define RTC_TAMPCR_TAMP1E 0x00000001U
Kojto	122:f9eeca106725	6284
Kojto	122:f9eeca106725	6285	/* Legacy defines */
Kojto	122:f9eeca106725	6286	#define RTC_TAMPCR_TAMP3_TRG RTC_TAMPCR_TAMP3TRG
Kojto	122:f9eeca106725	6287	#define RTC_TAMPCR_TAMP2_TRG RTC_TAMPCR_TAMP2TRG
Kojto	122:f9eeca106725	6288	#define RTC_TAMPCR_TAMP1_TRG RTC_TAMPCR_TAMP1TRG
Kojto	107:4f6c30876dfa	6289
Kojto	107:4f6c30876dfa	6290	/****************** Bits definition for RTC_ALRMASSR register ***********/
Kojto	122:f9eeca106725	6291	#define RTC_ALRMASSR_MASKSS 0x0F000000U
Kojto	122:f9eeca106725	6292	#define RTC_ALRMASSR_MASKSS_0 0x01000000U
Kojto	122:f9eeca106725	6293	#define RTC_ALRMASSR_MASKSS_1 0x02000000U
Kojto	122:f9eeca106725	6294	#define RTC_ALRMASSR_MASKSS_2 0x04000000U
Kojto	122:f9eeca106725	6295	#define RTC_ALRMASSR_MASKSS_3 0x08000000U
Kojto	122:f9eeca106725	6296	#define RTC_ALRMASSR_SS 0x00007FFFU
Kojto	107:4f6c30876dfa	6297
Kojto	107:4f6c30876dfa	6298	/****************** Bits definition for RTC_ALRMBSSR register ***********/
Kojto	122:f9eeca106725	6299	#define RTC_ALRMBSSR_MASKSS 0x0F000000U
Kojto	122:f9eeca106725	6300	#define RTC_ALRMBSSR_MASKSS_0 0x01000000U
Kojto	122:f9eeca106725	6301	#define RTC_ALRMBSSR_MASKSS_1 0x02000000U
Kojto	122:f9eeca106725	6302	#define RTC_ALRMBSSR_MASKSS_2 0x04000000U
Kojto	122:f9eeca106725	6303	#define RTC_ALRMBSSR_MASKSS_3 0x08000000U
Kojto	122:f9eeca106725	6304	#define RTC_ALRMBSSR_SS 0x00007FFFU
Kojto	107:4f6c30876dfa	6305
Kojto	107:4f6c30876dfa	6306	/****************** Bits definition for RTC_OR register **************/
Kojto	122:f9eeca106725	6307	#define RTC_OR_TSINSEL 0x00000006U
Kojto	122:f9eeca106725	6308	#define RTC_OR_TSINSEL_0 0x00000002U
Kojto	122:f9eeca106725	6309	#define RTC_OR_TSINSEL_1 0x00000004U
Kojto	122:f9eeca106725	6310	#define RTC_OR_ALARMTYPE 0x00000008U
Kojto	107:4f6c30876dfa	6311
Kojto	107:4f6c30876dfa	6312	/****************** Bits definition for RTC_BKP0R register **************/
Kojto	122:f9eeca106725	6313	#define RTC_BKP0R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6314
Kojto	107:4f6c30876dfa	6315	/****************** Bits definition for RTC_BKP1R register **************/
Kojto	122:f9eeca106725	6316	#define RTC_BKP1R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6317
Kojto	107:4f6c30876dfa	6318	/****************** Bits definition for RTC_BKP2R register **************/
Kojto	122:f9eeca106725	6319	#define RTC_BKP2R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6320
Kojto	107:4f6c30876dfa	6321	/****************** Bits definition for RTC_BKP3R register **************/
Kojto	122:f9eeca106725	6322	#define RTC_BKP3R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6323
Kojto	107:4f6c30876dfa	6324	/****************** Bits definition for RTC_BKP4R register **************/
Kojto	122:f9eeca106725	6325	#define RTC_BKP4R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6326
Kojto	107:4f6c30876dfa	6327	/****************** Bits definition for RTC_BKP5R register **************/
Kojto	122:f9eeca106725	6328	#define RTC_BKP5R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6329
Kojto	107:4f6c30876dfa	6330	/****************** Bits definition for RTC_BKP6R register **************/
Kojto	122:f9eeca106725	6331	#define RTC_BKP6R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6332
Kojto	107:4f6c30876dfa	6333	/****************** Bits definition for RTC_BKP7R register **************/
Kojto	122:f9eeca106725	6334	#define RTC_BKP7R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6335
Kojto	107:4f6c30876dfa	6336	/****************** Bits definition for RTC_BKP8R register **************/
Kojto	122:f9eeca106725	6337	#define RTC_BKP8R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6338
Kojto	107:4f6c30876dfa	6339	/****************** Bits definition for RTC_BKP9R register **************/
Kojto	122:f9eeca106725	6340	#define RTC_BKP9R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6341
Kojto	107:4f6c30876dfa	6342	/****************** Bits definition for RTC_BKP10R register *************/
Kojto	122:f9eeca106725	6343	#define RTC_BKP10R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6344
Kojto	107:4f6c30876dfa	6345	/****************** Bits definition for RTC_BKP11R register *************/
Kojto	122:f9eeca106725	6346	#define RTC_BKP11R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6347
Kojto	107:4f6c30876dfa	6348	/****************** Bits definition for RTC_BKP12R register *************/
Kojto	122:f9eeca106725	6349	#define RTC_BKP12R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6350
Kojto	107:4f6c30876dfa	6351	/****************** Bits definition for RTC_BKP13R register *************/
Kojto	122:f9eeca106725	6352	#define RTC_BKP13R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6353
Kojto	107:4f6c30876dfa	6354	/****************** Bits definition for RTC_BKP14R register *************/
Kojto	122:f9eeca106725	6355	#define RTC_BKP14R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6356
Kojto	107:4f6c30876dfa	6357	/****************** Bits definition for RTC_BKP15R register *************/
Kojto	122:f9eeca106725	6358	#define RTC_BKP15R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6359
Kojto	107:4f6c30876dfa	6360	/****************** Bits definition for RTC_BKP16R register *************/
Kojto	122:f9eeca106725	6361	#define RTC_BKP16R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6362
Kojto	107:4f6c30876dfa	6363	/****************** Bits definition for RTC_BKP17R register *************/
Kojto	122:f9eeca106725	6364	#define RTC_BKP17R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6365
Kojto	107:4f6c30876dfa	6366	/****************** Bits definition for RTC_BKP18R register *************/
Kojto	122:f9eeca106725	6367	#define RTC_BKP18R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6368
Kojto	107:4f6c30876dfa	6369	/****************** Bits definition for RTC_BKP19R register *************/
Kojto	122:f9eeca106725	6370	#define RTC_BKP19R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6371
Kojto	107:4f6c30876dfa	6372	/****************** Bits definition for RTC_BKP20R register *************/
Kojto	122:f9eeca106725	6373	#define RTC_BKP20R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6374
Kojto	107:4f6c30876dfa	6375	/****************** Bits definition for RTC_BKP21R register *************/
Kojto	122:f9eeca106725	6376	#define RTC_BKP21R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6377
Kojto	107:4f6c30876dfa	6378	/****************** Bits definition for RTC_BKP22R register *************/
Kojto	122:f9eeca106725	6379	#define RTC_BKP22R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6380
Kojto	107:4f6c30876dfa	6381	/****************** Bits definition for RTC_BKP23R register *************/
Kojto	122:f9eeca106725	6382	#define RTC_BKP23R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6383
Kojto	107:4f6c30876dfa	6384	/****************** Bits definition for RTC_BKP24R register *************/
Kojto	122:f9eeca106725	6385	#define RTC_BKP24R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6386
Kojto	107:4f6c30876dfa	6387	/****************** Bits definition for RTC_BKP25R register *************/
Kojto	122:f9eeca106725	6388	#define RTC_BKP25R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6389
Kojto	107:4f6c30876dfa	6390	/****************** Bits definition for RTC_BKP26R register *************/
Kojto	122:f9eeca106725	6391	#define RTC_BKP26R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6392
Kojto	107:4f6c30876dfa	6393	/****************** Bits definition for RTC_BKP27R register *************/
Kojto	122:f9eeca106725	6394	#define RTC_BKP27R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6395
Kojto	107:4f6c30876dfa	6396	/****************** Bits definition for RTC_BKP28R register *************/
Kojto	122:f9eeca106725	6397	#define RTC_BKP28R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6398
Kojto	107:4f6c30876dfa	6399	/****************** Bits definition for RTC_BKP29R register *************/
Kojto	122:f9eeca106725	6400	#define RTC_BKP29R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6401
Kojto	107:4f6c30876dfa	6402	/****************** Bits definition for RTC_BKP30R register *************/
Kojto	122:f9eeca106725	6403	#define RTC_BKP30R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6404
Kojto	107:4f6c30876dfa	6405	/****************** Bits definition for RTC_BKP31R register *************/
Kojto	122:f9eeca106725	6406	#define RTC_BKP31R 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6407
Kojto	107:4f6c30876dfa	6408	/****************** Number of backup registers ****************************/
Kojto	122:f9eeca106725	6409	#define RTC_BKP_NUMBER 0x00000020U
Kojto	107:4f6c30876dfa	6410
Kojto	107:4f6c30876dfa	6411
Kojto	107:4f6c30876dfa	6412	/******************************************************************************/
Kojto	107:4f6c30876dfa	6413	/* */
Kojto	107:4f6c30876dfa	6414	/* Serial Audio Interface */
Kojto	107:4f6c30876dfa	6415	/* */
Kojto	107:4f6c30876dfa	6416	/******************************************************************************/
Kojto	107:4f6c30876dfa	6417	/****************** Bit definition for SAI_GCR register *****************/
Kojto	122:f9eeca106725	6418	#define SAI_GCR_SYNCIN 0x00000003U /!<SYNCIN[1:0] bits (Synchronization Inputs) /
Kojto	122:f9eeca106725	6419	#define SAI_GCR_SYNCIN_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	6420	#define SAI_GCR_SYNCIN_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	6421
Kojto	122:f9eeca106725	6422	#define SAI_GCR_SYNCOUT 0x00000030U /!<SYNCOUT[1:0] bits (Synchronization Outputs) /
Kojto	122:f9eeca106725	6423	#define SAI_GCR_SYNCOUT_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	6424	#define SAI_GCR_SYNCOUT_1 0x00000020U /!<Bit 1 /
Kojto	107:4f6c30876dfa	6425
Kojto	107:4f6c30876dfa	6426	/***************** Bit definition for SAI_xCR1 register *****************/
Kojto	122:f9eeca106725	6427	#define SAI_xCR1_MODE 0x00000003U /!<MODE[1:0] bits (Audio Block Mode) /
Kojto	122:f9eeca106725	6428	#define SAI_xCR1_MODE_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	6429	#define SAI_xCR1_MODE_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	6430
Kojto	122:f9eeca106725	6431	#define SAI_xCR1_PRTCFG 0x0000000CU /!<PRTCFG[1:0] bits (Protocol Configuration) /
Kojto	122:f9eeca106725	6432	#define SAI_xCR1_PRTCFG_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	6433	#define SAI_xCR1_PRTCFG_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	6434
Kojto	122:f9eeca106725	6435	#define SAI_xCR1_DS 0x000000E0U /!<DS[1:0] bits (Data Size) /
Kojto	122:f9eeca106725	6436	#define SAI_xCR1_DS_0 0x00000020U /!<Bit 0 /
Kojto	122:f9eeca106725	6437	#define SAI_xCR1_DS_1 0x00000040U /!<Bit 1 /
Kojto	122:f9eeca106725	6438	#define SAI_xCR1_DS_2 0x00000080U /!<Bit 2 /
Kojto	122:f9eeca106725	6439
Kojto	122:f9eeca106725	6440	#define SAI_xCR1_LSBFIRST 0x00000100U /!<LSB First Configuration /
Kojto	122:f9eeca106725	6441	#define SAI_xCR1_CKSTR 0x00000200U /!<ClocK STRobing edge /
Kojto	122:f9eeca106725	6442
Kojto	122:f9eeca106725	6443	#define SAI_xCR1_SYNCEN 0x00000C00U /!<SYNCEN[1:0](SYNChronization ENable) /
Kojto	122:f9eeca106725	6444	#define SAI_xCR1_SYNCEN_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	6445	#define SAI_xCR1_SYNCEN_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	6446
Kojto	122:f9eeca106725	6447	#define SAI_xCR1_MONO 0x00001000U /!<Mono mode /
Kojto	122:f9eeca106725	6448	#define SAI_xCR1_OUTDRIV 0x00002000U /!<Output Drive /
Kojto	122:f9eeca106725	6449	#define SAI_xCR1_SAIEN 0x00010000U /!<Audio Block enable /
Kojto	122:f9eeca106725	6450	#define SAI_xCR1_DMAEN 0x00020000U /!<DMA enable /
Kojto	122:f9eeca106725	6451	#define SAI_xCR1_NODIV 0x00080000U /!<No Divider Configuration /
Kojto	122:f9eeca106725	6452
Kojto	122:f9eeca106725	6453	#define SAI_xCR1_MCKDIV 0x00F00000U /!<MCKDIV[3:0] (Master ClocK Divider) /
Kojto	122:f9eeca106725	6454	#define SAI_xCR1_MCKDIV_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	6455	#define SAI_xCR1_MCKDIV_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	6456	#define SAI_xCR1_MCKDIV_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	6457	#define SAI_xCR1_MCKDIV_3 0x00800000U /!<Bit 3 /
Kojto	107:4f6c30876dfa	6458
Kojto	107:4f6c30876dfa	6459	/***************** Bit definition for SAI_xCR2 register *****************/
Kojto	122:f9eeca106725	6460	#define SAI_xCR2_FTH 0x00000007U /!<FTH[2:0](Fifo THreshold) /
Kojto	122:f9eeca106725	6461	#define SAI_xCR2_FTH_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	6462	#define SAI_xCR2_FTH_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	6463	#define SAI_xCR2_FTH_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	6464
Kojto	122:f9eeca106725	6465	#define SAI_xCR2_FFLUSH 0x00000008U /!<Fifo FLUSH /
Kojto	122:f9eeca106725	6466	#define SAI_xCR2_TRIS 0x00000010U /!<TRIState Management on data line /
Kojto	122:f9eeca106725	6467	#define SAI_xCR2_MUTE 0x00000020U /!<Mute mode /
Kojto	122:f9eeca106725	6468	#define SAI_xCR2_MUTEVAL 0x00000040U /!<Muate value /
Kojto	122:f9eeca106725	6469
Kojto	122:f9eeca106725	6470	#define SAI_xCR2_MUTECNT 0x00001F80U /!<MUTECNT[5:0] (MUTE counter) /
Kojto	122:f9eeca106725	6471	#define SAI_xCR2_MUTECNT_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	6472	#define SAI_xCR2_MUTECNT_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	6473	#define SAI_xCR2_MUTECNT_2 0x00000200U /!<Bit 2 /
Kojto	122:f9eeca106725	6474	#define SAI_xCR2_MUTECNT_3 0x00000400U /!<Bit 3 /
Kojto	122:f9eeca106725	6475	#define SAI_xCR2_MUTECNT_4 0x00000800U /!<Bit 4 /
Kojto	122:f9eeca106725	6476	#define SAI_xCR2_MUTECNT_5 0x00001000U /!<Bit 5 /
Kojto	122:f9eeca106725	6477
Kojto	122:f9eeca106725	6478	#define SAI_xCR2_CPL 0x00002000U /!< Complement Bit /
Kojto	122:f9eeca106725	6479
Kojto	122:f9eeca106725	6480	#define SAI_xCR2_COMP 0x0000C000U /!<COMP[1:0] (Companding mode) /
Kojto	122:f9eeca106725	6481	#define SAI_xCR2_COMP_0 0x00004000U /!<Bit 0 /
Kojto	122:f9eeca106725	6482	#define SAI_xCR2_COMP_1 0x00008000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	6483
Kojto	107:4f6c30876dfa	6484	/**************** Bit definition for SAI_xFRCR register *****************/
Kojto	122:f9eeca106725	6485	#define SAI_xFRCR_FRL 0x000000FFU /!<FRL[1:0](Frame length) /
Kojto	122:f9eeca106725	6486	#define SAI_xFRCR_FRL_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	6487	#define SAI_xFRCR_FRL_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	6488	#define SAI_xFRCR_FRL_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	6489	#define SAI_xFRCR_FRL_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	6490	#define SAI_xFRCR_FRL_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	6491	#define SAI_xFRCR_FRL_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	6492	#define SAI_xFRCR_FRL_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	6493	#define SAI_xFRCR_FRL_7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	6494
Kojto	122:f9eeca106725	6495	#define SAI_xFRCR_FSALL 0x00007F00U /!<FRL[1:0] (Frame synchronization active level length) /
Kojto	122:f9eeca106725	6496	#define SAI_xFRCR_FSALL_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	6497	#define SAI_xFRCR_FSALL_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	6498	#define SAI_xFRCR_FSALL_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	6499	#define SAI_xFRCR_FSALL_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	6500	#define SAI_xFRCR_FSALL_4 0x00001000U /!<Bit 4 /
Kojto	122:f9eeca106725	6501	#define SAI_xFRCR_FSALL_5 0x00002000U /!<Bit 5 /
Kojto	122:f9eeca106725	6502	#define SAI_xFRCR_FSALL_6 0x00004000U /!<Bit 6 /
Kojto	122:f9eeca106725	6503
Kojto	122:f9eeca106725	6504	#define SAI_xFRCR_FSDEF 0x00010000U /!<Frame Synchronization Definition /
Kojto	122:f9eeca106725	6505	#define SAI_xFRCR_FSPOL 0x00020000U /!<Frame Synchronization POLarity /
Kojto	122:f9eeca106725	6506	#define SAI_xFRCR_FSOFF 0x00040000U /!<Frame Synchronization OFFset /
Kojto	122:f9eeca106725	6507
Kojto	122:f9eeca106725	6508	/* Legacy define */
Kojto	122:f9eeca106725	6509	#define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
Kojto	107:4f6c30876dfa	6510
Kojto	107:4f6c30876dfa	6511	/**************** Bit definition for SAI_xSLOTR register *****************/
Kojto	122:f9eeca106725	6512	#define SAI_xSLOTR_FBOFF 0x0000001FU /!<FRL[4:0](First Bit Offset) /
Kojto	122:f9eeca106725	6513	#define SAI_xSLOTR_FBOFF_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	6514	#define SAI_xSLOTR_FBOFF_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	6515	#define SAI_xSLOTR_FBOFF_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	6516	#define SAI_xSLOTR_FBOFF_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	6517	#define SAI_xSLOTR_FBOFF_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	6518
Kojto	122:f9eeca106725	6519	#define SAI_xSLOTR_SLOTSZ 0x000000C0U /!<SLOTSZ[1:0] (Slot size) /
Kojto	122:f9eeca106725	6520	#define SAI_xSLOTR_SLOTSZ_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	6521	#define SAI_xSLOTR_SLOTSZ_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	6522
Kojto	122:f9eeca106725	6523	#define SAI_xSLOTR_NBSLOT 0x00000F00U /!<NBSLOT[3:0] (Number of Slot in audio Frame) /
Kojto	122:f9eeca106725	6524	#define SAI_xSLOTR_NBSLOT_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	6525	#define SAI_xSLOTR_NBSLOT_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	6526	#define SAI_xSLOTR_NBSLOT_2 0x00000400U /!<Bit 2 /
Kojto	122:f9eeca106725	6527	#define SAI_xSLOTR_NBSLOT_3 0x00000800U /!<Bit 3 /
Kojto	122:f9eeca106725	6528
Kojto	122:f9eeca106725	6529	#define SAI_xSLOTR_SLOTEN 0xFFFF0000U /!<SLOTEN[15:0] (Slot Enable) /
Kojto	107:4f6c30876dfa	6530
Kojto	107:4f6c30876dfa	6531	/***************** Bit definition for SAI_xIMR register *****************/
Kojto	122:f9eeca106725	6532	#define SAI_xIMR_OVRUDRIE 0x00000001U /!<Overrun underrun interrupt enable /
Kojto	122:f9eeca106725	6533	#define SAI_xIMR_MUTEDETIE 0x00000002U /!<Mute detection interrupt enable /
Kojto	122:f9eeca106725	6534	#define SAI_xIMR_WCKCFGIE 0x00000004U /!<Wrong Clock Configuration interrupt enable /
Kojto	122:f9eeca106725	6535	#define SAI_xIMR_FREQIE 0x00000008U /!<FIFO request interrupt enable /
Kojto	122:f9eeca106725	6536	#define SAI_xIMR_CNRDYIE 0x00000010U /!<Codec not ready interrupt enable /
Kojto	122:f9eeca106725	6537	#define SAI_xIMR_AFSDETIE 0x00000020U /!<Anticipated frame synchronization detection interrupt enable /
Kojto	122:f9eeca106725	6538	#define SAI_xIMR_LFSDETIE 0x00000040U /!<Late frame synchronization detection interrupt enable /
Kojto	107:4f6c30876dfa	6539
Kojto	107:4f6c30876dfa	6540	/****************** Bit definition for SAI_xSR register *****************/
Kojto	122:f9eeca106725	6541	#define SAI_xSR_OVRUDR 0x00000001U /!<Overrun underrun /
Kojto	122:f9eeca106725	6542	#define SAI_xSR_MUTEDET 0x00000002U /!<Mute detection /
Kojto	122:f9eeca106725	6543	#define SAI_xSR_WCKCFG 0x00000004U /!<Wrong Clock Configuration /
Kojto	122:f9eeca106725	6544	#define SAI_xSR_FREQ 0x00000008U /!<FIFO request /
Kojto	122:f9eeca106725	6545	#define SAI_xSR_CNRDY 0x00000010U /!<Codec not ready /
Kojto	122:f9eeca106725	6546	#define SAI_xSR_AFSDET 0x00000020U /!<Anticipated frame synchronization detection /
Kojto	122:f9eeca106725	6547	#define SAI_xSR_LFSDET 0x00000040U /!<Late frame synchronization detection /
Kojto	122:f9eeca106725	6548
Kojto	122:f9eeca106725	6549	#define SAI_xSR_FLVL 0x00070000U /!<FLVL[2:0] (FIFO Level Threshold) /
Kojto	122:f9eeca106725	6550	#define SAI_xSR_FLVL_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	6551	#define SAI_xSR_FLVL_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	6552	#define SAI_xSR_FLVL_2 0x00040000U /!<Bit 2 /
Kojto	107:4f6c30876dfa	6553
Kojto	107:4f6c30876dfa	6554	/**************** Bit definition for SAI_xCLRFR register ****************/
Kojto	122:f9eeca106725	6555	#define SAI_xCLRFR_COVRUDR 0x00000001U /!<Clear Overrun underrun /
Kojto	122:f9eeca106725	6556	#define SAI_xCLRFR_CMUTEDET 0x00000002U /!<Clear Mute detection /
Kojto	122:f9eeca106725	6557	#define SAI_xCLRFR_CWCKCFG 0x00000004U /!<Clear Wrong Clock Configuration /
Kojto	122:f9eeca106725	6558	#define SAI_xCLRFR_CFREQ 0x00000008U /!<Clear FIFO request /
Kojto	122:f9eeca106725	6559	#define SAI_xCLRFR_CCNRDY 0x00000010U /!<Clear Codec not ready /
Kojto	122:f9eeca106725	6560	#define SAI_xCLRFR_CAFSDET 0x00000020U /!<Clear Anticipated frame synchronization detection /
Kojto	122:f9eeca106725	6561	#define SAI_xCLRFR_CLFSDET 0x00000040U /!<Clear Late frame synchronization detection /
Kojto	107:4f6c30876dfa	6562
Kojto	107:4f6c30876dfa	6563	/**************** Bit definition for SAI_xDR register *******************/
Kojto	122:f9eeca106725	6564	#define SAI_xDR_DATA 0xFFFFFFFFU
Kojto	107:4f6c30876dfa	6565
Kojto	107:4f6c30876dfa	6566	/******************************************************************************/
Kojto	107:4f6c30876dfa	6567	/* */
Kojto	107:4f6c30876dfa	6568	/* SPDIF-RX Interface */
Kojto	107:4f6c30876dfa	6569	/* */
Kojto	107:4f6c30876dfa	6570	/******************************************************************************/
Kojto	107:4f6c30876dfa	6571	/****************** Bit definition for SPDIF_CR register *****************/
Kojto	122:f9eeca106725	6572	#define SPDIFRX_CR_SPDIFEN 0x00000003U /!<Peripheral Block Enable /
Kojto	122:f9eeca106725	6573	#define SPDIFRX_CR_RXDMAEN 0x00000004U /!<Receiver DMA Enable for data flow /
Kojto	122:f9eeca106725	6574	#define SPDIFRX_CR_RXSTEO 0x00000008U /!<Stereo Mode /
Kojto	122:f9eeca106725	6575	#define SPDIFRX_CR_DRFMT 0x00000030U /!<RX Data format /
Kojto	122:f9eeca106725	6576	#define SPDIFRX_CR_PMSK 0x00000040U /!<Mask Parity error bit /
Kojto	122:f9eeca106725	6577	#define SPDIFRX_CR_VMSK 0x00000080U /!<Mask of Validity bit /
Kojto	122:f9eeca106725	6578	#define SPDIFRX_CR_CUMSK 0x00000100U /!<Mask of channel status and user bits /
Kojto	122:f9eeca106725	6579	#define SPDIFRX_CR_PTMSK 0x00000200U /!<Mask of Preamble Type bits /
Kojto	122:f9eeca106725	6580	#define SPDIFRX_CR_CBDMAEN 0x00000400U /!<Control Buffer DMA ENable for control flow /
Kojto	122:f9eeca106725	6581	#define SPDIFRX_CR_CHSEL 0x00000800U /!<Channel Selection /
Kojto	122:f9eeca106725	6582	#define SPDIFRX_CR_NBTR 0x00003000U /!<Maximum allowed re-tries during synchronization phase /
Kojto	122:f9eeca106725	6583	#define SPDIFRX_CR_WFA 0x00004000U /!<Wait For Activity /
Kojto	122:f9eeca106725	6584	#define SPDIFRX_CR_INSEL 0x00070000U /!<SPDIF input selection /
Kojto	107:4f6c30876dfa	6585
Kojto	107:4f6c30876dfa	6586	/***************** Bit definition for SPDIFRX_IMR register *****************/
Kojto	122:f9eeca106725	6587	#define SPDIFRX_IMR_RXNEIE 0x00000001U /!<RXNE interrupt enable /
Kojto	122:f9eeca106725	6588	#define SPDIFRX_IMR_CSRNEIE 0x00000002U /!<Control Buffer Ready Interrupt Enable /
Kojto	122:f9eeca106725	6589	#define SPDIFRX_IMR_PERRIE 0x00000004U /!<Parity error interrupt enable /
Kojto	122:f9eeca106725	6590	#define SPDIFRX_IMR_OVRIE 0x00000008U /!<Overrun error Interrupt Enable /
Kojto	122:f9eeca106725	6591	#define SPDIFRX_IMR_SBLKIE 0x00000010U /!<Synchronization Block Detected Interrupt Enable /
Kojto	122:f9eeca106725	6592	#define SPDIFRX_IMR_SYNCDIE 0x00000020U /!<Synchronization Done /
Kojto	122:f9eeca106725	6593	#define SPDIFRX_IMR_IFEIE 0x00000040U /!<Serial Interface Error Interrupt Enable /
Kojto	107:4f6c30876dfa	6594
Kojto	107:4f6c30876dfa	6595	/***************** Bit definition for SPDIFRX_SR register *****************/
Kojto	122:f9eeca106725	6596	#define SPDIFRX_SR_RXNE 0x00000001U /!<Read data register not empty /
Kojto	122:f9eeca106725	6597	#define SPDIFRX_SR_CSRNE 0x00000002U /!<The Control Buffer register is not empty /
Kojto	122:f9eeca106725	6598	#define SPDIFRX_SR_PERR 0x00000004U /!<Parity error /
Kojto	122:f9eeca106725	6599	#define SPDIFRX_SR_OVR 0x00000008U /!<Overrun error /
Kojto	122:f9eeca106725	6600	#define SPDIFRX_SR_SBD 0x00000010U /!<Synchronization Block Detected /
Kojto	122:f9eeca106725	6601	#define SPDIFRX_SR_SYNCD 0x00000020U /!<Synchronization Done /
Kojto	122:f9eeca106725	6602	#define SPDIFRX_SR_FERR 0x00000040U /!<Framing error /
Kojto	122:f9eeca106725	6603	#define SPDIFRX_SR_SERR 0x00000080U /!<Synchronization error /
Kojto	122:f9eeca106725	6604	#define SPDIFRX_SR_TERR 0x00000100U /!<Time-out error /
Kojto	122:f9eeca106725	6605	#define SPDIFRX_SR_WIDTH5 0x7FFF0000U /!<Duration of 5 symbols counted with spdif_clk /
Kojto	107:4f6c30876dfa	6606
Kojto	107:4f6c30876dfa	6607	/***************** Bit definition for SPDIFRX_IFCR register *****************/
Kojto	122:f9eeca106725	6608	#define SPDIFRX_IFCR_PERRCF 0x00000004U /!<Clears the Parity error flag /
Kojto	122:f9eeca106725	6609	#define SPDIFRX_IFCR_OVRCF 0x00000008U /!<Clears the Overrun error flag /
Kojto	122:f9eeca106725	6610	#define SPDIFRX_IFCR_SBDCF 0x00000010U /!<Clears the Synchronization Block Detected flag /
Kojto	122:f9eeca106725	6611	#define SPDIFRX_IFCR_SYNCDCF 0x00000020U /!<Clears the Synchronization Done flag /
Kojto	107:4f6c30876dfa	6612
Kojto	107:4f6c30876dfa	6613	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *****************/
Kojto	122:f9eeca106725	6614	#define SPDIFRX_DR0_DR 0x00FFFFFFU /!<Data value /
Kojto	122:f9eeca106725	6615	#define SPDIFRX_DR0_PE 0x01000000U /!<Parity Error bit /
Kojto	122:f9eeca106725	6616	#define SPDIFRX_DR0_V 0x02000000U /!<Validity bit /
Kojto	122:f9eeca106725	6617	#define SPDIFRX_DR0_U 0x04000000U /!<User bit /
Kojto	122:f9eeca106725	6618	#define SPDIFRX_DR0_C 0x08000000U /!<Channel Status bit /
Kojto	122:f9eeca106725	6619	#define SPDIFRX_DR0_PT 0x30000000U /!<Preamble Type /
Kojto	107:4f6c30876dfa	6620
Kojto	107:4f6c30876dfa	6621	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *****************/
Kojto	122:f9eeca106725	6622	#define SPDIFRX_DR1_DR 0xFFFFFF00U /!<Data value /
Kojto	122:f9eeca106725	6623	#define SPDIFRX_DR1_PT 0x00000030U /!<Preamble Type /
Kojto	122:f9eeca106725	6624	#define SPDIFRX_DR1_C 0x00000008U /!<Channel Status bit /
Kojto	122:f9eeca106725	6625	#define SPDIFRX_DR1_U 0x00000004U /!<User bit /
Kojto	122:f9eeca106725	6626	#define SPDIFRX_DR1_V 0x00000002U /!<Validity bit /
Kojto	122:f9eeca106725	6627	#define SPDIFRX_DR1_PE 0x00000001U /!<Parity Error bit /
Kojto	107:4f6c30876dfa	6628
Kojto	107:4f6c30876dfa	6629	/***************** Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *****************/
Kojto	122:f9eeca106725	6630	#define SPDIFRX_DR1_DRNL1 0xFFFF0000U /!<Data value Channel B /
Kojto	122:f9eeca106725	6631	#define SPDIFRX_DR1_DRNL2 0x0000FFFFU /!<Data value Channel A /
Kojto	107:4f6c30876dfa	6632
Kojto	107:4f6c30876dfa	6633	/***************** Bit definition for SPDIFRX_CSR register *****************/
Kojto	122:f9eeca106725	6634	#define SPDIFRX_CSR_USR 0x0000FFFFU /!<User data information /
Kojto	122:f9eeca106725	6635	#define SPDIFRX_CSR_CS 0x00FF0000U /!<Channel A status information /
Kojto	122:f9eeca106725	6636	#define SPDIFRX_CSR_SOB 0x01000000U /!<Start Of Block /
Kojto	107:4f6c30876dfa	6637
Kojto	107:4f6c30876dfa	6638	/***************** Bit definition for SPDIFRX_DIR register *****************/
Kojto	122:f9eeca106725	6639	#define SPDIFRX_DIR_THI 0x000013FFU /!<Threshold LOW /
Kojto	122:f9eeca106725	6640	#define SPDIFRX_DIR_TLO 0x1FFF0000U /!<Threshold HIGH /
Kojto	107:4f6c30876dfa	6641
Kojto	107:4f6c30876dfa	6642
Kojto	107:4f6c30876dfa	6643	/******************************************************************************/
Kojto	107:4f6c30876dfa	6644	/* */
Kojto	107:4f6c30876dfa	6645	/* SD host Interface */
Kojto	107:4f6c30876dfa	6646	/* */
Kojto	107:4f6c30876dfa	6647	/******************************************************************************/
Kojto	107:4f6c30876dfa	6648	/**************** Bit definition for SDMMC_POWER register ****************/
Kojto	122:f9eeca106725	6649	#define SDMMC_POWER_PWRCTRL 0x03U /!<PWRCTRL[1:0] bits (Power supply control bits) /
Kojto	122:f9eeca106725	6650	#define SDMMC_POWER_PWRCTRL_0 0x01U /!<Bit 0 /
Kojto	122:f9eeca106725	6651	#define SDMMC_POWER_PWRCTRL_1 0x02U /!<Bit 1 /
Kojto	107:4f6c30876dfa	6652
Kojto	107:4f6c30876dfa	6653	/**************** Bit definition for SDMMC_CLKCR register ****************/
Kojto	122:f9eeca106725	6654	#define SDMMC_CLKCR_CLKDIV 0x00FFU /!<Clock divide factor /
Kojto	122:f9eeca106725	6655	#define SDMMC_CLKCR_CLKEN 0x0100U /!<Clock enable bit /
Kojto	122:f9eeca106725	6656	#define SDMMC_CLKCR_PWRSAV 0x0200U /!<Power saving configuration bit /
Kojto	122:f9eeca106725	6657	#define SDMMC_CLKCR_BYPASS 0x0400U /!<Clock divider bypass enable bit /
Kojto	107:4f6c30876dfa	6658
Kojto	122:f9eeca106725	6659	#define SDMMC_CLKCR_WIDBUS 0x1800U /!<WIDBUS[1:0] bits (Wide bus mode enable bit) /
Kojto	122:f9eeca106725	6660	#define SDMMC_CLKCR_WIDBUS_0 0x0800U /!<Bit 0 /
Kojto	122:f9eeca106725	6661	#define SDMMC_CLKCR_WIDBUS_1 0x1000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	6662
Kojto	122:f9eeca106725	6663	#define SDMMC_CLKCR_NEGEDGE 0x2000U /!<SDMMC_CK dephasing selection bit /
Kojto	122:f9eeca106725	6664	#define SDMMC_CLKCR_HWFC_EN 0x4000U /!<HW Flow Control enable /
Kojto	107:4f6c30876dfa	6665
Kojto	107:4f6c30876dfa	6666	/***************** Bit definition for SDMMC_ARG register *****************/
Kojto	122:f9eeca106725	6667	#define SDMMC_ARG_CMDARG 0xFFFFFFFFU /!<Command argument /
Kojto	107:4f6c30876dfa	6668
Kojto	107:4f6c30876dfa	6669	/***************** Bit definition for SDMMC_CMD register *****************/
Kojto	122:f9eeca106725	6670	#define SDMMC_CMD_CMDINDEX 0x003FU /!<Command Index /
Kojto	107:4f6c30876dfa	6671
Kojto	122:f9eeca106725	6672	#define SDMMC_CMD_WAITRESP 0x00C0U /!<WAITRESP[1:0] bits (Wait for response bits) /
Kojto	122:f9eeca106725	6673	#define SDMMC_CMD_WAITRESP_0 0x0040U /!< Bit 0 /
Kojto	122:f9eeca106725	6674	#define SDMMC_CMD_WAITRESP_1 0x0080U /!< Bit 1 /
Kojto	107:4f6c30876dfa	6675
Kojto	122:f9eeca106725	6676	#define SDMMC_CMD_WAITINT 0x0100U /!<CPSM Waits for Interrupt Request /
Kojto	122:f9eeca106725	6677	#define SDMMC_CMD_WAITPEND 0x0200U /!<CPSM Waits for ends of data transfer (CmdPend internal signal) /
Kojto	122:f9eeca106725	6678	#define SDMMC_CMD_CPSMEN 0x0400U /!<Command path state machine (CPSM) Enable bit /
Kojto	122:f9eeca106725	6679	#define SDMMC_CMD_SDIOSUSPEND 0x0800U /!<SD I/O suspend command /
Kojto	107:4f6c30876dfa	6680
Kojto	107:4f6c30876dfa	6681	/*************** Bit definition for SDMMC_RESPCMD register ***************/
Kojto	122:f9eeca106725	6682	#define SDMMC_RESPCMD_RESPCMD 0x3FU /!<Response command index /
Kojto	107:4f6c30876dfa	6683
Kojto	107:4f6c30876dfa	6684	/**************** Bit definition for SDMMC_RESP0 register ****************/
Kojto	122:f9eeca106725	6685	#define SDMMC_RESP0_CARDSTATUS0 0xFFFFFFFFU /!<Card Status /
Kojto	107:4f6c30876dfa	6686
Kojto	107:4f6c30876dfa	6687	/**************** Bit definition for SDMMC_RESP1 register ****************/
Kojto	122:f9eeca106725	6688	#define SDMMC_RESP1_CARDSTATUS1 0xFFFFFFFFU /!<Card Status /
Kojto	107:4f6c30876dfa	6689
Kojto	107:4f6c30876dfa	6690	/**************** Bit definition for SDMMC_RESP2 register ****************/
Kojto	122:f9eeca106725	6691	#define SDMMC_RESP2_CARDSTATUS2 0xFFFFFFFFU /!<Card Status /
Kojto	107:4f6c30876dfa	6692
Kojto	107:4f6c30876dfa	6693	/**************** Bit definition for SDMMC_RESP3 register ****************/
Kojto	122:f9eeca106725	6694	#define SDMMC_RESP3_CARDSTATUS3 0xFFFFFFFFU /!<Card Status /
Kojto	107:4f6c30876dfa	6695
Kojto	107:4f6c30876dfa	6696	/**************** Bit definition for SDMMC_RESP4 register ****************/
Kojto	122:f9eeca106725	6697	#define SDMMC_RESP4_CARDSTATUS4 0xFFFFFFFFU /!<Card Status /
Kojto	107:4f6c30876dfa	6698
Kojto	107:4f6c30876dfa	6699	/**************** Bit definition for SDMMC_DTIMER register ***************/
Kojto	122:f9eeca106725	6700	#define SDMMC_DTIMER_DATATIME 0xFFFFFFFFU /!<Data timeout period. /
Kojto	107:4f6c30876dfa	6701
Kojto	107:4f6c30876dfa	6702	/**************** Bit definition for SDMMC_DLEN register *****************/
Kojto	122:f9eeca106725	6703	#define SDMMC_DLEN_DATALENGTH 0x01FFFFFFU /!<Data length value /
Kojto	107:4f6c30876dfa	6704
Kojto	107:4f6c30876dfa	6705	/**************** Bit definition for SDMMC_DCTRL register ****************/
Kojto	122:f9eeca106725	6706	#define SDMMC_DCTRL_DTEN 0x0001U /!<Data transfer enabled bit /
Kojto	122:f9eeca106725	6707	#define SDMMC_DCTRL_DTDIR 0x0002U /!<Data transfer direction selection /
Kojto	122:f9eeca106725	6708	#define SDMMC_DCTRL_DTMODE 0x0004U /!<Data transfer mode selection /
Kojto	122:f9eeca106725	6709	#define SDMMC_DCTRL_DMAEN 0x0008U /!<DMA enabled bit /
Kojto	122:f9eeca106725	6710
Kojto	122:f9eeca106725	6711	#define SDMMC_DCTRL_DBLOCKSIZE 0x00F0U /!<DBLOCKSIZE[3:0] bits (Data block size) /
Kojto	122:f9eeca106725	6712	#define SDMMC_DCTRL_DBLOCKSIZE_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	6713	#define SDMMC_DCTRL_DBLOCKSIZE_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	6714	#define SDMMC_DCTRL_DBLOCKSIZE_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	6715	#define SDMMC_DCTRL_DBLOCKSIZE_3 0x0080U /!<Bit 3 /
Kojto	122:f9eeca106725	6716
Kojto	122:f9eeca106725	6717	#define SDMMC_DCTRL_RWSTART 0x0100U /!<Read wait start /
Kojto	122:f9eeca106725	6718	#define SDMMC_DCTRL_RWSTOP 0x0200U /!<Read wait stop /
Kojto	122:f9eeca106725	6719	#define SDMMC_DCTRL_RWMOD 0x0400U /!<Read wait mode /
Kojto	122:f9eeca106725	6720	#define SDMMC_DCTRL_SDIOEN 0x0800U /!<SD I/O enable functions /
Kojto	107:4f6c30876dfa	6721
Kojto	107:4f6c30876dfa	6722	/**************** Bit definition for SDMMC_DCOUNT register ***************/
Kojto	122:f9eeca106725	6723	#define SDMMC_DCOUNT_DATACOUNT 0x01FFFFFFU /!<Data count value /
Kojto	122:f9eeca106725	6724
Kojto	122:f9eeca106725	6725	/**************** Bit definition for SDMMC_STA registe ******************/
Kojto	122:f9eeca106725	6726	#define SDMMC_STA_CCRCFAIL 0x00000001U /!<Command response received (CRC check failed) /
Kojto	122:f9eeca106725	6727	#define SDMMC_STA_DCRCFAIL 0x00000002U /!<Data block sent/received (CRC check failed) /
Kojto	122:f9eeca106725	6728	#define SDMMC_STA_CTIMEOUT 0x00000004U /!<Command response timeout /
Kojto	122:f9eeca106725	6729	#define SDMMC_STA_DTIMEOUT 0x00000008U /!<Data timeout /
Kojto	122:f9eeca106725	6730	#define SDMMC_STA_TXUNDERR 0x00000010U /!<Transmit FIFO underrun error /
Kojto	122:f9eeca106725	6731	#define SDMMC_STA_RXOVERR 0x00000020U /!<Received FIFO overrun error /
Kojto	122:f9eeca106725	6732	#define SDMMC_STA_CMDREND 0x00000040U /!<Command response received (CRC check passed) /
Kojto	122:f9eeca106725	6733	#define SDMMC_STA_CMDSENT 0x00000080U /!<Command sent (no response required) /
Kojto	122:f9eeca106725	6734	#define SDMMC_STA_DATAEND 0x00000100U /!<Data end (data counter, SDIDCOUNT, is zero) /
Kojto	122:f9eeca106725	6735	#define SDMMC_STA_DBCKEND 0x00000400U /!<Data block sent/received (CRC check passed) /
Kojto	122:f9eeca106725	6736	#define SDMMC_STA_CMDACT 0x00000800U /!<Command transfer in progress /
Kojto	122:f9eeca106725	6737	#define SDMMC_STA_TXACT 0x00001000U /!<Data transmit in progress /
Kojto	122:f9eeca106725	6738	#define SDMMC_STA_RXACT 0x00002000U /!<Data receive in progress /
Kojto	122:f9eeca106725	6739	#define SDMMC_STA_TXFIFOHE 0x00004000U /!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO /
Kojto	122:f9eeca106725	6740	#define SDMMC_STA_RXFIFOHF 0x00008000U /!<Receive FIFO Half Full: there are at least 8 words in the FIFO /
Kojto	122:f9eeca106725	6741	#define SDMMC_STA_TXFIFOF 0x00010000U /!<Transmit FIFO full /
Kojto	122:f9eeca106725	6742	#define SDMMC_STA_RXFIFOF 0x00020000U /!<Receive FIFO full /
Kojto	122:f9eeca106725	6743	#define SDMMC_STA_TXFIFOE 0x00040000U /!<Transmit FIFO empty /
Kojto	122:f9eeca106725	6744	#define SDMMC_STA_RXFIFOE 0x00080000U /!<Receive FIFO empty /
Kojto	122:f9eeca106725	6745	#define SDMMC_STA_TXDAVL 0x00100000U /!<Data available in transmit FIFO /
Kojto	122:f9eeca106725	6746	#define SDMMC_STA_RXDAVL 0x00200000U /!<Data available in receive FIFO /
Kojto	122:f9eeca106725	6747	#define SDMMC_STA_SDIOIT 0x00400000U /!<SDMMC interrupt received /
Kojto	107:4f6c30876dfa	6748
Kojto	107:4f6c30876dfa	6749	/***************** Bit definition for SDMMC_ICR register *****************/
Kojto	122:f9eeca106725	6750	#define SDMMC_ICR_CCRCFAILC 0x00000001U /!<CCRCFAIL flag clear bit /
Kojto	122:f9eeca106725	6751	#define SDMMC_ICR_DCRCFAILC 0x00000002U /!<DCRCFAIL flag clear bit /
Kojto	122:f9eeca106725	6752	#define SDMMC_ICR_CTIMEOUTC 0x00000004U /!<CTIMEOUT flag clear bit /
Kojto	122:f9eeca106725	6753	#define SDMMC_ICR_DTIMEOUTC 0x00000008U /!<DTIMEOUT flag clear bit /
Kojto	122:f9eeca106725	6754	#define SDMMC_ICR_TXUNDERRC 0x00000010U /!<TXUNDERR flag clear bit /
Kojto	122:f9eeca106725	6755	#define SDMMC_ICR_RXOVERRC 0x00000020U /!<RXOVERR flag clear bit /
Kojto	122:f9eeca106725	6756	#define SDMMC_ICR_CMDRENDC 0x00000040U /!<CMDREND flag clear bit /
Kojto	122:f9eeca106725	6757	#define SDMMC_ICR_CMDSENTC 0x00000080U /!<CMDSENT flag clear bit /
Kojto	122:f9eeca106725	6758	#define SDMMC_ICR_DATAENDC 0x00000100U /!<DATAEND flag clear bit /
Kojto	122:f9eeca106725	6759	#define SDMMC_ICR_DBCKENDC 0x00000400U /!<DBCKEND flag clear bit /
Kojto	122:f9eeca106725	6760	#define SDMMC_ICR_SDIOITC 0x00400000U /!<SDMMCIT flag clear bit /
Kojto	107:4f6c30876dfa	6761
Kojto	107:4f6c30876dfa	6762	/**************** Bit definition for SDMMC_MASK register *****************/
Kojto	122:f9eeca106725	6763	#define SDMMC_MASK_CCRCFAILIE 0x00000001U /!<Command CRC Fail Interrupt Enable /
Kojto	122:f9eeca106725	6764	#define SDMMC_MASK_DCRCFAILIE 0x00000002U /!<Data CRC Fail Interrupt Enable /
Kojto	122:f9eeca106725	6765	#define SDMMC_MASK_CTIMEOUTIE 0x00000004U /!<Command TimeOut Interrupt Enable /
Kojto	122:f9eeca106725	6766	#define SDMMC_MASK_DTIMEOUTIE 0x00000008U /!<Data TimeOut Interrupt Enable /
Kojto	122:f9eeca106725	6767	#define SDMMC_MASK_TXUNDERRIE 0x00000010U /!<Tx FIFO UnderRun Error Interrupt Enable /
Kojto	122:f9eeca106725	6768	#define SDMMC_MASK_RXOVERRIE 0x00000020U /!<Rx FIFO OverRun Error Interrupt Enable /
Kojto	122:f9eeca106725	6769	#define SDMMC_MASK_CMDRENDIE 0x00000040U /!<Command Response Received Interrupt Enable /
Kojto	122:f9eeca106725	6770	#define SDMMC_MASK_CMDSENTIE 0x00000080U /!<Command Sent Interrupt Enable /
Kojto	122:f9eeca106725	6771	#define SDMMC_MASK_DATAENDIE 0x00000100U /!<Data End Interrupt Enable /
Kojto	122:f9eeca106725	6772	#define SDMMC_MASK_DBCKENDIE 0x00000400U /!<Data Block End Interrupt Enable /
Kojto	122:f9eeca106725	6773	#define SDMMC_MASK_CMDACTIE 0x00000800U /!<CCommand Acting Interrupt Enable /
Kojto	122:f9eeca106725	6774	#define SDMMC_MASK_TXACTIE 0x00001000U /!<Data Transmit Acting Interrupt Enable /
Kojto	122:f9eeca106725	6775	#define SDMMC_MASK_RXACTIE 0x00002000U /!<Data receive acting interrupt enabled /
Kojto	122:f9eeca106725	6776	#define SDMMC_MASK_TXFIFOHEIE 0x00004000U /!<Tx FIFO Half Empty interrupt Enable /
Kojto	122:f9eeca106725	6777	#define SDMMC_MASK_RXFIFOHFIE 0x00008000U /!<Rx FIFO Half Full interrupt Enable /
Kojto	122:f9eeca106725	6778	#define SDMMC_MASK_TXFIFOFIE 0x00010000U /!<Tx FIFO Full interrupt Enable /
Kojto	122:f9eeca106725	6779	#define SDMMC_MASK_RXFIFOFIE 0x00020000U /!<Rx FIFO Full interrupt Enable /
Kojto	122:f9eeca106725	6780	#define SDMMC_MASK_TXFIFOEIE 0x00040000U /!<Tx FIFO Empty interrupt Enable /
Kojto	122:f9eeca106725	6781	#define SDMMC_MASK_RXFIFOEIE 0x00080000U /!<Rx FIFO Empty interrupt Enable /
Kojto	122:f9eeca106725	6782	#define SDMMC_MASK_TXDAVLIE 0x00100000U /!<Data available in Tx FIFO interrupt Enable /
Kojto	122:f9eeca106725	6783	#define SDMMC_MASK_RXDAVLIE 0x00200000U /!<Data available in Rx FIFO interrupt Enable /
Kojto	122:f9eeca106725	6784	#define SDMMC_MASK_SDIOITIE 0x00400000U /!<SDMMC Mode Interrupt Received interrupt Enable /
Kojto	107:4f6c30876dfa	6785
Kojto	107:4f6c30876dfa	6786	/*************** Bit definition for SDMMC_FIFOCNT register ***************/
Kojto	122:f9eeca106725	6787	#define SDMMC_FIFOCNT_FIFOCOUNT 0x00FFFFFFU /!<Remaining number of words to be written to or read from the FIFO /
Kojto	107:4f6c30876dfa	6788
Kojto	107:4f6c30876dfa	6789	/**************** Bit definition for SDMMC_FIFO register *****************/
Kojto	122:f9eeca106725	6790	#define SDMMC_FIFO_FIFODATA 0xFFFFFFFFU /!<Receive and transmit FIFO data /
Kojto	107:4f6c30876dfa	6791
Kojto	107:4f6c30876dfa	6792	/******************************************************************************/
Kojto	107:4f6c30876dfa	6793	/* */
Kojto	107:4f6c30876dfa	6794	/* Serial Peripheral Interface (SPI) */
Kojto	107:4f6c30876dfa	6795	/* */
Kojto	107:4f6c30876dfa	6796	/******************************************************************************/
Kojto	107:4f6c30876dfa	6797	/***************** Bit definition for SPI_CR1 register ******************/
Kojto	122:f9eeca106725	6798	#define SPI_CR1_CPHA 0x00000001U /!< Clock Phase /
Kojto	122:f9eeca106725	6799	#define SPI_CR1_CPOL 0x00000002U /!< Clock Polarity /
Kojto	122:f9eeca106725	6800	#define SPI_CR1_MSTR 0x00000004U /!< Master Selection /
Kojto	122:f9eeca106725	6801	#define SPI_CR1_BR 0x00000038U /!< BR[2:0] bits (Baud Rate Control) /
Kojto	122:f9eeca106725	6802	#define SPI_CR1_BR_0 0x00000008U /!< Bit 0 /
Kojto	122:f9eeca106725	6803	#define SPI_CR1_BR_1 0x00000010U /!< Bit 1 /
Kojto	122:f9eeca106725	6804	#define SPI_CR1_BR_2 0x00000020U /!< Bit 2 /
Kojto	122:f9eeca106725	6805	#define SPI_CR1_SPE 0x00000040U /!< SPI Enable /
Kojto	122:f9eeca106725	6806	#define SPI_CR1_LSBFIRST 0x00000080U /!< Frame Format /
Kojto	122:f9eeca106725	6807	#define SPI_CR1_SSI 0x00000100U /!< Internal slave select /
Kojto	122:f9eeca106725	6808	#define SPI_CR1_SSM 0x00000200U /!< Software slave management /
Kojto	122:f9eeca106725	6809	#define SPI_CR1_RXONLY 0x00000400U /!< Receive only /
Kojto	122:f9eeca106725	6810	#define SPI_CR1_CRCL 0x00000800U /!< CRC Length /
Kojto	122:f9eeca106725	6811	#define SPI_CR1_CRCNEXT 0x00001000U /!< Transmit CRC next /
Kojto	122:f9eeca106725	6812	#define SPI_CR1_CRCEN 0x00002000U /!< Hardware CRC calculation enable /
Kojto	122:f9eeca106725	6813	#define SPI_CR1_BIDIOE 0x00004000U /!< Output enable in bidirectional mode /
Kojto	122:f9eeca106725	6814	#define SPI_CR1_BIDIMODE 0x00008000U /!< Bidirectional data mode enable /
Kojto	107:4f6c30876dfa	6815
Kojto	107:4f6c30876dfa	6816	/***************** Bit definition for SPI_CR2 register ******************/
Kojto	122:f9eeca106725	6817	#define SPI_CR2_RXDMAEN 0x00000001U /!< Rx Buffer DMA Enable /
Kojto	122:f9eeca106725	6818	#define SPI_CR2_TXDMAEN 0x00000002U /!< Tx Buffer DMA Enable /
Kojto	122:f9eeca106725	6819	#define SPI_CR2_SSOE 0x00000004U /!< SS Output Enable /
Kojto	122:f9eeca106725	6820	#define SPI_CR2_NSSP 0x00000008U /!< NSS pulse management Enable /
Kojto	122:f9eeca106725	6821	#define SPI_CR2_FRF 0x00000010U /!< Frame Format Enable /
Kojto	122:f9eeca106725	6822	#define SPI_CR2_ERRIE 0x00000020U /!< Error Interrupt Enable /
Kojto	122:f9eeca106725	6823	#define SPI_CR2_RXNEIE 0x00000040U /!< RX buffer Not Empty Interrupt Enable /
Kojto	122:f9eeca106725	6824	#define SPI_CR2_TXEIE 0x00000080U /!< Tx buffer Empty Interrupt Enable /
Kojto	122:f9eeca106725	6825	#define SPI_CR2_DS 0x00000F00U /!< DS[3:0] Data Size /
Kojto	122:f9eeca106725	6826	#define SPI_CR2_DS_0 0x00000100U /!< Bit 0 /
Kojto	122:f9eeca106725	6827	#define SPI_CR2_DS_1 0x00000200U /!< Bit 1 /
Kojto	122:f9eeca106725	6828	#define SPI_CR2_DS_2 0x00000400U /!< Bit 2 /
Kojto	122:f9eeca106725	6829	#define SPI_CR2_DS_3 0x00000800U /!< Bit 3 /
Kojto	122:f9eeca106725	6830	#define SPI_CR2_FRXTH 0x00001000U /!< FIFO reception Threshold /
Kojto	122:f9eeca106725	6831	#define SPI_CR2_LDMARX 0x00002000U /!< Last DMA transfer for reception /
Kojto	122:f9eeca106725	6832	#define SPI_CR2_LDMATX 0x00004000U /!< Last DMA transfer for transmission /
Kojto	107:4f6c30876dfa	6833
Kojto	107:4f6c30876dfa	6834	/****************** Bit definition for SPI_SR register ******************/
Kojto	122:f9eeca106725	6835	#define SPI_SR_RXNE 0x00000001U /!< Receive buffer Not Empty /
Kojto	122:f9eeca106725	6836	#define SPI_SR_TXE 0x00000002U /!< Transmit buffer Empty /
Kojto	122:f9eeca106725	6837	#define SPI_SR_CHSIDE 0x00000004U /!< Channel side /
Kojto	122:f9eeca106725	6838	#define SPI_SR_UDR 0x00000008U /!< Underrun flag /
Kojto	122:f9eeca106725	6839	#define SPI_SR_CRCERR 0x00000010U /!< CRC Error flag /
Kojto	122:f9eeca106725	6840	#define SPI_SR_MODF 0x00000020U /!< Mode fault /
Kojto	122:f9eeca106725	6841	#define SPI_SR_OVR 0x00000040U /!< Overrun flag /
Kojto	122:f9eeca106725	6842	#define SPI_SR_BSY 0x00000080U /!< Busy flag /
Kojto	122:f9eeca106725	6843	#define SPI_SR_FRE 0x00000100U /!< TI frame format error /
Kojto	122:f9eeca106725	6844	#define SPI_SR_FRLVL 0x00000600U /!< FIFO Reception Level /
Kojto	122:f9eeca106725	6845	#define SPI_SR_FRLVL_0 0x00000200U /!< Bit 0 /
Kojto	122:f9eeca106725	6846	#define SPI_SR_FRLVL_1 0x00000400U /!< Bit 1 /
Kojto	122:f9eeca106725	6847	#define SPI_SR_FTLVL 0x00001800U /!< FIFO Transmission Level /
Kojto	122:f9eeca106725	6848	#define SPI_SR_FTLVL_0 0x00000800U /!< Bit 0 /
Kojto	122:f9eeca106725	6849	#define SPI_SR_FTLVL_1 0x00001000U /!< Bit 1 /
Kojto	107:4f6c30876dfa	6850
Kojto	107:4f6c30876dfa	6851	/****************** Bit definition for SPI_DR register ******************/
Kojto	122:f9eeca106725	6852	#define SPI_DR_DR 0xFFFFU /!< Data Register /
Kojto	107:4f6c30876dfa	6853
Kojto	107:4f6c30876dfa	6854	/***************** Bit definition for SPI_CRCPR register ****************/
Kojto	122:f9eeca106725	6855	#define SPI_CRCPR_CRCPOLY 0xFFFFU /!< CRC polynomial register /
Kojto	107:4f6c30876dfa	6856
Kojto	107:4f6c30876dfa	6857	/**************** Bit definition for SPI_RXCRCR register ****************/
Kojto	122:f9eeca106725	6858	#define SPI_RXCRCR_RXCRC 0xFFFFU /!< Rx CRC Register /
Kojto	107:4f6c30876dfa	6859
Kojto	107:4f6c30876dfa	6860	/**************** Bit definition for SPI_TXCRCR register ****************/
Kojto	122:f9eeca106725	6861	#define SPI_TXCRCR_TXCRC 0xFFFFU /!< Tx CRC Register /
Kojto	107:4f6c30876dfa	6862
Kojto	107:4f6c30876dfa	6863	/**************** Bit definition for SPI_I2SCFGR register ***************/
Kojto	122:f9eeca106725	6864	#define SPI_I2SCFGR_CHLEN 0x00000001U /!<Channel length (number of bits per audio channel) /
Kojto	122:f9eeca106725	6865	#define SPI_I2SCFGR_DATLEN 0x00000006U /!<DATLEN[1:0] bits (Data length to be transferred) /
Kojto	122:f9eeca106725	6866	#define SPI_I2SCFGR_DATLEN_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	6867	#define SPI_I2SCFGR_DATLEN_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	6868	#define SPI_I2SCFGR_CKPOL 0x00000008U /!<steady state clock polarity /
Kojto	122:f9eeca106725	6869	#define SPI_I2SCFGR_I2SSTD 0x00000030U /!<I2SSTD[1:0] bits (I2S standard selection) /
Kojto	122:f9eeca106725	6870	#define SPI_I2SCFGR_I2SSTD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	6871	#define SPI_I2SCFGR_I2SSTD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	6872	#define SPI_I2SCFGR_PCMSYNC 0x00000080U /!<PCM frame synchronization /
Kojto	122:f9eeca106725	6873	#define SPI_I2SCFGR_I2SCFG 0x00000300U /!<I2SCFG[1:0] bits (I2S configuration mode) /
Kojto	122:f9eeca106725	6874	#define SPI_I2SCFGR_I2SCFG_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	6875	#define SPI_I2SCFGR_I2SCFG_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	6876	#define SPI_I2SCFGR_I2SE 0x00000400U /!<I2S Enable /
Kojto	122:f9eeca106725	6877	#define SPI_I2SCFGR_I2SMOD 0x00000800U /!<I2S mode selection /
Kojto	122:f9eeca106725	6878	#define SPI_I2SCFGR_ASTRTEN 0x00001000U /!<Asynchronous start enable /
Kojto	107:4f6c30876dfa	6879
Kojto	107:4f6c30876dfa	6880	/**************** Bit definition for SPI_I2SPR register *****************/
Kojto	122:f9eeca106725	6881	#define SPI_I2SPR_I2SDIV 0x00FFU /!<I2S Linear prescaler /
Kojto	122:f9eeca106725	6882	#define SPI_I2SPR_ODD 0x0100U /!<Odd factor for the prescaler /
Kojto	122:f9eeca106725	6883	#define SPI_I2SPR_MCKOE 0x0200U /!<Master Clock Output Enable /
Kojto	107:4f6c30876dfa	6884
Kojto	107:4f6c30876dfa	6885
Kojto	107:4f6c30876dfa	6886	/******************************************************************************/
Kojto	107:4f6c30876dfa	6887	/* */
Kojto	107:4f6c30876dfa	6888	/* SYSCFG */
Kojto	107:4f6c30876dfa	6889	/* */
Kojto	107:4f6c30876dfa	6890	/******************************************************************************/
Kojto	107:4f6c30876dfa	6891	/**************** Bit definition for SYSCFG_MEMRMP register *************/
Kojto	122:f9eeca106725	6892	#define SYSCFG_MEMRMP_MEM_BOOT 0x00000001U /!< Boot information after Reset /
Kojto	122:f9eeca106725	6893
Kojto	122:f9eeca106725	6894
Kojto	122:f9eeca106725	6895	#define SYSCFG_MEMRMP_SWP_FMC 0x00000C00U /!< FMC Memory Mapping swapping /
Kojto	122:f9eeca106725	6896	#define SYSCFG_MEMRMP_SWP_FMC_0 0x00000400U
Kojto	122:f9eeca106725	6897	#define SYSCFG_MEMRMP_SWP_FMC_1 0x00000800U
Kojto	107:4f6c30876dfa	6898
Kojto	107:4f6c30876dfa	6899	/**************** Bit definition for SYSCFG_PMC register ****************/
Kojto	116:c0f6e94411f5	6900
Kojto	122:f9eeca106725	6901	#define SYSCFG_PMC_ADCxDC2 0x00070000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	6902	#define SYSCFG_PMC_ADC1DC2 0x00010000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	6903	#define SYSCFG_PMC_ADC2DC2 0x00020000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	6904	#define SYSCFG_PMC_ADC3DC2 0x00040000U /!< Refer to AN4073 on how to use this bit /
Kojto	122:f9eeca106725	6905
Kojto	122:f9eeca106725	6906	#define SYSCFG_PMC_MII_RMII_SEL 0x00800000U /!<Ethernet PHY interface selection /
Kojto	107:4f6c30876dfa	6907
Kojto	107:4f6c30876dfa	6908	/*************** Bit definition for SYSCFG_EXTICR1 register *************/
Kojto	122:f9eeca106725	6909	#define SYSCFG_EXTICR1_EXTI0 0x000FU /!<EXTI 0 configuration /
Kojto	122:f9eeca106725	6910	#define SYSCFG_EXTICR1_EXTI1 0x00F0U /!<EXTI 1 configuration /
Kojto	122:f9eeca106725	6911	#define SYSCFG_EXTICR1_EXTI2 0x0F00U /!<EXTI 2 configuration /
Kojto	122:f9eeca106725	6912	#define SYSCFG_EXTICR1_EXTI3 0xF000U /!<EXTI 3 configuration /
Kojto	107:4f6c30876dfa	6913	/**
Kojto	107:4f6c30876dfa	6914	* @brief EXTI0 configuration
Kojto	107:4f6c30876dfa	6915	*/
Kojto	122:f9eeca106725	6916	#define SYSCFG_EXTICR1_EXTI0_PA 0x0000U /!<PA[0] pin /
Kojto	122:f9eeca106725	6917	#define SYSCFG_EXTICR1_EXTI0_PB 0x0001U /!<PB[0] pin /
Kojto	122:f9eeca106725	6918	#define SYSCFG_EXTICR1_EXTI0_PC 0x0002U /!<PC[0] pin /
Kojto	122:f9eeca106725	6919	#define SYSCFG_EXTICR1_EXTI0_PD 0x0003U /!<PD[0] pin /
Kojto	122:f9eeca106725	6920	#define SYSCFG_EXTICR1_EXTI0_PE 0x0004U /!<PE[0] pin /
Kojto	122:f9eeca106725	6921	#define SYSCFG_EXTICR1_EXTI0_PF 0x0005U /!<PF[0] pin /
Kojto	122:f9eeca106725	6922	#define SYSCFG_EXTICR1_EXTI0_PG 0x0006U /!<PG[0] pin /
Kojto	122:f9eeca106725	6923	#define SYSCFG_EXTICR1_EXTI0_PH 0x0007U /!<PH[0] pin /
Kojto	122:f9eeca106725	6924	#define SYSCFG_EXTICR1_EXTI0_PI 0x0008U /!<PI[0] pin /
Kojto	122:f9eeca106725	6925	#define SYSCFG_EXTICR1_EXTI0_PJ 0x0009U /!<PJ[0] pin /
Kojto	122:f9eeca106725	6926	#define SYSCFG_EXTICR1_EXTI0_PK 0x000AU /!<PK[0] pin /
Kojto	107:4f6c30876dfa	6927
Kojto	107:4f6c30876dfa	6928	/**
Kojto	107:4f6c30876dfa	6929	* @brief EXTI1 configuration
Kojto	107:4f6c30876dfa	6930	*/
Kojto	122:f9eeca106725	6931	#define SYSCFG_EXTICR1_EXTI1_PA 0x0000U /!<PA[1] pin /
Kojto	122:f9eeca106725	6932	#define SYSCFG_EXTICR1_EXTI1_PB 0x0010U /!<PB[1] pin /
Kojto	122:f9eeca106725	6933	#define SYSCFG_EXTICR1_EXTI1_PC 0x0020U /!<PC[1] pin /
Kojto	122:f9eeca106725	6934	#define SYSCFG_EXTICR1_EXTI1_PD 0x0030U /!<PD[1] pin /
Kojto	122:f9eeca106725	6935	#define SYSCFG_EXTICR1_EXTI1_PE 0x0040U /!<PE[1] pin /
Kojto	122:f9eeca106725	6936	#define SYSCFG_EXTICR1_EXTI1_PF 0x0050U /!<PF[1] pin /
Kojto	122:f9eeca106725	6937	#define SYSCFG_EXTICR1_EXTI1_PG 0x0060U /!<PG[1] pin /
Kojto	122:f9eeca106725	6938	#define SYSCFG_EXTICR1_EXTI1_PH 0x0070U /!<PH[1] pin /
Kojto	122:f9eeca106725	6939	#define SYSCFG_EXTICR1_EXTI1_PI 0x0080U /!<PI[1] pin /
Kojto	122:f9eeca106725	6940	#define SYSCFG_EXTICR1_EXTI1_PJ 0x0090U /!<PJ[1] pin /
Kojto	122:f9eeca106725	6941	#define SYSCFG_EXTICR1_EXTI1_PK 0x00A0U /!<PK[1] pin /
Kojto	107:4f6c30876dfa	6942
Kojto	107:4f6c30876dfa	6943	/**
Kojto	107:4f6c30876dfa	6944	* @brief EXTI2 configuration
Kojto	107:4f6c30876dfa	6945	*/
Kojto	122:f9eeca106725	6946	#define SYSCFG_EXTICR1_EXTI2_PA 0x0000U /!<PA[2] pin /
Kojto	122:f9eeca106725	6947	#define SYSCFG_EXTICR1_EXTI2_PB 0x0100U /!<PB[2] pin /
Kojto	122:f9eeca106725	6948	#define SYSCFG_EXTICR1_EXTI2_PC 0x0200U /!<PC[2] pin /
Kojto	122:f9eeca106725	6949	#define SYSCFG_EXTICR1_EXTI2_PD 0x0300U /!<PD[2] pin /
Kojto	122:f9eeca106725	6950	#define SYSCFG_EXTICR1_EXTI2_PE 0x0400U /!<PE[2] pin /
Kojto	122:f9eeca106725	6951	#define SYSCFG_EXTICR1_EXTI2_PF 0x0500U /!<PF[2] pin /
Kojto	122:f9eeca106725	6952	#define SYSCFG_EXTICR1_EXTI2_PG 0x0600U /!<PG[2] pin /
Kojto	122:f9eeca106725	6953	#define SYSCFG_EXTICR1_EXTI2_PH 0x0700U /!<PH[2] pin /
Kojto	122:f9eeca106725	6954	#define SYSCFG_EXTICR1_EXTI2_PI 0x0800U /!<PI[2] pin /
Kojto	122:f9eeca106725	6955	#define SYSCFG_EXTICR1_EXTI2_PJ 0x0900U /!<PJ[2] pin /
Kojto	122:f9eeca106725	6956	#define SYSCFG_EXTICR1_EXTI2_PK 0x0A00U /!<PK[2] pin /
Kojto	107:4f6c30876dfa	6957
Kojto	107:4f6c30876dfa	6958	/**
Kojto	107:4f6c30876dfa	6959	* @brief EXTI3 configuration
Kojto	107:4f6c30876dfa	6960	*/
Kojto	122:f9eeca106725	6961	#define SYSCFG_EXTICR1_EXTI3_PA 0x0000U /!<PA[3] pin /
Kojto	122:f9eeca106725	6962	#define SYSCFG_EXTICR1_EXTI3_PB 0x1000U /!<PB[3] pin /
Kojto	122:f9eeca106725	6963	#define SYSCFG_EXTICR1_EXTI3_PC 0x2000U /!<PC[3] pin /
Kojto	122:f9eeca106725	6964	#define SYSCFG_EXTICR1_EXTI3_PD 0x3000U /!<PD[3] pin /
Kojto	122:f9eeca106725	6965	#define SYSCFG_EXTICR1_EXTI3_PE 0x4000U /!<PE[3] pin /
Kojto	122:f9eeca106725	6966	#define SYSCFG_EXTICR1_EXTI3_PF 0x5000U /!<PF[3] pin /
Kojto	122:f9eeca106725	6967	#define SYSCFG_EXTICR1_EXTI3_PG 0x6000U /!<PG[3] pin /
Kojto	122:f9eeca106725	6968	#define SYSCFG_EXTICR1_EXTI3_PH 0x7000U /!<PH[3] pin /
Kojto	122:f9eeca106725	6969	#define SYSCFG_EXTICR1_EXTI3_PI 0x8000U /!<PI[3] pin /
Kojto	122:f9eeca106725	6970	#define SYSCFG_EXTICR1_EXTI3_PJ 0x9000U /!<PJ[3] pin /
Kojto	122:f9eeca106725	6971	#define SYSCFG_EXTICR1_EXTI3_PK 0xA000U /!<PK[3] pin /
Kojto	107:4f6c30876dfa	6972
Kojto	107:4f6c30876dfa	6973	/*************** Bit definition for SYSCFG_EXTICR2 register *************/
Kojto	122:f9eeca106725	6974	#define SYSCFG_EXTICR2_EXTI4 0x000FU /!<EXTI 4 configuration /
Kojto	122:f9eeca106725	6975	#define SYSCFG_EXTICR2_EXTI5 0x00F0U /!<EXTI 5 configuration /
Kojto	122:f9eeca106725	6976	#define SYSCFG_EXTICR2_EXTI6 0x0F00U /!<EXTI 6 configuration /
Kojto	122:f9eeca106725	6977	#define SYSCFG_EXTICR2_EXTI7 0xF000U /!<EXTI 7 configuration /
Kojto	107:4f6c30876dfa	6978	/**
Kojto	107:4f6c30876dfa	6979	* @brief EXTI4 configuration
Kojto	107:4f6c30876dfa	6980	*/
Kojto	122:f9eeca106725	6981	#define SYSCFG_EXTICR2_EXTI4_PA 0x0000U /!<PA[4] pin /
Kojto	122:f9eeca106725	6982	#define SYSCFG_EXTICR2_EXTI4_PB 0x0001U /!<PB[4] pin /
Kojto	122:f9eeca106725	6983	#define SYSCFG_EXTICR2_EXTI4_PC 0x0002U /!<PC[4] pin /
Kojto	122:f9eeca106725	6984	#define SYSCFG_EXTICR2_EXTI4_PD 0x0003U /!<PD[4] pin /
Kojto	122:f9eeca106725	6985	#define SYSCFG_EXTICR2_EXTI4_PE 0x0004U /!<PE[4] pin /
Kojto	122:f9eeca106725	6986	#define SYSCFG_EXTICR2_EXTI4_PF 0x0005U /!<PF[4] pin /
Kojto	122:f9eeca106725	6987	#define SYSCFG_EXTICR2_EXTI4_PG 0x0006U /!<PG[4] pin /
Kojto	122:f9eeca106725	6988	#define SYSCFG_EXTICR2_EXTI4_PH 0x0007U /!<PH[4] pin /
Kojto	122:f9eeca106725	6989	#define SYSCFG_EXTICR2_EXTI4_PI 0x0008U /!<PI[4] pin /
Kojto	122:f9eeca106725	6990	#define SYSCFG_EXTICR2_EXTI4_PJ 0x0009U /!<PJ[4] pin /
Kojto	122:f9eeca106725	6991	#define SYSCFG_EXTICR2_EXTI4_PK 0x000AU /!<PK[4] pin /
Kojto	107:4f6c30876dfa	6992
Kojto	107:4f6c30876dfa	6993	/**
Kojto	107:4f6c30876dfa	6994	* @brief EXTI5 configuration
Kojto	107:4f6c30876dfa	6995	*/
Kojto	122:f9eeca106725	6996	#define SYSCFG_EXTICR2_EXTI5_PA 0x0000U /!<PA[5] pin /
Kojto	122:f9eeca106725	6997	#define SYSCFG_EXTICR2_EXTI5_PB 0x0010U /!<PB[5] pin /
Kojto	122:f9eeca106725	6998	#define SYSCFG_EXTICR2_EXTI5_PC 0x0020U /!<PC[5] pin /
Kojto	122:f9eeca106725	6999	#define SYSCFG_EXTICR2_EXTI5_PD 0x0030U /!<PD[5] pin /
Kojto	122:f9eeca106725	7000	#define SYSCFG_EXTICR2_EXTI5_PE 0x0040U /!<PE[5] pin /
Kojto	122:f9eeca106725	7001	#define SYSCFG_EXTICR2_EXTI5_PF 0x0050U /!<PF[5] pin /
Kojto	122:f9eeca106725	7002	#define SYSCFG_EXTICR2_EXTI5_PG 0x0060U /!<PG[5] pin /
Kojto	122:f9eeca106725	7003	#define SYSCFG_EXTICR2_EXTI5_PH 0x0070U /!<PH[5] pin /
Kojto	122:f9eeca106725	7004	#define SYSCFG_EXTICR2_EXTI5_PI 0x0080U /!<PI[5] pin /
Kojto	122:f9eeca106725	7005	#define SYSCFG_EXTICR2_EXTI5_PJ 0x0090U /!<PJ[5] pin /
Kojto	122:f9eeca106725	7006	#define SYSCFG_EXTICR2_EXTI5_PK 0x00A0U /!<PK[5] pin /
Kojto	107:4f6c30876dfa	7007
Kojto	107:4f6c30876dfa	7008	/**
Kojto	107:4f6c30876dfa	7009	* @brief EXTI6 configuration
Kojto	107:4f6c30876dfa	7010	*/
Kojto	122:f9eeca106725	7011	#define SYSCFG_EXTICR2_EXTI6_PA 0x0000U /!<PA[6] pin /
Kojto	122:f9eeca106725	7012	#define SYSCFG_EXTICR2_EXTI6_PB 0x0100U /!<PB[6] pin /
Kojto	122:f9eeca106725	7013	#define SYSCFG_EXTICR2_EXTI6_PC 0x0200U /!<PC[6] pin /
Kojto	122:f9eeca106725	7014	#define SYSCFG_EXTICR2_EXTI6_PD 0x0300U /!<PD[6] pin /
Kojto	122:f9eeca106725	7015	#define SYSCFG_EXTICR2_EXTI6_PE 0x0400U /!<PE[6] pin /
Kojto	122:f9eeca106725	7016	#define SYSCFG_EXTICR2_EXTI6_PF 0x0500U /!<PF[6] pin /
Kojto	122:f9eeca106725	7017	#define SYSCFG_EXTICR2_EXTI6_PG 0x0600U /!<PG[6] pin /
Kojto	122:f9eeca106725	7018	#define SYSCFG_EXTICR2_EXTI6_PH 0x0700U /!<PH[6] pin /
Kojto	122:f9eeca106725	7019	#define SYSCFG_EXTICR2_EXTI6_PI 0x0800U /!<PI[6] pin /
Kojto	122:f9eeca106725	7020	#define SYSCFG_EXTICR2_EXTI6_PJ 0x0900U /!<PJ[6] pin /
Kojto	122:f9eeca106725	7021	#define SYSCFG_EXTICR2_EXTI6_PK 0x0A00U /!<PK[6] pin /
Kojto	107:4f6c30876dfa	7022
Kojto	107:4f6c30876dfa	7023	/**
Kojto	107:4f6c30876dfa	7024	* @brief EXTI7 configuration
Kojto	107:4f6c30876dfa	7025	*/
Kojto	122:f9eeca106725	7026	#define SYSCFG_EXTICR2_EXTI7_PA 0x0000U /!<PA[7] pin /
Kojto	122:f9eeca106725	7027	#define SYSCFG_EXTICR2_EXTI7_PB 0x1000U /!<PB[7] pin /
Kojto	122:f9eeca106725	7028	#define SYSCFG_EXTICR2_EXTI7_PC 0x2000U /!<PC[7] pin /
Kojto	122:f9eeca106725	7029	#define SYSCFG_EXTICR2_EXTI7_PD 0x3000U /!<PD[7] pin /
Kojto	122:f9eeca106725	7030	#define SYSCFG_EXTICR2_EXTI7_PE 0x4000U /!<PE[7] pin /
Kojto	122:f9eeca106725	7031	#define SYSCFG_EXTICR2_EXTI7_PF 0x5000U /!<PF[7] pin /
Kojto	122:f9eeca106725	7032	#define SYSCFG_EXTICR2_EXTI7_PG 0x6000U /!<PG[7] pin /
Kojto	122:f9eeca106725	7033	#define SYSCFG_EXTICR2_EXTI7_PH 0x7000U /!<PH[7] pin /
Kojto	122:f9eeca106725	7034	#define SYSCFG_EXTICR2_EXTI7_PI 0x8000U /!<PI[7] pin /
Kojto	122:f9eeca106725	7035	#define SYSCFG_EXTICR2_EXTI7_PJ 0x9000U /!<PJ[7] pin /
Kojto	122:f9eeca106725	7036	#define SYSCFG_EXTICR2_EXTI7_PK 0xA000U /!<PK[7] pin /
Kojto	107:4f6c30876dfa	7037
Kojto	107:4f6c30876dfa	7038	/*************** Bit definition for SYSCFG_EXTICR3 register *************/
Kojto	122:f9eeca106725	7039	#define SYSCFG_EXTICR3_EXTI8 0x000FU /!<EXTI 8 configuration /
Kojto	122:f9eeca106725	7040	#define SYSCFG_EXTICR3_EXTI9 0x00F0U /!<EXTI 9 configuration /
Kojto	122:f9eeca106725	7041	#define SYSCFG_EXTICR3_EXTI10 0x0F00U /!<EXTI 10 configuration /
Kojto	122:f9eeca106725	7042	#define SYSCFG_EXTICR3_EXTI11 0xF000U /!<EXTI 11 configuration /
Kojto	107:4f6c30876dfa	7043
Kojto	107:4f6c30876dfa	7044	/**
Kojto	107:4f6c30876dfa	7045	* @brief EXTI8 configuration
Kojto	107:4f6c30876dfa	7046	*/
Kojto	122:f9eeca106725	7047	#define SYSCFG_EXTICR3_EXTI8_PA 0x0000U /!<PA[8] pin /
Kojto	122:f9eeca106725	7048	#define SYSCFG_EXTICR3_EXTI8_PB 0x0001U /!<PB[8] pin /
Kojto	122:f9eeca106725	7049	#define SYSCFG_EXTICR3_EXTI8_PC 0x0002U /!<PC[8] pin /
Kojto	122:f9eeca106725	7050	#define SYSCFG_EXTICR3_EXTI8_PD 0x0003U /!<PD[8] pin /
Kojto	122:f9eeca106725	7051	#define SYSCFG_EXTICR3_EXTI8_PE 0x0004U /!<PE[8] pin /
Kojto	122:f9eeca106725	7052	#define SYSCFG_EXTICR3_EXTI8_PF 0x0005U /!<PF[8] pin /
Kojto	122:f9eeca106725	7053	#define SYSCFG_EXTICR3_EXTI8_PG 0x0006U /!<PG[8] pin /
Kojto	122:f9eeca106725	7054	#define SYSCFG_EXTICR3_EXTI8_PH 0x0007U /!<PH[8] pin /
Kojto	122:f9eeca106725	7055	#define SYSCFG_EXTICR3_EXTI8_PI 0x0008U /!<PI[8] pin /
Kojto	122:f9eeca106725	7056	#define SYSCFG_EXTICR3_EXTI8_PJ 0x0009U /!<PJ[8] pin /
Kojto	107:4f6c30876dfa	7057
Kojto	107:4f6c30876dfa	7058	/**
Kojto	107:4f6c30876dfa	7059	* @brief EXTI9 configuration
Kojto	107:4f6c30876dfa	7060	*/
Kojto	122:f9eeca106725	7061	#define SYSCFG_EXTICR3_EXTI9_PA 0x0000U /!<PA[9] pin /
Kojto	122:f9eeca106725	7062	#define SYSCFG_EXTICR3_EXTI9_PB 0x0010U /!<PB[9] pin /
Kojto	122:f9eeca106725	7063	#define SYSCFG_EXTICR3_EXTI9_PC 0x0020U /!<PC[9] pin /
Kojto	122:f9eeca106725	7064	#define SYSCFG_EXTICR3_EXTI9_PD 0x0030U /!<PD[9] pin /
Kojto	122:f9eeca106725	7065	#define SYSCFG_EXTICR3_EXTI9_PE 0x0040U /!<PE[9] pin /
Kojto	122:f9eeca106725	7066	#define SYSCFG_EXTICR3_EXTI9_PF 0x0050U /!<PF[9] pin /
Kojto	122:f9eeca106725	7067	#define SYSCFG_EXTICR3_EXTI9_PG 0x0060U /!<PG[9] pin /
Kojto	122:f9eeca106725	7068	#define SYSCFG_EXTICR3_EXTI9_PH 0x0070U /!<PH[9] pin /
Kojto	122:f9eeca106725	7069	#define SYSCFG_EXTICR3_EXTI9_PI 0x0080U /!<PI[9] pin /
Kojto	122:f9eeca106725	7070	#define SYSCFG_EXTICR3_EXTI9_PJ 0x0090U /!<PJ[9] pin /
Kojto	107:4f6c30876dfa	7071
Kojto	107:4f6c30876dfa	7072	/**
Kojto	107:4f6c30876dfa	7073	* @brief EXTI10 configuration
Kojto	107:4f6c30876dfa	7074	*/
Kojto	122:f9eeca106725	7075	#define SYSCFG_EXTICR3_EXTI10_PA 0x0000U /!<PA[10] pin /
Kojto	122:f9eeca106725	7076	#define SYSCFG_EXTICR3_EXTI10_PB 0x0100U /!<PB[10] pin /
Kojto	122:f9eeca106725	7077	#define SYSCFG_EXTICR3_EXTI10_PC 0x0200U /!<PC[10] pin /
Kojto	122:f9eeca106725	7078	#define SYSCFG_EXTICR3_EXTI10_PD 0x0300U /!<PD[10] pin /
Kojto	122:f9eeca106725	7079	#define SYSCFG_EXTICR3_EXTI10_PE 0x0400U /!<PE[10] pin /
Kojto	122:f9eeca106725	7080	#define SYSCFG_EXTICR3_EXTI10_PF 0x0500U /!<PF[10] pin /
Kojto	122:f9eeca106725	7081	#define SYSCFG_EXTICR3_EXTI10_PG 0x0600U /!<PG[10] pin /
Kojto	122:f9eeca106725	7082	#define SYSCFG_EXTICR3_EXTI10_PH 0x0700U /!<PH[10] pin /
Kojto	122:f9eeca106725	7083	#define SYSCFG_EXTICR3_EXTI10_PI 0x0800U /!<PI[10] pin /
Kojto	122:f9eeca106725	7084	#define SYSCFG_EXTICR3_EXTI10_PJ 0x0900U /!<PJ[10] pin /
Kojto	107:4f6c30876dfa	7085
Kojto	107:4f6c30876dfa	7086	/**
Kojto	107:4f6c30876dfa	7087	* @brief EXTI11 configuration
Kojto	107:4f6c30876dfa	7088	*/
Kojto	122:f9eeca106725	7089	#define SYSCFG_EXTICR3_EXTI11_PA 0x0000U /!<PA[11] pin /
Kojto	122:f9eeca106725	7090	#define SYSCFG_EXTICR3_EXTI11_PB 0x1000U /!<PB[11] pin /
Kojto	122:f9eeca106725	7091	#define SYSCFG_EXTICR3_EXTI11_PC 0x2000U /!<PC[11] pin /
Kojto	122:f9eeca106725	7092	#define SYSCFG_EXTICR3_EXTI11_PD 0x3000U /!<PD[11] pin /
Kojto	122:f9eeca106725	7093	#define SYSCFG_EXTICR3_EXTI11_PE 0x4000U /!<PE[11] pin /
Kojto	122:f9eeca106725	7094	#define SYSCFG_EXTICR3_EXTI11_PF 0x5000U /!<PF[11] pin /
Kojto	122:f9eeca106725	7095	#define SYSCFG_EXTICR3_EXTI11_PG 0x6000U /!<PG[11] pin /
Kojto	122:f9eeca106725	7096	#define SYSCFG_EXTICR3_EXTI11_PH 0x7000U /!<PH[11] pin /
Kojto	122:f9eeca106725	7097	#define SYSCFG_EXTICR3_EXTI11_PI 0x8000U /!<PI[11] pin /
Kojto	122:f9eeca106725	7098	#define SYSCFG_EXTICR3_EXTI11_PJ 0x9000U /!<PJ[11] pin /
Kojto	107:4f6c30876dfa	7099
Kojto	107:4f6c30876dfa	7100
Kojto	107:4f6c30876dfa	7101	/*************** Bit definition for SYSCFG_EXTICR4 register *************/
Kojto	122:f9eeca106725	7102	#define SYSCFG_EXTICR4_EXTI12 0x000FU /!<EXTI 12 configuration /
Kojto	122:f9eeca106725	7103	#define SYSCFG_EXTICR4_EXTI13 0x00F0U /!<EXTI 13 configuration /
Kojto	122:f9eeca106725	7104	#define SYSCFG_EXTICR4_EXTI14 0x0F00U /!<EXTI 14 configuration /
Kojto	122:f9eeca106725	7105	#define SYSCFG_EXTICR4_EXTI15 0xF000U /!<EXTI 15 configuration /
Kojto	107:4f6c30876dfa	7106	/**
Kojto	107:4f6c30876dfa	7107	* @brief EXTI12 configuration
Kojto	107:4f6c30876dfa	7108	*/
Kojto	122:f9eeca106725	7109	#define SYSCFG_EXTICR4_EXTI12_PA 0x0000U /!<PA[12] pin /
Kojto	122:f9eeca106725	7110	#define SYSCFG_EXTICR4_EXTI12_PB 0x0001U /!<PB[12] pin /
Kojto	122:f9eeca106725	7111	#define SYSCFG_EXTICR4_EXTI12_PC 0x0002U /!<PC[12] pin /
Kojto	122:f9eeca106725	7112	#define SYSCFG_EXTICR4_EXTI12_PD 0x0003U /!<PD[12] pin /
Kojto	122:f9eeca106725	7113	#define SYSCFG_EXTICR4_EXTI12_PE 0x0004U /!<PE[12] pin /
Kojto	122:f9eeca106725	7114	#define SYSCFG_EXTICR4_EXTI12_PF 0x0005U /!<PF[12] pin /
Kojto	122:f9eeca106725	7115	#define SYSCFG_EXTICR4_EXTI12_PG 0x0006U /!<PG[12] pin /
Kojto	122:f9eeca106725	7116	#define SYSCFG_EXTICR4_EXTI12_PH 0x0007U /!<PH[12] pin /
Kojto	122:f9eeca106725	7117	#define SYSCFG_EXTICR4_EXTI12_PI 0x0008U /!<PI[12] pin /
Kojto	122:f9eeca106725	7118	#define SYSCFG_EXTICR4_EXTI12_PJ 0x0009U /!<PJ[12] pin /
Kojto	107:4f6c30876dfa	7119
Kojto	107:4f6c30876dfa	7120	/**
Kojto	107:4f6c30876dfa	7121	* @brief EXTI13 configuration
Kojto	107:4f6c30876dfa	7122	*/
Kojto	122:f9eeca106725	7123	#define SYSCFG_EXTICR4_EXTI13_PA 0x0000U /!<PA[13] pin /
Kojto	122:f9eeca106725	7124	#define SYSCFG_EXTICR4_EXTI13_PB 0x0010U /!<PB[13] pin /
Kojto	122:f9eeca106725	7125	#define SYSCFG_EXTICR4_EXTI13_PC 0x0020U /!<PC[13] pin /
Kojto	122:f9eeca106725	7126	#define SYSCFG_EXTICR4_EXTI13_PD 0x0030U /!<PD[13] pin /
Kojto	122:f9eeca106725	7127	#define SYSCFG_EXTICR4_EXTI13_PE 0x0040U /!<PE[13] pin /
Kojto	122:f9eeca106725	7128	#define SYSCFG_EXTICR4_EXTI13_PF 0x0050U /!<PF[13] pin /
Kojto	122:f9eeca106725	7129	#define SYSCFG_EXTICR4_EXTI13_PG 0x0060U /!<PG[13] pin /
Kojto	122:f9eeca106725	7130	#define SYSCFG_EXTICR4_EXTI13_PH 0x0070U /!<PH[13] pin /
Kojto	122:f9eeca106725	7131	#define SYSCFG_EXTICR4_EXTI13_PI 0x0080U /!<PI[13] pin /
Kojto	122:f9eeca106725	7132	#define SYSCFG_EXTICR4_EXTI13_PJ 0x0090U /!<PJ[13] pin /
Kojto	107:4f6c30876dfa	7133
Kojto	107:4f6c30876dfa	7134	/**
Kojto	107:4f6c30876dfa	7135	* @brief EXTI14 configuration
Kojto	107:4f6c30876dfa	7136	*/
Kojto	122:f9eeca106725	7137	#define SYSCFG_EXTICR4_EXTI14_PA 0x0000U /!<PA[14] pin /
Kojto	122:f9eeca106725	7138	#define SYSCFG_EXTICR4_EXTI14_PB 0x0100U /!<PB[14] pin /
Kojto	122:f9eeca106725	7139	#define SYSCFG_EXTICR4_EXTI14_PC 0x0200U /!<PC[14] pin /
Kojto	122:f9eeca106725	7140	#define SYSCFG_EXTICR4_EXTI14_PD 0x0300U /!<PD[14] pin /
Kojto	122:f9eeca106725	7141	#define SYSCFG_EXTICR4_EXTI14_PE 0x0400U /!<PE[14] pin /
Kojto	122:f9eeca106725	7142	#define SYSCFG_EXTICR4_EXTI14_PF 0x0500U /!<PF[14] pin /
Kojto	122:f9eeca106725	7143	#define SYSCFG_EXTICR4_EXTI14_PG 0x0600U /!<PG[14] pin /
Kojto	122:f9eeca106725	7144	#define SYSCFG_EXTICR4_EXTI14_PH 0x0700U /!<PH[14] pin /
Kojto	122:f9eeca106725	7145	#define SYSCFG_EXTICR4_EXTI14_PI 0x0800U /!<PI[14] pin /
Kojto	122:f9eeca106725	7146	#define SYSCFG_EXTICR4_EXTI14_PJ 0x0900U /!<PJ[14] pin /
Kojto	107:4f6c30876dfa	7147
Kojto	107:4f6c30876dfa	7148	/**
Kojto	107:4f6c30876dfa	7149	* @brief EXTI15 configuration
Kojto	107:4f6c30876dfa	7150	*/
Kojto	122:f9eeca106725	7151	#define SYSCFG_EXTICR4_EXTI15_PA 0x0000U /!<PA[15] pin /
Kojto	122:f9eeca106725	7152	#define SYSCFG_EXTICR4_EXTI15_PB 0x1000U /!<PB[15] pin /
Kojto	122:f9eeca106725	7153	#define SYSCFG_EXTICR4_EXTI15_PC 0x2000U /!<PC[15] pin /
Kojto	122:f9eeca106725	7154	#define SYSCFG_EXTICR4_EXTI15_PD 0x3000U /!<PD[15] pin /
Kojto	122:f9eeca106725	7155	#define SYSCFG_EXTICR4_EXTI15_PE 0x4000U /!<PE[15] pin /
Kojto	122:f9eeca106725	7156	#define SYSCFG_EXTICR4_EXTI15_PF 0x5000U /!<PF[15] pin /
Kojto	122:f9eeca106725	7157	#define SYSCFG_EXTICR4_EXTI15_PG 0x6000U /!<PG[15] pin /
Kojto	122:f9eeca106725	7158	#define SYSCFG_EXTICR4_EXTI15_PH 0x7000U /!<PH[15] pin /
Kojto	122:f9eeca106725	7159	#define SYSCFG_EXTICR4_EXTI15_PI 0x8000U /!<PI[15] pin /
Kojto	122:f9eeca106725	7160	#define SYSCFG_EXTICR4_EXTI15_PJ 0x9000U /!<PJ[15] pin /
Kojto	122:f9eeca106725	7161
Kojto	107:4f6c30876dfa	7162
Kojto	107:4f6c30876dfa	7163	/**************** Bit definition for SYSCFG_CMPCR register **************/
Kojto	122:f9eeca106725	7164	#define SYSCFG_CMPCR_CMP_PD 0x00000001U /!<Compensation cell power-down /
Kojto	122:f9eeca106725	7165	#define SYSCFG_CMPCR_READY 0x00000100U /!<Compensation cell ready flag /
Kojto	107:4f6c30876dfa	7166
Kojto	107:4f6c30876dfa	7167	/******************************************************************************/
Kojto	107:4f6c30876dfa	7168	/* */
Kojto	107:4f6c30876dfa	7169	/* TIM */
Kojto	107:4f6c30876dfa	7170	/* */
Kojto	107:4f6c30876dfa	7171	/******************************************************************************/
Kojto	107:4f6c30876dfa	7172	/***************** Bit definition for TIM_CR1 register ******************/
Kojto	122:f9eeca106725	7173	#define TIM_CR1_CEN 0x0001U /!<Counter enable /
Kojto	122:f9eeca106725	7174	#define TIM_CR1_UDIS 0x0002U /!<Update disable /
Kojto	122:f9eeca106725	7175	#define TIM_CR1_URS 0x0004U /!<Update request source /
Kojto	122:f9eeca106725	7176	#define TIM_CR1_OPM 0x0008U /!<One pulse mode /
Kojto	122:f9eeca106725	7177	#define TIM_CR1_DIR 0x0010U /!<Direction /
Kojto	122:f9eeca106725	7178
Kojto	122:f9eeca106725	7179	#define TIM_CR1_CMS 0x0060U /!<CMS[1:0] bits (Center-aligned mode selection) /
Kojto	122:f9eeca106725	7180	#define TIM_CR1_CMS_0 0x0020U /!<Bit 0 /
Kojto	122:f9eeca106725	7181	#define TIM_CR1_CMS_1 0x0040U /!<Bit 1 /
Kojto	122:f9eeca106725	7182
Kojto	122:f9eeca106725	7183	#define TIM_CR1_ARPE 0x0080U /!<Auto-reload preload enable /
Kojto	122:f9eeca106725	7184
Kojto	122:f9eeca106725	7185	#define TIM_CR1_CKD 0x0300U /!<CKD[1:0] bits (clock division) /
Kojto	122:f9eeca106725	7186	#define TIM_CR1_CKD_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	7187	#define TIM_CR1_CKD_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	7188	#define TIM_CR1_UIFREMAP 0x0800U /!<UIF status bit /
Kojto	107:4f6c30876dfa	7189
Kojto	107:4f6c30876dfa	7190	/***************** Bit definition for TIM_CR2 register ******************/
Kojto	122:f9eeca106725	7191	#define TIM_CR2_CCPC 0x00000001U /!<Capture/Compare Preloaded Control /
Kojto	122:f9eeca106725	7192	#define TIM_CR2_CCUS 0x00000004U /!<Capture/Compare Control Update Selection /
Kojto	122:f9eeca106725	7193	#define TIM_CR2_CCDS 0x00000008U /!<Capture/Compare DMA Selection /
Kojto	122:f9eeca106725	7194
Kojto	122:f9eeca106725	7195	#define TIM_CR2_OIS5 0x00010000U /!<Output Idle state 4 (OC4 output) /
Kojto	122:f9eeca106725	7196	#define TIM_CR2_OIS6 0x00040000U /!<Output Idle state 4 (OC4 output) /
Kojto	122:f9eeca106725	7197
Kojto	122:f9eeca106725	7198	#define TIM_CR2_MMS 0x0070U /!<MMS[2:0] bits (Master Mode Selection) /
Kojto	122:f9eeca106725	7199	#define TIM_CR2_MMS_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	7200	#define TIM_CR2_MMS_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	7201	#define TIM_CR2_MMS_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	7202
Kojto	122:f9eeca106725	7203	#define TIM_CR2_MMS2 0x00F00000U /!<MMS[2:0] bits (Master Mode Selection) /
Kojto	122:f9eeca106725	7204	#define TIM_CR2_MMS2_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	7205	#define TIM_CR2_MMS2_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	7206	#define TIM_CR2_MMS2_2 0x00400000U /!<Bit 2 /
Kojto	122:f9eeca106725	7207	#define TIM_CR2_MMS2_3 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	7208
Kojto	122:f9eeca106725	7209	#define TIM_CR2_TI1S 0x0080U /!<TI1 Selection /
Kojto	122:f9eeca106725	7210	#define TIM_CR2_OIS1 0x0100U /!<Output Idle state 1 (OC1 output) /
Kojto	122:f9eeca106725	7211	#define TIM_CR2_OIS1N 0x0200U /!<Output Idle state 1 (OC1N output) /
Kojto	122:f9eeca106725	7212	#define TIM_CR2_OIS2 0x0400U /!<Output Idle state 2 (OC2 output) /
Kojto	122:f9eeca106725	7213	#define TIM_CR2_OIS2N 0x0800U /!<Output Idle state 2 (OC2N output) /
Kojto	122:f9eeca106725	7214	#define TIM_CR2_OIS3 0x1000U /!<Output Idle state 3 (OC3 output) /
Kojto	122:f9eeca106725	7215	#define TIM_CR2_OIS3N 0x2000U /!<Output Idle state 3 (OC3N output) /
Kojto	122:f9eeca106725	7216	#define TIM_CR2_OIS4 0x4000U /!<Output Idle state 4 (OC4 output) /
Kojto	107:4f6c30876dfa	7217
Kojto	107:4f6c30876dfa	7218	/***************** Bit definition for TIM_SMCR register *****************/
Kojto	122:f9eeca106725	7219	#define TIM_SMCR_SMS 0x00010007U /!<SMS[2:0] bits (Slave mode selection) /
Kojto	122:f9eeca106725	7220	#define TIM_SMCR_SMS_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7221	#define TIM_SMCR_SMS_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7222	#define TIM_SMCR_SMS_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	7223	#define TIM_SMCR_SMS_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	7224	#define TIM_SMCR_OCCS 0x00000008U /!< OCREF clear selection /
Kojto	122:f9eeca106725	7225
Kojto	122:f9eeca106725	7226	#define TIM_SMCR_TS 0x0070U /!<TS[2:0] bits (Trigger selection) /
Kojto	122:f9eeca106725	7227	#define TIM_SMCR_TS_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	7228	#define TIM_SMCR_TS_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	7229	#define TIM_SMCR_TS_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	7230
Kojto	122:f9eeca106725	7231	#define TIM_SMCR_MSM 0x0080U /!<Master/slave mode /
Kojto	122:f9eeca106725	7232
Kojto	122:f9eeca106725	7233	#define TIM_SMCR_ETF 0x0F00U /!<ETF[3:0] bits (External trigger filter) /
Kojto	122:f9eeca106725	7234	#define TIM_SMCR_ETF_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	7235	#define TIM_SMCR_ETF_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	7236	#define TIM_SMCR_ETF_2 0x0400U /!<Bit 2 /
Kojto	122:f9eeca106725	7237	#define TIM_SMCR_ETF_3 0x0800U /!<Bit 3 /
Kojto	122:f9eeca106725	7238
Kojto	122:f9eeca106725	7239	#define TIM_SMCR_ETPS 0x3000U /!<ETPS[1:0] bits (External trigger prescaler) /
Kojto	122:f9eeca106725	7240	#define TIM_SMCR_ETPS_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	7241	#define TIM_SMCR_ETPS_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	7242
Kojto	122:f9eeca106725	7243	#define TIM_SMCR_ECE 0x4000U /!<External clock enable /
Kojto	122:f9eeca106725	7244	#define TIM_SMCR_ETP 0x8000U /!<External trigger polarity /
Kojto	107:4f6c30876dfa	7245
Kojto	107:4f6c30876dfa	7246	/***************** Bit definition for TIM_DIER register *****************/
Kojto	122:f9eeca106725	7247	#define TIM_DIER_UIE 0x0001U /!<Update interrupt enable /
Kojto	122:f9eeca106725	7248	#define TIM_DIER_CC1IE 0x0002U /!<Capture/Compare 1 interrupt enable /
Kojto	122:f9eeca106725	7249	#define TIM_DIER_CC2IE 0x0004U /!<Capture/Compare 2 interrupt enable /
Kojto	122:f9eeca106725	7250	#define TIM_DIER_CC3IE 0x0008U /!<Capture/Compare 3 interrupt enable /
Kojto	122:f9eeca106725	7251	#define TIM_DIER_CC4IE 0x0010U /!<Capture/Compare 4 interrupt enable /
Kojto	122:f9eeca106725	7252	#define TIM_DIER_COMIE 0x0020U /!<COM interrupt enable /
Kojto	122:f9eeca106725	7253	#define TIM_DIER_TIE 0x0040U /!<Trigger interrupt enable /
Kojto	122:f9eeca106725	7254	#define TIM_DIER_BIE 0x0080U /!<Break interrupt enable /
Kojto	122:f9eeca106725	7255	#define TIM_DIER_UDE 0x0100U /!<Update DMA request enable /
Kojto	122:f9eeca106725	7256	#define TIM_DIER_CC1DE 0x0200U /!<Capture/Compare 1 DMA request enable /
Kojto	122:f9eeca106725	7257	#define TIM_DIER_CC2DE 0x0400U /!<Capture/Compare 2 DMA request enable /
Kojto	122:f9eeca106725	7258	#define TIM_DIER_CC3DE 0x0800U /!<Capture/Compare 3 DMA request enable /
Kojto	122:f9eeca106725	7259	#define TIM_DIER_CC4DE 0x1000U /!<Capture/Compare 4 DMA request enable /
Kojto	122:f9eeca106725	7260	#define TIM_DIER_COMDE 0x2000U /!<COM DMA request enable /
Kojto	122:f9eeca106725	7261	#define TIM_DIER_TDE 0x4000U /!<Trigger DMA request enable /
Kojto	107:4f6c30876dfa	7262
Kojto	107:4f6c30876dfa	7263	/****************** Bit definition for TIM_SR register ******************/
Kojto	122:f9eeca106725	7264	#define TIM_SR_UIF 0x0001U /!<Update interrupt Flag /
Kojto	122:f9eeca106725	7265	#define TIM_SR_CC1IF 0x0002U /!<Capture/Compare 1 interrupt Flag /
Kojto	122:f9eeca106725	7266	#define TIM_SR_CC2IF 0x0004U /!<Capture/Compare 2 interrupt Flag /
Kojto	122:f9eeca106725	7267	#define TIM_SR_CC3IF 0x0008U /!<Capture/Compare 3 interrupt Flag /
Kojto	122:f9eeca106725	7268	#define TIM_SR_CC4IF 0x0010U /!<Capture/Compare 4 interrupt Flag /
Kojto	122:f9eeca106725	7269	#define TIM_SR_COMIF 0x0020U /!<COM interrupt Flag /
Kojto	122:f9eeca106725	7270	#define TIM_SR_TIF 0x0040U /!<Trigger interrupt Flag /
Kojto	122:f9eeca106725	7271	#define TIM_SR_BIF 0x0080U /!<Break interrupt Flag /
Kojto	122:f9eeca106725	7272	#define TIM_SR_B2IF 0x0100U /!<Break2 interrupt Flag /
Kojto	122:f9eeca106725	7273	#define TIM_SR_CC1OF 0x0200U /!<Capture/Compare 1 Overcapture Flag /
Kojto	122:f9eeca106725	7274	#define TIM_SR_CC2OF 0x0400U /!<Capture/Compare 2 Overcapture Flag /
Kojto	122:f9eeca106725	7275	#define TIM_SR_CC3OF 0x0800U /!<Capture/Compare 3 Overcapture Flag /
Kojto	122:f9eeca106725	7276	#define TIM_SR_CC4OF 0x1000U /!<Capture/Compare 4 Overcapture Flag /
Kojto	107:4f6c30876dfa	7277
Kojto	107:4f6c30876dfa	7278	/***************** Bit definition for TIM_EGR register ******************/
Kojto	122:f9eeca106725	7279	#define TIM_EGR_UG 0x00000001U /!<Update Generation /
Kojto	122:f9eeca106725	7280	#define TIM_EGR_CC1G 0x00000002U /!<Capture/Compare 1 Generation /
Kojto	122:f9eeca106725	7281	#define TIM_EGR_CC2G 0x00000004U /!<Capture/Compare 2 Generation /
Kojto	122:f9eeca106725	7282	#define TIM_EGR_CC3G 0x00000008U /!<Capture/Compare 3 Generation /
Kojto	122:f9eeca106725	7283	#define TIM_EGR_CC4G 0x00000010U /!<Capture/Compare 4 Generation /
Kojto	122:f9eeca106725	7284	#define TIM_EGR_COMG 0x00000020U /!<Capture/Compare Control Update Generation /
Kojto	122:f9eeca106725	7285	#define TIM_EGR_TG 0x00000040U /!<Trigger Generation /
Kojto	122:f9eeca106725	7286	#define TIM_EGR_BG 0x00000080U /!<Break Generation /
Kojto	122:f9eeca106725	7287	#define TIM_EGR_B2G 0x00000100U /!<Break2 Generation /
Kojto	107:4f6c30876dfa	7288
Kojto	107:4f6c30876dfa	7289	/**************** Bit definition for TIM_CCMR1 register *****************/
Kojto	122:f9eeca106725	7290	#define TIM_CCMR1_CC1S 0x00000003U /!<CC1S[1:0] bits (Capture/Compare 1 Selection) /
Kojto	122:f9eeca106725	7291	#define TIM_CCMR1_CC1S_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7292	#define TIM_CCMR1_CC1S_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7293
Kojto	122:f9eeca106725	7294	#define TIM_CCMR1_OC1FE 0x00000004U /!<Output Compare 1 Fast enable /
Kojto	122:f9eeca106725	7295	#define TIM_CCMR1_OC1PE 0x00000008U /!<Output Compare 1 Preload enable /
Kojto	122:f9eeca106725	7296
Kojto	122:f9eeca106725	7297	#define TIM_CCMR1_OC1M 0x00010070U /!<OC1M[2:0] bits (Output Compare 1 Mode) /
Kojto	122:f9eeca106725	7298	#define TIM_CCMR1_OC1M_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	7299	#define TIM_CCMR1_OC1M_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	7300	#define TIM_CCMR1_OC1M_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	7301	#define TIM_CCMR1_OC1M_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	7302
Kojto	122:f9eeca106725	7303	#define TIM_CCMR1_OC1CE 0x00000080U /!<Output Compare 1Clear Enable /
Kojto	122:f9eeca106725	7304
Kojto	122:f9eeca106725	7305	#define TIM_CCMR1_CC2S 0x00000300U /!<CC2S[1:0] bits (Capture/Compare 2 Selection) /
Kojto	122:f9eeca106725	7306	#define TIM_CCMR1_CC2S_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	7307	#define TIM_CCMR1_CC2S_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	7308
Kojto	122:f9eeca106725	7309	#define TIM_CCMR1_OC2FE 0x00000400U /!<Output Compare 2 Fast enable /
Kojto	122:f9eeca106725	7310	#define TIM_CCMR1_OC2PE 0x00000800U /!<Output Compare 2 Preload enable /
Kojto	122:f9eeca106725	7311
Kojto	122:f9eeca106725	7312	#define TIM_CCMR1_OC2M 0x01007000U /!<OC2M[2:0] bits (Output Compare 2 Mode) /
Kojto	122:f9eeca106725	7313	#define TIM_CCMR1_OC2M_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	7314	#define TIM_CCMR1_OC2M_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	7315	#define TIM_CCMR1_OC2M_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	7316	#define TIM_CCMR1_OC2M_3 0x01000000U /!<Bit 3 /
Kojto	122:f9eeca106725	7317
Kojto	122:f9eeca106725	7318	#define TIM_CCMR1_OC2CE 0x00008000U /!<Output Compare 2 Clear Enable /
Kojto	107:4f6c30876dfa	7319
Kojto	107:4f6c30876dfa	7320	/----------------------------------------------------------------------------/
Kojto	107:4f6c30876dfa	7321
Kojto	122:f9eeca106725	7322	#define TIM_CCMR1_IC1PSC 0x000CU /!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) /
Kojto	122:f9eeca106725	7323	#define TIM_CCMR1_IC1PSC_0 0x0004U /!<Bit 0 /
Kojto	122:f9eeca106725	7324	#define TIM_CCMR1_IC1PSC_1 0x0008U /!<Bit 1 /
Kojto	122:f9eeca106725	7325
Kojto	122:f9eeca106725	7326	#define TIM_CCMR1_IC1F 0x00F0U /!<IC1F[3:0] bits (Input Capture 1 Filter) /
Kojto	122:f9eeca106725	7327	#define TIM_CCMR1_IC1F_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	7328	#define TIM_CCMR1_IC1F_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	7329	#define TIM_CCMR1_IC1F_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	7330	#define TIM_CCMR1_IC1F_3 0x0080U /!<Bit 3 /
Kojto	122:f9eeca106725	7331
Kojto	122:f9eeca106725	7332	#define TIM_CCMR1_IC2PSC 0x0C00U /!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) /
Kojto	122:f9eeca106725	7333	#define TIM_CCMR1_IC2PSC_0 0x0400U /!<Bit 0 /
Kojto	122:f9eeca106725	7334	#define TIM_CCMR1_IC2PSC_1 0x0800U /!<Bit 1 /
Kojto	122:f9eeca106725	7335
Kojto	122:f9eeca106725	7336	#define TIM_CCMR1_IC2F 0xF000U /!<IC2F[3:0] bits (Input Capture 2 Filter) /
Kojto	122:f9eeca106725	7337	#define TIM_CCMR1_IC2F_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	7338	#define TIM_CCMR1_IC2F_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	7339	#define TIM_CCMR1_IC2F_2 0x4000U /!<Bit 2 /
Kojto	122:f9eeca106725	7340	#define TIM_CCMR1_IC2F_3 0x8000U /!<Bit 3 /
Kojto	107:4f6c30876dfa	7341
Kojto	107:4f6c30876dfa	7342	/**************** Bit definition for TIM_CCMR2 register *****************/
Kojto	122:f9eeca106725	7343	#define TIM_CCMR2_CC3S 0x00000003U /!<CC3S[1:0] bits (Capture/Compare 3 Selection) /
Kojto	122:f9eeca106725	7344	#define TIM_CCMR2_CC3S_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7345	#define TIM_CCMR2_CC3S_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7346
Kojto	122:f9eeca106725	7347	#define TIM_CCMR2_OC3FE 0x00000004U /!<Output Compare 3 Fast enable /
Kojto	122:f9eeca106725	7348	#define TIM_CCMR2_OC3PE 0x00000008U /!<Output Compare 3 Preload enable /
Kojto	122:f9eeca106725	7349
Kojto	122:f9eeca106725	7350	#define TIM_CCMR2_OC3M 0x00010070U /!<OC3M[2:0] bits (Output Compare 3 Mode) /
Kojto	122:f9eeca106725	7351	#define TIM_CCMR2_OC3M_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	7352	#define TIM_CCMR2_OC3M_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	7353	#define TIM_CCMR2_OC3M_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	7354	#define TIM_CCMR2_OC3M_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	7355
Kojto	122:f9eeca106725	7356
Kojto	122:f9eeca106725	7357
Kojto	122:f9eeca106725	7358	#define TIM_CCMR2_OC3CE 0x00000080U /!<Output Compare 3 Clear Enable /
Kojto	122:f9eeca106725	7359
Kojto	122:f9eeca106725	7360	#define TIM_CCMR2_CC4S 0x00000300U /!<CC4S[1:0] bits (Capture/Compare 4 Selection) /
Kojto	122:f9eeca106725	7361	#define TIM_CCMR2_CC4S_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	7362	#define TIM_CCMR2_CC4S_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	7363
Kojto	122:f9eeca106725	7364	#define TIM_CCMR2_OC4FE 0x00000400U /!<Output Compare 4 Fast enable /
Kojto	122:f9eeca106725	7365	#define TIM_CCMR2_OC4PE 0x00000800U /!<Output Compare 4 Preload enable /
Kojto	122:f9eeca106725	7366
Kojto	122:f9eeca106725	7367	#define TIM_CCMR2_OC4M 0x01007000U /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Kojto	122:f9eeca106725	7368	#define TIM_CCMR2_OC4M_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	7369	#define TIM_CCMR2_OC4M_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	7370	#define TIM_CCMR2_OC4M_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	7371	#define TIM_CCMR2_OC4M_3 0x01000000U /!<Bit 3 /
Kojto	122:f9eeca106725	7372
Kojto	122:f9eeca106725	7373	#define TIM_CCMR2_OC4CE 0x8000U /!<Output Compare 4 Clear Enable /
Kojto	107:4f6c30876dfa	7374
Kojto	107:4f6c30876dfa	7375	/----------------------------------------------------------------------------/
Kojto	107:4f6c30876dfa	7376
Kojto	122:f9eeca106725	7377	#define TIM_CCMR2_IC3PSC 0x000CU /!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) /
Kojto	122:f9eeca106725	7378	#define TIM_CCMR2_IC3PSC_0 0x0004U /!<Bit 0 /
Kojto	122:f9eeca106725	7379	#define TIM_CCMR2_IC3PSC_1 0x0008U /!<Bit 1 /
Kojto	122:f9eeca106725	7380
Kojto	122:f9eeca106725	7381	#define TIM_CCMR2_IC3F 0x00F0U /!<IC3F[3:0] bits (Input Capture 3 Filter) /
Kojto	122:f9eeca106725	7382	#define TIM_CCMR2_IC3F_0 0x0010U /!<Bit 0 /
Kojto	122:f9eeca106725	7383	#define TIM_CCMR2_IC3F_1 0x0020U /!<Bit 1 /
Kojto	122:f9eeca106725	7384	#define TIM_CCMR2_IC3F_2 0x0040U /!<Bit 2 /
Kojto	122:f9eeca106725	7385	#define TIM_CCMR2_IC3F_3 0x0080U /!<Bit 3 /
Kojto	122:f9eeca106725	7386
Kojto	122:f9eeca106725	7387	#define TIM_CCMR2_IC4PSC 0x0C00U /!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) /
Kojto	122:f9eeca106725	7388	#define TIM_CCMR2_IC4PSC_0 0x0400U /!<Bit 0 /
Kojto	122:f9eeca106725	7389	#define TIM_CCMR2_IC4PSC_1 0x0800U /!<Bit 1 /
Kojto	122:f9eeca106725	7390
Kojto	122:f9eeca106725	7391	#define TIM_CCMR2_IC4F 0xF000U /!<IC4F[3:0] bits (Input Capture 4 Filter) /
Kojto	122:f9eeca106725	7392	#define TIM_CCMR2_IC4F_0 0x1000U /!<Bit 0 /
Kojto	122:f9eeca106725	7393	#define TIM_CCMR2_IC4F_1 0x2000U /!<Bit 1 /
Kojto	122:f9eeca106725	7394	#define TIM_CCMR2_IC4F_2 0x4000U /!<Bit 2 /
Kojto	122:f9eeca106725	7395	#define TIM_CCMR2_IC4F_3 0x8000U /!<Bit 3 /
Kojto	107:4f6c30876dfa	7396
Kojto	107:4f6c30876dfa	7397	/***************** Bit definition for TIM_CCER register *****************/
Kojto	122:f9eeca106725	7398	#define TIM_CCER_CC1E 0x00000001U /!<Capture/Compare 1 output enable /
Kojto	122:f9eeca106725	7399	#define TIM_CCER_CC1P 0x00000002U /!<Capture/Compare 1 output Polarity /
Kojto	122:f9eeca106725	7400	#define TIM_CCER_CC1NE 0x00000004U /!<Capture/Compare 1 Complementary output enable /
Kojto	122:f9eeca106725	7401	#define TIM_CCER_CC1NP 0x00000008U /!<Capture/Compare 1 Complementary output Polarity /
Kojto	122:f9eeca106725	7402	#define TIM_CCER_CC2E 0x00000010U /!<Capture/Compare 2 output enable /
Kojto	122:f9eeca106725	7403	#define TIM_CCER_CC2P 0x00000020U /!<Capture/Compare 2 output Polarity /
Kojto	122:f9eeca106725	7404	#define TIM_CCER_CC2NE 0x00000040U /!<Capture/Compare 2 Complementary output enable /
Kojto	122:f9eeca106725	7405	#define TIM_CCER_CC2NP 0x00000080U /!<Capture/Compare 2 Complementary output Polarity /
Kojto	122:f9eeca106725	7406	#define TIM_CCER_CC3E 0x00000100U /!<Capture/Compare 3 output enable /
Kojto	122:f9eeca106725	7407	#define TIM_CCER_CC3P 0x00000200U /!<Capture/Compare 3 output Polarity /
Kojto	122:f9eeca106725	7408	#define TIM_CCER_CC3NE 0x00000400U /!<Capture/Compare 3 Complementary output enable /
Kojto	122:f9eeca106725	7409	#define TIM_CCER_CC3NP 0x00000800U /!<Capture/Compare 3 Complementary output Polarity /
Kojto	122:f9eeca106725	7410	#define TIM_CCER_CC4E 0x00001000U /!<Capture/Compare 4 output enable /
Kojto	122:f9eeca106725	7411	#define TIM_CCER_CC4P 0x00002000U /!<Capture/Compare 4 output Polarity /
Kojto	122:f9eeca106725	7412	#define TIM_CCER_CC4NP 0x00008000U /!<Capture/Compare 4 Complementary output Polarity /
Kojto	122:f9eeca106725	7413	#define TIM_CCER_CC5E 0x00010000U /!<Capture/Compare 5 output enable /
Kojto	122:f9eeca106725	7414	#define TIM_CCER_CC5P 0x00020000U /!<Capture/Compare 5 output Polarity /
Kojto	122:f9eeca106725	7415	#define TIM_CCER_CC6E 0x00100000U /!<Capture/Compare 6 output enable /
Kojto	122:f9eeca106725	7416	#define TIM_CCER_CC6P 0x00200000U /!<Capture/Compare 6 output Polarity /
Kojto	107:4f6c30876dfa	7417
Kojto	107:4f6c30876dfa	7418
Kojto	107:4f6c30876dfa	7419	/***************** Bit definition for TIM_CNT register ******************/
Kojto	122:f9eeca106725	7420	#define TIM_CNT_CNT 0xFFFFU /!<Counter Value /
Kojto	107:4f6c30876dfa	7421
Kojto	107:4f6c30876dfa	7422	/***************** Bit definition for TIM_PSC register ******************/
Kojto	122:f9eeca106725	7423	#define TIM_PSC_PSC 0xFFFFU /!<Prescaler Value /
Kojto	107:4f6c30876dfa	7424
Kojto	107:4f6c30876dfa	7425	/***************** Bit definition for TIM_ARR register ******************/
Kojto	122:f9eeca106725	7426	#define TIM_ARR_ARR 0xFFFFU /!<actual auto-reload Value /
Kojto	107:4f6c30876dfa	7427
Kojto	107:4f6c30876dfa	7428	/***************** Bit definition for TIM_RCR register ******************/
Kojto	122:f9eeca106725	7429	#define TIM_RCR_REP ((uint8_t)0xFFU) /!<Repetition Counter Value /
Kojto	107:4f6c30876dfa	7430
Kojto	107:4f6c30876dfa	7431	/***************** Bit definition for TIM_CCR1 register *****************/
Kojto	122:f9eeca106725	7432	#define TIM_CCR1_CCR1 0xFFFFU /!<Capture/Compare 1 Value /
Kojto	107:4f6c30876dfa	7433
Kojto	107:4f6c30876dfa	7434	/***************** Bit definition for TIM_CCR2 register *****************/
Kojto	122:f9eeca106725	7435	#define TIM_CCR2_CCR2 0xFFFFU /!<Capture/Compare 2 Value /
Kojto	107:4f6c30876dfa	7436
Kojto	107:4f6c30876dfa	7437	/***************** Bit definition for TIM_CCR3 register *****************/
Kojto	122:f9eeca106725	7438	#define TIM_CCR3_CCR3 0xFFFFU /!<Capture/Compare 3 Value /
Kojto	107:4f6c30876dfa	7439
Kojto	107:4f6c30876dfa	7440	/***************** Bit definition for TIM_CCR4 register *****************/
Kojto	122:f9eeca106725	7441	#define TIM_CCR4_CCR4 0xFFFFU /!<Capture/Compare 4 Value /
Kojto	107:4f6c30876dfa	7442
Kojto	107:4f6c30876dfa	7443	/***************** Bit definition for TIM_BDTR register *****************/
Kojto	122:f9eeca106725	7444	#define TIM_BDTR_DTG 0x000000FFU /!<DTG[0:7] bits (Dead-Time Generator set-up) /
Kojto	122:f9eeca106725	7445	#define TIM_BDTR_DTG_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	7446	#define TIM_BDTR_DTG_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	7447	#define TIM_BDTR_DTG_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	7448	#define TIM_BDTR_DTG_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	7449	#define TIM_BDTR_DTG_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	7450	#define TIM_BDTR_DTG_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	7451	#define TIM_BDTR_DTG_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	7452	#define TIM_BDTR_DTG_7 0x00000080U /!<Bit 7 /
Kojto	122:f9eeca106725	7453
Kojto	122:f9eeca106725	7454	#define TIM_BDTR_LOCK 0x00000300U /!<LOCK[1:0] bits (Lock Configuration) /
Kojto	122:f9eeca106725	7455	#define TIM_BDTR_LOCK_0 0x00000100U /!<Bit 0 /
Kojto	122:f9eeca106725	7456	#define TIM_BDTR_LOCK_1 0x00000200U /!<Bit 1 /
Kojto	122:f9eeca106725	7457
Kojto	122:f9eeca106725	7458	#define TIM_BDTR_OSSI 0x00000400U /!<Off-State Selection for Idle mode /
Kojto	122:f9eeca106725	7459	#define TIM_BDTR_OSSR 0x00000800U /!<Off-State Selection for Run mode /
Kojto	122:f9eeca106725	7460	#define TIM_BDTR_BKE 0x00001000U /!<Break enable /
Kojto	122:f9eeca106725	7461	#define TIM_BDTR_BKP 0x00002000U /!<Break Polarity /
Kojto	122:f9eeca106725	7462	#define TIM_BDTR_AOE 0x00004000U /!<Automatic Output enable /
Kojto	122:f9eeca106725	7463	#define TIM_BDTR_MOE 0x00008000U /!<Main Output enable /
Kojto	122:f9eeca106725	7464	#define TIM_BDTR_BKF 0x000F0000U /!<Break Filter for Break1 /
Kojto	122:f9eeca106725	7465	#define TIM_BDTR_BK2F 0x00F00000U /!<Break Filter for Break2 /
Kojto	122:f9eeca106725	7466	#define TIM_BDTR_BK2E 0x01000000U /!<Break enable for Break2 /
Kojto	122:f9eeca106725	7467	#define TIM_BDTR_BK2P 0x02000000U /!<Break Polarity for Break2 /
Kojto	107:4f6c30876dfa	7468
Kojto	107:4f6c30876dfa	7469	/***************** Bit definition for TIM_DCR register ******************/
Kojto	122:f9eeca106725	7470	#define TIM_DCR_DBA 0x001FU /!<DBA[4:0] bits (DMA Base Address) /
Kojto	122:f9eeca106725	7471	#define TIM_DCR_DBA_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	7472	#define TIM_DCR_DBA_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	7473	#define TIM_DCR_DBA_2 0x0004U /!<Bit 2 /
Kojto	122:f9eeca106725	7474	#define TIM_DCR_DBA_3 0x0008U /!<Bit 3 /
Kojto	122:f9eeca106725	7475	#define TIM_DCR_DBA_4 0x0010U /!<Bit 4 /
Kojto	122:f9eeca106725	7476
Kojto	122:f9eeca106725	7477	#define TIM_DCR_DBL 0x1F00U /!<DBL[4:0] bits (DMA Burst Length) /
Kojto	122:f9eeca106725	7478	#define TIM_DCR_DBL_0 0x0100U /!<Bit 0 /
Kojto	122:f9eeca106725	7479	#define TIM_DCR_DBL_1 0x0200U /!<Bit 1 /
Kojto	122:f9eeca106725	7480	#define TIM_DCR_DBL_2 0x0400U /!<Bit 2 /
Kojto	122:f9eeca106725	7481	#define TIM_DCR_DBL_3 0x0800U /!<Bit 3 /
Kojto	122:f9eeca106725	7482	#define TIM_DCR_DBL_4 0x1000U /!<Bit 4 /
Kojto	107:4f6c30876dfa	7483
Kojto	107:4f6c30876dfa	7484	/***************** Bit definition for TIM_DMAR register *****************/
Kojto	122:f9eeca106725	7485	#define TIM_DMAR_DMAB 0xFFFFU /!<DMA register for burst accesses /
Kojto	122:f9eeca106725	7486
Kojto	122:f9eeca106725	7487	/***************** Bit definition for TIM_OR regiter *******************/
Kojto	122:f9eeca106725	7488	#define TIM_OR_TI4_RMP 0x00C0U /!<TI4_RMP[1:0] bits (TIM5 Input 4 remap) /
Kojto	122:f9eeca106725	7489	#define TIM_OR_TI4_RMP_0 0x0040U /!<Bit 0 /
Kojto	122:f9eeca106725	7490	#define TIM_OR_TI4_RMP_1 0x0080U /!<Bit 1 /
Kojto	122:f9eeca106725	7491	#define TIM_OR_ITR1_RMP 0x0C00U /!<ITR1_RMP[1:0] bits (TIM2 Internal trigger 1 remap) /
Kojto	122:f9eeca106725	7492	#define TIM_OR_ITR1_RMP_0 0x0400U /!<Bit 0 /
Kojto	122:f9eeca106725	7493	#define TIM_OR_ITR1_RMP_1 0x0800U /!<Bit 1 /
Kojto	107:4f6c30876dfa	7494
Kojto	107:4f6c30876dfa	7495	/**************** Bit definition for TIM_CCMR3 register *****************/
Kojto	122:f9eeca106725	7496	#define TIM_CCMR3_OC5FE 0x00000004U /!<Output Compare 5 Fast enable /
Kojto	122:f9eeca106725	7497	#define TIM_CCMR3_OC5PE 0x00000008U /!<Output Compare 5 Preload enable /
Kojto	122:f9eeca106725	7498
Kojto	122:f9eeca106725	7499	#define TIM_CCMR3_OC5M 0x00010070U /!<OC5M[2:0] bits (Output Compare 5 Mode) /
Kojto	122:f9eeca106725	7500	#define TIM_CCMR3_OC5M_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	7501	#define TIM_CCMR3_OC5M_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	7502	#define TIM_CCMR3_OC5M_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	7503	#define TIM_CCMR3_OC5M_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	7504
Kojto	122:f9eeca106725	7505	#define TIM_CCMR3_OC5CE 0x00000080U /!<Output Compare 5 Clear Enable /
Kojto	122:f9eeca106725	7506
Kojto	122:f9eeca106725	7507	#define TIM_CCMR3_OC6FE 0x00000400U /!<Output Compare 4 Fast enable /
Kojto	122:f9eeca106725	7508	#define TIM_CCMR3_OC6PE 0x00000800U /!<Output Compare 4 Preload enable /
Kojto	122:f9eeca106725	7509
Kojto	122:f9eeca106725	7510	#define TIM_CCMR3_OC6M 0x01007000U /!<OC4M[2:0] bits (Output Compare 4 Mode) /
Kojto	122:f9eeca106725	7511	#define TIM_CCMR3_OC6M_0 0x00001000U /!<Bit 0 /
Kojto	122:f9eeca106725	7512	#define TIM_CCMR3_OC6M_1 0x00002000U /!<Bit 1 /
Kojto	122:f9eeca106725	7513	#define TIM_CCMR3_OC6M_2 0x00004000U /!<Bit 2 /
Kojto	122:f9eeca106725	7514	#define TIM_CCMR3_OC6M_3 0x01000000U /!<Bit 3 /
Kojto	122:f9eeca106725	7515
Kojto	122:f9eeca106725	7516	#define TIM_CCMR3_OC6CE 0x00008000U /!<Output Compare 4 Clear Enable /
Kojto	107:4f6c30876dfa	7517
Kojto	107:4f6c30876dfa	7518	/***************** Bit definition for TIM_CCR5 register *****************/
Kojto	122:f9eeca106725	7519	#define TIM_CCR5_CCR5 0xFFFFFFFFU /!<Capture/Compare 5 Value /
Kojto	122:f9eeca106725	7520	#define TIM_CCR5_GC5C1 0x20000000U /!<Group Channel 5 and Channel 1 /
Kojto	122:f9eeca106725	7521	#define TIM_CCR5_GC5C2 0x40000000U /!<Group Channel 5 and Channel 2 /
Kojto	122:f9eeca106725	7522	#define TIM_CCR5_GC5C3 0x80000000U /!<Group Channel 5 and Channel 3 /
Kojto	107:4f6c30876dfa	7523
Kojto	107:4f6c30876dfa	7524	/***************** Bit definition for TIM_CCR6 register *****************/
Kojto	122:f9eeca106725	7525	#define TIM_CCR6_CCR6 ((uint16_t)0xFFFFU) /!<Capture/Compare 6 Value /
Kojto	107:4f6c30876dfa	7526
Kojto	116:c0f6e94411f5	7527
Kojto	107:4f6c30876dfa	7528	/******************************************************************************/
Kojto	107:4f6c30876dfa	7529	/* */
Kojto	107:4f6c30876dfa	7530	/* Low Power Timer (LPTIM) */
Kojto	107:4f6c30876dfa	7531	/* */
Kojto	107:4f6c30876dfa	7532	/******************************************************************************/
Kojto	107:4f6c30876dfa	7533	/**************** Bit definition for LPTIM_ISR register *****************/
Kojto	122:f9eeca106725	7534	#define LPTIM_ISR_CMPM 0x00000001U /!< Compare match /
Kojto	122:f9eeca106725	7535	#define LPTIM_ISR_ARRM 0x00000002U /!< Autoreload match /
Kojto	122:f9eeca106725	7536	#define LPTIM_ISR_EXTTRIG 0x00000004U /!< External trigger edge event /
Kojto	122:f9eeca106725	7537	#define LPTIM_ISR_CMPOK 0x00000008U /!< Compare register update OK /
Kojto	122:f9eeca106725	7538	#define LPTIM_ISR_ARROK 0x00000010U /!< Autoreload register update OK /
Kojto	122:f9eeca106725	7539	#define LPTIM_ISR_UP 0x00000020U /!< Counter direction change down to up /
Kojto	122:f9eeca106725	7540	#define LPTIM_ISR_DOWN 0x00000040U /!< Counter direction change up to down /
Kojto	107:4f6c30876dfa	7541
Kojto	107:4f6c30876dfa	7542	/**************** Bit definition for LPTIM_ICR register *****************/
Kojto	122:f9eeca106725	7543	#define LPTIM_ICR_CMPMCF 0x00000001U /!< Compare match Clear Flag /
Kojto	122:f9eeca106725	7544	#define LPTIM_ICR_ARRMCF 0x00000002U /!< Autoreload match Clear Flag /
Kojto	122:f9eeca106725	7545	#define LPTIM_ICR_EXTTRIGCF 0x00000004U /!< External trigger edge event Clear Flag /
Kojto	122:f9eeca106725	7546	#define LPTIM_ICR_CMPOKCF 0x00000008U /!< Compare register update OK Clear Flag /
Kojto	122:f9eeca106725	7547	#define LPTIM_ICR_ARROKCF 0x00000010U /!< Autoreload register update OK Clear Flag /
Kojto	122:f9eeca106725	7548	#define LPTIM_ICR_UPCF 0x00000020U /!< Counter direction change down to up Clear Flag /
Kojto	122:f9eeca106725	7549	#define LPTIM_ICR_DOWNCF 0x00000040U /!< Counter direction change up to down Clear Flag /
Kojto	122:f9eeca106725	7550
Kojto	122:f9eeca106725	7551	/**************** Bit definition for LPTIM_IER register *****************/
Kojto	122:f9eeca106725	7552	#define LPTIM_IER_CMPMIE 0x00000001U /!< Compare match Interrupt Enable /
Kojto	122:f9eeca106725	7553	#define LPTIM_IER_ARRMIE 0x00000002U /!< Autoreload match Interrupt Enable /
Kojto	122:f9eeca106725	7554	#define LPTIM_IER_EXTTRIGIE 0x00000004U /!< External trigger edge event Interrupt Enable /
Kojto	122:f9eeca106725	7555	#define LPTIM_IER_CMPOKIE 0x00000008U /!< Compare register update OK Interrupt Enable /
Kojto	122:f9eeca106725	7556	#define LPTIM_IER_ARROKIE 0x00000010U /!< Autoreload register update OK Interrupt Enable /
Kojto	122:f9eeca106725	7557	#define LPTIM_IER_UPIE 0x00000020U /!< Counter direction change down to up Interrupt Enable /
Kojto	122:f9eeca106725	7558	#define LPTIM_IER_DOWNIE 0x00000040U /!< Counter direction change up to down Interrupt Enable /
Kojto	122:f9eeca106725	7559
Kojto	122:f9eeca106725	7560	/**************** Bit definition for LPTIM_CFGR register*****************/
Kojto	122:f9eeca106725	7561	#define LPTIM_CFGR_CKSEL 0x00000001U /!< Clock selector /
Kojto	122:f9eeca106725	7562
Kojto	122:f9eeca106725	7563	#define LPTIM_CFGR_CKPOL 0x00000006U /!< CKPOL[1:0] bits (Clock polarity) /
Kojto	122:f9eeca106725	7564	#define LPTIM_CFGR_CKPOL_0 0x00000002U /!< Bit 0 /
Kojto	122:f9eeca106725	7565	#define LPTIM_CFGR_CKPOL_1 0x00000004U /!< Bit 1 /
Kojto	122:f9eeca106725	7566
Kojto	122:f9eeca106725	7567	#define LPTIM_CFGR_CKFLT 0x00000018U /!< CKFLT[1:0] bits (Configurable digital filter for external clock) /
Kojto	122:f9eeca106725	7568	#define LPTIM_CFGR_CKFLT_0 0x00000008U /!< Bit 0 /
Kojto	122:f9eeca106725	7569	#define LPTIM_CFGR_CKFLT_1 0x00000010U /!< Bit 1 /
Kojto	122:f9eeca106725	7570
Kojto	122:f9eeca106725	7571	#define LPTIM_CFGR_TRGFLT 0x000000C0U /!< TRGFLT[1:0] bits (Configurable digital filter for trigger) /
Kojto	122:f9eeca106725	7572	#define LPTIM_CFGR_TRGFLT_0 0x00000040U /!< Bit 0 /
Kojto	122:f9eeca106725	7573	#define LPTIM_CFGR_TRGFLT_1 0x00000080U /!< Bit 1 /
Kojto	122:f9eeca106725	7574
Kojto	122:f9eeca106725	7575	#define LPTIM_CFGR_PRESC 0x00000E00U /!< PRESC[2:0] bits (Clock prescaler) /
Kojto	122:f9eeca106725	7576	#define LPTIM_CFGR_PRESC_0 0x00000200U /!< Bit 0 /
Kojto	122:f9eeca106725	7577	#define LPTIM_CFGR_PRESC_1 0x00000400U /!< Bit 1 /
Kojto	122:f9eeca106725	7578	#define LPTIM_CFGR_PRESC_2 0x00000800U /!< Bit 2 /
Kojto	122:f9eeca106725	7579
Kojto	122:f9eeca106725	7580	#define LPTIM_CFGR_TRIGSEL 0x0000E000U /!< TRIGSEL[2:0]] bits (Trigger selector) /
Kojto	122:f9eeca106725	7581	#define LPTIM_CFGR_TRIGSEL_0 0x00002000U /!< Bit 0 /
Kojto	122:f9eeca106725	7582	#define LPTIM_CFGR_TRIGSEL_1 0x00004000U /!< Bit 1 /
Kojto	122:f9eeca106725	7583	#define LPTIM_CFGR_TRIGSEL_2 0x00008000U /!< Bit 2 /
Kojto	122:f9eeca106725	7584
Kojto	122:f9eeca106725	7585	#define LPTIM_CFGR_TRIGEN 0x00060000U /!< TRIGEN[1:0] bits (Trigger enable and polarity) /
Kojto	122:f9eeca106725	7586	#define LPTIM_CFGR_TRIGEN_0 0x00020000U /!< Bit 0 /
Kojto	122:f9eeca106725	7587	#define LPTIM_CFGR_TRIGEN_1 0x00040000U /!< Bit 1 /
Kojto	122:f9eeca106725	7588
Kojto	122:f9eeca106725	7589	#define LPTIM_CFGR_TIMOUT 0x00080000U /!< Timout enable /
Kojto	122:f9eeca106725	7590	#define LPTIM_CFGR_WAVE 0x00100000U /!< Waveform shape /
Kojto	122:f9eeca106725	7591	#define LPTIM_CFGR_WAVPOL 0x00200000U /!< Waveform shape polarity /
Kojto	122:f9eeca106725	7592	#define LPTIM_CFGR_PRELOAD 0x00400000U /!< Reg update mode /
Kojto	122:f9eeca106725	7593	#define LPTIM_CFGR_COUNTMODE 0x00800000U /!< Counter mode enable /
Kojto	122:f9eeca106725	7594	#define LPTIM_CFGR_ENC 0x01000000U /!< Encoder mode enable /
Kojto	107:4f6c30876dfa	7595
Kojto	107:4f6c30876dfa	7596	/**************** Bit definition for LPTIM_CR register ******************/
Kojto	122:f9eeca106725	7597	#define LPTIM_CR_ENABLE 0x00000001U /!< LPTIMer enable /
Kojto	122:f9eeca106725	7598	#define LPTIM_CR_SNGSTRT 0x00000002U /!< Timer start in single mode /
Kojto	122:f9eeca106725	7599	#define LPTIM_CR_CNTSTRT 0x00000004U /!< Timer start in continuous mode /
Kojto	122:f9eeca106725	7600
Kojto	122:f9eeca106725	7601	/**************** Bit definition for LPTIM_CMP register *****************/
Kojto	122:f9eeca106725	7602	#define LPTIM_CMP_CMP 0x0000FFFFU /!< Compare register /
Kojto	122:f9eeca106725	7603
Kojto	122:f9eeca106725	7604	/**************** Bit definition for LPTIM_ARR register *****************/
Kojto	122:f9eeca106725	7605	#define LPTIM_ARR_ARR 0x0000FFFFU /!< Auto reload register /
Kojto	122:f9eeca106725	7606
Kojto	122:f9eeca106725	7607	/**************** Bit definition for LPTIM_CNT register *****************/
Kojto	122:f9eeca106725	7608	#define LPTIM_CNT_CNT 0x0000FFFFU /!< Counter register /
Kojto	107:4f6c30876dfa	7609	/******************************************************************************/
Kojto	107:4f6c30876dfa	7610	/* */
Kojto	107:4f6c30876dfa	7611	/* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto	107:4f6c30876dfa	7612	/* */
Kojto	107:4f6c30876dfa	7613	/******************************************************************************/
Kojto	107:4f6c30876dfa	7614	/**************** Bit definition for USART_CR1 register *****************/
Kojto	122:f9eeca106725	7615	#define USART_CR1_UE 0x00000001U /!< USART Enable /
Kojto	122:f9eeca106725	7616	#define USART_CR1_RE 0x00000004U /!< Receiver Enable /
Kojto	122:f9eeca106725	7617	#define USART_CR1_TE 0x00000008U /!< Transmitter Enable /
Kojto	122:f9eeca106725	7618	#define USART_CR1_IDLEIE 0x00000010U /!< IDLE Interrupt Enable /
Kojto	122:f9eeca106725	7619	#define USART_CR1_RXNEIE 0x00000020U /!< RXNE Interrupt Enable /
Kojto	122:f9eeca106725	7620	#define USART_CR1_TCIE 0x00000040U /!< Transmission Complete Interrupt Enable /
Kojto	122:f9eeca106725	7621	#define USART_CR1_TXEIE 0x00000080U /!< TXE Interrupt Enable /
Kojto	122:f9eeca106725	7622	#define USART_CR1_PEIE 0x00000100U /!< PE Interrupt Enable /
Kojto	122:f9eeca106725	7623	#define USART_CR1_PS 0x00000200U /!< Parity Selection /
Kojto	122:f9eeca106725	7624	#define USART_CR1_PCE 0x00000400U /!< Parity Control Enable /
Kojto	122:f9eeca106725	7625	#define USART_CR1_WAKE 0x00000800U /!< Receiver Wakeup method /
Kojto	122:f9eeca106725	7626	#define USART_CR1_M 0x10001000U /!< Word length /
Kojto	122:f9eeca106725	7627	#define USART_CR1_M_0 0x00001000U /!< Word length - Bit 0 /
Kojto	122:f9eeca106725	7628	#define USART_CR1_MME 0x00002000U /!< Mute Mode Enable /
Kojto	122:f9eeca106725	7629	#define USART_CR1_CMIE 0x00004000U /!< Character match interrupt enable /
Kojto	122:f9eeca106725	7630	#define USART_CR1_OVER8 0x00008000U /!< Oversampling by 8-bit or 16-bit mode /
Kojto	122:f9eeca106725	7631	#define USART_CR1_DEDT 0x001F0000U /!< DEDT[4:0] bits (Driver Enable Deassertion Time) /
Kojto	122:f9eeca106725	7632	#define USART_CR1_DEDT_0 0x00010000U /!< Bit 0 /
Kojto	122:f9eeca106725	7633	#define USART_CR1_DEDT_1 0x00020000U /!< Bit 1 /
Kojto	122:f9eeca106725	7634	#define USART_CR1_DEDT_2 0x00040000U /!< Bit 2 /
Kojto	122:f9eeca106725	7635	#define USART_CR1_DEDT_3 0x00080000U /!< Bit 3 /
Kojto	122:f9eeca106725	7636	#define USART_CR1_DEDT_4 0x00100000U /!< Bit 4 /
Kojto	122:f9eeca106725	7637	#define USART_CR1_DEAT 0x03E00000U /!< DEAT[4:0] bits (Driver Enable Assertion Time) /
Kojto	122:f9eeca106725	7638	#define USART_CR1_DEAT_0 0x00200000U /!< Bit 0 /
Kojto	122:f9eeca106725	7639	#define USART_CR1_DEAT_1 0x00400000U /!< Bit 1 /
Kojto	122:f9eeca106725	7640	#define USART_CR1_DEAT_2 0x00800000U /!< Bit 2 /
Kojto	122:f9eeca106725	7641	#define USART_CR1_DEAT_3 0x01000000U /!< Bit 3 /
Kojto	122:f9eeca106725	7642	#define USART_CR1_DEAT_4 0x02000000U /!< Bit 4 /
Kojto	122:f9eeca106725	7643	#define USART_CR1_RTOIE 0x04000000U /!< Receive Time Out interrupt enable /
Kojto	122:f9eeca106725	7644	#define USART_CR1_EOBIE 0x08000000U /!< End of Block interrupt enable /
Kojto	122:f9eeca106725	7645	#define USART_CR1_M_1 0x10000000U /!< Word length - Bit 1 /
Kojto	107:4f6c30876dfa	7646
Kojto	107:4f6c30876dfa	7647	/**************** Bit definition for USART_CR2 register *****************/
Kojto	122:f9eeca106725	7648	#define USART_CR2_ADDM7 0x00000010U /!< 7-bit or 4-bit Address Detection /
Kojto	122:f9eeca106725	7649	#define USART_CR2_LBDL 0x00000020U /!< LIN Break Detection Length /
Kojto	122:f9eeca106725	7650	#define USART_CR2_LBDIE 0x00000040U /!< LIN Break Detection Interrupt Enable /
Kojto	122:f9eeca106725	7651	#define USART_CR2_LBCL 0x00000100U /!< Last Bit Clock pulse /
Kojto	122:f9eeca106725	7652	#define USART_CR2_CPHA 0x00000200U /!< Clock Phase /
Kojto	122:f9eeca106725	7653	#define USART_CR2_CPOL 0x00000400U /!< Clock Polarity /
Kojto	122:f9eeca106725	7654	#define USART_CR2_CLKEN 0x00000800U /!< Clock Enable /
Kojto	122:f9eeca106725	7655	#define USART_CR2_STOP 0x00003000U /!< STOP[1:0] bits (STOP bits) /
Kojto	122:f9eeca106725	7656	#define USART_CR2_STOP_0 0x00001000U /!< Bit 0 /
Kojto	122:f9eeca106725	7657	#define USART_CR2_STOP_1 0x00002000U /!< Bit 1 /
Kojto	122:f9eeca106725	7658	#define USART_CR2_LINEN 0x00004000U /!< LIN mode enable /
Kojto	122:f9eeca106725	7659	#define USART_CR2_SWAP 0x00008000U /!< SWAP TX/RX pins /
Kojto	122:f9eeca106725	7660	#define USART_CR2_RXINV 0x00010000U /!< RX pin active level inversion /
Kojto	122:f9eeca106725	7661	#define USART_CR2_TXINV 0x00020000U /!< TX pin active level inversion /
Kojto	122:f9eeca106725	7662	#define USART_CR2_DATAINV 0x00040000U /!< Binary data inversion /
Kojto	122:f9eeca106725	7663	#define USART_CR2_MSBFIRST 0x00080000U /!< Most Significant Bit First /
Kojto	122:f9eeca106725	7664	#define USART_CR2_ABREN 0x00100000U /!< Auto Baud-Rate Enable /
Kojto	122:f9eeca106725	7665	#define USART_CR2_ABRMODE 0x00600000U /!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) /
Kojto	122:f9eeca106725	7666	#define USART_CR2_ABRMODE_0 0x00200000U /!< Bit 0 /
Kojto	122:f9eeca106725	7667	#define USART_CR2_ABRMODE_1 0x00400000U /!< Bit 1 /
Kojto	122:f9eeca106725	7668	#define USART_CR2_RTOEN 0x00800000U /!< Receiver Time-Out enable /
Kojto	122:f9eeca106725	7669	#define USART_CR2_ADD 0xFF000000U /!< Address of the USART node /
Kojto	107:4f6c30876dfa	7670
Kojto	107:4f6c30876dfa	7671	/**************** Bit definition for USART_CR3 register *****************/
Kojto	122:f9eeca106725	7672	#define USART_CR3_EIE 0x00000001U /!< Error Interrupt Enable /
Kojto	122:f9eeca106725	7673	#define USART_CR3_IREN 0x00000002U /!< IrDA mode Enable /
Kojto	122:f9eeca106725	7674	#define USART_CR3_IRLP 0x00000004U /!< IrDA Low-Power /
Kojto	122:f9eeca106725	7675	#define USART_CR3_HDSEL 0x00000008U /!< Half-Duplex Selection /
Kojto	122:f9eeca106725	7676	#define USART_CR3_NACK 0x00000010U /!< SmartCard NACK enable /
Kojto	122:f9eeca106725	7677	#define USART_CR3_SCEN 0x00000020U /!< SmartCard mode enable /
Kojto	122:f9eeca106725	7678	#define USART_CR3_DMAR 0x00000040U /!< DMA Enable Receiver /
Kojto	122:f9eeca106725	7679	#define USART_CR3_DMAT 0x00000080U /!< DMA Enable Transmitter /
Kojto	122:f9eeca106725	7680	#define USART_CR3_RTSE 0x00000100U /!< RTS Enable /
Kojto	122:f9eeca106725	7681	#define USART_CR3_CTSE 0x00000200U /!< CTS Enable /
Kojto	122:f9eeca106725	7682	#define USART_CR3_CTSIE 0x00000400U /!< CTS Interrupt Enable /
Kojto	122:f9eeca106725	7683	#define USART_CR3_ONEBIT 0x00000800U /!< One sample bit method enable /
Kojto	122:f9eeca106725	7684	#define USART_CR3_OVRDIS 0x00001000U /!< Overrun Disable /
Kojto	122:f9eeca106725	7685	#define USART_CR3_DDRE 0x00002000U /!< DMA Disable on Reception Error /
Kojto	122:f9eeca106725	7686	#define USART_CR3_DEM 0x00004000U /!< Driver Enable Mode /
Kojto	122:f9eeca106725	7687	#define USART_CR3_DEP 0x00008000U /!< Driver Enable Polarity Selection /
Kojto	122:f9eeca106725	7688	#define USART_CR3_SCARCNT 0x000E0000U /!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) /
Kojto	122:f9eeca106725	7689	#define USART_CR3_SCARCNT_0 0x00020000U /!< Bit 0 /
Kojto	122:f9eeca106725	7690	#define USART_CR3_SCARCNT_1 0x00040000U /!< Bit 1 /
Kojto	122:f9eeca106725	7691	#define USART_CR3_SCARCNT_2 0x00080000U /!< Bit 2 /
Kojto	107:4f6c30876dfa	7692
Kojto	116:c0f6e94411f5	7693
Kojto	107:4f6c30876dfa	7694	/**************** Bit definition for USART_BRR register *****************/
Kojto	122:f9eeca106725	7695	#define USART_BRR_DIV_FRACTION 0x000FU /!< Fraction of USARTDIV /
Kojto	122:f9eeca106725	7696	#define USART_BRR_DIV_MANTISSA 0xFFF0U /!< Mantissa of USARTDIV /
Kojto	107:4f6c30876dfa	7697
Kojto	107:4f6c30876dfa	7698	/**************** Bit definition for USART_GTPR register ****************/
Kojto	122:f9eeca106725	7699	#define USART_GTPR_PSC 0x00FFU /!< PSC[7:0] bits (Prescaler value) /
Kojto	122:f9eeca106725	7700	#define USART_GTPR_GT 0xFF00U /!< GT[7:0] bits (Guard time value) /
Kojto	107:4f6c30876dfa	7701
Kojto	107:4f6c30876dfa	7702
Kojto	107:4f6c30876dfa	7703	/***************** Bit definition for USART_RTOR register ***************/
Kojto	122:f9eeca106725	7704	#define USART_RTOR_RTO 0x00FFFFFFU /!< Receiver Time Out Value /
Kojto	122:f9eeca106725	7705	#define USART_RTOR_BLEN 0xFF000000U /!< Block Length /
Kojto	107:4f6c30876dfa	7706
Kojto	107:4f6c30876dfa	7707	/***************** Bit definition for USART_RQR register ****************/
Kojto	122:f9eeca106725	7708	#define USART_RQR_ABRRQ 0x0001U /!< Auto-Baud Rate Request /
Kojto	122:f9eeca106725	7709	#define USART_RQR_SBKRQ 0x0002U /!< Send Break Request /
Kojto	122:f9eeca106725	7710	#define USART_RQR_MMRQ 0x0004U /!< Mute Mode Request /
Kojto	122:f9eeca106725	7711	#define USART_RQR_RXFRQ 0x0008U /!< Receive Data flush Request /
Kojto	122:f9eeca106725	7712	#define USART_RQR_TXFRQ 0x0010U /!< Transmit data flush Request /
Kojto	107:4f6c30876dfa	7713
Kojto	107:4f6c30876dfa	7714	/***************** Bit definition for USART_ISR register ****************/
Kojto	122:f9eeca106725	7715	#define USART_ISR_PE 0x00000001U /!< Parity Error /
Kojto	122:f9eeca106725	7716	#define USART_ISR_FE 0x00000002U /!< Framing Error /
Kojto	122:f9eeca106725	7717	#define USART_ISR_NE 0x00000004U /!< Noise detected Flag /
Kojto	122:f9eeca106725	7718	#define USART_ISR_ORE 0x00000008U /!< OverRun Error /
Kojto	122:f9eeca106725	7719	#define USART_ISR_IDLE 0x00000010U /!< IDLE line detected /
Kojto	122:f9eeca106725	7720	#define USART_ISR_RXNE 0x00000020U /!< Read Data Register Not Empty /
Kojto	122:f9eeca106725	7721	#define USART_ISR_TC 0x00000040U /!< Transmission Complete /
Kojto	122:f9eeca106725	7722	#define USART_ISR_TXE 0x00000080U /!< Transmit Data Register Empty /
Kojto	122:f9eeca106725	7723	#define USART_ISR_LBDF 0x00000100U /!< LIN Break Detection Flag /
Kojto	122:f9eeca106725	7724	#define USART_ISR_CTSIF 0x00000200U /!< CTS interrupt flag /
Kojto	122:f9eeca106725	7725	#define USART_ISR_CTS 0x00000400U /!< CTS flag /
Kojto	122:f9eeca106725	7726	#define USART_ISR_RTOF 0x00000800U /!< Receiver Time Out /
Kojto	122:f9eeca106725	7727	#define USART_ISR_EOBF 0x00001000U /!< End Of Block Flag /
Kojto	122:f9eeca106725	7728	#define USART_ISR_ABRE 0x00004000U /!< Auto-Baud Rate Error /
Kojto	122:f9eeca106725	7729	#define USART_ISR_ABRF 0x00008000U /!< Auto-Baud Rate Flag /
Kojto	122:f9eeca106725	7730	#define USART_ISR_BUSY 0x00010000U /!< Busy Flag /
Kojto	122:f9eeca106725	7731	#define USART_ISR_CMF 0x00020000U /!< Character Match Flag /
Kojto	122:f9eeca106725	7732	#define USART_ISR_SBKF 0x00040000U /!< Send Break Flag /
Kojto	122:f9eeca106725	7733	#define USART_ISR_RWU 0x00080000U /!< Receive Wake Up from mute mode Flag /
Kojto	122:f9eeca106725	7734	#define USART_ISR_WUF 0x00100000U /!< Wake Up from stop mode Flag /
Kojto	122:f9eeca106725	7735	#define USART_ISR_TEACK 0x00200000U /!< Transmit Enable Acknowledge Flag /
Kojto	122:f9eeca106725	7736	#define USART_ISR_REACK 0x00400000U /!< Receive Enable Acknowledge Flag /
Kojto	122:f9eeca106725	7737
Kojto	122:f9eeca106725	7738	/* Legacy define */
Kojto	122:f9eeca106725	7739	#define USART_ISR_LBD USART_ISR_LBDF
Kojto	107:4f6c30876dfa	7740
Kojto	107:4f6c30876dfa	7741	/***************** Bit definition for USART_ICR register ****************/
Kojto	122:f9eeca106725	7742	#define USART_ICR_PECF 0x00000001U /!< Parity Error Clear Flag /
Kojto	122:f9eeca106725	7743	#define USART_ICR_FECF 0x00000002U /!< Framing Error Clear Flag /
Kojto	122:f9eeca106725	7744	#define USART_ICR_NCF 0x00000004U /!< Noise detected Clear Flag /
Kojto	122:f9eeca106725	7745	#define USART_ICR_ORECF 0x00000008U /!< OverRun Error Clear Flag /
Kojto	122:f9eeca106725	7746	#define USART_ICR_IDLECF 0x00000010U /!< IDLE line detected Clear Flag /
Kojto	122:f9eeca106725	7747	#define USART_ICR_TCCF 0x00000040U /!< Transmission Complete Clear Flag /
Kojto	122:f9eeca106725	7748	#define USART_ICR_LBDCF 0x00000100U /!< LIN Break Detection Clear Flag /
Kojto	122:f9eeca106725	7749	#define USART_ICR_CTSCF 0x00000200U /!< CTS Interrupt Clear Flag /
Kojto	122:f9eeca106725	7750	#define USART_ICR_RTOCF 0x00000800U /!< Receiver Time Out Clear Flag /
Kojto	122:f9eeca106725	7751	#define USART_ICR_EOBCF 0x00001000U /!< End Of Block Clear Flag /
Kojto	122:f9eeca106725	7752	#define USART_ICR_CMCF 0x00020000U /!< Character Match Clear Flag /
Kojto	122:f9eeca106725	7753	#define USART_ICR_WUCF 0x00100000U /!< Wake Up from stop mode Clear Flag /
Kojto	107:4f6c30876dfa	7754
Kojto	107:4f6c30876dfa	7755	/***************** Bit definition for USART_RDR register ****************/
Kojto	122:f9eeca106725	7756	#define USART_RDR_RDR 0x01FFU /!< RDR[8:0] bits (Receive Data value) /
Kojto	107:4f6c30876dfa	7757
Kojto	107:4f6c30876dfa	7758	/***************** Bit definition for USART_TDR register ****************/
Kojto	122:f9eeca106725	7759	#define USART_TDR_TDR 0x01FFU /!< TDR[8:0] bits (Transmit Data value) /
Kojto	107:4f6c30876dfa	7760
Kojto	107:4f6c30876dfa	7761	/******************************************************************************/
Kojto	107:4f6c30876dfa	7762	/* */
Kojto	107:4f6c30876dfa	7763	/* Window WATCHDOG */
Kojto	107:4f6c30876dfa	7764	/* */
Kojto	107:4f6c30876dfa	7765	/******************************************************************************/
Kojto	107:4f6c30876dfa	7766	/***************** Bit definition for WWDG_CR register ******************/
Kojto	122:f9eeca106725	7767	#define WWDG_CR_T 0x7FU /!<T[6:0] bits (7-Bit counter (MSB to LSB)) /
Kojto	122:f9eeca106725	7768	#define WWDG_CR_T_0 0x01U /!<Bit 0 /
Kojto	122:f9eeca106725	7769	#define WWDG_CR_T_1 0x02U /!<Bit 1 /
Kojto	122:f9eeca106725	7770	#define WWDG_CR_T_2 0x04U /!<Bit 2 /
Kojto	122:f9eeca106725	7771	#define WWDG_CR_T_3 0x08U /!<Bit 3 /
Kojto	122:f9eeca106725	7772	#define WWDG_CR_T_4 0x10U /!<Bit 4 /
Kojto	122:f9eeca106725	7773	#define WWDG_CR_T_5 0x20U /!<Bit 5 /
Kojto	122:f9eeca106725	7774	#define WWDG_CR_T_6 0x40U /!<Bit 6 /
Kojto	116:c0f6e94411f5	7775
Kojto	116:c0f6e94411f5	7776	/* Legacy defines */
Kojto	116:c0f6e94411f5	7777	#define WWDG_CR_T0 WWDG_CR_T_0 /!<Bit 0 /
Kojto	116:c0f6e94411f5	7778	#define WWDG_CR_T1 WWDG_CR_T_1 /!<Bit 1 /
Kojto	116:c0f6e94411f5	7779	#define WWDG_CR_T2 WWDG_CR_T_2 /!<Bit 2 /
Kojto	116:c0f6e94411f5	7780	#define WWDG_CR_T3 WWDG_CR_T_3 /!<Bit 3 /
Kojto	116:c0f6e94411f5	7781	#define WWDG_CR_T4 WWDG_CR_T_4 /!<Bit 4 /
Kojto	116:c0f6e94411f5	7782	#define WWDG_CR_T5 WWDG_CR_T_5 /!<Bit 5 /
Kojto	116:c0f6e94411f5	7783	#define WWDG_CR_T6 WWDG_CR_T_6 /!<Bit 6 /
Kojto	116:c0f6e94411f5	7784
Kojto	122:f9eeca106725	7785	#define WWDG_CR_WDGA 0x80U /!<Activation bit /
Kojto	107:4f6c30876dfa	7786
Kojto	107:4f6c30876dfa	7787	/***************** Bit definition for WWDG_CFR register *****************/
Kojto	122:f9eeca106725	7788	#define WWDG_CFR_W 0x007FU /!<W[6:0] bits (7-bit window value) /
Kojto	122:f9eeca106725	7789	#define WWDG_CFR_W_0 0x0001U /!<Bit 0 /
Kojto	122:f9eeca106725	7790	#define WWDG_CFR_W_1 0x0002U /!<Bit 1 /
Kojto	122:f9eeca106725	7791	#define WWDG_CFR_W_2 0x0004U /!<Bit 2 /
Kojto	122:f9eeca106725	7792	#define WWDG_CFR_W_3 0x0008U /!<Bit 3 /
Kojto	122:f9eeca106725	7793	#define WWDG_CFR_W_4 0x0010U /!<Bit 4 /
Kojto	122:f9eeca106725	7794	#define WWDG_CFR_W_5 0x0020U /!<Bit 5 /
Kojto	122:f9eeca106725	7795	#define WWDG_CFR_W_6 0x0040U /!<Bit 6 /
Kojto	116:c0f6e94411f5	7796
Kojto	116:c0f6e94411f5	7797	/* Legacy defines */
Kojto	116:c0f6e94411f5	7798	#define WWDG_CFR_W0 WWDG_CFR_W_0 /!<Bit 0 /
Kojto	116:c0f6e94411f5	7799	#define WWDG_CFR_W1 WWDG_CFR_W_1 /!<Bit 1 /
Kojto	116:c0f6e94411f5	7800	#define WWDG_CFR_W2 WWDG_CFR_W_2 /!<Bit 2 /
Kojto	116:c0f6e94411f5	7801	#define WWDG_CFR_W3 WWDG_CFR_W_3 /!<Bit 3 /
Kojto	116:c0f6e94411f5	7802	#define WWDG_CFR_W4 WWDG_CFR_W_4 /!<Bit 4 /
Kojto	116:c0f6e94411f5	7803	#define WWDG_CFR_W5 WWDG_CFR_W_5 /!<Bit 5 /
Kojto	116:c0f6e94411f5	7804	#define WWDG_CFR_W6 WWDG_CFR_W_6 /!<Bit 6 /
Kojto	116:c0f6e94411f5	7805
Kojto	122:f9eeca106725	7806	#define WWDG_CFR_WDGTB 0x0180U /!<WDGTB[1:0] bits (Timer Base) /
Kojto	122:f9eeca106725	7807	#define WWDG_CFR_WDGTB_0 0x0080U /!<Bit 0 /
Kojto	122:f9eeca106725	7808	#define WWDG_CFR_WDGTB_1 0x0100U /!<Bit 1 /
Kojto	116:c0f6e94411f5	7809
Kojto	116:c0f6e94411f5	7810	/* Legacy defines */
Kojto	116:c0f6e94411f5	7811	#define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0 /!<Bit 0 /
Kojto	116:c0f6e94411f5	7812	#define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1 /!<Bit 1 /
Kojto	116:c0f6e94411f5	7813
Kojto	122:f9eeca106725	7814	#define WWDG_CFR_EWI 0x0200U /!<Early Wakeup Interrupt /
Kojto	107:4f6c30876dfa	7815
Kojto	107:4f6c30876dfa	7816	/***************** Bit definition for WWDG_SR register ******************/
Kojto	122:f9eeca106725	7817	#define WWDG_SR_EWIF 0x01U /!<Early Wakeup Interrupt Flag /
Kojto	107:4f6c30876dfa	7818
Kojto	107:4f6c30876dfa	7819	/******************************************************************************/
Kojto	107:4f6c30876dfa	7820	/* */
Kojto	107:4f6c30876dfa	7821	/* DBG */
Kojto	107:4f6c30876dfa	7822	/* */
Kojto	107:4f6c30876dfa	7823	/******************************************************************************/
Kojto	107:4f6c30876dfa	7824	/****************** Bit definition for DBGMCU_IDCODE register ***********/
Kojto	122:f9eeca106725	7825	#define DBGMCU_IDCODE_DEV_ID 0x00000FFFU
Kojto	122:f9eeca106725	7826	#define DBGMCU_IDCODE_REV_ID 0xFFFF0000U
Kojto	107:4f6c30876dfa	7827
Kojto	107:4f6c30876dfa	7828	/****************** Bit definition for DBGMCU_CR register ***************/
Kojto	122:f9eeca106725	7829	#define DBGMCU_CR_DBG_SLEEP 0x00000001U
Kojto	122:f9eeca106725	7830	#define DBGMCU_CR_DBG_STOP 0x00000002U
Kojto	122:f9eeca106725	7831	#define DBGMCU_CR_DBG_STANDBY 0x00000004U
Kojto	122:f9eeca106725	7832	#define DBGMCU_CR_TRACE_IOEN 0x00000020U
Kojto	122:f9eeca106725	7833
Kojto	122:f9eeca106725	7834	#define DBGMCU_CR_TRACE_MODE 0x000000C0U
Kojto	122:f9eeca106725	7835	#define DBGMCU_CR_TRACE_MODE_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	7836	#define DBGMCU_CR_TRACE_MODE_1 0x00000080U /!<Bit 1 /
Kojto	107:4f6c30876dfa	7837
Kojto	107:4f6c30876dfa	7838	/****************** Bit definition for DBGMCU_APB1_FZ register **********/
Kojto	122:f9eeca106725	7839	#define DBGMCU_APB1_FZ_DBG_TIM2_STOP 0x00000001U
Kojto	122:f9eeca106725	7840	#define DBGMCU_APB1_FZ_DBG_TIM3_STOP 0x00000002U
Kojto	122:f9eeca106725	7841	#define DBGMCU_APB1_FZ_DBG_TIM4_STOP 0x00000004U
Kojto	122:f9eeca106725	7842	#define DBGMCU_APB1_FZ_DBG_TIM5_STOP 0x00000008U
Kojto	122:f9eeca106725	7843	#define DBGMCU_APB1_FZ_DBG_TIM6_STOP 0x00000010U
Kojto	122:f9eeca106725	7844	#define DBGMCU_APB1_FZ_DBG_TIM7_STOP 0x00000020U
Kojto	122:f9eeca106725	7845	#define DBGMCU_APB1_FZ_DBG_TIM12_STOP 0x00000040U
Kojto	122:f9eeca106725	7846	#define DBGMCU_APB1_FZ_DBG_TIM13_STOP 0x00000080U
Kojto	122:f9eeca106725	7847	#define DBGMCU_APB1_FZ_DBG_TIM14_STOP 0x00000100U
Kojto	122:f9eeca106725	7848	#define DBGMCU_APB1_FZ_DBG_RTC_STOP 0x00000400U
Kojto	122:f9eeca106725	7849	#define DBGMCU_APB1_FZ_DBG_WWDG_STOP 0x00000800U
Kojto	122:f9eeca106725	7850	#define DBGMCU_APB1_FZ_DBG_IWDG_STOP 0x00001000U
Kojto	122:f9eeca106725	7851	#define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT 0x00200000U
Kojto	122:f9eeca106725	7852	#define DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT 0x00400000U
Kojto	122:f9eeca106725	7853	#define DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT 0x00800000U
Kojto	122:f9eeca106725	7854	#define DBGMCU_APB1_FZ_DBG_CAN1_STOP 0x02000000U
Kojto	122:f9eeca106725	7855	#define DBGMCU_APB1_FZ_DBG_CAN2_STOP 0x04000000U
Kojto	107:4f6c30876dfa	7856
Kojto	107:4f6c30876dfa	7857	/****************** Bit definition for DBGMCU_APB2_FZ register **********/
Kojto	122:f9eeca106725	7858	#define DBGMCU_APB2_FZ_DBG_TIM1_STOP 0x00000001U
Kojto	122:f9eeca106725	7859	#define DBGMCU_APB2_FZ_DBG_TIM8_STOP 0x00000002U
Kojto	122:f9eeca106725	7860	#define DBGMCU_APB2_FZ_DBG_TIM9_STOP 0x00010000U
Kojto	122:f9eeca106725	7861	#define DBGMCU_APB2_FZ_DBG_TIM10_STOP 0x00020000U
Kojto	122:f9eeca106725	7862	#define DBGMCU_APB2_FZ_DBG_TIM11_STOP 0x00040000U
Kojto	107:4f6c30876dfa	7863
Kojto	107:4f6c30876dfa	7864	/******************************************************************************/
Kojto	107:4f6c30876dfa	7865	/* */
Kojto	107:4f6c30876dfa	7866	/* Ethernet MAC Registers bits definitions */
Kojto	107:4f6c30876dfa	7867	/* */
Kojto	107:4f6c30876dfa	7868	/******************************************************************************/
Kojto	107:4f6c30876dfa	7869	/* Bit definition for Ethernet MAC Control Register register */
Kojto	122:f9eeca106725	7870	#define ETH_MACCR_WD 0x00800000U /* Watchdog disable */
Kojto	122:f9eeca106725	7871	#define ETH_MACCR_JD 0x00400000U /* Jabber disable */
Kojto	122:f9eeca106725	7872	#define ETH_MACCR_IFG 0x000E0000U /* Inter-frame gap */
Kojto	122:f9eeca106725	7873	#define ETH_MACCR_IFG_96Bit 0x00000000U /* Minimum IFG between frames during transmission is 96Bit */
Kojto	122:f9eeca106725	7874	#define ETH_MACCR_IFG_88Bit 0x00020000U /* Minimum IFG between frames during transmission is 88Bit */
Kojto	122:f9eeca106725	7875	#define ETH_MACCR_IFG_80Bit 0x00040000U /* Minimum IFG between frames during transmission is 80Bit */
Kojto	122:f9eeca106725	7876	#define ETH_MACCR_IFG_72Bit 0x00060000U /* Minimum IFG between frames during transmission is 72Bit */
Kojto	122:f9eeca106725	7877	#define ETH_MACCR_IFG_64Bit 0x00080000U /* Minimum IFG between frames during transmission is 64Bit */
Kojto	122:f9eeca106725	7878	#define ETH_MACCR_IFG_56Bit 0x000A0000U /* Minimum IFG between frames during transmission is 56Bit */
Kojto	122:f9eeca106725	7879	#define ETH_MACCR_IFG_48Bit 0x000C0000U /* Minimum IFG between frames during transmission is 48Bit */
Kojto	122:f9eeca106725	7880	#define ETH_MACCR_IFG_40Bit 0x000E0000U /* Minimum IFG between frames during transmission is 40Bit */
Kojto	122:f9eeca106725	7881	#define ETH_MACCR_CSD 0x00010000U /* Carrier sense disable (during transmission) */
Kojto	122:f9eeca106725	7882	#define ETH_MACCR_FES 0x00004000U /* Fast ethernet speed */
Kojto	122:f9eeca106725	7883	#define ETH_MACCR_ROD 0x00002000U /* Receive own disable */
Kojto	122:f9eeca106725	7884	#define ETH_MACCR_LM 0x00001000U /* loopback mode */
Kojto	122:f9eeca106725	7885	#define ETH_MACCR_DM 0x00000800U /* Duplex mode */
Kojto	122:f9eeca106725	7886	#define ETH_MACCR_IPCO 0x00000400U /* IP Checksum offload */
Kojto	122:f9eeca106725	7887	#define ETH_MACCR_RD 0x00000200U /* Retry disable */
Kojto	122:f9eeca106725	7888	#define ETH_MACCR_APCS 0x00000080U /* Automatic Pad/CRC stripping */
Kojto	122:f9eeca106725	7889	#define ETH_MACCR_BL 0x00000060U /* Back-off limit: random integer number (r) of slot time delays before rescheduling
Kojto	107:4f6c30876dfa	7890	a transmission attempt during retries after a collision: 0 =< r <2^k */
Kojto	122:f9eeca106725	7891	#define ETH_MACCR_BL_10 0x00000000U /* k = min (n, 10) */
Kojto	122:f9eeca106725	7892	#define ETH_MACCR_BL_8 0x00000020U /* k = min (n, 8) */
Kojto	122:f9eeca106725	7893	#define ETH_MACCR_BL_4 0x00000040U /* k = min (n, 4) */
Kojto	122:f9eeca106725	7894	#define ETH_MACCR_BL_1 0x00000060U /* k = min (n, 1) */
Kojto	122:f9eeca106725	7895	#define ETH_MACCR_DC 0x00000010U /* Defferal check */
Kojto	122:f9eeca106725	7896	#define ETH_MACCR_TE 0x00000008U /* Transmitter enable */
Kojto	122:f9eeca106725	7897	#define ETH_MACCR_RE 0x00000004U /* Receiver enable */
Kojto	107:4f6c30876dfa	7898
Kojto	107:4f6c30876dfa	7899	/* Bit definition for Ethernet MAC Frame Filter Register */
Kojto	122:f9eeca106725	7900	#define ETH_MACFFR_RA 0x80000000U /* Receive all */
Kojto	122:f9eeca106725	7901	#define ETH_MACFFR_HPF 0x00000400U /* Hash or perfect filter */
Kojto	122:f9eeca106725	7902	#define ETH_MACFFR_SAF 0x00000200U /* Source address filter enable */
Kojto	122:f9eeca106725	7903	#define ETH_MACFFR_SAIF 0x00000100U /* SA inverse filtering */
Kojto	122:f9eeca106725	7904	#define ETH_MACFFR_PCF 0x000000C0U /* Pass control frames: 3 cases */
Kojto	122:f9eeca106725	7905	#define ETH_MACFFR_PCF_BlockAll 0x00000040U /* MAC filters all control frames from reaching the application */
Kojto	122:f9eeca106725	7906	#define ETH_MACFFR_PCF_ForwardAll 0x00000080U /* MAC forwards all control frames to application even if they fail the Address Filter */
Kojto	122:f9eeca106725	7907	#define ETH_MACFFR_PCF_ForwardPassedAddrFilter 0x000000C0U /* MAC forwards control frames that pass the Address Filter. */
Kojto	122:f9eeca106725	7908	#define ETH_MACFFR_BFD 0x00000020U /* Broadcast frame disable */
Kojto	122:f9eeca106725	7909	#define ETH_MACFFR_PAM 0x00000010U /* Pass all mutlicast */
Kojto	122:f9eeca106725	7910	#define ETH_MACFFR_DAIF 0x00000008U /* DA Inverse filtering */
Kojto	122:f9eeca106725	7911	#define ETH_MACFFR_HM 0x00000004U /* Hash multicast */
Kojto	122:f9eeca106725	7912	#define ETH_MACFFR_HU 0x00000002U /* Hash unicast */
Kojto	122:f9eeca106725	7913	#define ETH_MACFFR_PM 0x00000001U /* Promiscuous mode */
Kojto	107:4f6c30876dfa	7914
Kojto	107:4f6c30876dfa	7915	/* Bit definition for Ethernet MAC Hash Table High Register */
Kojto	122:f9eeca106725	7916	#define ETH_MACHTHR_HTH 0xFFFFFFFFU /* Hash table high */
Kojto	107:4f6c30876dfa	7917
Kojto	107:4f6c30876dfa	7918	/* Bit definition for Ethernet MAC Hash Table Low Register */
Kojto	122:f9eeca106725	7919	#define ETH_MACHTLR_HTL 0xFFFFFFFFU /* Hash table low */
Kojto	107:4f6c30876dfa	7920
Kojto	107:4f6c30876dfa	7921	/* Bit definition for Ethernet MAC MII Address Register */
Kojto	122:f9eeca106725	7922	#define ETH_MACMIIAR_PA 0x0000F800U /* Physical layer address */
Kojto	122:f9eeca106725	7923	#define ETH_MACMIIAR_MR 0x000007C0U /* MII register in the selected PHY */
Kojto	122:f9eeca106725	7924	#define ETH_MACMIIAR_CR 0x0000001CU /* CR clock range: 6 cases */
Kojto	122:f9eeca106725	7925	#define ETH_MACMIIAR_CR_Div42 0x00000000U /* HCLK:60-100 MHz; MDC clock= HCLK/42 */
Kojto	122:f9eeca106725	7926	#define ETH_MACMIIAR_CR_Div62 0x00000004U /* HCLK:100-150 MHz; MDC clock= HCLK/62 */
Kojto	122:f9eeca106725	7927	#define ETH_MACMIIAR_CR_Div16 0x00000008U /* HCLK:20-35 MHz; MDC clock= HCLK/16 */
Kojto	122:f9eeca106725	7928	#define ETH_MACMIIAR_CR_Div26 0x0000000CU /* HCLK:35-60 MHz; MDC clock= HCLK/26 */
Kojto	122:f9eeca106725	7929	#define ETH_MACMIIAR_CR_Div102 0x00000010U /* HCLK:150-168 MHz; MDC clock= HCLK/102 */
Kojto	122:f9eeca106725	7930	#define ETH_MACMIIAR_MW 0x00000002U /* MII write */
Kojto	122:f9eeca106725	7931	#define ETH_MACMIIAR_MB 0x00000001U /* MII busy */
Kojto	107:4f6c30876dfa	7932
Kojto	107:4f6c30876dfa	7933	/* Bit definition for Ethernet MAC MII Data Register */
Kojto	122:f9eeca106725	7934	#define ETH_MACMIIDR_MD 0x0000FFFFU /* MII data: read/write data from/to PHY */
Kojto	107:4f6c30876dfa	7935
Kojto	107:4f6c30876dfa	7936	/* Bit definition for Ethernet MAC Flow Control Register */
Kojto	122:f9eeca106725	7937	#define ETH_MACFCR_PT 0xFFFF0000U /* Pause time */
Kojto	122:f9eeca106725	7938	#define ETH_MACFCR_ZQPD 0x00000080U /* Zero-quanta pause disable */
Kojto	122:f9eeca106725	7939	#define ETH_MACFCR_PLT 0x00000030U /* Pause low threshold: 4 cases */
Kojto	122:f9eeca106725	7940	#define ETH_MACFCR_PLT_Minus4 0x00000000U /* Pause time minus 4 slot times */
Kojto	122:f9eeca106725	7941	#define ETH_MACFCR_PLT_Minus28 0x00000010U /* Pause time minus 28 slot times */
Kojto	122:f9eeca106725	7942	#define ETH_MACFCR_PLT_Minus144 0x00000020U /* Pause time minus 144 slot times */
Kojto	122:f9eeca106725	7943	#define ETH_MACFCR_PLT_Minus256 0x00000030U /* Pause time minus 256 slot times */
Kojto	122:f9eeca106725	7944	#define ETH_MACFCR_UPFD 0x00000008U /* Unicast pause frame detect */
Kojto	122:f9eeca106725	7945	#define ETH_MACFCR_RFCE 0x00000004U /* Receive flow control enable */
Kojto	122:f9eeca106725	7946	#define ETH_MACFCR_TFCE 0x00000002U /* Transmit flow control enable */
Kojto	122:f9eeca106725	7947	#define ETH_MACFCR_FCBBPA 0x00000001U /* Flow control busy/backpressure activate */
Kojto	107:4f6c30876dfa	7948
Kojto	107:4f6c30876dfa	7949	/* Bit definition for Ethernet MAC VLAN Tag Register */
Kojto	122:f9eeca106725	7950	#define ETH_MACVLANTR_VLANTC 0x00010000U /* 12-bit VLAN tag comparison */
Kojto	122:f9eeca106725	7951	#define ETH_MACVLANTR_VLANTI 0x0000FFFFU /* VLAN tag identifier (for receive frames) */
Kojto	107:4f6c30876dfa	7952
Kojto	107:4f6c30876dfa	7953	/* Bit definition for Ethernet MAC Remote Wake-UpFrame Filter Register */
Kojto	122:f9eeca106725	7954	#define ETH_MACRWUFFR_D 0xFFFFFFFFU /* Wake-up frame filter register data */
Kojto	107:4f6c30876dfa	7955	/* Eight sequential Writes to this address (offset 0x28) will write all Wake-UpFrame Filter Registers.
Kojto	107:4f6c30876dfa	7956	Eight sequential Reads from this address (offset 0x28) will read all Wake-UpFrame Filter Registers. */
Kojto	107:4f6c30876dfa	7957	/* Wake-UpFrame Filter Reg0 : Filter 0 Byte Mask
Kojto	107:4f6c30876dfa	7958	Wake-UpFrame Filter Reg1 : Filter 1 Byte Mask
Kojto	107:4f6c30876dfa	7959	Wake-UpFrame Filter Reg2 : Filter 2 Byte Mask
Kojto	107:4f6c30876dfa	7960	Wake-UpFrame Filter Reg3 : Filter 3 Byte Mask
Kojto	107:4f6c30876dfa	7961	Wake-UpFrame Filter Reg4 : RSVD - Filter3 Command - RSVD - Filter2 Command -
Kojto	107:4f6c30876dfa	7962	RSVD - Filter1 Command - RSVD - Filter0 Command
Kojto	107:4f6c30876dfa	7963	Wake-UpFrame Filter Re5 : Filter3 Offset - Filter2 Offset - Filter1 Offset - Filter0 Offset
Kojto	107:4f6c30876dfa	7964	Wake-UpFrame Filter Re6 : Filter1 CRC16 - Filter0 CRC16
Kojto	107:4f6c30876dfa	7965	Wake-UpFrame Filter Re7 : Filter3 CRC16 - Filter2 CRC16 */
Kojto	107:4f6c30876dfa	7966
Kojto	107:4f6c30876dfa	7967	/* Bit definition for Ethernet MAC PMT Control and Status Register */
Kojto	122:f9eeca106725	7968	#define ETH_MACPMTCSR_WFFRPR 0x80000000U /* Wake-Up Frame Filter Register Pointer Reset */
Kojto	122:f9eeca106725	7969	#define ETH_MACPMTCSR_GU 0x00000200U /* Global Unicast */
Kojto	122:f9eeca106725	7970	#define ETH_MACPMTCSR_WFR 0x00000040U /* Wake-Up Frame Received */
Kojto	122:f9eeca106725	7971	#define ETH_MACPMTCSR_MPR 0x00000020U /* Magic Packet Received */
Kojto	122:f9eeca106725	7972	#define ETH_MACPMTCSR_WFE 0x00000004U /* Wake-Up Frame Enable */
Kojto	122:f9eeca106725	7973	#define ETH_MACPMTCSR_MPE 0x00000002U /* Magic Packet Enable */
Kojto	122:f9eeca106725	7974	#define ETH_MACPMTCSR_PD 0x00000001U /* Power Down */
Kojto	107:4f6c30876dfa	7975
Kojto	107:4f6c30876dfa	7976	/* Bit definition for Ethernet MAC Status Register */
Kojto	122:f9eeca106725	7977	#define ETH_MACSR_TSTS 0x00000200U /* Time stamp trigger status */
Kojto	122:f9eeca106725	7978	#define ETH_MACSR_MMCTS 0x00000040U /* MMC transmit status */
Kojto	122:f9eeca106725	7979	#define ETH_MACSR_MMMCRS 0x00000020U /* MMC receive status */
Kojto	122:f9eeca106725	7980	#define ETH_MACSR_MMCS 0x00000010U /* MMC status */
Kojto	122:f9eeca106725	7981	#define ETH_MACSR_PMTS 0x00000008U /* PMT status */
Kojto	107:4f6c30876dfa	7982
Kojto	107:4f6c30876dfa	7983	/* Bit definition for Ethernet MAC Interrupt Mask Register */
Kojto	122:f9eeca106725	7984	#define ETH_MACIMR_TSTIM 0x00000200U /* Time stamp trigger interrupt mask */
Kojto	122:f9eeca106725	7985	#define ETH_MACIMR_PMTIM 0x00000008U /* PMT interrupt mask */
Kojto	107:4f6c30876dfa	7986
Kojto	107:4f6c30876dfa	7987	/* Bit definition for Ethernet MAC Address0 High Register */
Kojto	122:f9eeca106725	7988	#define ETH_MACA0HR_MACA0H 0x0000FFFFU /* MAC address0 high */
Kojto	107:4f6c30876dfa	7989
Kojto	107:4f6c30876dfa	7990	/* Bit definition for Ethernet MAC Address0 Low Register */
Kojto	122:f9eeca106725	7991	#define ETH_MACA0LR_MACA0L 0xFFFFFFFFU /* MAC address0 low */
Kojto	107:4f6c30876dfa	7992
Kojto	107:4f6c30876dfa	7993	/* Bit definition for Ethernet MAC Address1 High Register */
Kojto	122:f9eeca106725	7994	#define ETH_MACA1HR_AE 0x80000000U /* Address enable */
Kojto	122:f9eeca106725	7995	#define ETH_MACA1HR_SA 0x40000000U /* Source address */
Kojto	122:f9eeca106725	7996	#define ETH_MACA1HR_MBC 0x3F000000U /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
Kojto	122:f9eeca106725	7997	#define ETH_MACA1HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto	122:f9eeca106725	7998	#define ETH_MACA1HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto	122:f9eeca106725	7999	#define ETH_MACA1HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto	122:f9eeca106725	8000	#define ETH_MACA1HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto	122:f9eeca106725	8001	#define ETH_MACA1HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto	122:f9eeca106725	8002	#define ETH_MACA1HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [7:0] */
Kojto	122:f9eeca106725	8003	#define ETH_MACA1HR_MACA1H 0x0000FFFFU /* MAC address1 high */
Kojto	107:4f6c30876dfa	8004
Kojto	107:4f6c30876dfa	8005	/* Bit definition for Ethernet MAC Address1 Low Register */
Kojto	122:f9eeca106725	8006	#define ETH_MACA1LR_MACA1L 0xFFFFFFFFU /* MAC address1 low */
Kojto	107:4f6c30876dfa	8007
Kojto	107:4f6c30876dfa	8008	/* Bit definition for Ethernet MAC Address2 High Register */
Kojto	122:f9eeca106725	8009	#define ETH_MACA2HR_AE 0x80000000U /* Address enable */
Kojto	122:f9eeca106725	8010	#define ETH_MACA2HR_SA 0x40000000U /* Source address */
Kojto	122:f9eeca106725	8011	#define ETH_MACA2HR_MBC 0x3F000000U /* Mask byte control */
Kojto	122:f9eeca106725	8012	#define ETH_MACA2HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto	122:f9eeca106725	8013	#define ETH_MACA2HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto	122:f9eeca106725	8014	#define ETH_MACA2HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto	122:f9eeca106725	8015	#define ETH_MACA2HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto	122:f9eeca106725	8016	#define ETH_MACA2HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto	122:f9eeca106725	8017	#define ETH_MACA2HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
Kojto	122:f9eeca106725	8018	#define ETH_MACA2HR_MACA2H 0x0000FFFFU /* MAC address1 high */
Kojto	107:4f6c30876dfa	8019
Kojto	107:4f6c30876dfa	8020	/* Bit definition for Ethernet MAC Address2 Low Register */
Kojto	122:f9eeca106725	8021	#define ETH_MACA2LR_MACA2L 0xFFFFFFFFU /* MAC address2 low */
Kojto	107:4f6c30876dfa	8022
Kojto	107:4f6c30876dfa	8023	/* Bit definition for Ethernet MAC Address3 High Register */
Kojto	122:f9eeca106725	8024	#define ETH_MACA3HR_AE 0x80000000U /* Address enable */
Kojto	122:f9eeca106725	8025	#define ETH_MACA3HR_SA 0x40000000U /* Source address */
Kojto	122:f9eeca106725	8026	#define ETH_MACA3HR_MBC 0x3F000000U /* Mask byte control */
Kojto	122:f9eeca106725	8027	#define ETH_MACA3HR_MBC_HBits15_8 0x20000000U /* Mask MAC Address high reg bits [15:8] */
Kojto	122:f9eeca106725	8028	#define ETH_MACA3HR_MBC_HBits7_0 0x10000000U /* Mask MAC Address high reg bits [7:0] */
Kojto	122:f9eeca106725	8029	#define ETH_MACA3HR_MBC_LBits31_24 0x08000000U /* Mask MAC Address low reg bits [31:24] */
Kojto	122:f9eeca106725	8030	#define ETH_MACA3HR_MBC_LBits23_16 0x04000000U /* Mask MAC Address low reg bits [23:16] */
Kojto	122:f9eeca106725	8031	#define ETH_MACA3HR_MBC_LBits15_8 0x02000000U /* Mask MAC Address low reg bits [15:8] */
Kojto	122:f9eeca106725	8032	#define ETH_MACA3HR_MBC_LBits7_0 0x01000000U /* Mask MAC Address low reg bits [70] */
Kojto	122:f9eeca106725	8033	#define ETH_MACA3HR_MACA3H 0x0000FFFFU /* MAC address3 high */
Kojto	107:4f6c30876dfa	8034
Kojto	107:4f6c30876dfa	8035	/* Bit definition for Ethernet MAC Address3 Low Register */
Kojto	122:f9eeca106725	8036	#define ETH_MACA3LR_MACA3L 0xFFFFFFFFU /* MAC address3 low */
Kojto	107:4f6c30876dfa	8037
Kojto	107:4f6c30876dfa	8038	/******************************************************************************/
Kojto	107:4f6c30876dfa	8039	/* Ethernet MMC Registers bits definition */
Kojto	107:4f6c30876dfa	8040	/******************************************************************************/
Kojto	107:4f6c30876dfa	8041
Kojto	107:4f6c30876dfa	8042	/* Bit definition for Ethernet MMC Contol Register */
Kojto	122:f9eeca106725	8043	#define ETH_MMCCR_MCFHP 0x00000020U /* MMC counter Full-Half preset */
Kojto	122:f9eeca106725	8044	#define ETH_MMCCR_MCP 0x00000010U /* MMC counter preset */
Kojto	122:f9eeca106725	8045	#define ETH_MMCCR_MCF 0x00000008U /* MMC Counter Freeze */
Kojto	122:f9eeca106725	8046	#define ETH_MMCCR_ROR 0x00000004U /* Reset on Read */
Kojto	122:f9eeca106725	8047	#define ETH_MMCCR_CSR 0x00000002U /* Counter Stop Rollover */
Kojto	122:f9eeca106725	8048	#define ETH_MMCCR_CR 0x00000001U /* Counters Reset */
Kojto	107:4f6c30876dfa	8049
Kojto	107:4f6c30876dfa	8050	/* Bit definition for Ethernet MMC Receive Interrupt Register */
Kojto	122:f9eeca106725	8051	#define ETH_MMCRIR_RGUFS 0x00020000U /* Set when Rx good unicast frames counter reaches half the maximum value */
Kojto	122:f9eeca106725	8052	#define ETH_MMCRIR_RFAES 0x00000040U /* Set when Rx alignment error counter reaches half the maximum value */
Kojto	122:f9eeca106725	8053	#define ETH_MMCRIR_RFCES 0x00000020U /* Set when Rx crc error counter reaches half the maximum value */
Kojto	107:4f6c30876dfa	8054
Kojto	107:4f6c30876dfa	8055	/* Bit definition for Ethernet MMC Transmit Interrupt Register */
Kojto	122:f9eeca106725	8056	#define ETH_MMCTIR_TGFS 0x00200000U /* Set when Tx good frame count counter reaches half the maximum value */
Kojto	122:f9eeca106725	8057	#define ETH_MMCTIR_TGFMSCS 0x00008000U /* Set when Tx good multi col counter reaches half the maximum value */
Kojto	122:f9eeca106725	8058	#define ETH_MMCTIR_TGFSCS 0x00004000U /* Set when Tx good single col counter reaches half the maximum value */
Kojto	107:4f6c30876dfa	8059
Kojto	107:4f6c30876dfa	8060	/* Bit definition for Ethernet MMC Receive Interrupt Mask Register */
Kojto	122:f9eeca106725	8061	#define ETH_MMCRIMR_RGUFM 0x00020000U /* Mask the interrupt when Rx good unicast frames counter reaches half the maximum value */
Kojto	122:f9eeca106725	8062	#define ETH_MMCRIMR_RFAEM 0x00000040U /* Mask the interrupt when when Rx alignment error counter reaches half the maximum value */
Kojto	122:f9eeca106725	8063	#define ETH_MMCRIMR_RFCEM 0x00000020U /* Mask the interrupt when Rx crc error counter reaches half the maximum value */
Kojto	107:4f6c30876dfa	8064
Kojto	107:4f6c30876dfa	8065	/* Bit definition for Ethernet MMC Transmit Interrupt Mask Register */
Kojto	122:f9eeca106725	8066	#define ETH_MMCTIMR_TGFM 0x00200000U /* Mask the interrupt when Tx good frame count counter reaches half the maximum value */
Kojto	122:f9eeca106725	8067	#define ETH_MMCTIMR_TGFMSCM 0x00008000U /* Mask the interrupt when Tx good multi col counter reaches half the maximum value */
Kojto	122:f9eeca106725	8068	#define ETH_MMCTIMR_TGFSCM 0x00004000U /* Mask the interrupt when Tx good single col counter reaches half the maximum value */
Kojto	107:4f6c30876dfa	8069
Kojto	107:4f6c30876dfa	8070	/* Bit definition for Ethernet MMC Transmitted Good Frames after Single Collision Counter Register */
Kojto	122:f9eeca106725	8071	#define ETH_MMCTGFSCCR_TGFSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after a single collision in Half-duplex mode. */
Kojto	107:4f6c30876dfa	8072
Kojto	107:4f6c30876dfa	8073	/* Bit definition for Ethernet MMC Transmitted Good Frames after More than a Single Collision Counter Register */
Kojto	122:f9eeca106725	8074	#define ETH_MMCTGFMSCCR_TGFMSCC 0xFFFFFFFFU /* Number of successfully transmitted frames after more than a single collision in Half-duplex mode. */
Kojto	107:4f6c30876dfa	8075
Kojto	107:4f6c30876dfa	8076	/* Bit definition for Ethernet MMC Transmitted Good Frames Counter Register */
Kojto	122:f9eeca106725	8077	#define ETH_MMCTGFCR_TGFC 0xFFFFFFFFU /* Number of good frames transmitted. */
Kojto	107:4f6c30876dfa	8078
Kojto	107:4f6c30876dfa	8079	/* Bit definition for Ethernet MMC Received Frames with CRC Error Counter Register */
Kojto	122:f9eeca106725	8080	#define ETH_MMCRFCECR_RFCEC 0xFFFFFFFFU /* Number of frames received with CRC error. */
Kojto	107:4f6c30876dfa	8081
Kojto	107:4f6c30876dfa	8082	/* Bit definition for Ethernet MMC Received Frames with Alignement Error Counter Register */
Kojto	122:f9eeca106725	8083	#define ETH_MMCRFAECR_RFAEC 0xFFFFFFFFU /* Number of frames received with alignment (dribble) error */
Kojto	107:4f6c30876dfa	8084
Kojto	107:4f6c30876dfa	8085	/* Bit definition for Ethernet MMC Received Good Unicast Frames Counter Register */
Kojto	122:f9eeca106725	8086	#define ETH_MMCRGUFCR_RGUFC 0xFFFFFFFFU /* Number of good unicast frames received. */
Kojto	107:4f6c30876dfa	8087
Kojto	107:4f6c30876dfa	8088	/******************************************************************************/
Kojto	107:4f6c30876dfa	8089	/* Ethernet PTP Registers bits definition */
Kojto	107:4f6c30876dfa	8090	/******************************************************************************/
Kojto	107:4f6c30876dfa	8091
Kojto	107:4f6c30876dfa	8092	/* Bit definition for Ethernet PTP Time Stamp Contol Register */
Kojto	122:f9eeca106725	8093	#define ETH_PTPTSCR_TSCNT 0x00030000U /* Time stamp clock node type */
Kojto	122:f9eeca106725	8094	#define ETH_PTPTSSR_TSSMRME 0x00008000U /* Time stamp snapshot for message relevant to master enable */
Kojto	122:f9eeca106725	8095	#define ETH_PTPTSSR_TSSEME 0x00004000U /* Time stamp snapshot for event message enable */
Kojto	122:f9eeca106725	8096	#define ETH_PTPTSSR_TSSIPV4FE 0x00002000U /* Time stamp snapshot for IPv4 frames enable */
Kojto	122:f9eeca106725	8097	#define ETH_PTPTSSR_TSSIPV6FE 0x00001000U /* Time stamp snapshot for IPv6 frames enable */
Kojto	122:f9eeca106725	8098	#define ETH_PTPTSSR_TSSPTPOEFE 0x00000800U /* Time stamp snapshot for PTP over ethernet frames enable */
Kojto	122:f9eeca106725	8099	#define ETH_PTPTSSR_TSPTPPSV2E 0x00000400U /* Time stamp PTP packet snooping for version2 format enable */
Kojto	122:f9eeca106725	8100	#define ETH_PTPTSSR_TSSSR 0x00000200U /* Time stamp Sub-seconds rollover */
Kojto	122:f9eeca106725	8101	#define ETH_PTPTSSR_TSSARFE 0x00000100U /* Time stamp snapshot for all received frames enable */
Kojto	122:f9eeca106725	8102
Kojto	122:f9eeca106725	8103	#define ETH_PTPTSCR_TSARU 0x00000020U /* Addend register update */
Kojto	122:f9eeca106725	8104	#define ETH_PTPTSCR_TSITE 0x00000010U /* Time stamp interrupt trigger enable */
Kojto	122:f9eeca106725	8105	#define ETH_PTPTSCR_TSSTU 0x00000008U /* Time stamp update */
Kojto	122:f9eeca106725	8106	#define ETH_PTPTSCR_TSSTI 0x00000004U /* Time stamp initialize */
Kojto	122:f9eeca106725	8107	#define ETH_PTPTSCR_TSFCU 0x00000002U /* Time stamp fine or coarse update */
Kojto	122:f9eeca106725	8108	#define ETH_PTPTSCR_TSE 0x00000001U /* Time stamp enable */
Kojto	107:4f6c30876dfa	8109
Kojto	107:4f6c30876dfa	8110	/* Bit definition for Ethernet PTP Sub-Second Increment Register */
Kojto	122:f9eeca106725	8111	#define ETH_PTPSSIR_STSSI 0x000000FFU /* System time Sub-second increment value */
Kojto	107:4f6c30876dfa	8112
Kojto	107:4f6c30876dfa	8113	/* Bit definition for Ethernet PTP Time Stamp High Register */
Kojto	122:f9eeca106725	8114	#define ETH_PTPTSHR_STS 0xFFFFFFFFU /* System Time second */
Kojto	107:4f6c30876dfa	8115
Kojto	107:4f6c30876dfa	8116	/* Bit definition for Ethernet PTP Time Stamp Low Register */
Kojto	122:f9eeca106725	8117	#define ETH_PTPTSLR_STPNS 0x80000000U /* System Time Positive or negative time */
Kojto	122:f9eeca106725	8118	#define ETH_PTPTSLR_STSS 0x7FFFFFFFU /* System Time sub-seconds */
Kojto	107:4f6c30876dfa	8119
Kojto	107:4f6c30876dfa	8120	/* Bit definition for Ethernet PTP Time Stamp High Update Register */
Kojto	122:f9eeca106725	8121	#define ETH_PTPTSHUR_TSUS 0xFFFFFFFFU /* Time stamp update seconds */
Kojto	107:4f6c30876dfa	8122
Kojto	107:4f6c30876dfa	8123	/* Bit definition for Ethernet PTP Time Stamp Low Update Register */
Kojto	122:f9eeca106725	8124	#define ETH_PTPTSLUR_TSUPNS 0x80000000U /* Time stamp update Positive or negative time */
Kojto	122:f9eeca106725	8125	#define ETH_PTPTSLUR_TSUSS 0x7FFFFFFFU /* Time stamp update sub-seconds */
Kojto	107:4f6c30876dfa	8126
Kojto	107:4f6c30876dfa	8127	/* Bit definition for Ethernet PTP Time Stamp Addend Register */
Kojto	122:f9eeca106725	8128	#define ETH_PTPTSAR_TSA 0xFFFFFFFFU /* Time stamp addend */
Kojto	107:4f6c30876dfa	8129
Kojto	107:4f6c30876dfa	8130	/* Bit definition for Ethernet PTP Target Time High Register */
Kojto	122:f9eeca106725	8131	#define ETH_PTPTTHR_TTSH 0xFFFFFFFFU /* Target time stamp high */
Kojto	107:4f6c30876dfa	8132
Kojto	107:4f6c30876dfa	8133	/* Bit definition for Ethernet PTP Target Time Low Register */
Kojto	122:f9eeca106725	8134	#define ETH_PTPTTLR_TTSL 0xFFFFFFFFU /* Target time stamp low */
Kojto	107:4f6c30876dfa	8135
Kojto	107:4f6c30876dfa	8136	/* Bit definition for Ethernet PTP Time Stamp Status Register */
Kojto	122:f9eeca106725	8137	#define ETH_PTPTSSR_TSTTR 0x00000020U /* Time stamp target time reached */
Kojto	122:f9eeca106725	8138	#define ETH_PTPTSSR_TSSO 0x00000010U /* Time stamp seconds overflow */
Kojto	107:4f6c30876dfa	8139
Kojto	107:4f6c30876dfa	8140	/******************************************************************************/
Kojto	107:4f6c30876dfa	8141	/* Ethernet DMA Registers bits definition */
Kojto	107:4f6c30876dfa	8142	/******************************************************************************/
Kojto	107:4f6c30876dfa	8143
Kojto	107:4f6c30876dfa	8144	/* Bit definition for Ethernet DMA Bus Mode Register */
Kojto	122:f9eeca106725	8145	#define ETH_DMABMR_AAB 0x02000000U /* Address-Aligned beats */
Kojto	122:f9eeca106725	8146	#define ETH_DMABMR_FPM 0x01000000U /* 4xPBL mode */
Kojto	122:f9eeca106725	8147	#define ETH_DMABMR_USP 0x00800000U /* Use separate PBL */
Kojto	122:f9eeca106725	8148	#define ETH_DMABMR_RDP 0x007E0000U /* RxDMA PBL */
Kojto	122:f9eeca106725	8149	#define ETH_DMABMR_RDP_1Beat 0x00020000U /* maximum number of beats to be transferred in one RxDMA transaction is 1 */
Kojto	122:f9eeca106725	8150	#define ETH_DMABMR_RDP_2Beat 0x00040000U /* maximum number of beats to be transferred in one RxDMA transaction is 2 */
Kojto	122:f9eeca106725	8151	#define ETH_DMABMR_RDP_4Beat 0x00080000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto	122:f9eeca106725	8152	#define ETH_DMABMR_RDP_8Beat 0x00100000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto	122:f9eeca106725	8153	#define ETH_DMABMR_RDP_16Beat 0x00200000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto	122:f9eeca106725	8154	#define ETH_DMABMR_RDP_32Beat 0x00400000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto	122:f9eeca106725	8155	#define ETH_DMABMR_RDP_4xPBL_4Beat 0x01020000U /* maximum number of beats to be transferred in one RxDMA transaction is 4 */
Kojto	122:f9eeca106725	8156	#define ETH_DMABMR_RDP_4xPBL_8Beat 0x01040000U /* maximum number of beats to be transferred in one RxDMA transaction is 8 */
Kojto	122:f9eeca106725	8157	#define ETH_DMABMR_RDP_4xPBL_16Beat 0x01080000U /* maximum number of beats to be transferred in one RxDMA transaction is 16 */
Kojto	122:f9eeca106725	8158	#define ETH_DMABMR_RDP_4xPBL_32Beat 0x01100000U /* maximum number of beats to be transferred in one RxDMA transaction is 32 */
Kojto	122:f9eeca106725	8159	#define ETH_DMABMR_RDP_4xPBL_64Beat 0x01200000U /* maximum number of beats to be transferred in one RxDMA transaction is 64 */
Kojto	122:f9eeca106725	8160	#define ETH_DMABMR_RDP_4xPBL_128Beat 0x01400000U /* maximum number of beats to be transferred in one RxDMA transaction is 128 */
Kojto	122:f9eeca106725	8161	#define ETH_DMABMR_FB 0x00010000U /* Fixed Burst */
Kojto	122:f9eeca106725	8162	#define ETH_DMABMR_RTPR 0x0000C000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	8163	#define ETH_DMABMR_RTPR_1_1 0x00000000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	8164	#define ETH_DMABMR_RTPR_2_1 0x00004000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	8165	#define ETH_DMABMR_RTPR_3_1 0x00008000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	8166	#define ETH_DMABMR_RTPR_4_1 0x0000C000U /* Rx Tx priority ratio */
Kojto	122:f9eeca106725	8167	#define ETH_DMABMR_PBL 0x00003F00U /* Programmable burst length */
Kojto	122:f9eeca106725	8168	#define ETH_DMABMR_PBL_1Beat 0x00000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
Kojto	122:f9eeca106725	8169	#define ETH_DMABMR_PBL_2Beat 0x00000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
Kojto	122:f9eeca106725	8170	#define ETH_DMABMR_PBL_4Beat 0x00000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto	122:f9eeca106725	8171	#define ETH_DMABMR_PBL_8Beat 0x00000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto	122:f9eeca106725	8172	#define ETH_DMABMR_PBL_16Beat 0x00001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto	122:f9eeca106725	8173	#define ETH_DMABMR_PBL_32Beat 0x00002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto	122:f9eeca106725	8174	#define ETH_DMABMR_PBL_4xPBL_4Beat 0x01000100U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
Kojto	122:f9eeca106725	8175	#define ETH_DMABMR_PBL_4xPBL_8Beat 0x01000200U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
Kojto	122:f9eeca106725	8176	#define ETH_DMABMR_PBL_4xPBL_16Beat 0x01000400U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
Kojto	122:f9eeca106725	8177	#define ETH_DMABMR_PBL_4xPBL_32Beat 0x01000800U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
Kojto	122:f9eeca106725	8178	#define ETH_DMABMR_PBL_4xPBL_64Beat 0x01001000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
Kojto	122:f9eeca106725	8179	#define ETH_DMABMR_PBL_4xPBL_128Beat 0x01002000U /* maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
Kojto	122:f9eeca106725	8180	#define ETH_DMABMR_EDE 0x00000080U /* Enhanced Descriptor Enable */
Kojto	122:f9eeca106725	8181	#define ETH_DMABMR_DSL 0x0000007CU /* Descriptor Skip Length */
Kojto	122:f9eeca106725	8182	#define ETH_DMABMR_DA 0x00000002U /* DMA arbitration scheme */
Kojto	122:f9eeca106725	8183	#define ETH_DMABMR_SR 0x00000001U /* Software reset */
Kojto	107:4f6c30876dfa	8184
Kojto	107:4f6c30876dfa	8185	/* Bit definition for Ethernet DMA Transmit Poll Demand Register */
Kojto	122:f9eeca106725	8186	#define ETH_DMATPDR_TPD 0xFFFFFFFFU /* Transmit poll demand */
Kojto	107:4f6c30876dfa	8187
Kojto	107:4f6c30876dfa	8188	/* Bit definition for Ethernet DMA Receive Poll Demand Register */
Kojto	122:f9eeca106725	8189	#define ETH_DMARPDR_RPD 0xFFFFFFFFU /* Receive poll demand */
Kojto	107:4f6c30876dfa	8190
Kojto	107:4f6c30876dfa	8191	/* Bit definition for Ethernet DMA Receive Descriptor List Address Register */
Kojto	122:f9eeca106725	8192	#define ETH_DMARDLAR_SRL 0xFFFFFFFFU /* Start of receive list */
Kojto	107:4f6c30876dfa	8193
Kojto	107:4f6c30876dfa	8194	/* Bit definition for Ethernet DMA Transmit Descriptor List Address Register */
Kojto	122:f9eeca106725	8195	#define ETH_DMATDLAR_STL 0xFFFFFFFFU /* Start of transmit list */
Kojto	107:4f6c30876dfa	8196
Kojto	107:4f6c30876dfa	8197	/* Bit definition for Ethernet DMA Status Register */
Kojto	122:f9eeca106725	8198	#define ETH_DMASR_TSTS 0x20000000U /* Time-stamp trigger status */
Kojto	122:f9eeca106725	8199	#define ETH_DMASR_PMTS 0x10000000U /* PMT status */
Kojto	122:f9eeca106725	8200	#define ETH_DMASR_MMCS 0x08000000U /* MMC status */
Kojto	122:f9eeca106725	8201	#define ETH_DMASR_EBS 0x03800000U /* Error bits status */
Kojto	107:4f6c30876dfa	8202	/* combination with EBS[2:0] for GetFlagStatus function */
Kojto	122:f9eeca106725	8203	#define ETH_DMASR_EBS_DescAccess 0x02000000U /* Error bits 0-data buffer, 1-desc. access */
Kojto	122:f9eeca106725	8204	#define ETH_DMASR_EBS_ReadTransf 0x01000000U /* Error bits 0-write trnsf, 1-read transfr */
Kojto	122:f9eeca106725	8205	#define ETH_DMASR_EBS_DataTransfTx 0x00800000U /* Error bits 0-Rx DMA, 1-Tx DMA */
Kojto	122:f9eeca106725	8206	#define ETH_DMASR_TPS 0x00700000U /* Transmit process state */
Kojto	122:f9eeca106725	8207	#define ETH_DMASR_TPS_Stopped 0x00000000U /* Stopped - Reset or Stop Tx Command issued */
Kojto	122:f9eeca106725	8208	#define ETH_DMASR_TPS_Fetching 0x00100000U /* Running - fetching the Tx descriptor */
Kojto	122:f9eeca106725	8209	#define ETH_DMASR_TPS_Waiting 0x00200000U /* Running - waiting for status */
Kojto	122:f9eeca106725	8210	#define ETH_DMASR_TPS_Reading 0x00300000U /* Running - reading the data from host memory */
Kojto	122:f9eeca106725	8211	#define ETH_DMASR_TPS_Suspended 0x00600000U /* Suspended - Tx Descriptor unavailabe */
Kojto	122:f9eeca106725	8212	#define ETH_DMASR_TPS_Closing 0x00700000U /* Running - closing Rx descriptor */
Kojto	122:f9eeca106725	8213	#define ETH_DMASR_RPS 0x000E0000U /* Receive process state */
Kojto	122:f9eeca106725	8214	#define ETH_DMASR_RPS_Stopped 0x00000000U /* Stopped - Reset or Stop Rx Command issued */
Kojto	122:f9eeca106725	8215	#define ETH_DMASR_RPS_Fetching 0x00020000U /* Running - fetching the Rx descriptor */
Kojto	122:f9eeca106725	8216	#define ETH_DMASR_RPS_Waiting 0x00060000U /* Running - waiting for packet */
Kojto	122:f9eeca106725	8217	#define ETH_DMASR_RPS_Suspended 0x00080000U /* Suspended - Rx Descriptor unavailable */
Kojto	122:f9eeca106725	8218	#define ETH_DMASR_RPS_Closing 0x000A0000U /* Running - closing descriptor */
Kojto	122:f9eeca106725	8219	#define ETH_DMASR_RPS_Queuing 0x000E0000U /* Running - queuing the recieve frame into host memory */
Kojto	122:f9eeca106725	8220	#define ETH_DMASR_NIS 0x00010000U /* Normal interrupt summary */
Kojto	122:f9eeca106725	8221	#define ETH_DMASR_AIS 0x00008000U /* Abnormal interrupt summary */
Kojto	122:f9eeca106725	8222	#define ETH_DMASR_ERS 0x00004000U /* Early receive status */
Kojto	122:f9eeca106725	8223	#define ETH_DMASR_FBES 0x00002000U /* Fatal bus error status */
Kojto	122:f9eeca106725	8224	#define ETH_DMASR_ETS 0x00000400U /* Early transmit status */
Kojto	122:f9eeca106725	8225	#define ETH_DMASR_RWTS 0x00000200U /* Receive watchdog timeout status */
Kojto	122:f9eeca106725	8226	#define ETH_DMASR_RPSS 0x00000100U /* Receive process stopped status */
Kojto	122:f9eeca106725	8227	#define ETH_DMASR_RBUS 0x00000080U /* Receive buffer unavailable status */
Kojto	122:f9eeca106725	8228	#define ETH_DMASR_RS 0x00000040U /* Receive status */
Kojto	122:f9eeca106725	8229	#define ETH_DMASR_TUS 0x00000020U /* Transmit underflow status */
Kojto	122:f9eeca106725	8230	#define ETH_DMASR_ROS 0x00000010U /* Receive overflow status */
Kojto	122:f9eeca106725	8231	#define ETH_DMASR_TJTS 0x00000008U /* Transmit jabber timeout status */
Kojto	122:f9eeca106725	8232	#define ETH_DMASR_TBUS 0x00000004U /* Transmit buffer unavailable status */
Kojto	122:f9eeca106725	8233	#define ETH_DMASR_TPSS 0x00000002U /* Transmit process stopped status */
Kojto	122:f9eeca106725	8234	#define ETH_DMASR_TS 0x00000001U /* Transmit status */
Kojto	107:4f6c30876dfa	8235
Kojto	107:4f6c30876dfa	8236	/* Bit definition for Ethernet DMA Operation Mode Register */
Kojto	122:f9eeca106725	8237	#define ETH_DMAOMR_DTCEFD 0x04000000U /* Disable Dropping of TCP/IP checksum error frames */
Kojto	122:f9eeca106725	8238	#define ETH_DMAOMR_RSF 0x02000000U /* Receive store and forward */
Kojto	122:f9eeca106725	8239	#define ETH_DMAOMR_DFRF 0x01000000U /* Disable flushing of received frames */
Kojto	122:f9eeca106725	8240	#define ETH_DMAOMR_TSF 0x00200000U /* Transmit store and forward */
Kojto	122:f9eeca106725	8241	#define ETH_DMAOMR_FTF 0x00100000U /* Flush transmit FIFO */
Kojto	122:f9eeca106725	8242	#define ETH_DMAOMR_TTC 0x0001C000U /* Transmit threshold control */
Kojto	122:f9eeca106725	8243	#define ETH_DMAOMR_TTC_64Bytes 0x00000000U /* threshold level of the MTL Transmit FIFO is 64 Bytes */
Kojto	122:f9eeca106725	8244	#define ETH_DMAOMR_TTC_128Bytes 0x00004000U /* threshold level of the MTL Transmit FIFO is 128 Bytes */
Kojto	122:f9eeca106725	8245	#define ETH_DMAOMR_TTC_192Bytes 0x00008000U /* threshold level of the MTL Transmit FIFO is 192 Bytes */
Kojto	122:f9eeca106725	8246	#define ETH_DMAOMR_TTC_256Bytes 0x0000C000U /* threshold level of the MTL Transmit FIFO is 256 Bytes */
Kojto	122:f9eeca106725	8247	#define ETH_DMAOMR_TTC_40Bytes 0x00010000U /* threshold level of the MTL Transmit FIFO is 40 Bytes */
Kojto	122:f9eeca106725	8248	#define ETH_DMAOMR_TTC_32Bytes 0x00014000U /* threshold level of the MTL Transmit FIFO is 32 Bytes */
Kojto	122:f9eeca106725	8249	#define ETH_DMAOMR_TTC_24Bytes 0x00018000U /* threshold level of the MTL Transmit FIFO is 24 Bytes */
Kojto	122:f9eeca106725	8250	#define ETH_DMAOMR_TTC_16Bytes 0x0001C000U /* threshold level of the MTL Transmit FIFO is 16 Bytes */
Kojto	122:f9eeca106725	8251	#define ETH_DMAOMR_ST 0x00002000U /* Start/stop transmission command */
Kojto	122:f9eeca106725	8252	#define ETH_DMAOMR_FEF 0x00000080U /* Forward error frames */
Kojto	122:f9eeca106725	8253	#define ETH_DMAOMR_FUGF 0x00000040U /* Forward undersized good frames */
Kojto	122:f9eeca106725	8254	#define ETH_DMAOMR_RTC 0x00000018U /* receive threshold control */
Kojto	122:f9eeca106725	8255	#define ETH_DMAOMR_RTC_64Bytes 0x00000000U /* threshold level of the MTL Receive FIFO is 64 Bytes */
Kojto	122:f9eeca106725	8256	#define ETH_DMAOMR_RTC_32Bytes 0x00000008U /* threshold level of the MTL Receive FIFO is 32 Bytes */
Kojto	122:f9eeca106725	8257	#define ETH_DMAOMR_RTC_96Bytes 0x00000010U /* threshold level of the MTL Receive FIFO is 96 Bytes */
Kojto	122:f9eeca106725	8258	#define ETH_DMAOMR_RTC_128Bytes 0x00000018U /* threshold level of the MTL Receive FIFO is 128 Bytes */
Kojto	122:f9eeca106725	8259	#define ETH_DMAOMR_OSF 0x00000004U /* operate on second frame */
Kojto	122:f9eeca106725	8260	#define ETH_DMAOMR_SR 0x00000002U /* Start/stop receive */
Kojto	107:4f6c30876dfa	8261
Kojto	107:4f6c30876dfa	8262	/* Bit definition for Ethernet DMA Interrupt Enable Register */
Kojto	122:f9eeca106725	8263	#define ETH_DMAIER_NISE 0x00010000U /* Normal interrupt summary enable */
Kojto	122:f9eeca106725	8264	#define ETH_DMAIER_AISE 0x00008000U /* Abnormal interrupt summary enable */
Kojto	122:f9eeca106725	8265	#define ETH_DMAIER_ERIE 0x00004000U /* Early receive interrupt enable */
Kojto	122:f9eeca106725	8266	#define ETH_DMAIER_FBEIE 0x00002000U /* Fatal bus error interrupt enable */
Kojto	122:f9eeca106725	8267	#define ETH_DMAIER_ETIE 0x00000400U /* Early transmit interrupt enable */
Kojto	122:f9eeca106725	8268	#define ETH_DMAIER_RWTIE 0x00000200U /* Receive watchdog timeout interrupt enable */
Kojto	122:f9eeca106725	8269	#define ETH_DMAIER_RPSIE 0x00000100U /* Receive process stopped interrupt enable */
Kojto	122:f9eeca106725	8270	#define ETH_DMAIER_RBUIE 0x00000080U /* Receive buffer unavailable interrupt enable */
Kojto	122:f9eeca106725	8271	#define ETH_DMAIER_RIE 0x00000040U /* Receive interrupt enable */
Kojto	122:f9eeca106725	8272	#define ETH_DMAIER_TUIE 0x00000020U /* Transmit Underflow interrupt enable */
Kojto	122:f9eeca106725	8273	#define ETH_DMAIER_ROIE 0x00000010U /* Receive Overflow interrupt enable */
Kojto	122:f9eeca106725	8274	#define ETH_DMAIER_TJTIE 0x00000008U /* Transmit jabber timeout interrupt enable */
Kojto	122:f9eeca106725	8275	#define ETH_DMAIER_TBUIE 0x00000004U /* Transmit buffer unavailable interrupt enable */
Kojto	122:f9eeca106725	8276	#define ETH_DMAIER_TPSIE 0x00000002U /* Transmit process stopped interrupt enable */
Kojto	122:f9eeca106725	8277	#define ETH_DMAIER_TIE 0x00000001U /* Transmit interrupt enable */
Kojto	107:4f6c30876dfa	8278
Kojto	107:4f6c30876dfa	8279	/* Bit definition for Ethernet DMA Missed Frame and Buffer Overflow Counter Register */
Kojto	122:f9eeca106725	8280	#define ETH_DMAMFBOCR_OFOC 0x10000000U /* Overflow bit for FIFO overflow counter */
Kojto	122:f9eeca106725	8281	#define ETH_DMAMFBOCR_MFA 0x0FFE0000U /* Number of frames missed by the application */
Kojto	122:f9eeca106725	8282	#define ETH_DMAMFBOCR_OMFC 0x00010000U /* Overflow bit for missed frame counter */
Kojto	122:f9eeca106725	8283	#define ETH_DMAMFBOCR_MFC 0x0000FFFFU /* Number of frames missed by the controller */
Kojto	107:4f6c30876dfa	8284
Kojto	107:4f6c30876dfa	8285	/* Bit definition for Ethernet DMA Current Host Transmit Descriptor Register */
Kojto	122:f9eeca106725	8286	#define ETH_DMACHTDR_HTDAP 0xFFFFFFFFU /* Host transmit descriptor address pointer */
Kojto	107:4f6c30876dfa	8287
Kojto	107:4f6c30876dfa	8288	/* Bit definition for Ethernet DMA Current Host Receive Descriptor Register */
Kojto	122:f9eeca106725	8289	#define ETH_DMACHRDR_HRDAP 0xFFFFFFFFU /* Host receive descriptor address pointer */
Kojto	107:4f6c30876dfa	8290
Kojto	107:4f6c30876dfa	8291	/* Bit definition for Ethernet DMA Current Host Transmit Buffer Address Register */
Kojto	122:f9eeca106725	8292	#define ETH_DMACHTBAR_HTBAP 0xFFFFFFFFU /* Host transmit buffer address pointer */
Kojto	107:4f6c30876dfa	8293
Kojto	107:4f6c30876dfa	8294	/* Bit definition for Ethernet DMA Current Host Receive Buffer Address Register */
Kojto	122:f9eeca106725	8295	#define ETH_DMACHRBAR_HRBAP 0xFFFFFFFFU /* Host receive buffer address pointer */
Kojto	107:4f6c30876dfa	8296
Kojto	107:4f6c30876dfa	8297	/******************************************************************************/
Kojto	107:4f6c30876dfa	8298	/* */
Kojto	107:4f6c30876dfa	8299	/* USB_OTG */
Kojto	107:4f6c30876dfa	8300	/* */
Kojto	107:4f6c30876dfa	8301	/******************************************************************************/
Kojto	107:4f6c30876dfa	8302	/****************** Bit definition for USB_OTG_GOTGCTL register ******************/
Kojto	122:f9eeca106725	8303	#define USB_OTG_GOTGCTL_SRQSCS 0x00000001U /!< Session request success /
Kojto	122:f9eeca106725	8304	#define USB_OTG_GOTGCTL_SRQ 0x00000002U /!< Session request /
Kojto	122:f9eeca106725	8305	#define USB_OTG_GOTGCTL_VBVALOEN 0x00000004U /!< VBUS valid override enable /
Kojto	122:f9eeca106725	8306	#define USB_OTG_GOTGCTL_VBVALOVAL 0x00000008U /!< VBUS valid override value /
Kojto	122:f9eeca106725	8307	#define USB_OTG_GOTGCTL_AVALOEN 0x00000010U /!< A-peripheral session valid override enable /
Kojto	122:f9eeca106725	8308	#define USB_OTG_GOTGCTL_AVALOVAL 0x00000020U /!< A-peripheral session valid override value /
Kojto	122:f9eeca106725	8309	#define USB_OTG_GOTGCTL_BVALOEN 0x00000040U /!< B-peripheral session valid override enable /
Kojto	122:f9eeca106725	8310	#define USB_OTG_GOTGCTL_BVALOVAL 0x00000080U /!< B-peripheral session valid override value /
Kojto	122:f9eeca106725	8311	#define USB_OTG_GOTGCTL_HNGSCS 0x00000100U /!< Host set HNP enable /
Kojto	122:f9eeca106725	8312	#define USB_OTG_GOTGCTL_HNPRQ 0x00000200U /!< HNP request /
Kojto	122:f9eeca106725	8313	#define USB_OTG_GOTGCTL_HSHNPEN 0x00000400U /!< Host set HNP enable /
Kojto	122:f9eeca106725	8314	#define USB_OTG_GOTGCTL_DHNPEN 0x00000800U /!< Device HNP enabled /
Kojto	122:f9eeca106725	8315	#define USB_OTG_GOTGCTL_EHEN 0x00001000U /!< Embedded host enable /
Kojto	122:f9eeca106725	8316	#define USB_OTG_GOTGCTL_CIDSTS 0x00010000U /!< Connector ID status /
Kojto	122:f9eeca106725	8317	#define USB_OTG_GOTGCTL_DBCT 0x00020000U /!< Long/short debounce time /
Kojto	122:f9eeca106725	8318	#define USB_OTG_GOTGCTL_ASVLD 0x00040000U /!< A-session valid /
Kojto	122:f9eeca106725	8319	#define USB_OTG_GOTGCTL_BSESVLD 0x00080000U /!< B-session valid /
Kojto	122:f9eeca106725	8320	#define USB_OTG_GOTGCTL_OTGVER 0x00100000U /!< OTG version /
Kojto	107:4f6c30876dfa	8321
Kojto	107:4f6c30876dfa	8322	/****************** Bit definition for USB_OTG_HCFG register ******************/
Kojto	122:f9eeca106725	8323	#define USB_OTG_HCFG_FSLSPCS 0x00000003U /!< FS/LS PHY clock select /
Kojto	122:f9eeca106725	8324	#define USB_OTG_HCFG_FSLSPCS_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8325	#define USB_OTG_HCFG_FSLSPCS_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8326	#define USB_OTG_HCFG_FSLSS 0x00000004U /!< FS- and LS-only support /
Kojto	107:4f6c30876dfa	8327
Kojto	107:4f6c30876dfa	8328	/****************** Bit definition for USB_OTG_DCFG register ******************/
Kojto	122:f9eeca106725	8329	#define USB_OTG_DCFG_DSPD 0x00000003U /!< Device speed /
Kojto	122:f9eeca106725	8330	#define USB_OTG_DCFG_DSPD_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8331	#define USB_OTG_DCFG_DSPD_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8332	#define USB_OTG_DCFG_NZLSOHSK 0x00000004U /!< Nonzero-length status OUT handshake /
Kojto	122:f9eeca106725	8333
Kojto	122:f9eeca106725	8334	#define USB_OTG_DCFG_DAD 0x000007F0U /!< Device address /
Kojto	122:f9eeca106725	8335	#define USB_OTG_DCFG_DAD_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	8336	#define USB_OTG_DCFG_DAD_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	8337	#define USB_OTG_DCFG_DAD_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	8338	#define USB_OTG_DCFG_DAD_3 0x00000080U /!<Bit 3 /
Kojto	122:f9eeca106725	8339	#define USB_OTG_DCFG_DAD_4 0x00000100U /!<Bit 4 /
Kojto	122:f9eeca106725	8340	#define USB_OTG_DCFG_DAD_5 0x00000200U /!<Bit 5 /
Kojto	122:f9eeca106725	8341	#define USB_OTG_DCFG_DAD_6 0x00000400U /!<Bit 6 /
Kojto	122:f9eeca106725	8342
Kojto	122:f9eeca106725	8343	#define USB_OTG_DCFG_PFIVL 0x00001800U /!< Periodic (micro)frame interval /
Kojto	122:f9eeca106725	8344	#define USB_OTG_DCFG_PFIVL_0 0x00000800U /!<Bit 0 /
Kojto	122:f9eeca106725	8345	#define USB_OTG_DCFG_PFIVL_1 0x00001000U /!<Bit 1 /
Kojto	122:f9eeca106725	8346
Kojto	122:f9eeca106725	8347	#define USB_OTG_DCFG_PERSCHIVL 0x03000000U /!< Periodic scheduling interval /
Kojto	122:f9eeca106725	8348	#define USB_OTG_DCFG_PERSCHIVL_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	8349	#define USB_OTG_DCFG_PERSCHIVL_1 0x02000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	8350
Kojto	107:4f6c30876dfa	8351	/****************** Bit definition for USB_OTG_PCGCR register ******************/
Kojto	122:f9eeca106725	8352	#define USB_OTG_PCGCR_STPPCLK 0x00000001U /!< Stop PHY clock /
Kojto	122:f9eeca106725	8353	#define USB_OTG_PCGCR_GATEHCLK 0x00000002U /!< Gate HCLK /
Kojto	122:f9eeca106725	8354	#define USB_OTG_PCGCR_PHYSUSP 0x00000010U /!< PHY suspended /
Kojto	107:4f6c30876dfa	8355
Kojto	107:4f6c30876dfa	8356	/****************** Bit definition for USB_OTG_GOTGINT register ******************/
Kojto	122:f9eeca106725	8357	#define USB_OTG_GOTGINT_SEDET 0x00000004U /!< Session end detected /
Kojto	122:f9eeca106725	8358	#define USB_OTG_GOTGINT_SRSSCHG 0x00000100U /!< Session request success status change /
Kojto	122:f9eeca106725	8359	#define USB_OTG_GOTGINT_HNSSCHG 0x00000200U /!< Host negotiation success status change /
Kojto	122:f9eeca106725	8360	#define USB_OTG_GOTGINT_HNGDET 0x00020000U /!< Host negotiation detected /
Kojto	122:f9eeca106725	8361	#define USB_OTG_GOTGINT_ADTOCHG 0x00040000U /!< A-device timeout change /
Kojto	122:f9eeca106725	8362	#define USB_OTG_GOTGINT_DBCDNE 0x00080000U /!< Debounce done /
Kojto	122:f9eeca106725	8363	#define USB_OTG_GOTGINT_IDCHNG 0x00100000U /!< Change in ID pin input value /
Kojto	107:4f6c30876dfa	8364
Kojto	107:4f6c30876dfa	8365	/****************** Bit definition for USB_OTG_DCTL register ******************/
Kojto	122:f9eeca106725	8366	#define USB_OTG_DCTL_RWUSIG 0x00000001U /!< Remote wakeup signaling /
Kojto	122:f9eeca106725	8367	#define USB_OTG_DCTL_SDIS 0x00000002U /!< Soft disconnect /
Kojto	122:f9eeca106725	8368	#define USB_OTG_DCTL_GINSTS 0x00000004U /!< Global IN NAK status /
Kojto	122:f9eeca106725	8369	#define USB_OTG_DCTL_GONSTS 0x00000008U /!< Global OUT NAK status /
Kojto	122:f9eeca106725	8370
Kojto	122:f9eeca106725	8371	#define USB_OTG_DCTL_TCTL 0x00000070U /!< Test control /
Kojto	122:f9eeca106725	8372	#define USB_OTG_DCTL_TCTL_0 0x00000010U /!<Bit 0 /
Kojto	122:f9eeca106725	8373	#define USB_OTG_DCTL_TCTL_1 0x00000020U /!<Bit 1 /
Kojto	122:f9eeca106725	8374	#define USB_OTG_DCTL_TCTL_2 0x00000040U /!<Bit 2 /
Kojto	122:f9eeca106725	8375	#define USB_OTG_DCTL_SGINAK 0x00000080U /!< Set global IN NAK /
Kojto	122:f9eeca106725	8376	#define USB_OTG_DCTL_CGINAK 0x00000100U /!< Clear global IN NAK /
Kojto	122:f9eeca106725	8377	#define USB_OTG_DCTL_SGONAK 0x00000200U /!< Set global OUT NAK /
Kojto	122:f9eeca106725	8378	#define USB_OTG_DCTL_CGONAK 0x00000400U /!< Clear global OUT NAK /
Kojto	122:f9eeca106725	8379	#define USB_OTG_DCTL_POPRGDNE 0x00000800U /!< Power-on programming done /
Kojto	107:4f6c30876dfa	8380
Kojto	107:4f6c30876dfa	8381	/****************** Bit definition for USB_OTG_HFIR register ******************/
Kojto	122:f9eeca106725	8382	#define USB_OTG_HFIR_FRIVL 0x0000FFFFU /!< Frame interval /
Kojto	107:4f6c30876dfa	8383
Kojto	107:4f6c30876dfa	8384	/****************** Bit definition for USB_OTG_HFNUM register ******************/
Kojto	122:f9eeca106725	8385	#define USB_OTG_HFNUM_FRNUM 0x0000FFFFU /!< Frame number /
Kojto	122:f9eeca106725	8386	#define USB_OTG_HFNUM_FTREM 0xFFFF0000U /!< Frame time remaining /
Kojto	107:4f6c30876dfa	8387
Kojto	107:4f6c30876dfa	8388	/****************** Bit definition for USB_OTG_DSTS register ******************/
Kojto	122:f9eeca106725	8389	#define USB_OTG_DSTS_SUSPSTS 0x00000001U /!< Suspend status /
Kojto	122:f9eeca106725	8390
Kojto	122:f9eeca106725	8391	#define USB_OTG_DSTS_ENUMSPD 0x00000006U /!< Enumerated speed /
Kojto	122:f9eeca106725	8392	#define USB_OTG_DSTS_ENUMSPD_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	8393	#define USB_OTG_DSTS_ENUMSPD_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	8394	#define USB_OTG_DSTS_EERR 0x00000008U /!< Erratic error /
Kojto	122:f9eeca106725	8395	#define USB_OTG_DSTS_FNSOF 0x003FFF00U /!< Frame number of the received SOF /
Kojto	107:4f6c30876dfa	8396
Kojto	107:4f6c30876dfa	8397	/****************** Bit definition for USB_OTG_GAHBCFG register ******************/
Kojto	122:f9eeca106725	8398	#define USB_OTG_GAHBCFG_GINT 0x00000001U /!< Global interrupt mask /
Kojto	122:f9eeca106725	8399	#define USB_OTG_GAHBCFG_HBSTLEN 0x0000001EU /!< Burst length/type /
Kojto	122:f9eeca106725	8400	#define USB_OTG_GAHBCFG_HBSTLEN_0 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	8401	#define USB_OTG_GAHBCFG_HBSTLEN_1 0x00000004U /!<Bit 1 /
Kojto	122:f9eeca106725	8402	#define USB_OTG_GAHBCFG_HBSTLEN_2 0x00000008U /!<Bit 2 /
Kojto	122:f9eeca106725	8403	#define USB_OTG_GAHBCFG_HBSTLEN_3 0x00000010U /!<Bit 3 /
Kojto	122:f9eeca106725	8404	#define USB_OTG_GAHBCFG_DMAEN 0x00000020U /!< DMA enable /
Kojto	122:f9eeca106725	8405	#define USB_OTG_GAHBCFG_TXFELVL 0x00000080U /!< TxFIFO empty level /
Kojto	122:f9eeca106725	8406	#define USB_OTG_GAHBCFG_PTXFELVL 0x00000100U /!< Periodic TxFIFO empty level /
Kojto	107:4f6c30876dfa	8407
Kojto	107:4f6c30876dfa	8408	/****************** Bit definition for USB_OTG_GUSBCFG register ******************/
Kojto	122:f9eeca106725	8409	#define USB_OTG_GUSBCFG_TOCAL 0x00000007U /!< FS timeout calibration /
Kojto	122:f9eeca106725	8410	#define USB_OTG_GUSBCFG_TOCAL_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8411	#define USB_OTG_GUSBCFG_TOCAL_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8412	#define USB_OTG_GUSBCFG_TOCAL_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	8413	#define USB_OTG_GUSBCFG_PHYSEL 0x00000040U /!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select /
Kojto	122:f9eeca106725	8414	#define USB_OTG_GUSBCFG_SRPCAP 0x00000100U /!< SRP-capable /
Kojto	122:f9eeca106725	8415	#define USB_OTG_GUSBCFG_HNPCAP 0x00000200U /!< HNP-capable /
Kojto	122:f9eeca106725	8416	#define USB_OTG_GUSBCFG_TRDT 0x00003C00U /!< USB turnaround time /
Kojto	122:f9eeca106725	8417	#define USB_OTG_GUSBCFG_TRDT_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	8418	#define USB_OTG_GUSBCFG_TRDT_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	8419	#define USB_OTG_GUSBCFG_TRDT_2 0x00001000U /!<Bit 2 /
Kojto	122:f9eeca106725	8420	#define USB_OTG_GUSBCFG_TRDT_3 0x00002000U /!<Bit 3 /
Kojto	122:f9eeca106725	8421	#define USB_OTG_GUSBCFG_PHYLPCS 0x00008000U /!< PHY Low-power clock select /
Kojto	122:f9eeca106725	8422	#define USB_OTG_GUSBCFG_ULPIFSLS 0x00020000U /!< ULPI FS/LS select /
Kojto	122:f9eeca106725	8423	#define USB_OTG_GUSBCFG_ULPIAR 0x00040000U /!< ULPI Auto-resume /
Kojto	122:f9eeca106725	8424	#define USB_OTG_GUSBCFG_ULPICSM 0x00080000U /!< ULPI Clock SuspendM /
Kojto	122:f9eeca106725	8425	#define USB_OTG_GUSBCFG_ULPIEVBUSD 0x00100000U /!< ULPI External VBUS Drive /
Kojto	122:f9eeca106725	8426	#define USB_OTG_GUSBCFG_ULPIEVBUSI 0x00200000U /!< ULPI external VBUS indicator /
Kojto	122:f9eeca106725	8427	#define USB_OTG_GUSBCFG_TSDPS 0x00400000U /!< TermSel DLine pulsing selection /
Kojto	122:f9eeca106725	8428	#define USB_OTG_GUSBCFG_PCCI 0x00800000U /!< Indicator complement /
Kojto	122:f9eeca106725	8429	#define USB_OTG_GUSBCFG_PTCI 0x01000000U /!< Indicator pass through /
Kojto	122:f9eeca106725	8430	#define USB_OTG_GUSBCFG_ULPIIPD 0x02000000U /!< ULPI interface protect disable /
Kojto	122:f9eeca106725	8431	#define USB_OTG_GUSBCFG_FHMOD 0x20000000U /!< Forced host mode /
Kojto	122:f9eeca106725	8432	#define USB_OTG_GUSBCFG_FDMOD 0x40000000U /!< Forced peripheral mode /
Kojto	122:f9eeca106725	8433	#define USB_OTG_GUSBCFG_CTXPKT 0x80000000U /!< Corrupt Tx packet /
Kojto	107:4f6c30876dfa	8434
Kojto	107:4f6c30876dfa	8435	/****************** Bit definition for USB_OTG_GRSTCTL register ******************/
Kojto	122:f9eeca106725	8436	#define USB_OTG_GRSTCTL_CSRST 0x00000001U /!< Core soft reset /
Kojto	122:f9eeca106725	8437	#define USB_OTG_GRSTCTL_HSRST 0x00000002U /!< HCLK soft reset /
Kojto	122:f9eeca106725	8438	#define USB_OTG_GRSTCTL_FCRST 0x00000004U /!< Host frame counter reset /
Kojto	122:f9eeca106725	8439	#define USB_OTG_GRSTCTL_RXFFLSH 0x00000010U /!< RxFIFO flush /
Kojto	122:f9eeca106725	8440	#define USB_OTG_GRSTCTL_TXFFLSH 0x00000020U /!< TxFIFO flush /
Kojto	122:f9eeca106725	8441	#define USB_OTG_GRSTCTL_TXFNUM 0x000007C0U /!< TxFIFO number /
Kojto	122:f9eeca106725	8442	#define USB_OTG_GRSTCTL_TXFNUM_0 0x00000040U /!<Bit 0 /
Kojto	122:f9eeca106725	8443	#define USB_OTG_GRSTCTL_TXFNUM_1 0x00000080U /!<Bit 1 /
Kojto	122:f9eeca106725	8444	#define USB_OTG_GRSTCTL_TXFNUM_2 0x00000100U /!<Bit 2 /
Kojto	122:f9eeca106725	8445	#define USB_OTG_GRSTCTL_TXFNUM_3 0x00000200U /!<Bit 3 /
Kojto	122:f9eeca106725	8446	#define USB_OTG_GRSTCTL_TXFNUM_4 0x00000400U /!<Bit 4 /
Kojto	122:f9eeca106725	8447	#define USB_OTG_GRSTCTL_DMAREQ 0x40000000U /!< DMA request signal /
Kojto	122:f9eeca106725	8448	#define USB_OTG_GRSTCTL_AHBIDL 0x80000000U /!< AHB master idle /
Kojto	107:4f6c30876dfa	8449
Kojto	107:4f6c30876dfa	8450	/****************** Bit definition for USB_OTG_DIEPMSK register ******************/
Kojto	122:f9eeca106725	8451	#define USB_OTG_DIEPMSK_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	8452	#define USB_OTG_DIEPMSK_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	8453	#define USB_OTG_DIEPMSK_TOM 0x00000008U /!< Timeout condition mask (nonisochronous endpoints) /
Kojto	122:f9eeca106725	8454	#define USB_OTG_DIEPMSK_ITTXFEMSK 0x00000010U /!< IN token received when TxFIFO empty mask /
Kojto	122:f9eeca106725	8455	#define USB_OTG_DIEPMSK_INEPNMM 0x00000020U /!< IN token received with EP mismatch mask /
Kojto	122:f9eeca106725	8456	#define USB_OTG_DIEPMSK_INEPNEM 0x00000040U /!< IN endpoint NAK effective mask /
Kojto	122:f9eeca106725	8457	#define USB_OTG_DIEPMSK_TXFURM 0x00000100U /!< FIFO underrun mask /
Kojto	122:f9eeca106725	8458	#define USB_OTG_DIEPMSK_BIM 0x00000200U /!< BNA interrupt mask /
Kojto	107:4f6c30876dfa	8459
Kojto	107:4f6c30876dfa	8460	/****************** Bit definition for USB_OTG_HPTXSTS register ******************/
Kojto	122:f9eeca106725	8461	#define USB_OTG_HPTXSTS_PTXFSAVL 0x0000FFFFU /!< Periodic transmit data FIFO space available /
Kojto	122:f9eeca106725	8462	#define USB_OTG_HPTXSTS_PTXQSAV 0x00FF0000U /!< Periodic transmit request queue space available /
Kojto	122:f9eeca106725	8463	#define USB_OTG_HPTXSTS_PTXQSAV_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	8464	#define USB_OTG_HPTXSTS_PTXQSAV_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	8465	#define USB_OTG_HPTXSTS_PTXQSAV_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	8466	#define USB_OTG_HPTXSTS_PTXQSAV_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	8467	#define USB_OTG_HPTXSTS_PTXQSAV_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	8468	#define USB_OTG_HPTXSTS_PTXQSAV_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	8469	#define USB_OTG_HPTXSTS_PTXQSAV_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	8470	#define USB_OTG_HPTXSTS_PTXQSAV_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	8471
Kojto	122:f9eeca106725	8472	#define USB_OTG_HPTXSTS_PTXQTOP 0xFF000000U /!< Top of the periodic transmit request queue /
Kojto	122:f9eeca106725	8473	#define USB_OTG_HPTXSTS_PTXQTOP_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	8474	#define USB_OTG_HPTXSTS_PTXQTOP_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	8475	#define USB_OTG_HPTXSTS_PTXQTOP_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	8476	#define USB_OTG_HPTXSTS_PTXQTOP_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	8477	#define USB_OTG_HPTXSTS_PTXQTOP_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	8478	#define USB_OTG_HPTXSTS_PTXQTOP_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	8479	#define USB_OTG_HPTXSTS_PTXQTOP_6 0x40000000U /!<Bit 6 /
Kojto	122:f9eeca106725	8480	#define USB_OTG_HPTXSTS_PTXQTOP_7 0x80000000U /!<Bit 7 /
Kojto	107:4f6c30876dfa	8481
Kojto	107:4f6c30876dfa	8482	/****************** Bit definition for USB_OTG_HAINT register ******************/
Kojto	122:f9eeca106725	8483	#define USB_OTG_HAINT_HAINT 0x0000FFFFU /!< Channel interrupts /
Kojto	107:4f6c30876dfa	8484
Kojto	107:4f6c30876dfa	8485	/****************** Bit definition for USB_OTG_DOEPMSK register ******************/
Kojto	122:f9eeca106725	8486	#define USB_OTG_DOEPMSK_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	8487	#define USB_OTG_DOEPMSK_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	8488	#define USB_OTG_DOEPMSK_STUPM 0x00000008U /!< SETUP phase done mask /
Kojto	122:f9eeca106725	8489	#define USB_OTG_DOEPMSK_OTEPDM 0x00000010U /!< OUT token received when endpoint disabled mask /
Kojto	122:f9eeca106725	8490	#define USB_OTG_DOEPMSK_OTEPSPRM 0x00000020U /!< Status Phase Received mask /
Kojto	122:f9eeca106725	8491	#define USB_OTG_DOEPMSK_B2BSTUP 0x00000040U /!< Back-to-back SETUP packets received mask /
Kojto	122:f9eeca106725	8492	#define USB_OTG_DOEPMSK_OPEM 0x00000100U /!< OUT packet error mask /
Kojto	122:f9eeca106725	8493	#define USB_OTG_DOEPMSK_BOIM 0x00000200U /!< BNA interrupt mask /
Kojto	107:4f6c30876dfa	8494
Kojto	107:4f6c30876dfa	8495	/****************** Bit definition for USB_OTG_GINTSTS register ******************/
Kojto	122:f9eeca106725	8496	#define USB_OTG_GINTSTS_CMOD 0x00000001U /!< Current mode of operation /
Kojto	122:f9eeca106725	8497	#define USB_OTG_GINTSTS_MMIS 0x00000002U /!< Mode mismatch interrupt /
Kojto	122:f9eeca106725	8498	#define USB_OTG_GINTSTS_OTGINT 0x00000004U /!< OTG interrupt /
Kojto	122:f9eeca106725	8499	#define USB_OTG_GINTSTS_SOF 0x00000008U /!< Start of frame /
Kojto	122:f9eeca106725	8500	#define USB_OTG_GINTSTS_RXFLVL 0x00000010U /!< RxFIFO nonempty /
Kojto	122:f9eeca106725	8501	#define USB_OTG_GINTSTS_NPTXFE 0x00000020U /!< Nonperiodic TxFIFO empty /
Kojto	122:f9eeca106725	8502	#define USB_OTG_GINTSTS_GINAKEFF 0x00000040U /!< Global IN nonperiodic NAK effective /
Kojto	122:f9eeca106725	8503	#define USB_OTG_GINTSTS_BOUTNAKEFF 0x00000080U /!< Global OUT NAK effective /
Kojto	122:f9eeca106725	8504	#define USB_OTG_GINTSTS_ESUSP 0x00000400U /!< Early suspend /
Kojto	122:f9eeca106725	8505	#define USB_OTG_GINTSTS_USBSUSP 0x00000800U /!< USB suspend /
Kojto	122:f9eeca106725	8506	#define USB_OTG_GINTSTS_USBRST 0x00001000U /!< USB reset /
Kojto	122:f9eeca106725	8507	#define USB_OTG_GINTSTS_ENUMDNE 0x00002000U /!< Enumeration done /
Kojto	122:f9eeca106725	8508	#define USB_OTG_GINTSTS_ISOODRP 0x00004000U /!< Isochronous OUT packet dropped interrupt /
Kojto	122:f9eeca106725	8509	#define USB_OTG_GINTSTS_EOPF 0x00008000U /!< End of periodic frame interrupt /
Kojto	122:f9eeca106725	8510	#define USB_OTG_GINTSTS_IEPINT 0x00040000U /!< IN endpoint interrupt /
Kojto	122:f9eeca106725	8511	#define USB_OTG_GINTSTS_OEPINT 0x00080000U /!< OUT endpoint interrupt /
Kojto	122:f9eeca106725	8512	#define USB_OTG_GINTSTS_IISOIXFR 0x00100000U /!< Incomplete isochronous IN transfer /
Kojto	122:f9eeca106725	8513	#define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT 0x00200000U /!< Incomplete periodic transfer /
Kojto	122:f9eeca106725	8514	#define USB_OTG_GINTSTS_DATAFSUSP 0x00400000U /!< Data fetch suspended /
Kojto	122:f9eeca106725	8515	#define USB_OTG_GINTSTS_RSTDET 0x00800000U /!< Reset detected interrupt /
Kojto	122:f9eeca106725	8516	#define USB_OTG_GINTSTS_HPRTINT 0x01000000U /!< Host port interrupt /
Kojto	122:f9eeca106725	8517	#define USB_OTG_GINTSTS_HCINT 0x02000000U /!< Host channels interrupt /
Kojto	122:f9eeca106725	8518	#define USB_OTG_GINTSTS_PTXFE 0x04000000U /!< Periodic TxFIFO empty /
Kojto	122:f9eeca106725	8519	#define USB_OTG_GINTSTS_LPMINT 0x08000000U /!< LPM interrupt /
Kojto	122:f9eeca106725	8520	#define USB_OTG_GINTSTS_CIDSCHG 0x10000000U /!< Connector ID status change /
Kojto	122:f9eeca106725	8521	#define USB_OTG_GINTSTS_DISCINT 0x20000000U /!< Disconnect detected interrupt /
Kojto	122:f9eeca106725	8522	#define USB_OTG_GINTSTS_SRQINT 0x40000000U /!< Session request/new session detected interrupt /
Kojto	122:f9eeca106725	8523	#define USB_OTG_GINTSTS_WKUINT 0x80000000U /!< Resume/remote wakeup detected interrupt /
Kojto	107:4f6c30876dfa	8524
Kojto	107:4f6c30876dfa	8525	/****************** Bit definition for USB_OTG_GINTMSK register ******************/
Kojto	122:f9eeca106725	8526	#define USB_OTG_GINTMSK_MMISM 0x00000002U /!< Mode mismatch interrupt mask /
Kojto	122:f9eeca106725	8527	#define USB_OTG_GINTMSK_OTGINT 0x00000004U /!< OTG interrupt mask /
Kojto	122:f9eeca106725	8528	#define USB_OTG_GINTMSK_SOFM 0x00000008U /!< Start of frame mask /
Kojto	122:f9eeca106725	8529	#define USB_OTG_GINTMSK_RXFLVLM 0x00000010U /!< Receive FIFO nonempty mask /
Kojto	122:f9eeca106725	8530	#define USB_OTG_GINTMSK_NPTXFEM 0x00000020U /!< Nonperiodic TxFIFO empty mask /
Kojto	122:f9eeca106725	8531	#define USB_OTG_GINTMSK_GINAKEFFM 0x00000040U /!< Global nonperiodic IN NAK effective mask /
Kojto	122:f9eeca106725	8532	#define USB_OTG_GINTMSK_GONAKEFFM 0x00000080U /!< Global OUT NAK effective mask /
Kojto	122:f9eeca106725	8533	#define USB_OTG_GINTMSK_ESUSPM 0x00000400U /!< Early suspend mask /
Kojto	122:f9eeca106725	8534	#define USB_OTG_GINTMSK_USBSUSPM 0x00000800U /!< USB suspend mask /
Kojto	122:f9eeca106725	8535	#define USB_OTG_GINTMSK_USBRST 0x00001000U /!< USB reset mask /
Kojto	122:f9eeca106725	8536	#define USB_OTG_GINTMSK_ENUMDNEM 0x00002000U /!< Enumeration done mask /
Kojto	122:f9eeca106725	8537	#define USB_OTG_GINTMSK_ISOODRPM 0x00004000U /!< Isochronous OUT packet dropped interrupt mask /
Kojto	122:f9eeca106725	8538	#define USB_OTG_GINTMSK_EOPFM 0x00008000U /!< End of periodic frame interrupt mask /
Kojto	122:f9eeca106725	8539	#define USB_OTG_GINTMSK_EPMISM 0x00020000U /!< Endpoint mismatch interrupt mask /
Kojto	122:f9eeca106725	8540	#define USB_OTG_GINTMSK_IEPINT 0x00040000U /!< IN endpoints interrupt mask /
Kojto	122:f9eeca106725	8541	#define USB_OTG_GINTMSK_OEPINT 0x00080000U /!< OUT endpoints interrupt mask /
Kojto	122:f9eeca106725	8542	#define USB_OTG_GINTMSK_IISOIXFRM 0x00100000U /!< Incomplete isochronous IN transfer mask /
Kojto	122:f9eeca106725	8543	#define USB_OTG_GINTMSK_PXFRM_IISOOXFRM 0x00200000U /!< Incomplete periodic transfer mask /
Kojto	122:f9eeca106725	8544	#define USB_OTG_GINTMSK_FSUSPM 0x00400000U /!< Data fetch suspended mask /
Kojto	122:f9eeca106725	8545	#define USB_OTG_GINTMSK_RSTDEM 0x00800000U /!< Reset detected interrupt mask /
Kojto	122:f9eeca106725	8546	#define USB_OTG_GINTMSK_PRTIM 0x01000000U /!< Host port interrupt mask /
Kojto	122:f9eeca106725	8547	#define USB_OTG_GINTMSK_HCIM 0x02000000U /!< Host channels interrupt mask /
Kojto	122:f9eeca106725	8548	#define USB_OTG_GINTMSK_PTXFEM 0x04000000U /!< Periodic TxFIFO empty mask /
Kojto	122:f9eeca106725	8549	#define USB_OTG_GINTMSK_LPMINTM 0x08000000U /!< LPM interrupt Mask /
Kojto	122:f9eeca106725	8550	#define USB_OTG_GINTMSK_CIDSCHGM 0x10000000U /!< Connector ID status change mask /
Kojto	122:f9eeca106725	8551	#define USB_OTG_GINTMSK_DISCINT 0x20000000U /!< Disconnect detected interrupt mask /
Kojto	122:f9eeca106725	8552	#define USB_OTG_GINTMSK_SRQIM 0x40000000U /!< Session request/new session detected interrupt mask /
Kojto	122:f9eeca106725	8553	#define USB_OTG_GINTMSK_WUIM 0x80000000U /!< Resume/remote wakeup detected interrupt mask /
Kojto	107:4f6c30876dfa	8554
Kojto	107:4f6c30876dfa	8555	/****************** Bit definition for USB_OTG_DAINT register ******************/
Kojto	122:f9eeca106725	8556	#define USB_OTG_DAINT_IEPINT 0x0000FFFFU /!< IN endpoint interrupt bits /
Kojto	122:f9eeca106725	8557	#define USB_OTG_DAINT_OEPINT 0xFFFF0000U /!< OUT endpoint interrupt bits /
Kojto	107:4f6c30876dfa	8558
Kojto	107:4f6c30876dfa	8559	/****************** Bit definition for USB_OTG_HAINTMSK register ******************/
Kojto	122:f9eeca106725	8560	#define USB_OTG_HAINTMSK_HAINTM 0x0000FFFFU /!< Channel interrupt mask /
Kojto	107:4f6c30876dfa	8561
Kojto	107:4f6c30876dfa	8562	/****************** Bit definition for USB_OTG_GRXSTSP register ******************/
Kojto	122:f9eeca106725	8563	#define USB_OTG_GRXSTSP_EPNUM 0x0000000FU /!< IN EP interrupt mask bits /
Kojto	122:f9eeca106725	8564	#define USB_OTG_GRXSTSP_BCNT 0x00007FF0U /!< OUT EP interrupt mask bits /
Kojto	122:f9eeca106725	8565	#define USB_OTG_GRXSTSP_DPID 0x00018000U /!< OUT EP interrupt mask bits /
Kojto	122:f9eeca106725	8566	#define USB_OTG_GRXSTSP_PKTSTS 0x001E0000U /!< OUT EP interrupt mask bits /
Kojto	107:4f6c30876dfa	8567
Kojto	107:4f6c30876dfa	8568	/****************** Bit definition for USB_OTG_DAINTMSK register ******************/
Kojto	122:f9eeca106725	8569	#define USB_OTG_DAINTMSK_IEPM 0x0000FFFFU /!< IN EP interrupt mask bits /
Kojto	122:f9eeca106725	8570	#define USB_OTG_DAINTMSK_OEPM 0xFFFF0000U /!< OUT EP interrupt mask bits /
Kojto	107:4f6c30876dfa	8571
Kojto	107:4f6c30876dfa	8572	/****************** Bit definition for OTG register ******************/
Kojto	107:4f6c30876dfa	8573
Kojto	122:f9eeca106725	8574	#define USB_OTG_CHNUM 0x0000000FU /!< Channel number /
Kojto	122:f9eeca106725	8575	#define USB_OTG_CHNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8576	#define USB_OTG_CHNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8577	#define USB_OTG_CHNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	8578	#define USB_OTG_CHNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	8579	#define USB_OTG_BCNT 0x00007FF0U /!< Byte count /
Kojto	122:f9eeca106725	8580
Kojto	122:f9eeca106725	8581	#define USB_OTG_DPID 0x00018000U /!< Data PID /
Kojto	122:f9eeca106725	8582	#define USB_OTG_DPID_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	8583	#define USB_OTG_DPID_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	8584
Kojto	122:f9eeca106725	8585	#define USB_OTG_PKTSTS 0x001E0000U /!< Packet status /
Kojto	122:f9eeca106725	8586	#define USB_OTG_PKTSTS_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	8587	#define USB_OTG_PKTSTS_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	8588	#define USB_OTG_PKTSTS_2 0x00080000U /!<Bit 2 /
Kojto	122:f9eeca106725	8589	#define USB_OTG_PKTSTS_3 0x00100000U /!<Bit 3 /
Kojto	122:f9eeca106725	8590
Kojto	122:f9eeca106725	8591	#define USB_OTG_EPNUM 0x0000000FU /!< Endpoint number /
Kojto	122:f9eeca106725	8592	#define USB_OTG_EPNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8593	#define USB_OTG_EPNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8594	#define USB_OTG_EPNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	8595	#define USB_OTG_EPNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	8596
Kojto	122:f9eeca106725	8597	#define USB_OTG_FRMNUM 0x01E00000U /!< Frame number /
Kojto	122:f9eeca106725	8598	#define USB_OTG_FRMNUM_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	8599	#define USB_OTG_FRMNUM_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	8600	#define USB_OTG_FRMNUM_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	8601	#define USB_OTG_FRMNUM_3 0x01000000U /!<Bit 3 /
Kojto	107:4f6c30876dfa	8602
Kojto	107:4f6c30876dfa	8603	/****************** Bit definition for OTG register ******************/
Kojto	107:4f6c30876dfa	8604
Kojto	122:f9eeca106725	8605	#define USB_OTG_CHNUM 0x0000000FU /!< Channel number /
Kojto	122:f9eeca106725	8606	#define USB_OTG_CHNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8607	#define USB_OTG_CHNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8608	#define USB_OTG_CHNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	8609	#define USB_OTG_CHNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	8610	#define USB_OTG_BCNT 0x00007FF0U /!< Byte count /
Kojto	122:f9eeca106725	8611
Kojto	122:f9eeca106725	8612	#define USB_OTG_DPID 0x00018000U /!< Data PID /
Kojto	122:f9eeca106725	8613	#define USB_OTG_DPID_0 0x00008000U /!<Bit 0 /
Kojto	122:f9eeca106725	8614	#define USB_OTG_DPID_1 0x00010000U /!<Bit 1 /
Kojto	122:f9eeca106725	8615
Kojto	122:f9eeca106725	8616	#define USB_OTG_PKTSTS 0x001E0000U /!< Packet status /
Kojto	122:f9eeca106725	8617	#define USB_OTG_PKTSTS_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	8618	#define USB_OTG_PKTSTS_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	8619	#define USB_OTG_PKTSTS_2 0x00080000U /!<Bit 2 /
Kojto	122:f9eeca106725	8620	#define USB_OTG_PKTSTS_3 0x00100000U /!<Bit 3 /
Kojto	122:f9eeca106725	8621
Kojto	122:f9eeca106725	8622	#define USB_OTG_EPNUM 0x0000000FU /!< Endpoint number /
Kojto	122:f9eeca106725	8623	#define USB_OTG_EPNUM_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8624	#define USB_OTG_EPNUM_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8625	#define USB_OTG_EPNUM_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	8626	#define USB_OTG_EPNUM_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	8627
Kojto	122:f9eeca106725	8628	#define USB_OTG_FRMNUM 0x01E00000U /!< Frame number /
Kojto	122:f9eeca106725	8629	#define USB_OTG_FRMNUM_0 0x00200000U /!<Bit 0 /
Kojto	122:f9eeca106725	8630	#define USB_OTG_FRMNUM_1 0x00400000U /!<Bit 1 /
Kojto	122:f9eeca106725	8631	#define USB_OTG_FRMNUM_2 0x00800000U /!<Bit 2 /
Kojto	122:f9eeca106725	8632	#define USB_OTG_FRMNUM_3 0x01000000U /!<Bit 3 /
Kojto	107:4f6c30876dfa	8633
Kojto	107:4f6c30876dfa	8634	/****************** Bit definition for USB_OTG_GRXFSIZ register ******************/
Kojto	122:f9eeca106725	8635	#define USB_OTG_GRXFSIZ_RXFD 0x0000FFFFU /!< RxFIFO depth /
Kojto	107:4f6c30876dfa	8636
Kojto	107:4f6c30876dfa	8637	/****************** Bit definition for USB_OTG_DVBUSDIS register ******************/
Kojto	122:f9eeca106725	8638	#define USB_OTG_DVBUSDIS_VBUSDT 0x0000FFFFU /!< Device VBUS discharge time /
Kojto	107:4f6c30876dfa	8639
Kojto	107:4f6c30876dfa	8640	/****************** Bit definition for OTG register ******************/
Kojto	122:f9eeca106725	8641	#define USB_OTG_NPTXFSA 0x0000FFFFU /!< Nonperiodic transmit RAM start address /
Kojto	122:f9eeca106725	8642	#define USB_OTG_NPTXFD 0xFFFF0000U /!< Nonperiodic TxFIFO depth /
Kojto	122:f9eeca106725	8643	#define USB_OTG_TX0FSA 0x0000FFFFU /!< Endpoint 0 transmit RAM start address /
Kojto	122:f9eeca106725	8644	#define USB_OTG_TX0FD 0xFFFF0000U /!< Endpoint 0 TxFIFO depth /
Kojto	107:4f6c30876dfa	8645
Kojto	107:4f6c30876dfa	8646	/****************** Bit definition for USB_OTG_DVBUSPULSE register ******************/
Kojto	122:f9eeca106725	8647	#define USB_OTG_DVBUSPULSE_DVBUSP 0x00000FFFU /!< Device VBUS pulsing time /
Kojto	107:4f6c30876dfa	8648
Kojto	107:4f6c30876dfa	8649	/****************** Bit definition for USB_OTG_GNPTXSTS register ******************/
Kojto	122:f9eeca106725	8650	#define USB_OTG_GNPTXSTS_NPTXFSAV 0x0000FFFFU /!< Nonperiodic TxFIFO space available /
Kojto	122:f9eeca106725	8651
Kojto	122:f9eeca106725	8652	#define USB_OTG_GNPTXSTS_NPTQXSAV 0x00FF0000U /!< Nonperiodic transmit request queue space available /
Kojto	122:f9eeca106725	8653	#define USB_OTG_GNPTXSTS_NPTQXSAV_0 0x00010000U /!<Bit 0 /
Kojto	122:f9eeca106725	8654	#define USB_OTG_GNPTXSTS_NPTQXSAV_1 0x00020000U /!<Bit 1 /
Kojto	122:f9eeca106725	8655	#define USB_OTG_GNPTXSTS_NPTQXSAV_2 0x00040000U /!<Bit 2 /
Kojto	122:f9eeca106725	8656	#define USB_OTG_GNPTXSTS_NPTQXSAV_3 0x00080000U /!<Bit 3 /
Kojto	122:f9eeca106725	8657	#define USB_OTG_GNPTXSTS_NPTQXSAV_4 0x00100000U /!<Bit 4 /
Kojto	122:f9eeca106725	8658	#define USB_OTG_GNPTXSTS_NPTQXSAV_5 0x00200000U /!<Bit 5 /
Kojto	122:f9eeca106725	8659	#define USB_OTG_GNPTXSTS_NPTQXSAV_6 0x00400000U /!<Bit 6 /
Kojto	122:f9eeca106725	8660	#define USB_OTG_GNPTXSTS_NPTQXSAV_7 0x00800000U /!<Bit 7 /
Kojto	122:f9eeca106725	8661
Kojto	122:f9eeca106725	8662	#define USB_OTG_GNPTXSTS_NPTXQTOP 0x7F000000U /!< Top of the nonperiodic transmit request queue /
Kojto	122:f9eeca106725	8663	#define USB_OTG_GNPTXSTS_NPTXQTOP_0 0x01000000U /!<Bit 0 /
Kojto	122:f9eeca106725	8664	#define USB_OTG_GNPTXSTS_NPTXQTOP_1 0x02000000U /!<Bit 1 /
Kojto	122:f9eeca106725	8665	#define USB_OTG_GNPTXSTS_NPTXQTOP_2 0x04000000U /!<Bit 2 /
Kojto	122:f9eeca106725	8666	#define USB_OTG_GNPTXSTS_NPTXQTOP_3 0x08000000U /!<Bit 3 /
Kojto	122:f9eeca106725	8667	#define USB_OTG_GNPTXSTS_NPTXQTOP_4 0x10000000U /!<Bit 4 /
Kojto	122:f9eeca106725	8668	#define USB_OTG_GNPTXSTS_NPTXQTOP_5 0x20000000U /!<Bit 5 /
Kojto	122:f9eeca106725	8669	#define USB_OTG_GNPTXSTS_NPTXQTOP_6 0x40000000U /!<Bit 6 /
Kojto	107:4f6c30876dfa	8670
Kojto	107:4f6c30876dfa	8671	/****************** Bit definition for USB_OTG_DTHRCTL register ******************/
Kojto	122:f9eeca106725	8672	#define USB_OTG_DTHRCTL_NONISOTHREN 0x00000001U /!< Nonisochronous IN endpoints threshold enable /
Kojto	122:f9eeca106725	8673	#define USB_OTG_DTHRCTL_ISOTHREN 0x00000002U /!< ISO IN endpoint threshold enable /
Kojto	122:f9eeca106725	8674
Kojto	122:f9eeca106725	8675	#define USB_OTG_DTHRCTL_TXTHRLEN 0x000007FCU /!< Transmit threshold length /
Kojto	122:f9eeca106725	8676	#define USB_OTG_DTHRCTL_TXTHRLEN_0 0x00000004U /!<Bit 0 /
Kojto	122:f9eeca106725	8677	#define USB_OTG_DTHRCTL_TXTHRLEN_1 0x00000008U /!<Bit 1 /
Kojto	122:f9eeca106725	8678	#define USB_OTG_DTHRCTL_TXTHRLEN_2 0x00000010U /!<Bit 2 /
Kojto	122:f9eeca106725	8679	#define USB_OTG_DTHRCTL_TXTHRLEN_3 0x00000020U /!<Bit 3 /
Kojto	122:f9eeca106725	8680	#define USB_OTG_DTHRCTL_TXTHRLEN_4 0x00000040U /!<Bit 4 /
Kojto	122:f9eeca106725	8681	#define USB_OTG_DTHRCTL_TXTHRLEN_5 0x00000080U /!<Bit 5 /
Kojto	122:f9eeca106725	8682	#define USB_OTG_DTHRCTL_TXTHRLEN_6 0x00000100U /!<Bit 6 /
Kojto	122:f9eeca106725	8683	#define USB_OTG_DTHRCTL_TXTHRLEN_7 0x00000200U /!<Bit 7 /
Kojto	122:f9eeca106725	8684	#define USB_OTG_DTHRCTL_TXTHRLEN_8 0x00000400U /!<Bit 8 /
Kojto	122:f9eeca106725	8685	#define USB_OTG_DTHRCTL_RXTHREN 0x00010000U /!< Receive threshold enable /
Kojto	122:f9eeca106725	8686
Kojto	122:f9eeca106725	8687	#define USB_OTG_DTHRCTL_RXTHRLEN 0x03FE0000U /!< Receive threshold length /
Kojto	122:f9eeca106725	8688	#define USB_OTG_DTHRCTL_RXTHRLEN_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	8689	#define USB_OTG_DTHRCTL_RXTHRLEN_1 0x00040000U /!<Bit 1 /
Kojto	122:f9eeca106725	8690	#define USB_OTG_DTHRCTL_RXTHRLEN_2 0x00080000U /!<Bit 2 /
Kojto	122:f9eeca106725	8691	#define USB_OTG_DTHRCTL_RXTHRLEN_3 0x00100000U /!<Bit 3 /
Kojto	122:f9eeca106725	8692	#define USB_OTG_DTHRCTL_RXTHRLEN_4 0x00200000U /!<Bit 4 /
Kojto	122:f9eeca106725	8693	#define USB_OTG_DTHRCTL_RXTHRLEN_5 0x00400000U /!<Bit 5 /
Kojto	122:f9eeca106725	8694	#define USB_OTG_DTHRCTL_RXTHRLEN_6 0x00800000U /!<Bit 6 /
Kojto	122:f9eeca106725	8695	#define USB_OTG_DTHRCTL_RXTHRLEN_7 0x01000000U /!<Bit 7 /
Kojto	122:f9eeca106725	8696	#define USB_OTG_DTHRCTL_RXTHRLEN_8 0x02000000U /!<Bit 8 /
Kojto	122:f9eeca106725	8697	#define USB_OTG_DTHRCTL_ARPEN 0x08000000U /!< Arbiter parking enable /
Kojto	107:4f6c30876dfa	8698
Kojto	107:4f6c30876dfa	8699	/****************** Bit definition for USB_OTG_DIEPEMPMSK register ******************/
Kojto	122:f9eeca106725	8700	#define USB_OTG_DIEPEMPMSK_INEPTXFEM 0x0000FFFFU /!< IN EP Tx FIFO empty interrupt mask bits /
Kojto	107:4f6c30876dfa	8701
Kojto	107:4f6c30876dfa	8702	/****************** Bit definition for USB_OTG_DEACHINT register ******************/
Kojto	122:f9eeca106725	8703	#define USB_OTG_DEACHINT_IEP1INT 0x00000002U /!< IN endpoint 1interrupt bit /
Kojto	122:f9eeca106725	8704	#define USB_OTG_DEACHINT_OEP1INT 0x00020000U /!< OUT endpoint 1 interrupt bit /
Kojto	107:4f6c30876dfa	8705
Kojto	107:4f6c30876dfa	8706	/****************** Bit definition for USB_OTG_GCCFG register ******************/
Kojto	122:f9eeca106725	8707	#define USB_OTG_GCCFG_PWRDWN 0x00010000U /!< Power down /
Kojto	122:f9eeca106725	8708	#define USB_OTG_GCCFG_VBDEN 0x00200000U /!< USB VBUS Detection Enable /
Kojto	107:4f6c30876dfa	8709
Kojto	107:4f6c30876dfa	8710	/****************** Bit definition for USB_OTG_GPWRDN) register ******************/
Kojto	122:f9eeca106725	8711	#define USB_OTG_GPWRDN_ADPMEN 0x00000001U /!< ADP module enable /
Kojto	122:f9eeca106725	8712	#define USB_OTG_GPWRDN_ADPIF 0x00800000U /!< ADP Interrupt flag /
Kojto	107:4f6c30876dfa	8713
Kojto	107:4f6c30876dfa	8714	/****************** Bit definition for USB_OTG_DEACHINTMSK register ******************/
Kojto	122:f9eeca106725	8715	#define USB_OTG_DEACHINTMSK_IEP1INTM 0x00000002U /!< IN Endpoint 1 interrupt mask bit /
Kojto	122:f9eeca106725	8716	#define USB_OTG_DEACHINTMSK_OEP1INTM 0x00020000U /!< OUT Endpoint 1 interrupt mask bit /
Kojto	107:4f6c30876dfa	8717
Kojto	107:4f6c30876dfa	8718	/****************** Bit definition for USB_OTG_CID register ******************/
Kojto	122:f9eeca106725	8719	#define USB_OTG_CID_PRODUCT_ID 0xFFFFFFFFU /!< Product ID field /
Kojto	107:4f6c30876dfa	8720
Kojto	107:4f6c30876dfa	8721	/****************** Bit definition for USB_OTG_GLPMCFG register ******************/
Kojto	122:f9eeca106725	8722	#define USB_OTG_GLPMCFG_LPMEN 0x00000001U /!< LPM support enable /
Kojto	122:f9eeca106725	8723	#define USB_OTG_GLPMCFG_LPMACK 0x00000002U /!< LPM Token acknowledge enable /
Kojto	122:f9eeca106725	8724	#define USB_OTG_GLPMCFG_BESL 0x0000003CU /!< BESL value received with last ACKed LPM Token /
Kojto	122:f9eeca106725	8725	#define USB_OTG_GLPMCFG_REMWAKE 0x00000040U /!< bRemoteWake value received with last ACKed LPM Token /
Kojto	122:f9eeca106725	8726	#define USB_OTG_GLPMCFG_L1SSEN 0x00000080U /!< L1 shallow sleep enable /
Kojto	122:f9eeca106725	8727	#define USB_OTG_GLPMCFG_BESLTHRS 0x00000F00U /!< BESL threshold /
Kojto	122:f9eeca106725	8728	#define USB_OTG_GLPMCFG_L1DSEN 0x00001000U /!< L1 deep sleep enable /
Kojto	122:f9eeca106725	8729	#define USB_OTG_GLPMCFG_LPMRSP 0x00006000U /!< LPM response /
Kojto	122:f9eeca106725	8730	#define USB_OTG_GLPMCFG_SLPSTS 0x00008000U /!< Port sleep status /
Kojto	122:f9eeca106725	8731	#define USB_OTG_GLPMCFG_L1RSMOK 0x00010000U /!< Sleep State Resume OK /
Kojto	122:f9eeca106725	8732	#define USB_OTG_GLPMCFG_LPMCHIDX 0x001E0000U /!< LPM Channel Index /
Kojto	122:f9eeca106725	8733	#define USB_OTG_GLPMCFG_LPMRCNT 0x00E00000U /!< LPM retry count /
Kojto	122:f9eeca106725	8734	#define USB_OTG_GLPMCFG_SNDLPM 0x01000000U /!< Send LPM transaction /
Kojto	122:f9eeca106725	8735	#define USB_OTG_GLPMCFG_LPMRCNTSTS 0x0E000000U /!< LPM retry count status /
Kojto	122:f9eeca106725	8736	#define USB_OTG_GLPMCFG_ENBESL 0x10000000U /!< Enable best effort service latency /
Kojto	107:4f6c30876dfa	8737
Kojto	107:4f6c30876dfa	8738	/****************** Bit definition for USB_OTG_DIEPEACHMSK1 register ******************/
Kojto	122:f9eeca106725	8739	#define USB_OTG_DIEPEACHMSK1_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	8740	#define USB_OTG_DIEPEACHMSK1_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	8741	#define USB_OTG_DIEPEACHMSK1_TOM 0x00000008U /!< Timeout condition mask (nonisochronous endpoints) /
Kojto	122:f9eeca106725	8742	#define USB_OTG_DIEPEACHMSK1_ITTXFEMSK 0x00000010U /!< IN token received when TxFIFO empty mask /
Kojto	122:f9eeca106725	8743	#define USB_OTG_DIEPEACHMSK1_INEPNMM 0x00000020U /!< IN token received with EP mismatch mask /
Kojto	122:f9eeca106725	8744	#define USB_OTG_DIEPEACHMSK1_INEPNEM 0x00000040U /!< IN endpoint NAK effective mask /
Kojto	122:f9eeca106725	8745	#define USB_OTG_DIEPEACHMSK1_TXFURM 0x00000100U /!< FIFO underrun mask /
Kojto	122:f9eeca106725	8746	#define USB_OTG_DIEPEACHMSK1_BIM 0x00000200U /!< BNA interrupt mask /
Kojto	122:f9eeca106725	8747	#define USB_OTG_DIEPEACHMSK1_NAKM 0x00002000U /!< NAK interrupt mask /
Kojto	107:4f6c30876dfa	8748
Kojto	107:4f6c30876dfa	8749	/****************** Bit definition for USB_OTG_HPRT register ******************/
Kojto	122:f9eeca106725	8750	#define USB_OTG_HPRT_PCSTS 0x00000001U /!< Port connect status /
Kojto	122:f9eeca106725	8751	#define USB_OTG_HPRT_PCDET 0x00000002U /!< Port connect detected /
Kojto	122:f9eeca106725	8752	#define USB_OTG_HPRT_PENA 0x00000004U /!< Port enable /
Kojto	122:f9eeca106725	8753	#define USB_OTG_HPRT_PENCHNG 0x00000008U /!< Port enable/disable change /
Kojto	122:f9eeca106725	8754	#define USB_OTG_HPRT_POCA 0x00000010U /!< Port overcurrent active /
Kojto	122:f9eeca106725	8755	#define USB_OTG_HPRT_POCCHNG 0x00000020U /!< Port overcurrent change /
Kojto	122:f9eeca106725	8756	#define USB_OTG_HPRT_PRES 0x00000040U /!< Port resume /
Kojto	122:f9eeca106725	8757	#define USB_OTG_HPRT_PSUSP 0x00000080U /!< Port suspend /
Kojto	122:f9eeca106725	8758	#define USB_OTG_HPRT_PRST 0x00000100U /!< Port reset /
Kojto	122:f9eeca106725	8759
Kojto	122:f9eeca106725	8760	#define USB_OTG_HPRT_PLSTS 0x00000C00U /!< Port line status /
Kojto	122:f9eeca106725	8761	#define USB_OTG_HPRT_PLSTS_0 0x00000400U /!<Bit 0 /
Kojto	122:f9eeca106725	8762	#define USB_OTG_HPRT_PLSTS_1 0x00000800U /!<Bit 1 /
Kojto	122:f9eeca106725	8763	#define USB_OTG_HPRT_PPWR 0x00001000U /!< Port power /
Kojto	122:f9eeca106725	8764
Kojto	122:f9eeca106725	8765	#define USB_OTG_HPRT_PTCTL 0x0001E000U /!< Port test control /
Kojto	122:f9eeca106725	8766	#define USB_OTG_HPRT_PTCTL_0 0x00002000U /!<Bit 0 /
Kojto	122:f9eeca106725	8767	#define USB_OTG_HPRT_PTCTL_1 0x00004000U /!<Bit 1 /
Kojto	122:f9eeca106725	8768	#define USB_OTG_HPRT_PTCTL_2 0x00008000U /!<Bit 2 /
Kojto	122:f9eeca106725	8769	#define USB_OTG_HPRT_PTCTL_3 0x00010000U /!<Bit 3 /
Kojto	122:f9eeca106725	8770
Kojto	122:f9eeca106725	8771	#define USB_OTG_HPRT_PSPD 0x00060000U /!< Port speed /
Kojto	122:f9eeca106725	8772	#define USB_OTG_HPRT_PSPD_0 0x00020000U /!<Bit 0 /
Kojto	122:f9eeca106725	8773	#define USB_OTG_HPRT_PSPD_1 0x00040000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	8774
Kojto	107:4f6c30876dfa	8775	/****************** Bit definition for USB_OTG_DOEPEACHMSK1 register ******************/
Kojto	122:f9eeca106725	8776	#define USB_OTG_DOEPEACHMSK1_XFRCM 0x00000001U /!< Transfer completed interrupt mask /
Kojto	122:f9eeca106725	8777	#define USB_OTG_DOEPEACHMSK1_EPDM 0x00000002U /!< Endpoint disabled interrupt mask /
Kojto	122:f9eeca106725	8778	#define USB_OTG_DOEPEACHMSK1_TOM 0x00000008U /!< Timeout condition mask /
Kojto	122:f9eeca106725	8779	#define USB_OTG_DOEPEACHMSK1_ITTXFEMSK 0x00000010U /!< IN token received when TxFIFO empty mask /
Kojto	122:f9eeca106725	8780	#define USB_OTG_DOEPEACHMSK1_INEPNMM 0x00000020U /!< IN token received with EP mismatch mask /
Kojto	122:f9eeca106725	8781	#define USB_OTG_DOEPEACHMSK1_INEPNEM 0x00000040U /!< IN endpoint NAK effective mask /
Kojto	122:f9eeca106725	8782	#define USB_OTG_DOEPEACHMSK1_TXFURM 0x00000100U /!< OUT packet error mask /
Kojto	122:f9eeca106725	8783	#define USB_OTG_DOEPEACHMSK1_BIM 0x00000200U /!< BNA interrupt mask /
Kojto	122:f9eeca106725	8784	#define USB_OTG_DOEPEACHMSK1_BERRM 0x00001000U /!< Bubble error interrupt mask /
Kojto	122:f9eeca106725	8785	#define USB_OTG_DOEPEACHMSK1_NAKM 0x00002000U /!< NAK interrupt mask /
Kojto	122:f9eeca106725	8786	#define USB_OTG_DOEPEACHMSK1_NYETM 0x00004000U /!< NYET interrupt mask /
Kojto	107:4f6c30876dfa	8787
Kojto	107:4f6c30876dfa	8788	/****************** Bit definition for USB_OTG_HPTXFSIZ register ******************/
Kojto	122:f9eeca106725	8789	#define USB_OTG_HPTXFSIZ_PTXSA 0x0000FFFFU /!< Host periodic TxFIFO start address /
Kojto	122:f9eeca106725	8790	#define USB_OTG_HPTXFSIZ_PTXFD 0xFFFF0000U /!< Host periodic TxFIFO depth /
Kojto	107:4f6c30876dfa	8791
Kojto	107:4f6c30876dfa	8792	/****************** Bit definition for USB_OTG_DIEPCTL register ******************/
Kojto	122:f9eeca106725	8793	#define USB_OTG_DIEPCTL_MPSIZ 0x000007FFU /!< Maximum packet size /
Kojto	122:f9eeca106725	8794	#define USB_OTG_DIEPCTL_USBAEP 0x00008000U /!< USB active endpoint /
Kojto	122:f9eeca106725	8795	#define USB_OTG_DIEPCTL_EONUM_DPID 0x00010000U /!< Even/odd frame /
Kojto	122:f9eeca106725	8796	#define USB_OTG_DIEPCTL_NAKSTS 0x00020000U /!< NAK status /
Kojto	122:f9eeca106725	8797
Kojto	122:f9eeca106725	8798	#define USB_OTG_DIEPCTL_EPTYP 0x000C0000U /!< Endpoint type /
Kojto	122:f9eeca106725	8799	#define USB_OTG_DIEPCTL_EPTYP_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	8800	#define USB_OTG_DIEPCTL_EPTYP_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	8801	#define USB_OTG_DIEPCTL_STALL 0x00200000U /!< STALL handshake /
Kojto	122:f9eeca106725	8802
Kojto	122:f9eeca106725	8803	#define USB_OTG_DIEPCTL_TXFNUM 0x03C00000U /!< TxFIFO number /
Kojto	122:f9eeca106725	8804	#define USB_OTG_DIEPCTL_TXFNUM_0 0x00400000U /!<Bit 0 /
Kojto	122:f9eeca106725	8805	#define USB_OTG_DIEPCTL_TXFNUM_1 0x00800000U /!<Bit 1 /
Kojto	122:f9eeca106725	8806	#define USB_OTG_DIEPCTL_TXFNUM_2 0x01000000U /!<Bit 2 /
Kojto	122:f9eeca106725	8807	#define USB_OTG_DIEPCTL_TXFNUM_3 0x02000000U /!<Bit 3 /
Kojto	122:f9eeca106725	8808	#define USB_OTG_DIEPCTL_CNAK 0x04000000U /!< Clear NAK /
Kojto	122:f9eeca106725	8809	#define USB_OTG_DIEPCTL_SNAK 0x08000000U /!< Set NAK /
Kojto	122:f9eeca106725	8810	#define USB_OTG_DIEPCTL_SD0PID_SEVNFRM 0x10000000U /!< Set DATA0 PID /
Kojto	122:f9eeca106725	8811	#define USB_OTG_DIEPCTL_SODDFRM 0x20000000U /!< Set odd frame /
Kojto	122:f9eeca106725	8812	#define USB_OTG_DIEPCTL_EPDIS 0x40000000U /!< Endpoint disable /
Kojto	122:f9eeca106725	8813	#define USB_OTG_DIEPCTL_EPENA 0x80000000U /!< Endpoint enable /
Kojto	107:4f6c30876dfa	8814
Kojto	107:4f6c30876dfa	8815	/****************** Bit definition for USB_OTG_HCCHAR register ******************/
Kojto	122:f9eeca106725	8816	#define USB_OTG_HCCHAR_MPSIZ 0x000007FFU /!< Maximum packet size /
Kojto	122:f9eeca106725	8817
Kojto	122:f9eeca106725	8818	#define USB_OTG_HCCHAR_EPNUM 0x00007800U /!< Endpoint number /
Kojto	122:f9eeca106725	8819	#define USB_OTG_HCCHAR_EPNUM_0 0x00000800U /!<Bit 0 /
Kojto	122:f9eeca106725	8820	#define USB_OTG_HCCHAR_EPNUM_1 0x00001000U /!<Bit 1 /
Kojto	122:f9eeca106725	8821	#define USB_OTG_HCCHAR_EPNUM_2 0x00002000U /!<Bit 2 /
Kojto	122:f9eeca106725	8822	#define USB_OTG_HCCHAR_EPNUM_3 0x00004000U /!<Bit 3 /
Kojto	122:f9eeca106725	8823	#define USB_OTG_HCCHAR_EPDIR 0x00008000U /!< Endpoint direction /
Kojto	122:f9eeca106725	8824	#define USB_OTG_HCCHAR_LSDEV 0x00020000U /!< Low-speed device /
Kojto	122:f9eeca106725	8825
Kojto	122:f9eeca106725	8826	#define USB_OTG_HCCHAR_EPTYP 0x000C0000U /!< Endpoint type /
Kojto	122:f9eeca106725	8827	#define USB_OTG_HCCHAR_EPTYP_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	8828	#define USB_OTG_HCCHAR_EPTYP_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	8829
Kojto	122:f9eeca106725	8830	#define USB_OTG_HCCHAR_MC 0x00300000U /!< Multi Count (MC) / Error Count (EC) /
Kojto	122:f9eeca106725	8831	#define USB_OTG_HCCHAR_MC_0 0x00100000U /!<Bit 0 /
Kojto	122:f9eeca106725	8832	#define USB_OTG_HCCHAR_MC_1 0x00200000U /!<Bit 1 /
Kojto	122:f9eeca106725	8833
Kojto	122:f9eeca106725	8834	#define USB_OTG_HCCHAR_DAD 0x1FC00000U /!< Device address /
Kojto	122:f9eeca106725	8835	#define USB_OTG_HCCHAR_DAD_0 0x00400000U /!<Bit 0 /
Kojto	122:f9eeca106725	8836	#define USB_OTG_HCCHAR_DAD_1 0x00800000U /!<Bit 1 /
Kojto	122:f9eeca106725	8837	#define USB_OTG_HCCHAR_DAD_2 0x01000000U /!<Bit 2 /
Kojto	122:f9eeca106725	8838	#define USB_OTG_HCCHAR_DAD_3 0x02000000U /!<Bit 3 /
Kojto	122:f9eeca106725	8839	#define USB_OTG_HCCHAR_DAD_4 0x04000000U /!<Bit 4 /
Kojto	122:f9eeca106725	8840	#define USB_OTG_HCCHAR_DAD_5 0x08000000U /!<Bit 5 /
Kojto	122:f9eeca106725	8841	#define USB_OTG_HCCHAR_DAD_6 0x10000000U /!<Bit 6 /
Kojto	122:f9eeca106725	8842	#define USB_OTG_HCCHAR_ODDFRM 0x20000000U /!< Odd frame /
Kojto	122:f9eeca106725	8843	#define USB_OTG_HCCHAR_CHDIS 0x40000000U /!< Channel disable /
Kojto	122:f9eeca106725	8844	#define USB_OTG_HCCHAR_CHENA 0x80000000U /!< Channel enable /
Kojto	107:4f6c30876dfa	8845
Kojto	107:4f6c30876dfa	8846	/****************** Bit definition for USB_OTG_HCSPLT register ******************/
Kojto	107:4f6c30876dfa	8847
Kojto	122:f9eeca106725	8848	#define USB_OTG_HCSPLT_PRTADDR 0x0000007FU /!< Port address /
Kojto	122:f9eeca106725	8849	#define USB_OTG_HCSPLT_PRTADDR_0 0x00000001U /!<Bit 0 /
Kojto	122:f9eeca106725	8850	#define USB_OTG_HCSPLT_PRTADDR_1 0x00000002U /!<Bit 1 /
Kojto	122:f9eeca106725	8851	#define USB_OTG_HCSPLT_PRTADDR_2 0x00000004U /!<Bit 2 /
Kojto	122:f9eeca106725	8852	#define USB_OTG_HCSPLT_PRTADDR_3 0x00000008U /!<Bit 3 /
Kojto	122:f9eeca106725	8853	#define USB_OTG_HCSPLT_PRTADDR_4 0x00000010U /!<Bit 4 /
Kojto	122:f9eeca106725	8854	#define USB_OTG_HCSPLT_PRTADDR_5 0x00000020U /!<Bit 5 /
Kojto	122:f9eeca106725	8855	#define USB_OTG_HCSPLT_PRTADDR_6 0x00000040U /!<Bit 6 /
Kojto	122:f9eeca106725	8856
Kojto	122:f9eeca106725	8857	#define USB_OTG_HCSPLT_HUBADDR 0x00003F80U /!< Hub address /
Kojto	122:f9eeca106725	8858	#define USB_OTG_HCSPLT_HUBADDR_0 0x00000080U /!<Bit 0 /
Kojto	122:f9eeca106725	8859	#define USB_OTG_HCSPLT_HUBADDR_1 0x00000100U /!<Bit 1 /
Kojto	122:f9eeca106725	8860	#define USB_OTG_HCSPLT_HUBADDR_2 0x00000200U /!<Bit 2 /
Kojto	122:f9eeca106725	8861	#define USB_OTG_HCSPLT_HUBADDR_3 0x00000400U /!<Bit 3 /
Kojto	122:f9eeca106725	8862	#define USB_OTG_HCSPLT_HUBADDR_4 0x00000800U /!<Bit 4 /
Kojto	122:f9eeca106725	8863	#define USB_OTG_HCSPLT_HUBADDR_5 0x00001000U /!<Bit 5 /
Kojto	122:f9eeca106725	8864	#define USB_OTG_HCSPLT_HUBADDR_6 0x00002000U /!<Bit 6 /
Kojto	122:f9eeca106725	8865
Kojto	122:f9eeca106725	8866	#define USB_OTG_HCSPLT_XACTPOS 0x0000C000U /!< XACTPOS /
Kojto	122:f9eeca106725	8867	#define USB_OTG_HCSPLT_XACTPOS_0 0x00004000U /!<Bit 0 /
Kojto	122:f9eeca106725	8868	#define USB_OTG_HCSPLT_XACTPOS_1 0x00008000U /!<Bit 1 /
Kojto	122:f9eeca106725	8869	#define USB_OTG_HCSPLT_COMPLSPLT 0x00010000U /!< Do complete split /
Kojto	122:f9eeca106725	8870	#define USB_OTG_HCSPLT_SPLITEN 0x80000000U /!< Split enable /
Kojto	107:4f6c30876dfa	8871
Kojto	107:4f6c30876dfa	8872	/****************** Bit definition for USB_OTG_HCINT register ******************/
Kojto	122:f9eeca106725	8873	#define USB_OTG_HCINT_XFRC 0x00000001U /!< Transfer completed /
Kojto	122:f9eeca106725	8874	#define USB_OTG_HCINT_CHH 0x00000002U /!< Channel halted /
Kojto	122:f9eeca106725	8875	#define USB_OTG_HCINT_AHBERR 0x00000004U /!< AHB error /
Kojto	122:f9eeca106725	8876	#define USB_OTG_HCINT_STALL 0x00000008U /!< STALL response received interrupt /
Kojto	122:f9eeca106725	8877	#define USB_OTG_HCINT_NAK 0x00000010U /!< NAK response received interrupt /
Kojto	122:f9eeca106725	8878	#define USB_OTG_HCINT_ACK 0x00000020U /!< ACK response received/transmitted interrupt /
Kojto	122:f9eeca106725	8879	#define USB_OTG_HCINT_NYET 0x00000040U /!< Response received interrupt /
Kojto	122:f9eeca106725	8880	#define USB_OTG_HCINT_TXERR 0x00000080U /!< Transaction error /
Kojto	122:f9eeca106725	8881	#define USB_OTG_HCINT_BBERR 0x00000100U /!< Babble error /
Kojto	122:f9eeca106725	8882	#define USB_OTG_HCINT_FRMOR 0x00000200U /!< Frame overrun /
Kojto	122:f9eeca106725	8883	#define USB_OTG_HCINT_DTERR 0x00000400U /!< Data toggle error /
Kojto	107:4f6c30876dfa	8884
Kojto	107:4f6c30876dfa	8885	/****************** Bit definition for USB_OTG_DIEPINT register ******************/
Kojto	122:f9eeca106725	8886	#define USB_OTG_DIEPINT_XFRC 0x00000001U /!< Transfer completed interrupt /
Kojto	122:f9eeca106725	8887	#define USB_OTG_DIEPINT_EPDISD 0x00000002U /!< Endpoint disabled interrupt /
Kojto	122:f9eeca106725	8888	#define USB_OTG_DIEPINT_TOC 0x00000008U /!< Timeout condition /
Kojto	122:f9eeca106725	8889	#define USB_OTG_DIEPINT_ITTXFE 0x00000010U /!< IN token received when TxFIFO is empty /
Kojto	122:f9eeca106725	8890	#define USB_OTG_DIEPINT_INEPNE 0x00000040U /!< IN endpoint NAK effective /
Kojto	122:f9eeca106725	8891	#define USB_OTG_DIEPINT_TXFE 0x00000080U /!< Transmit FIFO empty /
Kojto	122:f9eeca106725	8892	#define USB_OTG_DIEPINT_TXFIFOUDRN 0x00000100U /!< Transmit Fifo Underrun /
Kojto	122:f9eeca106725	8893	#define USB_OTG_DIEPINT_BNA 0x00000200U /!< Buffer not available interrupt /
Kojto	122:f9eeca106725	8894	#define USB_OTG_DIEPINT_PKTDRPSTS 0x00000800U /!< Packet dropped status /
Kojto	122:f9eeca106725	8895	#define USB_OTG_DIEPINT_BERR 0x00001000U /!< Babble error interrupt /
Kojto	122:f9eeca106725	8896	#define USB_OTG_DIEPINT_NAK 0x00002000U /!< NAK interrupt /
Kojto	107:4f6c30876dfa	8897
Kojto	107:4f6c30876dfa	8898	/****************** Bit definition for USB_OTG_HCINTMSK register ******************/
Kojto	122:f9eeca106725	8899	#define USB_OTG_HCINTMSK_XFRCM 0x00000001U /!< Transfer completed mask /
Kojto	122:f9eeca106725	8900	#define USB_OTG_HCINTMSK_CHHM 0x00000002U /!< Channel halted mask /
Kojto	122:f9eeca106725	8901	#define USB_OTG_HCINTMSK_AHBERR 0x00000004U /!< AHB error /
Kojto	122:f9eeca106725	8902	#define USB_OTG_HCINTMSK_STALLM 0x00000008U /!< STALL response received interrupt mask /
Kojto	122:f9eeca106725	8903	#define USB_OTG_HCINTMSK_NAKM 0x00000010U /!< NAK response received interrupt mask /
Kojto	122:f9eeca106725	8904	#define USB_OTG_HCINTMSK_ACKM 0x00000020U /!< ACK response received/transmitted interrupt mask /
Kojto	122:f9eeca106725	8905	#define USB_OTG_HCINTMSK_NYET 0x00000040U /!< response received interrupt mask /
Kojto	122:f9eeca106725	8906	#define USB_OTG_HCINTMSK_TXERRM 0x00000080U /!< Transaction error mask /
Kojto	122:f9eeca106725	8907	#define USB_OTG_HCINTMSK_BBERRM 0x00000100U /!< Babble error mask /
Kojto	122:f9eeca106725	8908	#define USB_OTG_HCINTMSK_FRMORM 0x00000200U /!< Frame overrun mask /
Kojto	122:f9eeca106725	8909	#define USB_OTG_HCINTMSK_DTERRM 0x00000400U /!< Data toggle error mask /
Kojto	107:4f6c30876dfa	8910
Kojto	107:4f6c30876dfa	8911	/****************** Bit definition for USB_OTG_DIEPTSIZ register ******************/
Kojto	107:4f6c30876dfa	8912
Kojto	122:f9eeca106725	8913	#define USB_OTG_DIEPTSIZ_XFRSIZ 0x0007FFFFU /!< Transfer size /
Kojto	122:f9eeca106725	8914	#define USB_OTG_DIEPTSIZ_PKTCNT 0x1FF80000U /!< Packet count /
Kojto	122:f9eeca106725	8915	#define USB_OTG_DIEPTSIZ_MULCNT 0x60000000U /!< Packet count /
Kojto	107:4f6c30876dfa	8916	/****************** Bit definition for USB_OTG_HCTSIZ register ******************/
Kojto	122:f9eeca106725	8917	#define USB_OTG_HCTSIZ_XFRSIZ 0x0007FFFFU /!< Transfer size /
Kojto	122:f9eeca106725	8918	#define USB_OTG_HCTSIZ_PKTCNT 0x1FF80000U /!< Packet count /
Kojto	122:f9eeca106725	8919	#define USB_OTG_HCTSIZ_DOPING 0x80000000U /!< Do PING /
Kojto	122:f9eeca106725	8920	#define USB_OTG_HCTSIZ_DPID 0x60000000U /!< Data PID /
Kojto	122:f9eeca106725	8921	#define USB_OTG_HCTSIZ_DPID_0 0x20000000U /!<Bit 0 /
Kojto	122:f9eeca106725	8922	#define USB_OTG_HCTSIZ_DPID_1 0x40000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	8923
Kojto	107:4f6c30876dfa	8924	/****************** Bit definition for USB_OTG_DIEPDMA register ******************/
Kojto	122:f9eeca106725	8925	#define USB_OTG_DIEPDMA_DMAADDR 0xFFFFFFFFU /!< DMA address /
Kojto	107:4f6c30876dfa	8926
Kojto	107:4f6c30876dfa	8927	/****************** Bit definition for USB_OTG_HCDMA register ******************/
Kojto	122:f9eeca106725	8928	#define USB_OTG_HCDMA_DMAADDR 0xFFFFFFFFU /!< DMA address /
Kojto	107:4f6c30876dfa	8929
Kojto	107:4f6c30876dfa	8930	/****************** Bit definition for USB_OTG_DTXFSTS register ******************/
Kojto	122:f9eeca106725	8931	#define USB_OTG_DTXFSTS_INEPTFSAV 0x0000FFFFU /!< IN endpoint TxFIFO space available /
Kojto	107:4f6c30876dfa	8932
Kojto	107:4f6c30876dfa	8933	/****************** Bit definition for USB_OTG_DIEPTXF register ******************/
Kojto	122:f9eeca106725	8934	#define USB_OTG_DIEPTXF_INEPTXSA 0x0000FFFFU /!< IN endpoint FIFOx transmit RAM start address /
Kojto	122:f9eeca106725	8935	#define USB_OTG_DIEPTXF_INEPTXFD 0xFFFF0000U /!< IN endpoint TxFIFO depth /
Kojto	107:4f6c30876dfa	8936
Kojto	107:4f6c30876dfa	8937	/****************** Bit definition for USB_OTG_DOEPCTL register ******************/
Kojto	122:f9eeca106725	8938	#define USB_OTG_DOEPCTL_MPSIZ 0x000007FFU /!< Maximum packet size / /!<Bit 1 /
Kojto	122:f9eeca106725	8939	#define USB_OTG_DOEPCTL_USBAEP 0x00008000U /!< USB active endpoint /
Kojto	122:f9eeca106725	8940	#define USB_OTG_DOEPCTL_NAKSTS 0x00020000U /!< NAK status /
Kojto	122:f9eeca106725	8941	#define USB_OTG_DOEPCTL_SD0PID_SEVNFRM 0x10000000U /!< Set DATA0 PID /
Kojto	122:f9eeca106725	8942	#define USB_OTG_DOEPCTL_SODDFRM 0x20000000U /!< Set odd frame /
Kojto	122:f9eeca106725	8943	#define USB_OTG_DOEPCTL_EPTYP 0x000C0000U /!< Endpoint type /
Kojto	122:f9eeca106725	8944	#define USB_OTG_DOEPCTL_EPTYP_0 0x00040000U /!<Bit 0 /
Kojto	122:f9eeca106725	8945	#define USB_OTG_DOEPCTL_EPTYP_1 0x00080000U /!<Bit 1 /
Kojto	122:f9eeca106725	8946	#define USB_OTG_DOEPCTL_SNPM 0x00100000U /!< Snoop mode /
Kojto	122:f9eeca106725	8947	#define USB_OTG_DOEPCTL_STALL 0x00200000U /!< STALL handshake /
Kojto	122:f9eeca106725	8948	#define USB_OTG_DOEPCTL_CNAK 0x04000000U /!< Clear NAK /
Kojto	122:f9eeca106725	8949	#define USB_OTG_DOEPCTL_SNAK 0x08000000U /!< Set NAK /
Kojto	122:f9eeca106725	8950	#define USB_OTG_DOEPCTL_EPDIS 0x40000000U /!< Endpoint disable /
Kojto	122:f9eeca106725	8951	#define USB_OTG_DOEPCTL_EPENA 0x80000000U /!< Endpoint enable /
Kojto	107:4f6c30876dfa	8952
Kojto	107:4f6c30876dfa	8953	/****************** Bit definition for USB_OTG_DOEPINT register ******************/
Kojto	122:f9eeca106725	8954	#define USB_OTG_DOEPINT_XFRC 0x00000001U /!< Transfer completed interrupt /
Kojto	122:f9eeca106725	8955	#define USB_OTG_DOEPINT_EPDISD 0x00000002U /!< Endpoint disabled interrupt /
Kojto	122:f9eeca106725	8956	#define USB_OTG_DOEPINT_STUP 0x00000008U /!< SETUP phase done /
Kojto	122:f9eeca106725	8957	#define USB_OTG_DOEPINT_OTEPDIS 0x00000010U /!< OUT token received when endpoint disabled /
Kojto	122:f9eeca106725	8958	#define USB_OTG_DOEPINT_OTEPSPR 0x00000020U /!< Status Phase Received For Control Write /
Kojto	122:f9eeca106725	8959	#define USB_OTG_DOEPINT_B2BSTUP 0x00000040U /!< Back-to-back SETUP packets received /
Kojto	122:f9eeca106725	8960	#define USB_OTG_DOEPINT_NYET 0x00004000U /!< NYET interrupt /
Kojto	107:4f6c30876dfa	8961
Kojto	107:4f6c30876dfa	8962	/****************** Bit definition for USB_OTG_DOEPTSIZ register ******************/
Kojto	122:f9eeca106725	8963	#define USB_OTG_DOEPTSIZ_XFRSIZ 0x0007FFFFU /!< Transfer size /
Kojto	122:f9eeca106725	8964	#define USB_OTG_DOEPTSIZ_PKTCNT 0x1FF80000U /!< Packet count /
Kojto	122:f9eeca106725	8965
Kojto	122:f9eeca106725	8966	#define USB_OTG_DOEPTSIZ_STUPCNT 0x60000000U /!< SETUP packet count /
Kojto	122:f9eeca106725	8967	#define USB_OTG_DOEPTSIZ_STUPCNT_0 0x20000000U /!<Bit 0 /
Kojto	122:f9eeca106725	8968	#define USB_OTG_DOEPTSIZ_STUPCNT_1 0x40000000U /!<Bit 1 /
Kojto	107:4f6c30876dfa	8969
Kojto	107:4f6c30876dfa	8970	/****************** Bit definition for PCGCCTL register ******************/
Kojto	122:f9eeca106725	8971	#define USB_OTG_PCGCCTL_STOPCLK 0x00000001U /!< SETUP packet count /
Kojto	122:f9eeca106725	8972	#define USB_OTG_PCGCCTL_GATECLK 0x00000002U /!<Bit 0 /
Kojto	122:f9eeca106725	8973	#define USB_OTG_PCGCCTL_PHYSUSP 0x00000010U /!<Bit 1 /
Kojto	122:f9eeca106725	8974
Kojto	122:f9eeca106725	8975
Kojto	107:4f6c30876dfa	8976
Kojto	107:4f6c30876dfa	8977	/**
Kojto	107:4f6c30876dfa	8978	* @}
Kojto	107:4f6c30876dfa	8979	*/
Kojto	107:4f6c30876dfa	8980
Kojto	107:4f6c30876dfa	8981	/**
Kojto	107:4f6c30876dfa	8982	* @}
Kojto	107:4f6c30876dfa	8983	*/
Kojto	107:4f6c30876dfa	8984
Kojto	107:4f6c30876dfa	8985	/** @addtogroup Exported_macros
Kojto	107:4f6c30876dfa	8986	* @{
Kojto	107:4f6c30876dfa	8987	*/
Kojto	107:4f6c30876dfa	8988
Kojto	107:4f6c30876dfa	8989	/***************************** ADC Instances ******************************/
Kojto	107:4f6c30876dfa	8990	#define IS_ADC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == ADC1) \|\| \
Kojto	107:4f6c30876dfa	8991	((__INSTANCE__) == ADC2) \|\| \
Kojto	107:4f6c30876dfa	8992	((__INSTANCE__) == ADC3))
Kojto	107:4f6c30876dfa	8993
Kojto	107:4f6c30876dfa	8994	/***************************** CAN Instances ******************************/
Kojto	107:4f6c30876dfa	8995	#define IS_CAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == CAN1) \|\| \
Kojto	122:f9eeca106725	8996	((__INSTANCE__) == CAN2))
Kojto	107:4f6c30876dfa	8997	/***************************** CRC Instances ******************************/
Kojto	107:4f6c30876dfa	8998	#define IS_CRC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CRC)
Kojto	107:4f6c30876dfa	8999
Kojto	107:4f6c30876dfa	9000	/***************************** DAC Instances ******************************/
Kojto	107:4f6c30876dfa	9001	#define IS_DAC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DAC)
Kojto	107:4f6c30876dfa	9002
Kojto	107:4f6c30876dfa	9003	/***************************** DCMI Instances *****************************/
Kojto	107:4f6c30876dfa	9004	#define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
Kojto	107:4f6c30876dfa	9005
Kojto	116:c0f6e94411f5	9006
Kojto	107:4f6c30876dfa	9007	/***************************** DMA2D Instances *****************************/
Kojto	107:4f6c30876dfa	9008	#define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
Kojto	107:4f6c30876dfa	9009
Kojto	107:4f6c30876dfa	9010	/****************************** DMA Instances *****************************/
Kojto	107:4f6c30876dfa	9011	#define IS_DMA_STREAM_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == DMA1_Stream0) \|\| \
Kojto	107:4f6c30876dfa	9012	((__INSTANCE__) == DMA1_Stream1) \|\| \
Kojto	107:4f6c30876dfa	9013	((__INSTANCE__) == DMA1_Stream2) \|\| \
Kojto	107:4f6c30876dfa	9014	((__INSTANCE__) == DMA1_Stream3) \|\| \
Kojto	107:4f6c30876dfa	9015	((__INSTANCE__) == DMA1_Stream4) \|\| \
Kojto	107:4f6c30876dfa	9016	((__INSTANCE__) == DMA1_Stream5) \|\| \
Kojto	107:4f6c30876dfa	9017	((__INSTANCE__) == DMA1_Stream6) \|\| \
Kojto	107:4f6c30876dfa	9018	((__INSTANCE__) == DMA1_Stream7) \|\| \
Kojto	107:4f6c30876dfa	9019	((__INSTANCE__) == DMA2_Stream0) \|\| \
Kojto	107:4f6c30876dfa	9020	((__INSTANCE__) == DMA2_Stream1) \|\| \
Kojto	107:4f6c30876dfa	9021	((__INSTANCE__) == DMA2_Stream2) \|\| \
Kojto	107:4f6c30876dfa	9022	((__INSTANCE__) == DMA2_Stream3) \|\| \
Kojto	107:4f6c30876dfa	9023	((__INSTANCE__) == DMA2_Stream4) \|\| \
Kojto	107:4f6c30876dfa	9024	((__INSTANCE__) == DMA2_Stream5) \|\| \
Kojto	107:4f6c30876dfa	9025	((__INSTANCE__) == DMA2_Stream6) \|\| \
Kojto	107:4f6c30876dfa	9026	((__INSTANCE__) == DMA2_Stream7))
Kojto	107:4f6c30876dfa	9027
Kojto	107:4f6c30876dfa	9028	/***************************** GPIO Instances *****************************/
Kojto	107:4f6c30876dfa	9029	#define IS_GPIO_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) \|\| \
Kojto	107:4f6c30876dfa	9030	((__INSTANCE__) == GPIOB) \|\| \
Kojto	107:4f6c30876dfa	9031	((__INSTANCE__) == GPIOC) \|\| \
Kojto	107:4f6c30876dfa	9032	((__INSTANCE__) == GPIOD) \|\| \
Kojto	107:4f6c30876dfa	9033	((__INSTANCE__) == GPIOE) \|\| \
Kojto	107:4f6c30876dfa	9034	((__INSTANCE__) == GPIOF) \|\| \
Kojto	107:4f6c30876dfa	9035	((__INSTANCE__) == GPIOG) \|\| \
Kojto	107:4f6c30876dfa	9036	((__INSTANCE__) == GPIOH) \|\| \
Kojto	107:4f6c30876dfa	9037	((__INSTANCE__) == GPIOI) \|\| \
Kojto	107:4f6c30876dfa	9038	((__INSTANCE__) == GPIOJ) \|\| \
Kojto	107:4f6c30876dfa	9039	((__INSTANCE__) == GPIOK))
Kojto	107:4f6c30876dfa	9040
Kojto	107:4f6c30876dfa	9041	#define IS_GPIO_AF_INSTANCE(__INSTANCE__) (((__INSTANCE__) == GPIOA) \|\| \
Kojto	107:4f6c30876dfa	9042	((__INSTANCE__) == GPIOB) \|\| \
Kojto	107:4f6c30876dfa	9043	((__INSTANCE__) == GPIOC) \|\| \
Kojto	107:4f6c30876dfa	9044	((__INSTANCE__) == GPIOD) \|\| \
Kojto	107:4f6c30876dfa	9045	((__INSTANCE__) == GPIOE) \|\| \
Kojto	107:4f6c30876dfa	9046	((__INSTANCE__) == GPIOF) \|\| \
Kojto	107:4f6c30876dfa	9047	((__INSTANCE__) == GPIOG) \|\| \
Kojto	107:4f6c30876dfa	9048	((__INSTANCE__) == GPIOH) \|\| \
Kojto	107:4f6c30876dfa	9049	((__INSTANCE__) == GPIOI) \|\| \
Kojto	107:4f6c30876dfa	9050	((__INSTANCE__) == GPIOJ) \|\| \
Kojto	107:4f6c30876dfa	9051	((__INSTANCE__) == GPIOK))
Kojto	107:4f6c30876dfa	9052
Kojto	107:4f6c30876dfa	9053	/**************************** CEC Instances *******************************/
Kojto	107:4f6c30876dfa	9054	#define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
Kojto	107:4f6c30876dfa	9055
Kojto	107:4f6c30876dfa	9056	/**************************** QSPI Instances *******************************/
Kojto	107:4f6c30876dfa	9057	#define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
Kojto	107:4f6c30876dfa	9058
Kojto	107:4f6c30876dfa	9059
Kojto	107:4f6c30876dfa	9060	/****************************** I2C Instances *****************************/
Kojto	107:4f6c30876dfa	9061	#define IS_I2C_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == I2C1) \|\| \
Kojto	107:4f6c30876dfa	9062	((__INSTANCE__) == I2C2) \|\| \
Kojto	107:4f6c30876dfa	9063	((__INSTANCE__) == I2C3) \|\| \
Kojto	107:4f6c30876dfa	9064	((__INSTANCE__) == I2C4))
Kojto	107:4f6c30876dfa	9065
Kojto	107:4f6c30876dfa	9066	/****************************** I2S Instances *****************************/
Kojto	107:4f6c30876dfa	9067	#define IS_I2S_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) \|\| \
Kojto	107:4f6c30876dfa	9068	((__INSTANCE__) == SPI2) \|\| \
Kojto	107:4f6c30876dfa	9069	((__INSTANCE__) == SPI3))
Kojto	107:4f6c30876dfa	9070
Kojto	107:4f6c30876dfa	9071	/***************************** LPTIM Instances ******************************/
Kojto	107:4f6c30876dfa	9072	#define IS_LPTIM_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LPTIM1)
Kojto	107:4f6c30876dfa	9073
Kojto	107:4f6c30876dfa	9074	/**************************** LTDC Instances ******************************/
Kojto	107:4f6c30876dfa	9075	#define IS_LTDC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == LTDC)
Kojto	107:4f6c30876dfa	9076
Kojto	116:c0f6e94411f5	9077
Kojto	122:f9eeca106725	9078
Kojto	107:4f6c30876dfa	9079	/***************************** RNG Instances ******************************/
Kojto	107:4f6c30876dfa	9080	#define IS_RNG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RNG)
Kojto	107:4f6c30876dfa	9081
Kojto	107:4f6c30876dfa	9082	/**************************** RTC Instances *******************************/
Kojto	107:4f6c30876dfa	9083	#define IS_RTC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == RTC)
Kojto	107:4f6c30876dfa	9084
Kojto	107:4f6c30876dfa	9085	/***************************** SAI Instances ******************************/
Kojto	122:f9eeca106725	9086	#define IS_SAI_ALL_INSTANCE(__PERIPH__) (((__PERIPH__) == SAI1_Block_A) \|\| \
Kojto	122:f9eeca106725	9087	((__PERIPH__) == SAI1_Block_B) \|\| \
Kojto	122:f9eeca106725	9088	((__PERIPH__) == SAI2_Block_A) \|\| \
Kojto	122:f9eeca106725	9089	((__PERIPH__) == SAI2_Block_B))
Kojto	122:f9eeca106725	9090	/* Legacy define */
Kojto	122:f9eeca106725	9091	#define IS_SAI_BLOCK_PERIPH IS_SAI_ALL_INSTANCE
Kojto	107:4f6c30876dfa	9092
Kojto	107:4f6c30876dfa	9093	/****************************** SDMMC Instances *****************************/
Kojto	107:4f6c30876dfa	9094	#define IS_SDMMC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SDMMC1)
Kojto	107:4f6c30876dfa	9095
Kojto	107:4f6c30876dfa	9096	/**************************** SPDIFRX Instances *******************************/
Kojto	107:4f6c30876dfa	9097	#define IS_SPDIFRX_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == SPDIFRX)
Kojto	107:4f6c30876dfa	9098
Kojto	107:4f6c30876dfa	9099	/****************************** SPI Instances *****************************/
Kojto	107:4f6c30876dfa	9100	#define IS_SPI_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == SPI1) \|\| \
Kojto	107:4f6c30876dfa	9101	((__INSTANCE__) == SPI2) \|\| \
Kojto	107:4f6c30876dfa	9102	((__INSTANCE__) == SPI3) \|\| \
Kojto	107:4f6c30876dfa	9103	((__INSTANCE__) == SPI4) \|\| \
Kojto	107:4f6c30876dfa	9104	((__INSTANCE__) == SPI5) \|\| \
Kojto	107:4f6c30876dfa	9105	((__INSTANCE__) == SPI6))
Kojto	107:4f6c30876dfa	9106
Kojto	107:4f6c30876dfa	9107	/**************** TIM Instances : All supported instances *****************/
Kojto	107:4f6c30876dfa	9108	#define IS_TIM_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9109	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9110	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9111	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9112	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9113	((__INSTANCE__) == TIM6) \|\| \
Kojto	107:4f6c30876dfa	9114	((__INSTANCE__) == TIM7) \|\| \
Kojto	107:4f6c30876dfa	9115	((__INSTANCE__) == TIM8) \|\| \
Kojto	107:4f6c30876dfa	9116	((__INSTANCE__) == TIM9) \|\| \
Kojto	107:4f6c30876dfa	9117	((__INSTANCE__) == TIM10) \|\| \
Kojto	107:4f6c30876dfa	9118	((__INSTANCE__) == TIM11) \|\| \
Kojto	107:4f6c30876dfa	9119	((__INSTANCE__) == TIM12) \|\| \
Kojto	107:4f6c30876dfa	9120	((__INSTANCE__) == TIM13) \|\| \
Kojto	107:4f6c30876dfa	9121	((__INSTANCE__) == TIM14))
Kojto	107:4f6c30876dfa	9122
Kojto	107:4f6c30876dfa	9123	/*********** TIM Instances : at least 1 capture/compare channel ***********/
Kojto	107:4f6c30876dfa	9124	#define IS_TIM_CC1_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9125	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9126	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9127	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9128	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9129	((__INSTANCE__) == TIM8) \|\| \
Kojto	107:4f6c30876dfa	9130	((__INSTANCE__) == TIM9) \|\| \
Kojto	107:4f6c30876dfa	9131	((__INSTANCE__) == TIM10) \|\| \
Kojto	107:4f6c30876dfa	9132	((__INSTANCE__) == TIM11) \|\| \
Kojto	107:4f6c30876dfa	9133	((__INSTANCE__) == TIM12) \|\| \
Kojto	107:4f6c30876dfa	9134	((__INSTANCE__) == TIM13) \|\| \
Kojto	107:4f6c30876dfa	9135	((__INSTANCE__) == TIM14))
Kojto	107:4f6c30876dfa	9136
Kojto	107:4f6c30876dfa	9137	/********** TIM Instances : at least 2 capture/compare channels ***********/
Kojto	107:4f6c30876dfa	9138	#define IS_TIM_CC2_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9139	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9140	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9141	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9142	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9143	((__INSTANCE__) == TIM8) \|\| \
Kojto	107:4f6c30876dfa	9144	((__INSTANCE__) == TIM9) \|\| \
Kojto	107:4f6c30876dfa	9145	((__INSTANCE__) == TIM12))
Kojto	107:4f6c30876dfa	9146
Kojto	107:4f6c30876dfa	9147	/********** TIM Instances : at least 3 capture/compare channels ***********/
Kojto	107:4f6c30876dfa	9148	#define IS_TIM_CC3_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9149	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9150	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9151	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9152	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9153	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9154
Kojto	107:4f6c30876dfa	9155	/********** TIM Instances : at least 4 capture/compare channels ***********/
Kojto	107:4f6c30876dfa	9156	#define IS_TIM_CC4_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9157	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9158	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9159	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9160	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9161	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9162
Kojto	107:4f6c30876dfa	9163	/**************** TIM Instances : supporting combined 3-phase PWM mode ****/
Kojto	107:4f6c30876dfa	9164	#define IS_TIM_COMBINED3PHASEPWM_INSTANCE(__INSTANCE__) \
Kojto	107:4f6c30876dfa	9165	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9166	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9167
Kojto	107:4f6c30876dfa	9168	/**************** TIM Instances : supporting OCxREF clear *****************/
Kojto	107:4f6c30876dfa	9169	#define IS_TIM_OCXREF_CLEAR_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9170	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9171	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9172	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9173	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9174	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9175
Kojto	107:4f6c30876dfa	9176	/****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
Kojto	107:4f6c30876dfa	9177	#define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9178	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9179	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9180	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9181	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9182	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9183	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9184
Kojto	107:4f6c30876dfa	9185	/**************** TIM Instances : supporting internal trigger inputs(ITRX) *****/
Kojto	107:4f6c30876dfa	9186	#define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9187	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9188	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9189	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9190	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9191	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9192	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9193	/**************** TIM Instances : at least 5 capture/compare channels *****/
Kojto	107:4f6c30876dfa	9194	#define IS_TIM_CC5_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9195	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9196	((__INSTANCE__) == TIM8) )
Kojto	107:4f6c30876dfa	9197
Kojto	107:4f6c30876dfa	9198	/**************** TIM Instances : at least 6 capture/compare channels *****/
Kojto	107:4f6c30876dfa	9199	#define IS_TIM_CC6_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9200	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9201	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9202
Kojto	107:4f6c30876dfa	9203
Kojto	107:4f6c30876dfa	9204	/****************** TIM Instances : Advanced-control timers ***************/
Kojto	107:4f6c30876dfa	9205	#define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9206	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9207
Kojto	107:4f6c30876dfa	9208	/**************** TIM Instances : supporting 2 break inputs ***************/
Kojto	107:4f6c30876dfa	9209	#define IS_TIM_BREAK_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9210	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9211	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9212
Kojto	107:4f6c30876dfa	9213	/***************** TIM Instances : Timer input XOR function ***************/
Kojto	107:4f6c30876dfa	9214	#define IS_TIM_XOR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9215	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9216	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9217	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9218	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9219	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9220
Kojto	107:4f6c30876dfa	9221	/**************** TIM Instances : DMA requests generation (UDE) ***********/
Kojto	107:4f6c30876dfa	9222	#define IS_TIM_DMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9223	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9224	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9225	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9226	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9227	((__INSTANCE__) == TIM6) \|\| \
Kojto	107:4f6c30876dfa	9228	((__INSTANCE__) == TIM7) \|\| \
Kojto	107:4f6c30876dfa	9229	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9230
Kojto	107:4f6c30876dfa	9231	/********** TIM Instances : DMA requests generation (CCxDE) ***************/
Kojto	107:4f6c30876dfa	9232	#define IS_TIM_DMA_CC_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9233	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9234	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9235	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9236	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9237	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9238
Kojto	107:4f6c30876dfa	9239	/********** TIM Instances : DMA requests generation (COMDE) ***************/
Kojto	107:4f6c30876dfa	9240	#define IS_TIM_CCDMA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9241	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9242	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9243	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9244	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9245	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9246
Kojto	107:4f6c30876dfa	9247	/****************** TIM Instances : DMA burst feature *********************/
Kojto	107:4f6c30876dfa	9248	#define IS_TIM_DMABURST_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9249	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9250	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9251	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9252	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9253	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9254
Kojto	107:4f6c30876dfa	9255	/**** TIM Instances : master mode available (TIMx_CR2.MMS available )******/
Kojto	107:4f6c30876dfa	9256	#define IS_TIM_MASTER_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9257	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9258	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9259	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9260	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9261	((__INSTANCE__) == TIM6) \|\| \
Kojto	107:4f6c30876dfa	9262	((__INSTANCE__) == TIM7) \|\| \
Kojto	107:4f6c30876dfa	9263	((__INSTANCE__) == TIM8) \|\| \
Kojto	107:4f6c30876dfa	9264	((__INSTANCE__) == TIM13) \|\| \
Kojto	107:4f6c30876dfa	9265	((__INSTANCE__) == TIM14))
Kojto	107:4f6c30876dfa	9266
Kojto	107:4f6c30876dfa	9267	/********* TIM Instances : Slave mode available (TIMx_SMCR available )*****/
Kojto	107:4f6c30876dfa	9268	#define IS_TIM_SLAVE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9269	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9270	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9271	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9272	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9273	((__INSTANCE__) == TIM8) \|\| \
Kojto	107:4f6c30876dfa	9274	((__INSTANCE__) == TIM9) \|\| \
Kojto	107:4f6c30876dfa	9275	((__INSTANCE__) == TIM12))
Kojto	107:4f6c30876dfa	9276
Kojto	107:4f6c30876dfa	9277	/******************** TIM Instances : 32 bit Counter **********************/
Kojto	107:4f6c30876dfa	9278	#define IS_TIM_32B_COUNTER_INSTANCE(__INSTANCE__)(((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9279	((__INSTANCE__) == TIM5))
Kojto	107:4f6c30876dfa	9280
Kojto	107:4f6c30876dfa	9281	/*************** TIM Instances : external trigger input available **********/
Kojto	107:4f6c30876dfa	9282	#define IS_TIM_ETR_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9283	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9284	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9285	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9286	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9287	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9288
Kojto	107:4f6c30876dfa	9289	/**************** TIM Instances : remapping capability ********************/
Kojto	107:4f6c30876dfa	9290	#define IS_TIM_REMAP_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9291	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9292	((__INSTANCE__) == TIM11))
Kojto	107:4f6c30876dfa	9293
Kojto	107:4f6c30876dfa	9294	/***************** TIM Instances : output(s) available ********************/
Kojto	107:4f6c30876dfa	9295	#define IS_TIM_CCX_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto	107:4f6c30876dfa	9296	((((__INSTANCE__) == TIM1) && \
Kojto	107:4f6c30876dfa	9297	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9298	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9299	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	107:4f6c30876dfa	9300	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	107:4f6c30876dfa	9301	\|\| \
Kojto	107:4f6c30876dfa	9302	(((__INSTANCE__) == TIM2) && \
Kojto	107:4f6c30876dfa	9303	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9304	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9305	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	107:4f6c30876dfa	9306	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	107:4f6c30876dfa	9307	\|\| \
Kojto	107:4f6c30876dfa	9308	(((__INSTANCE__) == TIM3) && \
Kojto	107:4f6c30876dfa	9309	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9310	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9311	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	107:4f6c30876dfa	9312	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	107:4f6c30876dfa	9313	\|\| \
Kojto	107:4f6c30876dfa	9314	(((__INSTANCE__) == TIM4) && \
Kojto	107:4f6c30876dfa	9315	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9316	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9317	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	107:4f6c30876dfa	9318	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	107:4f6c30876dfa	9319	\|\| \
Kojto	107:4f6c30876dfa	9320	(((__INSTANCE__) == TIM5) && \
Kojto	107:4f6c30876dfa	9321	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9322	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9323	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	107:4f6c30876dfa	9324	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	107:4f6c30876dfa	9325	\|\| \
Kojto	107:4f6c30876dfa	9326	(((__INSTANCE__) == TIM8) && \
Kojto	107:4f6c30876dfa	9327	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9328	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9329	((__CHANNEL__) == TIM_CHANNEL_3) \|\| \
Kojto	107:4f6c30876dfa	9330	((__CHANNEL__) == TIM_CHANNEL_4))) \
Kojto	107:4f6c30876dfa	9331	\|\| \
Kojto	107:4f6c30876dfa	9332	(((__INSTANCE__) == TIM9) && \
Kojto	107:4f6c30876dfa	9333	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9334	((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto	107:4f6c30876dfa	9335	\|\| \
Kojto	107:4f6c30876dfa	9336	(((__INSTANCE__) == TIM10) && \
Kojto	107:4f6c30876dfa	9337	(((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto	107:4f6c30876dfa	9338	\|\| \
Kojto	107:4f6c30876dfa	9339	(((__INSTANCE__) == TIM11) && \
Kojto	107:4f6c30876dfa	9340	(((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto	107:4f6c30876dfa	9341	\|\| \
Kojto	107:4f6c30876dfa	9342	(((__INSTANCE__) == TIM12) && \
Kojto	107:4f6c30876dfa	9343	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9344	((__CHANNEL__) == TIM_CHANNEL_2))) \
Kojto	107:4f6c30876dfa	9345	\|\| \
Kojto	107:4f6c30876dfa	9346	(((__INSTANCE__) == TIM13) && \
Kojto	107:4f6c30876dfa	9347	(((__CHANNEL__) == TIM_CHANNEL_1))) \
Kojto	107:4f6c30876dfa	9348	\|\| \
Kojto	107:4f6c30876dfa	9349	(((__INSTANCE__) == TIM14) && \
Kojto	107:4f6c30876dfa	9350	(((__CHANNEL__) == TIM_CHANNEL_1))))
Kojto	107:4f6c30876dfa	9351
Kojto	107:4f6c30876dfa	9352	/********** TIM Instances : complementary output(s) available *************/
Kojto	107:4f6c30876dfa	9353	#define IS_TIM_CCXN_INSTANCE(__INSTANCE__, __CHANNEL__) \
Kojto	107:4f6c30876dfa	9354	((((__INSTANCE__) == TIM1) && \
Kojto	107:4f6c30876dfa	9355	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9356	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9357	((__CHANNEL__) == TIM_CHANNEL_3))) \
Kojto	107:4f6c30876dfa	9358	\|\| \
Kojto	107:4f6c30876dfa	9359	(((__INSTANCE__) == TIM8) && \
Kojto	107:4f6c30876dfa	9360	(((__CHANNEL__) == TIM_CHANNEL_1) \|\| \
Kojto	107:4f6c30876dfa	9361	((__CHANNEL__) == TIM_CHANNEL_2) \|\| \
Kojto	107:4f6c30876dfa	9362	((__CHANNEL__) == TIM_CHANNEL_3))))
Kojto	107:4f6c30876dfa	9363
Kojto	107:4f6c30876dfa	9364	/**************** TIM Instances : supporting ADC triggering through TRGO2 */
Kojto	107:4f6c30876dfa	9365	#define IS_TIM_TRGO2_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9366	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9367	((__INSTANCE__) == TIM8) )
Kojto	107:4f6c30876dfa	9368
Kojto	107:4f6c30876dfa	9369	/**************** TIM Instances : supporting synchronization **************/
Kojto	107:4f6c30876dfa	9370	#define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
Kojto	107:4f6c30876dfa	9371	(((__INSTANCE__) == TIM1) \|\| \
Kojto	107:4f6c30876dfa	9372	((__INSTANCE__) == TIM2) \|\| \
Kojto	107:4f6c30876dfa	9373	((__INSTANCE__) == TIM3) \|\| \
Kojto	107:4f6c30876dfa	9374	((__INSTANCE__) == TIM4) \|\| \
Kojto	107:4f6c30876dfa	9375	((__INSTANCE__) == TIM5) \|\| \
Kojto	107:4f6c30876dfa	9376	((__INSTANCE__) == TIM6) \|\| \
Kojto	107:4f6c30876dfa	9377	((__INSTANCE__) == TIM7) \|\| \
Kojto	107:4f6c30876dfa	9378	((__INSTANCE__) == TIM8))
Kojto	107:4f6c30876dfa	9379
Kojto	107:4f6c30876dfa	9380	/****************** USART Instances : Synchronous mode ********************/
Kojto	107:4f6c30876dfa	9381	#define IS_USART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	107:4f6c30876dfa	9382	((__INSTANCE__) == USART2) \|\| \
Kojto	107:4f6c30876dfa	9383	((__INSTANCE__) == USART3) \|\| \
Kojto	107:4f6c30876dfa	9384	((__INSTANCE__) == USART6))
Kojto	107:4f6c30876dfa	9385
Kojto	107:4f6c30876dfa	9386	/****************** UART Instances : Asynchronous mode ********************/
Kojto	107:4f6c30876dfa	9387	#define IS_UART_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	107:4f6c30876dfa	9388	((__INSTANCE__) == USART2) \|\| \
Kojto	107:4f6c30876dfa	9389	((__INSTANCE__) == USART3) \|\| \
Kojto	107:4f6c30876dfa	9390	((__INSTANCE__) == UART4) \|\| \
Kojto	107:4f6c30876dfa	9391	((__INSTANCE__) == UART5) \|\| \
Kojto	107:4f6c30876dfa	9392	((__INSTANCE__) == USART6) \|\| \
Kojto	107:4f6c30876dfa	9393	((__INSTANCE__) == UART7) \|\| \
Kojto	107:4f6c30876dfa	9394	((__INSTANCE__) == UART8))
Kojto	107:4f6c30876dfa	9395
Kojto	122:f9eeca106725	9396	/**************** UART Instances : Driver Enable ***************/
Kojto	122:f9eeca106725	9397	#define IS_UART_DRIVER_ENABLE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	122:f9eeca106725	9398	((__INSTANCE__) == USART2) \|\| \
Kojto	122:f9eeca106725	9399	((__INSTANCE__) == USART3) \|\| \
Kojto	122:f9eeca106725	9400	((__INSTANCE__) == UART4) \|\| \
Kojto	122:f9eeca106725	9401	((__INSTANCE__) == UART5) \|\| \
Kojto	122:f9eeca106725	9402	((__INSTANCE__) == USART6) \|\| \
Kojto	122:f9eeca106725	9403	((__INSTANCE__) == UART7) \|\| \
Kojto	122:f9eeca106725	9404	((__INSTANCE__) == UART8))
Kojto	122:f9eeca106725	9405
Kojto	107:4f6c30876dfa	9406	/**************** UART Instances : Hardware Flow control ******************/
Kojto	107:4f6c30876dfa	9407	#define IS_UART_HWFLOW_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	107:4f6c30876dfa	9408	((__INSTANCE__) == USART2) \|\| \
Kojto	107:4f6c30876dfa	9409	((__INSTANCE__) == USART3) \|\| \
Kojto	107:4f6c30876dfa	9410	((__INSTANCE__) == UART4) \|\| \
Kojto	107:4f6c30876dfa	9411	((__INSTANCE__) == UART5) \|\| \
Kojto	107:4f6c30876dfa	9412	((__INSTANCE__) == USART6) \|\| \
Kojto	107:4f6c30876dfa	9413	((__INSTANCE__) == UART7) \|\| \
Kojto	107:4f6c30876dfa	9414	((__INSTANCE__) == UART8))
Kojto	107:4f6c30876dfa	9415
Kojto	107:4f6c30876dfa	9416	/******************* UART Instances : Smart card mode *********************/
Kojto	107:4f6c30876dfa	9417	#define IS_SMARTCARD_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	107:4f6c30876dfa	9418	((__INSTANCE__) == USART2) \|\| \
Kojto	107:4f6c30876dfa	9419	((__INSTANCE__) == USART3) \|\| \
Kojto	107:4f6c30876dfa	9420	((__INSTANCE__) == USART6))
Kojto	107:4f6c30876dfa	9421
Kojto	107:4f6c30876dfa	9422	/********************* UART Instances : IRDA mode *************************/
Kojto	107:4f6c30876dfa	9423	#define IS_IRDA_INSTANCE(__INSTANCE__) (((__INSTANCE__) == USART1) \|\| \
Kojto	107:4f6c30876dfa	9424	((__INSTANCE__) == USART2) \|\| \
Kojto	107:4f6c30876dfa	9425	((__INSTANCE__) == USART3) \|\| \
Kojto	107:4f6c30876dfa	9426	((__INSTANCE__) == UART4) \|\| \
Kojto	107:4f6c30876dfa	9427	((__INSTANCE__) == UART5) \|\| \
Kojto	107:4f6c30876dfa	9428	((__INSTANCE__) == USART6) \|\| \
Kojto	107:4f6c30876dfa	9429	((__INSTANCE__) == UART7) \|\| \
Kojto	107:4f6c30876dfa	9430	((__INSTANCE__) == UART8))
Kojto	107:4f6c30876dfa	9431
Kojto	107:4f6c30876dfa	9432	/**************************** IWDG Instances ******************************/
Kojto	107:4f6c30876dfa	9433	#define IS_IWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == IWDG)
Kojto	107:4f6c30876dfa	9434
Kojto	107:4f6c30876dfa	9435	/**************************** WWDG Instances ******************************/
Kojto	107:4f6c30876dfa	9436	#define IS_WWDG_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == WWDG)
Kojto	107:4f6c30876dfa	9437
Kojto	107:4f6c30876dfa	9438
Kojto	107:4f6c30876dfa	9439	/******************************************************************************/
Kojto	107:4f6c30876dfa	9440	/* For a painless codes migration between the STM32F7xx device product */
Kojto	107:4f6c30876dfa	9441	/* lines, the aliases defined below are put in place to overcome the */
Kojto	107:4f6c30876dfa	9442	/* differences in the interrupt handlers and IRQn definitions. */
Kojto	107:4f6c30876dfa	9443	/* No need to update developed interrupt code when moving across */
Kojto	107:4f6c30876dfa	9444	/* product lines within the same STM32F7 Family */
Kojto	107:4f6c30876dfa	9445	/******************************************************************************/
Kojto	107:4f6c30876dfa	9446
Kojto	107:4f6c30876dfa	9447	/* Aliases for __IRQn */
Kojto	107:4f6c30876dfa	9448	#define HASH_RNG_IRQn RNG_IRQn
Kojto	107:4f6c30876dfa	9449
Kojto	107:4f6c30876dfa	9450	/* Aliases for __IRQHandler */
Kojto	107:4f6c30876dfa	9451	#define HASH_RNG_IRQHandler RNG_IRQHandler
Kojto	107:4f6c30876dfa	9452
Kojto	107:4f6c30876dfa	9453	/**
Kojto	107:4f6c30876dfa	9454	* @}
Kojto	107:4f6c30876dfa	9455	*/
Kojto	107:4f6c30876dfa	9456
Kojto	107:4f6c30876dfa	9457	/**
Kojto	107:4f6c30876dfa	9458	* @}
Kojto	107:4f6c30876dfa	9459	*/
Kojto	107:4f6c30876dfa	9460
Kojto	107:4f6c30876dfa	9461	/**
Kojto	107:4f6c30876dfa	9462	* @}
Kojto	107:4f6c30876dfa	9463	*/
Kojto	107:4f6c30876dfa	9464
Kojto	107:4f6c30876dfa	9465	#ifdef __cplusplus
Kojto	107:4f6c30876dfa	9466	}
Kojto	107:4f6c30876dfa	9467	#endif /* __cplusplus */
Kojto	107:4f6c30876dfa	9468
Kojto	107:4f6c30876dfa	9469	#endif /* __STM32F746xx_H */
Kojto	107:4f6c30876dfa	9470
Kojto	107:4f6c30876dfa	9471
Kojto	107:4f6c30876dfa	9472	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/