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TARGET_NUCLEO_L011K4/TARGET_STM/TARGET_STM32L0/device/stm32l0xx_hal_tim.h@157:e7ca05fa8600, 2017-11-09 (annotated)
- Committer:
- AnnaBridge
- Date:
- Thu Nov 09 11:14:10 2017 +0000
- Revision:
- 157:e7ca05fa8600
- Child:
- 167:84c0a372a020
Release 155 of the mbed library.
Who changed what in which revision?
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AnnaBridge | 157:e7ca05fa8600 | 1 | /** |
AnnaBridge | 157:e7ca05fa8600 | 2 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 3 | * @file stm32l0xx_hal_tim.h |
AnnaBridge | 157:e7ca05fa8600 | 4 | * @author MCD Application Team |
AnnaBridge | 157:e7ca05fa8600 | 5 | * @version V1.7.0 |
AnnaBridge | 157:e7ca05fa8600 | 6 | * @date 31-May-2016 |
AnnaBridge | 157:e7ca05fa8600 | 7 | * @brief Header file of TIM HAL module. |
AnnaBridge | 157:e7ca05fa8600 | 8 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 9 | * @attention |
AnnaBridge | 157:e7ca05fa8600 | 10 | * |
AnnaBridge | 157:e7ca05fa8600 | 11 | * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> |
AnnaBridge | 157:e7ca05fa8600 | 12 | * |
AnnaBridge | 157:e7ca05fa8600 | 13 | * Redistribution and use in source and binary forms, with or without modification, |
AnnaBridge | 157:e7ca05fa8600 | 14 | * are permitted provided that the following conditions are met: |
AnnaBridge | 157:e7ca05fa8600 | 15 | * 1. Redistributions of source code must retain the above copyright notice, |
AnnaBridge | 157:e7ca05fa8600 | 16 | * this list of conditions and the following disclaimer. |
AnnaBridge | 157:e7ca05fa8600 | 17 | * 2. Redistributions in binary form must reproduce the above copyright notice, |
AnnaBridge | 157:e7ca05fa8600 | 18 | * this list of conditions and the following disclaimer in the documentation |
AnnaBridge | 157:e7ca05fa8600 | 19 | * and/or other materials provided with the distribution. |
AnnaBridge | 157:e7ca05fa8600 | 20 | * 3. Neither the name of STMicroelectronics nor the names of its contributors |
AnnaBridge | 157:e7ca05fa8600 | 21 | * may be used to endorse or promote products derived from this software |
AnnaBridge | 157:e7ca05fa8600 | 22 | * without specific prior written permission. |
AnnaBridge | 157:e7ca05fa8600 | 23 | * |
AnnaBridge | 157:e7ca05fa8600 | 24 | * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
AnnaBridge | 157:e7ca05fa8600 | 25 | * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
AnnaBridge | 157:e7ca05fa8600 | 26 | * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
AnnaBridge | 157:e7ca05fa8600 | 27 | * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE |
AnnaBridge | 157:e7ca05fa8600 | 28 | * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL |
AnnaBridge | 157:e7ca05fa8600 | 29 | * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
AnnaBridge | 157:e7ca05fa8600 | 30 | * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER |
AnnaBridge | 157:e7ca05fa8600 | 31 | * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, |
AnnaBridge | 157:e7ca05fa8600 | 32 | * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE |
AnnaBridge | 157:e7ca05fa8600 | 33 | * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
AnnaBridge | 157:e7ca05fa8600 | 34 | * |
AnnaBridge | 157:e7ca05fa8600 | 35 | ****************************************************************************** |
AnnaBridge | 157:e7ca05fa8600 | 36 | */ |
AnnaBridge | 157:e7ca05fa8600 | 37 | |
AnnaBridge | 157:e7ca05fa8600 | 38 | /* Define to prevent recursive inclusion -------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 39 | #ifndef __STM32L0xx_HAL_TIM_H |
AnnaBridge | 157:e7ca05fa8600 | 40 | #define __STM32L0xx_HAL_TIM_H |
AnnaBridge | 157:e7ca05fa8600 | 41 | |
AnnaBridge | 157:e7ca05fa8600 | 42 | #ifdef __cplusplus |
AnnaBridge | 157:e7ca05fa8600 | 43 | extern "C" { |
AnnaBridge | 157:e7ca05fa8600 | 44 | #endif |
AnnaBridge | 157:e7ca05fa8600 | 45 | |
AnnaBridge | 157:e7ca05fa8600 | 46 | /* Includes ------------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 47 | #include "stm32l0xx_hal_def.h" |
AnnaBridge | 157:e7ca05fa8600 | 48 | |
AnnaBridge | 157:e7ca05fa8600 | 49 | /** @addtogroup STM32L0xx_HAL_Driver |
AnnaBridge | 157:e7ca05fa8600 | 50 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 51 | */ |
AnnaBridge | 157:e7ca05fa8600 | 52 | |
AnnaBridge | 157:e7ca05fa8600 | 53 | /** @defgroup TIM TIM (Timer) |
AnnaBridge | 157:e7ca05fa8600 | 54 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 55 | */ |
AnnaBridge | 157:e7ca05fa8600 | 56 | |
AnnaBridge | 157:e7ca05fa8600 | 57 | /* Exported types ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 58 | |
AnnaBridge | 157:e7ca05fa8600 | 59 | /** @defgroup TIM_Exported_Types TIM Exported Types |
AnnaBridge | 157:e7ca05fa8600 | 60 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 61 | */ |
AnnaBridge | 157:e7ca05fa8600 | 62 | |
AnnaBridge | 157:e7ca05fa8600 | 63 | /** @defgroup TIM_Base_Configuration TIM base configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 64 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 65 | */ |
AnnaBridge | 157:e7ca05fa8600 | 66 | /** |
AnnaBridge | 157:e7ca05fa8600 | 67 | * @brief TIM Time base Configuration Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 68 | */ |
AnnaBridge | 157:e7ca05fa8600 | 69 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 70 | { |
AnnaBridge | 157:e7ca05fa8600 | 71 | uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock. |
AnnaBridge | 157:e7ca05fa8600 | 72 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 157:e7ca05fa8600 | 73 | |
AnnaBridge | 157:e7ca05fa8600 | 74 | uint32_t CounterMode; /*!< Specifies the counter mode. |
AnnaBridge | 157:e7ca05fa8600 | 75 | This parameter can be a value of @ref TIM_Counter_Mode */ |
AnnaBridge | 157:e7ca05fa8600 | 76 | |
AnnaBridge | 157:e7ca05fa8600 | 77 | uint32_t Period; /*!< Specifies the period value to be loaded into the active |
AnnaBridge | 157:e7ca05fa8600 | 78 | Auto-Reload Register at the next update event. |
AnnaBridge | 157:e7ca05fa8600 | 79 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */ |
AnnaBridge | 157:e7ca05fa8600 | 80 | |
AnnaBridge | 157:e7ca05fa8600 | 81 | uint32_t ClockDivision; /*!< Specifies the clock division. |
AnnaBridge | 157:e7ca05fa8600 | 82 | This parameter can be a value of @ref TIM_ClockDivision */ |
AnnaBridge | 157:e7ca05fa8600 | 83 | } TIM_Base_InitTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 84 | /** |
AnnaBridge | 157:e7ca05fa8600 | 85 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 86 | */ |
AnnaBridge | 157:e7ca05fa8600 | 87 | |
AnnaBridge | 157:e7ca05fa8600 | 88 | /** @defgroup TIM_Output_Configuration TIM output compare configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 89 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 90 | */ |
AnnaBridge | 157:e7ca05fa8600 | 91 | |
AnnaBridge | 157:e7ca05fa8600 | 92 | /** |
AnnaBridge | 157:e7ca05fa8600 | 93 | * @brief TIM Output Compare Configuration Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 94 | */ |
AnnaBridge | 157:e7ca05fa8600 | 95 | |
AnnaBridge | 157:e7ca05fa8600 | 96 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 97 | { |
AnnaBridge | 157:e7ca05fa8600 | 98 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 157:e7ca05fa8600 | 99 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
AnnaBridge | 157:e7ca05fa8600 | 100 | |
AnnaBridge | 157:e7ca05fa8600 | 101 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 157:e7ca05fa8600 | 102 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 157:e7ca05fa8600 | 103 | |
AnnaBridge | 157:e7ca05fa8600 | 104 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 157:e7ca05fa8600 | 105 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 106 | |
AnnaBridge | 157:e7ca05fa8600 | 107 | uint32_t OCFastMode; /*!< Specifies the Fast mode state. |
AnnaBridge | 157:e7ca05fa8600 | 108 | This parameter can be a value of @ref TIM_Output_Fast_State |
AnnaBridge | 157:e7ca05fa8600 | 109 | @note This parameter is valid only in PWM1 and PWM2 mode. */ |
AnnaBridge | 157:e7ca05fa8600 | 110 | |
AnnaBridge | 157:e7ca05fa8600 | 111 | } TIM_OC_InitTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 112 | /** |
AnnaBridge | 157:e7ca05fa8600 | 113 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 114 | */ |
AnnaBridge | 157:e7ca05fa8600 | 115 | |
AnnaBridge | 157:e7ca05fa8600 | 116 | /** @defgroup TIM_OnePulse_Configuration TIM One Pulse configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 117 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 118 | */ |
AnnaBridge | 157:e7ca05fa8600 | 119 | /** |
AnnaBridge | 157:e7ca05fa8600 | 120 | * @brief TIM One Pulse Mode Configuration Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 121 | */ |
AnnaBridge | 157:e7ca05fa8600 | 122 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 123 | { |
AnnaBridge | 157:e7ca05fa8600 | 124 | uint32_t OCMode; /*!< Specifies the TIM mode. |
AnnaBridge | 157:e7ca05fa8600 | 125 | This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */ |
AnnaBridge | 157:e7ca05fa8600 | 126 | |
AnnaBridge | 157:e7ca05fa8600 | 127 | uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register. |
AnnaBridge | 157:e7ca05fa8600 | 128 | This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */ |
AnnaBridge | 157:e7ca05fa8600 | 129 | |
AnnaBridge | 157:e7ca05fa8600 | 130 | uint32_t OCPolarity; /*!< Specifies the output polarity. |
AnnaBridge | 157:e7ca05fa8600 | 131 | This parameter can be a value of @ref TIM_Output_Compare_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 132 | |
AnnaBridge | 157:e7ca05fa8600 | 133 | |
AnnaBridge | 157:e7ca05fa8600 | 134 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 157:e7ca05fa8600 | 135 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 136 | |
AnnaBridge | 157:e7ca05fa8600 | 137 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 157:e7ca05fa8600 | 138 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 157:e7ca05fa8600 | 139 | |
AnnaBridge | 157:e7ca05fa8600 | 140 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 157:e7ca05fa8600 | 141 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 157:e7ca05fa8600 | 142 | } TIM_OnePulse_InitTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 143 | /** |
AnnaBridge | 157:e7ca05fa8600 | 144 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 145 | */ |
AnnaBridge | 157:e7ca05fa8600 | 146 | |
AnnaBridge | 157:e7ca05fa8600 | 147 | /** @defgroup TIM_Input_Capture TIM input capture configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 148 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 149 | */ |
AnnaBridge | 157:e7ca05fa8600 | 150 | /** |
AnnaBridge | 157:e7ca05fa8600 | 151 | * @brief TIM Input Capture Configuration Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 152 | */ |
AnnaBridge | 157:e7ca05fa8600 | 153 | |
AnnaBridge | 157:e7ca05fa8600 | 154 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 155 | { |
AnnaBridge | 157:e7ca05fa8600 | 156 | uint32_t ICPolarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 157:e7ca05fa8600 | 157 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 158 | |
AnnaBridge | 157:e7ca05fa8600 | 159 | uint32_t ICSelection; /*!< Specifies the input. |
AnnaBridge | 157:e7ca05fa8600 | 160 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 157:e7ca05fa8600 | 161 | |
AnnaBridge | 157:e7ca05fa8600 | 162 | uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 157:e7ca05fa8600 | 163 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 157:e7ca05fa8600 | 164 | |
AnnaBridge | 157:e7ca05fa8600 | 165 | uint32_t ICFilter; /*!< Specifies the input capture filter. |
AnnaBridge | 157:e7ca05fa8600 | 166 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 157:e7ca05fa8600 | 167 | } TIM_IC_InitTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 168 | /** |
AnnaBridge | 157:e7ca05fa8600 | 169 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 170 | */ |
AnnaBridge | 157:e7ca05fa8600 | 171 | |
AnnaBridge | 157:e7ca05fa8600 | 172 | /** @defgroup TIM_Encoder TIM encoder configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 173 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 174 | */ |
AnnaBridge | 157:e7ca05fa8600 | 175 | /** |
AnnaBridge | 157:e7ca05fa8600 | 176 | * @brief TIM Encoder Configuration Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 177 | */ |
AnnaBridge | 157:e7ca05fa8600 | 178 | |
AnnaBridge | 157:e7ca05fa8600 | 179 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 180 | { |
AnnaBridge | 157:e7ca05fa8600 | 181 | uint32_t EncoderMode; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 157:e7ca05fa8600 | 182 | This parameter can be a value of @ref TIM_Encoder_Mode */ |
AnnaBridge | 157:e7ca05fa8600 | 183 | |
AnnaBridge | 157:e7ca05fa8600 | 184 | uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 157:e7ca05fa8600 | 185 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 186 | |
AnnaBridge | 157:e7ca05fa8600 | 187 | uint32_t IC1Selection; /*!< Specifies the input. |
AnnaBridge | 157:e7ca05fa8600 | 188 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 157:e7ca05fa8600 | 189 | |
AnnaBridge | 157:e7ca05fa8600 | 190 | uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 157:e7ca05fa8600 | 191 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 157:e7ca05fa8600 | 192 | |
AnnaBridge | 157:e7ca05fa8600 | 193 | uint32_t IC1Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 157:e7ca05fa8600 | 194 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 157:e7ca05fa8600 | 195 | |
AnnaBridge | 157:e7ca05fa8600 | 196 | uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal. |
AnnaBridge | 157:e7ca05fa8600 | 197 | This parameter can be a value of @ref TIM_Input_Capture_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 198 | |
AnnaBridge | 157:e7ca05fa8600 | 199 | uint32_t IC2Selection; /*!< Specifies the input. |
AnnaBridge | 157:e7ca05fa8600 | 200 | This parameter can be a value of @ref TIM_Input_Capture_Selection */ |
AnnaBridge | 157:e7ca05fa8600 | 201 | |
AnnaBridge | 157:e7ca05fa8600 | 202 | uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler. |
AnnaBridge | 157:e7ca05fa8600 | 203 | This parameter can be a value of @ref TIM_Input_Capture_Prescaler */ |
AnnaBridge | 157:e7ca05fa8600 | 204 | |
AnnaBridge | 157:e7ca05fa8600 | 205 | uint32_t IC2Filter; /*!< Specifies the input capture filter. |
AnnaBridge | 157:e7ca05fa8600 | 206 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 157:e7ca05fa8600 | 207 | } TIM_Encoder_InitTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 208 | /** |
AnnaBridge | 157:e7ca05fa8600 | 209 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 210 | */ |
AnnaBridge | 157:e7ca05fa8600 | 211 | |
AnnaBridge | 157:e7ca05fa8600 | 212 | /** @defgroup TIM_Clock_Configuration TIM clock configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 213 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 214 | */ |
AnnaBridge | 157:e7ca05fa8600 | 215 | /** |
AnnaBridge | 157:e7ca05fa8600 | 216 | * @brief Clock Configuration Handle Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 217 | */ |
AnnaBridge | 157:e7ca05fa8600 | 218 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 219 | { |
AnnaBridge | 157:e7ca05fa8600 | 220 | uint32_t ClockSource; /*!< TIM clock sources. |
AnnaBridge | 157:e7ca05fa8600 | 221 | This parameter can be a value of @ref TIM_Clock_Source */ |
AnnaBridge | 157:e7ca05fa8600 | 222 | uint32_t ClockPolarity; /*!< TIM clock polarity. |
AnnaBridge | 157:e7ca05fa8600 | 223 | This parameter can be a value of @ref TIM_Clock_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 224 | uint32_t ClockPrescaler; /*!< TIM clock prescaler. |
AnnaBridge | 157:e7ca05fa8600 | 225 | This parameter can be a value of @ref TIM_Clock_Prescaler */ |
AnnaBridge | 157:e7ca05fa8600 | 226 | uint32_t ClockFilter; /*!< TIM clock filter. |
AnnaBridge | 157:e7ca05fa8600 | 227 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 157:e7ca05fa8600 | 228 | }TIM_ClockConfigTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 229 | /** |
AnnaBridge | 157:e7ca05fa8600 | 230 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 231 | */ |
AnnaBridge | 157:e7ca05fa8600 | 232 | |
AnnaBridge | 157:e7ca05fa8600 | 233 | /** @defgroup TIM_Clear_Input_Configuration TIM clear input configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 234 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 235 | */ |
AnnaBridge | 157:e7ca05fa8600 | 236 | /** |
AnnaBridge | 157:e7ca05fa8600 | 237 | * @brief Clear Input Configuration Handle Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 238 | */ |
AnnaBridge | 157:e7ca05fa8600 | 239 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 240 | { |
AnnaBridge | 157:e7ca05fa8600 | 241 | uint32_t ClearInputState; /*!< TIM clear Input state. |
AnnaBridge | 157:e7ca05fa8600 | 242 | This parameter can be ENABLE or DISABLE */ |
AnnaBridge | 157:e7ca05fa8600 | 243 | uint32_t ClearInputSource; /*!< TIM clear Input sources. |
AnnaBridge | 157:e7ca05fa8600 | 244 | This parameter can be a value of @ref TIM_ClearInput_Source */ |
AnnaBridge | 157:e7ca05fa8600 | 245 | uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity. |
AnnaBridge | 157:e7ca05fa8600 | 246 | This parameter can be a value of @ref TIM_ClearInput_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 247 | uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler. |
AnnaBridge | 157:e7ca05fa8600 | 248 | This parameter can be a value of @ref TIM_ClearInput_Prescaler */ |
AnnaBridge | 157:e7ca05fa8600 | 249 | uint32_t ClearInputFilter; /*!< TIM Clear Input filter. |
AnnaBridge | 157:e7ca05fa8600 | 250 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 157:e7ca05fa8600 | 251 | }TIM_ClearInputConfigTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 252 | /** |
AnnaBridge | 157:e7ca05fa8600 | 253 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 254 | */ |
AnnaBridge | 157:e7ca05fa8600 | 255 | |
AnnaBridge | 157:e7ca05fa8600 | 256 | /** @defgroup TIM_Slave_Configuratio TIM slave configuration structure |
AnnaBridge | 157:e7ca05fa8600 | 257 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 258 | */ |
AnnaBridge | 157:e7ca05fa8600 | 259 | /** |
AnnaBridge | 157:e7ca05fa8600 | 260 | * @brief TIM Slave configuration Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 261 | */ |
AnnaBridge | 157:e7ca05fa8600 | 262 | typedef struct { |
AnnaBridge | 157:e7ca05fa8600 | 263 | uint32_t SlaveMode; /*!< Slave mode selection. |
AnnaBridge | 157:e7ca05fa8600 | 264 | This parameter can be a value of @ref TIM_Slave_Mode */ |
AnnaBridge | 157:e7ca05fa8600 | 265 | uint32_t InputTrigger; /*!< Input Trigger source. |
AnnaBridge | 157:e7ca05fa8600 | 266 | This parameter can be a value of @ref TIM_Trigger_Selection */ |
AnnaBridge | 157:e7ca05fa8600 | 267 | uint32_t TriggerPolarity; /*!< Input Trigger polarity. |
AnnaBridge | 157:e7ca05fa8600 | 268 | This parameter can be a value of @ref TIM_Trigger_Polarity */ |
AnnaBridge | 157:e7ca05fa8600 | 269 | uint32_t TriggerPrescaler; /*!< Input trigger prescaler. |
AnnaBridge | 157:e7ca05fa8600 | 270 | This parameter can be a value of @ref TIM_Trigger_Prescaler */ |
AnnaBridge | 157:e7ca05fa8600 | 271 | uint32_t TriggerFilter; /*!< Input trigger filter. |
AnnaBridge | 157:e7ca05fa8600 | 272 | This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */ |
AnnaBridge | 157:e7ca05fa8600 | 273 | |
AnnaBridge | 157:e7ca05fa8600 | 274 | }TIM_SlaveConfigTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 275 | /** |
AnnaBridge | 157:e7ca05fa8600 | 276 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 277 | */ |
AnnaBridge | 157:e7ca05fa8600 | 278 | |
AnnaBridge | 157:e7ca05fa8600 | 279 | /** @defgroup TIM_State_Definition TIM state definition |
AnnaBridge | 157:e7ca05fa8600 | 280 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 281 | */ |
AnnaBridge | 157:e7ca05fa8600 | 282 | /** |
AnnaBridge | 157:e7ca05fa8600 | 283 | * @brief HAL State structures definition |
AnnaBridge | 157:e7ca05fa8600 | 284 | */ |
AnnaBridge | 157:e7ca05fa8600 | 285 | typedef enum |
AnnaBridge | 157:e7ca05fa8600 | 286 | { |
AnnaBridge | 157:e7ca05fa8600 | 287 | HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */ |
AnnaBridge | 157:e7ca05fa8600 | 288 | HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */ |
AnnaBridge | 157:e7ca05fa8600 | 289 | HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */ |
AnnaBridge | 157:e7ca05fa8600 | 290 | HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */ |
AnnaBridge | 157:e7ca05fa8600 | 291 | HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */ |
AnnaBridge | 157:e7ca05fa8600 | 292 | }HAL_TIM_StateTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 293 | /** |
AnnaBridge | 157:e7ca05fa8600 | 294 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 295 | */ |
AnnaBridge | 157:e7ca05fa8600 | 296 | |
AnnaBridge | 157:e7ca05fa8600 | 297 | /** @defgroup TIM_Active_Channel TIM active channel definition |
AnnaBridge | 157:e7ca05fa8600 | 298 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 299 | */ |
AnnaBridge | 157:e7ca05fa8600 | 300 | /** |
AnnaBridge | 157:e7ca05fa8600 | 301 | * @brief HAL Active channel structures definition |
AnnaBridge | 157:e7ca05fa8600 | 302 | */ |
AnnaBridge | 157:e7ca05fa8600 | 303 | typedef enum |
AnnaBridge | 157:e7ca05fa8600 | 304 | { |
AnnaBridge | 157:e7ca05fa8600 | 305 | HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */ |
AnnaBridge | 157:e7ca05fa8600 | 306 | HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 307 | HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */ |
AnnaBridge | 157:e7ca05fa8600 | 308 | HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 309 | HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */ |
AnnaBridge | 157:e7ca05fa8600 | 310 | }HAL_TIM_ActiveChannel; |
AnnaBridge | 157:e7ca05fa8600 | 311 | /** |
AnnaBridge | 157:e7ca05fa8600 | 312 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 313 | */ |
AnnaBridge | 157:e7ca05fa8600 | 314 | |
AnnaBridge | 157:e7ca05fa8600 | 315 | /** @defgroup TIM_Handle TIM handler |
AnnaBridge | 157:e7ca05fa8600 | 316 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 317 | */ |
AnnaBridge | 157:e7ca05fa8600 | 318 | /** |
AnnaBridge | 157:e7ca05fa8600 | 319 | * @brief TIM Time Base Handle Structure definition |
AnnaBridge | 157:e7ca05fa8600 | 320 | */ |
AnnaBridge | 157:e7ca05fa8600 | 321 | typedef struct |
AnnaBridge | 157:e7ca05fa8600 | 322 | { |
AnnaBridge | 157:e7ca05fa8600 | 323 | TIM_TypeDef *Instance; /*!< Register base address */ |
AnnaBridge | 157:e7ca05fa8600 | 324 | TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */ |
AnnaBridge | 157:e7ca05fa8600 | 325 | HAL_TIM_ActiveChannel Channel; /*!< Active channel */ |
AnnaBridge | 157:e7ca05fa8600 | 326 | DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array |
AnnaBridge | 157:e7ca05fa8600 | 327 | This array is accessed by a @ref DMA_Handle_index */ |
AnnaBridge | 157:e7ca05fa8600 | 328 | HAL_LockTypeDef Lock; /*!< Locking object */ |
AnnaBridge | 157:e7ca05fa8600 | 329 | __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */ |
AnnaBridge | 157:e7ca05fa8600 | 330 | }TIM_HandleTypeDef; |
AnnaBridge | 157:e7ca05fa8600 | 331 | /** |
AnnaBridge | 157:e7ca05fa8600 | 332 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 333 | */ |
AnnaBridge | 157:e7ca05fa8600 | 334 | |
AnnaBridge | 157:e7ca05fa8600 | 335 | /** |
AnnaBridge | 157:e7ca05fa8600 | 336 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 337 | */ |
AnnaBridge | 157:e7ca05fa8600 | 338 | /* Exported constants --------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 339 | /** @defgroup TIM_Exported_Constants TIM Exported Constants |
AnnaBridge | 157:e7ca05fa8600 | 340 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 341 | */ |
AnnaBridge | 157:e7ca05fa8600 | 342 | |
AnnaBridge | 157:e7ca05fa8600 | 343 | |
AnnaBridge | 157:e7ca05fa8600 | 344 | #define IS_TIM_PERIOD(__PERIOD__) ((__PERIOD__) <= 0xFFFFU) |
AnnaBridge | 157:e7ca05fa8600 | 345 | |
AnnaBridge | 157:e7ca05fa8600 | 346 | #define IS_TIM_PRESCALER(__PRESCALER__) ((__PRESCALER__) <= 0xFFFFU) |
AnnaBridge | 157:e7ca05fa8600 | 347 | |
AnnaBridge | 157:e7ca05fa8600 | 348 | |
AnnaBridge | 157:e7ca05fa8600 | 349 | /** @defgroup TIM_Input_Channel_Polarity Input channel polarity |
AnnaBridge | 157:e7ca05fa8600 | 350 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 351 | */ |
AnnaBridge | 157:e7ca05fa8600 | 352 | #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */ |
AnnaBridge | 157:e7ca05fa8600 | 353 | #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */ |
AnnaBridge | 157:e7ca05fa8600 | 354 | #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */ |
AnnaBridge | 157:e7ca05fa8600 | 355 | /** |
AnnaBridge | 157:e7ca05fa8600 | 356 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 357 | */ |
AnnaBridge | 157:e7ca05fa8600 | 358 | |
AnnaBridge | 157:e7ca05fa8600 | 359 | /** @defgroup TIM_ETR_Polarity ETR polarity |
AnnaBridge | 157:e7ca05fa8600 | 360 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 361 | */ |
AnnaBridge | 157:e7ca05fa8600 | 362 | #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */ |
AnnaBridge | 157:e7ca05fa8600 | 363 | #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */ |
AnnaBridge | 157:e7ca05fa8600 | 364 | /** |
AnnaBridge | 157:e7ca05fa8600 | 365 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 366 | */ |
AnnaBridge | 157:e7ca05fa8600 | 367 | |
AnnaBridge | 157:e7ca05fa8600 | 368 | /** @defgroup TIM_ETR_Prescaler ETR prescaler |
AnnaBridge | 157:e7ca05fa8600 | 369 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 370 | */ |
AnnaBridge | 157:e7ca05fa8600 | 371 | #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */ |
AnnaBridge | 157:e7ca05fa8600 | 372 | #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */ |
AnnaBridge | 157:e7ca05fa8600 | 373 | #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */ |
AnnaBridge | 157:e7ca05fa8600 | 374 | #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */ |
AnnaBridge | 157:e7ca05fa8600 | 375 | /** |
AnnaBridge | 157:e7ca05fa8600 | 376 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 377 | */ |
AnnaBridge | 157:e7ca05fa8600 | 378 | |
AnnaBridge | 157:e7ca05fa8600 | 379 | /** @defgroup TIM_Counter_Mode Counter mode |
AnnaBridge | 157:e7ca05fa8600 | 380 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 381 | */ |
AnnaBridge | 157:e7ca05fa8600 | 382 | #define TIM_COUNTERMODE_UP ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 383 | #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR |
AnnaBridge | 157:e7ca05fa8600 | 384 | #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0 |
AnnaBridge | 157:e7ca05fa8600 | 385 | #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1 |
AnnaBridge | 157:e7ca05fa8600 | 386 | #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS |
AnnaBridge | 157:e7ca05fa8600 | 387 | /** |
AnnaBridge | 157:e7ca05fa8600 | 388 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 389 | */ |
AnnaBridge | 157:e7ca05fa8600 | 390 | #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \ |
AnnaBridge | 157:e7ca05fa8600 | 391 | ((__MODE__) == TIM_COUNTERMODE_DOWN) || \ |
AnnaBridge | 157:e7ca05fa8600 | 392 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 393 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 394 | ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3)) |
AnnaBridge | 157:e7ca05fa8600 | 395 | |
AnnaBridge | 157:e7ca05fa8600 | 396 | |
AnnaBridge | 157:e7ca05fa8600 | 397 | |
AnnaBridge | 157:e7ca05fa8600 | 398 | |
AnnaBridge | 157:e7ca05fa8600 | 399 | /** @defgroup TIM_ClockDivision Clock division |
AnnaBridge | 157:e7ca05fa8600 | 400 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 401 | */ |
AnnaBridge | 157:e7ca05fa8600 | 402 | #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 403 | #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0) |
AnnaBridge | 157:e7ca05fa8600 | 404 | #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1) |
AnnaBridge | 157:e7ca05fa8600 | 405 | /** |
AnnaBridge | 157:e7ca05fa8600 | 406 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 407 | */ |
AnnaBridge | 157:e7ca05fa8600 | 408 | #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 409 | ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 410 | ((__DIV__) == TIM_CLOCKDIVISION_DIV4)) |
AnnaBridge | 157:e7ca05fa8600 | 411 | |
AnnaBridge | 157:e7ca05fa8600 | 412 | |
AnnaBridge | 157:e7ca05fa8600 | 413 | /** @defgroup TIM_Output_Compare_and_PWM_modes Output compare and PWM modes |
AnnaBridge | 157:e7ca05fa8600 | 414 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 415 | */ |
AnnaBridge | 157:e7ca05fa8600 | 416 | #define TIM_OCMODE_TIMING ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 417 | #define TIM_OCMODE_ACTIVE (TIM_CCMR1_OC1M_0) |
AnnaBridge | 157:e7ca05fa8600 | 418 | #define TIM_OCMODE_INACTIVE (TIM_CCMR1_OC1M_1) |
AnnaBridge | 157:e7ca05fa8600 | 419 | #define TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_1) |
AnnaBridge | 157:e7ca05fa8600 | 420 | #define TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) |
AnnaBridge | 157:e7ca05fa8600 | 421 | #define TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M) |
AnnaBridge | 157:e7ca05fa8600 | 422 | #define TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) |
AnnaBridge | 157:e7ca05fa8600 | 423 | #define TIM_OCMODE_FORCED_INACTIVE (TIM_CCMR1_OC1M_2) |
AnnaBridge | 157:e7ca05fa8600 | 424 | /** |
AnnaBridge | 157:e7ca05fa8600 | 425 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 426 | */ |
AnnaBridge | 157:e7ca05fa8600 | 427 | |
AnnaBridge | 157:e7ca05fa8600 | 428 | #define IS_TIM_PWM_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_PWM1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 429 | ((__MODE__) == TIM_OCMODE_PWM2)) |
AnnaBridge | 157:e7ca05fa8600 | 430 | |
AnnaBridge | 157:e7ca05fa8600 | 431 | #define IS_TIM_OC_MODE(__MODE__) (((__MODE__) == TIM_OCMODE_TIMING) || \ |
AnnaBridge | 157:e7ca05fa8600 | 432 | ((__MODE__) == TIM_OCMODE_ACTIVE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 433 | ((__MODE__) == TIM_OCMODE_INACTIVE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 434 | ((__MODE__) == TIM_OCMODE_TOGGLE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 435 | ((__MODE__) == TIM_OCMODE_FORCED_ACTIVE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 436 | ((__MODE__) == TIM_OCMODE_FORCED_INACTIVE)) |
AnnaBridge | 157:e7ca05fa8600 | 437 | |
AnnaBridge | 157:e7ca05fa8600 | 438 | |
AnnaBridge | 157:e7ca05fa8600 | 439 | /** @defgroup TIM_Output_Compare_State Output compare state |
AnnaBridge | 157:e7ca05fa8600 | 440 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 441 | */ |
AnnaBridge | 157:e7ca05fa8600 | 442 | #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 443 | #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E) |
AnnaBridge | 157:e7ca05fa8600 | 444 | /** |
AnnaBridge | 157:e7ca05fa8600 | 445 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 446 | */ |
AnnaBridge | 157:e7ca05fa8600 | 447 | |
AnnaBridge | 157:e7ca05fa8600 | 448 | /** @defgroup TIM_Output_Fast_State Output fast state |
AnnaBridge | 157:e7ca05fa8600 | 449 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 450 | */ |
AnnaBridge | 157:e7ca05fa8600 | 451 | #define TIM_OCFAST_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 452 | #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE) |
AnnaBridge | 157:e7ca05fa8600 | 453 | /** |
AnnaBridge | 157:e7ca05fa8600 | 454 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 455 | */ |
AnnaBridge | 157:e7ca05fa8600 | 456 | #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 457 | ((__STATE__) == TIM_OCFAST_ENABLE)) |
AnnaBridge | 157:e7ca05fa8600 | 458 | |
AnnaBridge | 157:e7ca05fa8600 | 459 | /** @defgroup TIM_Output_Compare_N_State Output compare N state |
AnnaBridge | 157:e7ca05fa8600 | 460 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 461 | */ |
AnnaBridge | 157:e7ca05fa8600 | 462 | #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 463 | #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE) |
AnnaBridge | 157:e7ca05fa8600 | 464 | /** |
AnnaBridge | 157:e7ca05fa8600 | 465 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 466 | */ |
AnnaBridge | 157:e7ca05fa8600 | 467 | |
AnnaBridge | 157:e7ca05fa8600 | 468 | /** @defgroup TIM_Output_Compare_Polarity Output compare polarity |
AnnaBridge | 157:e7ca05fa8600 | 469 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 470 | */ |
AnnaBridge | 157:e7ca05fa8600 | 471 | #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 472 | #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P) |
AnnaBridge | 157:e7ca05fa8600 | 473 | /** |
AnnaBridge | 157:e7ca05fa8600 | 474 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 475 | */ |
AnnaBridge | 157:e7ca05fa8600 | 476 | #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \ |
AnnaBridge | 157:e7ca05fa8600 | 477 | ((__POLARITY__) == TIM_OCPOLARITY_LOW)) |
AnnaBridge | 157:e7ca05fa8600 | 478 | |
AnnaBridge | 157:e7ca05fa8600 | 479 | /** @defgroup TIM_Channel TIM channels |
AnnaBridge | 157:e7ca05fa8600 | 480 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 481 | */ |
AnnaBridge | 157:e7ca05fa8600 | 482 | #define TIM_CHANNEL_1 ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 483 | #define TIM_CHANNEL_2 ((uint32_t)0x0004U) |
AnnaBridge | 157:e7ca05fa8600 | 484 | #define TIM_CHANNEL_3 ((uint32_t)0x0008U) |
AnnaBridge | 157:e7ca05fa8600 | 485 | #define TIM_CHANNEL_4 ((uint32_t)0x000CU) |
AnnaBridge | 157:e7ca05fa8600 | 486 | #define TIM_CHANNEL_ALL ((uint32_t)0x0018U) |
AnnaBridge | 157:e7ca05fa8600 | 487 | /** |
AnnaBridge | 157:e7ca05fa8600 | 488 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 489 | */ |
AnnaBridge | 157:e7ca05fa8600 | 490 | |
AnnaBridge | 157:e7ca05fa8600 | 491 | #define IS_TIM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 492 | ((__CHANNEL__) == TIM_CHANNEL_2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 493 | ((__CHANNEL__) == TIM_CHANNEL_3) || \ |
AnnaBridge | 157:e7ca05fa8600 | 494 | ((__CHANNEL__) == TIM_CHANNEL_4) || \ |
AnnaBridge | 157:e7ca05fa8600 | 495 | ((__CHANNEL__) == TIM_CHANNEL_ALL)) |
AnnaBridge | 157:e7ca05fa8600 | 496 | |
AnnaBridge | 157:e7ca05fa8600 | 497 | #define IS_TIM_OPM_CHANNELS(__CHANNEL__) (((__CHANNEL__) == TIM_CHANNEL_1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 498 | ((__CHANNEL__) == TIM_CHANNEL_2)) |
AnnaBridge | 157:e7ca05fa8600 | 499 | |
AnnaBridge | 157:e7ca05fa8600 | 500 | |
AnnaBridge | 157:e7ca05fa8600 | 501 | /** @defgroup TIM_Input_Capture_Polarity Input capture polarity |
AnnaBridge | 157:e7ca05fa8600 | 502 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 503 | */ |
AnnaBridge | 157:e7ca05fa8600 | 504 | #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING |
AnnaBridge | 157:e7ca05fa8600 | 505 | #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING |
AnnaBridge | 157:e7ca05fa8600 | 506 | #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE |
AnnaBridge | 157:e7ca05fa8600 | 507 | /** |
AnnaBridge | 157:e7ca05fa8600 | 508 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 509 | */ |
AnnaBridge | 157:e7ca05fa8600 | 510 | #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \ |
AnnaBridge | 157:e7ca05fa8600 | 511 | ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \ |
AnnaBridge | 157:e7ca05fa8600 | 512 | ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE)) |
AnnaBridge | 157:e7ca05fa8600 | 513 | |
AnnaBridge | 157:e7ca05fa8600 | 514 | |
AnnaBridge | 157:e7ca05fa8600 | 515 | /** @defgroup TIM_Input_Capture_Selection Input capture selection |
AnnaBridge | 157:e7ca05fa8600 | 516 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 517 | */ |
AnnaBridge | 157:e7ca05fa8600 | 518 | #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 157:e7ca05fa8600 | 519 | connected to IC1, IC2, IC3 or IC4, respectively */ |
AnnaBridge | 157:e7ca05fa8600 | 520 | #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be |
AnnaBridge | 157:e7ca05fa8600 | 521 | connected to IC2, IC1, IC4 or IC3, respectively */ |
AnnaBridge | 157:e7ca05fa8600 | 522 | #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */ |
AnnaBridge | 157:e7ca05fa8600 | 523 | |
AnnaBridge | 157:e7ca05fa8600 | 524 | #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \ |
AnnaBridge | 157:e7ca05fa8600 | 525 | ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \ |
AnnaBridge | 157:e7ca05fa8600 | 526 | ((__SELECTION__) == TIM_ICSELECTION_TRC)) |
AnnaBridge | 157:e7ca05fa8600 | 527 | /** |
AnnaBridge | 157:e7ca05fa8600 | 528 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 529 | */ |
AnnaBridge | 157:e7ca05fa8600 | 530 | |
AnnaBridge | 157:e7ca05fa8600 | 531 | /** @defgroup TIM_Input_Capture_Prescaler Input capture prescaler |
AnnaBridge | 157:e7ca05fa8600 | 532 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 533 | */ |
AnnaBridge | 157:e7ca05fa8600 | 534 | #define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */ |
AnnaBridge | 157:e7ca05fa8600 | 535 | #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */ |
AnnaBridge | 157:e7ca05fa8600 | 536 | #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */ |
AnnaBridge | 157:e7ca05fa8600 | 537 | #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */ |
AnnaBridge | 157:e7ca05fa8600 | 538 | /** |
AnnaBridge | 157:e7ca05fa8600 | 539 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 540 | */ |
AnnaBridge | 157:e7ca05fa8600 | 541 | #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 542 | ((__PRESCALER__) == TIM_ICPSC_DIV2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 543 | ((__PRESCALER__) == TIM_ICPSC_DIV4) || \ |
AnnaBridge | 157:e7ca05fa8600 | 544 | ((__PRESCALER__) == TIM_ICPSC_DIV8)) |
AnnaBridge | 157:e7ca05fa8600 | 545 | |
AnnaBridge | 157:e7ca05fa8600 | 546 | /** @defgroup TIM_One_Pulse_Mode One pulse mode |
AnnaBridge | 157:e7ca05fa8600 | 547 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 548 | */ |
AnnaBridge | 157:e7ca05fa8600 | 549 | #define TIM_OPMODE_SINGLE (TIM_CR1_OPM) |
AnnaBridge | 157:e7ca05fa8600 | 550 | #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 551 | /** |
AnnaBridge | 157:e7ca05fa8600 | 552 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 553 | */ |
AnnaBridge | 157:e7ca05fa8600 | 554 | #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 555 | ((__MODE__) == TIM_OPMODE_REPETITIVE)) |
AnnaBridge | 157:e7ca05fa8600 | 556 | |
AnnaBridge | 157:e7ca05fa8600 | 557 | /** @defgroup TIM_Encoder_Mode Encoder_Mode |
AnnaBridge | 157:e7ca05fa8600 | 558 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 559 | */ |
AnnaBridge | 157:e7ca05fa8600 | 560 | #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0) |
AnnaBridge | 157:e7ca05fa8600 | 561 | #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1) |
AnnaBridge | 157:e7ca05fa8600 | 562 | #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) |
AnnaBridge | 157:e7ca05fa8600 | 563 | /** |
AnnaBridge | 157:e7ca05fa8600 | 564 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 565 | */ |
AnnaBridge | 157:e7ca05fa8600 | 566 | #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 567 | ((__MODE__) == TIM_ENCODERMODE_TI2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 568 | ((__MODE__) == TIM_ENCODERMODE_TI12)) |
AnnaBridge | 157:e7ca05fa8600 | 569 | |
AnnaBridge | 157:e7ca05fa8600 | 570 | /** @defgroup TIM_Interrupt_definition Interrupt definition |
AnnaBridge | 157:e7ca05fa8600 | 571 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 572 | */ |
AnnaBridge | 157:e7ca05fa8600 | 573 | #define TIM_IT_UPDATE (TIM_DIER_UIE) |
AnnaBridge | 157:e7ca05fa8600 | 574 | #define TIM_IT_CC1 (TIM_DIER_CC1IE) |
AnnaBridge | 157:e7ca05fa8600 | 575 | #define TIM_IT_CC2 (TIM_DIER_CC2IE) |
AnnaBridge | 157:e7ca05fa8600 | 576 | #define TIM_IT_CC3 (TIM_DIER_CC3IE) |
AnnaBridge | 157:e7ca05fa8600 | 577 | #define TIM_IT_CC4 (TIM_DIER_CC4IE) |
AnnaBridge | 157:e7ca05fa8600 | 578 | #define TIM_IT_TRIGGER (TIM_DIER_TIE) |
AnnaBridge | 157:e7ca05fa8600 | 579 | /** |
AnnaBridge | 157:e7ca05fa8600 | 580 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 581 | */ |
AnnaBridge | 157:e7ca05fa8600 | 582 | |
AnnaBridge | 157:e7ca05fa8600 | 583 | /** @defgroup TIM_DMA_sources DMA sources |
AnnaBridge | 157:e7ca05fa8600 | 584 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 585 | */ |
AnnaBridge | 157:e7ca05fa8600 | 586 | #define TIM_DMA_UPDATE (TIM_DIER_UDE) |
AnnaBridge | 157:e7ca05fa8600 | 587 | #define TIM_DMA_CC1 (TIM_DIER_CC1DE) |
AnnaBridge | 157:e7ca05fa8600 | 588 | #define TIM_DMA_CC2 (TIM_DIER_CC2DE) |
AnnaBridge | 157:e7ca05fa8600 | 589 | #define TIM_DMA_CC3 (TIM_DIER_CC3DE) |
AnnaBridge | 157:e7ca05fa8600 | 590 | #define TIM_DMA_CC4 (TIM_DIER_CC4DE) |
AnnaBridge | 157:e7ca05fa8600 | 591 | #define TIM_DMA_TRIGGER (TIM_DIER_TDE) |
AnnaBridge | 157:e7ca05fa8600 | 592 | /** |
AnnaBridge | 157:e7ca05fa8600 | 593 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 594 | */ |
AnnaBridge | 157:e7ca05fa8600 | 595 | #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFA0FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
AnnaBridge | 157:e7ca05fa8600 | 596 | |
AnnaBridge | 157:e7ca05fa8600 | 597 | |
AnnaBridge | 157:e7ca05fa8600 | 598 | |
AnnaBridge | 157:e7ca05fa8600 | 599 | /** @defgroup TIM_Event_Source Event sources |
AnnaBridge | 157:e7ca05fa8600 | 600 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 601 | */ |
AnnaBridge | 157:e7ca05fa8600 | 602 | #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG |
AnnaBridge | 157:e7ca05fa8600 | 603 | #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G |
AnnaBridge | 157:e7ca05fa8600 | 604 | #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G |
AnnaBridge | 157:e7ca05fa8600 | 605 | #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G |
AnnaBridge | 157:e7ca05fa8600 | 606 | #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G |
AnnaBridge | 157:e7ca05fa8600 | 607 | #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG |
AnnaBridge | 157:e7ca05fa8600 | 608 | /** |
AnnaBridge | 157:e7ca05fa8600 | 609 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 610 | */ |
AnnaBridge | 157:e7ca05fa8600 | 611 | #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFFA0U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U)) |
AnnaBridge | 157:e7ca05fa8600 | 612 | |
AnnaBridge | 157:e7ca05fa8600 | 613 | |
AnnaBridge | 157:e7ca05fa8600 | 614 | /** @defgroup TIM_Flag_definition Flag definition |
AnnaBridge | 157:e7ca05fa8600 | 615 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 616 | */ |
AnnaBridge | 157:e7ca05fa8600 | 617 | #define TIM_FLAG_UPDATE (TIM_SR_UIF) |
AnnaBridge | 157:e7ca05fa8600 | 618 | #define TIM_FLAG_CC1 (TIM_SR_CC1IF) |
AnnaBridge | 157:e7ca05fa8600 | 619 | #define TIM_FLAG_CC2 (TIM_SR_CC2IF) |
AnnaBridge | 157:e7ca05fa8600 | 620 | #define TIM_FLAG_CC3 (TIM_SR_CC3IF) |
AnnaBridge | 157:e7ca05fa8600 | 621 | #define TIM_FLAG_CC4 (TIM_SR_CC4IF) |
AnnaBridge | 157:e7ca05fa8600 | 622 | #define TIM_FLAG_TRIGGER (TIM_SR_TIF) |
AnnaBridge | 157:e7ca05fa8600 | 623 | #define TIM_FLAG_CC1OF (TIM_SR_CC1OF) |
AnnaBridge | 157:e7ca05fa8600 | 624 | #define TIM_FLAG_CC2OF (TIM_SR_CC2OF) |
AnnaBridge | 157:e7ca05fa8600 | 625 | #define TIM_FLAG_CC3OF (TIM_SR_CC3OF) |
AnnaBridge | 157:e7ca05fa8600 | 626 | #define TIM_FLAG_CC4OF (TIM_SR_CC4OF) |
AnnaBridge | 157:e7ca05fa8600 | 627 | /** |
AnnaBridge | 157:e7ca05fa8600 | 628 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 629 | */ |
AnnaBridge | 157:e7ca05fa8600 | 630 | |
AnnaBridge | 157:e7ca05fa8600 | 631 | /** @defgroup TIM_Clock_Source Clock source |
AnnaBridge | 157:e7ca05fa8600 | 632 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 633 | */ |
AnnaBridge | 157:e7ca05fa8600 | 634 | #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1) |
AnnaBridge | 157:e7ca05fa8600 | 635 | #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0) |
AnnaBridge | 157:e7ca05fa8600 | 636 | #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 637 | #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0) |
AnnaBridge | 157:e7ca05fa8600 | 638 | #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1) |
AnnaBridge | 157:e7ca05fa8600 | 639 | #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) |
AnnaBridge | 157:e7ca05fa8600 | 640 | #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2) |
AnnaBridge | 157:e7ca05fa8600 | 641 | #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2) |
AnnaBridge | 157:e7ca05fa8600 | 642 | #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2) |
AnnaBridge | 157:e7ca05fa8600 | 643 | #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS) |
AnnaBridge | 157:e7ca05fa8600 | 644 | /** |
AnnaBridge | 157:e7ca05fa8600 | 645 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 646 | */ |
AnnaBridge | 157:e7ca05fa8600 | 647 | |
AnnaBridge | 157:e7ca05fa8600 | 648 | #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \ |
AnnaBridge | 157:e7ca05fa8600 | 649 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 650 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \ |
AnnaBridge | 157:e7ca05fa8600 | 651 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 652 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 653 | ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \ |
AnnaBridge | 157:e7ca05fa8600 | 654 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \ |
AnnaBridge | 157:e7ca05fa8600 | 655 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 656 | ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 657 | ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1)) |
AnnaBridge | 157:e7ca05fa8600 | 658 | |
AnnaBridge | 157:e7ca05fa8600 | 659 | |
AnnaBridge | 157:e7ca05fa8600 | 660 | /** @defgroup TIM_Clock_Polarity Clock polarity |
AnnaBridge | 157:e7ca05fa8600 | 661 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 662 | */ |
AnnaBridge | 157:e7ca05fa8600 | 663 | #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 157:e7ca05fa8600 | 664 | #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */ |
AnnaBridge | 157:e7ca05fa8600 | 665 | #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 157:e7ca05fa8600 | 666 | #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */ |
AnnaBridge | 157:e7ca05fa8600 | 667 | #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */ |
AnnaBridge | 157:e7ca05fa8600 | 668 | /** |
AnnaBridge | 157:e7ca05fa8600 | 669 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 670 | */ |
AnnaBridge | 157:e7ca05fa8600 | 671 | #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \ |
AnnaBridge | 157:e7ca05fa8600 | 672 | ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \ |
AnnaBridge | 157:e7ca05fa8600 | 673 | ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \ |
AnnaBridge | 157:e7ca05fa8600 | 674 | ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \ |
AnnaBridge | 157:e7ca05fa8600 | 675 | ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE)) |
AnnaBridge | 157:e7ca05fa8600 | 676 | |
AnnaBridge | 157:e7ca05fa8600 | 677 | /** @defgroup TIM_Clock_Prescaler Clock prescaler |
AnnaBridge | 157:e7ca05fa8600 | 678 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 679 | */ |
AnnaBridge | 157:e7ca05fa8600 | 680 | #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 157:e7ca05fa8600 | 681 | #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 682 | #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 683 | #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 684 | /** |
AnnaBridge | 157:e7ca05fa8600 | 685 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 686 | */ |
AnnaBridge | 157:e7ca05fa8600 | 687 | #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 688 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 689 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \ |
AnnaBridge | 157:e7ca05fa8600 | 690 | ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8)) |
AnnaBridge | 157:e7ca05fa8600 | 691 | |
AnnaBridge | 157:e7ca05fa8600 | 692 | |
AnnaBridge | 157:e7ca05fa8600 | 693 | /* Check clock filter */ |
AnnaBridge | 157:e7ca05fa8600 | 694 | #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
AnnaBridge | 157:e7ca05fa8600 | 695 | |
AnnaBridge | 157:e7ca05fa8600 | 696 | /** @defgroup TIM_ClearInput_Source Clear input source |
AnnaBridge | 157:e7ca05fa8600 | 697 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 698 | */ |
AnnaBridge | 157:e7ca05fa8600 | 699 | #define TIM_CLEARINPUTSOURCE_ETR ((uint32_t)0x0001U) |
AnnaBridge | 157:e7ca05fa8600 | 700 | #define TIM_CLEARINPUTSOURCE_NONE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 701 | /** |
AnnaBridge | 157:e7ca05fa8600 | 702 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 703 | */ |
AnnaBridge | 157:e7ca05fa8600 | 704 | |
AnnaBridge | 157:e7ca05fa8600 | 705 | #define IS_TIM_CLEARINPUT_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_CLEARINPUTSOURCE_NONE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 706 | ((__SOURCE__) == TIM_CLEARINPUTSOURCE_ETR)) |
AnnaBridge | 157:e7ca05fa8600 | 707 | |
AnnaBridge | 157:e7ca05fa8600 | 708 | |
AnnaBridge | 157:e7ca05fa8600 | 709 | /** @defgroup TIM_ClearInput_Polarity Clear input polarity |
AnnaBridge | 157:e7ca05fa8600 | 710 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 711 | */ |
AnnaBridge | 157:e7ca05fa8600 | 712 | #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 157:e7ca05fa8600 | 713 | #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */ |
AnnaBridge | 157:e7ca05fa8600 | 714 | /** |
AnnaBridge | 157:e7ca05fa8600 | 715 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 716 | */ |
AnnaBridge | 157:e7ca05fa8600 | 717 | #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \ |
AnnaBridge | 157:e7ca05fa8600 | 718 | ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED)) |
AnnaBridge | 157:e7ca05fa8600 | 719 | |
AnnaBridge | 157:e7ca05fa8600 | 720 | |
AnnaBridge | 157:e7ca05fa8600 | 721 | /** @defgroup TIM_ClearInput_Prescaler Clear input prescaler |
AnnaBridge | 157:e7ca05fa8600 | 722 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 723 | */ |
AnnaBridge | 157:e7ca05fa8600 | 724 | #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 157:e7ca05fa8600 | 725 | #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 726 | #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 727 | #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 728 | /** |
AnnaBridge | 157:e7ca05fa8600 | 729 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 730 | */ |
AnnaBridge | 157:e7ca05fa8600 | 731 | #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 732 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 733 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \ |
AnnaBridge | 157:e7ca05fa8600 | 734 | ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8)) |
AnnaBridge | 157:e7ca05fa8600 | 735 | |
AnnaBridge | 157:e7ca05fa8600 | 736 | |
AnnaBridge | 157:e7ca05fa8600 | 737 | /* Check IC filter */ |
AnnaBridge | 157:e7ca05fa8600 | 738 | #define IS_TIM_CLEARINPUT_FILTER(ICFILTER) ((ICFILTER) <= 0xFU) |
AnnaBridge | 157:e7ca05fa8600 | 739 | |
AnnaBridge | 157:e7ca05fa8600 | 740 | |
AnnaBridge | 157:e7ca05fa8600 | 741 | /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection |
AnnaBridge | 157:e7ca05fa8600 | 742 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 743 | */ |
AnnaBridge | 157:e7ca05fa8600 | 744 | #define TIM_TRGO_RESET ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 745 | #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0) |
AnnaBridge | 157:e7ca05fa8600 | 746 | #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1) |
AnnaBridge | 157:e7ca05fa8600 | 747 | #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 157:e7ca05fa8600 | 748 | #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2) |
AnnaBridge | 157:e7ca05fa8600 | 749 | #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0)) |
AnnaBridge | 157:e7ca05fa8600 | 750 | #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1)) |
AnnaBridge | 157:e7ca05fa8600 | 751 | #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0)) |
AnnaBridge | 157:e7ca05fa8600 | 752 | /** |
AnnaBridge | 157:e7ca05fa8600 | 753 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 754 | */ |
AnnaBridge | 157:e7ca05fa8600 | 755 | #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \ |
AnnaBridge | 157:e7ca05fa8600 | 756 | ((__SOURCE__) == TIM_TRGO_ENABLE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 757 | ((__SOURCE__) == TIM_TRGO_UPDATE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 758 | ((__SOURCE__) == TIM_TRGO_OC1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 759 | ((__SOURCE__) == TIM_TRGO_OC1REF) || \ |
AnnaBridge | 157:e7ca05fa8600 | 760 | ((__SOURCE__) == TIM_TRGO_OC2REF) || \ |
AnnaBridge | 157:e7ca05fa8600 | 761 | ((__SOURCE__) == TIM_TRGO_OC3REF) || \ |
AnnaBridge | 157:e7ca05fa8600 | 762 | ((__SOURCE__) == TIM_TRGO_OC4REF)) |
AnnaBridge | 157:e7ca05fa8600 | 763 | |
AnnaBridge | 157:e7ca05fa8600 | 764 | |
AnnaBridge | 157:e7ca05fa8600 | 765 | |
AnnaBridge | 157:e7ca05fa8600 | 766 | /** @defgroup TIM_Slave_Mode Slave mode |
AnnaBridge | 157:e7ca05fa8600 | 767 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 768 | */ |
AnnaBridge | 157:e7ca05fa8600 | 769 | #define TIM_SLAVEMODE_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 770 | #define TIM_SLAVEMODE_RESET ((uint32_t)0x0004U) |
AnnaBridge | 157:e7ca05fa8600 | 771 | #define TIM_SLAVEMODE_GATED ((uint32_t)0x0005U) |
AnnaBridge | 157:e7ca05fa8600 | 772 | #define TIM_SLAVEMODE_TRIGGER ((uint32_t)0x0006U) |
AnnaBridge | 157:e7ca05fa8600 | 773 | #define TIM_SLAVEMODE_EXTERNAL1 ((uint32_t)0x0007U) |
AnnaBridge | 157:e7ca05fa8600 | 774 | /** |
AnnaBridge | 157:e7ca05fa8600 | 775 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 776 | */ |
AnnaBridge | 157:e7ca05fa8600 | 777 | #define IS_TIM_SLAVE_MODE(__MODE__) (((__MODE__) == TIM_SLAVEMODE_DISABLE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 778 | ((__MODE__) == TIM_SLAVEMODE_GATED) || \ |
AnnaBridge | 157:e7ca05fa8600 | 779 | ((__MODE__) == TIM_SLAVEMODE_RESET) || \ |
AnnaBridge | 157:e7ca05fa8600 | 780 | ((__MODE__) == TIM_SLAVEMODE_TRIGGER) || \ |
AnnaBridge | 157:e7ca05fa8600 | 781 | ((__MODE__) == TIM_SLAVEMODE_EXTERNAL1)) |
AnnaBridge | 157:e7ca05fa8600 | 782 | |
AnnaBridge | 157:e7ca05fa8600 | 783 | /** @defgroup TIM_Master_Slave_Mode Master slave mode |
AnnaBridge | 157:e7ca05fa8600 | 784 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 785 | */ |
AnnaBridge | 157:e7ca05fa8600 | 786 | |
AnnaBridge | 157:e7ca05fa8600 | 787 | #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080U) |
AnnaBridge | 157:e7ca05fa8600 | 788 | #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 789 | /** |
AnnaBridge | 157:e7ca05fa8600 | 790 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 791 | */ |
AnnaBridge | 157:e7ca05fa8600 | 792 | #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \ |
AnnaBridge | 157:e7ca05fa8600 | 793 | ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE)) |
AnnaBridge | 157:e7ca05fa8600 | 794 | |
AnnaBridge | 157:e7ca05fa8600 | 795 | /** @defgroup TIM_Trigger_Selection Trigger selection |
AnnaBridge | 157:e7ca05fa8600 | 796 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 797 | */ |
AnnaBridge | 157:e7ca05fa8600 | 798 | #define TIM_TS_ITR0 ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 799 | #define TIM_TS_ITR1 ((uint32_t)0x0010U) |
AnnaBridge | 157:e7ca05fa8600 | 800 | #define TIM_TS_ITR2 ((uint32_t)0x0020U) |
AnnaBridge | 157:e7ca05fa8600 | 801 | #define TIM_TS_ITR3 ((uint32_t)0x0030U) |
AnnaBridge | 157:e7ca05fa8600 | 802 | #define TIM_TS_TI1F_ED ((uint32_t)0x0040U) |
AnnaBridge | 157:e7ca05fa8600 | 803 | #define TIM_TS_TI1FP1 ((uint32_t)0x0050U) |
AnnaBridge | 157:e7ca05fa8600 | 804 | #define TIM_TS_TI2FP2 ((uint32_t)0x0060U) |
AnnaBridge | 157:e7ca05fa8600 | 805 | #define TIM_TS_ETRF ((uint32_t)0x0070U) |
AnnaBridge | 157:e7ca05fa8600 | 806 | #define TIM_TS_NONE ((uint32_t)0xFFFFU) |
AnnaBridge | 157:e7ca05fa8600 | 807 | /** |
AnnaBridge | 157:e7ca05fa8600 | 808 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 809 | */ |
AnnaBridge | 157:e7ca05fa8600 | 810 | #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
AnnaBridge | 157:e7ca05fa8600 | 811 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 812 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 813 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
AnnaBridge | 157:e7ca05fa8600 | 814 | ((__SELECTION__) == TIM_TS_TI1F_ED) || \ |
AnnaBridge | 157:e7ca05fa8600 | 815 | ((__SELECTION__) == TIM_TS_TI1FP1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 816 | ((__SELECTION__) == TIM_TS_TI2FP2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 817 | ((__SELECTION__) == TIM_TS_ETRF)) |
AnnaBridge | 157:e7ca05fa8600 | 818 | #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \ |
AnnaBridge | 157:e7ca05fa8600 | 819 | ((__SELECTION__) == TIM_TS_ITR1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 820 | ((__SELECTION__) == TIM_TS_ITR2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 821 | ((__SELECTION__) == TIM_TS_ITR3) || \ |
AnnaBridge | 157:e7ca05fa8600 | 822 | ((__SELECTION__) == TIM_TS_NONE)) |
AnnaBridge | 157:e7ca05fa8600 | 823 | |
AnnaBridge | 157:e7ca05fa8600 | 824 | |
AnnaBridge | 157:e7ca05fa8600 | 825 | /** @defgroup TIM_Trigger_Polarity Trigger polarity |
AnnaBridge | 157:e7ca05fa8600 | 826 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 827 | */ |
AnnaBridge | 157:e7ca05fa8600 | 828 | #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 157:e7ca05fa8600 | 829 | #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */ |
AnnaBridge | 157:e7ca05fa8600 | 830 | #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 157:e7ca05fa8600 | 831 | #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 157:e7ca05fa8600 | 832 | #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */ |
AnnaBridge | 157:e7ca05fa8600 | 833 | /** |
AnnaBridge | 157:e7ca05fa8600 | 834 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 835 | */ |
AnnaBridge | 157:e7ca05fa8600 | 836 | #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \ |
AnnaBridge | 157:e7ca05fa8600 | 837 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \ |
AnnaBridge | 157:e7ca05fa8600 | 838 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \ |
AnnaBridge | 157:e7ca05fa8600 | 839 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \ |
AnnaBridge | 157:e7ca05fa8600 | 840 | ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE )) |
AnnaBridge | 157:e7ca05fa8600 | 841 | |
AnnaBridge | 157:e7ca05fa8600 | 842 | |
AnnaBridge | 157:e7ca05fa8600 | 843 | /** @defgroup TIM_Trigger_Prescaler Trigger prescaler |
AnnaBridge | 157:e7ca05fa8600 | 844 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 845 | */ |
AnnaBridge | 157:e7ca05fa8600 | 846 | #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */ |
AnnaBridge | 157:e7ca05fa8600 | 847 | #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 848 | #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 849 | #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */ |
AnnaBridge | 157:e7ca05fa8600 | 850 | /** |
AnnaBridge | 157:e7ca05fa8600 | 851 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 852 | */ |
AnnaBridge | 157:e7ca05fa8600 | 853 | #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 854 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 855 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \ |
AnnaBridge | 157:e7ca05fa8600 | 856 | ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8)) |
AnnaBridge | 157:e7ca05fa8600 | 857 | |
AnnaBridge | 157:e7ca05fa8600 | 858 | |
AnnaBridge | 157:e7ca05fa8600 | 859 | /* Check trigger filter */ |
AnnaBridge | 157:e7ca05fa8600 | 860 | #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
AnnaBridge | 157:e7ca05fa8600 | 861 | |
AnnaBridge | 157:e7ca05fa8600 | 862 | |
AnnaBridge | 157:e7ca05fa8600 | 863 | /** @defgroup TIM_TI1_Selection TI1 selection |
AnnaBridge | 157:e7ca05fa8600 | 864 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 865 | */ |
AnnaBridge | 157:e7ca05fa8600 | 866 | #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 867 | #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S) |
AnnaBridge | 157:e7ca05fa8600 | 868 | /** |
AnnaBridge | 157:e7ca05fa8600 | 869 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 870 | */ |
AnnaBridge | 157:e7ca05fa8600 | 871 | #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 872 | ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION)) |
AnnaBridge | 157:e7ca05fa8600 | 873 | |
AnnaBridge | 157:e7ca05fa8600 | 874 | |
AnnaBridge | 157:e7ca05fa8600 | 875 | /** @defgroup TIM_DMA_Base_address DMA base address |
AnnaBridge | 157:e7ca05fa8600 | 876 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 877 | */ |
AnnaBridge | 157:e7ca05fa8600 | 878 | #define TIM_DMABASE_CR1 (0x00000000U) |
AnnaBridge | 157:e7ca05fa8600 | 879 | #define TIM_DMABASE_CR2 (0x00000001U) |
AnnaBridge | 157:e7ca05fa8600 | 880 | #define TIM_DMABASE_SMCR (0x00000002U) |
AnnaBridge | 157:e7ca05fa8600 | 881 | #define TIM_DMABASE_DIER (0x00000003U) |
AnnaBridge | 157:e7ca05fa8600 | 882 | #define TIM_DMABASE_SR (0x00000004U) |
AnnaBridge | 157:e7ca05fa8600 | 883 | #define TIM_DMABASE_EGR (0x00000005U) |
AnnaBridge | 157:e7ca05fa8600 | 884 | #define TIM_DMABASE_CCMR1 (0x00000006U) |
AnnaBridge | 157:e7ca05fa8600 | 885 | #define TIM_DMABASE_CCMR2 (0x00000007U) |
AnnaBridge | 157:e7ca05fa8600 | 886 | #define TIM_DMABASE_CCER (0x00000008U) |
AnnaBridge | 157:e7ca05fa8600 | 887 | #define TIM_DMABASE_CNT (0x00000009U) |
AnnaBridge | 157:e7ca05fa8600 | 888 | #define TIM_DMABASE_PSC (0x0000000AU) |
AnnaBridge | 157:e7ca05fa8600 | 889 | #define TIM_DMABASE_ARR (0x0000000BU) |
AnnaBridge | 157:e7ca05fa8600 | 890 | #define TIM_DMABASE_CCR1 (0x0000000DU) |
AnnaBridge | 157:e7ca05fa8600 | 891 | #define TIM_DMABASE_CCR2 (0x0000000EU) |
AnnaBridge | 157:e7ca05fa8600 | 892 | #define TIM_DMABASE_CCR3 (0x0000000FU) |
AnnaBridge | 157:e7ca05fa8600 | 893 | #define TIM_DMABASE_CCR4 (0x00000010U) |
AnnaBridge | 157:e7ca05fa8600 | 894 | #define TIM_DMABASE_DCR (0x00000012U) |
AnnaBridge | 157:e7ca05fa8600 | 895 | #define TIM_DMABASE_OR (0x00000013U) |
AnnaBridge | 157:e7ca05fa8600 | 896 | /** |
AnnaBridge | 157:e7ca05fa8600 | 897 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 898 | */ |
AnnaBridge | 157:e7ca05fa8600 | 899 | #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 900 | ((__BASE__) == TIM_DMABASE_CR2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 901 | ((__BASE__) == TIM_DMABASE_SMCR) || \ |
AnnaBridge | 157:e7ca05fa8600 | 902 | ((__BASE__) == TIM_DMABASE_DIER) || \ |
AnnaBridge | 157:e7ca05fa8600 | 903 | ((__BASE__) == TIM_DMABASE_SR) || \ |
AnnaBridge | 157:e7ca05fa8600 | 904 | ((__BASE__) == TIM_DMABASE_EGR) || \ |
AnnaBridge | 157:e7ca05fa8600 | 905 | ((__BASE__) == TIM_DMABASE_CCMR1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 906 | ((__BASE__) == TIM_DMABASE_CCMR2 ) || \ |
AnnaBridge | 157:e7ca05fa8600 | 907 | ((__BASE__) == TIM_DMABASE_CCER) || \ |
AnnaBridge | 157:e7ca05fa8600 | 908 | ((__BASE__) == TIM_DMABASE_CNT) || \ |
AnnaBridge | 157:e7ca05fa8600 | 909 | ((__BASE__) == TIM_DMABASE_PSC) || \ |
AnnaBridge | 157:e7ca05fa8600 | 910 | ((__BASE__) == TIM_DMABASE_ARR) || \ |
AnnaBridge | 157:e7ca05fa8600 | 911 | ((__BASE__) == TIM_DMABASE_CCR1) || \ |
AnnaBridge | 157:e7ca05fa8600 | 912 | ((__BASE__) == TIM_DMABASE_CCR2) || \ |
AnnaBridge | 157:e7ca05fa8600 | 913 | ((__BASE__) == TIM_DMABASE_CCR3) || \ |
AnnaBridge | 157:e7ca05fa8600 | 914 | ((__BASE__) == TIM_DMABASE_CCR4) || \ |
AnnaBridge | 157:e7ca05fa8600 | 915 | ((__BASE__) == TIM_DMABASE_DCR) || \ |
AnnaBridge | 157:e7ca05fa8600 | 916 | ((__BASE__) == TIM_DMABASE_OR)) |
AnnaBridge | 157:e7ca05fa8600 | 917 | |
AnnaBridge | 157:e7ca05fa8600 | 918 | |
AnnaBridge | 157:e7ca05fa8600 | 919 | /** @defgroup TIM_DMA_Burst_Length DMA burst length |
AnnaBridge | 157:e7ca05fa8600 | 920 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 921 | */ |
AnnaBridge | 157:e7ca05fa8600 | 922 | #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U) |
AnnaBridge | 157:e7ca05fa8600 | 923 | #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U) |
AnnaBridge | 157:e7ca05fa8600 | 924 | #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U) |
AnnaBridge | 157:e7ca05fa8600 | 925 | #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U) |
AnnaBridge | 157:e7ca05fa8600 | 926 | #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U) |
AnnaBridge | 157:e7ca05fa8600 | 927 | #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U) |
AnnaBridge | 157:e7ca05fa8600 | 928 | #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U) |
AnnaBridge | 157:e7ca05fa8600 | 929 | #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U) |
AnnaBridge | 157:e7ca05fa8600 | 930 | #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U) |
AnnaBridge | 157:e7ca05fa8600 | 931 | #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U) |
AnnaBridge | 157:e7ca05fa8600 | 932 | #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U) |
AnnaBridge | 157:e7ca05fa8600 | 933 | #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U) |
AnnaBridge | 157:e7ca05fa8600 | 934 | #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U) |
AnnaBridge | 157:e7ca05fa8600 | 935 | #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U) |
AnnaBridge | 157:e7ca05fa8600 | 936 | #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U) |
AnnaBridge | 157:e7ca05fa8600 | 937 | #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U) |
AnnaBridge | 157:e7ca05fa8600 | 938 | #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U) |
AnnaBridge | 157:e7ca05fa8600 | 939 | #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U) |
AnnaBridge | 157:e7ca05fa8600 | 940 | /** |
AnnaBridge | 157:e7ca05fa8600 | 941 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 942 | */ |
AnnaBridge | 157:e7ca05fa8600 | 943 | #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER ) || \ |
AnnaBridge | 157:e7ca05fa8600 | 944 | ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 945 | ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 946 | ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 947 | ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 948 | ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 949 | ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 950 | ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 951 | ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS ) || \ |
AnnaBridge | 157:e7ca05fa8600 | 952 | ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 953 | ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS ) || \ |
AnnaBridge | 157:e7ca05fa8600 | 954 | ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 955 | ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 956 | ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 957 | ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 958 | ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 959 | ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \ |
AnnaBridge | 157:e7ca05fa8600 | 960 | ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS )) |
AnnaBridge | 157:e7ca05fa8600 | 961 | |
AnnaBridge | 157:e7ca05fa8600 | 962 | |
AnnaBridge | 157:e7ca05fa8600 | 963 | /* Check IC filter */ |
AnnaBridge | 157:e7ca05fa8600 | 964 | #define IS_TIM_IC_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xFU) |
AnnaBridge | 157:e7ca05fa8600 | 965 | |
AnnaBridge | 157:e7ca05fa8600 | 966 | /** @defgroup DMA_Handle_index DMA handle index |
AnnaBridge | 157:e7ca05fa8600 | 967 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 968 | */ |
AnnaBridge | 157:e7ca05fa8600 | 969 | #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */ |
AnnaBridge | 157:e7ca05fa8600 | 970 | #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */ |
AnnaBridge | 157:e7ca05fa8600 | 971 | #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */ |
AnnaBridge | 157:e7ca05fa8600 | 972 | #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */ |
AnnaBridge | 157:e7ca05fa8600 | 973 | #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */ |
AnnaBridge | 157:e7ca05fa8600 | 974 | #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Trigger DMA requests */ |
AnnaBridge | 157:e7ca05fa8600 | 975 | /** |
AnnaBridge | 157:e7ca05fa8600 | 976 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 977 | */ |
AnnaBridge | 157:e7ca05fa8600 | 978 | |
AnnaBridge | 157:e7ca05fa8600 | 979 | /** @defgroup Channel_CC_State Channel state |
AnnaBridge | 157:e7ca05fa8600 | 980 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 981 | */ |
AnnaBridge | 157:e7ca05fa8600 | 982 | #define TIM_CCx_ENABLE ((uint32_t)0x0001U) |
AnnaBridge | 157:e7ca05fa8600 | 983 | #define TIM_CCx_DISABLE ((uint32_t)0x0000U) |
AnnaBridge | 157:e7ca05fa8600 | 984 | /** |
AnnaBridge | 157:e7ca05fa8600 | 985 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 986 | */ |
AnnaBridge | 157:e7ca05fa8600 | 987 | |
AnnaBridge | 157:e7ca05fa8600 | 988 | /** |
AnnaBridge | 157:e7ca05fa8600 | 989 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 990 | */ |
AnnaBridge | 157:e7ca05fa8600 | 991 | |
AnnaBridge | 157:e7ca05fa8600 | 992 | /* Exported macro ------------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 993 | /** @defgroup TIM_Exported_Macro TIM Exported Macro |
AnnaBridge | 157:e7ca05fa8600 | 994 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 995 | */ |
AnnaBridge | 157:e7ca05fa8600 | 996 | |
AnnaBridge | 157:e7ca05fa8600 | 997 | /** @brief Reset UART handle state |
AnnaBridge | 157:e7ca05fa8600 | 998 | * @param __HANDLE__ : TIM handle |
AnnaBridge | 157:e7ca05fa8600 | 999 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1000 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1001 | #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET) |
AnnaBridge | 157:e7ca05fa8600 | 1002 | |
AnnaBridge | 157:e7ca05fa8600 | 1003 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1004 | * @brief Enable the TIM peripheral. |
AnnaBridge | 157:e7ca05fa8600 | 1005 | * @param __HANDLE__ : TIM handle |
AnnaBridge | 157:e7ca05fa8600 | 1006 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1007 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1008 | #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN)) |
AnnaBridge | 157:e7ca05fa8600 | 1009 | |
AnnaBridge | 157:e7ca05fa8600 | 1010 | /* The counter of a timer instance is disabled only if all the CCx channels have |
AnnaBridge | 157:e7ca05fa8600 | 1011 | been disabled */ |
AnnaBridge | 157:e7ca05fa8600 | 1012 | #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E)) |
AnnaBridge | 157:e7ca05fa8600 | 1013 | |
AnnaBridge | 157:e7ca05fa8600 | 1014 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1015 | * @brief Disable the TIM peripheral. |
AnnaBridge | 157:e7ca05fa8600 | 1016 | * @param __HANDLE__ : TIM handle |
AnnaBridge | 157:e7ca05fa8600 | 1017 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1018 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1019 | #define __HAL_TIM_DISABLE(__HANDLE__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1020 | do { \ |
AnnaBridge | 157:e7ca05fa8600 | 1021 | if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0U) \ |
AnnaBridge | 157:e7ca05fa8600 | 1022 | { \ |
AnnaBridge | 157:e7ca05fa8600 | 1023 | (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \ |
AnnaBridge | 157:e7ca05fa8600 | 1024 | } \ |
AnnaBridge | 157:e7ca05fa8600 | 1025 | } while(0) |
AnnaBridge | 157:e7ca05fa8600 | 1026 | |
AnnaBridge | 157:e7ca05fa8600 | 1027 | #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__)) |
AnnaBridge | 157:e7ca05fa8600 | 1028 | #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__)) |
AnnaBridge | 157:e7ca05fa8600 | 1029 | #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__)) |
AnnaBridge | 157:e7ca05fa8600 | 1030 | #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__)) |
AnnaBridge | 157:e7ca05fa8600 | 1031 | #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__)) |
AnnaBridge | 157:e7ca05fa8600 | 1032 | #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__)) |
AnnaBridge | 157:e7ca05fa8600 | 1033 | |
AnnaBridge | 157:e7ca05fa8600 | 1034 | #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) |
AnnaBridge | 157:e7ca05fa8600 | 1035 | #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__)) |
AnnaBridge | 157:e7ca05fa8600 | 1036 | |
AnnaBridge | 157:e7ca05fa8600 | 1037 | #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR)) |
AnnaBridge | 157:e7ca05fa8600 | 1038 | #define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__)) |
AnnaBridge | 157:e7ca05fa8600 | 1039 | |
AnnaBridge | 157:e7ca05fa8600 | 1040 | #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1041 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1042 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8U)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1043 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1044 | ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8))) |
AnnaBridge | 157:e7ca05fa8600 | 1045 | |
AnnaBridge | 157:e7ca05fa8600 | 1046 | #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1047 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1048 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1049 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1050 | ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC)) |
AnnaBridge | 157:e7ca05fa8600 | 1051 | |
AnnaBridge | 157:e7ca05fa8600 | 1052 | #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1053 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1054 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4U)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1055 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8U)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1056 | ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12U) & TIM_CCER_CC4P))) |
AnnaBridge | 157:e7ca05fa8600 | 1057 | |
AnnaBridge | 157:e7ca05fa8600 | 1058 | #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1059 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1060 | ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1061 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1062 | ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P)) |
AnnaBridge | 157:e7ca05fa8600 | 1063 | |
AnnaBridge | 157:e7ca05fa8600 | 1064 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1065 | * @brief Sets the TIM Capture Compare Register value on runtime without |
AnnaBridge | 157:e7ca05fa8600 | 1066 | * calling another time ConfigChannel function. |
AnnaBridge | 157:e7ca05fa8600 | 1067 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1068 | * @param __CHANNEL__ : TIM Channels to be configured. |
AnnaBridge | 157:e7ca05fa8600 | 1069 | * This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1070 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 157:e7ca05fa8600 | 1071 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 157:e7ca05fa8600 | 1072 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 157:e7ca05fa8600 | 1073 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 157:e7ca05fa8600 | 1074 | * @param __COMPARE__: specifies the Capture Compare register new value. |
AnnaBridge | 157:e7ca05fa8600 | 1075 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1076 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1077 | #define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1078 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U)) = (__COMPARE__)) |
AnnaBridge | 157:e7ca05fa8600 | 1079 | |
AnnaBridge | 157:e7ca05fa8600 | 1080 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1081 | * @brief Gets the TIM Capture Compare Register value on runtime |
AnnaBridge | 157:e7ca05fa8600 | 1082 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1083 | * @param __CHANNEL__ : TIM Channel associated with the capture compare register |
AnnaBridge | 157:e7ca05fa8600 | 1084 | * This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1085 | * @arg TIM_CHANNEL_1: get capture/compare 1 register value |
AnnaBridge | 157:e7ca05fa8600 | 1086 | * @arg TIM_CHANNEL_2: get capture/compare 2 register value |
AnnaBridge | 157:e7ca05fa8600 | 1087 | * @arg TIM_CHANNEL_3: get capture/compare 3 register value |
AnnaBridge | 157:e7ca05fa8600 | 1088 | * @arg TIM_CHANNEL_4: get capture/compare 4 register value |
AnnaBridge | 157:e7ca05fa8600 | 1089 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1090 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1091 | #define __HAL_TIM_GET_COMPARE(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1092 | (*(__IO uint32_t *)(&((__HANDLE__)->Instance->CCR1) + ((__CHANNEL__) >> 2U))) |
AnnaBridge | 157:e7ca05fa8600 | 1093 | |
AnnaBridge | 157:e7ca05fa8600 | 1094 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1095 | * @brief Sets the TIM Counter Register value on runtime. |
AnnaBridge | 157:e7ca05fa8600 | 1096 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1097 | * @param __COUNTER__: specifies the Counter register new value. |
AnnaBridge | 157:e7ca05fa8600 | 1098 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1099 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1100 | #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__)) |
AnnaBridge | 157:e7ca05fa8600 | 1101 | |
AnnaBridge | 157:e7ca05fa8600 | 1102 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1103 | * @brief Gets the TIM Counter Register value on runtime. |
AnnaBridge | 157:e7ca05fa8600 | 1104 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1105 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1106 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1107 | #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT) |
AnnaBridge | 157:e7ca05fa8600 | 1108 | |
AnnaBridge | 157:e7ca05fa8600 | 1109 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1110 | * @brief Sets the TIM Autoreload Register value on runtime without calling |
AnnaBridge | 157:e7ca05fa8600 | 1111 | * another time any Init function. |
AnnaBridge | 157:e7ca05fa8600 | 1112 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1113 | * @param __AUTORELOAD__: specifies the Counter register new value. |
AnnaBridge | 157:e7ca05fa8600 | 1114 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1115 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1116 | #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1117 | do{ \ |
AnnaBridge | 157:e7ca05fa8600 | 1118 | (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \ |
AnnaBridge | 157:e7ca05fa8600 | 1119 | (__HANDLE__)->Init.Period = (__AUTORELOAD__); \ |
AnnaBridge | 157:e7ca05fa8600 | 1120 | } while(0) |
AnnaBridge | 157:e7ca05fa8600 | 1121 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1122 | * @brief Gets the TIM Autoreload Register value on runtime |
AnnaBridge | 157:e7ca05fa8600 | 1123 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1124 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1125 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1126 | #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR) |
AnnaBridge | 157:e7ca05fa8600 | 1127 | |
AnnaBridge | 157:e7ca05fa8600 | 1128 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1129 | * @brief Sets the TIM Clock Division value on runtime without calling |
AnnaBridge | 157:e7ca05fa8600 | 1130 | * another time any Init function. |
AnnaBridge | 157:e7ca05fa8600 | 1131 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1132 | * @param __CKD__: specifies the clock division value. |
AnnaBridge | 157:e7ca05fa8600 | 1133 | * This parameter can be one of the following value: |
AnnaBridge | 157:e7ca05fa8600 | 1134 | * @arg TIM_CLOCKDIVISION_DIV1 |
AnnaBridge | 157:e7ca05fa8600 | 1135 | * @arg TIM_CLOCKDIVISION_DIV2 |
AnnaBridge | 157:e7ca05fa8600 | 1136 | * @arg TIM_CLOCKDIVISION_DIV4 |
AnnaBridge | 157:e7ca05fa8600 | 1137 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1138 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1139 | #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1140 | do{ \ |
AnnaBridge | 157:e7ca05fa8600 | 1141 | (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \ |
AnnaBridge | 157:e7ca05fa8600 | 1142 | (__HANDLE__)->Instance->CR1 |= (__CKD__); \ |
AnnaBridge | 157:e7ca05fa8600 | 1143 | (__HANDLE__)->Init.ClockDivision = (__CKD__); \ |
AnnaBridge | 157:e7ca05fa8600 | 1144 | } while(0) |
AnnaBridge | 157:e7ca05fa8600 | 1145 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1146 | * @brief Gets the TIM Clock Division value on runtime |
AnnaBridge | 157:e7ca05fa8600 | 1147 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1148 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1149 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1150 | #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD) |
AnnaBridge | 157:e7ca05fa8600 | 1151 | |
AnnaBridge | 157:e7ca05fa8600 | 1152 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1153 | * @brief Sets the TIM Input Capture prescaler on runtime without calling |
AnnaBridge | 157:e7ca05fa8600 | 1154 | * another time HAL_TIM_IC_ConfigChannel() function. |
AnnaBridge | 157:e7ca05fa8600 | 1155 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1156 | * @param __CHANNEL__ : TIM Channels to be configured. |
AnnaBridge | 157:e7ca05fa8600 | 1157 | * This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1158 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 157:e7ca05fa8600 | 1159 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 157:e7ca05fa8600 | 1160 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 157:e7ca05fa8600 | 1161 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 157:e7ca05fa8600 | 1162 | * @param __ICPSC__: specifies the Input Capture4 prescaler new value. |
AnnaBridge | 157:e7ca05fa8600 | 1163 | * This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1164 | * @arg TIM_ICPSC_DIV1: no prescaler |
AnnaBridge | 157:e7ca05fa8600 | 1165 | * @arg TIM_ICPSC_DIV2: capture is done once every 2 events |
AnnaBridge | 157:e7ca05fa8600 | 1166 | * @arg TIM_ICPSC_DIV4: capture is done once every 4 events |
AnnaBridge | 157:e7ca05fa8600 | 1167 | * @arg TIM_ICPSC_DIV8: capture is done once every 8 events |
AnnaBridge | 157:e7ca05fa8600 | 1168 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1169 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1170 | #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1171 | do{ \ |
AnnaBridge | 157:e7ca05fa8600 | 1172 | TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 157:e7ca05fa8600 | 1173 | TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \ |
AnnaBridge | 157:e7ca05fa8600 | 1174 | } while(0) |
AnnaBridge | 157:e7ca05fa8600 | 1175 | |
AnnaBridge | 157:e7ca05fa8600 | 1176 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1177 | * @brief Gets the TIM Input Capture prescaler on runtime |
AnnaBridge | 157:e7ca05fa8600 | 1178 | * @param __HANDLE__ : TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1179 | * @param __CHANNEL__ : TIM Channels to be configured. |
AnnaBridge | 157:e7ca05fa8600 | 1180 | * This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1181 | * @arg TIM_CHANNEL_1: get input capture 1 prescaler value |
AnnaBridge | 157:e7ca05fa8600 | 1182 | * @arg TIM_CHANNEL_2: get input capture 2 prescaler value |
AnnaBridge | 157:e7ca05fa8600 | 1183 | * @arg TIM_CHANNEL_3: get input capture 3 prescaler value |
AnnaBridge | 157:e7ca05fa8600 | 1184 | * @arg TIM_CHANNEL_4: get input capture 4 prescaler value |
AnnaBridge | 157:e7ca05fa8600 | 1185 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1186 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1187 | #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1188 | (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1189 | ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1190 | ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\ |
AnnaBridge | 157:e7ca05fa8600 | 1191 | (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8U) |
AnnaBridge | 157:e7ca05fa8600 | 1192 | |
AnnaBridge | 157:e7ca05fa8600 | 1193 | |
AnnaBridge | 157:e7ca05fa8600 | 1194 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1195 | * @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register |
AnnaBridge | 157:e7ca05fa8600 | 1196 | * @param __HANDLE__: TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1197 | * @note When the URS bit of the TIMx_CR1 register is set, only counter |
AnnaBridge | 157:e7ca05fa8600 | 1198 | * overflow/underflow generates an update interrupt or DMA request (if |
AnnaBridge | 157:e7ca05fa8600 | 1199 | * enabled) |
AnnaBridge | 157:e7ca05fa8600 | 1200 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1201 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1202 | #define __HAL_TIM_URS_ENABLE(__HANDLE__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1203 | ((__HANDLE__)->Instance->CR1|= (TIM_CR1_URS)) |
AnnaBridge | 157:e7ca05fa8600 | 1204 | |
AnnaBridge | 157:e7ca05fa8600 | 1205 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1206 | * @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register |
AnnaBridge | 157:e7ca05fa8600 | 1207 | * @param __HANDLE__: TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1208 | * @note When the URS bit of the TIMx_CR1 register is reset, any of the |
AnnaBridge | 157:e7ca05fa8600 | 1209 | * following events generate an update interrupt or DMA request (if |
AnnaBridge | 157:e7ca05fa8600 | 1210 | * enabled): |
AnnaBridge | 157:e7ca05fa8600 | 1211 | * Counter overflow/underflow |
AnnaBridge | 157:e7ca05fa8600 | 1212 | * Setting the UG bit |
AnnaBridge | 157:e7ca05fa8600 | 1213 | * Update generation through the slave mode controller |
AnnaBridge | 157:e7ca05fa8600 | 1214 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1215 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1216 | #define __HAL_TIM_URS_DISABLE(__HANDLE__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1217 | ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS)) |
AnnaBridge | 157:e7ca05fa8600 | 1218 | |
AnnaBridge | 157:e7ca05fa8600 | 1219 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1220 | * @brief Sets the TIM Capture x input polarity on runtime. |
AnnaBridge | 157:e7ca05fa8600 | 1221 | * @param __HANDLE__: TIM handle. |
AnnaBridge | 157:e7ca05fa8600 | 1222 | * @param __CHANNEL__: TIM Channels to be configured. |
AnnaBridge | 157:e7ca05fa8600 | 1223 | * This parameter can be one of the following values: |
AnnaBridge | 157:e7ca05fa8600 | 1224 | * @arg TIM_CHANNEL_1: TIM Channel 1 selected |
AnnaBridge | 157:e7ca05fa8600 | 1225 | * @arg TIM_CHANNEL_2: TIM Channel 2 selected |
AnnaBridge | 157:e7ca05fa8600 | 1226 | * @arg TIM_CHANNEL_3: TIM Channel 3 selected |
AnnaBridge | 157:e7ca05fa8600 | 1227 | * @arg TIM_CHANNEL_4: TIM Channel 4 selected |
AnnaBridge | 157:e7ca05fa8600 | 1228 | * @param __POLARITY__: Polarity for TIx source |
AnnaBridge | 157:e7ca05fa8600 | 1229 | * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge |
AnnaBridge | 157:e7ca05fa8600 | 1230 | * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge |
AnnaBridge | 157:e7ca05fa8600 | 1231 | * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge |
AnnaBridge | 157:e7ca05fa8600 | 1232 | * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4. |
AnnaBridge | 157:e7ca05fa8600 | 1233 | * @retval None |
AnnaBridge | 157:e7ca05fa8600 | 1234 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1235 | #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \ |
AnnaBridge | 157:e7ca05fa8600 | 1236 | do{ \ |
AnnaBridge | 157:e7ca05fa8600 | 1237 | TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \ |
AnnaBridge | 157:e7ca05fa8600 | 1238 | TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \ |
AnnaBridge | 157:e7ca05fa8600 | 1239 | }while(0) |
AnnaBridge | 157:e7ca05fa8600 | 1240 | |
AnnaBridge | 157:e7ca05fa8600 | 1241 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1242 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1243 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1244 | |
AnnaBridge | 157:e7ca05fa8600 | 1245 | /* Include TIM HAL Extension module */ |
AnnaBridge | 157:e7ca05fa8600 | 1246 | #include "stm32l0xx_hal_tim_ex.h" |
AnnaBridge | 157:e7ca05fa8600 | 1247 | |
AnnaBridge | 157:e7ca05fa8600 | 1248 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 1249 | /** @defgroup TIM_Exported_Functions TIM Exported Functions |
AnnaBridge | 157:e7ca05fa8600 | 1250 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1251 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1252 | |
AnnaBridge | 157:e7ca05fa8600 | 1253 | /* Exported functions --------------------------------------------------------*/ |
AnnaBridge | 157:e7ca05fa8600 | 1254 | /* Time Base functions ********************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1255 | |
AnnaBridge | 157:e7ca05fa8600 | 1256 | /** @defgroup TIM_Exported_Functions_Group1 Timer Base functions |
AnnaBridge | 157:e7ca05fa8600 | 1257 | * @brief Time Base functions |
AnnaBridge | 157:e7ca05fa8600 | 1258 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1259 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1260 | HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1261 | HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1262 | void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1263 | void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1264 | /* Blocking mode: Polling */ |
AnnaBridge | 157:e7ca05fa8600 | 1265 | HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1266 | HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1267 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 157:e7ca05fa8600 | 1268 | HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1269 | HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1270 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 157:e7ca05fa8600 | 1271 | HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length); |
AnnaBridge | 157:e7ca05fa8600 | 1272 | HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1273 | |
AnnaBridge | 157:e7ca05fa8600 | 1274 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1275 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1276 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1277 | |
AnnaBridge | 157:e7ca05fa8600 | 1278 | |
AnnaBridge | 157:e7ca05fa8600 | 1279 | /* Timer Output Compare functions **********************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1280 | |
AnnaBridge | 157:e7ca05fa8600 | 1281 | /** @defgroup TIM_Exported_Functions_Group2 Timer Output Compare functions |
AnnaBridge | 157:e7ca05fa8600 | 1282 | * @brief Timer Output Compare functions |
AnnaBridge | 157:e7ca05fa8600 | 1283 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1284 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1285 | |
AnnaBridge | 157:e7ca05fa8600 | 1286 | HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1287 | HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1288 | void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1289 | void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1290 | /* Blocking mode: Polling */ |
AnnaBridge | 157:e7ca05fa8600 | 1291 | HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1292 | HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1293 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 157:e7ca05fa8600 | 1294 | HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1295 | HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1296 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 157:e7ca05fa8600 | 1297 | HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 157:e7ca05fa8600 | 1298 | HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1299 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1300 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1301 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1302 | |
AnnaBridge | 157:e7ca05fa8600 | 1303 | |
AnnaBridge | 157:e7ca05fa8600 | 1304 | /* Timer PWM functions *********************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1305 | |
AnnaBridge | 157:e7ca05fa8600 | 1306 | /** @defgroup TIM_Exported_Functions_Group3 Timer PWM functions |
AnnaBridge | 157:e7ca05fa8600 | 1307 | * @brief Timer PWM functions |
AnnaBridge | 157:e7ca05fa8600 | 1308 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1309 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1310 | HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1311 | HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1312 | void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1313 | void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1314 | /* Blocking mode: Polling */ |
AnnaBridge | 157:e7ca05fa8600 | 1315 | HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1316 | HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1317 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 157:e7ca05fa8600 | 1318 | HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1319 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1320 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 157:e7ca05fa8600 | 1321 | HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 157:e7ca05fa8600 | 1322 | HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1323 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1324 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1325 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1326 | |
AnnaBridge | 157:e7ca05fa8600 | 1327 | /* Timer Input Capture functions ***********************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1328 | |
AnnaBridge | 157:e7ca05fa8600 | 1329 | /** @defgroup TIM_Exported_Functions_Group4 Timer Input Capture functions |
AnnaBridge | 157:e7ca05fa8600 | 1330 | * @brief Timer Input Capture functions |
AnnaBridge | 157:e7ca05fa8600 | 1331 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1332 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1333 | HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1334 | HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1335 | void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1336 | void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1337 | /* Blocking mode: Polling */ |
AnnaBridge | 157:e7ca05fa8600 | 1338 | HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1339 | HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1340 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 157:e7ca05fa8600 | 1341 | HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1342 | HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1343 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 157:e7ca05fa8600 | 1344 | HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length); |
AnnaBridge | 157:e7ca05fa8600 | 1345 | HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1346 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1347 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1348 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1349 | |
AnnaBridge | 157:e7ca05fa8600 | 1350 | /* Timer One Pulse functions ***************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1351 | |
AnnaBridge | 157:e7ca05fa8600 | 1352 | /** @defgroup TIM_Exported_Functions_Group5 Timer One Pulse functions |
AnnaBridge | 157:e7ca05fa8600 | 1353 | * @brief Timer One Pulse functions |
AnnaBridge | 157:e7ca05fa8600 | 1354 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1355 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1356 | HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode); |
AnnaBridge | 157:e7ca05fa8600 | 1357 | HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1358 | void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1359 | void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1360 | /* Blocking mode: Polling */ |
AnnaBridge | 157:e7ca05fa8600 | 1361 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 157:e7ca05fa8600 | 1362 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 157:e7ca05fa8600 | 1363 | |
AnnaBridge | 157:e7ca05fa8600 | 1364 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 157:e7ca05fa8600 | 1365 | HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 157:e7ca05fa8600 | 1366 | HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel); |
AnnaBridge | 157:e7ca05fa8600 | 1367 | |
AnnaBridge | 157:e7ca05fa8600 | 1368 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1369 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1370 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1371 | |
AnnaBridge | 157:e7ca05fa8600 | 1372 | /* Timer Encoder functions *****************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1373 | |
AnnaBridge | 157:e7ca05fa8600 | 1374 | /** @defgroup TIM_Exported_Functions_Group6 Timer Encoder functions |
AnnaBridge | 157:e7ca05fa8600 | 1375 | * @brief Timer Encoder functions |
AnnaBridge | 157:e7ca05fa8600 | 1376 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1377 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1378 | HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig); |
AnnaBridge | 157:e7ca05fa8600 | 1379 | HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1380 | void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1381 | void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1382 | /* Blocking mode: Polling */ |
AnnaBridge | 157:e7ca05fa8600 | 1383 | HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1384 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1385 | /* Non-Blocking mode: Interrupt */ |
AnnaBridge | 157:e7ca05fa8600 | 1386 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1387 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1388 | /* Non-Blocking mode: DMA */ |
AnnaBridge | 157:e7ca05fa8600 | 1389 | HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length); |
AnnaBridge | 157:e7ca05fa8600 | 1390 | HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1391 | |
AnnaBridge | 157:e7ca05fa8600 | 1392 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1393 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1394 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1395 | |
AnnaBridge | 157:e7ca05fa8600 | 1396 | /* Interrupt Handler functions **********************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1397 | |
AnnaBridge | 157:e7ca05fa8600 | 1398 | /** @defgroup TIM_Exported_Functions_Group7 Timer IRQ handler management |
AnnaBridge | 157:e7ca05fa8600 | 1399 | * @brief Interrupt Handler functions |
AnnaBridge | 157:e7ca05fa8600 | 1400 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1401 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1402 | void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1403 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1404 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1405 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1406 | |
AnnaBridge | 157:e7ca05fa8600 | 1407 | /* Control functions *********************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1408 | |
AnnaBridge | 157:e7ca05fa8600 | 1409 | /** @defgroup TIM_Exported_Functions_Group8 Peripheral Control functions |
AnnaBridge | 157:e7ca05fa8600 | 1410 | * @brief Control functions |
AnnaBridge | 157:e7ca05fa8600 | 1411 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1412 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1413 | HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1414 | HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1415 | HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1416 | HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel); |
AnnaBridge | 157:e7ca05fa8600 | 1417 | HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1418 | HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig); |
AnnaBridge | 157:e7ca05fa8600 | 1419 | HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection); |
AnnaBridge | 157:e7ca05fa8600 | 1420 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 157:e7ca05fa8600 | 1421 | HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig); |
AnnaBridge | 157:e7ca05fa8600 | 1422 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 157:e7ca05fa8600 | 1423 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 157:e7ca05fa8600 | 1424 | HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 157:e7ca05fa8600 | 1425 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \ |
AnnaBridge | 157:e7ca05fa8600 | 1426 | uint32_t *BurstBuffer, uint32_t BurstLength); |
AnnaBridge | 157:e7ca05fa8600 | 1427 | HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc); |
AnnaBridge | 157:e7ca05fa8600 | 1428 | HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource); |
AnnaBridge | 157:e7ca05fa8600 | 1429 | uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel); |
AnnaBridge | 157:e7ca05fa8600 | 1430 | |
AnnaBridge | 157:e7ca05fa8600 | 1431 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1432 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1433 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1434 | |
AnnaBridge | 157:e7ca05fa8600 | 1435 | /* Callback in non blocking modes (Interrupt and DMA) *************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1436 | |
AnnaBridge | 157:e7ca05fa8600 | 1437 | /** @defgroup TIM_Exported_Functions_Group9 Timer Callbacks functions |
AnnaBridge | 157:e7ca05fa8600 | 1438 | * @brief Callback functions |
AnnaBridge | 157:e7ca05fa8600 | 1439 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1440 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1441 | void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1442 | void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1443 | void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1444 | void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1445 | void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1446 | void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1447 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1448 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1449 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1450 | |
AnnaBridge | 157:e7ca05fa8600 | 1451 | |
AnnaBridge | 157:e7ca05fa8600 | 1452 | /* Peripheral State functions **************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1453 | |
AnnaBridge | 157:e7ca05fa8600 | 1454 | /** @defgroup TIM_Exported_Functions_Group10 Peripheral State functions |
AnnaBridge | 157:e7ca05fa8600 | 1455 | * @brief Peripheral State functions |
AnnaBridge | 157:e7ca05fa8600 | 1456 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1457 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1458 | HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1459 | HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1460 | HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1461 | HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1462 | HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1463 | HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim); |
AnnaBridge | 157:e7ca05fa8600 | 1464 | void TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 157:e7ca05fa8600 | 1465 | void TIM_DMAError(DMA_HandleTypeDef *hdma); |
AnnaBridge | 157:e7ca05fa8600 | 1466 | void TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma); |
AnnaBridge | 157:e7ca05fa8600 | 1467 | |
AnnaBridge | 157:e7ca05fa8600 | 1468 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1469 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1470 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1471 | |
AnnaBridge | 157:e7ca05fa8600 | 1472 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1473 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1474 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1475 | |
AnnaBridge | 157:e7ca05fa8600 | 1476 | /* Define the private group ***********************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1477 | /**************************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1478 | /** @defgroup TIM_Private TIM Private |
AnnaBridge | 157:e7ca05fa8600 | 1479 | * @{ |
AnnaBridge | 157:e7ca05fa8600 | 1480 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1481 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1482 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1483 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1484 | /**************************************************************/ |
AnnaBridge | 157:e7ca05fa8600 | 1485 | |
AnnaBridge | 157:e7ca05fa8600 | 1486 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1487 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1488 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1489 | |
AnnaBridge | 157:e7ca05fa8600 | 1490 | /** |
AnnaBridge | 157:e7ca05fa8600 | 1491 | * @} |
AnnaBridge | 157:e7ca05fa8600 | 1492 | */ |
AnnaBridge | 157:e7ca05fa8600 | 1493 | |
AnnaBridge | 157:e7ca05fa8600 | 1494 | #ifdef __cplusplus |
AnnaBridge | 157:e7ca05fa8600 | 1495 | } |
AnnaBridge | 157:e7ca05fa8600 | 1496 | #endif |
AnnaBridge | 157:e7ca05fa8600 | 1497 | |
AnnaBridge | 157:e7ca05fa8600 | 1498 | #endif /* __STM32L0xx_HAL_TIM_H */ |
AnnaBridge | 157:e7ca05fa8600 | 1499 | |
AnnaBridge | 157:e7ca05fa8600 | 1500 | /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ |
AnnaBridge | 157:e7ca05fa8600 | 1501 |