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Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

TARGET_DISCO_L053C8/stm32l053xx.h@119:aae6fcc7d9bb, 2016-04-27 (annotated)

Committer:
Kojto
Date:
Wed Apr 27 12:10:56 2016 -0500
Revision:
119:aae6fcc7d9bb
Parent:
99:dbbf35b96557 
Release 119 of the mbed library



Changes:

- new targets - EFM32PG_STK3401, NUCLEO_L031K6

- ST - hwflwctl support for NUCLEO_L476RG

     - Update STM32CUBE_L0 from v1.2 to v1.5

     - STM32F7 - bugfix - The weak function HAL_Delay is overwritten to use us ticker API.

- Maxim - Fixing the send break for the MAXWSNENV and MAX32600MBED

Who changed what in which revision?

UserRevisionLine numberNew contents of line
Kojto 99:dbbf35b96557 1 /**
Kojto 99:dbbf35b96557 2 ******************************************************************************
Kojto 99:dbbf35b96557 3 * @file stm32l053xx.h
Kojto 99:dbbf35b96557 4 * @author MCD Application Team
Kojto 119:aae6fcc7d9bb 5 * @version V1.5.0
Kojto 119:aae6fcc7d9bb 6 * @date 8-January-2016
Kojto 99:dbbf35b96557 7 * @brief CMSIS Cortex-M0+ Device Peripheral Access Layer Header File.
Kojto 99:dbbf35b96557 8 * This file contains all the peripheral register's definitions, bits
Kojto 99:dbbf35b96557 9 * definitions and memory mapping for stm32l053xx devices.
Kojto 99:dbbf35b96557 10 *
Kojto 99:dbbf35b96557 11 * This file contains:
Kojto 99:dbbf35b96557 12 * - Data structures and the address mapping for all peripherals
Kojto 99:dbbf35b96557 13 * - Peripheral's registers declarations and bits definition
Kojto 99:dbbf35b96557 14 * - Macros to access peripheral's registers hardware
Kojto 99:dbbf35b96557 15 *
Kojto 99:dbbf35b96557 16 ******************************************************************************
Kojto 99:dbbf35b96557 17 * @attention
Kojto 99:dbbf35b96557 18 *
Kojto 119:aae6fcc7d9bb 19 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
Kojto 99:dbbf35b96557 20 *
Kojto 99:dbbf35b96557 21 * Redistribution and use in source and binary forms, with or without modification,
Kojto 99:dbbf35b96557 22 * are permitted provided that the following conditions are met:
Kojto 99:dbbf35b96557 23 * 1. Redistributions of source code must retain the above copyright notice,
Kojto 99:dbbf35b96557 24 * this list of conditions and the following disclaimer.
Kojto 99:dbbf35b96557 25 * 2. Redistributions in binary form must reproduce the above copyright notice,
Kojto 99:dbbf35b96557 26 * this list of conditions and the following disclaimer in the documentation
Kojto 99:dbbf35b96557 27 * and/or other materials provided with the distribution.
Kojto 99:dbbf35b96557 28 * 3. Neither the name of STMicroelectronics nor the names of its contributors
Kojto 99:dbbf35b96557 29 * may be used to endorse or promote products derived from this software
Kojto 99:dbbf35b96557 30 * without specific prior written permission.
Kojto 99:dbbf35b96557 31 *
Kojto 99:dbbf35b96557 32 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
Kojto 99:dbbf35b96557 33 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
Kojto 99:dbbf35b96557 34 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
Kojto 99:dbbf35b96557 35 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
Kojto 99:dbbf35b96557 36 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
Kojto 99:dbbf35b96557 37 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
Kojto 99:dbbf35b96557 38 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
Kojto 99:dbbf35b96557 39 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
Kojto 99:dbbf35b96557 40 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
Kojto 99:dbbf35b96557 41 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
Kojto 99:dbbf35b96557 42 *
Kojto 99:dbbf35b96557 43 ******************************************************************************
Kojto 99:dbbf35b96557 44 */
Kojto 99:dbbf35b96557 45
Kojto 99:dbbf35b96557 46 /** @addtogroup CMSIS
Kojto 99:dbbf35b96557 47 * @{
Kojto 99:dbbf35b96557 48 */
Kojto 99:dbbf35b96557 49
Kojto 99:dbbf35b96557 50 /** @addtogroup stm32l053xx
Kojto 99:dbbf35b96557 51 * @{
Kojto 99:dbbf35b96557 52 */
Kojto 99:dbbf35b96557 53
Kojto 99:dbbf35b96557 54 #ifndef __STM32L053xx_H
Kojto 99:dbbf35b96557 55 #define __STM32L053xx_H
Kojto 99:dbbf35b96557 56
Kojto 99:dbbf35b96557 57 #ifdef __cplusplus
Kojto 99:dbbf35b96557 58 extern "C" {
Kojto 99:dbbf35b96557 59 #endif
Kojto 99:dbbf35b96557 60
Kojto 99:dbbf35b96557 61
Kojto 99:dbbf35b96557 62 /** @addtogroup Configuration_section_for_CMSIS
Kojto 99:dbbf35b96557 63 * @{
Kojto 99:dbbf35b96557 64 */
Kojto 99:dbbf35b96557 65 /**
Kojto 99:dbbf35b96557 66 * @brief Configuration of the Cortex-M0+ Processor and Core Peripherals
Kojto 99:dbbf35b96557 67 */
Kojto 99:dbbf35b96557 68 #define __CM0PLUS_REV 0 /*!< Core Revision r0p0 */
Kojto 99:dbbf35b96557 69 #define __MPU_PRESENT 1 /*!< STM32L0xx provides an MPU */
Kojto 99:dbbf35b96557 70 #define __VTOR_PRESENT 1 /*!< Vector Table Register supported */
Kojto 99:dbbf35b96557 71 #define __NVIC_PRIO_BITS 2 /*!< STM32L0xx uses 2 Bits for the Priority Levels */
Kojto 99:dbbf35b96557 72 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
Kojto 99:dbbf35b96557 73
Kojto 99:dbbf35b96557 74 /**
Kojto 99:dbbf35b96557 75 * @}
Kojto 99:dbbf35b96557 76 */
Kojto 99:dbbf35b96557 77
Kojto 99:dbbf35b96557 78 /** @addtogroup Peripheral_interrupt_number_definition
Kojto 99:dbbf35b96557 79 * @{
Kojto 99:dbbf35b96557 80 */
Kojto 99:dbbf35b96557 81
Kojto 99:dbbf35b96557 82 /**
Kojto 99:dbbf35b96557 83 * @brief stm32l053xx Interrupt Number Definition, according to the selected device
Kojto 99:dbbf35b96557 84 * in @ref Library_configuration_section
Kojto 99:dbbf35b96557 85 */
Kojto 99:dbbf35b96557 86
Kojto 99:dbbf35b96557 87 /*!< Interrupt Number Definition */
Kojto 99:dbbf35b96557 88 typedef enum
Kojto 99:dbbf35b96557 89 {
Kojto 99:dbbf35b96557 90 /****** Cortex-M0 Processor Exceptions Numbers ******************************************************/
Kojto 99:dbbf35b96557 91 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
Kojto 99:dbbf35b96557 92 HardFault_IRQn = -13, /*!< 3 Cortex-M0+ Hard Fault Interrupt */
Kojto 99:dbbf35b96557 93 SVC_IRQn = -5, /*!< 11 Cortex-M0+ SV Call Interrupt */
Kojto 99:dbbf35b96557 94 PendSV_IRQn = -2, /*!< 14 Cortex-M0+ Pend SV Interrupt */
Kojto 99:dbbf35b96557 95 SysTick_IRQn = -1, /*!< 15 Cortex-M0+ System Tick Interrupt */
Kojto 99:dbbf35b96557 96
Kojto 99:dbbf35b96557 97 /****** STM32L-0 specific Interrupt Numbers *********************************************************/
Kojto 99:dbbf35b96557 98 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
Kojto 99:dbbf35b96557 99 PVD_IRQn = 1, /*!< PVD through EXTI Line detect Interrupt */
Kojto 99:dbbf35b96557 100 RTC_IRQn = 2, /*!< RTC through EXTI Line Interrupt */
Kojto 99:dbbf35b96557 101 FLASH_IRQn = 3, /*!< FLASH Interrupt */
Kojto 99:dbbf35b96557 102 RCC_CRS_IRQn = 4, /*!< RCC and CRS Interrupts */
Kojto 99:dbbf35b96557 103 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
Kojto 99:dbbf35b96557 104 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
Kojto 99:dbbf35b96557 105 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
Kojto 99:dbbf35b96557 106 TSC_IRQn = 8, /*!< TSC Interrupt */
Kojto 99:dbbf35b96557 107 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
Kojto 99:dbbf35b96557 108 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
Kojto 99:dbbf35b96557 109 DMA1_Channel4_5_6_7_IRQn = 11, /*!< DMA1 Channel 4, Channel 5, Channel 6 and Channel 7 Interrupts */
Kojto 99:dbbf35b96557 110 ADC1_COMP_IRQn = 12, /*!< ADC1, COMP1 and COMP2 Interrupts */
Kojto 99:dbbf35b96557 111 LPTIM1_IRQn = 13, /*!< LPTIM1 Interrupt */
Kojto 99:dbbf35b96557 112 TIM2_IRQn = 15, /*!< TIM2 Interrupt */
Kojto 99:dbbf35b96557 113 TIM6_DAC_IRQn = 17, /*!< TIM6 and DAC Interrupts */
Kojto 99:dbbf35b96557 114 TIM21_IRQn = 20, /*!< TIM21 Interrupt */
Kojto 99:dbbf35b96557 115 TIM22_IRQn = 22, /*!< TIM22 Interrupt */
Kojto 99:dbbf35b96557 116 I2C1_IRQn = 23, /*!< I2C1 Interrupt */
Kojto 99:dbbf35b96557 117 I2C2_IRQn = 24, /*!< I2C2 Interrupt */
Kojto 99:dbbf35b96557 118 SPI1_IRQn = 25, /*!< SPI1 Interrupt */
Kojto 99:dbbf35b96557 119 SPI2_IRQn = 26, /*!< SPI2 Interrupt */
Kojto 99:dbbf35b96557 120 USART1_IRQn = 27, /*!< USART1 Interrupt */
Kojto 99:dbbf35b96557 121 USART2_IRQn = 28, /*!< USART2 Interrupt */
Kojto 99:dbbf35b96557 122 RNG_LPUART1_IRQn = 29, /*!< RNG and LPUART1 Interrupts */
Kojto 99:dbbf35b96557 123 LCD_IRQn = 30, /*!< LCD Interrupt */
Kojto 99:dbbf35b96557 124 USB_IRQn = 31, /*!< USB global Interrupt */
Kojto 99:dbbf35b96557 125 } IRQn_Type;
Kojto 99:dbbf35b96557 126
Kojto 99:dbbf35b96557 127 /**
Kojto 99:dbbf35b96557 128 * @}
Kojto 99:dbbf35b96557 129 */
Kojto 99:dbbf35b96557 130
Kojto 99:dbbf35b96557 131 #include "core_cm0plus.h"
Kojto 99:dbbf35b96557 132 #include "system_stm32l0xx.h"
Kojto 99:dbbf35b96557 133 #include <stdint.h>
Kojto 99:dbbf35b96557 134
Kojto 99:dbbf35b96557 135 /** @addtogroup Peripheral_registers_structures
Kojto 99:dbbf35b96557 136 * @{
Kojto 99:dbbf35b96557 137 */
Kojto 99:dbbf35b96557 138
Kojto 99:dbbf35b96557 139 /**
Kojto 99:dbbf35b96557 140 * @brief Analog to Digital Converter
Kojto 99:dbbf35b96557 141 */
Kojto 99:dbbf35b96557 142
Kojto 99:dbbf35b96557 143 typedef struct
Kojto 99:dbbf35b96557 144 {
Kojto 99:dbbf35b96557 145 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
Kojto 99:dbbf35b96557 146 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
Kojto 99:dbbf35b96557 147 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
Kojto 99:dbbf35b96557 148 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
Kojto 99:dbbf35b96557 149 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
Kojto 99:dbbf35b96557 150 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
Kojto 99:dbbf35b96557 151 uint32_t RESERVED1; /*!< Reserved, 0x18 */
Kojto 99:dbbf35b96557 152 uint32_t RESERVED2; /*!< Reserved, 0x1C */
Kojto 99:dbbf35b96557 153 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
Kojto 99:dbbf35b96557 154 uint32_t RESERVED3; /*!< Reserved, 0x24 */
Kojto 99:dbbf35b96557 155 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
Kojto 99:dbbf35b96557 156 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
Kojto 99:dbbf35b96557 157 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
Kojto 99:dbbf35b96557 158 uint32_t RESERVED5[28]; /*!< Reserved, 0x44 - 0xB0 */
Kojto 99:dbbf35b96557 159 __IO uint32_t CALFACT; /*!< ADC data register, Address offset:0xB4 */
Kojto 99:dbbf35b96557 160 } ADC_TypeDef;
Kojto 99:dbbf35b96557 161
Kojto 99:dbbf35b96557 162 typedef struct
Kojto 99:dbbf35b96557 163 {
Kojto 99:dbbf35b96557 164 __IO uint32_t CCR;
Kojto 99:dbbf35b96557 165 } ADC_Common_TypeDef;
Kojto 99:dbbf35b96557 166
Kojto 99:dbbf35b96557 167
Kojto 99:dbbf35b96557 168 /**
Kojto 99:dbbf35b96557 169 * @brief Comparator
Kojto 99:dbbf35b96557 170 */
Kojto 99:dbbf35b96557 171
Kojto 99:dbbf35b96557 172 typedef struct
Kojto 99:dbbf35b96557 173 {
Kojto 99:dbbf35b96557 174 __IO uint32_t CSR; /*!< COMP comparator control and status register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 175 } COMP_TypeDef;
Kojto 99:dbbf35b96557 176
Kojto 119:aae6fcc7d9bb 177 typedef struct
Kojto 119:aae6fcc7d9bb 178 {
Kojto 119:aae6fcc7d9bb 179 __IO uint32_t CSR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
Kojto 119:aae6fcc7d9bb 180 } COMP_Common_TypeDef;
Kojto 119:aae6fcc7d9bb 181
Kojto 119:aae6fcc7d9bb 182
Kojto 119:aae6fcc7d9bb 183 /**
Kojto 119:aae6fcc7d9bb 184 * @brief CRC calculation unit
Kojto 119:aae6fcc7d9bb 185 */
Kojto 99:dbbf35b96557 186
Kojto 99:dbbf35b96557 187 typedef struct
Kojto 99:dbbf35b96557 188 {
Kojto 119:aae6fcc7d9bb 189 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
Kojto 119:aae6fcc7d9bb 190 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
Kojto 119:aae6fcc7d9bb 191 uint8_t RESERVED0; /*!< Reserved, 0x05 */
Kojto 119:aae6fcc7d9bb 192 uint16_t RESERVED1; /*!< Reserved, 0x06 */
Kojto 119:aae6fcc7d9bb 193 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
Kojto 119:aae6fcc7d9bb 194 uint32_t RESERVED2; /*!< Reserved, 0x0C */
Kojto 119:aae6fcc7d9bb 195 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
Kojto 119:aae6fcc7d9bb 196 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 197 } CRC_TypeDef;
Kojto 99:dbbf35b96557 198
Kojto 99:dbbf35b96557 199 /**
Kojto 99:dbbf35b96557 200 * @brief Clock Recovery System
Kojto 99:dbbf35b96557 201 */
Kojto 99:dbbf35b96557 202
Kojto 99:dbbf35b96557 203 typedef struct
Kojto 99:dbbf35b96557 204 {
Kojto 99:dbbf35b96557 205 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 206 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 207 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 208 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 209 } CRS_TypeDef;
Kojto 99:dbbf35b96557 210
Kojto 99:dbbf35b96557 211 /**
Kojto 99:dbbf35b96557 212 * @brief Digital to Analog Converter
Kojto 99:dbbf35b96557 213 */
Kojto 99:dbbf35b96557 214
Kojto 99:dbbf35b96557 215 typedef struct
Kojto 99:dbbf35b96557 216 {
Kojto 99:dbbf35b96557 217 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 218 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 219 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 220 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 221 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 222 uint32_t RESERVED0[6]; /*!< 0x14-0x28 */
Kojto 99:dbbf35b96557 223 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
Kojto 99:dbbf35b96557 224 uint32_t RESERVED1; /*!< 0x30 */
Kojto 99:dbbf35b96557 225 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
Kojto 99:dbbf35b96557 226 } DAC_TypeDef;
Kojto 99:dbbf35b96557 227
Kojto 99:dbbf35b96557 228 /**
Kojto 99:dbbf35b96557 229 * @brief Debug MCU
Kojto 99:dbbf35b96557 230 */
Kojto 99:dbbf35b96557 231
Kojto 99:dbbf35b96557 232 typedef struct
Kojto 99:dbbf35b96557 233 {
Kojto 99:dbbf35b96557 234 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
Kojto 99:dbbf35b96557 235 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 236 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 237 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 238 }DBGMCU_TypeDef;
Kojto 99:dbbf35b96557 239
Kojto 99:dbbf35b96557 240 /**
Kojto 99:dbbf35b96557 241 * @brief DMA Controller
Kojto 99:dbbf35b96557 242 */
Kojto 99:dbbf35b96557 243
Kojto 99:dbbf35b96557 244 typedef struct
Kojto 99:dbbf35b96557 245 {
Kojto 99:dbbf35b96557 246 __IO uint32_t CCR; /*!< DMA channel x configuration register */
Kojto 99:dbbf35b96557 247 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
Kojto 99:dbbf35b96557 248 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
Kojto 99:dbbf35b96557 249 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
Kojto 99:dbbf35b96557 250 } DMA_Channel_TypeDef;
Kojto 99:dbbf35b96557 251
Kojto 99:dbbf35b96557 252 typedef struct
Kojto 99:dbbf35b96557 253 {
Kojto 99:dbbf35b96557 254 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 255 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 256 } DMA_TypeDef;
Kojto 99:dbbf35b96557 257
Kojto 99:dbbf35b96557 258 typedef struct
Kojto 99:dbbf35b96557 259 {
Kojto 99:dbbf35b96557 260 __IO uint32_t CSELR; /*!< DMA channel selection register, Address offset: 0xA8 */
Kojto 99:dbbf35b96557 261 } DMA_Request_TypeDef;
Kojto 99:dbbf35b96557 262
Kojto 99:dbbf35b96557 263 /**
Kojto 99:dbbf35b96557 264 * @brief External Interrupt/Event Controller
Kojto 99:dbbf35b96557 265 */
Kojto 99:dbbf35b96557 266
Kojto 99:dbbf35b96557 267 typedef struct
Kojto 99:dbbf35b96557 268 {
Kojto 99:dbbf35b96557 269 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 270 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 271 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
Kojto 99:dbbf35b96557 272 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 273 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 274 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 275 }EXTI_TypeDef;
Kojto 99:dbbf35b96557 276
Kojto 99:dbbf35b96557 277 /**
Kojto 99:dbbf35b96557 278 * @brief FLASH Registers
Kojto 99:dbbf35b96557 279 */
Kojto 99:dbbf35b96557 280 typedef struct
Kojto 99:dbbf35b96557 281 {
Kojto 99:dbbf35b96557 282 __IO uint32_t ACR; /*!< Access control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 283 __IO uint32_t PECR; /*!< Program/erase control register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 284 __IO uint32_t PDKEYR; /*!< Power down key register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 285 __IO uint32_t PEKEYR; /*!< Program/erase key register, Address offset: 0x0c */
Kojto 99:dbbf35b96557 286 __IO uint32_t PRGKEYR; /*!< Program memory key register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 287 __IO uint32_t OPTKEYR; /*!< Option byte key register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 288 __IO uint32_t SR; /*!< Status register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 289 __IO uint32_t OPTR; /*!< Option byte register, Address offset: 0x1c */
Kojto 99:dbbf35b96557 290 __IO uint32_t WRPR; /*!< Write protection register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 291 } FLASH_TypeDef;
Kojto 99:dbbf35b96557 292
Kojto 99:dbbf35b96557 293
Kojto 99:dbbf35b96557 294 /**
Kojto 99:dbbf35b96557 295 * @brief Option Bytes Registers
Kojto 99:dbbf35b96557 296 */
Kojto 99:dbbf35b96557 297 typedef struct
Kojto 99:dbbf35b96557 298 {
Kojto 99:dbbf35b96557 299 __IO uint32_t RDP; /*!< Read protection register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 300 __IO uint32_t USER; /*!< user register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 301 __IO uint32_t WRP01; /*!< write protection Bytes 0 and 1 Address offset: 0x08 */
Kojto 99:dbbf35b96557 302 } OB_TypeDef;
Kojto 99:dbbf35b96557 303
Kojto 99:dbbf35b96557 304
Kojto 99:dbbf35b96557 305 /**
Kojto 99:dbbf35b96557 306 * @brief General Purpose IO
Kojto 99:dbbf35b96557 307 */
Kojto 99:dbbf35b96557 308
Kojto 99:dbbf35b96557 309 typedef struct
Kojto 99:dbbf35b96557 310 {
Kojto 99:dbbf35b96557 311 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 312 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 313 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 314 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 315 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 316 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 317 __IO uint32_t BSRR; /*!< GPIO port bit set/reset registerBSRR, Address offset: 0x18 */
Kojto 99:dbbf35b96557 318 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 319 __IO uint32_t AFR[2]; /*!< GPIO alternate function register, Address offset: 0x20-0x24 */
Kojto 99:dbbf35b96557 320 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
Kojto 99:dbbf35b96557 321 }GPIO_TypeDef;
Kojto 99:dbbf35b96557 322
Kojto 99:dbbf35b96557 323 /**
Kojto 99:dbbf35b96557 324 * @brief LPTIMIMER
Kojto 99:dbbf35b96557 325 */
Kojto 99:dbbf35b96557 326 typedef struct
Kojto 99:dbbf35b96557 327 {
Kojto 99:dbbf35b96557 328 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 329 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 330 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 331 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 332 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 333 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 334 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 335 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 336 } LPTIM_TypeDef;
Kojto 99:dbbf35b96557 337
Kojto 99:dbbf35b96557 338 /**
Kojto 99:dbbf35b96557 339 * @brief SysTem Configuration
Kojto 99:dbbf35b96557 340 */
Kojto 99:dbbf35b96557 341
Kojto 99:dbbf35b96557 342 typedef struct
Kojto 99:dbbf35b96557 343 {
Kojto 99:dbbf35b96557 344 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
Kojto 99:dbbf35b96557 345 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x04 */
Kojto 99:dbbf35b96557 346 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
Kojto 99:dbbf35b96557 347 uint32_t RESERVED[2]; /*!< Reserved, 0x18-0x1C */
Kojto 99:dbbf35b96557 348 __IO uint32_t CFGR3; /*!< SYSCFG configuration register 3, Address offset: 0x20 */
Kojto 99:dbbf35b96557 349 } SYSCFG_TypeDef;
Kojto 99:dbbf35b96557 350
Kojto 99:dbbf35b96557 351
Kojto 99:dbbf35b96557 352
Kojto 99:dbbf35b96557 353 /**
Kojto 99:dbbf35b96557 354 * @brief Inter-integrated Circuit Interface
Kojto 99:dbbf35b96557 355 */
Kojto 99:dbbf35b96557 356
Kojto 99:dbbf35b96557 357 typedef struct
Kojto 99:dbbf35b96557 358 {
Kojto 99:dbbf35b96557 359 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
Kojto 99:dbbf35b96557 360 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
Kojto 99:dbbf35b96557 361 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 362 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 363 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 364 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 365 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 366 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 367 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 368 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
Kojto 99:dbbf35b96557 369 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
Kojto 99:dbbf35b96557 370 }I2C_TypeDef;
Kojto 99:dbbf35b96557 371
Kojto 99:dbbf35b96557 372
Kojto 99:dbbf35b96557 373 /**
Kojto 99:dbbf35b96557 374 * @brief Independent WATCHDOG
Kojto 99:dbbf35b96557 375 */
Kojto 99:dbbf35b96557 376 typedef struct
Kojto 99:dbbf35b96557 377 {
Kojto 99:dbbf35b96557 378 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 379 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 380 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 381 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 382 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 383 } IWDG_TypeDef;
Kojto 99:dbbf35b96557 384
Kojto 99:dbbf35b96557 385 /**
Kojto 99:dbbf35b96557 386 * @brief LCD
Kojto 99:dbbf35b96557 387 */
Kojto 99:dbbf35b96557 388 typedef struct
Kojto 99:dbbf35b96557 389 {
Kojto 99:dbbf35b96557 390 __IO uint32_t CR; /*!< LCD control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 391 __IO uint32_t FCR; /*!< LCD frame control register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 392 __IO uint32_t SR; /*!< LCD status register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 393 __IO uint32_t CLR; /*!< LCD clear register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 394 uint32_t RESERVED; /*!< Reserved, Address offset: 0x10 */
Kojto 99:dbbf35b96557 395 __IO uint32_t RAM[16]; /*!< LCD display memory, Address offset: 0x14-0x50 */
Kojto 99:dbbf35b96557 396 } LCD_TypeDef;
Kojto 99:dbbf35b96557 397
Kojto 99:dbbf35b96557 398 /**
Kojto 99:dbbf35b96557 399 * @brief MIFARE Firewall
Kojto 99:dbbf35b96557 400 */
Kojto 99:dbbf35b96557 401 typedef struct
Kojto 99:dbbf35b96557 402 {
Kojto 99:dbbf35b96557 403 __IO uint32_t CSSA; /*!< Code Segment Start Address register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 404 __IO uint32_t CSL; /*!< Code Segment Length register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 405 __IO uint32_t NVDSSA; /*!< NON volatile data Segment Start Address register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 406 __IO uint32_t NVDSL; /*!< NON volatile data Segment Length register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 407 __IO uint32_t VDSSA ; /*!< Volatile data Segment Start Address register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 408 __IO uint32_t VDSL ; /*!< Volatile data Segment Length register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 409 __IO uint32_t LSSA ; /*!< Library Segment Start Address register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 410 __IO uint32_t LSL ; /*!< Library Segment Length register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 411 __IO uint32_t CR ; /*!< Configuration register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 412
Kojto 119:aae6fcc7d9bb 413 } FIREWALL_TypeDef;
Kojto 99:dbbf35b96557 414
Kojto 99:dbbf35b96557 415 /**
Kojto 99:dbbf35b96557 416 * @brief Power Control
Kojto 99:dbbf35b96557 417 */
Kojto 99:dbbf35b96557 418 typedef struct
Kojto 99:dbbf35b96557 419 {
Kojto 99:dbbf35b96557 420 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 421 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 422 } PWR_TypeDef;
Kojto 99:dbbf35b96557 423
Kojto 99:dbbf35b96557 424 /**
Kojto 99:dbbf35b96557 425 * @brief Reset and Clock Control
Kojto 99:dbbf35b96557 426 */
Kojto 99:dbbf35b96557 427 typedef struct
Kojto 99:dbbf35b96557 428 {
Kojto 99:dbbf35b96557 429 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 430 __IO uint32_t ICSCR; /*!< RCC Internal clock sources calibration register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 431 __IO uint32_t CRRCR; /*!< RCC Clock recovery RC register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 432 __IO uint32_t CFGR; /*!< RCC Clock configuration register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 433 __IO uint32_t CIER; /*!< RCC Clock interrupt enable register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 434 __IO uint32_t CIFR; /*!< RCC Clock interrupt flag register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 435 __IO uint32_t CICR; /*!< RCC Clock interrupt clear register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 436 __IO uint32_t IOPRSTR; /*!< RCC IO port reset register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 437 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 438 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x24 */
Kojto 99:dbbf35b96557 439 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x28 */
Kojto 99:dbbf35b96557 440 __IO uint32_t IOPENR; /*!< RCC Clock IO port enable register, Address offset: 0x2C */
Kojto 99:dbbf35b96557 441 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock enable register, Address offset: 0x30 */
Kojto 99:dbbf35b96557 442 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral enable register, Address offset: 0x34 */
Kojto 99:dbbf35b96557 443 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral enable register, Address offset: 0x38 */
Kojto 99:dbbf35b96557 444 __IO uint32_t IOPSMENR; /*!< RCC IO port clock enable in sleep mode register, Address offset: 0x3C */
Kojto 99:dbbf35b96557 445 __IO uint32_t AHBSMENR; /*!< RCC AHB peripheral clock enable in sleep mode register, Address offset: 0x40 */
Kojto 99:dbbf35b96557 446 __IO uint32_t APB2SMENR; /*!< RCC APB2 peripheral clock enable in sleep mode register, Address offset: 0x44 */
Kojto 99:dbbf35b96557 447 __IO uint32_t APB1SMENR; /*!< RCC APB1 peripheral clock enable in sleep mode register, Address offset: 0x48 */
Kojto 99:dbbf35b96557 448 __IO uint32_t CCIPR; /*!< RCC clock configuration register, Address offset: 0x4C */
Kojto 99:dbbf35b96557 449 __IO uint32_t CSR; /*!< RCC Control/status register, Address offset: 0x50 */
Kojto 99:dbbf35b96557 450 } RCC_TypeDef;
Kojto 99:dbbf35b96557 451
Kojto 99:dbbf35b96557 452 /**
Kojto 99:dbbf35b96557 453 * @brief Random numbers generator
Kojto 99:dbbf35b96557 454 */
Kojto 99:dbbf35b96557 455 typedef struct
Kojto 99:dbbf35b96557 456 {
Kojto 99:dbbf35b96557 457 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 458 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 459 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 460 } RNG_TypeDef;
Kojto 99:dbbf35b96557 461
Kojto 99:dbbf35b96557 462 /**
Kojto 99:dbbf35b96557 463 * @brief Real-Time Clock
Kojto 99:dbbf35b96557 464 */
Kojto 99:dbbf35b96557 465 typedef struct
Kojto 99:dbbf35b96557 466 {
Kojto 99:dbbf35b96557 467 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 468 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 469 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 470 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 471 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 472 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 473 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
Kojto 99:dbbf35b96557 474 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 475 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 476 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
Kojto 99:dbbf35b96557 477 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
Kojto 99:dbbf35b96557 478 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
Kojto 99:dbbf35b96557 479 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
Kojto 99:dbbf35b96557 480 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
Kojto 99:dbbf35b96557 481 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
Kojto 99:dbbf35b96557 482 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
Kojto 99:dbbf35b96557 483 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
Kojto 99:dbbf35b96557 484 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
Kojto 99:dbbf35b96557 485 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
Kojto 99:dbbf35b96557 486 __IO uint32_t OR; /*!< RTC option register, Address offset 0x4C */
Kojto 99:dbbf35b96557 487 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
Kojto 99:dbbf35b96557 488 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
Kojto 99:dbbf35b96557 489 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
Kojto 99:dbbf35b96557 490 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
Kojto 99:dbbf35b96557 491 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
Kojto 99:dbbf35b96557 492 } RTC_TypeDef;
Kojto 99:dbbf35b96557 493
Kojto 99:dbbf35b96557 494
Kojto 99:dbbf35b96557 495 /**
Kojto 99:dbbf35b96557 496 * @brief Serial Peripheral Interface
Kojto 99:dbbf35b96557 497 */
Kojto 99:dbbf35b96557 498 typedef struct
Kojto 99:dbbf35b96557 499 {
Kojto 99:dbbf35b96557 500 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
Kojto 99:dbbf35b96557 501 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
Kojto 99:dbbf35b96557 502 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 503 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 504 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
Kojto 99:dbbf35b96557 505 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
Kojto 99:dbbf35b96557 506 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
Kojto 99:dbbf35b96557 507 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 508 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 509 } SPI_TypeDef;
Kojto 99:dbbf35b96557 510
Kojto 99:dbbf35b96557 511 /**
Kojto 99:dbbf35b96557 512 * @brief TIM
Kojto 99:dbbf35b96557 513 */
Kojto 99:dbbf35b96557 514 typedef struct
Kojto 99:dbbf35b96557 515 {
Kojto 119:aae6fcc7d9bb 516 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
Kojto 119:aae6fcc7d9bb 517 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
Kojto 119:aae6fcc7d9bb 518 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
Kojto 119:aae6fcc7d9bb 519 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
Kojto 119:aae6fcc7d9bb 520 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
Kojto 119:aae6fcc7d9bb 521 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
Kojto 119:aae6fcc7d9bb 522 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
Kojto 119:aae6fcc7d9bb 523 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
Kojto 119:aae6fcc7d9bb 524 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
Kojto 119:aae6fcc7d9bb 525 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
Kojto 119:aae6fcc7d9bb 526 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
Kojto 119:aae6fcc7d9bb 527 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
Kojto 119:aae6fcc7d9bb 528 uint32_t RESERVED12;/*!< Reserved Address offset: 0x30 */
Kojto 119:aae6fcc7d9bb 529 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
Kojto 119:aae6fcc7d9bb 530 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
Kojto 119:aae6fcc7d9bb 531 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
Kojto 119:aae6fcc7d9bb 532 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
Kojto 119:aae6fcc7d9bb 533 uint32_t RESERVED17;/*!< Reserved, Address offset: 0x44 */
Kojto 119:aae6fcc7d9bb 534 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
Kojto 119:aae6fcc7d9bb 535 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
Kojto 119:aae6fcc7d9bb 536 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
Kojto 99:dbbf35b96557 537 } TIM_TypeDef;
Kojto 99:dbbf35b96557 538
Kojto 99:dbbf35b96557 539 /**
Kojto 99:dbbf35b96557 540 * @brief Touch Sensing Controller (TSC)
Kojto 99:dbbf35b96557 541 */
Kojto 99:dbbf35b96557 542 typedef struct
Kojto 99:dbbf35b96557 543 {
Kojto 99:dbbf35b96557 544 __IO uint32_t CR; /*!< TSC control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 545 __IO uint32_t IER; /*!< TSC interrupt enable register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 546 __IO uint32_t ICR; /*!< TSC interrupt clear register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 547 __IO uint32_t ISR; /*!< TSC interrupt status register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 548 __IO uint32_t IOHCR; /*!< TSC I/O hysteresis control register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 549 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
Kojto 99:dbbf35b96557 550 __IO uint32_t IOASCR; /*!< TSC I/O analog switch control register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 551 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
Kojto 99:dbbf35b96557 552 __IO uint32_t IOSCR; /*!< TSC I/O sampling control register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 553 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x24 */
Kojto 99:dbbf35b96557 554 __IO uint32_t IOCCR; /*!< TSC I/O channel control register, Address offset: 0x28 */
Kojto 99:dbbf35b96557 555 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x2C */
Kojto 99:dbbf35b96557 556 __IO uint32_t IOGCSR; /*!< TSC I/O group control status register, Address offset: 0x30 */
Kojto 99:dbbf35b96557 557 __IO uint32_t IOGXCR[8]; /*!< TSC I/O group x counter register, Address offset: 0x34-50 */
Kojto 99:dbbf35b96557 558 } TSC_TypeDef;
Kojto 99:dbbf35b96557 559
Kojto 99:dbbf35b96557 560 /**
Kojto 99:dbbf35b96557 561 * @brief Universal Synchronous Asynchronous Receiver Transmitter
Kojto 99:dbbf35b96557 562 */
Kojto 99:dbbf35b96557 563 typedef struct
Kojto 99:dbbf35b96557 564 {
Kojto 99:dbbf35b96557 565 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
Kojto 99:dbbf35b96557 566 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
Kojto 99:dbbf35b96557 567 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
Kojto 99:dbbf35b96557 568 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 569 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 570 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 571 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 572 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 573 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
Kojto 99:dbbf35b96557 574 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
Kojto 99:dbbf35b96557 575 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
Kojto 99:dbbf35b96557 576 } USART_TypeDef;
Kojto 99:dbbf35b96557 577
Kojto 99:dbbf35b96557 578 /**
Kojto 99:dbbf35b96557 579 * @brief Window WATCHDOG
Kojto 99:dbbf35b96557 580 */
Kojto 99:dbbf35b96557 581 typedef struct
Kojto 99:dbbf35b96557 582 {
Kojto 99:dbbf35b96557 583 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 584 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 585 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 586 } WWDG_TypeDef;
Kojto 99:dbbf35b96557 587
Kojto 99:dbbf35b96557 588 /**
Kojto 99:dbbf35b96557 589 * @brief Universal Serial Bus Full Speed Device
Kojto 99:dbbf35b96557 590 */
Kojto 99:dbbf35b96557 591 typedef struct
Kojto 99:dbbf35b96557 592 {
Kojto 99:dbbf35b96557 593 __IO uint16_t EP0R; /*!< USB Endpoint 0 register, Address offset: 0x00 */
Kojto 99:dbbf35b96557 594 __IO uint16_t RESERVED0; /*!< Reserved */
Kojto 99:dbbf35b96557 595 __IO uint16_t EP1R; /*!< USB Endpoint 1 register, Address offset: 0x04 */
Kojto 99:dbbf35b96557 596 __IO uint16_t RESERVED1; /*!< Reserved */
Kojto 99:dbbf35b96557 597 __IO uint16_t EP2R; /*!< USB Endpoint 2 register, Address offset: 0x08 */
Kojto 99:dbbf35b96557 598 __IO uint16_t RESERVED2; /*!< Reserved */
Kojto 99:dbbf35b96557 599 __IO uint16_t EP3R; /*!< USB Endpoint 3 register, Address offset: 0x0C */
Kojto 99:dbbf35b96557 600 __IO uint16_t RESERVED3; /*!< Reserved */
Kojto 99:dbbf35b96557 601 __IO uint16_t EP4R; /*!< USB Endpoint 4 register, Address offset: 0x10 */
Kojto 99:dbbf35b96557 602 __IO uint16_t RESERVED4; /*!< Reserved */
Kojto 99:dbbf35b96557 603 __IO uint16_t EP5R; /*!< USB Endpoint 5 register, Address offset: 0x14 */
Kojto 99:dbbf35b96557 604 __IO uint16_t RESERVED5; /*!< Reserved */
Kojto 99:dbbf35b96557 605 __IO uint16_t EP6R; /*!< USB Endpoint 6 register, Address offset: 0x18 */
Kojto 99:dbbf35b96557 606 __IO uint16_t RESERVED6; /*!< Reserved */
Kojto 99:dbbf35b96557 607 __IO uint16_t EP7R; /*!< USB Endpoint 7 register, Address offset: 0x1C */
Kojto 99:dbbf35b96557 608 __IO uint16_t RESERVED7[17]; /*!< Reserved */
Kojto 99:dbbf35b96557 609 __IO uint16_t CNTR; /*!< Control register, Address offset: 0x40 */
Kojto 99:dbbf35b96557 610 __IO uint16_t RESERVED8; /*!< Reserved */
Kojto 99:dbbf35b96557 611 __IO uint16_t ISTR; /*!< Interrupt status register, Address offset: 0x44 */
Kojto 99:dbbf35b96557 612 __IO uint16_t RESERVED9; /*!< Reserved */
Kojto 99:dbbf35b96557 613 __IO uint16_t FNR; /*!< Frame number register, Address offset: 0x48 */
Kojto 99:dbbf35b96557 614 __IO uint16_t RESERVEDA; /*!< Reserved */
Kojto 99:dbbf35b96557 615 __IO uint16_t DADDR; /*!< Device address register, Address offset: 0x4C */
Kojto 99:dbbf35b96557 616 __IO uint16_t RESERVEDB; /*!< Reserved */
Kojto 99:dbbf35b96557 617 __IO uint16_t BTABLE; /*!< Buffer Table address register, Address offset: 0x50 */
Kojto 99:dbbf35b96557 618 __IO uint16_t RESERVEDC; /*!< Reserved */
Kojto 99:dbbf35b96557 619 __IO uint16_t LPMCSR; /*!< LPM Control and Status register, Address offset: 0x54 */
Kojto 99:dbbf35b96557 620 __IO uint16_t RESERVEDD; /*!< Reserved */
Kojto 99:dbbf35b96557 621 __IO uint16_t BCDR; /*!< Battery Charging detector register, Address offset: 0x58 */
Kojto 99:dbbf35b96557 622 __IO uint16_t RESERVEDE; /*!< Reserved */
Kojto 99:dbbf35b96557 623 } USB_TypeDef;
Kojto 99:dbbf35b96557 624
Kojto 99:dbbf35b96557 625 /**
Kojto 99:dbbf35b96557 626 * @}
Kojto 99:dbbf35b96557 627 */
Kojto 99:dbbf35b96557 628
Kojto 99:dbbf35b96557 629 /** @addtogroup Peripheral_memory_map
Kojto 99:dbbf35b96557 630 * @{
Kojto 99:dbbf35b96557 631 */
Kojto 119:aae6fcc7d9bb 632 #define FLASH_BASE ((uint32_t)0x08000000U) /*!< FLASH base address in the alias region */
Kojto 119:aae6fcc7d9bb 633 #define FLASH_END ((uint32_t)0x0800FFFFU) /*!< FLASH end address in the alias region */
Kojto 119:aae6fcc7d9bb 634 #define DATA_EEPROM_BASE ((uint32_t)0x08080000U) /*!< DATA_EEPROM base address in the alias region */
Kojto 119:aae6fcc7d9bb 635 #define DATA_EEPROM_END ((uint32_t)0x080807FFU) /*!< DATA EEPROM end address in the alias region */
Kojto 119:aae6fcc7d9bb 636 #define SRAM_BASE ((uint32_t)0x20000000U) /*!< SRAM base address in the alias region */
Kojto 119:aae6fcc7d9bb 637 #define PERIPH_BASE ((uint32_t)0x40000000U) /*!< Peripheral base address in the alias region */
Kojto 99:dbbf35b96557 638
Kojto 99:dbbf35b96557 639 /*!< Peripheral memory map */
Kojto 99:dbbf35b96557 640 #define APBPERIPH_BASE PERIPH_BASE
Kojto 99:dbbf35b96557 641 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
Kojto 99:dbbf35b96557 642 #define IOPPERIPH_BASE (PERIPH_BASE + 0x10000000)
Kojto 99:dbbf35b96557 643
Kojto 99:dbbf35b96557 644 #define TIM2_BASE (APBPERIPH_BASE + 0x00000000)
Kojto 99:dbbf35b96557 645 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
Kojto 99:dbbf35b96557 646 #define LCD_BASE (APBPERIPH_BASE + 0x00002400)
Kojto 99:dbbf35b96557 647 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
Kojto 99:dbbf35b96557 648 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
Kojto 99:dbbf35b96557 649 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
Kojto 99:dbbf35b96557 650 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
Kojto 99:dbbf35b96557 651 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
Kojto 99:dbbf35b96557 652 #define LPUART1_BASE (APBPERIPH_BASE + 0x00004800)
Kojto 99:dbbf35b96557 653 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
Kojto 99:dbbf35b96557 654 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
Kojto 99:dbbf35b96557 655 #define CRS_BASE (APBPERIPH_BASE + 0x00006C00)
Kojto 99:dbbf35b96557 656 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
Kojto 99:dbbf35b96557 657 #define DAC_BASE (APBPERIPH_BASE + 0x00007400)
Kojto 99:dbbf35b96557 658 #define LPTIM1_BASE (APBPERIPH_BASE + 0x00007C00)
Kojto 99:dbbf35b96557 659
Kojto 99:dbbf35b96557 660 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
Kojto 99:dbbf35b96557 661 #define COMP1_BASE (APBPERIPH_BASE + 0x00010018)
Kojto 99:dbbf35b96557 662 #define COMP2_BASE (APBPERIPH_BASE + 0x0001001C)
Kojto 119:aae6fcc7d9bb 663 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP1_BASE)
Kojto 99:dbbf35b96557 664 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
Kojto 99:dbbf35b96557 665 #define TIM21_BASE (APBPERIPH_BASE + 0x00010800)
Kojto 99:dbbf35b96557 666 #define TIM22_BASE (APBPERIPH_BASE + 0x00011400)
Kojto 119:aae6fcc7d9bb 667 #define FIREWALL_BASE (APBPERIPH_BASE + 0x00011C00)
Kojto 99:dbbf35b96557 668 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
Kojto 99:dbbf35b96557 669 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
Kojto 99:dbbf35b96557 670 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
Kojto 99:dbbf35b96557 671 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
Kojto 99:dbbf35b96557 672 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
Kojto 99:dbbf35b96557 673
Kojto 99:dbbf35b96557 674 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
Kojto 99:dbbf35b96557 675 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
Kojto 99:dbbf35b96557 676 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
Kojto 99:dbbf35b96557 677 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
Kojto 99:dbbf35b96557 678 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
Kojto 99:dbbf35b96557 679 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
Kojto 99:dbbf35b96557 680 #define DMA1_Channel6_BASE (DMA1_BASE + 0x0000006C)
Kojto 99:dbbf35b96557 681 #define DMA1_Channel7_BASE (DMA1_BASE + 0x00000080)
Kojto 99:dbbf35b96557 682 #define DMA1_CSELR_BASE (DMA1_BASE + 0x000000A8)
Kojto 99:dbbf35b96557 683
Kojto 99:dbbf35b96557 684
Kojto 99:dbbf35b96557 685 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
Kojto 99:dbbf35b96557 686 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
Kojto 119:aae6fcc7d9bb 687 #define OB_BASE ((uint32_t)0x1FF80000U) /*!< FLASH Option Bytes base address */
Kojto 99:dbbf35b96557 688 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
Kojto 99:dbbf35b96557 689 #define TSC_BASE (AHBPERIPH_BASE + 0x00004000)
Kojto 99:dbbf35b96557 690 #define RNG_BASE (AHBPERIPH_BASE + 0x00005000)
Kojto 99:dbbf35b96557 691
Kojto 99:dbbf35b96557 692 #define GPIOA_BASE (IOPPERIPH_BASE + 0x00000000)
Kojto 99:dbbf35b96557 693 #define GPIOB_BASE (IOPPERIPH_BASE + 0x00000400)
Kojto 99:dbbf35b96557 694 #define GPIOC_BASE (IOPPERIPH_BASE + 0x00000800)
Kojto 99:dbbf35b96557 695 #define GPIOD_BASE (IOPPERIPH_BASE + 0x00000C00)
Kojto 99:dbbf35b96557 696 #define GPIOH_BASE (IOPPERIPH_BASE + 0x00001C00)
Kojto 99:dbbf35b96557 697
Kojto 99:dbbf35b96557 698 /**
Kojto 99:dbbf35b96557 699 * @}
Kojto 99:dbbf35b96557 700 */
Kojto 99:dbbf35b96557 701
Kojto 99:dbbf35b96557 702 /** @addtogroup Peripheral_declaration
Kojto 99:dbbf35b96557 703 * @{
Kojto 99:dbbf35b96557 704 */
Kojto 99:dbbf35b96557 705
Kojto 99:dbbf35b96557 706 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
Kojto 99:dbbf35b96557 707 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
Kojto 99:dbbf35b96557 708 #define RTC ((RTC_TypeDef *) RTC_BASE)
Kojto 99:dbbf35b96557 709 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
Kojto 99:dbbf35b96557 710 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
Kojto 99:dbbf35b96557 711 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
Kojto 99:dbbf35b96557 712 #define USART2 ((USART_TypeDef *) USART2_BASE)
Kojto 99:dbbf35b96557 713 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
Kojto 99:dbbf35b96557 714 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
Kojto 99:dbbf35b96557 715 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
Kojto 99:dbbf35b96557 716 #define CRS ((CRS_TypeDef *) CRS_BASE)
Kojto 99:dbbf35b96557 717 #define PWR ((PWR_TypeDef *) PWR_BASE)
Kojto 99:dbbf35b96557 718 #define DAC ((DAC_TypeDef *) DAC_BASE)
Kojto 119:aae6fcc7d9bb 719 #define DAC1 ((DAC_TypeDef *) DAC_BASE)
Kojto 99:dbbf35b96557 720 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
Kojto 99:dbbf35b96557 721 #define LCD ((LCD_TypeDef *) LCD_BASE)
Kojto 99:dbbf35b96557 722
Kojto 99:dbbf35b96557 723 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
Kojto 99:dbbf35b96557 724 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
Kojto 99:dbbf35b96557 725 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
Kojto 99:dbbf35b96557 726 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
Kojto 99:dbbf35b96557 727 #define TIM21 ((TIM_TypeDef *) TIM21_BASE)
Kojto 99:dbbf35b96557 728 #define TIM22 ((TIM_TypeDef *) TIM22_BASE)
Kojto 119:aae6fcc7d9bb 729 #define FIREWALL ((FIREWALL_TypeDef *) FIREWALL_BASE)
Kojto 99:dbbf35b96557 730 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
Kojto 119:aae6fcc7d9bb 731 #define ADC1_COMMON ((ADC_Common_TypeDef *) ADC_BASE)
Kojto 119:aae6fcc7d9bb 732 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 733 #define ADC ADC1_COMMON
Kojto 99:dbbf35b96557 734 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
Kojto 99:dbbf35b96557 735 #define USART1 ((USART_TypeDef *) USART1_BASE)
Kojto 99:dbbf35b96557 736 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
Kojto 99:dbbf35b96557 737
Kojto 99:dbbf35b96557 738 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
Kojto 99:dbbf35b96557 739 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
Kojto 99:dbbf35b96557 740 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
Kojto 99:dbbf35b96557 741 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
Kojto 99:dbbf35b96557 742 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
Kojto 99:dbbf35b96557 743 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
Kojto 99:dbbf35b96557 744 #define DMA1_Channel6 ((DMA_Channel_TypeDef *) DMA1_Channel6_BASE)
Kojto 99:dbbf35b96557 745 #define DMA1_Channel7 ((DMA_Channel_TypeDef *) DMA1_Channel7_BASE)
Kojto 99:dbbf35b96557 746 #define DMA1_CSELR ((DMA_Request_TypeDef *) DMA1_CSELR_BASE)
Kojto 99:dbbf35b96557 747
Kojto 99:dbbf35b96557 748
Kojto 99:dbbf35b96557 749 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
Kojto 99:dbbf35b96557 750 #define OB ((OB_TypeDef *) OB_BASE)
Kojto 99:dbbf35b96557 751 #define RCC ((RCC_TypeDef *) RCC_BASE)
Kojto 99:dbbf35b96557 752 #define CRC ((CRC_TypeDef *) CRC_BASE)
Kojto 99:dbbf35b96557 753 #define TSC ((TSC_TypeDef *) TSC_BASE)
Kojto 99:dbbf35b96557 754 #define RNG ((RNG_TypeDef *) RNG_BASE)
Kojto 99:dbbf35b96557 755
Kojto 99:dbbf35b96557 756 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
Kojto 99:dbbf35b96557 757 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
Kojto 99:dbbf35b96557 758 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
Kojto 99:dbbf35b96557 759 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
Kojto 99:dbbf35b96557 760 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
Kojto 99:dbbf35b96557 761
Kojto 99:dbbf35b96557 762 #define USB ((USB_TypeDef *) USB_BASE)
Kojto 99:dbbf35b96557 763
Kojto 99:dbbf35b96557 764 /**
Kojto 99:dbbf35b96557 765 * @}
Kojto 99:dbbf35b96557 766 */
Kojto 99:dbbf35b96557 767
Kojto 99:dbbf35b96557 768 /** @addtogroup Exported_constants
Kojto 99:dbbf35b96557 769 * @{
Kojto 99:dbbf35b96557 770 */
Kojto 99:dbbf35b96557 771
Kojto 99:dbbf35b96557 772 /** @addtogroup Peripheral_Registers_Bits_Definition
Kojto 99:dbbf35b96557 773 * @{
Kojto 99:dbbf35b96557 774 */
Kojto 99:dbbf35b96557 775
Kojto 99:dbbf35b96557 776 /******************************************************************************/
Kojto 99:dbbf35b96557 777 /* Peripheral Registers Bits Definition */
Kojto 99:dbbf35b96557 778 /******************************************************************************/
Kojto 99:dbbf35b96557 779 /******************************************************************************/
Kojto 99:dbbf35b96557 780 /* */
Kojto 99:dbbf35b96557 781 /* Analog to Digital Converter (ADC) */
Kojto 99:dbbf35b96557 782 /* */
Kojto 99:dbbf35b96557 783 /******************************************************************************/
Kojto 99:dbbf35b96557 784 /******************** Bits definition for ADC_ISR register ******************/
Kojto 119:aae6fcc7d9bb 785 #define ADC_ISR_EOCAL ((uint32_t)0x00000800U) /*!< End of calibration flag */
Kojto 119:aae6fcc7d9bb 786 #define ADC_ISR_AWD ((uint32_t)0x00000080U) /*!< Analog watchdog flag */
Kojto 119:aae6fcc7d9bb 787 #define ADC_ISR_OVR ((uint32_t)0x00000010U) /*!< Overrun flag */
Kojto 119:aae6fcc7d9bb 788 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008U) /*!< End of Sequence flag */
Kojto 119:aae6fcc7d9bb 789 #define ADC_ISR_EOC ((uint32_t)0x00000004U) /*!< End of Conversion */
Kojto 119:aae6fcc7d9bb 790 #define ADC_ISR_EOSMP ((uint32_t)0x00000002U) /*!< End of sampling flag */
Kojto 119:aae6fcc7d9bb 791 #define ADC_ISR_ADRDY ((uint32_t)0x00000001U) /*!< ADC Ready */
Kojto 99:dbbf35b96557 792
Kojto 99:dbbf35b96557 793 /* Old EOSEQ bit definition, maintained for legacy purpose */
Kojto 99:dbbf35b96557 794 #define ADC_ISR_EOS ADC_ISR_EOSEQ
Kojto 99:dbbf35b96557 795
Kojto 99:dbbf35b96557 796 /******************** Bits definition for ADC_IER register ******************/
Kojto 119:aae6fcc7d9bb 797 #define ADC_IER_EOCALIE ((uint32_t)0x00000800U) /*!< Enf Of Calibration interrupt enable */
Kojto 119:aae6fcc7d9bb 798 #define ADC_IER_AWDIE ((uint32_t)0x00000080U) /*!< Analog Watchdog interrupt enable */
Kojto 119:aae6fcc7d9bb 799 #define ADC_IER_OVRIE ((uint32_t)0x00000010U) /*!< Overrun interrupt enable */
Kojto 119:aae6fcc7d9bb 800 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008U) /*!< End of Sequence of conversion interrupt enable */
Kojto 119:aae6fcc7d9bb 801 #define ADC_IER_EOCIE ((uint32_t)0x00000004U) /*!< End of Conversion interrupt enable */
Kojto 119:aae6fcc7d9bb 802 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002U) /*!< End of sampling interrupt enable */
Kojto 119:aae6fcc7d9bb 803 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001U) /*!< ADC Ready interrupt enable */
Kojto 99:dbbf35b96557 804
Kojto 99:dbbf35b96557 805 /* Old EOSEQIE bit definition, maintained for legacy purpose */
Kojto 99:dbbf35b96557 806 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
Kojto 99:dbbf35b96557 807
Kojto 99:dbbf35b96557 808 /******************** Bits definition for ADC_CR register *******************/
Kojto 119:aae6fcc7d9bb 809 #define ADC_CR_ADCAL ((uint32_t)0x80000000U) /*!< ADC calibration */
Kojto 119:aae6fcc7d9bb 810 #define ADC_CR_ADVREGEN ((uint32_t)0x10000000U) /*!< ADC Voltage Regulator Enable */
Kojto 119:aae6fcc7d9bb 811 #define ADC_CR_ADSTP ((uint32_t)0x00000010U) /*!< ADC stop of conversion command */
Kojto 119:aae6fcc7d9bb 812 #define ADC_CR_ADSTART ((uint32_t)0x00000004U) /*!< ADC start of conversion */
Kojto 119:aae6fcc7d9bb 813 #define ADC_CR_ADDIS ((uint32_t)0x00000002U) /*!< ADC disable command */
Kojto 119:aae6fcc7d9bb 814 #define ADC_CR_ADEN ((uint32_t)0x00000001U) /*!< ADC enable control */ /*#### TBV */
Kojto 99:dbbf35b96557 815
Kojto 99:dbbf35b96557 816 /******************* Bits definition for ADC_CFGR1 register *****************/
Kojto 119:aae6fcc7d9bb 817 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000U) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
Kojto 119:aae6fcc7d9bb 818 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 819 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 820 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 821 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 822 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000U) /*!< Bit 4 */
Kojto 119:aae6fcc7d9bb 823 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000U) /*!< Analog watchdog enable on regular channels */
Kojto 119:aae6fcc7d9bb 824 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000U) /*!< Enable the watchdog on a single channel or on all channels */
Kojto 119:aae6fcc7d9bb 825 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000U) /*!< Discontinuous mode on regular channels */
Kojto 119:aae6fcc7d9bb 826 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000U) /*!< ADC auto power off */
Kojto 119:aae6fcc7d9bb 827 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000U) /*!< ADC wait conversion mode */
Kojto 119:aae6fcc7d9bb 828 #define ADC_CFGR1_CONT ((uint32_t)0x00002000U) /*!< Continuous Conversion */
Kojto 119:aae6fcc7d9bb 829 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000U) /*!< Overrun mode */
Kojto 119:aae6fcc7d9bb 830 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00U) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
Kojto 119:aae6fcc7d9bb 831 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 832 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 833 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0U) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
Kojto 119:aae6fcc7d9bb 834 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 835 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 836 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 837 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020U) /*!< Data Alignment */
Kojto 119:aae6fcc7d9bb 838 #define ADC_CFGR1_RES ((uint32_t)0x00000018U) /*!< RES[1:0] bits (Resolution) */
Kojto 119:aae6fcc7d9bb 839 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 840 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 841 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004U) /*!< Sequence scan direction */
Kojto 119:aae6fcc7d9bb 842 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002U) /*!< Direct memory access configuration */
Kojto 119:aae6fcc7d9bb 843 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001U) /*!< Direct memory access enable */
Kojto 99:dbbf35b96557 844
Kojto 99:dbbf35b96557 845 /* Old WAIT bit definition, maintained for legacy purpose */
Kojto 99:dbbf35b96557 846 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
Kojto 99:dbbf35b96557 847
Kojto 99:dbbf35b96557 848 /******************* Bits definition for ADC_CFGR2 register *****************/
Kojto 119:aae6fcc7d9bb 849 #define ADC_CFGR2_TOVS ((uint32_t)0x80000200U) /*!< Triggered Oversampling */
Kojto 119:aae6fcc7d9bb 850 #define ADC_CFGR2_OVSS ((uint32_t)0x000001E0U) /*!< OVSS [3:0] bits (Oversampling shift) */
Kojto 119:aae6fcc7d9bb 851 #define ADC_CFGR2_OVSS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 852 #define ADC_CFGR2_OVSS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 853 #define ADC_CFGR2_OVSS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 854 #define ADC_CFGR2_OVSS_3 ((uint32_t)0x00000100U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 855 #define ADC_CFGR2_OVSR ((uint32_t)0x0000001CU) /*!< OVSR [2:0] bits (Oversampling ratio) */
Kojto 119:aae6fcc7d9bb 856 #define ADC_CFGR2_OVSR_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 857 #define ADC_CFGR2_OVSR_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 858 #define ADC_CFGR2_OVSR_2 ((uint32_t)0x00000010U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 859 #define ADC_CFGR2_OVSE ((uint32_t)0x00000001U) /*!< Oversampler Enable */
Kojto 119:aae6fcc7d9bb 860 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000U) /*!< CKMODE [1:0] bits (ADC clock mode) */
Kojto 119:aae6fcc7d9bb 861 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 862 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000U) /*!< Bit 1 */
Kojto 99:dbbf35b96557 863
Kojto 99:dbbf35b96557 864
Kojto 99:dbbf35b96557 865 /****************** Bit definition for ADC_SMPR register ********************/
Kojto 119:aae6fcc7d9bb 866 #define ADC_SMPR_SMP ((uint32_t)0x00000007U) /*!< SMPR[2:0] bits (Sampling time selection) */
Kojto 119:aae6fcc7d9bb 867 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 868 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 869 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 870
Kojto 119:aae6fcc7d9bb 871 /* Legacy defines */
Kojto 99:dbbf35b96557 872 #define ADC_SMPR_SMPR ADC_SMPR_SMP
Kojto 99:dbbf35b96557 873 #define ADC_SMPR_SMPR_0 ADC_SMPR_SMP_0
Kojto 99:dbbf35b96557 874 #define ADC_SMPR_SMPR_1 ADC_SMPR_SMP_1
Kojto 99:dbbf35b96557 875 #define ADC_SMPR_SMPR_2 ADC_SMPR_SMP_2
Kojto 99:dbbf35b96557 876
Kojto 99:dbbf35b96557 877 /******************* Bit definition for ADC_TR register ********************/
Kojto 119:aae6fcc7d9bb 878 #define ADC_TR_HT ((uint32_t)0x0FFF0000U) /*!< Analog watchdog high threshold */
Kojto 119:aae6fcc7d9bb 879 #define ADC_TR_LT ((uint32_t)0x00000FFFU) /*!< Analog watchdog low threshold */
Kojto 99:dbbf35b96557 880
Kojto 99:dbbf35b96557 881 /****************** Bit definition for ADC_CHSELR register ******************/
Kojto 119:aae6fcc7d9bb 882 #define ADC_CHSELR_CHSEL ((uint32_t)0x0007FFFFU) /*!< ADC group regular sequencer channels */
Kojto 119:aae6fcc7d9bb 883 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000U) /*!< Channel 18 selection */
Kojto 119:aae6fcc7d9bb 884 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000U) /*!< Channel 17 selection */
Kojto 119:aae6fcc7d9bb 885 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000U) /*!< Channel 16 selection */
Kojto 119:aae6fcc7d9bb 886 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000U) /*!< Channel 15 selection */
Kojto 119:aae6fcc7d9bb 887 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000U) /*!< Channel 14 selection */
Kojto 119:aae6fcc7d9bb 888 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000U) /*!< Channel 13 selection */
Kojto 119:aae6fcc7d9bb 889 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000U) /*!< Channel 12 selection */
Kojto 119:aae6fcc7d9bb 890 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800U) /*!< Channel 11 selection */
Kojto 119:aae6fcc7d9bb 891 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400U) /*!< Channel 10 selection */
Kojto 119:aae6fcc7d9bb 892 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200U) /*!< Channel 9 selection */
Kojto 119:aae6fcc7d9bb 893 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100U) /*!< Channel 8 selection */
Kojto 119:aae6fcc7d9bb 894 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080U) /*!< Channel 7 selection */
Kojto 119:aae6fcc7d9bb 895 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040U) /*!< Channel 6 selection */
Kojto 119:aae6fcc7d9bb 896 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020U) /*!< Channel 5 selection */
Kojto 119:aae6fcc7d9bb 897 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010U) /*!< Channel 4 selection */
Kojto 119:aae6fcc7d9bb 898 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008U) /*!< Channel 3 selection */
Kojto 119:aae6fcc7d9bb 899 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004U) /*!< Channel 2 selection */
Kojto 119:aae6fcc7d9bb 900 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002U) /*!< Channel 1 selection */
Kojto 119:aae6fcc7d9bb 901 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001U) /*!< Channel 0 selection */
Kojto 99:dbbf35b96557 902
Kojto 99:dbbf35b96557 903 /******************** Bit definition for ADC_DR register ********************/
Kojto 119:aae6fcc7d9bb 904 #define ADC_DR_DATA ((uint32_t)0x0000FFFFU) /*!< Regular data */
Kojto 99:dbbf35b96557 905
Kojto 99:dbbf35b96557 906 /******************** Bit definition for ADC_CALFACT register ********************/
Kojto 119:aae6fcc7d9bb 907 #define ADC_CALFACT_CALFACT ((uint32_t)0x0000007FU) /*!< Calibration factor */
Kojto 99:dbbf35b96557 908
Kojto 99:dbbf35b96557 909 /******************* Bit definition for ADC_CCR register ********************/
Kojto 119:aae6fcc7d9bb 910 #define ADC_CCR_LFMEN ((uint32_t)0x02000000U) /*!< Low Frequency Mode enable */
Kojto 119:aae6fcc7d9bb 911 #define ADC_CCR_VLCDEN ((uint32_t)0x01000000U) /*!< Voltage LCD enable */
Kojto 119:aae6fcc7d9bb 912 #define ADC_CCR_TSEN ((uint32_t)0x00800000U) /*!< Temperature sensore enable */
Kojto 119:aae6fcc7d9bb 913 #define ADC_CCR_VREFEN ((uint32_t)0x00400000U) /*!< Vrefint enable */
Kojto 119:aae6fcc7d9bb 914 #define ADC_CCR_PRESC ((uint32_t)0x003C0000U) /*!< PRESC [3:0] bits (ADC prescaler) */
Kojto 119:aae6fcc7d9bb 915 #define ADC_CCR_PRESC_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 916 #define ADC_CCR_PRESC_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 917 #define ADC_CCR_PRESC_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 918 #define ADC_CCR_PRESC_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
Kojto 99:dbbf35b96557 919
Kojto 99:dbbf35b96557 920 /******************************************************************************/
Kojto 99:dbbf35b96557 921 /* */
Kojto 99:dbbf35b96557 922 /* Analog Comparators (COMP) */
Kojto 99:dbbf35b96557 923 /* */
Kojto 99:dbbf35b96557 924 /******************************************************************************/
Kojto 99:dbbf35b96557 925 /************* Bit definition for COMP_CSR register (COMP1 and COMP2) **************/
Kojto 99:dbbf35b96557 926 /* COMP1 bits definition */
Kojto 119:aae6fcc7d9bb 927 #define COMP_CSR_COMP1EN ((uint32_t)0x00000001U) /*!< COMP1 enable */
Kojto 119:aae6fcc7d9bb 928 #define COMP_CSR_COMP1INNSEL ((uint32_t)0x00000030U) /*!< COMP1 inverting input select */
Kojto 119:aae6fcc7d9bb 929 #define COMP_CSR_COMP1INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP1 inverting input select bit 0 */
Kojto 119:aae6fcc7d9bb 930 #define COMP_CSR_COMP1INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP1 inverting input select bit 1 */
Kojto 119:aae6fcc7d9bb 931 #define COMP_CSR_COMP1WM ((uint32_t)0x00000100U) /*!< Comparators window mode enable */
Kojto 119:aae6fcc7d9bb 932 #define COMP_CSR_COMP1LPTIM1IN1 ((uint32_t)0x00001000U) /*!< COMP1 LPTIM1 IN1 connection */
Kojto 119:aae6fcc7d9bb 933 #define COMP_CSR_COMP1POLARITY ((uint32_t)0x00008000U) /*!< COMP1 output polarity */
Kojto 119:aae6fcc7d9bb 934 #define COMP_CSR_COMP1VALUE ((uint32_t)0x40000000U) /*!< COMP1 output level */
Kojto 119:aae6fcc7d9bb 935 #define COMP_CSR_COMP1LOCK ((uint32_t)0x80000000U) /*!< COMP1 lock */
Kojto 99:dbbf35b96557 936 /* COMP2 bits definition */
Kojto 119:aae6fcc7d9bb 937 #define COMP_CSR_COMP2EN ((uint32_t)0x00000001U) /*!< COMP2 enable */
Kojto 119:aae6fcc7d9bb 938 #define COMP_CSR_COMP2SPEED ((uint32_t)0x00000008U) /*!< COMP2 power mode */
Kojto 119:aae6fcc7d9bb 939 #define COMP_CSR_COMP2INNSEL ((uint32_t)0x00000070U) /*!< COMP2 inverting input select */
Kojto 119:aae6fcc7d9bb 940 #define COMP_CSR_COMP2INNSEL_0 ((uint32_t)0x00000010U) /*!< COMP2 inverting input select bit 0 */
Kojto 119:aae6fcc7d9bb 941 #define COMP_CSR_COMP2INNSEL_1 ((uint32_t)0x00000020U) /*!< COMP2 inverting input select bit 1 */
Kojto 119:aae6fcc7d9bb 942 #define COMP_CSR_COMP2INNSEL_2 ((uint32_t)0x00000040U) /*!< COMP2 inverting input select bit 2 */
Kojto 119:aae6fcc7d9bb 943 #define COMP_CSR_COMP2INPSEL ((uint32_t)0x00000700U) /*!< COMPx non inverting input select */
Kojto 119:aae6fcc7d9bb 944 #define COMP_CSR_COMP2INPSEL_0 ((uint32_t)0x00000100U) /*!< COMPx non inverting input select */
Kojto 119:aae6fcc7d9bb 945 #define COMP_CSR_COMP2INPSEL_1 ((uint32_t)0x00000200U) /*!< COMPx non inverting input select */
Kojto 119:aae6fcc7d9bb 946 #define COMP_CSR_COMP2INPSEL_2 ((uint32_t)0x00000400U) /*!< COMPx non inverting input select */
Kojto 119:aae6fcc7d9bb 947 #define COMP_CSR_COMP2LPTIM1IN2 ((uint32_t)0x00001000U) /*!< COMP2 LPTIM1 IN2 connection */
Kojto 119:aae6fcc7d9bb 948 #define COMP_CSR_COMP2LPTIM1IN1 ((uint32_t)0x00002000U) /*!< COMP2 LPTIM1 IN1 connection */
Kojto 119:aae6fcc7d9bb 949 #define COMP_CSR_COMP2POLARITY ((uint32_t)0x00008000U) /*!< COMP2 output polarity */
Kojto 119:aae6fcc7d9bb 950 #define COMP_CSR_COMP2VALUE ((uint32_t)0x40000000U) /*!< COMP2 output level */
Kojto 119:aae6fcc7d9bb 951 #define COMP_CSR_COMP2LOCK ((uint32_t)0x80000000U) /*!< COMP2 lock */
Kojto 99:dbbf35b96557 952
Kojto 99:dbbf35b96557 953 /********************** Bit definition for COMP_CSR register common ****************/
Kojto 119:aae6fcc7d9bb 954 #define COMP_CSR_COMPxEN ((uint32_t)0x00000001U) /*!< COMPx enable */
Kojto 119:aae6fcc7d9bb 955 #define COMP_CSR_COMPxPOLARITY ((uint32_t)0x00008000U) /*!< COMPx output polarity */
Kojto 119:aae6fcc7d9bb 956 #define COMP_CSR_COMPxOUTVALUE ((uint32_t)0x40000000U) /*!< COMPx output level */
Kojto 119:aae6fcc7d9bb 957 #define COMP_CSR_COMPxLOCK ((uint32_t)0x80000000U) /*!< COMPx lock */
Kojto 119:aae6fcc7d9bb 958
Kojto 119:aae6fcc7d9bb 959 /* Reference defines */
Kojto 119:aae6fcc7d9bb 960 #define COMP_CSR_WINMODE COMP_CSR_COMP1WM /*!< Bit intended to be used with COMP common instance (COMP_Common_TypeDef) */
Kojto 99:dbbf35b96557 961
Kojto 99:dbbf35b96557 962 /******************************************************************************/
Kojto 99:dbbf35b96557 963 /* */
Kojto 99:dbbf35b96557 964 /* CRC calculation unit (CRC) */
Kojto 99:dbbf35b96557 965 /* */
Kojto 99:dbbf35b96557 966 /******************************************************************************/
Kojto 99:dbbf35b96557 967 /******************* Bit definition for CRC_DR register *********************/
Kojto 119:aae6fcc7d9bb 968 #define CRC_DR_DR ((uint32_t)0xFFFFFFFFU) /*!< Data register bits */
Kojto 99:dbbf35b96557 969
Kojto 99:dbbf35b96557 970 /******************* Bit definition for CRC_IDR register ********************/
Kojto 119:aae6fcc7d9bb 971 #define CRC_IDR_IDR ((uint8_t)0xFFU) /*!< General-purpose 8-bit data register bits */
Kojto 99:dbbf35b96557 972
Kojto 99:dbbf35b96557 973 /******************** Bit definition for CRC_CR register ********************/
Kojto 119:aae6fcc7d9bb 974 #define CRC_CR_RESET ((uint32_t)0x00000001U) /*!< RESET the CRC computation unit bit */
Kojto 119:aae6fcc7d9bb 975 #define CRC_CR_POLYSIZE ((uint32_t)0x00000018U) /*!< Polynomial size bits */
Kojto 119:aae6fcc7d9bb 976 #define CRC_CR_POLYSIZE_0 ((uint32_t)0x00000008U) /*!< Polynomial size bit 0 */
Kojto 119:aae6fcc7d9bb 977 #define CRC_CR_POLYSIZE_1 ((uint32_t)0x00000010U) /*!< Polynomial size bit 1 */
Kojto 119:aae6fcc7d9bb 978 #define CRC_CR_REV_IN ((uint32_t)0x00000060U) /*!< REV_IN Reverse Input Data bits */
Kojto 119:aae6fcc7d9bb 979 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 980 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 981 #define CRC_CR_REV_OUT ((uint32_t)0x00000080U) /*!< REV_OUT Reverse Output Data bits */
Kojto 99:dbbf35b96557 982
Kojto 99:dbbf35b96557 983 /******************* Bit definition for CRC_INIT register *******************/
Kojto 119:aae6fcc7d9bb 984 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFFU) /*!< Initial CRC value bits */
Kojto 99:dbbf35b96557 985
Kojto 99:dbbf35b96557 986 /******************* Bit definition for CRC_POL register ********************/
Kojto 119:aae6fcc7d9bb 987 #define CRC_POL_POL ((uint32_t)0xFFFFFFFFU) /*!< Coefficients of the polynomial */
Kojto 99:dbbf35b96557 988
Kojto 99:dbbf35b96557 989 /******************************************************************************/
Kojto 99:dbbf35b96557 990 /* */
Kojto 99:dbbf35b96557 991 /* CRS Clock Recovery System */
Kojto 99:dbbf35b96557 992 /* */
Kojto 99:dbbf35b96557 993 /******************************************************************************/
Kojto 99:dbbf35b96557 994
Kojto 99:dbbf35b96557 995 /******************* Bit definition for CRS_CR register *********************/
Kojto 119:aae6fcc7d9bb 996 #define CRS_CR_SYNCOKIE ((uint32_t)0x00000001U) /* SYNC event OK interrupt enable */
Kojto 119:aae6fcc7d9bb 997 #define CRS_CR_SYNCWARNIE ((uint32_t)0x00000002U) /* SYNC warning interrupt enable */
Kojto 119:aae6fcc7d9bb 998 #define CRS_CR_ERRIE ((uint32_t)0x00000004U) /* SYNC error interrupt enable */
Kojto 119:aae6fcc7d9bb 999 #define CRS_CR_ESYNCIE ((uint32_t)0x00000008U) /* Expected SYNC(ESYNCF) interrupt Enable*/
Kojto 119:aae6fcc7d9bb 1000 #define CRS_CR_CEN ((uint32_t)0x00000020U) /* Frequency error counter enable */
Kojto 119:aae6fcc7d9bb 1001 #define CRS_CR_AUTOTRIMEN ((uint32_t)0x00000040U) /* Automatic trimming enable */
Kojto 119:aae6fcc7d9bb 1002 #define CRS_CR_SWSYNC ((uint32_t)0x00000080U) /* A Software SYNC event is generated */
Kojto 119:aae6fcc7d9bb 1003 #define CRS_CR_TRIM ((uint32_t)0x00003F00U) /* HSI48 oscillator smooth trimming */
Kojto 99:dbbf35b96557 1004
Kojto 99:dbbf35b96557 1005 /******************* Bit definition for CRS_CFGR register *********************/
Kojto 119:aae6fcc7d9bb 1006 #define CRS_CFGR_RELOAD ((uint32_t)0x0000FFFFU) /* Counter reload value */
Kojto 119:aae6fcc7d9bb 1007 #define CRS_CFGR_FELIM ((uint32_t)0x00FF0000U) /* Frequency error limit */
Kojto 119:aae6fcc7d9bb 1008
Kojto 119:aae6fcc7d9bb 1009 #define CRS_CFGR_SYNCDIV ((uint32_t)0x07000000U) /* SYNC divider */
Kojto 119:aae6fcc7d9bb 1010 #define CRS_CFGR_SYNCDIV_0 ((uint32_t)0x01000000U) /* Bit 0 */
Kojto 119:aae6fcc7d9bb 1011 #define CRS_CFGR_SYNCDIV_1 ((uint32_t)0x02000000U) /* Bit 1 */
Kojto 119:aae6fcc7d9bb 1012 #define CRS_CFGR_SYNCDIV_2 ((uint32_t)0x04000000U) /* Bit 2 */
Kojto 119:aae6fcc7d9bb 1013
Kojto 119:aae6fcc7d9bb 1014 #define CRS_CFGR_SYNCSRC ((uint32_t)0x30000000U) /* SYNC signal source selection */
Kojto 119:aae6fcc7d9bb 1015 #define CRS_CFGR_SYNCSRC_0 ((uint32_t)0x10000000U) /* Bit 0 */
Kojto 119:aae6fcc7d9bb 1016 #define CRS_CFGR_SYNCSRC_1 ((uint32_t)0x20000000U) /* Bit 1 */
Kojto 119:aae6fcc7d9bb 1017
Kojto 119:aae6fcc7d9bb 1018 #define CRS_CFGR_SYNCPOL ((uint32_t)0x80000000U) /* SYNC polarity selection */
Kojto 99:dbbf35b96557 1019
Kojto 99:dbbf35b96557 1020 /******************* Bit definition for CRS_ISR register *********************/
Kojto 119:aae6fcc7d9bb 1021 #define CRS_ISR_SYNCOKF ((uint32_t)0x00000001U) /* SYNC event OK flag */
Kojto 119:aae6fcc7d9bb 1022 #define CRS_ISR_SYNCWARNF ((uint32_t)0x00000002U) /* SYNC warning */
Kojto 119:aae6fcc7d9bb 1023 #define CRS_ISR_ERRF ((uint32_t)0x00000004U) /* SYNC error flag */
Kojto 119:aae6fcc7d9bb 1024 #define CRS_ISR_ESYNCF ((uint32_t)0x00000008U) /* Expected SYNC flag */
Kojto 119:aae6fcc7d9bb 1025 #define CRS_ISR_SYNCERR ((uint32_t)0x00000100U) /* SYNC error */
Kojto 119:aae6fcc7d9bb 1026 #define CRS_ISR_SYNCMISS ((uint32_t)0x00000200U) /* SYNC missed */
Kojto 119:aae6fcc7d9bb 1027 #define CRS_ISR_TRIMOVF ((uint32_t)0x00000400U) /* Trimming overflow or underflow */
Kojto 119:aae6fcc7d9bb 1028 #define CRS_ISR_FEDIR ((uint32_t)0x00008000U) /* Frequency error direction */
Kojto 119:aae6fcc7d9bb 1029 #define CRS_ISR_FECAP ((uint32_t)0xFFFF0000U) /* Frequency error capture */
Kojto 99:dbbf35b96557 1030
Kojto 99:dbbf35b96557 1031 /******************* Bit definition for CRS_ICR register *********************/
Kojto 119:aae6fcc7d9bb 1032 #define CRS_ICR_SYNCOKC ((uint32_t)0x00000001U) /* SYNC event OK clear flag */
Kojto 119:aae6fcc7d9bb 1033 #define CRS_ICR_SYNCWARNC ((uint32_t)0x00000002U) /* SYNC warning clear flag */
Kojto 119:aae6fcc7d9bb 1034 #define CRS_ICR_ERRC ((uint32_t)0x00000004U) /* Error clear flag */
Kojto 119:aae6fcc7d9bb 1035 #define CRS_ICR_ESYNCC ((uint32_t)0x00000008U) /* Expected SYNC clear flag */
Kojto 99:dbbf35b96557 1036
Kojto 99:dbbf35b96557 1037 /******************************************************************************/
Kojto 99:dbbf35b96557 1038 /* */
Kojto 99:dbbf35b96557 1039 /* Digital to Analog Converter (DAC) */
Kojto 99:dbbf35b96557 1040 /* */
Kojto 99:dbbf35b96557 1041 /******************************************************************************/
Kojto 119:aae6fcc7d9bb 1042
Kojto 119:aae6fcc7d9bb 1043 /*
Kojto 119:aae6fcc7d9bb 1044 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
Kojto 119:aae6fcc7d9bb 1045 */
Kojto 119:aae6fcc7d9bb 1046 /* Note: No specific macro feature on this device */
Kojto 119:aae6fcc7d9bb 1047
Kojto 99:dbbf35b96557 1048 /******************** Bit definition for DAC_CR register ********************/
Kojto 119:aae6fcc7d9bb 1049 #define DAC_CR_EN1 ((uint32_t)0x00000001U) /*!< DAC channel1 enable */
Kojto 119:aae6fcc7d9bb 1050 #define DAC_CR_BOFF1 ((uint32_t)0x00000002U) /*!< DAC channel1 output buffer disable */
Kojto 119:aae6fcc7d9bb 1051 #define DAC_CR_TEN1 ((uint32_t)0x00000004U) /*!< DAC channel1 Trigger enable */
Kojto 119:aae6fcc7d9bb 1052
Kojto 119:aae6fcc7d9bb 1053 #define DAC_CR_TSEL1 ((uint32_t)0x00000038U) /*!< TSEL1[2:0] (DAC channel1 Trigger selection) */
Kojto 119:aae6fcc7d9bb 1054 #define DAC_CR_TSEL1_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1055 #define DAC_CR_TSEL1_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1056 #define DAC_CR_TSEL1_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 1057
Kojto 119:aae6fcc7d9bb 1058 #define DAC_CR_WAVE1 ((uint32_t)0x000000C0U) /*!< WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
Kojto 119:aae6fcc7d9bb 1059 #define DAC_CR_WAVE1_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1060 #define DAC_CR_WAVE1_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1061
Kojto 119:aae6fcc7d9bb 1062 #define DAC_CR_MAMP1 ((uint32_t)0x00000F00U) /*!< MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
Kojto 119:aae6fcc7d9bb 1063 #define DAC_CR_MAMP1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1064 #define DAC_CR_MAMP1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1065 #define DAC_CR_MAMP1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 1066 #define DAC_CR_MAMP1_3 ((uint32_t)0x00000800U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 1067
Kojto 119:aae6fcc7d9bb 1068 #define DAC_CR_DMAEN1 ((uint32_t)0x00001000U) /*!< DAC channel1 DMA enable */
Kojto 119:aae6fcc7d9bb 1069 #define DAC_CR_DMAUDRIE1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA Underrun interrupt enable */
Kojto 99:dbbf35b96557 1070
Kojto 99:dbbf35b96557 1071 /***************** Bit definition for DAC_SWTRIGR register ******************/
Kojto 119:aae6fcc7d9bb 1072 #define DAC_SWTRIGR_SWTRIG1 ((uint32_t)0x00000001U) /*!< DAC channel1 software trigger */
Kojto 99:dbbf35b96557 1073
Kojto 99:dbbf35b96557 1074 /***************** Bit definition for DAC_DHR12R1 register ******************/
Kojto 119:aae6fcc7d9bb 1075 #define DAC_DHR12R1_DACC1DHR ((uint32_t)0x00000FFFU) /*!< DAC channel1 12-bit Right aligned data */
Kojto 99:dbbf35b96557 1076
Kojto 99:dbbf35b96557 1077 /***************** Bit definition for DAC_DHR12L1 register ******************/
Kojto 119:aae6fcc7d9bb 1078 #define DAC_DHR12L1_DACC1DHR ((uint32_t)0x0000FFF0U) /*!< DAC channel1 12-bit Left aligned data */
Kojto 99:dbbf35b96557 1079
Kojto 99:dbbf35b96557 1080 /****************** Bit definition for DAC_DHR8R1 register ******************/
Kojto 119:aae6fcc7d9bb 1081 #define DAC_DHR8R1_DACC1DHR ((uint32_t)0x000000FFU) /*!< DAC channel1 8-bit Right aligned data */
Kojto 99:dbbf35b96557 1082
Kojto 99:dbbf35b96557 1083 /******************* Bit definition for DAC_DOR1 register *******************/
Kojto 119:aae6fcc7d9bb 1084 #define DAC_DOR1_DACC1DOR ((uint16_t)0x00000FFFU) /*!< DAC channel1 data output */
Kojto 99:dbbf35b96557 1085
Kojto 99:dbbf35b96557 1086 /******************** Bit definition for DAC_SR register ********************/
Kojto 119:aae6fcc7d9bb 1087 #define DAC_SR_DMAUDR1 ((uint32_t)0x00002000U) /*!< DAC channel1 DMA underrun flag */
Kojto 99:dbbf35b96557 1088
Kojto 99:dbbf35b96557 1089 /******************************************************************************/
Kojto 99:dbbf35b96557 1090 /* */
Kojto 99:dbbf35b96557 1091 /* Debug MCU (DBGMCU) */
Kojto 99:dbbf35b96557 1092 /* */
Kojto 99:dbbf35b96557 1093 /******************************************************************************/
Kojto 99:dbbf35b96557 1094
Kojto 99:dbbf35b96557 1095 /**************** Bit definition for DBGMCU_IDCODE register *****************/
Kojto 119:aae6fcc7d9bb 1096 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFFU) /*!< Device Identifier */
Kojto 119:aae6fcc7d9bb 1097
Kojto 119:aae6fcc7d9bb 1098 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000U) /*!< REV_ID[15:0] bits (Revision Identifier) */
Kojto 119:aae6fcc7d9bb 1099 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1100 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1101 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 1102 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 1103 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
Kojto 119:aae6fcc7d9bb 1104 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000U) /*!< Bit 5 */
Kojto 119:aae6fcc7d9bb 1105 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000U) /*!< Bit 6 */
Kojto 119:aae6fcc7d9bb 1106 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000U) /*!< Bit 7 */
Kojto 119:aae6fcc7d9bb 1107 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000U) /*!< Bit 8 */
Kojto 119:aae6fcc7d9bb 1108 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000U) /*!< Bit 9 */
Kojto 119:aae6fcc7d9bb 1109 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000U) /*!< Bit 10 */
Kojto 119:aae6fcc7d9bb 1110 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000U) /*!< Bit 11 */
Kojto 119:aae6fcc7d9bb 1111 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000U) /*!< Bit 12 */
Kojto 119:aae6fcc7d9bb 1112 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000U) /*!< Bit 13 */
Kojto 119:aae6fcc7d9bb 1113 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000U) /*!< Bit 14 */
Kojto 119:aae6fcc7d9bb 1114 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000U) /*!< Bit 15 */
Kojto 99:dbbf35b96557 1115
Kojto 99:dbbf35b96557 1116 /****************** Bit definition for DBGMCU_CR register *******************/
Kojto 119:aae6fcc7d9bb 1117 #define DBGMCU_CR_DBG ((uint32_t)0x00000007U) /*!< Debug mode mask */
Kojto 119:aae6fcc7d9bb 1118 #define DBGMCU_CR_DBG_SLEEP ((uint32_t)0x00000001U) /*!< Debug Sleep Mode */
Kojto 119:aae6fcc7d9bb 1119 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002U) /*!< Debug Stop Mode */
Kojto 119:aae6fcc7d9bb 1120 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004U) /*!< Debug Standby mode */
Kojto 99:dbbf35b96557 1121
Kojto 99:dbbf35b96557 1122 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
Kojto 119:aae6fcc7d9bb 1123 #define DBGMCU_APB1_FZ_DBG_TIM2_STOP ((uint32_t)0x00000001U) /*!< TIM2 counter stopped when core is halted */
Kojto 119:aae6fcc7d9bb 1124 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010U) /*!< TIM6 counter stopped when core is halted */
Kojto 119:aae6fcc7d9bb 1125 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400U) /*!< RTC Calendar frozen when core is halted */
Kojto 119:aae6fcc7d9bb 1126 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800U) /*!< Debug Window Watchdog stopped when Core is halted */
Kojto 119:aae6fcc7d9bb 1127 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000U) /*!< Debug Independent Watchdog stopped when Core is halted */
Kojto 119:aae6fcc7d9bb 1128 #define DBGMCU_APB1_FZ_DBG_I2C1_STOP ((uint32_t)0x00200000U) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
Kojto 119:aae6fcc7d9bb 1129 #define DBGMCU_APB1_FZ_DBG_I2C2_STOP ((uint32_t)0x00400000U) /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
Kojto 119:aae6fcc7d9bb 1130 #define DBGMCU_APB1_FZ_DBG_LPTIMER_STOP ((uint32_t)0x80000000U) /*!< LPTIM1 counter stopped when core is halted */
Kojto 99:dbbf35b96557 1131 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
Kojto 119:aae6fcc7d9bb 1132 #define DBGMCU_APB2_FZ_DBG_TIM22_STOP ((uint32_t)0x00000020U) /*!< TIM22 counter stopped when core is halted */
Kojto 119:aae6fcc7d9bb 1133 #define DBGMCU_APB2_FZ_DBG_TIM21_STOP ((uint32_t)0x00000004U) /*!< TIM21 counter stopped when core is halted */
Kojto 99:dbbf35b96557 1134
Kojto 99:dbbf35b96557 1135 /******************************************************************************/
Kojto 99:dbbf35b96557 1136 /* */
Kojto 99:dbbf35b96557 1137 /* DMA Controller (DMA) */
Kojto 99:dbbf35b96557 1138 /* */
Kojto 99:dbbf35b96557 1139 /******************************************************************************/
Kojto 99:dbbf35b96557 1140
Kojto 99:dbbf35b96557 1141 /******************* Bit definition for DMA_ISR register ********************/
Kojto 119:aae6fcc7d9bb 1142 #define DMA_ISR_GIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt flag */
Kojto 119:aae6fcc7d9bb 1143 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete flag */
Kojto 119:aae6fcc7d9bb 1144 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer flag */
Kojto 119:aae6fcc7d9bb 1145 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error flag */
Kojto 119:aae6fcc7d9bb 1146 #define DMA_ISR_GIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt flag */
Kojto 119:aae6fcc7d9bb 1147 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete flag */
Kojto 119:aae6fcc7d9bb 1148 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer flag */
Kojto 119:aae6fcc7d9bb 1149 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error flag */
Kojto 119:aae6fcc7d9bb 1150 #define DMA_ISR_GIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt flag */
Kojto 119:aae6fcc7d9bb 1151 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete flag */
Kojto 119:aae6fcc7d9bb 1152 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer flag */
Kojto 119:aae6fcc7d9bb 1153 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error flag */
Kojto 119:aae6fcc7d9bb 1154 #define DMA_ISR_GIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt flag */
Kojto 119:aae6fcc7d9bb 1155 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete flag */
Kojto 119:aae6fcc7d9bb 1156 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer flag */
Kojto 119:aae6fcc7d9bb 1157 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error flag */
Kojto 119:aae6fcc7d9bb 1158 #define DMA_ISR_GIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt flag */
Kojto 119:aae6fcc7d9bb 1159 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete flag */
Kojto 119:aae6fcc7d9bb 1160 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer flag */
Kojto 119:aae6fcc7d9bb 1161 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error flag */
Kojto 119:aae6fcc7d9bb 1162 #define DMA_ISR_GIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt flag */
Kojto 119:aae6fcc7d9bb 1163 #define DMA_ISR_TCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete flag */
Kojto 119:aae6fcc7d9bb 1164 #define DMA_ISR_HTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer flag */
Kojto 119:aae6fcc7d9bb 1165 #define DMA_ISR_TEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error flag */
Kojto 119:aae6fcc7d9bb 1166 #define DMA_ISR_GIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt flag */
Kojto 119:aae6fcc7d9bb 1167 #define DMA_ISR_TCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete flag */
Kojto 119:aae6fcc7d9bb 1168 #define DMA_ISR_HTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer flag */
Kojto 119:aae6fcc7d9bb 1169 #define DMA_ISR_TEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error flag */
Kojto 99:dbbf35b96557 1170
Kojto 99:dbbf35b96557 1171 /******************* Bit definition for DMA_IFCR register *******************/
Kojto 119:aae6fcc7d9bb 1172 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001U) /*!< Channel 1 Global interrupt clear */
Kojto 119:aae6fcc7d9bb 1173 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002U) /*!< Channel 1 Transfer Complete clear */
Kojto 119:aae6fcc7d9bb 1174 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004U) /*!< Channel 1 Half Transfer clear */
Kojto 119:aae6fcc7d9bb 1175 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008U) /*!< Channel 1 Transfer Error clear */
Kojto 119:aae6fcc7d9bb 1176 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010U) /*!< Channel 2 Global interrupt clear */
Kojto 119:aae6fcc7d9bb 1177 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020U) /*!< Channel 2 Transfer Complete clear */
Kojto 119:aae6fcc7d9bb 1178 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040U) /*!< Channel 2 Half Transfer clear */
Kojto 119:aae6fcc7d9bb 1179 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080U) /*!< Channel 2 Transfer Error clear */
Kojto 119:aae6fcc7d9bb 1180 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100U) /*!< Channel 3 Global interrupt clear */
Kojto 119:aae6fcc7d9bb 1181 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200U) /*!< Channel 3 Transfer Complete clear */
Kojto 119:aae6fcc7d9bb 1182 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400U) /*!< Channel 3 Half Transfer clear */
Kojto 119:aae6fcc7d9bb 1183 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800U) /*!< Channel 3 Transfer Error clear */
Kojto 119:aae6fcc7d9bb 1184 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000U) /*!< Channel 4 Global interrupt clear */
Kojto 119:aae6fcc7d9bb 1185 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000U) /*!< Channel 4 Transfer Complete clear */
Kojto 119:aae6fcc7d9bb 1186 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000U) /*!< Channel 4 Half Transfer clear */
Kojto 119:aae6fcc7d9bb 1187 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000U) /*!< Channel 4 Transfer Error clear */
Kojto 119:aae6fcc7d9bb 1188 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000U) /*!< Channel 5 Global interrupt clear */
Kojto 119:aae6fcc7d9bb 1189 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000U) /*!< Channel 5 Transfer Complete clear */
Kojto 119:aae6fcc7d9bb 1190 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000U) /*!< Channel 5 Half Transfer clear */
Kojto 119:aae6fcc7d9bb 1191 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000U) /*!< Channel 5 Transfer Error clear */
Kojto 119:aae6fcc7d9bb 1192 #define DMA_IFCR_CGIF6 ((uint32_t)0x00100000U) /*!< Channel 6 Global interrupt clear */
Kojto 119:aae6fcc7d9bb 1193 #define DMA_IFCR_CTCIF6 ((uint32_t)0x00200000U) /*!< Channel 6 Transfer Complete clear */
Kojto 119:aae6fcc7d9bb 1194 #define DMA_IFCR_CHTIF6 ((uint32_t)0x00400000U) /*!< Channel 6 Half Transfer clear */
Kojto 119:aae6fcc7d9bb 1195 #define DMA_IFCR_CTEIF6 ((uint32_t)0x00800000U) /*!< Channel 6 Transfer Error clear */
Kojto 119:aae6fcc7d9bb 1196 #define DMA_IFCR_CGIF7 ((uint32_t)0x01000000U) /*!< Channel 7 Global interrupt clear */
Kojto 119:aae6fcc7d9bb 1197 #define DMA_IFCR_CTCIF7 ((uint32_t)0x02000000U) /*!< Channel 7 Transfer Complete clear */
Kojto 119:aae6fcc7d9bb 1198 #define DMA_IFCR_CHTIF7 ((uint32_t)0x04000000U) /*!< Channel 7 Half Transfer clear */
Kojto 119:aae6fcc7d9bb 1199 #define DMA_IFCR_CTEIF7 ((uint32_t)0x08000000U) /*!< Channel 7 Transfer Error clear */
Kojto 99:dbbf35b96557 1200
Kojto 99:dbbf35b96557 1201 /******************* Bit definition for DMA_CCR register ********************/
Kojto 119:aae6fcc7d9bb 1202 #define DMA_CCR_EN ((uint32_t)0x00000001U) /*!< Channel enable */
Kojto 119:aae6fcc7d9bb 1203 #define DMA_CCR_TCIE ((uint32_t)0x00000002U) /*!< Transfer complete interrupt enable */
Kojto 119:aae6fcc7d9bb 1204 #define DMA_CCR_HTIE ((uint32_t)0x00000004U) /*!< Half Transfer interrupt enable */
Kojto 119:aae6fcc7d9bb 1205 #define DMA_CCR_TEIE ((uint32_t)0x00000008U) /*!< Transfer error interrupt enable */
Kojto 119:aae6fcc7d9bb 1206 #define DMA_CCR_DIR ((uint32_t)0x00000010U) /*!< Data transfer direction */
Kojto 119:aae6fcc7d9bb 1207 #define DMA_CCR_CIRC ((uint32_t)0x00000020U) /*!< Circular mode */
Kojto 119:aae6fcc7d9bb 1208 #define DMA_CCR_PINC ((uint32_t)0x00000040U) /*!< Peripheral increment mode */
Kojto 119:aae6fcc7d9bb 1209 #define DMA_CCR_MINC ((uint32_t)0x00000080U) /*!< Memory increment mode */
Kojto 119:aae6fcc7d9bb 1210
Kojto 119:aae6fcc7d9bb 1211 #define DMA_CCR_PSIZE ((uint32_t)0x00000300U) /*!< PSIZE[1:0] bits (Peripheral size) */
Kojto 119:aae6fcc7d9bb 1212 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1213 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1214
Kojto 119:aae6fcc7d9bb 1215 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00U) /*!< MSIZE[1:0] bits (Memory size) */
Kojto 119:aae6fcc7d9bb 1216 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1217 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1218
Kojto 119:aae6fcc7d9bb 1219 #define DMA_CCR_PL ((uint32_t)0x00003000U) /*!< PL[1:0] bits(Channel Priority level)*/
Kojto 119:aae6fcc7d9bb 1220 #define DMA_CCR_PL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1221 #define DMA_CCR_PL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1222
Kojto 119:aae6fcc7d9bb 1223 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000U) /*!< Memory to memory mode */
Kojto 99:dbbf35b96557 1224
Kojto 99:dbbf35b96557 1225 /****************** Bit definition for DMA_CNDTR register *******************/
Kojto 119:aae6fcc7d9bb 1226 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFFU) /*!< Number of data to Transfer */
Kojto 99:dbbf35b96557 1227
Kojto 99:dbbf35b96557 1228 /****************** Bit definition for DMA_CPAR register ********************/
Kojto 119:aae6fcc7d9bb 1229 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFFU) /*!< Peripheral Address */
Kojto 99:dbbf35b96557 1230
Kojto 99:dbbf35b96557 1231 /****************** Bit definition for DMA_CMAR register ********************/
Kojto 119:aae6fcc7d9bb 1232 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFFU) /*!< Memory Address */
Kojto 99:dbbf35b96557 1233
Kojto 99:dbbf35b96557 1234
Kojto 99:dbbf35b96557 1235 /******************* Bit definition for DMA_CSELR register *******************/
Kojto 119:aae6fcc7d9bb 1236 #define DMA_CSELR_C1S ((uint32_t)0x0000000FU) /*!< Channel 1 Selection */
Kojto 119:aae6fcc7d9bb 1237 #define DMA_CSELR_C2S ((uint32_t)0x000000F0U) /*!< Channel 2 Selection */
Kojto 119:aae6fcc7d9bb 1238 #define DMA_CSELR_C3S ((uint32_t)0x00000F00U) /*!< Channel 3 Selection */
Kojto 119:aae6fcc7d9bb 1239 #define DMA_CSELR_C4S ((uint32_t)0x0000F000U) /*!< Channel 4 Selection */
Kojto 119:aae6fcc7d9bb 1240 #define DMA_CSELR_C5S ((uint32_t)0x000F0000U) /*!< Channel 5 Selection */
Kojto 119:aae6fcc7d9bb 1241 #define DMA_CSELR_C6S ((uint32_t)0x00F00000U) /*!< Channel 6 Selection */
Kojto 119:aae6fcc7d9bb 1242 #define DMA_CSELR_C7S ((uint32_t)0x0F000000U) /*!< Channel 7 Selection */
Kojto 99:dbbf35b96557 1243
Kojto 99:dbbf35b96557 1244
Kojto 99:dbbf35b96557 1245 /******************************************************************************/
Kojto 99:dbbf35b96557 1246 /* */
Kojto 99:dbbf35b96557 1247 /* External Interrupt/Event Controller (EXTI) */
Kojto 99:dbbf35b96557 1248 /* */
Kojto 99:dbbf35b96557 1249 /******************************************************************************/
Kojto 99:dbbf35b96557 1250
Kojto 99:dbbf35b96557 1251 /******************* Bit definition for EXTI_IMR register *******************/
Kojto 119:aae6fcc7d9bb 1252 #define EXTI_IMR_IM0 ((uint32_t)0x00000001U) /*!< Interrupt Mask on line 0 */
Kojto 119:aae6fcc7d9bb 1253 #define EXTI_IMR_IM1 ((uint32_t)0x00000002U) /*!< Interrupt Mask on line 1 */
Kojto 119:aae6fcc7d9bb 1254 #define EXTI_IMR_IM2 ((uint32_t)0x00000004U) /*!< Interrupt Mask on line 2 */
Kojto 119:aae6fcc7d9bb 1255 #define EXTI_IMR_IM3 ((uint32_t)0x00000008U) /*!< Interrupt Mask on line 3 */
Kojto 119:aae6fcc7d9bb 1256 #define EXTI_IMR_IM4 ((uint32_t)0x00000010U) /*!< Interrupt Mask on line 4 */
Kojto 119:aae6fcc7d9bb 1257 #define EXTI_IMR_IM5 ((uint32_t)0x00000020U) /*!< Interrupt Mask on line 5 */
Kojto 119:aae6fcc7d9bb 1258 #define EXTI_IMR_IM6 ((uint32_t)0x00000040U) /*!< Interrupt Mask on line 6 */
Kojto 119:aae6fcc7d9bb 1259 #define EXTI_IMR_IM7 ((uint32_t)0x00000080U) /*!< Interrupt Mask on line 7 */
Kojto 119:aae6fcc7d9bb 1260 #define EXTI_IMR_IM8 ((uint32_t)0x00000100U) /*!< Interrupt Mask on line 8 */
Kojto 119:aae6fcc7d9bb 1261 #define EXTI_IMR_IM9 ((uint32_t)0x00000200U) /*!< Interrupt Mask on line 9 */
Kojto 119:aae6fcc7d9bb 1262 #define EXTI_IMR_IM10 ((uint32_t)0x00000400U) /*!< Interrupt Mask on line 10 */
Kojto 119:aae6fcc7d9bb 1263 #define EXTI_IMR_IM11 ((uint32_t)0x00000800U) /*!< Interrupt Mask on line 11 */
Kojto 119:aae6fcc7d9bb 1264 #define EXTI_IMR_IM12 ((uint32_t)0x00001000U) /*!< Interrupt Mask on line 12 */
Kojto 119:aae6fcc7d9bb 1265 #define EXTI_IMR_IM13 ((uint32_t)0x00002000U) /*!< Interrupt Mask on line 13 */
Kojto 119:aae6fcc7d9bb 1266 #define EXTI_IMR_IM14 ((uint32_t)0x00004000U) /*!< Interrupt Mask on line 14 */
Kojto 119:aae6fcc7d9bb 1267 #define EXTI_IMR_IM15 ((uint32_t)0x00008000U) /*!< Interrupt Mask on line 15 */
Kojto 119:aae6fcc7d9bb 1268 #define EXTI_IMR_IM16 ((uint32_t)0x00010000U) /*!< Interrupt Mask on line 16 */
Kojto 119:aae6fcc7d9bb 1269 #define EXTI_IMR_IM17 ((uint32_t)0x00020000U) /*!< Interrupt Mask on line 17 */
Kojto 119:aae6fcc7d9bb 1270 #define EXTI_IMR_IM18 ((uint32_t)0x00040000U) /*!< Interrupt Mask on line 18 */
Kojto 119:aae6fcc7d9bb 1271 #define EXTI_IMR_IM19 ((uint32_t)0x00080000U) /*!< Interrupt Mask on line 19 */
Kojto 119:aae6fcc7d9bb 1272 #define EXTI_IMR_IM20 ((uint32_t)0x00100000U) /*!< Interrupt Mask on line 20 */
Kojto 119:aae6fcc7d9bb 1273 #define EXTI_IMR_IM21 ((uint32_t)0x00200000U) /*!< Interrupt Mask on line 21 */
Kojto 119:aae6fcc7d9bb 1274 #define EXTI_IMR_IM22 ((uint32_t)0x00400000U) /*!< Interrupt Mask on line 22 */
Kojto 119:aae6fcc7d9bb 1275 #define EXTI_IMR_IM23 ((uint32_t)0x00800000U) /*!< Interrupt Mask on line 23 */
Kojto 119:aae6fcc7d9bb 1276 #define EXTI_IMR_IM25 ((uint32_t)0x02000000U) /*!< Interrupt Mask on line 25 */
Kojto 119:aae6fcc7d9bb 1277 #define EXTI_IMR_IM26 ((uint32_t)0x04000000U) /*!< Interrupt Mask on line 26 */
Kojto 119:aae6fcc7d9bb 1278 #define EXTI_IMR_IM28 ((uint32_t)0x10000000U) /*!< Interrupt Mask on line 28 */
Kojto 119:aae6fcc7d9bb 1279 #define EXTI_IMR_IM29 ((uint32_t)0x20000000U) /*!< Interrupt Mask on line 29 */
Kojto 99:dbbf35b96557 1280
Kojto 99:dbbf35b96557 1281 /****************** Bit definition for EXTI_EMR register ********************/
Kojto 119:aae6fcc7d9bb 1282 #define EXTI_EMR_EM0 ((uint32_t)0x00000001U) /*!< Event Mask on line 0 */
Kojto 119:aae6fcc7d9bb 1283 #define EXTI_EMR_EM1 ((uint32_t)0x00000002U) /*!< Event Mask on line 1 */
Kojto 119:aae6fcc7d9bb 1284 #define EXTI_EMR_EM2 ((uint32_t)0x00000004U) /*!< Event Mask on line 2 */
Kojto 119:aae6fcc7d9bb 1285 #define EXTI_EMR_EM3 ((uint32_t)0x00000008U) /*!< Event Mask on line 3 */
Kojto 119:aae6fcc7d9bb 1286 #define EXTI_EMR_EM4 ((uint32_t)0x00000010U) /*!< Event Mask on line 4 */
Kojto 119:aae6fcc7d9bb 1287 #define EXTI_EMR_EM5 ((uint32_t)0x00000020U) /*!< Event Mask on line 5 */
Kojto 119:aae6fcc7d9bb 1288 #define EXTI_EMR_EM6 ((uint32_t)0x00000040U) /*!< Event Mask on line 6 */
Kojto 119:aae6fcc7d9bb 1289 #define EXTI_EMR_EM7 ((uint32_t)0x00000080U) /*!< Event Mask on line 7 */
Kojto 119:aae6fcc7d9bb 1290 #define EXTI_EMR_EM8 ((uint32_t)0x00000100U) /*!< Event Mask on line 8 */
Kojto 119:aae6fcc7d9bb 1291 #define EXTI_EMR_EM9 ((uint32_t)0x00000200U) /*!< Event Mask on line 9 */
Kojto 119:aae6fcc7d9bb 1292 #define EXTI_EMR_EM10 ((uint32_t)0x00000400U) /*!< Event Mask on line 10 */
Kojto 119:aae6fcc7d9bb 1293 #define EXTI_EMR_EM11 ((uint32_t)0x00000800U) /*!< Event Mask on line 11 */
Kojto 119:aae6fcc7d9bb 1294 #define EXTI_EMR_EM12 ((uint32_t)0x00001000U) /*!< Event Mask on line 12 */
Kojto 119:aae6fcc7d9bb 1295 #define EXTI_EMR_EM13 ((uint32_t)0x00002000U) /*!< Event Mask on line 13 */
Kojto 119:aae6fcc7d9bb 1296 #define EXTI_EMR_EM14 ((uint32_t)0x00004000U) /*!< Event Mask on line 14 */
Kojto 119:aae6fcc7d9bb 1297 #define EXTI_EMR_EM15 ((uint32_t)0x00008000U) /*!< Event Mask on line 15 */
Kojto 119:aae6fcc7d9bb 1298 #define EXTI_EMR_EM16 ((uint32_t)0x00010000U) /*!< Event Mask on line 16 */
Kojto 119:aae6fcc7d9bb 1299 #define EXTI_EMR_EM17 ((uint32_t)0x00020000U) /*!< Event Mask on line 17 */
Kojto 119:aae6fcc7d9bb 1300 #define EXTI_EMR_EM18 ((uint32_t)0x00040000U) /*!< Event Mask on line 18 */
Kojto 119:aae6fcc7d9bb 1301 #define EXTI_EMR_EM19 ((uint32_t)0x00080000U) /*!< Event Mask on line 19 */
Kojto 119:aae6fcc7d9bb 1302 #define EXTI_EMR_EM20 ((uint32_t)0x00100000U) /*!< Event Mask on line 20 */
Kojto 119:aae6fcc7d9bb 1303 #define EXTI_EMR_EM21 ((uint32_t)0x00200000U) /*!< Event Mask on line 21 */
Kojto 119:aae6fcc7d9bb 1304 #define EXTI_EMR_EM22 ((uint32_t)0x00400000U) /*!< Event Mask on line 22 */
Kojto 119:aae6fcc7d9bb 1305 #define EXTI_EMR_EM23 ((uint32_t)0x00800000U) /*!< Event Mask on line 23 */
Kojto 119:aae6fcc7d9bb 1306 #define EXTI_EMR_EM25 ((uint32_t)0x02000000U) /*!< Event Mask on line 25 */
Kojto 119:aae6fcc7d9bb 1307 #define EXTI_EMR_EM26 ((uint32_t)0x04000000U) /*!< Event Mask on line 26 */
Kojto 119:aae6fcc7d9bb 1308 #define EXTI_EMR_EM28 ((uint32_t)0x10000000U) /*!< Event Mask on line 28 */
Kojto 119:aae6fcc7d9bb 1309 #define EXTI_EMR_EM29 ((uint32_t)0x20000000U) /*!< Event Mask on line 29 */
Kojto 99:dbbf35b96557 1310
Kojto 99:dbbf35b96557 1311 /******************* Bit definition for EXTI_RTSR register ******************/
Kojto 119:aae6fcc7d9bb 1312 #define EXTI_RTSR_RT0 ((uint32_t)0x00000001U) /*!< Rising trigger event configuration bit of line 0 */
Kojto 119:aae6fcc7d9bb 1313 #define EXTI_RTSR_RT1 ((uint32_t)0x00000002U) /*!< Rising trigger event configuration bit of line 1 */
Kojto 119:aae6fcc7d9bb 1314 #define EXTI_RTSR_RT2 ((uint32_t)0x00000004U) /*!< Rising trigger event configuration bit of line 2 */
Kojto 119:aae6fcc7d9bb 1315 #define EXTI_RTSR_RT3 ((uint32_t)0x00000008U) /*!< Rising trigger event configuration bit of line 3 */
Kojto 119:aae6fcc7d9bb 1316 #define EXTI_RTSR_RT4 ((uint32_t)0x00000010U) /*!< Rising trigger event configuration bit of line 4 */
Kojto 119:aae6fcc7d9bb 1317 #define EXTI_RTSR_RT5 ((uint32_t)0x00000020U) /*!< Rising trigger event configuration bit of line 5 */
Kojto 119:aae6fcc7d9bb 1318 #define EXTI_RTSR_RT6 ((uint32_t)0x00000040U) /*!< Rising trigger event configuration bit of line 6 */
Kojto 119:aae6fcc7d9bb 1319 #define EXTI_RTSR_RT7 ((uint32_t)0x00000080U) /*!< Rising trigger event configuration bit of line 7 */
Kojto 119:aae6fcc7d9bb 1320 #define EXTI_RTSR_RT8 ((uint32_t)0x00000100U) /*!< Rising trigger event configuration bit of line 8 */
Kojto 119:aae6fcc7d9bb 1321 #define EXTI_RTSR_RT9 ((uint32_t)0x00000200U) /*!< Rising trigger event configuration bit of line 9 */
Kojto 119:aae6fcc7d9bb 1322 #define EXTI_RTSR_RT10 ((uint32_t)0x00000400U) /*!< Rising trigger event configuration bit of line 10 */
Kojto 119:aae6fcc7d9bb 1323 #define EXTI_RTSR_RT11 ((uint32_t)0x00000800U) /*!< Rising trigger event configuration bit of line 11 */
Kojto 119:aae6fcc7d9bb 1324 #define EXTI_RTSR_RT12 ((uint32_t)0x00001000U) /*!< Rising trigger event configuration bit of line 12 */
Kojto 119:aae6fcc7d9bb 1325 #define EXTI_RTSR_RT13 ((uint32_t)0x00002000U) /*!< Rising trigger event configuration bit of line 13 */
Kojto 119:aae6fcc7d9bb 1326 #define EXTI_RTSR_RT14 ((uint32_t)0x00004000U) /*!< Rising trigger event configuration bit of line 14 */
Kojto 119:aae6fcc7d9bb 1327 #define EXTI_RTSR_RT15 ((uint32_t)0x00008000U) /*!< Rising trigger event configuration bit of line 15 */
Kojto 119:aae6fcc7d9bb 1328 #define EXTI_RTSR_RT16 ((uint32_t)0x00010000U) /*!< Rising trigger event configuration bit of line 16 */
Kojto 119:aae6fcc7d9bb 1329 #define EXTI_RTSR_RT17 ((uint32_t)0x00020000U) /*!< Rising trigger event configuration bit of line 17 */
Kojto 119:aae6fcc7d9bb 1330 #define EXTI_RTSR_RT19 ((uint32_t)0x00080000U) /*!< Rising trigger event configuration bit of line 19 */
Kojto 119:aae6fcc7d9bb 1331 #define EXTI_RTSR_RT20 ((uint32_t)0x00100000U) /*!< Rising trigger event configuration bit of line 20 */
Kojto 119:aae6fcc7d9bb 1332 #define EXTI_RTSR_RT21 ((uint32_t)0x00200000U) /*!< Rising trigger event configuration bit of line 21 */
Kojto 119:aae6fcc7d9bb 1333 #define EXTI_RTSR_RT22 ((uint32_t)0x00400000U) /*!< Rising trigger event configuration bit of line 22 */
Kojto 119:aae6fcc7d9bb 1334
Kojto 119:aae6fcc7d9bb 1335 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 1336 #define EXTI_RTSR_TR0 EXTI_RTSR_RT0
Kojto 119:aae6fcc7d9bb 1337 #define EXTI_RTSR_TR1 EXTI_RTSR_RT1
Kojto 119:aae6fcc7d9bb 1338 #define EXTI_RTSR_TR2 EXTI_RTSR_RT2
Kojto 119:aae6fcc7d9bb 1339 #define EXTI_RTSR_TR3 EXTI_RTSR_RT3
Kojto 119:aae6fcc7d9bb 1340 #define EXTI_RTSR_TR4 EXTI_RTSR_RT4
Kojto 119:aae6fcc7d9bb 1341 #define EXTI_RTSR_TR5 EXTI_RTSR_RT5
Kojto 119:aae6fcc7d9bb 1342 #define EXTI_RTSR_TR6 EXTI_RTSR_RT6
Kojto 119:aae6fcc7d9bb 1343 #define EXTI_RTSR_TR7 EXTI_RTSR_RT7
Kojto 119:aae6fcc7d9bb 1344 #define EXTI_RTSR_TR8 EXTI_RTSR_RT8
Kojto 119:aae6fcc7d9bb 1345 #define EXTI_RTSR_TR9 EXTI_RTSR_RT9
Kojto 119:aae6fcc7d9bb 1346 #define EXTI_RTSR_TR10 EXTI_RTSR_RT10
Kojto 119:aae6fcc7d9bb 1347 #define EXTI_RTSR_TR11 EXTI_RTSR_RT11
Kojto 119:aae6fcc7d9bb 1348 #define EXTI_RTSR_TR12 EXTI_RTSR_RT12
Kojto 119:aae6fcc7d9bb 1349 #define EXTI_RTSR_TR13 EXTI_RTSR_RT13
Kojto 119:aae6fcc7d9bb 1350 #define EXTI_RTSR_TR14 EXTI_RTSR_RT14
Kojto 119:aae6fcc7d9bb 1351 #define EXTI_RTSR_TR15 EXTI_RTSR_RT15
Kojto 119:aae6fcc7d9bb 1352 #define EXTI_RTSR_TR16 EXTI_RTSR_RT16
Kojto 119:aae6fcc7d9bb 1353 #define EXTI_RTSR_TR17 EXTI_RTSR_RT17
Kojto 119:aae6fcc7d9bb 1354 #define EXTI_RTSR_TR19 EXTI_RTSR_RT19
Kojto 119:aae6fcc7d9bb 1355 #define EXTI_RTSR_TR20 EXTI_RTSR_RT20
Kojto 119:aae6fcc7d9bb 1356 #define EXTI_RTSR_TR21 EXTI_RTSR_RT21
Kojto 119:aae6fcc7d9bb 1357 #define EXTI_RTSR_TR22 EXTI_RTSR_RT22
Kojto 99:dbbf35b96557 1358
Kojto 99:dbbf35b96557 1359 /******************* Bit definition for EXTI_FTSR register *******************/
Kojto 119:aae6fcc7d9bb 1360 #define EXTI_FTSR_FT0 ((uint32_t)0x00000001U) /*!< Falling trigger event configuration bit of line 0 */
Kojto 119:aae6fcc7d9bb 1361 #define EXTI_FTSR_FT1 ((uint32_t)0x00000002U) /*!< Falling trigger event configuration bit of line 1 */
Kojto 119:aae6fcc7d9bb 1362 #define EXTI_FTSR_FT2 ((uint32_t)0x00000004U) /*!< Falling trigger event configuration bit of line 2 */
Kojto 119:aae6fcc7d9bb 1363 #define EXTI_FTSR_FT3 ((uint32_t)0x00000008U) /*!< Falling trigger event configuration bit of line 3 */
Kojto 119:aae6fcc7d9bb 1364 #define EXTI_FTSR_FT4 ((uint32_t)0x00000010U) /*!< Falling trigger event configuration bit of line 4 */
Kojto 119:aae6fcc7d9bb 1365 #define EXTI_FTSR_FT5 ((uint32_t)0x00000020U) /*!< Falling trigger event configuration bit of line 5 */
Kojto 119:aae6fcc7d9bb 1366 #define EXTI_FTSR_FT6 ((uint32_t)0x00000040U) /*!< Falling trigger event configuration bit of line 6 */
Kojto 119:aae6fcc7d9bb 1367 #define EXTI_FTSR_FT7 ((uint32_t)0x00000080U) /*!< Falling trigger event configuration bit of line 7 */
Kojto 119:aae6fcc7d9bb 1368 #define EXTI_FTSR_FT8 ((uint32_t)0x00000100U) /*!< Falling trigger event configuration bit of line 8 */
Kojto 119:aae6fcc7d9bb 1369 #define EXTI_FTSR_FT9 ((uint32_t)0x00000200U) /*!< Falling trigger event configuration bit of line 9 */
Kojto 119:aae6fcc7d9bb 1370 #define EXTI_FTSR_FT10 ((uint32_t)0x00000400U) /*!< Falling trigger event configuration bit of line 10 */
Kojto 119:aae6fcc7d9bb 1371 #define EXTI_FTSR_FT11 ((uint32_t)0x00000800U) /*!< Falling trigger event configuration bit of line 11 */
Kojto 119:aae6fcc7d9bb 1372 #define EXTI_FTSR_FT12 ((uint32_t)0x00001000U) /*!< Falling trigger event configuration bit of line 12 */
Kojto 119:aae6fcc7d9bb 1373 #define EXTI_FTSR_FT13 ((uint32_t)0x00002000U) /*!< Falling trigger event configuration bit of line 13 */
Kojto 119:aae6fcc7d9bb 1374 #define EXTI_FTSR_FT14 ((uint32_t)0x00004000U) /*!< Falling trigger event configuration bit of line 14 */
Kojto 119:aae6fcc7d9bb 1375 #define EXTI_FTSR_FT15 ((uint32_t)0x00008000U) /*!< Falling trigger event configuration bit of line 15 */
Kojto 119:aae6fcc7d9bb 1376 #define EXTI_FTSR_FT16 ((uint32_t)0x00010000U) /*!< Falling trigger event configuration bit of line 16 */
Kojto 119:aae6fcc7d9bb 1377 #define EXTI_FTSR_FT17 ((uint32_t)0x00020000U) /*!< Falling trigger event configuration bit of line 17 */
Kojto 119:aae6fcc7d9bb 1378 #define EXTI_FTSR_FT19 ((uint32_t)0x00080000U) /*!< Falling trigger event configuration bit of line 19 */
Kojto 119:aae6fcc7d9bb 1379 #define EXTI_FTSR_FT20 ((uint32_t)0x00100000U) /*!< Falling trigger event configuration bit of line 20 */
Kojto 119:aae6fcc7d9bb 1380 #define EXTI_FTSR_FT21 ((uint32_t)0x00200000U) /*!< Falling trigger event configuration bit of line 21 */
Kojto 119:aae6fcc7d9bb 1381 #define EXTI_FTSR_FT22 ((uint32_t)0x00400000U) /*!< Falling trigger event configuration bit of line 22 */
Kojto 119:aae6fcc7d9bb 1382
Kojto 119:aae6fcc7d9bb 1383 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 1384 #define EXTI_FTSR_TR0 EXTI_FTSR_FT0
Kojto 119:aae6fcc7d9bb 1385 #define EXTI_FTSR_TR1 EXTI_FTSR_FT1
Kojto 119:aae6fcc7d9bb 1386 #define EXTI_FTSR_TR2 EXTI_FTSR_FT2
Kojto 119:aae6fcc7d9bb 1387 #define EXTI_FTSR_TR3 EXTI_FTSR_FT3
Kojto 119:aae6fcc7d9bb 1388 #define EXTI_FTSR_TR4 EXTI_FTSR_FT4
Kojto 119:aae6fcc7d9bb 1389 #define EXTI_FTSR_TR5 EXTI_FTSR_FT5
Kojto 119:aae6fcc7d9bb 1390 #define EXTI_FTSR_TR6 EXTI_FTSR_FT6
Kojto 119:aae6fcc7d9bb 1391 #define EXTI_FTSR_TR7 EXTI_FTSR_FT7
Kojto 119:aae6fcc7d9bb 1392 #define EXTI_FTSR_TR8 EXTI_FTSR_FT8
Kojto 119:aae6fcc7d9bb 1393 #define EXTI_FTSR_TR9 EXTI_FTSR_FT9
Kojto 119:aae6fcc7d9bb 1394 #define EXTI_FTSR_TR10 EXTI_FTSR_FT10
Kojto 119:aae6fcc7d9bb 1395 #define EXTI_FTSR_TR11 EXTI_FTSR_FT11
Kojto 119:aae6fcc7d9bb 1396 #define EXTI_FTSR_TR12 EXTI_FTSR_FT12
Kojto 119:aae6fcc7d9bb 1397 #define EXTI_FTSR_TR13 EXTI_FTSR_FT13
Kojto 119:aae6fcc7d9bb 1398 #define EXTI_FTSR_TR14 EXTI_FTSR_FT14
Kojto 119:aae6fcc7d9bb 1399 #define EXTI_FTSR_TR15 EXTI_FTSR_FT15
Kojto 119:aae6fcc7d9bb 1400 #define EXTI_FTSR_TR16 EXTI_FTSR_FT16
Kojto 119:aae6fcc7d9bb 1401 #define EXTI_FTSR_TR17 EXTI_FTSR_FT17
Kojto 119:aae6fcc7d9bb 1402 #define EXTI_FTSR_TR19 EXTI_FTSR_FT19
Kojto 119:aae6fcc7d9bb 1403 #define EXTI_FTSR_TR20 EXTI_FTSR_FT20
Kojto 119:aae6fcc7d9bb 1404 #define EXTI_FTSR_TR21 EXTI_FTSR_FT21
Kojto 119:aae6fcc7d9bb 1405 #define EXTI_FTSR_TR22 EXTI_FTSR_FT22
Kojto 99:dbbf35b96557 1406
Kojto 99:dbbf35b96557 1407 /******************* Bit definition for EXTI_SWIER register *******************/
Kojto 119:aae6fcc7d9bb 1408 #define EXTI_SWIER_SWI0 ((uint32_t)0x00000001U) /*!< Software Interrupt on line 0 */
Kojto 119:aae6fcc7d9bb 1409 #define EXTI_SWIER_SWI1 ((uint32_t)0x00000002U) /*!< Software Interrupt on line 1 */
Kojto 119:aae6fcc7d9bb 1410 #define EXTI_SWIER_SWI2 ((uint32_t)0x00000004U) /*!< Software Interrupt on line 2 */
Kojto 119:aae6fcc7d9bb 1411 #define EXTI_SWIER_SWI3 ((uint32_t)0x00000008U) /*!< Software Interrupt on line 3 */
Kojto 119:aae6fcc7d9bb 1412 #define EXTI_SWIER_SWI4 ((uint32_t)0x00000010U) /*!< Software Interrupt on line 4 */
Kojto 119:aae6fcc7d9bb 1413 #define EXTI_SWIER_SWI5 ((uint32_t)0x00000020U) /*!< Software Interrupt on line 5 */
Kojto 119:aae6fcc7d9bb 1414 #define EXTI_SWIER_SWI6 ((uint32_t)0x00000040U) /*!< Software Interrupt on line 6 */
Kojto 119:aae6fcc7d9bb 1415 #define EXTI_SWIER_SWI7 ((uint32_t)0x00000080U) /*!< Software Interrupt on line 7 */
Kojto 119:aae6fcc7d9bb 1416 #define EXTI_SWIER_SWI8 ((uint32_t)0x00000100U) /*!< Software Interrupt on line 8 */
Kojto 119:aae6fcc7d9bb 1417 #define EXTI_SWIER_SWI9 ((uint32_t)0x00000200U) /*!< Software Interrupt on line 9 */
Kojto 119:aae6fcc7d9bb 1418 #define EXTI_SWIER_SWI10 ((uint32_t)0x00000400U) /*!< Software Interrupt on line 10 */
Kojto 119:aae6fcc7d9bb 1419 #define EXTI_SWIER_SWI11 ((uint32_t)0x00000800U) /*!< Software Interrupt on line 11 */
Kojto 119:aae6fcc7d9bb 1420 #define EXTI_SWIER_SWI12 ((uint32_t)0x00001000U) /*!< Software Interrupt on line 12 */
Kojto 119:aae6fcc7d9bb 1421 #define EXTI_SWIER_SWI13 ((uint32_t)0x00002000U) /*!< Software Interrupt on line 13 */
Kojto 119:aae6fcc7d9bb 1422 #define EXTI_SWIER_SWI14 ((uint32_t)0x00004000U) /*!< Software Interrupt on line 14 */
Kojto 119:aae6fcc7d9bb 1423 #define EXTI_SWIER_SWI15 ((uint32_t)0x00008000U) /*!< Software Interrupt on line 15 */
Kojto 119:aae6fcc7d9bb 1424 #define EXTI_SWIER_SWI16 ((uint32_t)0x00010000U) /*!< Software Interrupt on line 16 */
Kojto 119:aae6fcc7d9bb 1425 #define EXTI_SWIER_SWI17 ((uint32_t)0x00020000U) /*!< Software Interrupt on line 17 */
Kojto 119:aae6fcc7d9bb 1426 #define EXTI_SWIER_SWI19 ((uint32_t)0x00080000U) /*!< Software Interrupt on line 19 */
Kojto 119:aae6fcc7d9bb 1427 #define EXTI_SWIER_SWI20 ((uint32_t)0x00100000U) /*!< Software Interrupt on line 20 */
Kojto 119:aae6fcc7d9bb 1428 #define EXTI_SWIER_SWI21 ((uint32_t)0x00200000U) /*!< Software Interrupt on line 21 */
Kojto 119:aae6fcc7d9bb 1429 #define EXTI_SWIER_SWI22 ((uint32_t)0x00400000U) /*!< Software Interrupt on line 22 */
Kojto 119:aae6fcc7d9bb 1430
Kojto 119:aae6fcc7d9bb 1431 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 1432 #define EXTI_SWIER_SWIER0 EXTI_SWIER_SWI0
Kojto 119:aae6fcc7d9bb 1433 #define EXTI_SWIER_SWIER1 EXTI_SWIER_SWI1
Kojto 119:aae6fcc7d9bb 1434 #define EXTI_SWIER_SWIER2 EXTI_SWIER_SWI2
Kojto 119:aae6fcc7d9bb 1435 #define EXTI_SWIER_SWIER3 EXTI_SWIER_SWI3
Kojto 119:aae6fcc7d9bb 1436 #define EXTI_SWIER_SWIER4 EXTI_SWIER_SWI4
Kojto 119:aae6fcc7d9bb 1437 #define EXTI_SWIER_SWIER5 EXTI_SWIER_SWI5
Kojto 119:aae6fcc7d9bb 1438 #define EXTI_SWIER_SWIER6 EXTI_SWIER_SWI6
Kojto 119:aae6fcc7d9bb 1439 #define EXTI_SWIER_SWIER7 EXTI_SWIER_SWI7
Kojto 119:aae6fcc7d9bb 1440 #define EXTI_SWIER_SWIER8 EXTI_SWIER_SWI8
Kojto 119:aae6fcc7d9bb 1441 #define EXTI_SWIER_SWIER9 EXTI_SWIER_SWI9
Kojto 119:aae6fcc7d9bb 1442 #define EXTI_SWIER_SWIER10 EXTI_SWIER_SWI10
Kojto 119:aae6fcc7d9bb 1443 #define EXTI_SWIER_SWIER11 EXTI_SWIER_SWI11
Kojto 119:aae6fcc7d9bb 1444 #define EXTI_SWIER_SWIER12 EXTI_SWIER_SWI12
Kojto 119:aae6fcc7d9bb 1445 #define EXTI_SWIER_SWIER13 EXTI_SWIER_SWI13
Kojto 119:aae6fcc7d9bb 1446 #define EXTI_SWIER_SWIER14 EXTI_SWIER_SWI14
Kojto 119:aae6fcc7d9bb 1447 #define EXTI_SWIER_SWIER15 EXTI_SWIER_SWI15
Kojto 119:aae6fcc7d9bb 1448 #define EXTI_SWIER_SWIER16 EXTI_SWIER_SWI16
Kojto 119:aae6fcc7d9bb 1449 #define EXTI_SWIER_SWIER17 EXTI_SWIER_SWI17
Kojto 119:aae6fcc7d9bb 1450 #define EXTI_SWIER_SWIER19 EXTI_SWIER_SWI19
Kojto 119:aae6fcc7d9bb 1451 #define EXTI_SWIER_SWIER20 EXTI_SWIER_SWI20
Kojto 119:aae6fcc7d9bb 1452 #define EXTI_SWIER_SWIER21 EXTI_SWIER_SWI21
Kojto 119:aae6fcc7d9bb 1453 #define EXTI_SWIER_SWIER22 EXTI_SWIER_SWI22
Kojto 99:dbbf35b96557 1454
Kojto 99:dbbf35b96557 1455 /****************** Bit definition for EXTI_PR register *********************/
Kojto 119:aae6fcc7d9bb 1456 #define EXTI_PR_PIF0 ((uint32_t)0x00000001U) /*!< Pending bit 0 */
Kojto 119:aae6fcc7d9bb 1457 #define EXTI_PR_PIF1 ((uint32_t)0x00000002U) /*!< Pending bit 1 */
Kojto 119:aae6fcc7d9bb 1458 #define EXTI_PR_PIF2 ((uint32_t)0x00000004U) /*!< Pending bit 2 */
Kojto 119:aae6fcc7d9bb 1459 #define EXTI_PR_PIF3 ((uint32_t)0x00000008U) /*!< Pending bit 3 */
Kojto 119:aae6fcc7d9bb 1460 #define EXTI_PR_PIF4 ((uint32_t)0x00000010U) /*!< Pending bit 4 */
Kojto 119:aae6fcc7d9bb 1461 #define EXTI_PR_PIF5 ((uint32_t)0x00000020U) /*!< Pending bit 5 */
Kojto 119:aae6fcc7d9bb 1462 #define EXTI_PR_PIF6 ((uint32_t)0x00000040U) /*!< Pending bit 6 */
Kojto 119:aae6fcc7d9bb 1463 #define EXTI_PR_PIF7 ((uint32_t)0x00000080U) /*!< Pending bit 7 */
Kojto 119:aae6fcc7d9bb 1464 #define EXTI_PR_PIF8 ((uint32_t)0x00000100U) /*!< Pending bit 8 */
Kojto 119:aae6fcc7d9bb 1465 #define EXTI_PR_PIF9 ((uint32_t)0x00000200U) /*!< Pending bit 9 */
Kojto 119:aae6fcc7d9bb 1466 #define EXTI_PR_PIF10 ((uint32_t)0x00000400U) /*!< Pending bit 10 */
Kojto 119:aae6fcc7d9bb 1467 #define EXTI_PR_PIF11 ((uint32_t)0x00000800U) /*!< Pending bit 11 */
Kojto 119:aae6fcc7d9bb 1468 #define EXTI_PR_PIF12 ((uint32_t)0x00001000U) /*!< Pending bit 12 */
Kojto 119:aae6fcc7d9bb 1469 #define EXTI_PR_PIF13 ((uint32_t)0x00002000U) /*!< Pending bit 13 */
Kojto 119:aae6fcc7d9bb 1470 #define EXTI_PR_PIF14 ((uint32_t)0x00004000U) /*!< Pending bit 14 */
Kojto 119:aae6fcc7d9bb 1471 #define EXTI_PR_PIF15 ((uint32_t)0x00008000U) /*!< Pending bit 15 */
Kojto 119:aae6fcc7d9bb 1472 #define EXTI_PR_PIF16 ((uint32_t)0x00010000U) /*!< Pending bit 16 */
Kojto 119:aae6fcc7d9bb 1473 #define EXTI_PR_PIF17 ((uint32_t)0x00020000U) /*!< Pending bit 17 */
Kojto 119:aae6fcc7d9bb 1474 #define EXTI_PR_PIF19 ((uint32_t)0x00080000U) /*!< Pending bit 19 */
Kojto 119:aae6fcc7d9bb 1475 #define EXTI_PR_PIF20 ((uint32_t)0x00100000U) /*!< Pending bit 20 */
Kojto 119:aae6fcc7d9bb 1476 #define EXTI_PR_PIF21 ((uint32_t)0x00200000U) /*!< Pending bit 21 */
Kojto 119:aae6fcc7d9bb 1477 #define EXTI_PR_PIF22 ((uint32_t)0x00400000U) /*!< Pending bit 22 */
Kojto 119:aae6fcc7d9bb 1478
Kojto 119:aae6fcc7d9bb 1479 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 1480 #define EXTI_PR_PR0 EXTI_PR_PIF0
Kojto 119:aae6fcc7d9bb 1481 #define EXTI_PR_PR1 EXTI_PR_PIF1
Kojto 119:aae6fcc7d9bb 1482 #define EXTI_PR_PR2 EXTI_PR_PIF2
Kojto 119:aae6fcc7d9bb 1483 #define EXTI_PR_PR3 EXTI_PR_PIF3
Kojto 119:aae6fcc7d9bb 1484 #define EXTI_PR_PR4 EXTI_PR_PIF4
Kojto 119:aae6fcc7d9bb 1485 #define EXTI_PR_PR5 EXTI_PR_PIF5
Kojto 119:aae6fcc7d9bb 1486 #define EXTI_PR_PR6 EXTI_PR_PIF6
Kojto 119:aae6fcc7d9bb 1487 #define EXTI_PR_PR7 EXTI_PR_PIF7
Kojto 119:aae6fcc7d9bb 1488 #define EXTI_PR_PR8 EXTI_PR_PIF8
Kojto 119:aae6fcc7d9bb 1489 #define EXTI_PR_PR9 EXTI_PR_PIF9
Kojto 119:aae6fcc7d9bb 1490 #define EXTI_PR_PR10 EXTI_PR_PIF10
Kojto 119:aae6fcc7d9bb 1491 #define EXTI_PR_PR11 EXTI_PR_PIF11
Kojto 119:aae6fcc7d9bb 1492 #define EXTI_PR_PR12 EXTI_PR_PIF12
Kojto 119:aae6fcc7d9bb 1493 #define EXTI_PR_PR13 EXTI_PR_PIF13
Kojto 119:aae6fcc7d9bb 1494 #define EXTI_PR_PR14 EXTI_PR_PIF14
Kojto 119:aae6fcc7d9bb 1495 #define EXTI_PR_PR15 EXTI_PR_PIF15
Kojto 119:aae6fcc7d9bb 1496 #define EXTI_PR_PR16 EXTI_PR_PIF16
Kojto 119:aae6fcc7d9bb 1497 #define EXTI_PR_PR17 EXTI_PR_PIF17
Kojto 119:aae6fcc7d9bb 1498 #define EXTI_PR_PR19 EXTI_PR_PIF19
Kojto 119:aae6fcc7d9bb 1499 #define EXTI_PR_PR20 EXTI_PR_PIF20
Kojto 119:aae6fcc7d9bb 1500 #define EXTI_PR_PR21 EXTI_PR_PIF21
Kojto 119:aae6fcc7d9bb 1501 #define EXTI_PR_PR22 EXTI_PR_PIF22
Kojto 99:dbbf35b96557 1502
Kojto 99:dbbf35b96557 1503 /******************************************************************************/
Kojto 99:dbbf35b96557 1504 /* */
Kojto 99:dbbf35b96557 1505 /* FLASH and Option Bytes Registers */
Kojto 99:dbbf35b96557 1506 /* */
Kojto 99:dbbf35b96557 1507 /******************************************************************************/
Kojto 99:dbbf35b96557 1508
Kojto 99:dbbf35b96557 1509 /******************* Bit definition for FLASH_ACR register ******************/
Kojto 119:aae6fcc7d9bb 1510 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001U) /*!< LATENCY bit (Latency) */
Kojto 119:aae6fcc7d9bb 1511 #define FLASH_ACR_PRFTEN ((uint32_t)0x00000002U) /*!< Prefetch Buffer Enable */
Kojto 119:aae6fcc7d9bb 1512 #define FLASH_ACR_SLEEP_PD ((uint32_t)0x00000008U) /*!< Flash mode during sleep mode */
Kojto 119:aae6fcc7d9bb 1513 #define FLASH_ACR_RUN_PD ((uint32_t)0x00000010U) /*!< Flash mode during RUN mode */
Kojto 119:aae6fcc7d9bb 1514 #define FLASH_ACR_DISAB_BUF ((uint32_t)0x00000020U) /*!< Disable Buffer */
Kojto 119:aae6fcc7d9bb 1515 #define FLASH_ACR_PRE_READ ((uint32_t)0x00000040U) /*!< Pre-read data address */
Kojto 99:dbbf35b96557 1516
Kojto 99:dbbf35b96557 1517 /******************* Bit definition for FLASH_PECR register ******************/
Kojto 119:aae6fcc7d9bb 1518 #define FLASH_PECR_PELOCK ((uint32_t)0x00000001U) /*!< FLASH_PECR and Flash data Lock */
Kojto 119:aae6fcc7d9bb 1519 #define FLASH_PECR_PRGLOCK ((uint32_t)0x00000002U) /*!< Program matrix Lock */
Kojto 119:aae6fcc7d9bb 1520 #define FLASH_PECR_OPTLOCK ((uint32_t)0x00000004U) /*!< Option byte matrix Lock */
Kojto 119:aae6fcc7d9bb 1521 #define FLASH_PECR_PROG ((uint32_t)0x00000008U) /*!< Program matrix selection */
Kojto 119:aae6fcc7d9bb 1522 #define FLASH_PECR_DATA ((uint32_t)0x00000010U) /*!< Data matrix selection */
Kojto 119:aae6fcc7d9bb 1523 #define FLASH_PECR_FIX ((uint32_t)0x00000100U) /*!< Fixed Time Data write for Word/Half Word/Byte programming */
Kojto 119:aae6fcc7d9bb 1524 #define FLASH_PECR_ERASE ((uint32_t)0x00000200U) /*!< Page erasing mode */
Kojto 119:aae6fcc7d9bb 1525 #define FLASH_PECR_FPRG ((uint32_t)0x00000400U) /*!< Fast Page/Half Page programming mode */
Kojto 119:aae6fcc7d9bb 1526 #define FLASH_PECR_EOPIE ((uint32_t)0x00010000U) /*!< End of programming interrupt */
Kojto 119:aae6fcc7d9bb 1527 #define FLASH_PECR_ERRIE ((uint32_t)0x00020000U) /*!< Error interrupt */
Kojto 119:aae6fcc7d9bb 1528 #define FLASH_PECR_OBL_LAUNCH ((uint32_t)0x00040000U) /*!< Launch the option byte loading */
Kojto 119:aae6fcc7d9bb 1529 #define FLASH_PECR_HALF_ARRAY ((uint32_t)0x00080000U) /*!< Half array mode */
Kojto 99:dbbf35b96557 1530
Kojto 99:dbbf35b96557 1531 /****************** Bit definition for FLASH_PDKEYR register ******************/
Kojto 119:aae6fcc7d9bb 1532 #define FLASH_PDKEYR_PDKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
Kojto 99:dbbf35b96557 1533
Kojto 99:dbbf35b96557 1534 /****************** Bit definition for FLASH_PEKEYR register ******************/
Kojto 119:aae6fcc7d9bb 1535 #define FLASH_PEKEYR_PEKEYR ((uint32_t)0xFFFFFFFFU) /*!< FLASH_PEC and data matrix Key */
Kojto 99:dbbf35b96557 1536
Kojto 99:dbbf35b96557 1537 /****************** Bit definition for FLASH_PRGKEYR register ******************/
Kojto 119:aae6fcc7d9bb 1538 #define FLASH_PRGKEYR_PRGKEYR ((uint32_t)0xFFFFFFFFU) /*!< Program matrix Key */
Kojto 99:dbbf35b96557 1539
Kojto 99:dbbf35b96557 1540 /****************** Bit definition for FLASH_OPTKEYR register ******************/
Kojto 119:aae6fcc7d9bb 1541 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFFU) /*!< Option bytes matrix Key */
Kojto 99:dbbf35b96557 1542
Kojto 99:dbbf35b96557 1543 /****************** Bit definition for FLASH_SR register *******************/
Kojto 119:aae6fcc7d9bb 1544 #define FLASH_SR_BSY ((uint32_t)0x00000001U) /*!< Busy */
Kojto 119:aae6fcc7d9bb 1545 #define FLASH_SR_EOP ((uint32_t)0x00000002U) /*!< End Of Programming*/
Kojto 119:aae6fcc7d9bb 1546 #define FLASH_SR_HVOFF ((uint32_t)0x00000004U) /*!< End of high voltage */
Kojto 119:aae6fcc7d9bb 1547 #define FLASH_SR_READY ((uint32_t)0x00000008U) /*!< Flash ready after low power mode */
Kojto 119:aae6fcc7d9bb 1548
Kojto 119:aae6fcc7d9bb 1549 #define FLASH_SR_WRPERR ((uint32_t)0x00000100U) /*!< Write protection error */
Kojto 119:aae6fcc7d9bb 1550 #define FLASH_SR_PGAERR ((uint32_t)0x00000200U) /*!< Programming Alignment Error */
Kojto 119:aae6fcc7d9bb 1551 #define FLASH_SR_SIZERR ((uint32_t)0x00000400U) /*!< Size error */
Kojto 119:aae6fcc7d9bb 1552 #define FLASH_SR_OPTVERR ((uint32_t)0x00000800U) /*!< Option Valid error */
Kojto 119:aae6fcc7d9bb 1553 #define FLASH_SR_RDERR ((uint32_t)0x00002000U) /*!< Read protected error */
Kojto 119:aae6fcc7d9bb 1554 #define FLASH_SR_NOTZEROERR ((uint32_t)0x00010000U) /*!< Not Zero error */
Kojto 119:aae6fcc7d9bb 1555 #define FLASH_SR_FWWERR ((uint32_t)0x00020000U) /*!< Write/Errase operation aborted */
Kojto 119:aae6fcc7d9bb 1556
Kojto 119:aae6fcc7d9bb 1557 /* Legacy defines */
Kojto 99:dbbf35b96557 1558 #define FLASH_SR_FWWER FLASH_SR_FWWERR
Kojto 99:dbbf35b96557 1559 #define FLASH_SR_ENHV FLASH_SR_HVOFF
Kojto 99:dbbf35b96557 1560 #define FLASH_SR_ENDHV FLASH_SR_HVOFF
Kojto 99:dbbf35b96557 1561
Kojto 99:dbbf35b96557 1562 /****************** Bit definition for FLASH_OPTR register *******************/
Kojto 119:aae6fcc7d9bb 1563 #define FLASH_OPTR_RDPROT ((uint32_t)0x000000FFU) /*!< Read Protection */
Kojto 119:aae6fcc7d9bb 1564 #define FLASH_OPTR_WPRMOD ((uint32_t)0x00000100U) /*!< Selection of protection mode of WPR bits */
Kojto 119:aae6fcc7d9bb 1565 #define FLASH_OPTR_BOR_LEV ((uint32_t)0x000F0000U) /*!< BOR_LEV[3:0] Brown Out Reset Threshold Level*/
Kojto 119:aae6fcc7d9bb 1566 #define FLASH_OPTR_IWDG_SW ((uint32_t)0x00100000U) /*!< IWDG_SW */
Kojto 119:aae6fcc7d9bb 1567 #define FLASH_OPTR_nRST_STOP ((uint32_t)0x00200000U) /*!< nRST_STOP */
Kojto 119:aae6fcc7d9bb 1568 #define FLASH_OPTR_nRST_STDBY ((uint32_t)0x00400000U) /*!< nRST_STDBY */
Kojto 119:aae6fcc7d9bb 1569 #define FLASH_OPTR_USER ((uint32_t)0x00700000U) /*!< User Option Bytes */
Kojto 119:aae6fcc7d9bb 1570 #define FLASH_OPTR_BOOT1 ((uint32_t)0x80000000U) /*!< BOOT1 */
Kojto 99:dbbf35b96557 1571
Kojto 99:dbbf35b96557 1572 /****************** Bit definition for FLASH_WRPR register ******************/
Kojto 119:aae6fcc7d9bb 1573 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFFU) /*!< Write Protection bits */
Kojto 99:dbbf35b96557 1574
Kojto 99:dbbf35b96557 1575 /******************************************************************************/
Kojto 99:dbbf35b96557 1576 /* */
Kojto 99:dbbf35b96557 1577 /* General Purpose IOs (GPIO) */
Kojto 99:dbbf35b96557 1578 /* */
Kojto 99:dbbf35b96557 1579 /******************************************************************************/
Kojto 99:dbbf35b96557 1580 /******************* Bit definition for GPIO_MODER register *****************/
Kojto 119:aae6fcc7d9bb 1581 #define GPIO_MODER_MODE0 ((uint32_t)0x00000003U)
Kojto 119:aae6fcc7d9bb 1582 #define GPIO_MODER_MODE0_0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1583 #define GPIO_MODER_MODE0_1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1584 #define GPIO_MODER_MODE1 ((uint32_t)0x0000000CU)
Kojto 119:aae6fcc7d9bb 1585 #define GPIO_MODER_MODE1_0 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1586 #define GPIO_MODER_MODE1_1 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1587 #define GPIO_MODER_MODE2 ((uint32_t)0x00000030U)
Kojto 119:aae6fcc7d9bb 1588 #define GPIO_MODER_MODE2_0 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1589 #define GPIO_MODER_MODE2_1 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1590 #define GPIO_MODER_MODE3 ((uint32_t)0x000000C0U)
Kojto 119:aae6fcc7d9bb 1591 #define GPIO_MODER_MODE3_0 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1592 #define GPIO_MODER_MODE3_1 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1593 #define GPIO_MODER_MODE4 ((uint32_t)0x00000300U)
Kojto 119:aae6fcc7d9bb 1594 #define GPIO_MODER_MODE4_0 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1595 #define GPIO_MODER_MODE4_1 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1596 #define GPIO_MODER_MODE5 ((uint32_t)0x00000C00U)
Kojto 119:aae6fcc7d9bb 1597 #define GPIO_MODER_MODE5_0 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1598 #define GPIO_MODER_MODE5_1 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1599 #define GPIO_MODER_MODE6 ((uint32_t)0x00003000U)
Kojto 119:aae6fcc7d9bb 1600 #define GPIO_MODER_MODE6_0 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1601 #define GPIO_MODER_MODE6_1 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1602 #define GPIO_MODER_MODE7 ((uint32_t)0x0000C000U)
Kojto 119:aae6fcc7d9bb 1603 #define GPIO_MODER_MODE7_0 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1604 #define GPIO_MODER_MODE7_1 ((uint32_t)0x00008000U)
Kojto 119:aae6fcc7d9bb 1605 #define GPIO_MODER_MODE8 ((uint32_t)0x00030000U)
Kojto 119:aae6fcc7d9bb 1606 #define GPIO_MODER_MODE8_0 ((uint32_t)0x00010000U)
Kojto 119:aae6fcc7d9bb 1607 #define GPIO_MODER_MODE8_1 ((uint32_t)0x00020000U)
Kojto 119:aae6fcc7d9bb 1608 #define GPIO_MODER_MODE9 ((uint32_t)0x000C0000U)
Kojto 119:aae6fcc7d9bb 1609 #define GPIO_MODER_MODE9_0 ((uint32_t)0x00040000U)
Kojto 119:aae6fcc7d9bb 1610 #define GPIO_MODER_MODE9_1 ((uint32_t)0x00080000U)
Kojto 119:aae6fcc7d9bb 1611 #define GPIO_MODER_MODE10 ((uint32_t)0x00300000U)
Kojto 119:aae6fcc7d9bb 1612 #define GPIO_MODER_MODE10_0 ((uint32_t)0x00100000U)
Kojto 119:aae6fcc7d9bb 1613 #define GPIO_MODER_MODE10_1 ((uint32_t)0x00200000U)
Kojto 119:aae6fcc7d9bb 1614 #define GPIO_MODER_MODE11 ((uint32_t)0x00C00000U)
Kojto 119:aae6fcc7d9bb 1615 #define GPIO_MODER_MODE11_0 ((uint32_t)0x00400000U)
Kojto 119:aae6fcc7d9bb 1616 #define GPIO_MODER_MODE11_1 ((uint32_t)0x00800000U)
Kojto 119:aae6fcc7d9bb 1617 #define GPIO_MODER_MODE12 ((uint32_t)0x03000000U)
Kojto 119:aae6fcc7d9bb 1618 #define GPIO_MODER_MODE12_0 ((uint32_t)0x01000000U)
Kojto 119:aae6fcc7d9bb 1619 #define GPIO_MODER_MODE12_1 ((uint32_t)0x02000000U)
Kojto 119:aae6fcc7d9bb 1620 #define GPIO_MODER_MODE13 ((uint32_t)0x0C000000U)
Kojto 119:aae6fcc7d9bb 1621 #define GPIO_MODER_MODE13_0 ((uint32_t)0x04000000U)
Kojto 119:aae6fcc7d9bb 1622 #define GPIO_MODER_MODE13_1 ((uint32_t)0x08000000U)
Kojto 119:aae6fcc7d9bb 1623 #define GPIO_MODER_MODE14 ((uint32_t)0x30000000U)
Kojto 119:aae6fcc7d9bb 1624 #define GPIO_MODER_MODE14_0 ((uint32_t)0x10000000U)
Kojto 119:aae6fcc7d9bb 1625 #define GPIO_MODER_MODE14_1 ((uint32_t)0x20000000U)
Kojto 119:aae6fcc7d9bb 1626 #define GPIO_MODER_MODE15 ((uint32_t)0xC0000000U)
Kojto 119:aae6fcc7d9bb 1627 #define GPIO_MODER_MODE15_0 ((uint32_t)0x40000000U)
Kojto 119:aae6fcc7d9bb 1628 #define GPIO_MODER_MODE15_1 ((uint32_t)0x80000000U)
Kojto 99:dbbf35b96557 1629
Kojto 99:dbbf35b96557 1630 /****************** Bit definition for GPIO_OTYPER register *****************/
Kojto 119:aae6fcc7d9bb 1631 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1632 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1633 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1634 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1635 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1636 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1637 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1638 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1639 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1640 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1641 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1642 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1643 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1644 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1645 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1646 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000U)
Kojto 99:dbbf35b96557 1647
Kojto 99:dbbf35b96557 1648 /**************** Bit definition for GPIO_OSPEEDR register ******************/
Kojto 119:aae6fcc7d9bb 1649 #define GPIO_OSPEEDER_OSPEED0 ((uint32_t)0x00000003U)
Kojto 119:aae6fcc7d9bb 1650 #define GPIO_OSPEEDER_OSPEED0_0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1651 #define GPIO_OSPEEDER_OSPEED0_1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1652 #define GPIO_OSPEEDER_OSPEED1 ((uint32_t)0x0000000CU)
Kojto 119:aae6fcc7d9bb 1653 #define GPIO_OSPEEDER_OSPEED1_0 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1654 #define GPIO_OSPEEDER_OSPEED1_1 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1655 #define GPIO_OSPEEDER_OSPEED2 ((uint32_t)0x00000030U)
Kojto 119:aae6fcc7d9bb 1656 #define GPIO_OSPEEDER_OSPEED2_0 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1657 #define GPIO_OSPEEDER_OSPEED2_1 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1658 #define GPIO_OSPEEDER_OSPEED3 ((uint32_t)0x000000C0U)
Kojto 119:aae6fcc7d9bb 1659 #define GPIO_OSPEEDER_OSPEED3_0 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1660 #define GPIO_OSPEEDER_OSPEED3_1 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1661 #define GPIO_OSPEEDER_OSPEED4 ((uint32_t)0x00000300U)
Kojto 119:aae6fcc7d9bb 1662 #define GPIO_OSPEEDER_OSPEED4_0 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1663 #define GPIO_OSPEEDER_OSPEED4_1 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1664 #define GPIO_OSPEEDER_OSPEED5 ((uint32_t)0x00000C00U)
Kojto 119:aae6fcc7d9bb 1665 #define GPIO_OSPEEDER_OSPEED5_0 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1666 #define GPIO_OSPEEDER_OSPEED5_1 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1667 #define GPIO_OSPEEDER_OSPEED6 ((uint32_t)0x00003000U)
Kojto 119:aae6fcc7d9bb 1668 #define GPIO_OSPEEDER_OSPEED6_0 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1669 #define GPIO_OSPEEDER_OSPEED6_1 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1670 #define GPIO_OSPEEDER_OSPEED7 ((uint32_t)0x0000C000U)
Kojto 119:aae6fcc7d9bb 1671 #define GPIO_OSPEEDER_OSPEED7_0 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1672 #define GPIO_OSPEEDER_OSPEED7_1 ((uint32_t)0x00008000U)
Kojto 119:aae6fcc7d9bb 1673 #define GPIO_OSPEEDER_OSPEED8 ((uint32_t)0x00030000U)
Kojto 119:aae6fcc7d9bb 1674 #define GPIO_OSPEEDER_OSPEED8_0 ((uint32_t)0x00010000U)
Kojto 119:aae6fcc7d9bb 1675 #define GPIO_OSPEEDER_OSPEED8_1 ((uint32_t)0x00020000U)
Kojto 119:aae6fcc7d9bb 1676 #define GPIO_OSPEEDER_OSPEED9 ((uint32_t)0x000C0000U)
Kojto 119:aae6fcc7d9bb 1677 #define GPIO_OSPEEDER_OSPEED9_0 ((uint32_t)0x00040000U)
Kojto 119:aae6fcc7d9bb 1678 #define GPIO_OSPEEDER_OSPEED9_1 ((uint32_t)0x00080000U)
Kojto 119:aae6fcc7d9bb 1679 #define GPIO_OSPEEDER_OSPEED10 ((uint32_t)0x00300000U)
Kojto 119:aae6fcc7d9bb 1680 #define GPIO_OSPEEDER_OSPEED10_0 ((uint32_t)0x00100000U)
Kojto 119:aae6fcc7d9bb 1681 #define GPIO_OSPEEDER_OSPEED10_1 ((uint32_t)0x00200000U)
Kojto 119:aae6fcc7d9bb 1682 #define GPIO_OSPEEDER_OSPEED11 ((uint32_t)0x00C00000U)
Kojto 119:aae6fcc7d9bb 1683 #define GPIO_OSPEEDER_OSPEED11_0 ((uint32_t)0x00400000U)
Kojto 119:aae6fcc7d9bb 1684 #define GPIO_OSPEEDER_OSPEED11_1 ((uint32_t)0x00800000U)
Kojto 119:aae6fcc7d9bb 1685 #define GPIO_OSPEEDER_OSPEED12 ((uint32_t)0x03000000U)
Kojto 119:aae6fcc7d9bb 1686 #define GPIO_OSPEEDER_OSPEED12_0 ((uint32_t)0x01000000U)
Kojto 119:aae6fcc7d9bb 1687 #define GPIO_OSPEEDER_OSPEED12_1 ((uint32_t)0x02000000U)
Kojto 119:aae6fcc7d9bb 1688 #define GPIO_OSPEEDER_OSPEED13 ((uint32_t)0x0C000000U)
Kojto 119:aae6fcc7d9bb 1689 #define GPIO_OSPEEDER_OSPEED13_0 ((uint32_t)0x04000000U)
Kojto 119:aae6fcc7d9bb 1690 #define GPIO_OSPEEDER_OSPEED13_1 ((uint32_t)0x08000000U)
Kojto 119:aae6fcc7d9bb 1691 #define GPIO_OSPEEDER_OSPEED14 ((uint32_t)0x30000000U)
Kojto 119:aae6fcc7d9bb 1692 #define GPIO_OSPEEDER_OSPEED14_0 ((uint32_t)0x10000000U)
Kojto 119:aae6fcc7d9bb 1693 #define GPIO_OSPEEDER_OSPEED14_1 ((uint32_t)0x20000000U)
Kojto 119:aae6fcc7d9bb 1694 #define GPIO_OSPEEDER_OSPEED15 ((uint32_t)0xC0000000U)
Kojto 119:aae6fcc7d9bb 1695 #define GPIO_OSPEEDER_OSPEED15_0 ((uint32_t)0x40000000U)
Kojto 119:aae6fcc7d9bb 1696 #define GPIO_OSPEEDER_OSPEED15_1 ((uint32_t)0x80000000U)
Kojto 99:dbbf35b96557 1697
Kojto 99:dbbf35b96557 1698 /******************* Bit definition for GPIO_PUPDR register ******************/
Kojto 119:aae6fcc7d9bb 1699 #define GPIO_PUPDR_PUPD0 ((uint32_t)0x00000003U)
Kojto 119:aae6fcc7d9bb 1700 #define GPIO_PUPDR_PUPD0_0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1701 #define GPIO_PUPDR_PUPD0_1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1702 #define GPIO_PUPDR_PUPD1 ((uint32_t)0x0000000CU)
Kojto 119:aae6fcc7d9bb 1703 #define GPIO_PUPDR_PUPD1_0 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1704 #define GPIO_PUPDR_PUPD1_1 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1705 #define GPIO_PUPDR_PUPD2 ((uint32_t)0x00000030U)
Kojto 119:aae6fcc7d9bb 1706 #define GPIO_PUPDR_PUPD2_0 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1707 #define GPIO_PUPDR_PUPD2_1 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1708 #define GPIO_PUPDR_PUPD3 ((uint32_t)0x000000C0U)
Kojto 119:aae6fcc7d9bb 1709 #define GPIO_PUPDR_PUPD3_0 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1710 #define GPIO_PUPDR_PUPD3_1 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1711 #define GPIO_PUPDR_PUPD4 ((uint32_t)0x00000300U)
Kojto 119:aae6fcc7d9bb 1712 #define GPIO_PUPDR_PUPD4_0 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1713 #define GPIO_PUPDR_PUPD4_1 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1714 #define GPIO_PUPDR_PUPD5 ((uint32_t)0x00000C00U)
Kojto 119:aae6fcc7d9bb 1715 #define GPIO_PUPDR_PUPD5_0 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1716 #define GPIO_PUPDR_PUPD5_1 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1717 #define GPIO_PUPDR_PUPD6 ((uint32_t)0x00003000U)
Kojto 119:aae6fcc7d9bb 1718 #define GPIO_PUPDR_PUPD6_0 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1719 #define GPIO_PUPDR_PUPD6_1 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1720 #define GPIO_PUPDR_PUPD7 ((uint32_t)0x0000C000U)
Kojto 119:aae6fcc7d9bb 1721 #define GPIO_PUPDR_PUPD7_0 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1722 #define GPIO_PUPDR_PUPD7_1 ((uint32_t)0x00008000U)
Kojto 119:aae6fcc7d9bb 1723 #define GPIO_PUPDR_PUPD8 ((uint32_t)0x00030000U)
Kojto 119:aae6fcc7d9bb 1724 #define GPIO_PUPDR_PUPD8_0 ((uint32_t)0x00010000U)
Kojto 119:aae6fcc7d9bb 1725 #define GPIO_PUPDR_PUPD8_1 ((uint32_t)0x00020000U)
Kojto 119:aae6fcc7d9bb 1726 #define GPIO_PUPDR_PUPD9 ((uint32_t)0x000C0000U)
Kojto 119:aae6fcc7d9bb 1727 #define GPIO_PUPDR_PUPD9_0 ((uint32_t)0x00040000U)
Kojto 119:aae6fcc7d9bb 1728 #define GPIO_PUPDR_PUPD9_1 ((uint32_t)0x00080000U)
Kojto 119:aae6fcc7d9bb 1729 #define GPIO_PUPDR_PUPD10 ((uint32_t)0x00300000U)
Kojto 119:aae6fcc7d9bb 1730 #define GPIO_PUPDR_PUPD10_0 ((uint32_t)0x00100000U)
Kojto 119:aae6fcc7d9bb 1731 #define GPIO_PUPDR_PUPD10_1 ((uint32_t)0x00200000U)
Kojto 119:aae6fcc7d9bb 1732 #define GPIO_PUPDR_PUPD11 ((uint32_t)0x00C00000U)
Kojto 119:aae6fcc7d9bb 1733 #define GPIO_PUPDR_PUPD11_0 ((uint32_t)0x00400000U)
Kojto 119:aae6fcc7d9bb 1734 #define GPIO_PUPDR_PUPD11_1 ((uint32_t)0x00800000U)
Kojto 119:aae6fcc7d9bb 1735 #define GPIO_PUPDR_PUPD12 ((uint32_t)0x03000000U)
Kojto 119:aae6fcc7d9bb 1736 #define GPIO_PUPDR_PUPD12_0 ((uint32_t)0x01000000U)
Kojto 119:aae6fcc7d9bb 1737 #define GPIO_PUPDR_PUPD12_1 ((uint32_t)0x02000000U)
Kojto 119:aae6fcc7d9bb 1738 #define GPIO_PUPDR_PUPD13 ((uint32_t)0x0C000000U)
Kojto 119:aae6fcc7d9bb 1739 #define GPIO_PUPDR_PUPD13_0 ((uint32_t)0x04000000U)
Kojto 119:aae6fcc7d9bb 1740 #define GPIO_PUPDR_PUPD13_1 ((uint32_t)0x08000000U)
Kojto 119:aae6fcc7d9bb 1741 #define GPIO_PUPDR_PUPD14 ((uint32_t)0x30000000U)
Kojto 119:aae6fcc7d9bb 1742 #define GPIO_PUPDR_PUPD14_0 ((uint32_t)0x10000000U)
Kojto 119:aae6fcc7d9bb 1743 #define GPIO_PUPDR_PUPD14_1 ((uint32_t)0x20000000U)
Kojto 119:aae6fcc7d9bb 1744 #define GPIO_PUPDR_PUPD15 ((uint32_t)0xC0000000U)
Kojto 119:aae6fcc7d9bb 1745 #define GPIO_PUPDR_PUPD15_0 ((uint32_t)0x40000000U)
Kojto 119:aae6fcc7d9bb 1746 #define GPIO_PUPDR_PUPD15_1 ((uint32_t)0x80000000U)
Kojto 99:dbbf35b96557 1747
Kojto 99:dbbf35b96557 1748 /******************* Bit definition for GPIO_IDR register *******************/
Kojto 119:aae6fcc7d9bb 1749 #define GPIO_IDR_ID0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1750 #define GPIO_IDR_ID1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1751 #define GPIO_IDR_ID2 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1752 #define GPIO_IDR_ID3 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1753 #define GPIO_IDR_ID4 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1754 #define GPIO_IDR_ID5 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1755 #define GPIO_IDR_ID6 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1756 #define GPIO_IDR_ID7 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1757 #define GPIO_IDR_ID8 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1758 #define GPIO_IDR_ID9 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1759 #define GPIO_IDR_ID10 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1760 #define GPIO_IDR_ID11 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1761 #define GPIO_IDR_ID12 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1762 #define GPIO_IDR_ID13 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1763 #define GPIO_IDR_ID14 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1764 #define GPIO_IDR_ID15 ((uint32_t)0x00008000U)
Kojto 99:dbbf35b96557 1765
Kojto 99:dbbf35b96557 1766 /****************** Bit definition for GPIO_ODR register ********************/
Kojto 119:aae6fcc7d9bb 1767 #define GPIO_ODR_OD0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1768 #define GPIO_ODR_OD1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1769 #define GPIO_ODR_OD2 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1770 #define GPIO_ODR_OD3 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1771 #define GPIO_ODR_OD4 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1772 #define GPIO_ODR_OD5 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1773 #define GPIO_ODR_OD6 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1774 #define GPIO_ODR_OD7 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1775 #define GPIO_ODR_OD8 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1776 #define GPIO_ODR_OD9 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1777 #define GPIO_ODR_OD10 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1778 #define GPIO_ODR_OD11 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1779 #define GPIO_ODR_OD12 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1780 #define GPIO_ODR_OD13 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1781 #define GPIO_ODR_OD14 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1782 #define GPIO_ODR_OD15 ((uint32_t)0x00008000U)
Kojto 99:dbbf35b96557 1783
Kojto 99:dbbf35b96557 1784 /****************** Bit definition for GPIO_BSRR register ********************/
Kojto 119:aae6fcc7d9bb 1785 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1786 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1787 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1788 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1789 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1790 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1791 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1792 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1793 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1794 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1795 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1796 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1797 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1798 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1799 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1800 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000U)
Kojto 119:aae6fcc7d9bb 1801 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000U)
Kojto 119:aae6fcc7d9bb 1802 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000U)
Kojto 119:aae6fcc7d9bb 1803 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000U)
Kojto 119:aae6fcc7d9bb 1804 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000U)
Kojto 119:aae6fcc7d9bb 1805 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000U)
Kojto 119:aae6fcc7d9bb 1806 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000U)
Kojto 119:aae6fcc7d9bb 1807 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000U)
Kojto 119:aae6fcc7d9bb 1808 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000U)
Kojto 119:aae6fcc7d9bb 1809 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000U)
Kojto 119:aae6fcc7d9bb 1810 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000U)
Kojto 119:aae6fcc7d9bb 1811 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000U)
Kojto 119:aae6fcc7d9bb 1812 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000U)
Kojto 119:aae6fcc7d9bb 1813 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000U)
Kojto 119:aae6fcc7d9bb 1814 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000U)
Kojto 119:aae6fcc7d9bb 1815 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000U)
Kojto 119:aae6fcc7d9bb 1816 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000U)
Kojto 99:dbbf35b96557 1817
Kojto 99:dbbf35b96557 1818 /****************** Bit definition for GPIO_LCKR register ********************/
Kojto 119:aae6fcc7d9bb 1819 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1820 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1821 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1822 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1823 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1824 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1825 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1826 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1827 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1828 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1829 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1830 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1831 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1832 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1833 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1834 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000U)
Kojto 119:aae6fcc7d9bb 1835 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000U)
Kojto 119:aae6fcc7d9bb 1836
Kojto 119:aae6fcc7d9bb 1837 /****************** Bit definition for GPIO_AFRL register ********************/
Kojto 119:aae6fcc7d9bb 1838 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000FU)
Kojto 119:aae6fcc7d9bb 1839 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0U)
Kojto 119:aae6fcc7d9bb 1840 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00U)
Kojto 119:aae6fcc7d9bb 1841 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000U)
Kojto 119:aae6fcc7d9bb 1842 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000U)
Kojto 119:aae6fcc7d9bb 1843 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000U)
Kojto 119:aae6fcc7d9bb 1844 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000U)
Kojto 119:aae6fcc7d9bb 1845 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000U)
Kojto 119:aae6fcc7d9bb 1846
Kojto 119:aae6fcc7d9bb 1847 /****************** Bit definition for GPIO_AFRH register ********************/
Kojto 119:aae6fcc7d9bb 1848 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000FU)
Kojto 119:aae6fcc7d9bb 1849 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0U)
Kojto 119:aae6fcc7d9bb 1850 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00U)
Kojto 119:aae6fcc7d9bb 1851 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000U)
Kojto 119:aae6fcc7d9bb 1852 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000U)
Kojto 119:aae6fcc7d9bb 1853 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000U)
Kojto 119:aae6fcc7d9bb 1854 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000U)
Kojto 119:aae6fcc7d9bb 1855 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000U)
Kojto 99:dbbf35b96557 1856
Kojto 99:dbbf35b96557 1857 /****************** Bit definition for GPIO_BRR register *********************/
Kojto 119:aae6fcc7d9bb 1858 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 1859 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 1860 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 1861 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 1862 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010U)
Kojto 119:aae6fcc7d9bb 1863 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 1864 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040U)
Kojto 119:aae6fcc7d9bb 1865 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080U)
Kojto 119:aae6fcc7d9bb 1866 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100U)
Kojto 119:aae6fcc7d9bb 1867 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200U)
Kojto 119:aae6fcc7d9bb 1868 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400U)
Kojto 119:aae6fcc7d9bb 1869 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800U)
Kojto 119:aae6fcc7d9bb 1870 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000U)
Kojto 119:aae6fcc7d9bb 1871 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000U)
Kojto 119:aae6fcc7d9bb 1872 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000U)
Kojto 119:aae6fcc7d9bb 1873 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000U)
Kojto 99:dbbf35b96557 1874
Kojto 99:dbbf35b96557 1875 /******************************************************************************/
Kojto 99:dbbf35b96557 1876 /* */
Kojto 99:dbbf35b96557 1877 /* Inter-integrated Circuit Interface (I2C) */
Kojto 99:dbbf35b96557 1878 /* */
Kojto 99:dbbf35b96557 1879 /******************************************************************************/
Kojto 99:dbbf35b96557 1880
Kojto 99:dbbf35b96557 1881 /******************* Bit definition for I2C_CR1 register *******************/
Kojto 119:aae6fcc7d9bb 1882 #define I2C_CR1_PE ((uint32_t)0x00000001U) /*!< Peripheral enable */
Kojto 119:aae6fcc7d9bb 1883 #define I2C_CR1_TXIE ((uint32_t)0x00000002U) /*!< TX interrupt enable */
Kojto 119:aae6fcc7d9bb 1884 #define I2C_CR1_RXIE ((uint32_t)0x00000004U) /*!< RX interrupt enable */
Kojto 119:aae6fcc7d9bb 1885 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008U) /*!< Address match interrupt enable */
Kojto 119:aae6fcc7d9bb 1886 #define I2C_CR1_NACKIE ((uint32_t)0x00000010U) /*!< NACK received interrupt enable */
Kojto 119:aae6fcc7d9bb 1887 #define I2C_CR1_STOPIE ((uint32_t)0x00000020U) /*!< STOP detection interrupt enable */
Kojto 119:aae6fcc7d9bb 1888 #define I2C_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transfer complete interrupt enable */
Kojto 119:aae6fcc7d9bb 1889 #define I2C_CR1_ERRIE ((uint32_t)0x00000080U) /*!< Errors interrupt enable */
Kojto 119:aae6fcc7d9bb 1890 #define I2C_CR1_DNF ((uint32_t)0x00000F00U) /*!< Digital noise filter */
Kojto 119:aae6fcc7d9bb 1891 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000U) /*!< Analog noise filter OFF */
Kojto 119:aae6fcc7d9bb 1892 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000U) /*!< DMA transmission requests enable */
Kojto 119:aae6fcc7d9bb 1893 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000U) /*!< DMA reception requests enable */
Kojto 119:aae6fcc7d9bb 1894 #define I2C_CR1_SBC ((uint32_t)0x00010000U) /*!< Slave byte control */
Kojto 119:aae6fcc7d9bb 1895 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000U) /*!< Clock stretching disable */
Kojto 119:aae6fcc7d9bb 1896 #define I2C_CR1_WUPEN ((uint32_t)0x00040000U) /*!< Wakeup from STOP enable */
Kojto 119:aae6fcc7d9bb 1897 #define I2C_CR1_GCEN ((uint32_t)0x00080000U) /*!< General call enable */
Kojto 119:aae6fcc7d9bb 1898 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000U) /*!< SMBus host address enable */
Kojto 119:aae6fcc7d9bb 1899 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000U) /*!< SMBus device default address enable */
Kojto 119:aae6fcc7d9bb 1900 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000U) /*!< SMBus alert enable */
Kojto 119:aae6fcc7d9bb 1901 #define I2C_CR1_PECEN ((uint32_t)0x00800000U) /*!< PEC enable */
Kojto 99:dbbf35b96557 1902
Kojto 99:dbbf35b96557 1903 /****************** Bit definition for I2C_CR2 register ********************/
Kojto 119:aae6fcc7d9bb 1904 #define I2C_CR2_SADD ((uint32_t)0x000003FFU) /*!< Slave address (master mode) */
Kojto 119:aae6fcc7d9bb 1905 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400U) /*!< Transfer direction (master mode) */
Kojto 119:aae6fcc7d9bb 1906 #define I2C_CR2_ADD10 ((uint32_t)0x00000800U) /*!< 10-bit addressing mode (master mode) */
Kojto 119:aae6fcc7d9bb 1907 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000U) /*!< 10-bit address header only read direction (master mode) */
Kojto 119:aae6fcc7d9bb 1908 #define I2C_CR2_START ((uint32_t)0x00002000U) /*!< START generation */
Kojto 119:aae6fcc7d9bb 1909 #define I2C_CR2_STOP ((uint32_t)0x00004000U) /*!< STOP generation (master mode) */
Kojto 119:aae6fcc7d9bb 1910 #define I2C_CR2_NACK ((uint32_t)0x00008000U) /*!< NACK generation (slave mode) */
Kojto 119:aae6fcc7d9bb 1911 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000U) /*!< Number of bytes */
Kojto 119:aae6fcc7d9bb 1912 #define I2C_CR2_RELOAD ((uint32_t)0x01000000U) /*!< NBYTES reload mode */
Kojto 119:aae6fcc7d9bb 1913 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000U) /*!< Automatic end mode (master mode) */
Kojto 119:aae6fcc7d9bb 1914 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000U) /*!< Packet error checking byte */
Kojto 99:dbbf35b96557 1915
Kojto 99:dbbf35b96557 1916 /******************* Bit definition for I2C_OAR1 register ******************/
Kojto 119:aae6fcc7d9bb 1917 #define I2C_OAR1_OA1 ((uint32_t)0x000003FFU) /*!< Interface own address 1 */
Kojto 119:aae6fcc7d9bb 1918 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400U) /*!< Own address 1 10-bit mode */
Kojto 119:aae6fcc7d9bb 1919 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000U) /*!< Own address 1 enable */
Kojto 99:dbbf35b96557 1920
Kojto 99:dbbf35b96557 1921 /******************* Bit definition for I2C_OAR2 register ******************/
Kojto 119:aae6fcc7d9bb 1922 #define I2C_OAR2_OA2 ((uint32_t)0x000000FEU) /*!< Interface own address 2 */
Kojto 119:aae6fcc7d9bb 1923 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700U) /*!< Own address 2 masks */
Kojto 119:aae6fcc7d9bb 1924 #define I2C_OAR2_OA2NOMASK ((uint32_t)0x00000000U) /*!< No mask */
Kojto 119:aae6fcc7d9bb 1925 #define I2C_OAR2_OA2MASK01 ((uint32_t)0x00000100U) /*!< OA2[1] is masked, Only OA2[7:2] are compared */
Kojto 119:aae6fcc7d9bb 1926 #define I2C_OAR2_OA2MASK02 ((uint32_t)0x00000200U) /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
Kojto 119:aae6fcc7d9bb 1927 #define I2C_OAR2_OA2MASK03 ((uint32_t)0x00000300U) /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
Kojto 119:aae6fcc7d9bb 1928 #define I2C_OAR2_OA2MASK04 ((uint32_t)0x00000400U) /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
Kojto 119:aae6fcc7d9bb 1929 #define I2C_OAR2_OA2MASK05 ((uint32_t)0x00000500U) /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
Kojto 119:aae6fcc7d9bb 1930 #define I2C_OAR2_OA2MASK06 ((uint32_t)0x00000600U) /*!< OA2[6:1] is masked, Only OA2[7] are compared */
Kojto 119:aae6fcc7d9bb 1931 #define I2C_OAR2_OA2MASK07 ((uint32_t)0x00000700U) /*!< OA2[7:1] is masked, No comparison is done */
Kojto 119:aae6fcc7d9bb 1932 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000U) /*!< Own address 2 enable */
Kojto 99:dbbf35b96557 1933
Kojto 99:dbbf35b96557 1934 /******************* Bit definition for I2C_TIMINGR register *******************/
Kojto 119:aae6fcc7d9bb 1935 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FFU) /*!< SCL low period (master mode) */
Kojto 119:aae6fcc7d9bb 1936 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00U) /*!< SCL high period (master mode) */
Kojto 119:aae6fcc7d9bb 1937 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000U) /*!< Data hold time */
Kojto 119:aae6fcc7d9bb 1938 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000U) /*!< Data setup time */
Kojto 119:aae6fcc7d9bb 1939 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000U) /*!< Timings prescaler */
Kojto 99:dbbf35b96557 1940
Kojto 99:dbbf35b96557 1941 /******************* Bit definition for I2C_TIMEOUTR register *******************/
Kojto 119:aae6fcc7d9bb 1942 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFFU) /*!< Bus timeout A */
Kojto 119:aae6fcc7d9bb 1943 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000U) /*!< Idle clock timeout detection */
Kojto 119:aae6fcc7d9bb 1944 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000U) /*!< Clock timeout enable */
Kojto 119:aae6fcc7d9bb 1945 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000U) /*!< Bus timeout B*/
Kojto 119:aae6fcc7d9bb 1946 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000U) /*!< Extended clock timeout enable */
Kojto 99:dbbf35b96557 1947
Kojto 99:dbbf35b96557 1948 /****************** Bit definition for I2C_ISR register *********************/
Kojto 119:aae6fcc7d9bb 1949 #define I2C_ISR_TXE ((uint32_t)0x00000001U) /*!< Transmit data register empty */
Kojto 119:aae6fcc7d9bb 1950 #define I2C_ISR_TXIS ((uint32_t)0x00000002U) /*!< Transmit interrupt status */
Kojto 119:aae6fcc7d9bb 1951 #define I2C_ISR_RXNE ((uint32_t)0x00000004U) /*!< Receive data register not empty */
Kojto 119:aae6fcc7d9bb 1952 #define I2C_ISR_ADDR ((uint32_t)0x00000008U) /*!< Address matched (slave mode)*/
Kojto 119:aae6fcc7d9bb 1953 #define I2C_ISR_NACKF ((uint32_t)0x00000010U) /*!< NACK received flag */
Kojto 119:aae6fcc7d9bb 1954 #define I2C_ISR_STOPF ((uint32_t)0x00000020U) /*!< STOP detection flag */
Kojto 119:aae6fcc7d9bb 1955 #define I2C_ISR_TC ((uint32_t)0x00000040U) /*!< Transfer complete (master mode) */
Kojto 119:aae6fcc7d9bb 1956 #define I2C_ISR_TCR ((uint32_t)0x00000080U) /*!< Transfer complete reload */
Kojto 119:aae6fcc7d9bb 1957 #define I2C_ISR_BERR ((uint32_t)0x00000100U) /*!< Bus error */
Kojto 119:aae6fcc7d9bb 1958 #define I2C_ISR_ARLO ((uint32_t)0x00000200U) /*!< Arbitration lost */
Kojto 119:aae6fcc7d9bb 1959 #define I2C_ISR_OVR ((uint32_t)0x00000400U) /*!< Overrun/Underrun */
Kojto 119:aae6fcc7d9bb 1960 #define I2C_ISR_PECERR ((uint32_t)0x00000800U) /*!< PEC error in reception */
Kojto 119:aae6fcc7d9bb 1961 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000U) /*!< Timeout or Tlow detection flag */
Kojto 119:aae6fcc7d9bb 1962 #define I2C_ISR_ALERT ((uint32_t)0x00002000U) /*!< SMBus alert */
Kojto 119:aae6fcc7d9bb 1963 #define I2C_ISR_BUSY ((uint32_t)0x00008000U) /*!< Bus busy */
Kojto 119:aae6fcc7d9bb 1964 #define I2C_ISR_DIR ((uint32_t)0x00010000U) /*!< Transfer direction (slave mode) */
Kojto 119:aae6fcc7d9bb 1965 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000U) /*!< Address match code (slave mode) */
Kojto 99:dbbf35b96557 1966
Kojto 99:dbbf35b96557 1967 /****************** Bit definition for I2C_ICR register *********************/
Kojto 119:aae6fcc7d9bb 1968 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008U) /*!< Address matched clear flag */
Kojto 119:aae6fcc7d9bb 1969 #define I2C_ICR_NACKCF ((uint32_t)0x00000010U) /*!< NACK clear flag */
Kojto 119:aae6fcc7d9bb 1970 #define I2C_ICR_STOPCF ((uint32_t)0x00000020U) /*!< STOP detection clear flag */
Kojto 119:aae6fcc7d9bb 1971 #define I2C_ICR_BERRCF ((uint32_t)0x00000100U) /*!< Bus error clear flag */
Kojto 119:aae6fcc7d9bb 1972 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200U) /*!< Arbitration lost clear flag */
Kojto 119:aae6fcc7d9bb 1973 #define I2C_ICR_OVRCF ((uint32_t)0x00000400U) /*!< Overrun/Underrun clear flag */
Kojto 119:aae6fcc7d9bb 1974 #define I2C_ICR_PECCF ((uint32_t)0x00000800U) /*!< PAC error clear flag */
Kojto 119:aae6fcc7d9bb 1975 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000U) /*!< Timeout clear flag */
Kojto 119:aae6fcc7d9bb 1976 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000U) /*!< Alert clear flag */
Kojto 99:dbbf35b96557 1977
Kojto 99:dbbf35b96557 1978 /****************** Bit definition for I2C_PECR register *********************/
Kojto 119:aae6fcc7d9bb 1979 #define I2C_PECR_PEC ((uint32_t)0x000000FFU) /*!< PEC register */
Kojto 99:dbbf35b96557 1980
Kojto 99:dbbf35b96557 1981 /****************** Bit definition for I2C_RXDR register *********************/
Kojto 119:aae6fcc7d9bb 1982 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FFU) /*!< 8-bit receive data */
Kojto 99:dbbf35b96557 1983
Kojto 99:dbbf35b96557 1984 /****************** Bit definition for I2C_TXDR register *********************/
Kojto 119:aae6fcc7d9bb 1985 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FFU) /*!< 8-bit transmit data */
Kojto 99:dbbf35b96557 1986
Kojto 99:dbbf35b96557 1987 /******************************************************************************/
Kojto 99:dbbf35b96557 1988 /* */
Kojto 99:dbbf35b96557 1989 /* Independent WATCHDOG (IWDG) */
Kojto 99:dbbf35b96557 1990 /* */
Kojto 99:dbbf35b96557 1991 /******************************************************************************/
Kojto 99:dbbf35b96557 1992 /******************* Bit definition for IWDG_KR register ********************/
Kojto 119:aae6fcc7d9bb 1993 #define IWDG_KR_KEY ((uint32_t)0x0000FFFFU) /*!< Key value (write only, read 0000h) */
Kojto 99:dbbf35b96557 1994
Kojto 99:dbbf35b96557 1995 /******************* Bit definition for IWDG_PR register ********************/
Kojto 119:aae6fcc7d9bb 1996 #define IWDG_PR_PR ((uint32_t)0x00000007U) /*!< PR[2:0] (Prescaler divider) */
Kojto 119:aae6fcc7d9bb 1997 #define IWDG_PR_PR_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 1998 #define IWDG_PR_PR_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 1999 #define IWDG_PR_PR_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 99:dbbf35b96557 2000
Kojto 99:dbbf35b96557 2001 /******************* Bit definition for IWDG_RLR register *******************/
Kojto 119:aae6fcc7d9bb 2002 #define IWDG_RLR_RL ((uint32_t)0x00000FFFU) /*!< Watchdog counter reload value */
Kojto 99:dbbf35b96557 2003
Kojto 99:dbbf35b96557 2004 /******************* Bit definition for IWDG_SR register ********************/
Kojto 119:aae6fcc7d9bb 2005 #define IWDG_SR_PVU ((uint32_t)0x00000001U) /*!< Watchdog prescaler value update */
Kojto 119:aae6fcc7d9bb 2006 #define IWDG_SR_RVU ((uint32_t)0x00000002U) /*!< Watchdog counter reload value update */
Kojto 119:aae6fcc7d9bb 2007 #define IWDG_SR_WVU ((uint32_t)0x00000004U) /*!< Watchdog counter window value update */
Kojto 99:dbbf35b96557 2008
Kojto 99:dbbf35b96557 2009 /******************* Bit definition for IWDG_KR register ********************/
Kojto 119:aae6fcc7d9bb 2010 #define IWDG_WINR_WIN ((uint32_t)0x00000FFFU) /*!< Watchdog counter window value */
Kojto 99:dbbf35b96557 2011
Kojto 99:dbbf35b96557 2012 /******************************************************************************/
Kojto 99:dbbf35b96557 2013 /* */
Kojto 99:dbbf35b96557 2014 /* LCD Controller (LCD) */
Kojto 99:dbbf35b96557 2015 /* */
Kojto 99:dbbf35b96557 2016 /******************************************************************************/
Kojto 99:dbbf35b96557 2017
Kojto 99:dbbf35b96557 2018 /******************* Bit definition for LCD_CR register *********************/
Kojto 119:aae6fcc7d9bb 2019 #define LCD_CR_LCDEN ((uint32_t)0x00000001U) /*!< LCD Enable Bit */
Kojto 119:aae6fcc7d9bb 2020 #define LCD_CR_VSEL ((uint32_t)0x00000002U) /*!< Voltage source selector Bit */
Kojto 119:aae6fcc7d9bb 2021
Kojto 119:aae6fcc7d9bb 2022 #define LCD_CR_DUTY ((uint32_t)0x0000001CU) /*!< DUTY[2:0] bits (Duty selector) */
Kojto 119:aae6fcc7d9bb 2023 #define LCD_CR_DUTY_0 ((uint32_t)0x00000004U) /*!< Duty selector Bit 0 */
Kojto 119:aae6fcc7d9bb 2024 #define LCD_CR_DUTY_1 ((uint32_t)0x00000008U) /*!< Duty selector Bit 1 */
Kojto 119:aae6fcc7d9bb 2025 #define LCD_CR_DUTY_2 ((uint32_t)0x00000010U) /*!< Duty selector Bit 2 */
Kojto 119:aae6fcc7d9bb 2026
Kojto 119:aae6fcc7d9bb 2027 #define LCD_CR_BIAS ((uint32_t)0x00000060U) /*!< BIAS[1:0] bits (Bias selector) */
Kojto 119:aae6fcc7d9bb 2028 #define LCD_CR_BIAS_0 ((uint32_t)0x00000020U) /*!< Bias selector Bit 0 */
Kojto 119:aae6fcc7d9bb 2029 #define LCD_CR_BIAS_1 ((uint32_t)0x00000040U) /*!< Bias selector Bit 1 */
Kojto 119:aae6fcc7d9bb 2030
Kojto 119:aae6fcc7d9bb 2031 #define LCD_CR_MUX_SEG ((uint32_t)0x00000080U) /*!< Mux Segment Enable Bit */
Kojto 99:dbbf35b96557 2032
Kojto 99:dbbf35b96557 2033 /******************* Bit definition for LCD_FCR register ********************/
Kojto 119:aae6fcc7d9bb 2034 #define LCD_FCR_HD ((uint32_t)0x00000001U) /*!< High Drive Enable Bit */
Kojto 119:aae6fcc7d9bb 2035 #define LCD_FCR_SOFIE ((uint32_t)0x00000002U) /*!< Start of Frame Interrupt Enable Bit */
Kojto 119:aae6fcc7d9bb 2036 #define LCD_FCR_UDDIE ((uint32_t)0x00000008U) /*!< Update Display Done Interrupt Enable Bit */
Kojto 119:aae6fcc7d9bb 2037
Kojto 119:aae6fcc7d9bb 2038 #define LCD_FCR_PON ((uint32_t)0x00000070U) /*!< PON[2:0] bits (Puls ON Duration) */
Kojto 119:aae6fcc7d9bb 2039 #define LCD_FCR_PON_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2040 #define LCD_FCR_PON_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2041 #define LCD_FCR_PON_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2042
Kojto 119:aae6fcc7d9bb 2043 #define LCD_FCR_DEAD ((uint32_t)0x00000380U) /*!< DEAD[2:0] bits (DEAD Time) */
Kojto 119:aae6fcc7d9bb 2044 #define LCD_FCR_DEAD_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2045 #define LCD_FCR_DEAD_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2046 #define LCD_FCR_DEAD_2 ((uint32_t)0x00000200U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2047
Kojto 119:aae6fcc7d9bb 2048 #define LCD_FCR_CC ((uint32_t)0x00001C00U) /*!< CC[2:0] bits (Contrast Control) */
Kojto 119:aae6fcc7d9bb 2049 #define LCD_FCR_CC_0 ((uint32_t)0x00000400U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2050 #define LCD_FCR_CC_1 ((uint32_t)0x00000800U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2051 #define LCD_FCR_CC_2 ((uint32_t)0x00001000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2052
Kojto 119:aae6fcc7d9bb 2053 #define LCD_FCR_BLINKF ((uint32_t)0x0000E000U) /*!< BLINKF[2:0] bits (Blink Frequency) */
Kojto 119:aae6fcc7d9bb 2054 #define LCD_FCR_BLINKF_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2055 #define LCD_FCR_BLINKF_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2056 #define LCD_FCR_BLINKF_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2057
Kojto 119:aae6fcc7d9bb 2058 #define LCD_FCR_BLINK ((uint32_t)0x00030000U) /*!< BLINK[1:0] bits (Blink Enable) */
Kojto 119:aae6fcc7d9bb 2059 #define LCD_FCR_BLINK_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2060 #define LCD_FCR_BLINK_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2061
Kojto 119:aae6fcc7d9bb 2062 #define LCD_FCR_DIV ((uint32_t)0x003C0000U) /*!< DIV[3:0] bits (Divider) */
Kojto 119:aae6fcc7d9bb 2063 #define LCD_FCR_PS ((uint32_t)0x03C00000U) /*!< PS[3:0] bits (Prescaler) */
Kojto 99:dbbf35b96557 2064
Kojto 99:dbbf35b96557 2065 /******************* Bit definition for LCD_SR register *********************/
Kojto 119:aae6fcc7d9bb 2066 #define LCD_SR_ENS ((uint32_t)0x00000001U) /*!< LCD Enabled Bit */
Kojto 119:aae6fcc7d9bb 2067 #define LCD_SR_SOF ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Bit */
Kojto 119:aae6fcc7d9bb 2068 #define LCD_SR_UDR ((uint32_t)0x00000004U) /*!< Update Display Request Bit */
Kojto 119:aae6fcc7d9bb 2069 #define LCD_SR_UDD ((uint32_t)0x00000008U) /*!< Update Display Done Flag Bit */
Kojto 119:aae6fcc7d9bb 2070 #define LCD_SR_RDY ((uint32_t)0x00000010U) /*!< Ready Flag Bit */
Kojto 119:aae6fcc7d9bb 2071 #define LCD_SR_FCRSR ((uint32_t)0x00000020U) /*!< LCD FCR Register Synchronization Flag Bit */
Kojto 99:dbbf35b96557 2072
Kojto 99:dbbf35b96557 2073 /******************* Bit definition for LCD_CLR register ********************/
Kojto 119:aae6fcc7d9bb 2074 #define LCD_CLR_SOFC ((uint32_t)0x00000002U) /*!< Start Of Frame Flag Clear Bit */
Kojto 119:aae6fcc7d9bb 2075 #define LCD_CLR_UDDC ((uint32_t)0x00000008U) /*!< Update Display Done Flag Clear Bit */
Kojto 99:dbbf35b96557 2076
Kojto 99:dbbf35b96557 2077 /******************* Bit definition for LCD_RAM register ********************/
Kojto 119:aae6fcc7d9bb 2078 #define LCD_RAM_SEGMENT_DATA ((uint32_t)0xFFFFFFFFU) /*!< Segment Data Bits */
Kojto 99:dbbf35b96557 2079
Kojto 99:dbbf35b96557 2080 /******************************************************************************/
Kojto 99:dbbf35b96557 2081 /* */
Kojto 99:dbbf35b96557 2082 /* Low Power Timer (LPTTIM) */
Kojto 99:dbbf35b96557 2083 /* */
Kojto 99:dbbf35b96557 2084 /******************************************************************************/
Kojto 99:dbbf35b96557 2085 /****************** Bit definition for LPTIM_ISR register *******************/
Kojto 119:aae6fcc7d9bb 2086 #define LPTIM_ISR_CMPM ((uint32_t)0x00000001U) /*!< Compare match */
Kojto 119:aae6fcc7d9bb 2087 #define LPTIM_ISR_ARRM ((uint32_t)0x00000002U) /*!< Autoreload match */
Kojto 119:aae6fcc7d9bb 2088 #define LPTIM_ISR_EXTTRIG ((uint32_t)0x00000004U) /*!< External trigger edge event */
Kojto 119:aae6fcc7d9bb 2089 #define LPTIM_ISR_CMPOK ((uint32_t)0x00000008U) /*!< Compare register update OK */
Kojto 119:aae6fcc7d9bb 2090 #define LPTIM_ISR_ARROK ((uint32_t)0x00000010U) /*!< Autoreload register update OK */
Kojto 119:aae6fcc7d9bb 2091 #define LPTIM_ISR_UP ((uint32_t)0x00000020U) /*!< Counter direction change down to up */
Kojto 119:aae6fcc7d9bb 2092 #define LPTIM_ISR_DOWN ((uint32_t)0x00000040U) /*!< Counter direction change up to down */
Kojto 99:dbbf35b96557 2093
Kojto 99:dbbf35b96557 2094 /****************** Bit definition for LPTIM_ICR register *******************/
Kojto 119:aae6fcc7d9bb 2095 #define LPTIM_ICR_CMPMCF ((uint32_t)0x00000001U) /*!< Compare match Clear Flag */
Kojto 119:aae6fcc7d9bb 2096 #define LPTIM_ICR_ARRMCF ((uint32_t)0x00000002U) /*!< Autoreload match Clear Flag */
Kojto 119:aae6fcc7d9bb 2097 #define LPTIM_ICR_EXTTRIGCF ((uint32_t)0x00000004U) /*!< External trigger edge event Clear Flag */
Kojto 119:aae6fcc7d9bb 2098 #define LPTIM_ICR_CMPOKCF ((uint32_t)0x00000008U) /*!< Compare register update OK Clear Flag */
Kojto 119:aae6fcc7d9bb 2099 #define LPTIM_ICR_ARROKCF ((uint32_t)0x00000010U) /*!< Autoreload register update OK Clear Flag */
Kojto 119:aae6fcc7d9bb 2100 #define LPTIM_ICR_UPCF ((uint32_t)0x00000020U) /*!< Counter direction change down to up Clear Flag */
Kojto 119:aae6fcc7d9bb 2101 #define LPTIM_ICR_DOWNCF ((uint32_t)0x00000040U) /*!< Counter direction change up to down Clear Flag */
Kojto 99:dbbf35b96557 2102
Kojto 99:dbbf35b96557 2103 /****************** Bit definition for LPTIM_IER register ********************/
Kojto 119:aae6fcc7d9bb 2104 #define LPTIM_IER_CMPMIE ((uint32_t)0x00000001U) /*!< Compare match Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2105 #define LPTIM_IER_ARRMIE ((uint32_t)0x00000002U) /*!< Autoreload match Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2106 #define LPTIM_IER_EXTTRIGIE ((uint32_t)0x00000004U) /*!< External trigger edge event Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2107 #define LPTIM_IER_CMPOKIE ((uint32_t)0x00000008U) /*!< Compare register update OK Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2108 #define LPTIM_IER_ARROKIE ((uint32_t)0x00000010U) /*!< Autoreload register update OK Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2109 #define LPTIM_IER_UPIE ((uint32_t)0x00000020U) /*!< Counter direction change down to up Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2110 #define LPTIM_IER_DOWNIE ((uint32_t)0x00000040U) /*!< Counter direction change up to down Interrupt Enable */
Kojto 99:dbbf35b96557 2111
Kojto 99:dbbf35b96557 2112 /****************** Bit definition for LPTIM_CFGR register *******************/
Kojto 119:aae6fcc7d9bb 2113 #define LPTIM_CFGR_CKSEL ((uint32_t)0x00000001U) /*!< Clock selector */
Kojto 119:aae6fcc7d9bb 2114
Kojto 119:aae6fcc7d9bb 2115 #define LPTIM_CFGR_CKPOL ((uint32_t)0x00000006U) /*!< CKPOL[1:0] bits (Clock polarity) */
Kojto 119:aae6fcc7d9bb 2116 #define LPTIM_CFGR_CKPOL_0 ((uint32_t)0x00000002U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2117 #define LPTIM_CFGR_CKPOL_1 ((uint32_t)0x00000004U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2118
Kojto 119:aae6fcc7d9bb 2119 #define LPTIM_CFGR_CKFLT ((uint32_t)0x00000018U) /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
Kojto 119:aae6fcc7d9bb 2120 #define LPTIM_CFGR_CKFLT_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2121 #define LPTIM_CFGR_CKFLT_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2122
Kojto 119:aae6fcc7d9bb 2123 #define LPTIM_CFGR_TRGFLT ((uint32_t)0x000000C0U) /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
Kojto 119:aae6fcc7d9bb 2124 #define LPTIM_CFGR_TRGFLT_0 ((uint32_t)0x00000040U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2125 #define LPTIM_CFGR_TRGFLT_1 ((uint32_t)0x00000080U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2126
Kojto 119:aae6fcc7d9bb 2127 #define LPTIM_CFGR_PRESC ((uint32_t)0x00000E00U) /*!< PRESC[2:0] bits (Clock prescaler) */
Kojto 119:aae6fcc7d9bb 2128 #define LPTIM_CFGR_PRESC_0 ((uint32_t)0x00000200U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2129 #define LPTIM_CFGR_PRESC_1 ((uint32_t)0x00000400U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2130 #define LPTIM_CFGR_PRESC_2 ((uint32_t)0x00000800U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2131
Kojto 119:aae6fcc7d9bb 2132 #define LPTIM_CFGR_TRIGSEL ((uint32_t)0x0000E000U) /*!< TRIGSEL[2:0]] bits (Trigger selector) */
Kojto 119:aae6fcc7d9bb 2133 #define LPTIM_CFGR_TRIGSEL_0 ((uint32_t)0x00002000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2134 #define LPTIM_CFGR_TRIGSEL_1 ((uint32_t)0x00004000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2135 #define LPTIM_CFGR_TRIGSEL_2 ((uint32_t)0x00008000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2136
Kojto 119:aae6fcc7d9bb 2137 #define LPTIM_CFGR_TRIGEN ((uint32_t)0x00060000U) /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
Kojto 119:aae6fcc7d9bb 2138 #define LPTIM_CFGR_TRIGEN_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2139 #define LPTIM_CFGR_TRIGEN_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2140
Kojto 119:aae6fcc7d9bb 2141 #define LPTIM_CFGR_TIMOUT ((uint32_t)0x00080000U) /*!< Timout enable */
Kojto 119:aae6fcc7d9bb 2142 #define LPTIM_CFGR_WAVE ((uint32_t)0x00100000U) /*!< Waveform shape */
Kojto 119:aae6fcc7d9bb 2143 #define LPTIM_CFGR_WAVPOL ((uint32_t)0x00200000U) /*!< Waveform shape polarity */
Kojto 119:aae6fcc7d9bb 2144 #define LPTIM_CFGR_PRELOAD ((uint32_t)0x00400000U) /*!< Reg update mode */
Kojto 119:aae6fcc7d9bb 2145 #define LPTIM_CFGR_COUNTMODE ((uint32_t)0x00800000U) /*!< Counter mode enable */
Kojto 119:aae6fcc7d9bb 2146 #define LPTIM_CFGR_ENC ((uint32_t)0x01000000U) /*!< Encoder mode enable */
Kojto 99:dbbf35b96557 2147
Kojto 99:dbbf35b96557 2148 /****************** Bit definition for LPTIM_CR register ********************/
Kojto 119:aae6fcc7d9bb 2149 #define LPTIM_CR_ENABLE ((uint32_t)0x00000001U) /*!< LPTIMer enable */
Kojto 119:aae6fcc7d9bb 2150 #define LPTIM_CR_SNGSTRT ((uint32_t)0x00000002U) /*!< Timer start in single mode */
Kojto 119:aae6fcc7d9bb 2151 #define LPTIM_CR_CNTSTRT ((uint32_t)0x00000004U) /*!< Timer start in continuous mode */
Kojto 99:dbbf35b96557 2152
Kojto 99:dbbf35b96557 2153 /****************** Bit definition for LPTIM_CMP register *******************/
Kojto 119:aae6fcc7d9bb 2154 #define LPTIM_CMP_CMP ((uint32_t)0x0000FFFFU) /*!< Compare register */
Kojto 99:dbbf35b96557 2155
Kojto 99:dbbf35b96557 2156 /****************** Bit definition for LPTIM_ARR register *******************/
Kojto 119:aae6fcc7d9bb 2157 #define LPTIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!< Auto reload register */
Kojto 99:dbbf35b96557 2158
Kojto 99:dbbf35b96557 2159 /****************** Bit definition for LPTIM_CNT register *******************/
Kojto 119:aae6fcc7d9bb 2160 #define LPTIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!< Counter register */
Kojto 99:dbbf35b96557 2161
Kojto 99:dbbf35b96557 2162 /******************************************************************************/
Kojto 99:dbbf35b96557 2163 /* */
Kojto 99:dbbf35b96557 2164 /* MIFARE Firewall */
Kojto 99:dbbf35b96557 2165 /* */
Kojto 99:dbbf35b96557 2166 /******************************************************************************/
Kojto 99:dbbf35b96557 2167
Kojto 99:dbbf35b96557 2168 /*******Bit definition for CSSA;CSL;NVDSSA;NVDSL;VDSSA;VDSL register */
Kojto 119:aae6fcc7d9bb 2169 #define FW_CSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Code Segment Start Address */
Kojto 119:aae6fcc7d9bb 2170 #define FW_CSL_LENG ((uint32_t)0x003FFF00U) /*!< Code Segment Length */
Kojto 119:aae6fcc7d9bb 2171 #define FW_NVDSSA_ADD ((uint32_t)0x00FFFF00U) /*!< Non Volatile Dat Segment Start Address */
Kojto 119:aae6fcc7d9bb 2172 #define FW_NVDSL_LENG ((uint32_t)0x003FFF00U) /*!< Non Volatile Data Segment Length */
Kojto 119:aae6fcc7d9bb 2173 #define FW_VDSSA_ADD ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Start Address */
Kojto 119:aae6fcc7d9bb 2174 #define FW_VDSL_LENG ((uint32_t)0x0000FFC0U) /*!< Volatile Data Segment Length */
Kojto 99:dbbf35b96557 2175
Kojto 99:dbbf35b96557 2176 /**************************Bit definition for CR register *********************/
Kojto 119:aae6fcc7d9bb 2177 #define FW_CR_FPA ((uint32_t)0x00000001U) /*!< Firewall Pre Arm*/
Kojto 119:aae6fcc7d9bb 2178 #define FW_CR_VDS ((uint32_t)0x00000002U) /*!< Volatile Data Sharing*/
Kojto 119:aae6fcc7d9bb 2179 #define FW_CR_VDE ((uint32_t)0x00000004U) /*!< Volatile Data Execution*/
Kojto 99:dbbf35b96557 2180
Kojto 99:dbbf35b96557 2181 /******************************************************************************/
Kojto 99:dbbf35b96557 2182 /* */
Kojto 99:dbbf35b96557 2183 /* Power Control (PWR) */
Kojto 99:dbbf35b96557 2184 /* */
Kojto 99:dbbf35b96557 2185 /******************************************************************************/
Kojto 99:dbbf35b96557 2186
Kojto 99:dbbf35b96557 2187 /******************** Bit definition for PWR_CR register ********************/
Kojto 119:aae6fcc7d9bb 2188 #define PWR_CR_LPSDSR ((uint32_t)0x00000001U) /*!< Low-power deepsleep/sleep/low power run */
Kojto 119:aae6fcc7d9bb 2189 #define PWR_CR_PDDS ((uint32_t)0x00000002U) /*!< Power Down Deepsleep */
Kojto 119:aae6fcc7d9bb 2190 #define PWR_CR_CWUF ((uint32_t)0x00000004U) /*!< Clear Wakeup Flag */
Kojto 119:aae6fcc7d9bb 2191 #define PWR_CR_CSBF ((uint32_t)0x00000008U) /*!< Clear Standby Flag */
Kojto 119:aae6fcc7d9bb 2192 #define PWR_CR_PVDE ((uint32_t)0x00000010U) /*!< Power Voltage Detector Enable */
Kojto 119:aae6fcc7d9bb 2193
Kojto 119:aae6fcc7d9bb 2194 #define PWR_CR_PLS ((uint32_t)0x000000E0U) /*!< PLS[2:0] bits (PVD Level Selection) */
Kojto 119:aae6fcc7d9bb 2195 #define PWR_CR_PLS_0 ((uint32_t)0x00000020U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2196 #define PWR_CR_PLS_1 ((uint32_t)0x00000040U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2197 #define PWR_CR_PLS_2 ((uint32_t)0x00000080U) /*!< Bit 2 */
Kojto 99:dbbf35b96557 2198
Kojto 99:dbbf35b96557 2199 /*!< PVD level configuration */
Kojto 119:aae6fcc7d9bb 2200 #define PWR_CR_PLS_LEV0 ((uint32_t)0x00000000U) /*!< PVD level 0 */
Kojto 119:aae6fcc7d9bb 2201 #define PWR_CR_PLS_LEV1 ((uint32_t)0x00000020U) /*!< PVD level 1 */
Kojto 119:aae6fcc7d9bb 2202 #define PWR_CR_PLS_LEV2 ((uint32_t)0x00000040U) /*!< PVD level 2 */
Kojto 119:aae6fcc7d9bb 2203 #define PWR_CR_PLS_LEV3 ((uint32_t)0x00000060U) /*!< PVD level 3 */
Kojto 119:aae6fcc7d9bb 2204 #define PWR_CR_PLS_LEV4 ((uint32_t)0x00000080U) /*!< PVD level 4 */
Kojto 119:aae6fcc7d9bb 2205 #define PWR_CR_PLS_LEV5 ((uint32_t)0x000000A0U) /*!< PVD level 5 */
Kojto 119:aae6fcc7d9bb 2206 #define PWR_CR_PLS_LEV6 ((uint32_t)0x000000C0U) /*!< PVD level 6 */
Kojto 119:aae6fcc7d9bb 2207 #define PWR_CR_PLS_LEV7 ((uint32_t)0x000000E0U) /*!< PVD level 7 */
Kojto 119:aae6fcc7d9bb 2208
Kojto 119:aae6fcc7d9bb 2209 #define PWR_CR_DBP ((uint32_t)0x00000100U) /*!< Disable Backup Domain write protection */
Kojto 119:aae6fcc7d9bb 2210 #define PWR_CR_ULP ((uint32_t)0x00000200U) /*!< Ultra Low Power mode */
Kojto 119:aae6fcc7d9bb 2211 #define PWR_CR_FWU ((uint32_t)0x00000400U) /*!< Fast wakeup */
Kojto 119:aae6fcc7d9bb 2212
Kojto 119:aae6fcc7d9bb 2213 #define PWR_CR_VOS ((uint32_t)0x00001800U) /*!< VOS[1:0] bits (Voltage scaling range selection) */
Kojto 119:aae6fcc7d9bb 2214 #define PWR_CR_VOS_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2215 #define PWR_CR_VOS_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2216 #define PWR_CR_DSEEKOFF ((uint32_t)0x00002000U) /*!< Deep Sleep mode with EEPROM kept Off */
Kojto 119:aae6fcc7d9bb 2217 #define PWR_CR_LPRUN ((uint32_t)0x00004000U) /*!< Low power run mode */
Kojto 99:dbbf35b96557 2218
Kojto 99:dbbf35b96557 2219 /******************* Bit definition for PWR_CSR register ********************/
Kojto 119:aae6fcc7d9bb 2220 #define PWR_CSR_WUF ((uint32_t)0x00000001U) /*!< Wakeup Flag */
Kojto 119:aae6fcc7d9bb 2221 #define PWR_CSR_SBF ((uint32_t)0x00000002U) /*!< Standby Flag */
Kojto 119:aae6fcc7d9bb 2222 #define PWR_CSR_PVDO ((uint32_t)0x00000004U) /*!< PVD Output */
Kojto 119:aae6fcc7d9bb 2223 #define PWR_CSR_VREFINTRDYF ((uint32_t)0x00000008U) /*!< Internal voltage reference (VREFINT) ready flag */
Kojto 119:aae6fcc7d9bb 2224 #define PWR_CSR_VOSF ((uint32_t)0x00000010U) /*!< Voltage Scaling select flag */
Kojto 119:aae6fcc7d9bb 2225 #define PWR_CSR_REGLPF ((uint32_t)0x00000020U) /*!< Regulator LP flag */
Kojto 119:aae6fcc7d9bb 2226
Kojto 119:aae6fcc7d9bb 2227 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100U) /*!< Enable WKUP pin 1 */
Kojto 119:aae6fcc7d9bb 2228 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200U) /*!< Enable WKUP pin 2 */
Kojto 99:dbbf35b96557 2229
Kojto 99:dbbf35b96557 2230 /******************************************************************************/
Kojto 99:dbbf35b96557 2231 /* */
Kojto 99:dbbf35b96557 2232 /* Reset and Clock Control */
Kojto 99:dbbf35b96557 2233 /* */
Kojto 99:dbbf35b96557 2234 /******************************************************************************/
Kojto 99:dbbf35b96557 2235
Kojto 99:dbbf35b96557 2236 /******************** Bit definition for RCC_CR register ********************/
Kojto 119:aae6fcc7d9bb 2237 #define RCC_CR_HSION ((uint32_t)0x00000001U) /*!< Internal High Speed clock enable */
Kojto 119:aae6fcc7d9bb 2238 #define RCC_CR_HSIKERON ((uint32_t)0x00000002U) /*!< Internal High Speed clock enable for some IPs Kernel */
Kojto 119:aae6fcc7d9bb 2239 #define RCC_CR_HSIRDY ((uint32_t)0x00000004U) /*!< Internal High Speed clock ready flag */
Kojto 119:aae6fcc7d9bb 2240 #define RCC_CR_HSIDIVEN ((uint32_t)0x00000008U) /*!< Internal High Speed clock divider enable */
Kojto 119:aae6fcc7d9bb 2241 #define RCC_CR_HSIDIVF ((uint32_t)0x00000010U) /*!< Internal High Speed clock divider flag */
Kojto 119:aae6fcc7d9bb 2242 #define RCC_CR_MSION ((uint32_t)0x00000100U) /*!< Internal Multi Speed clock enable */
Kojto 119:aae6fcc7d9bb 2243 #define RCC_CR_MSIRDY ((uint32_t)0x00000200U) /*!< Internal Multi Speed clock ready flag */
Kojto 119:aae6fcc7d9bb 2244 #define RCC_CR_HSEON ((uint32_t)0x00010000U) /*!< External High Speed clock enable */
Kojto 119:aae6fcc7d9bb 2245 #define RCC_CR_HSERDY ((uint32_t)0x00020000U) /*!< External High Speed clock ready flag */
Kojto 119:aae6fcc7d9bb 2246 #define RCC_CR_HSEBYP ((uint32_t)0x00040000U) /*!< External High Speed clock Bypass */
Kojto 119:aae6fcc7d9bb 2247 #define RCC_CR_CSSHSEON ((uint32_t)0x00080000U) /*!< HSE Clock Security System enable */
Kojto 119:aae6fcc7d9bb 2248 #define RCC_CR_RTCPRE ((uint32_t)0x00300000U) /*!< RTC/LCD prescaler [1:0] bits */
Kojto 119:aae6fcc7d9bb 2249 #define RCC_CR_RTCPRE_0 ((uint32_t)0x00100000U) /*!< RTC/LCD prescaler Bit 0 */
Kojto 119:aae6fcc7d9bb 2250 #define RCC_CR_RTCPRE_1 ((uint32_t)0x00200000U) /*!< RTC/LCD prescaler Bit 1 */
Kojto 119:aae6fcc7d9bb 2251 #define RCC_CR_PLLON ((uint32_t)0x01000000U) /*!< PLL enable */
Kojto 119:aae6fcc7d9bb 2252 #define RCC_CR_PLLRDY ((uint32_t)0x02000000U) /*!< PLL clock ready flag */
Kojto 119:aae6fcc7d9bb 2253
Kojto 119:aae6fcc7d9bb 2254 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2255 #define RCC_CR_CSSON RCC_CR_CSSHSEON
Kojto 99:dbbf35b96557 2256
Kojto 99:dbbf35b96557 2257 /******************** Bit definition for RCC_ICSCR register *****************/
Kojto 119:aae6fcc7d9bb 2258 #define RCC_ICSCR_HSICAL ((uint32_t)0x000000FFU) /*!< Internal High Speed clock Calibration */
Kojto 119:aae6fcc7d9bb 2259 #define RCC_ICSCR_HSITRIM ((uint32_t)0x00001F00U) /*!< Internal High Speed clock trimming */
Kojto 119:aae6fcc7d9bb 2260
Kojto 119:aae6fcc7d9bb 2261 #define RCC_ICSCR_MSIRANGE ((uint32_t)0x0000E000U) /*!< Internal Multi Speed clock Range */
Kojto 119:aae6fcc7d9bb 2262 #define RCC_ICSCR_MSIRANGE_0 ((uint32_t)0x00000000U) /*!< Internal Multi Speed clock Range 65.536 KHz */
Kojto 119:aae6fcc7d9bb 2263 #define RCC_ICSCR_MSIRANGE_1 ((uint32_t)0x00002000U) /*!< Internal Multi Speed clock Range 131.072 KHz */
Kojto 119:aae6fcc7d9bb 2264 #define RCC_ICSCR_MSIRANGE_2 ((uint32_t)0x00004000U) /*!< Internal Multi Speed clock Range 262.144 KHz */
Kojto 119:aae6fcc7d9bb 2265 #define RCC_ICSCR_MSIRANGE_3 ((uint32_t)0x00006000U) /*!< Internal Multi Speed clock Range 524.288 KHz */
Kojto 119:aae6fcc7d9bb 2266 #define RCC_ICSCR_MSIRANGE_4 ((uint32_t)0x00008000U) /*!< Internal Multi Speed clock Range 1.048 MHz */
Kojto 119:aae6fcc7d9bb 2267 #define RCC_ICSCR_MSIRANGE_5 ((uint32_t)0x0000A000U) /*!< Internal Multi Speed clock Range 2.097 MHz */
Kojto 119:aae6fcc7d9bb 2268 #define RCC_ICSCR_MSIRANGE_6 ((uint32_t)0x0000C000U) /*!< Internal Multi Speed clock Range 4.194 MHz */
Kojto 119:aae6fcc7d9bb 2269 #define RCC_ICSCR_MSICAL ((uint32_t)0x00FF0000U) /*!< Internal Multi Speed clock Calibration */
Kojto 119:aae6fcc7d9bb 2270 #define RCC_ICSCR_MSITRIM ((uint32_t)0xFF000000U) /*!< Internal Multi Speed clock trimming */
Kojto 99:dbbf35b96557 2271
Kojto 99:dbbf35b96557 2272 /******************** Bit definition for RCC_CRRCR register *****************/
Kojto 119:aae6fcc7d9bb 2273 #define RCC_CRRCR_HSI48ON ((uint32_t)0x00000001U) /*!< HSI 48MHz clock enable */
Kojto 119:aae6fcc7d9bb 2274 #define RCC_CRRCR_HSI48RDY ((uint32_t)0x00000002U) /*!< HSI 48MHz clock ready flag */
Kojto 119:aae6fcc7d9bb 2275 #define RCC_CRRCR_HSI48CAL ((uint32_t)0x0000FF00U) /*!< HSI 48MHz clock Calibration */
Kojto 99:dbbf35b96557 2276
Kojto 99:dbbf35b96557 2277 /******************* Bit definition for RCC_CFGR register *******************/
Kojto 99:dbbf35b96557 2278 /*!< SW configuration */
Kojto 119:aae6fcc7d9bb 2279 #define RCC_CFGR_SW ((uint32_t)0x00000003U) /*!< SW[1:0] bits (System clock Switch) */
Kojto 119:aae6fcc7d9bb 2280 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2281 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2282
Kojto 119:aae6fcc7d9bb 2283 #define RCC_CFGR_SW_MSI ((uint32_t)0x00000000U) /*!< MSI selected as system clock */
Kojto 119:aae6fcc7d9bb 2284 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000001U) /*!< HSI selected as system clock */
Kojto 119:aae6fcc7d9bb 2285 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000002U) /*!< HSE selected as system clock */
Kojto 119:aae6fcc7d9bb 2286 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000003U) /*!< PLL selected as system clock */
Kojto 99:dbbf35b96557 2287
Kojto 99:dbbf35b96557 2288 /*!< SWS configuration */
Kojto 119:aae6fcc7d9bb 2289 #define RCC_CFGR_SWS ((uint32_t)0x0000000CU) /*!< SWS[1:0] bits (System Clock Switch Status) */
Kojto 119:aae6fcc7d9bb 2290 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2291 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2292
Kojto 119:aae6fcc7d9bb 2293 #define RCC_CFGR_SWS_MSI ((uint32_t)0x00000000U) /*!< MSI oscillator used as system clock */
Kojto 119:aae6fcc7d9bb 2294 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000004U) /*!< HSI oscillator used as system clock */
Kojto 119:aae6fcc7d9bb 2295 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000008U) /*!< HSE oscillator used as system clock */
Kojto 119:aae6fcc7d9bb 2296 #define RCC_CFGR_SWS_PLL ((uint32_t)0x0000000CU) /*!< PLL used as system clock */
Kojto 99:dbbf35b96557 2297
Kojto 99:dbbf35b96557 2298 /*!< HPRE configuration */
Kojto 119:aae6fcc7d9bb 2299 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0U) /*!< HPRE[3:0] bits (AHB prescaler) */
Kojto 119:aae6fcc7d9bb 2300 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2301 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2302 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2303 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 2304
Kojto 119:aae6fcc7d9bb 2305 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000U) /*!< SYSCLK not divided */
Kojto 119:aae6fcc7d9bb 2306 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080U) /*!< SYSCLK divided by 2 */
Kojto 119:aae6fcc7d9bb 2307 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090U) /*!< SYSCLK divided by 4 */
Kojto 119:aae6fcc7d9bb 2308 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0U) /*!< SYSCLK divided by 8 */
Kojto 119:aae6fcc7d9bb 2309 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0U) /*!< SYSCLK divided by 16 */
Kojto 119:aae6fcc7d9bb 2310 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0U) /*!< SYSCLK divided by 64 */
Kojto 119:aae6fcc7d9bb 2311 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0U) /*!< SYSCLK divided by 128 */
Kojto 119:aae6fcc7d9bb 2312 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0U) /*!< SYSCLK divided by 256 */
Kojto 119:aae6fcc7d9bb 2313 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0U) /*!< SYSCLK divided by 512 */
Kojto 99:dbbf35b96557 2314
Kojto 99:dbbf35b96557 2315 /*!< PPRE1 configuration */
Kojto 119:aae6fcc7d9bb 2316 #define RCC_CFGR_PPRE1 ((uint32_t)0x00000700U) /*!< PRE1[2:0] bits (APB1 prescaler) */
Kojto 119:aae6fcc7d9bb 2317 #define RCC_CFGR_PPRE1_0 ((uint32_t)0x00000100U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2318 #define RCC_CFGR_PPRE1_1 ((uint32_t)0x00000200U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2319 #define RCC_CFGR_PPRE1_2 ((uint32_t)0x00000400U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2320
Kojto 119:aae6fcc7d9bb 2321 #define RCC_CFGR_PPRE1_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
Kojto 119:aae6fcc7d9bb 2322 #define RCC_CFGR_PPRE1_DIV2 ((uint32_t)0x00000400U) /*!< HCLK divided by 2 */
Kojto 119:aae6fcc7d9bb 2323 #define RCC_CFGR_PPRE1_DIV4 ((uint32_t)0x00000500U) /*!< HCLK divided by 4 */
Kojto 119:aae6fcc7d9bb 2324 #define RCC_CFGR_PPRE1_DIV8 ((uint32_t)0x00000600U) /*!< HCLK divided by 8 */
Kojto 119:aae6fcc7d9bb 2325 #define RCC_CFGR_PPRE1_DIV16 ((uint32_t)0x00000700U) /*!< HCLK divided by 16 */
Kojto 99:dbbf35b96557 2326
Kojto 99:dbbf35b96557 2327 /*!< PPRE2 configuration */
Kojto 119:aae6fcc7d9bb 2328 #define RCC_CFGR_PPRE2 ((uint32_t)0x00003800U) /*!< PRE2[2:0] bits (APB2 prescaler) */
Kojto 119:aae6fcc7d9bb 2329 #define RCC_CFGR_PPRE2_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2330 #define RCC_CFGR_PPRE2_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2331 #define RCC_CFGR_PPRE2_2 ((uint32_t)0x00002000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2332
Kojto 119:aae6fcc7d9bb 2333 #define RCC_CFGR_PPRE2_DIV1 ((uint32_t)0x00000000U) /*!< HCLK not divided */
Kojto 119:aae6fcc7d9bb 2334 #define RCC_CFGR_PPRE2_DIV2 ((uint32_t)0x00002000U) /*!< HCLK divided by 2 */
Kojto 119:aae6fcc7d9bb 2335 #define RCC_CFGR_PPRE2_DIV4 ((uint32_t)0x00002800U) /*!< HCLK divided by 4 */
Kojto 119:aae6fcc7d9bb 2336 #define RCC_CFGR_PPRE2_DIV8 ((uint32_t)0x00003000U) /*!< HCLK divided by 8 */
Kojto 119:aae6fcc7d9bb 2337 #define RCC_CFGR_PPRE2_DIV16 ((uint32_t)0x00003800U) /*!< HCLK divided by 16 */
Kojto 119:aae6fcc7d9bb 2338
Kojto 119:aae6fcc7d9bb 2339 #define RCC_CFGR_STOPWUCK ((uint32_t)0x00008000U) /*!< Wake Up from Stop Clock selection */
Kojto 99:dbbf35b96557 2340
Kojto 99:dbbf35b96557 2341 /*!< PLL entry clock source*/
Kojto 119:aae6fcc7d9bb 2342 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000U) /*!< PLL entry clock source */
Kojto 119:aae6fcc7d9bb 2343
Kojto 119:aae6fcc7d9bb 2344 #define RCC_CFGR_PLLSRC_HSI ((uint32_t)0x00000000U) /*!< HSI as PLL entry clock source */
Kojto 119:aae6fcc7d9bb 2345 #define RCC_CFGR_PLLSRC_HSE ((uint32_t)0x00010000U) /*!< HSE as PLL entry clock source */
Kojto 99:dbbf35b96557 2346
Kojto 99:dbbf35b96557 2347
Kojto 99:dbbf35b96557 2348 /*!< PLLMUL configuration */
Kojto 119:aae6fcc7d9bb 2349 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000U) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
Kojto 119:aae6fcc7d9bb 2350 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2351 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2352 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2353 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 2354
Kojto 119:aae6fcc7d9bb 2355 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00000000U) /*!< PLL input clock * 3 */
Kojto 119:aae6fcc7d9bb 2356 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00040000U) /*!< PLL input clock * 4 */
Kojto 119:aae6fcc7d9bb 2357 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00080000U) /*!< PLL input clock * 6 */
Kojto 119:aae6fcc7d9bb 2358 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x000C0000U) /*!< PLL input clock * 8 */
Kojto 119:aae6fcc7d9bb 2359 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00100000U) /*!< PLL input clock * 12 */
Kojto 119:aae6fcc7d9bb 2360 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00140000U) /*!< PLL input clock * 16 */
Kojto 119:aae6fcc7d9bb 2361 #define RCC_CFGR_PLLMUL24 ((uint32_t)0x00180000U) /*!< PLL input clock * 24 */
Kojto 119:aae6fcc7d9bb 2362 #define RCC_CFGR_PLLMUL32 ((uint32_t)0x001C0000U) /*!< PLL input clock * 32 */
Kojto 119:aae6fcc7d9bb 2363 #define RCC_CFGR_PLLMUL48 ((uint32_t)0x00200000U) /*!< PLL input clock * 48 */
Kojto 99:dbbf35b96557 2364
Kojto 99:dbbf35b96557 2365 /*!< PLLDIV configuration */
Kojto 119:aae6fcc7d9bb 2366 #define RCC_CFGR_PLLDIV ((uint32_t)0x00C00000U) /*!< PLLDIV[1:0] bits (PLL Output Division) */
Kojto 119:aae6fcc7d9bb 2367 #define RCC_CFGR_PLLDIV_0 ((uint32_t)0x00400000U) /*!< Bit0 */
Kojto 119:aae6fcc7d9bb 2368 #define RCC_CFGR_PLLDIV_1 ((uint32_t)0x00800000U) /*!< Bit1 */
Kojto 119:aae6fcc7d9bb 2369
Kojto 119:aae6fcc7d9bb 2370 #define RCC_CFGR_PLLDIV2 ((uint32_t)0x00400000U) /*!< PLL clock output = CKVCO / 2 */
Kojto 119:aae6fcc7d9bb 2371 #define RCC_CFGR_PLLDIV3 ((uint32_t)0x00800000U) /*!< PLL clock output = CKVCO / 3 */
Kojto 119:aae6fcc7d9bb 2372 #define RCC_CFGR_PLLDIV4 ((uint32_t)0x00C00000U) /*!< PLL clock output = CKVCO / 4 */
Kojto 99:dbbf35b96557 2373
Kojto 99:dbbf35b96557 2374 /*!< MCO configuration */
Kojto 119:aae6fcc7d9bb 2375 #define RCC_CFGR_MCOSEL ((uint32_t)0x0F000000U) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
Kojto 119:aae6fcc7d9bb 2376 #define RCC_CFGR_MCOSEL_0 ((uint32_t)0x01000000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2377 #define RCC_CFGR_MCOSEL_1 ((uint32_t)0x02000000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 2378 #define RCC_CFGR_MCOSEL_2 ((uint32_t)0x04000000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 2379 #define RCC_CFGR_MCOSEL_3 ((uint32_t)0x08000000U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 2380
Kojto 119:aae6fcc7d9bb 2381 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
Kojto 119:aae6fcc7d9bb 2382 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x01000000U) /*!< System clock selected as MCO source */
Kojto 119:aae6fcc7d9bb 2383 #define RCC_CFGR_MCO_HSI ((uint32_t)0x02000000U) /*!< Internal 16 MHz RC oscillator clock selected */
Kojto 119:aae6fcc7d9bb 2384 #define RCC_CFGR_MCO_MSI ((uint32_t)0x03000000U) /*!< Internal Medium Speed RC oscillator clock selected */
Kojto 119:aae6fcc7d9bb 2385 #define RCC_CFGR_MCO_HSE ((uint32_t)0x04000000U) /*!< External 1-25 MHz oscillator clock selected */
Kojto 119:aae6fcc7d9bb 2386 #define RCC_CFGR_MCO_PLL ((uint32_t)0x05000000U) /*!< PLL clock divided */
Kojto 119:aae6fcc7d9bb 2387 #define RCC_CFGR_MCO_LSI ((uint32_t)0x06000000U) /*!< LSI selected */
Kojto 119:aae6fcc7d9bb 2388 #define RCC_CFGR_MCO_LSE ((uint32_t)0x07000000U) /*!< LSE selected */
Kojto 119:aae6fcc7d9bb 2389 #define RCC_CFGR_MCO_HSI48 ((uint32_t)0x08000000U) /*!< HSI48 clock selected as MCO source */
Kojto 119:aae6fcc7d9bb 2390
Kojto 119:aae6fcc7d9bb 2391 #define RCC_CFGR_MCOPRE ((uint32_t)0x70000000U) /*!< MCO prescaler */
Kojto 119:aae6fcc7d9bb 2392 #define RCC_CFGR_MCOPRE_0 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
Kojto 119:aae6fcc7d9bb 2393 #define RCC_CFGR_MCOPRE_1 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
Kojto 119:aae6fcc7d9bb 2394 #define RCC_CFGR_MCOPRE_2 ((uint32_t)0x40000000U) /*!< MCO is divided by 8 */
Kojto 119:aae6fcc7d9bb 2395
Kojto 119:aae6fcc7d9bb 2396 #define RCC_CFGR_MCOPRE_DIV1 ((uint32_t)0x00000000U) /*!< MCO is divided by 1 */
Kojto 119:aae6fcc7d9bb 2397 #define RCC_CFGR_MCOPRE_DIV2 ((uint32_t)0x10000000U) /*!< MCO is divided by 2 */
Kojto 119:aae6fcc7d9bb 2398 #define RCC_CFGR_MCOPRE_DIV4 ((uint32_t)0x20000000U) /*!< MCO is divided by 4 */
Kojto 119:aae6fcc7d9bb 2399 #define RCC_CFGR_MCOPRE_DIV8 ((uint32_t)0x30000000U) /*!< MCO is divided by 8 */
Kojto 119:aae6fcc7d9bb 2400 #define RCC_CFGR_MCOPRE_DIV16 ((uint32_t)0x40000000U) /*!< MCO is divided by 16 */
Kojto 119:aae6fcc7d9bb 2401
Kojto 119:aae6fcc7d9bb 2402 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 2403 #define RCC_CFGR_MCO_PRE RCC_CFGR_MCOPRE /*!< MCO prescaler */
Kojto 119:aae6fcc7d9bb 2404 #define RCC_CFGR_MCO_PRE_1 RCC_CFGR_MCOPRE_DIV1 /*!< MCO is divided by 1 */
Kojto 119:aae6fcc7d9bb 2405 #define RCC_CFGR_MCO_PRE_2 RCC_CFGR_MCOPRE_DIV2 /*!< MCO is divided by 1 */
Kojto 119:aae6fcc7d9bb 2406 #define RCC_CFGR_MCO_PRE_4 RCC_CFGR_MCOPRE_DIV4 /*!< MCO is divided by 1 */
Kojto 119:aae6fcc7d9bb 2407 #define RCC_CFGR_MCO_PRE_8 RCC_CFGR_MCOPRE_DIV8 /*!< MCO is divided by 1 */
Kojto 119:aae6fcc7d9bb 2408 #define RCC_CFGR_MCO_PRE_16 RCC_CFGR_MCOPRE_DIV16 /*!< MCO is divided by 1 */
Kojto 99:dbbf35b96557 2409
Kojto 99:dbbf35b96557 2410 /*!<****************** Bit definition for RCC_CIER register ********************/
Kojto 119:aae6fcc7d9bb 2411 #define RCC_CIER_LSIRDYIE ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2412 #define RCC_CIER_LSERDYIE ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2413 #define RCC_CIER_HSIRDYIE ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2414 #define RCC_CIER_HSERDYIE ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2415 #define RCC_CIER_PLLRDYIE ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2416 #define RCC_CIER_MSIRDYIE ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2417 #define RCC_CIER_HSI48RDYIE ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2418 #define RCC_CIER_CSSLSE ((uint32_t)0x00000080U) /*!< LSE CSS Interrupt Enable */
Kojto 119:aae6fcc7d9bb 2419
Kojto 119:aae6fcc7d9bb 2420 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2421 #define RCC_CIER_LSECSSIE RCC_CIER_CSSLSE
Kojto 99:dbbf35b96557 2422
Kojto 99:dbbf35b96557 2423 /*!<****************** Bit definition for RCC_CIFR register ********************/
Kojto 119:aae6fcc7d9bb 2424 #define RCC_CIFR_LSIRDYF ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt flag */
Kojto 119:aae6fcc7d9bb 2425 #define RCC_CIFR_LSERDYF ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt flag */
Kojto 119:aae6fcc7d9bb 2426 #define RCC_CIFR_HSIRDYF ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt flag */
Kojto 119:aae6fcc7d9bb 2427 #define RCC_CIFR_HSERDYF ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt flag */
Kojto 119:aae6fcc7d9bb 2428 #define RCC_CIFR_PLLRDYF ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt flag */
Kojto 119:aae6fcc7d9bb 2429 #define RCC_CIFR_MSIRDYF ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt flag */
Kojto 119:aae6fcc7d9bb 2430 #define RCC_CIFR_HSI48RDYF ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt flag */
Kojto 119:aae6fcc7d9bb 2431 #define RCC_CIFR_CSSLSEF ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt flag */
Kojto 119:aae6fcc7d9bb 2432 #define RCC_CIFR_CSSHSEF ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt flag */
Kojto 119:aae6fcc7d9bb 2433
Kojto 119:aae6fcc7d9bb 2434 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2435 #define RCC_CIFR_LSECSSF RCC_CIFR_CSSLSEF
Kojto 119:aae6fcc7d9bb 2436 #define RCC_CIFR_CSSF RCC_CIFR_CSSHSEF
Kojto 99:dbbf35b96557 2437
Kojto 99:dbbf35b96557 2438 /*!<****************** Bit definition for RCC_CICR register ********************/
Kojto 119:aae6fcc7d9bb 2439 #define RCC_CICR_LSIRDYC ((uint32_t)0x00000001U) /*!< LSI Ready Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2440 #define RCC_CICR_LSERDYC ((uint32_t)0x00000002U) /*!< LSE Ready Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2441 #define RCC_CICR_HSIRDYC ((uint32_t)0x00000004U) /*!< HSI Ready Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2442 #define RCC_CICR_HSERDYC ((uint32_t)0x00000008U) /*!< HSE Ready Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2443 #define RCC_CICR_PLLRDYC ((uint32_t)0x00000010U) /*!< PLL Ready Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2444 #define RCC_CICR_MSIRDYC ((uint32_t)0x00000020U) /*!< MSI Ready Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2445 #define RCC_CICR_HSI48RDYC ((uint32_t)0x00000040U) /*!< HSI48 Ready Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2446 #define RCC_CICR_CSSLSEC ((uint32_t)0x00000080U) /*!< LSE Clock Security System Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2447 #define RCC_CICR_CSSHSEC ((uint32_t)0x00000100U) /*!< HSE Clock Security System Interrupt Clear */
Kojto 119:aae6fcc7d9bb 2448
Kojto 119:aae6fcc7d9bb 2449 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2450 #define RCC_CICR_LSECSSC RCC_CICR_CSSLSEC
Kojto 119:aae6fcc7d9bb 2451 #define RCC_CICR_CSSC RCC_CICR_CSSHSEC
Kojto 99:dbbf35b96557 2452 /***************** Bit definition for RCC_IOPRSTR register ******************/
Kojto 119:aae6fcc7d9bb 2453 #define RCC_IOPRSTR_IOPARST ((uint32_t)0x00000001U) /*!< GPIO port A reset */
Kojto 119:aae6fcc7d9bb 2454 #define RCC_IOPRSTR_IOPBRST ((uint32_t)0x00000002U) /*!< GPIO port B reset */
Kojto 119:aae6fcc7d9bb 2455 #define RCC_IOPRSTR_IOPCRST ((uint32_t)0x00000004U) /*!< GPIO port C reset */
Kojto 119:aae6fcc7d9bb 2456 #define RCC_IOPRSTR_IOPDRST ((uint32_t)0x00000008U) /*!< GPIO port D reset */
Kojto 119:aae6fcc7d9bb 2457 #define RCC_IOPRSTR_IOPHRST ((uint32_t)0x00000080U) /*!< GPIO port H reset */
Kojto 119:aae6fcc7d9bb 2458
Kojto 119:aae6fcc7d9bb 2459 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2460 #define RCC_IOPRSTR_GPIOARST RCC_IOPRSTR_IOPARST /*!< GPIO port A reset */
Kojto 119:aae6fcc7d9bb 2461 #define RCC_IOPRSTR_GPIOBRST RCC_IOPRSTR_IOPBRST /*!< GPIO port B reset */
Kojto 119:aae6fcc7d9bb 2462 #define RCC_IOPRSTR_GPIOCRST RCC_IOPRSTR_IOPCRST /*!< GPIO port C reset */
Kojto 119:aae6fcc7d9bb 2463 #define RCC_IOPRSTR_GPIODRST RCC_IOPRSTR_IOPDRST /*!< GPIO port D reset */
Kojto 119:aae6fcc7d9bb 2464 #define RCC_IOPRSTR_GPIOHRST RCC_IOPRSTR_IOPHRST /*!< GPIO port H reset */
Kojto 119:aae6fcc7d9bb 2465
Kojto 99:dbbf35b96557 2466
Kojto 99:dbbf35b96557 2467 /****************** Bit definition for RCC_AHBRST register ******************/
Kojto 119:aae6fcc7d9bb 2468 #define RCC_AHBRSTR_DMARST ((uint32_t)0x00000001U) /*!< DMA1 reset */
Kojto 119:aae6fcc7d9bb 2469 #define RCC_AHBRSTR_MIFRST ((uint32_t)0x00000100U) /*!< Memory interface reset reset */
Kojto 119:aae6fcc7d9bb 2470 #define RCC_AHBRSTR_CRCRST ((uint32_t)0x00001000U) /*!< CRC reset */
Kojto 119:aae6fcc7d9bb 2471 #define RCC_AHBRSTR_TSCRST ((uint32_t)0x00010000U) /*!< TSC reset */
Kojto 119:aae6fcc7d9bb 2472 #define RCC_AHBRSTR_RNGRST ((uint32_t)0x00100000U) /*!< RNG reset */
Kojto 119:aae6fcc7d9bb 2473
Kojto 119:aae6fcc7d9bb 2474 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2475 #define RCC_AHBRSTR_DMA1RST RCC_AHBRSTR_DMARST /*!< DMA1 reset */
Kojto 99:dbbf35b96557 2476
Kojto 99:dbbf35b96557 2477 /***************** Bit definition for RCC_APB2RSTR register *****************/
Kojto 119:aae6fcc7d9bb 2478 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001U) /*!< SYSCFG clock reset */
Kojto 119:aae6fcc7d9bb 2479 #define RCC_APB2RSTR_TIM21RST ((uint32_t)0x00000004U) /*!< TIM21 clock reset */
Kojto 119:aae6fcc7d9bb 2480 #define RCC_APB2RSTR_TIM22RST ((uint32_t)0x00000020U) /*!< TIM22 clock reset */
Kojto 119:aae6fcc7d9bb 2481 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200U) /*!< ADC1 clock reset */
Kojto 119:aae6fcc7d9bb 2482 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000U) /*!< SPI1 clock reset */
Kojto 119:aae6fcc7d9bb 2483 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000U) /*!< USART1 clock reset */
Kojto 119:aae6fcc7d9bb 2484 #define RCC_APB2RSTR_DBGRST ((uint32_t)0x00400000U) /*!< DBGMCU clock reset */
Kojto 119:aae6fcc7d9bb 2485
Kojto 119:aae6fcc7d9bb 2486 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2487 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST /*!< ADC1 clock reset */
Kojto 119:aae6fcc7d9bb 2488 #define RCC_APB2RSTR_DBGMCURST RCC_APB2RSTR_DBGRST /*!< DBGMCU clock reset */
Kojto 99:dbbf35b96557 2489
Kojto 99:dbbf35b96557 2490 /***************** Bit definition for RCC_APB1RSTR register *****************/
Kojto 119:aae6fcc7d9bb 2491 #define RCC_APB1RSTR_TIM2RST ((uint32_t)0x00000001U) /*!< Timer 2 clock reset */
Kojto 119:aae6fcc7d9bb 2492 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010U) /*!< Timer 6 clock reset */
Kojto 119:aae6fcc7d9bb 2493 #define RCC_APB1RSTR_LCDRST ((uint32_t)0x00000200U) /*!< LCD clock reset */
Kojto 119:aae6fcc7d9bb 2494 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800U) /*!< Window Watchdog clock reset */
Kojto 119:aae6fcc7d9bb 2495 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000U) /*!< SPI2 clock reset */
Kojto 119:aae6fcc7d9bb 2496 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000U) /*!< USART 2 clock reset */
Kojto 119:aae6fcc7d9bb 2497 #define RCC_APB1RSTR_LPUART1RST ((uint32_t)0x00040000U) /*!< LPUART1 clock reset */
Kojto 119:aae6fcc7d9bb 2498 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000U) /*!< I2C 1 clock reset */
Kojto 119:aae6fcc7d9bb 2499 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000U) /*!< I2C 2 clock reset */
Kojto 119:aae6fcc7d9bb 2500 #define RCC_APB1RSTR_USBRST ((uint32_t)0x00800000U) /*!< USB clock reset */
Kojto 119:aae6fcc7d9bb 2501 #define RCC_APB1RSTR_CRSRST ((uint32_t)0x08000000U) /*!< CRS clock reset */
Kojto 119:aae6fcc7d9bb 2502 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000U) /*!< PWR clock reset */
Kojto 119:aae6fcc7d9bb 2503 #define RCC_APB1RSTR_DACRST ((uint32_t)0x20000000U) /*!< DAC clock reset */
Kojto 119:aae6fcc7d9bb 2504 #define RCC_APB1RSTR_LPTIM1RST ((uint32_t)0x80000000U) /*!< LPTIM1 clock reset */
Kojto 99:dbbf35b96557 2505
Kojto 99:dbbf35b96557 2506 /***************** Bit definition for RCC_IOPENR register ******************/
Kojto 119:aae6fcc7d9bb 2507 #define RCC_IOPENR_IOPAEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enable */
Kojto 119:aae6fcc7d9bb 2508 #define RCC_IOPENR_IOPBEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enable */
Kojto 119:aae6fcc7d9bb 2509 #define RCC_IOPENR_IOPCEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enable */
Kojto 119:aae6fcc7d9bb 2510 #define RCC_IOPENR_IOPDEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enable */
Kojto 119:aae6fcc7d9bb 2511 #define RCC_IOPENR_IOPHEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enable */
Kojto 119:aae6fcc7d9bb 2512
Kojto 119:aae6fcc7d9bb 2513 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2514 #define RCC_IOPENR_GPIOAEN RCC_IOPENR_IOPAEN /*!< GPIO port A clock enable */
Kojto 119:aae6fcc7d9bb 2515 #define RCC_IOPENR_GPIOBEN RCC_IOPENR_IOPBEN /*!< GPIO port B clock enable */
Kojto 119:aae6fcc7d9bb 2516 #define RCC_IOPENR_GPIOCEN RCC_IOPENR_IOPCEN /*!< GPIO port C clock enable */
Kojto 119:aae6fcc7d9bb 2517 #define RCC_IOPENR_GPIODEN RCC_IOPENR_IOPDEN /*!< GPIO port D clock enable */
Kojto 119:aae6fcc7d9bb 2518 #define RCC_IOPENR_GPIOHEN RCC_IOPENR_IOPHEN /*!< GPIO port H clock enable */
Kojto 99:dbbf35b96557 2519
Kojto 99:dbbf35b96557 2520 /***************** Bit definition for RCC_AHBENR register ******************/
Kojto 119:aae6fcc7d9bb 2521 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001U) /*!< DMA1 clock enable */
Kojto 119:aae6fcc7d9bb 2522 #define RCC_AHBENR_MIFEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable bit */
Kojto 119:aae6fcc7d9bb 2523 #define RCC_AHBENR_CRCEN ((uint32_t)0x00001000U) /*!< CRC clock enable */
Kojto 119:aae6fcc7d9bb 2524 #define RCC_AHBENR_TSCEN ((uint32_t)0x00010000U) /*!< TSC clock enable */
Kojto 119:aae6fcc7d9bb 2525 #define RCC_AHBENR_RNGEN ((uint32_t)0x00100000U) /*!< RNG clock enable */
Kojto 119:aae6fcc7d9bb 2526
Kojto 119:aae6fcc7d9bb 2527 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2528 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
Kojto 99:dbbf35b96557 2529
Kojto 99:dbbf35b96557 2530 /***************** Bit definition for RCC_APB2ENR register ******************/
Kojto 119:aae6fcc7d9bb 2531 #define RCC_APB2ENR_SYSCFGEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enable */
Kojto 119:aae6fcc7d9bb 2532 #define RCC_APB2ENR_TIM21EN ((uint32_t)0x00000004U) /*!< TIM21 clock enable */
Kojto 119:aae6fcc7d9bb 2533 #define RCC_APB2ENR_TIM22EN ((uint32_t)0x00000020U) /*!< TIM22 clock enable */
Kojto 119:aae6fcc7d9bb 2534 #define RCC_APB2ENR_FWEN ((uint32_t)0x00000080U) /*!< MiFare Firewall clock enable */
Kojto 119:aae6fcc7d9bb 2535 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200U) /*!< ADC1 clock enable */
Kojto 119:aae6fcc7d9bb 2536 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000U) /*!< SPI1 clock enable */
Kojto 119:aae6fcc7d9bb 2537 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000U) /*!< USART1 clock enable */
Kojto 119:aae6fcc7d9bb 2538 #define RCC_APB2ENR_DBGEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enable */
Kojto 119:aae6fcc7d9bb 2539
Kojto 119:aae6fcc7d9bb 2540 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2541
Kojto 119:aae6fcc7d9bb 2542 #define RCC_APB2ENR_MIFIEN RCC_APB2ENR_FWEN /*!< MiFare Firewall clock enable */
Kojto 119:aae6fcc7d9bb 2543 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
Kojto 119:aae6fcc7d9bb 2544 #define RCC_APB2ENR_DBGMCUEN RCC_APB2ENR_DBGEN /*!< DBGMCU clock enable */
Kojto 99:dbbf35b96557 2545
Kojto 99:dbbf35b96557 2546 /***************** Bit definition for RCC_APB1ENR register ******************/
Kojto 119:aae6fcc7d9bb 2547 #define RCC_APB1ENR_TIM2EN ((uint32_t)0x00000001U) /*!< Timer 2 clock enable */
Kojto 119:aae6fcc7d9bb 2548 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010U) /*!< Timer 6 clock enable */
Kojto 119:aae6fcc7d9bb 2549 #define RCC_APB1ENR_LCDEN ((uint32_t)0x00000200U) /*!< LCD clock enable */
Kojto 119:aae6fcc7d9bb 2550 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enable */
Kojto 119:aae6fcc7d9bb 2551 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000U) /*!< SPI2 clock enable */
Kojto 119:aae6fcc7d9bb 2552 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000U) /*!< USART2 clock enable */
Kojto 119:aae6fcc7d9bb 2553 #define RCC_APB1ENR_LPUART1EN ((uint32_t)0x00040000U) /*!< LPUART1 clock enable */
Kojto 119:aae6fcc7d9bb 2554 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000U) /*!< I2C1 clock enable */
Kojto 119:aae6fcc7d9bb 2555 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000U) /*!< I2C2 clock enable */
Kojto 119:aae6fcc7d9bb 2556 #define RCC_APB1ENR_USBEN ((uint32_t)0x00800000U) /*!< USB clock enable */
Kojto 119:aae6fcc7d9bb 2557 #define RCC_APB1ENR_CRSEN ((uint32_t)0x08000000U) /*!< CRS clock enable */
Kojto 119:aae6fcc7d9bb 2558 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000U) /*!< PWR clock enable */
Kojto 119:aae6fcc7d9bb 2559 #define RCC_APB1ENR_DACEN ((uint32_t)0x20000000U) /*!< DAC clock enable */
Kojto 119:aae6fcc7d9bb 2560 #define RCC_APB1ENR_LPTIM1EN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enable */
Kojto 99:dbbf35b96557 2561
Kojto 99:dbbf35b96557 2562 /****************** Bit definition for RCC_IOPSMENR register ****************/
Kojto 119:aae6fcc7d9bb 2563 #define RCC_IOPSMENR_IOPASMEN ((uint32_t)0x00000001U) /*!< GPIO port A clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2564 #define RCC_IOPSMENR_IOPBSMEN ((uint32_t)0x00000002U) /*!< GPIO port B clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2565 #define RCC_IOPSMENR_IOPCSMEN ((uint32_t)0x00000004U) /*!< GPIO port C clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2566 #define RCC_IOPSMENR_IOPDSMEN ((uint32_t)0x00000008U) /*!< GPIO port D clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2567 #define RCC_IOPSMENR_IOPHSMEN ((uint32_t)0x00000080U) /*!< GPIO port H clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2568
Kojto 119:aae6fcc7d9bb 2569 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2570 #define RCC_IOPSMENR_GPIOASMEN RCC_IOPSMENR_IOPASMEN /*!< GPIO port A clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2571 #define RCC_IOPSMENR_GPIOBSMEN RCC_IOPSMENR_IOPBSMEN /*!< GPIO port B clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2572 #define RCC_IOPSMENR_GPIOCSMEN RCC_IOPSMENR_IOPCSMEN /*!< GPIO port C clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2573 #define RCC_IOPSMENR_GPIODSMEN RCC_IOPSMENR_IOPDSMEN /*!< GPIO port D clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2574 #define RCC_IOPSMENR_GPIOHSMEN RCC_IOPSMENR_IOPHSMEN /*!< GPIO port H clock enabled in sleep mode */
Kojto 99:dbbf35b96557 2575
Kojto 99:dbbf35b96557 2576 /***************** Bit definition for RCC_AHBSMENR register ******************/
Kojto 119:aae6fcc7d9bb 2577 #define RCC_AHBSMENR_DMASMEN ((uint32_t)0x00000001U) /*!< DMA1 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2578 #define RCC_AHBSMENR_MIFSMEN ((uint32_t)0x00000100U) /*!< NVM interface clock enable during sleep mode */
Kojto 119:aae6fcc7d9bb 2579 #define RCC_AHBSMENR_SRAMSMEN ((uint32_t)0x00000200U) /*!< SRAM clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2580 #define RCC_AHBSMENR_CRCSMEN ((uint32_t)0x00001000U) /*!< CRC clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2581 #define RCC_AHBSMENR_TSCSMEN ((uint32_t)0x00010000U) /*!< TSC clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2582 #define RCC_AHBSMENR_RNGSMEN ((uint32_t)0x00100000U) /*!< RNG clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2583
Kojto 119:aae6fcc7d9bb 2584 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2585 #define RCC_AHBSMENR_DMA1SMEN RCC_AHBSMENR_DMASMEN /*!< DMA1 clock enabled in sleep mode */
Kojto 99:dbbf35b96557 2586
Kojto 99:dbbf35b96557 2587 /***************** Bit definition for RCC_APB2SMENR register ******************/
Kojto 119:aae6fcc7d9bb 2588 #define RCC_APB2SMENR_SYSCFGSMEN ((uint32_t)0x00000001U) /*!< SYSCFG clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2589 #define RCC_APB2SMENR_TIM21SMEN ((uint32_t)0x00000004U) /*!< TIM21 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2590 #define RCC_APB2SMENR_TIM22SMEN ((uint32_t)0x00000020U) /*!< TIM22 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2591 #define RCC_APB2SMENR_ADCSMEN ((uint32_t)0x00000200U) /*!< ADC1 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2592 #define RCC_APB2SMENR_SPI1SMEN ((uint32_t)0x00001000U) /*!< SPI1 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2593 #define RCC_APB2SMENR_USART1SMEN ((uint32_t)0x00004000U) /*!< USART1 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2594 #define RCC_APB2SMENR_DBGSMEN ((uint32_t)0x00400000U) /*!< DBGMCU clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2595
Kojto 119:aae6fcc7d9bb 2596 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2597 #define RCC_APB2SMENR_ADC1SMEN RCC_APB2SMENR_ADCSMEN /*!< ADC1 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2598 #define RCC_APB2SMENR_DBGMCUSMEN RCC_APB2SMENR_DBGSMEN /*!< DBGMCU clock enabled in sleep mode */
Kojto 99:dbbf35b96557 2599
Kojto 99:dbbf35b96557 2600 /***************** Bit definition for RCC_APB1SMENR register ******************/
Kojto 119:aae6fcc7d9bb 2601 #define RCC_APB1SMENR_TIM2SMEN ((uint32_t)0x00000001U) /*!< Timer 2 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2602 #define RCC_APB1SMENR_TIM6SMEN ((uint32_t)0x00000010U) /*!< Timer 6 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2603 #define RCC_APB1SMENR_LCDSMEN ((uint32_t)0x00000200U) /*!< LCD clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2604 #define RCC_APB1SMENR_WWDGSMEN ((uint32_t)0x00000800U) /*!< Window Watchdog clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2605 #define RCC_APB1SMENR_SPI2SMEN ((uint32_t)0x00004000U) /*!< SPI2 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2606 #define RCC_APB1SMENR_USART2SMEN ((uint32_t)0x00020000U) /*!< USART2 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2607 #define RCC_APB1SMENR_LPUART1SMEN ((uint32_t)0x00040000U) /*!< LPUART1 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2608 #define RCC_APB1SMENR_I2C1SMEN ((uint32_t)0x00200000U) /*!< I2C1 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2609 #define RCC_APB1SMENR_I2C2SMEN ((uint32_t)0x00400000U) /*!< I2C2 clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2610 #define RCC_APB1SMENR_USBSMEN ((uint32_t)0x00800000U) /*!< USB clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2611 #define RCC_APB1SMENR_CRSSMEN ((uint32_t)0x08000000U) /*!< CRS clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2612 #define RCC_APB1SMENR_PWRSMEN ((uint32_t)0x10000000U) /*!< PWR clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2613 #define RCC_APB1SMENR_DACSMEN ((uint32_t)0x20000000U) /*!< DAC clock enabled in sleep mode */
Kojto 119:aae6fcc7d9bb 2614 #define RCC_APB1SMENR_LPTIM1SMEN ((uint32_t)0x80000000U) /*!< LPTIM1 clock enabled in sleep mode */
Kojto 99:dbbf35b96557 2615
Kojto 99:dbbf35b96557 2616 /******************* Bit definition for RCC_CCIPR register *******************/
Kojto 99:dbbf35b96557 2617 /*!< USART1 Clock source selection */
Kojto 119:aae6fcc7d9bb 2618 #define RCC_CCIPR_USART1SEL ((uint32_t)0x00000003U) /*!< USART1SEL[1:0] bits */
Kojto 119:aae6fcc7d9bb 2619 #define RCC_CCIPR_USART1SEL_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2620 #define RCC_CCIPR_USART1SEL_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 99:dbbf35b96557 2621
Kojto 99:dbbf35b96557 2622 /*!< USART2 Clock source selection */
Kojto 119:aae6fcc7d9bb 2623 #define RCC_CCIPR_USART2SEL ((uint32_t)0x0000000CU) /*!< USART2SEL[1:0] bits */
Kojto 119:aae6fcc7d9bb 2624 #define RCC_CCIPR_USART2SEL_0 ((uint32_t)0x00000004U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2625 #define RCC_CCIPR_USART2SEL_1 ((uint32_t)0x00000008U) /*!< Bit 1 */
Kojto 99:dbbf35b96557 2626
Kojto 99:dbbf35b96557 2627 /*!< LPUART1 Clock source selection */
Kojto 99:dbbf35b96557 2628 #define RCC_CCIPR_LPUART1SEL ((uint32_t)0x0000C00) /*!< LPUART1SEL[1:0] bits */
Kojto 99:dbbf35b96557 2629 #define RCC_CCIPR_LPUART1SEL_0 ((uint32_t)0x0000400) /*!< Bit 0 */
Kojto 99:dbbf35b96557 2630 #define RCC_CCIPR_LPUART1SEL_1 ((uint32_t)0x0000800) /*!< Bit 1 */
Kojto 99:dbbf35b96557 2631
Kojto 99:dbbf35b96557 2632 /*!< I2C1 Clock source selection */
Kojto 119:aae6fcc7d9bb 2633 #define RCC_CCIPR_I2C1SEL ((uint32_t)0x00003000U) /*!< I2C1SEL [1:0] bits */
Kojto 119:aae6fcc7d9bb 2634 #define RCC_CCIPR_I2C1SEL_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2635 #define RCC_CCIPR_I2C1SEL_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 99:dbbf35b96557 2636
Kojto 99:dbbf35b96557 2637
Kojto 99:dbbf35b96557 2638 /*!< LPTIM1 Clock source selection */
Kojto 119:aae6fcc7d9bb 2639 #define RCC_CCIPR_LPTIM1SEL ((uint32_t)0x000C0000U) /*!< LPTIM1SEL [1:0] bits */
Kojto 119:aae6fcc7d9bb 2640 #define RCC_CCIPR_LPTIM1SEL_0 ((uint32_t)0x00040000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2641 #define RCC_CCIPR_LPTIM1SEL_1 ((uint32_t)0x00080000U) /*!< Bit 1 */
Kojto 99:dbbf35b96557 2642
Kojto 99:dbbf35b96557 2643 /*!< HSI48 Clock source selection */
Kojto 119:aae6fcc7d9bb 2644 #define RCC_CCIPR_HSI48SEL ((uint32_t)0x04000000U) /*!< HSI48 RC clock source selection bit for USB and RNG*/
Kojto 119:aae6fcc7d9bb 2645
Kojto 119:aae6fcc7d9bb 2646 /* Legacy defines */
Kojto 99:dbbf35b96557 2647 #define RCC_CCIPR_HSI48MSEL RCC_CCIPR_HSI48SEL
Kojto 99:dbbf35b96557 2648
Kojto 99:dbbf35b96557 2649 /******************* Bit definition for RCC_CSR register *******************/
Kojto 119:aae6fcc7d9bb 2650 #define RCC_CSR_LSION ((uint32_t)0x00000001U) /*!< Internal Low Speed oscillator enable */
Kojto 119:aae6fcc7d9bb 2651 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002U) /*!< Internal Low Speed oscillator Ready */
Kojto 119:aae6fcc7d9bb 2652
Kojto 119:aae6fcc7d9bb 2653 #define RCC_CSR_LSEON ((uint32_t)0x00000100U) /*!< External Low Speed oscillator enable */
Kojto 119:aae6fcc7d9bb 2654 #define RCC_CSR_LSERDY ((uint32_t)0x00000200U) /*!< External Low Speed oscillator Ready */
Kojto 119:aae6fcc7d9bb 2655 #define RCC_CSR_LSEBYP ((uint32_t)0x00000400U) /*!< External Low Speed oscillator Bypass */
Kojto 99:dbbf35b96557 2656
Kojto 119:aae6fcc7d9bb 2657 #define RCC_CSR_LSEDRV ((uint32_t)0x00001800U) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
Kojto 119:aae6fcc7d9bb 2658 #define RCC_CSR_LSEDRV_0 ((uint32_t)0x00000800U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2659 #define RCC_CSR_LSEDRV_1 ((uint32_t)0x00001000U) /*!< Bit 1 */
Kojto 99:dbbf35b96557 2660
Kojto 119:aae6fcc7d9bb 2661 #define RCC_CSR_LSECSSON ((uint32_t)0x00002000U) /*!< External Low Speed oscillator CSS Enable */
Kojto 119:aae6fcc7d9bb 2662 #define RCC_CSR_LSECSSD ((uint32_t)0x00004000U) /*!< External Low Speed oscillator CSS Detected */
Kojto 99:dbbf35b96557 2663
Kojto 99:dbbf35b96557 2664 /*!< RTC congiguration */
Kojto 119:aae6fcc7d9bb 2665 #define RCC_CSR_RTCSEL ((uint32_t)0x00030000U) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
Kojto 119:aae6fcc7d9bb 2666 #define RCC_CSR_RTCSEL_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 2667 #define RCC_CSR_RTCSEL_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 99:dbbf35b96557 2668
Kojto 119:aae6fcc7d9bb 2669 #define RCC_CSR_RTCSEL_NOCLOCK ((uint32_t)0x00000000U) /*!< No clock */
Kojto 119:aae6fcc7d9bb 2670 #define RCC_CSR_RTCSEL_LSE ((uint32_t)0x00010000U) /*!< LSE oscillator clock used as RTC clock */
Kojto 119:aae6fcc7d9bb 2671 #define RCC_CSR_RTCSEL_LSI ((uint32_t)0x00020000U) /*!< LSI oscillator clock used as RTC clock */
Kojto 119:aae6fcc7d9bb 2672 #define RCC_CSR_RTCSEL_HSE ((uint32_t)0x00030000U) /*!< HSE oscillator clock used as RTC clock */
Kojto 99:dbbf35b96557 2673
Kojto 119:aae6fcc7d9bb 2674 #define RCC_CSR_RTCEN ((uint32_t)0x00040000U) /*!< RTC clock enable */
Kojto 119:aae6fcc7d9bb 2675 #define RCC_CSR_RTCRST ((uint32_t)0x00080000U) /*!< RTC software reset */
Kojto 119:aae6fcc7d9bb 2676
Kojto 119:aae6fcc7d9bb 2677 #define RCC_CSR_RMVF ((uint32_t)0x00800000U) /*!< Remove reset flag */
Kojto 119:aae6fcc7d9bb 2678 #define RCC_CSR_FWRSTF ((uint32_t)0x01000000U) /*!< Mifare Firewall reset flag */
Kojto 119:aae6fcc7d9bb 2679 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000U) /*!< OBL reset flag */
Kojto 119:aae6fcc7d9bb 2680 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000U) /*!< PIN reset flag */
Kojto 119:aae6fcc7d9bb 2681 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000U) /*!< POR/PDR reset flag */
Kojto 119:aae6fcc7d9bb 2682 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000U) /*!< Software Reset flag */
Kojto 119:aae6fcc7d9bb 2683 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000U) /*!< Independent Watchdog reset flag */
Kojto 119:aae6fcc7d9bb 2684 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000U) /*!< Window watchdog reset flag */
Kojto 119:aae6fcc7d9bb 2685 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000U) /*!< Low-Power reset flag */
Kojto 119:aae6fcc7d9bb 2686
Kojto 119:aae6fcc7d9bb 2687 /* Reference defines */
Kojto 119:aae6fcc7d9bb 2688 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
Kojto 119:aae6fcc7d9bb 2689
Kojto 99:dbbf35b96557 2690
Kojto 99:dbbf35b96557 2691 /******************************************************************************/
Kojto 99:dbbf35b96557 2692 /* */
Kojto 99:dbbf35b96557 2693 /* RNG */
Kojto 99:dbbf35b96557 2694 /* */
Kojto 99:dbbf35b96557 2695 /******************************************************************************/
Kojto 99:dbbf35b96557 2696 /******************** Bits definition for RNG_CR register *******************/
Kojto 119:aae6fcc7d9bb 2697 #define RNG_CR_RNGEN ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 2698 #define RNG_CR_IE ((uint32_t)0x00000008U)
Kojto 99:dbbf35b96557 2699
Kojto 99:dbbf35b96557 2700 /******************** Bits definition for RNG_SR register *******************/
Kojto 119:aae6fcc7d9bb 2701 #define RNG_SR_DRDY ((uint32_t)0x00000001U)
Kojto 119:aae6fcc7d9bb 2702 #define RNG_SR_CECS ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 2703 #define RNG_SR_SECS ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 2704 #define RNG_SR_CEIS ((uint32_t)0x00000020U)
Kojto 119:aae6fcc7d9bb 2705 #define RNG_SR_SEIS ((uint32_t)0x00000040U)
Kojto 99:dbbf35b96557 2706
Kojto 99:dbbf35b96557 2707 /******************************************************************************/
Kojto 99:dbbf35b96557 2708 /* */
Kojto 99:dbbf35b96557 2709 /* Real-Time Clock (RTC) */
Kojto 99:dbbf35b96557 2710 /* */
Kojto 99:dbbf35b96557 2711 /******************************************************************************/
Kojto 99:dbbf35b96557 2712 /******************** Bits definition for RTC_TR register *******************/
Kojto 119:aae6fcc7d9bb 2713 #define RTC_TR_PM ((uint32_t)0x00400000U) /*!< */
Kojto 119:aae6fcc7d9bb 2714 #define RTC_TR_HT ((uint32_t)0x00300000U) /*!< */
Kojto 119:aae6fcc7d9bb 2715 #define RTC_TR_HT_0 ((uint32_t)0x00100000U) /*!< */
Kojto 119:aae6fcc7d9bb 2716 #define RTC_TR_HT_1 ((uint32_t)0x00200000U) /*!< */
Kojto 119:aae6fcc7d9bb 2717 #define RTC_TR_HU ((uint32_t)0x000F0000U) /*!< */
Kojto 119:aae6fcc7d9bb 2718 #define RTC_TR_HU_0 ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 2719 #define RTC_TR_HU_1 ((uint32_t)0x00020000U) /*!< */
Kojto 119:aae6fcc7d9bb 2720 #define RTC_TR_HU_2 ((uint32_t)0x00040000U) /*!< */
Kojto 119:aae6fcc7d9bb 2721 #define RTC_TR_HU_3 ((uint32_t)0x00080000U) /*!< */
Kojto 119:aae6fcc7d9bb 2722 #define RTC_TR_MNT ((uint32_t)0x00007000U) /*!< */
Kojto 119:aae6fcc7d9bb 2723 #define RTC_TR_MNT_0 ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2724 #define RTC_TR_MNT_1 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2725 #define RTC_TR_MNT_2 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2726 #define RTC_TR_MNU ((uint32_t)0x00000F00U) /*!< */
Kojto 119:aae6fcc7d9bb 2727 #define RTC_TR_MNU_0 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2728 #define RTC_TR_MNU_1 ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2729 #define RTC_TR_MNU_2 ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2730 #define RTC_TR_MNU_3 ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2731 #define RTC_TR_ST ((uint32_t)0x00000070U) /*!< */
Kojto 119:aae6fcc7d9bb 2732 #define RTC_TR_ST_0 ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2733 #define RTC_TR_ST_1 ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2734 #define RTC_TR_ST_2 ((uint32_t)0x00000040U) /*!< */
Kojto 119:aae6fcc7d9bb 2735 #define RTC_TR_SU ((uint32_t)0x0000000FU) /*!< */
Kojto 119:aae6fcc7d9bb 2736 #define RTC_TR_SU_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2737 #define RTC_TR_SU_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2738 #define RTC_TR_SU_2 ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2739 #define RTC_TR_SU_3 ((uint32_t)0x00000008U) /*!< */
Kojto 99:dbbf35b96557 2740
Kojto 99:dbbf35b96557 2741 /******************** Bits definition for RTC_DR register *******************/
Kojto 119:aae6fcc7d9bb 2742 #define RTC_DR_YT ((uint32_t)0x00F00000U) /*!< */
Kojto 119:aae6fcc7d9bb 2743 #define RTC_DR_YT_0 ((uint32_t)0x00100000U) /*!< */
Kojto 119:aae6fcc7d9bb 2744 #define RTC_DR_YT_1 ((uint32_t)0x00200000U) /*!< */
Kojto 119:aae6fcc7d9bb 2745 #define RTC_DR_YT_2 ((uint32_t)0x00400000U) /*!< */
Kojto 119:aae6fcc7d9bb 2746 #define RTC_DR_YT_3 ((uint32_t)0x00800000U) /*!< */
Kojto 119:aae6fcc7d9bb 2747 #define RTC_DR_YU ((uint32_t)0x000F0000U) /*!< */
Kojto 119:aae6fcc7d9bb 2748 #define RTC_DR_YU_0 ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 2749 #define RTC_DR_YU_1 ((uint32_t)0x00020000U) /*!< */
Kojto 119:aae6fcc7d9bb 2750 #define RTC_DR_YU_2 ((uint32_t)0x00040000U) /*!< */
Kojto 119:aae6fcc7d9bb 2751 #define RTC_DR_YU_3 ((uint32_t)0x00080000U) /*!< */
Kojto 119:aae6fcc7d9bb 2752 #define RTC_DR_WDU ((uint32_t)0x0000E000U) /*!< */
Kojto 119:aae6fcc7d9bb 2753 #define RTC_DR_WDU_0 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2754 #define RTC_DR_WDU_1 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2755 #define RTC_DR_WDU_2 ((uint32_t)0x00008000U) /*!< */
Kojto 119:aae6fcc7d9bb 2756 #define RTC_DR_MT ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2757 #define RTC_DR_MU ((uint32_t)0x00000F00U) /*!< */
Kojto 119:aae6fcc7d9bb 2758 #define RTC_DR_MU_0 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2759 #define RTC_DR_MU_1 ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2760 #define RTC_DR_MU_2 ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2761 #define RTC_DR_MU_3 ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2762 #define RTC_DR_DT ((uint32_t)0x00000030U) /*!< */
Kojto 119:aae6fcc7d9bb 2763 #define RTC_DR_DT_0 ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2764 #define RTC_DR_DT_1 ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2765 #define RTC_DR_DU ((uint32_t)0x0000000FU) /*!< */
Kojto 119:aae6fcc7d9bb 2766 #define RTC_DR_DU_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2767 #define RTC_DR_DU_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2768 #define RTC_DR_DU_2 ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2769 #define RTC_DR_DU_3 ((uint32_t)0x00000008U) /*!< */
Kojto 99:dbbf35b96557 2770
Kojto 99:dbbf35b96557 2771 /******************** Bits definition for RTC_CR register *******************/
Kojto 119:aae6fcc7d9bb 2772 #define RTC_CR_COE ((uint32_t)0x00800000U) /*!< */
Kojto 119:aae6fcc7d9bb 2773 #define RTC_CR_OSEL ((uint32_t)0x00600000U) /*!< */
Kojto 119:aae6fcc7d9bb 2774 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000U) /*!< */
Kojto 119:aae6fcc7d9bb 2775 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000U) /*!< */
Kojto 119:aae6fcc7d9bb 2776 #define RTC_CR_POL ((uint32_t)0x00100000U) /*!< */
Kojto 119:aae6fcc7d9bb 2777 #define RTC_CR_COSEL ((uint32_t)0x00080000U) /*!< */
Kojto 119:aae6fcc7d9bb 2778 #define RTC_CR_BCK ((uint32_t)0x00040000U) /*!< */
Kojto 119:aae6fcc7d9bb 2779 #define RTC_CR_SUB1H ((uint32_t)0x00020000U) /*!< */
Kojto 119:aae6fcc7d9bb 2780 #define RTC_CR_ADD1H ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 2781 #define RTC_CR_TSIE ((uint32_t)0x00008000U) /*!< */
Kojto 119:aae6fcc7d9bb 2782 #define RTC_CR_WUTIE ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2783 #define RTC_CR_ALRBIE ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2784 #define RTC_CR_ALRAIE ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2785 #define RTC_CR_TSE ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2786 #define RTC_CR_WUTE ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2787 #define RTC_CR_ALRBE ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2788 #define RTC_CR_ALRAE ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2789 #define RTC_CR_FMT ((uint32_t)0x00000040U) /*!< */
Kojto 119:aae6fcc7d9bb 2790 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2791 #define RTC_CR_REFCKON ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2792 #define RTC_CR_TSEDGE ((uint32_t)0x00000008U) /*!< */
Kojto 119:aae6fcc7d9bb 2793 #define RTC_CR_WUCKSEL ((uint32_t)0x00000007U) /*!< */
Kojto 119:aae6fcc7d9bb 2794 #define RTC_CR_WUCKSEL_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2795 #define RTC_CR_WUCKSEL_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2796 #define RTC_CR_WUCKSEL_2 ((uint32_t)0x00000004U) /*!< */
Kojto 99:dbbf35b96557 2797
Kojto 99:dbbf35b96557 2798 /******************** Bits definition for RTC_ISR register ******************/
Kojto 119:aae6fcc7d9bb 2799 #define RTC_ISR_RECALPF ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 2800 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2801 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2802 #define RTC_ISR_TSOVF ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2803 #define RTC_ISR_TSF ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2804 #define RTC_ISR_WUTF ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2805 #define RTC_ISR_ALRBF ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2806 #define RTC_ISR_ALRAF ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2807 #define RTC_ISR_INIT ((uint32_t)0x00000080U) /*!< */
Kojto 119:aae6fcc7d9bb 2808 #define RTC_ISR_INITF ((uint32_t)0x00000040U) /*!< */
Kojto 119:aae6fcc7d9bb 2809 #define RTC_ISR_RSF ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2810 #define RTC_ISR_INITS ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2811 #define RTC_ISR_SHPF ((uint32_t)0x00000008U) /*!< */
Kojto 119:aae6fcc7d9bb 2812 #define RTC_ISR_WUTWF ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2813 #define RTC_ISR_ALRBWF ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2814 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001U) /*!< */
Kojto 99:dbbf35b96557 2815
Kojto 99:dbbf35b96557 2816 /******************** Bits definition for RTC_PRER register *****************/
Kojto 119:aae6fcc7d9bb 2817 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000U) /*!< */
Kojto 119:aae6fcc7d9bb 2818 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFFU) /*!< */
Kojto 99:dbbf35b96557 2819
Kojto 99:dbbf35b96557 2820 /******************** Bits definition for RTC_WUTR register *****************/
Kojto 119:aae6fcc7d9bb 2821 #define RTC_WUTR_WUT ((uint32_t)0x0000FFFFU)
Kojto 99:dbbf35b96557 2822
Kojto 99:dbbf35b96557 2823 /******************** Bits definition for RTC_ALRMAR register ***************/
Kojto 119:aae6fcc7d9bb 2824 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2825 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2826 #define RTC_ALRMAR_DT ((uint32_t)0x30000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2827 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2828 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2829 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2830 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2831 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2832 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2833 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2834 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000U) /*!< */
Kojto 119:aae6fcc7d9bb 2835 #define RTC_ALRMAR_PM ((uint32_t)0x00400000U) /*!< */
Kojto 119:aae6fcc7d9bb 2836 #define RTC_ALRMAR_HT ((uint32_t)0x00300000U) /*!< */
Kojto 119:aae6fcc7d9bb 2837 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000U) /*!< */
Kojto 119:aae6fcc7d9bb 2838 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000U) /*!< */
Kojto 119:aae6fcc7d9bb 2839 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000U) /*!< */
Kojto 119:aae6fcc7d9bb 2840 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 2841 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000U) /*!< */
Kojto 119:aae6fcc7d9bb 2842 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000U) /*!< */
Kojto 119:aae6fcc7d9bb 2843 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000U) /*!< */
Kojto 119:aae6fcc7d9bb 2844 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000U) /*!< */
Kojto 119:aae6fcc7d9bb 2845 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000U) /*!< */
Kojto 119:aae6fcc7d9bb 2846 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2847 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2848 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2849 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00U) /*!< */
Kojto 119:aae6fcc7d9bb 2850 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2851 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2852 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2853 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2854 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080U) /*!< */
Kojto 119:aae6fcc7d9bb 2855 #define RTC_ALRMAR_ST ((uint32_t)0x00000070U) /*!< */
Kojto 119:aae6fcc7d9bb 2856 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2857 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2858 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040U) /*!< */
Kojto 119:aae6fcc7d9bb 2859 #define RTC_ALRMAR_SU ((uint32_t)0x0000000FU) /*!< */
Kojto 119:aae6fcc7d9bb 2860 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2861 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2862 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2863 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008U) /*!< */
Kojto 99:dbbf35b96557 2864
Kojto 99:dbbf35b96557 2865 /******************** Bits definition for RTC_ALRMBR register ***************/
Kojto 119:aae6fcc7d9bb 2866 #define RTC_ALRMBR_MSK4 ((uint32_t)0x80000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2867 #define RTC_ALRMBR_WDSEL ((uint32_t)0x40000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2868 #define RTC_ALRMBR_DT ((uint32_t)0x30000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2869 #define RTC_ALRMBR_DT_0 ((uint32_t)0x10000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2870 #define RTC_ALRMBR_DT_1 ((uint32_t)0x20000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2871 #define RTC_ALRMBR_DU ((uint32_t)0x0F000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2872 #define RTC_ALRMBR_DU_0 ((uint32_t)0x01000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2873 #define RTC_ALRMBR_DU_1 ((uint32_t)0x02000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2874 #define RTC_ALRMBR_DU_2 ((uint32_t)0x04000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2875 #define RTC_ALRMBR_DU_3 ((uint32_t)0x08000000U) /*!< */
Kojto 119:aae6fcc7d9bb 2876 #define RTC_ALRMBR_MSK3 ((uint32_t)0x00800000U) /*!< */
Kojto 119:aae6fcc7d9bb 2877 #define RTC_ALRMBR_PM ((uint32_t)0x00400000U) /*!< */
Kojto 119:aae6fcc7d9bb 2878 #define RTC_ALRMBR_HT ((uint32_t)0x00300000U) /*!< */
Kojto 119:aae6fcc7d9bb 2879 #define RTC_ALRMBR_HT_0 ((uint32_t)0x00100000U) /*!< */
Kojto 119:aae6fcc7d9bb 2880 #define RTC_ALRMBR_HT_1 ((uint32_t)0x00200000U) /*!< */
Kojto 119:aae6fcc7d9bb 2881 #define RTC_ALRMBR_HU ((uint32_t)0x000F0000U) /*!< */
Kojto 119:aae6fcc7d9bb 2882 #define RTC_ALRMBR_HU_0 ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 2883 #define RTC_ALRMBR_HU_1 ((uint32_t)0x00020000U) /*!< */
Kojto 119:aae6fcc7d9bb 2884 #define RTC_ALRMBR_HU_2 ((uint32_t)0x00040000U) /*!< */
Kojto 119:aae6fcc7d9bb 2885 #define RTC_ALRMBR_HU_3 ((uint32_t)0x00080000U) /*!< */
Kojto 119:aae6fcc7d9bb 2886 #define RTC_ALRMBR_MSK2 ((uint32_t)0x00008000U) /*!< */
Kojto 119:aae6fcc7d9bb 2887 #define RTC_ALRMBR_MNT ((uint32_t)0x00007000U) /*!< */
Kojto 119:aae6fcc7d9bb 2888 #define RTC_ALRMBR_MNT_0 ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2889 #define RTC_ALRMBR_MNT_1 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2890 #define RTC_ALRMBR_MNT_2 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2891 #define RTC_ALRMBR_MNU ((uint32_t)0x00000F00U) /*!< */
Kojto 119:aae6fcc7d9bb 2892 #define RTC_ALRMBR_MNU_0 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2893 #define RTC_ALRMBR_MNU_1 ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2894 #define RTC_ALRMBR_MNU_2 ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2895 #define RTC_ALRMBR_MNU_3 ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2896 #define RTC_ALRMBR_MSK1 ((uint32_t)0x00000080U) /*!< */
Kojto 119:aae6fcc7d9bb 2897 #define RTC_ALRMBR_ST ((uint32_t)0x00000070U) /*!< */
Kojto 119:aae6fcc7d9bb 2898 #define RTC_ALRMBR_ST_0 ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2899 #define RTC_ALRMBR_ST_1 ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2900 #define RTC_ALRMBR_ST_2 ((uint32_t)0x00000040U) /*!< */
Kojto 119:aae6fcc7d9bb 2901 #define RTC_ALRMBR_SU ((uint32_t)0x0000000FU) /*!< */
Kojto 119:aae6fcc7d9bb 2902 #define RTC_ALRMBR_SU_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2903 #define RTC_ALRMBR_SU_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2904 #define RTC_ALRMBR_SU_2 ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2905 #define RTC_ALRMBR_SU_3 ((uint32_t)0x00000008U) /*!< */
Kojto 99:dbbf35b96557 2906
Kojto 99:dbbf35b96557 2907 /******************** Bits definition for RTC_WPR register ******************/
Kojto 119:aae6fcc7d9bb 2908 #define RTC_WPR_KEY ((uint32_t)0x000000FFU) /*!< */
Kojto 99:dbbf35b96557 2909
Kojto 99:dbbf35b96557 2910 /******************** Bits definition for RTC_SSR register ******************/
Kojto 119:aae6fcc7d9bb 2911 #define RTC_SSR_SS ((uint32_t)0x0000FFFFU) /*!< */
Kojto 99:dbbf35b96557 2912
Kojto 99:dbbf35b96557 2913 /******************** Bits definition for RTC_SHIFTR register ***************/
Kojto 119:aae6fcc7d9bb 2914 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFFU) /*!< */
Kojto 119:aae6fcc7d9bb 2915 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000U) /*!< */
Kojto 99:dbbf35b96557 2916
Kojto 99:dbbf35b96557 2917 /******************** Bits definition for RTC_TSTR register *****************/
Kojto 119:aae6fcc7d9bb 2918 #define RTC_TSTR_PM ((uint32_t)0x00400000U) /*!< */
Kojto 119:aae6fcc7d9bb 2919 #define RTC_TSTR_HT ((uint32_t)0x00300000U) /*!< */
Kojto 119:aae6fcc7d9bb 2920 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000U) /*!< */
Kojto 119:aae6fcc7d9bb 2921 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000U) /*!< */
Kojto 119:aae6fcc7d9bb 2922 #define RTC_TSTR_HU ((uint32_t)0x000F0000U) /*!< */
Kojto 119:aae6fcc7d9bb 2923 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 2924 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000U) /*!< */
Kojto 119:aae6fcc7d9bb 2925 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000U) /*!< */
Kojto 119:aae6fcc7d9bb 2926 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000U) /*!< */
Kojto 119:aae6fcc7d9bb 2927 #define RTC_TSTR_MNT ((uint32_t)0x00007000U) /*!< */
Kojto 119:aae6fcc7d9bb 2928 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2929 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2930 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2931 #define RTC_TSTR_MNU ((uint32_t)0x00000F00U) /*!< */
Kojto 119:aae6fcc7d9bb 2932 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2933 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2934 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2935 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2936 #define RTC_TSTR_ST ((uint32_t)0x00000070U) /*!< */
Kojto 119:aae6fcc7d9bb 2937 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2938 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2939 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040U) /*!< */
Kojto 119:aae6fcc7d9bb 2940 #define RTC_TSTR_SU ((uint32_t)0x0000000FU) /*!< */
Kojto 119:aae6fcc7d9bb 2941 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2942 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2943 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2944 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008U) /*!< */
Kojto 99:dbbf35b96557 2945
Kojto 99:dbbf35b96557 2946 /******************** Bits definition for RTC_TSDR register *****************/
Kojto 119:aae6fcc7d9bb 2947 #define RTC_TSDR_WDU ((uint32_t)0x0000E000U) /*!< */
Kojto 119:aae6fcc7d9bb 2948 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2949 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2950 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000U) /*!< */
Kojto 119:aae6fcc7d9bb 2951 #define RTC_TSDR_MT ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 2952 #define RTC_TSDR_MU ((uint32_t)0x00000F00U) /*!< */
Kojto 119:aae6fcc7d9bb 2953 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2954 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 2955 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 2956 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 2957 #define RTC_TSDR_DT ((uint32_t)0x00000030U) /*!< */
Kojto 119:aae6fcc7d9bb 2958 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2959 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2960 #define RTC_TSDR_DU ((uint32_t)0x0000000FU) /*!< */
Kojto 119:aae6fcc7d9bb 2961 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2962 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2963 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2964 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008U) /*!< */
Kojto 99:dbbf35b96557 2965
Kojto 99:dbbf35b96557 2966 /******************** Bits definition for RTC_TSSSR register ****************/
Kojto 119:aae6fcc7d9bb 2967 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFFU)
Kojto 119:aae6fcc7d9bb 2968
Kojto 119:aae6fcc7d9bb 2969 /******************** Bits definition for RTC_CALR register *****************/
Kojto 119:aae6fcc7d9bb 2970 #define RTC_CALR_CALP ((uint32_t)0x00008000U) /*!< */
Kojto 119:aae6fcc7d9bb 2971 #define RTC_CALR_CALW8 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 2972 #define RTC_CALR_CALW16 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 2973 #define RTC_CALR_CALM ((uint32_t)0x000001FFU) /*!< */
Kojto 119:aae6fcc7d9bb 2974 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 2975 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 2976 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 2977 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008U) /*!< */
Kojto 119:aae6fcc7d9bb 2978 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 2979 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020U) /*!< */
Kojto 119:aae6fcc7d9bb 2980 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040U) /*!< */
Kojto 119:aae6fcc7d9bb 2981 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080U) /*!< */
Kojto 119:aae6fcc7d9bb 2982 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 2983
Kojto 119:aae6fcc7d9bb 2984 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 2985 #define RTC_CAL_CALP RTC_CALR_CALP
Kojto 119:aae6fcc7d9bb 2986 #define RTC_CAL_CALW8 RTC_CALR_CALW8
Kojto 119:aae6fcc7d9bb 2987 #define RTC_CAL_CALW16 RTC_CALR_CALW16
Kojto 119:aae6fcc7d9bb 2988 #define RTC_CAL_CALM RTC_CALR_CALM
Kojto 119:aae6fcc7d9bb 2989 #define RTC_CAL_CALM_0 RTC_CALR_CALM_0
Kojto 119:aae6fcc7d9bb 2990 #define RTC_CAL_CALM_1 RTC_CALR_CALM_1
Kojto 119:aae6fcc7d9bb 2991 #define RTC_CAL_CALM_2 RTC_CALR_CALM_2
Kojto 119:aae6fcc7d9bb 2992 #define RTC_CAL_CALM_3 RTC_CALR_CALM_3
Kojto 119:aae6fcc7d9bb 2993 #define RTC_CAL_CALM_4 RTC_CALR_CALM_4
Kojto 119:aae6fcc7d9bb 2994 #define RTC_CAL_CALM_5 RTC_CALR_CALM_5
Kojto 119:aae6fcc7d9bb 2995 #define RTC_CAL_CALM_6 RTC_CALR_CALM_6
Kojto 119:aae6fcc7d9bb 2996 #define RTC_CAL_CALM_7 RTC_CALR_CALM_7
Kojto 119:aae6fcc7d9bb 2997 #define RTC_CAL_CALM_8 RTC_CALR_CALM_8
Kojto 99:dbbf35b96557 2998
Kojto 99:dbbf35b96557 2999 /******************** Bits definition for RTC_TAMPCR register ****************/
Kojto 119:aae6fcc7d9bb 3000 #define RTC_TAMPCR_TAMP2MF ((uint32_t)0x00200000U) /*!< */
Kojto 119:aae6fcc7d9bb 3001 #define RTC_TAMPCR_TAMP2NOERASE ((uint32_t)0x00100000U) /*!< */
Kojto 119:aae6fcc7d9bb 3002 #define RTC_TAMPCR_TAMP2IE ((uint32_t)0x00080000U) /*!< */
Kojto 119:aae6fcc7d9bb 3003 #define RTC_TAMPCR_TAMP1MF ((uint32_t)0x00040000U) /*!< */
Kojto 119:aae6fcc7d9bb 3004 #define RTC_TAMPCR_TAMP1NOERASE ((uint32_t)0x00020000U) /*!< */
Kojto 119:aae6fcc7d9bb 3005 #define RTC_TAMPCR_TAMP1IE ((uint32_t)0x00010000U) /*!< */
Kojto 119:aae6fcc7d9bb 3006 #define RTC_TAMPCR_TAMPPUDIS ((uint32_t)0x00008000U) /*!< */
Kojto 119:aae6fcc7d9bb 3007 #define RTC_TAMPCR_TAMPPRCH ((uint32_t)0x00006000U) /*!< */
Kojto 119:aae6fcc7d9bb 3008 #define RTC_TAMPCR_TAMPPRCH_0 ((uint32_t)0x00002000U) /*!< */
Kojto 119:aae6fcc7d9bb 3009 #define RTC_TAMPCR_TAMPPRCH_1 ((uint32_t)0x00004000U) /*!< */
Kojto 119:aae6fcc7d9bb 3010 #define RTC_TAMPCR_TAMPFLT ((uint32_t)0x00001800U) /*!< */
Kojto 119:aae6fcc7d9bb 3011 #define RTC_TAMPCR_TAMPFLT_0 ((uint32_t)0x00000800U) /*!< */
Kojto 119:aae6fcc7d9bb 3012 #define RTC_TAMPCR_TAMPFLT_1 ((uint32_t)0x00001000U) /*!< */
Kojto 119:aae6fcc7d9bb 3013 #define RTC_TAMPCR_TAMPFREQ ((uint32_t)0x00000700U) /*!< */
Kojto 119:aae6fcc7d9bb 3014 #define RTC_TAMPCR_TAMPFREQ_0 ((uint32_t)0x00000100U) /*!< */
Kojto 119:aae6fcc7d9bb 3015 #define RTC_TAMPCR_TAMPFREQ_1 ((uint32_t)0x00000200U) /*!< */
Kojto 119:aae6fcc7d9bb 3016 #define RTC_TAMPCR_TAMPFREQ_2 ((uint32_t)0x00000400U) /*!< */
Kojto 119:aae6fcc7d9bb 3017 #define RTC_TAMPCR_TAMPTS ((uint32_t)0x00000080U) /*!< */
Kojto 119:aae6fcc7d9bb 3018 #define RTC_TAMPCR_TAMP2TRG ((uint32_t)0x00000010U) /*!< */
Kojto 119:aae6fcc7d9bb 3019 #define RTC_TAMPCR_TAMP2E ((uint32_t)0x00000008U) /*!< */
Kojto 119:aae6fcc7d9bb 3020 #define RTC_TAMPCR_TAMPIE ((uint32_t)0x00000004U) /*!< */
Kojto 119:aae6fcc7d9bb 3021 #define RTC_TAMPCR_TAMP1TRG ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 3022 #define RTC_TAMPCR_TAMP1E ((uint32_t)0x00000001U) /*!< */
Kojto 99:dbbf35b96557 3023
Kojto 99:dbbf35b96557 3024 /******************** Bits definition for RTC_ALRMASSR register *************/
Kojto 119:aae6fcc7d9bb 3025 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000U)
Kojto 119:aae6fcc7d9bb 3026 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000U)
Kojto 119:aae6fcc7d9bb 3027 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000U)
Kojto 119:aae6fcc7d9bb 3028 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000U)
Kojto 119:aae6fcc7d9bb 3029 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000U)
Kojto 119:aae6fcc7d9bb 3030 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFFU)
Kojto 99:dbbf35b96557 3031
Kojto 99:dbbf35b96557 3032 /******************** Bits definition for RTC_ALRMBSSR register *************/
Kojto 119:aae6fcc7d9bb 3033 #define RTC_ALRMBSSR_MASKSS ((uint32_t)0x0F000000U)
Kojto 119:aae6fcc7d9bb 3034 #define RTC_ALRMBSSR_MASKSS_0 ((uint32_t)0x01000000U)
Kojto 119:aae6fcc7d9bb 3035 #define RTC_ALRMBSSR_MASKSS_1 ((uint32_t)0x02000000U)
Kojto 119:aae6fcc7d9bb 3036 #define RTC_ALRMBSSR_MASKSS_2 ((uint32_t)0x04000000U)
Kojto 119:aae6fcc7d9bb 3037 #define RTC_ALRMBSSR_MASKSS_3 ((uint32_t)0x08000000U)
Kojto 119:aae6fcc7d9bb 3038 #define RTC_ALRMBSSR_SS ((uint32_t)0x00007FFFU)
Kojto 99:dbbf35b96557 3039
Kojto 99:dbbf35b96557 3040 /******************** Bits definition for RTC_OR register ****************/
Kojto 119:aae6fcc7d9bb 3041 #define RTC_OR_OUT_RMP ((uint32_t)0x00000002U) /*!< */
Kojto 119:aae6fcc7d9bb 3042 #define RTC_OR_ALARMOUTTYPE ((uint32_t)0x00000001U) /*!< */
Kojto 119:aae6fcc7d9bb 3043
Kojto 119:aae6fcc7d9bb 3044 /* Legacy defines */
Kojto 99:dbbf35b96557 3045 #define RTC_OR_RTC_OUT_RMP RTC_OR_OUT_RMP
Kojto 99:dbbf35b96557 3046
Kojto 99:dbbf35b96557 3047 /******************** Bits definition for RTC_BKP0R register ****************/
Kojto 119:aae6fcc7d9bb 3048 #define RTC_BKP0R ((uint32_t)0xFFFFFFFFU) /*!< */
Kojto 99:dbbf35b96557 3049
Kojto 99:dbbf35b96557 3050 /******************** Bits definition for RTC_BKP1R register ****************/
Kojto 119:aae6fcc7d9bb 3051 #define RTC_BKP1R ((uint32_t)0xFFFFFFFFU) /*!< */
Kojto 99:dbbf35b96557 3052
Kojto 99:dbbf35b96557 3053 /******************** Bits definition for RTC_BKP2R register ****************/
Kojto 119:aae6fcc7d9bb 3054 #define RTC_BKP2R ((uint32_t)0xFFFFFFFFU) /*!< */
Kojto 99:dbbf35b96557 3055
Kojto 99:dbbf35b96557 3056 /******************** Bits definition for RTC_BKP3R register ****************/
Kojto 119:aae6fcc7d9bb 3057 #define RTC_BKP3R ((uint32_t)0xFFFFFFFFU) /*!< */
Kojto 99:dbbf35b96557 3058
Kojto 99:dbbf35b96557 3059 /******************** Bits definition for RTC_BKP4R register ****************/
Kojto 119:aae6fcc7d9bb 3060 #define RTC_BKP4R ((uint32_t)0xFFFFFFFFU) /*!< */
Kojto 119:aae6fcc7d9bb 3061
Kojto 119:aae6fcc7d9bb 3062 /******************** Number of backup registers ******************************/
Kojto 119:aae6fcc7d9bb 3063 #define RTC_BKP_NUMBER ((uint32_t)0x00000005U) /*!< */
Kojto 99:dbbf35b96557 3064
Kojto 99:dbbf35b96557 3065 /******************************************************************************/
Kojto 99:dbbf35b96557 3066 /* */
Kojto 99:dbbf35b96557 3067 /* Serial Peripheral Interface (SPI) */
Kojto 99:dbbf35b96557 3068 /* */
Kojto 99:dbbf35b96557 3069 /******************************************************************************/
Kojto 99:dbbf35b96557 3070 /******************* Bit definition for SPI_CR1 register ********************/
Kojto 119:aae6fcc7d9bb 3071 #define SPI_CR1_CPHA ((uint32_t)0x00000001U) /*!< Clock Phase */
Kojto 119:aae6fcc7d9bb 3072 #define SPI_CR1_CPOL ((uint32_t)0x00000002U) /*!< Clock Polarity */
Kojto 119:aae6fcc7d9bb 3073 #define SPI_CR1_MSTR ((uint32_t)0x00000004U) /*!< Master Selection */
Kojto 119:aae6fcc7d9bb 3074 #define SPI_CR1_BR ((uint32_t)0x00000038U) /*!< BR[2:0] bits (Baud Rate Control) */
Kojto 119:aae6fcc7d9bb 3075 #define SPI_CR1_BR_0 ((uint32_t)0x00000008U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3076 #define SPI_CR1_BR_1 ((uint32_t)0x00000010U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3077 #define SPI_CR1_BR_2 ((uint32_t)0x00000020U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 3078 #define SPI_CR1_SPE ((uint32_t)0x00000040U) /*!< SPI Enable */
Kojto 119:aae6fcc7d9bb 3079 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080U) /*!< Frame Format */
Kojto 119:aae6fcc7d9bb 3080 #define SPI_CR1_SSI ((uint32_t)0x00000100U) /*!< Internal slave select */
Kojto 119:aae6fcc7d9bb 3081 #define SPI_CR1_SSM ((uint32_t)0x00000200U) /*!< Software slave management */
Kojto 119:aae6fcc7d9bb 3082 #define SPI_CR1_RXONLY ((uint32_t)0x00000400U) /*!< Receive only */
Kojto 119:aae6fcc7d9bb 3083 #define SPI_CR1_DFF ((uint32_t)0x00000800U) /*!< Data Frame Format */
Kojto 119:aae6fcc7d9bb 3084 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000U) /*!< Transmit CRC next */
Kojto 119:aae6fcc7d9bb 3085 #define SPI_CR1_CRCEN ((uint32_t)0x00002000U) /*!< Hardware CRC calculation enable */
Kojto 119:aae6fcc7d9bb 3086 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000U) /*!< Output enable in bidirectional mode */
Kojto 119:aae6fcc7d9bb 3087 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000U) /*!< Bidirectional data mode enable */
Kojto 99:dbbf35b96557 3088
Kojto 99:dbbf35b96557 3089 /******************* Bit definition for SPI_CR2 register ********************/
Kojto 119:aae6fcc7d9bb 3090 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001U) /*!< Rx Buffer DMA Enable */
Kojto 119:aae6fcc7d9bb 3091 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002U) /*!< Tx Buffer DMA Enable */
Kojto 119:aae6fcc7d9bb 3092 #define SPI_CR2_SSOE ((uint32_t)0x00000004U) /*!< SS Output Enable */
Kojto 119:aae6fcc7d9bb 3093 #define SPI_CR2_FRF ((uint32_t)0x00000010U) /*!< Frame Format Enable */
Kojto 119:aae6fcc7d9bb 3094 #define SPI_CR2_ERRIE ((uint32_t)0x00000020U) /*!< Error Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3095 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040U) /*!< RX buffer Not Empty Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3096 #define SPI_CR2_TXEIE ((uint32_t)0x00000080U) /*!< Tx buffer Empty Interrupt Enable */
Kojto 99:dbbf35b96557 3097
Kojto 99:dbbf35b96557 3098 /******************** Bit definition for SPI_SR register ********************/
Kojto 119:aae6fcc7d9bb 3099 #define SPI_SR_RXNE ((uint32_t)0x00000001U) /*!< Receive buffer Not Empty */
Kojto 119:aae6fcc7d9bb 3100 #define SPI_SR_TXE ((uint32_t)0x00000002U) /*!< Transmit buffer Empty */
Kojto 119:aae6fcc7d9bb 3101 #define SPI_SR_CHSIDE ((uint32_t)0x00000004U) /*!< Channel side */
Kojto 119:aae6fcc7d9bb 3102 #define SPI_SR_UDR ((uint32_t)0x00000008U) /*!< Underrun flag */
Kojto 119:aae6fcc7d9bb 3103 #define SPI_SR_CRCERR ((uint32_t)0x00000010U) /*!< CRC Error flag */
Kojto 119:aae6fcc7d9bb 3104 #define SPI_SR_MODF ((uint32_t)0x00000020U) /*!< Mode fault */
Kojto 119:aae6fcc7d9bb 3105 #define SPI_SR_OVR ((uint32_t)0x00000040U) /*!< Overrun flag */
Kojto 119:aae6fcc7d9bb 3106 #define SPI_SR_BSY ((uint32_t)0x00000080U) /*!< Busy flag */
Kojto 119:aae6fcc7d9bb 3107 #define SPI_SR_FRE ((uint32_t)0x00000100U) /*!< TI frame format error */
Kojto 99:dbbf35b96557 3108
Kojto 99:dbbf35b96557 3109 /******************** Bit definition for SPI_DR register ********************/
Kojto 119:aae6fcc7d9bb 3110 #define SPI_DR_DR ((uint32_t)0x0000FFFFU) /*!< Data Register */
Kojto 99:dbbf35b96557 3111
Kojto 99:dbbf35b96557 3112 /******************* Bit definition for SPI_CRCPR register ******************/
Kojto 119:aae6fcc7d9bb 3113 #define SPI_CRCPR_CRCPOLY ((uint32_t)0x0000FFFFU) /*!< CRC polynomial register */
Kojto 99:dbbf35b96557 3114
Kojto 99:dbbf35b96557 3115 /****************** Bit definition for SPI_RXCRCR register ******************/
Kojto 119:aae6fcc7d9bb 3116 #define SPI_RXCRCR_RXCRC ((uint32_t)0x0000FFFFU) /*!< Rx CRC Register */
Kojto 99:dbbf35b96557 3117
Kojto 99:dbbf35b96557 3118 /****************** Bit definition for SPI_TXCRCR register ******************/
Kojto 119:aae6fcc7d9bb 3119 #define SPI_TXCRCR_TXCRC ((uint32_t)0x0000FFFFU) /*!< Tx CRC Register */
Kojto 99:dbbf35b96557 3120
Kojto 99:dbbf35b96557 3121 /****************** Bit definition for SPI_I2SCFGR register *****************/
Kojto 119:aae6fcc7d9bb 3122 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001U) /*!<Channel length (number of bits per audio channel) */
Kojto 119:aae6fcc7d9bb 3123 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006U) /*!<DATLEN[1:0] bits (Data length to be transferred) */
Kojto 119:aae6fcc7d9bb 3124 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3125 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3126 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008U) /*!<steady state clock polarity */
Kojto 119:aae6fcc7d9bb 3127 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030U) /*!<I2SSTD[1:0] bits (I2S standard selection) */
Kojto 119:aae6fcc7d9bb 3128 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3129 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3130 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080U) /*!<PCM frame synchronization */
Kojto 119:aae6fcc7d9bb 3131 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300U) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
Kojto 119:aae6fcc7d9bb 3132 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3133 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3134 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400U) /*!<I2S Enable */
Kojto 119:aae6fcc7d9bb 3135 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800U) /*!<I2S mode selection */
Kojto 99:dbbf35b96557 3136 /****************** Bit definition for SPI_I2SPR register *******************/
Kojto 119:aae6fcc7d9bb 3137 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FFU) /*!<I2S Linear prescaler */
Kojto 119:aae6fcc7d9bb 3138 #define SPI_I2SPR_ODD ((uint32_t)0x00000100U) /*!<Odd factor for the prescaler */
Kojto 119:aae6fcc7d9bb 3139 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200U) /*!<Master Clock Output Enable */
Kojto 99:dbbf35b96557 3140
Kojto 99:dbbf35b96557 3141 /******************************************************************************/
Kojto 99:dbbf35b96557 3142 /* */
Kojto 99:dbbf35b96557 3143 /* System Configuration (SYSCFG) */
Kojto 99:dbbf35b96557 3144 /* */
Kojto 99:dbbf35b96557 3145 /******************************************************************************/
Kojto 99:dbbf35b96557 3146 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
Kojto 119:aae6fcc7d9bb 3147 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003U) /*!< SYSCFG_Memory Remap Config */
Kojto 119:aae6fcc7d9bb 3148 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001U) /*!< SYSCFG_Memory Remap Config Bit 0 */
Kojto 119:aae6fcc7d9bb 3149 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002U) /*!< SYSCFG_Memory Remap Config Bit 1 */
Kojto 119:aae6fcc7d9bb 3150 #define SYSCFG_CFGR1_BOOT_MODE ((uint32_t)0x00000300U) /*!< SYSCFG_Boot mode Config */
Kojto 119:aae6fcc7d9bb 3151 #define SYSCFG_CFGR1_BOOT_MODE_0 ((uint32_t)0x00000100U) /*!< SYSCFG_Boot mode Config Bit 0 */
Kojto 119:aae6fcc7d9bb 3152 #define SYSCFG_CFGR1_BOOT_MODE_1 ((uint32_t)0x00000200U) /*!< SYSCFG_Boot mode Config Bit 1 */
Kojto 99:dbbf35b96557 3153
Kojto 99:dbbf35b96557 3154 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
Kojto 119:aae6fcc7d9bb 3155 #define SYSCFG_CFGR2_FWDISEN ((uint32_t)0x00000001U) /*!< Firewall disable bit */
Kojto 119:aae6fcc7d9bb 3156 #define SYSCFG_CFGR2_CAPA ((uint32_t)0x0000000EU) /*!< Connection of internal Vlcd rail to external capacitors */
Kojto 119:aae6fcc7d9bb 3157 #define SYSCFG_CFGR2_CAPA_0 ((uint32_t)0x00000002U)
Kojto 119:aae6fcc7d9bb 3158 #define SYSCFG_CFGR2_CAPA_1 ((uint32_t)0x00000004U)
Kojto 119:aae6fcc7d9bb 3159 #define SYSCFG_CFGR2_CAPA_2 ((uint32_t)0x00000008U)
Kojto 119:aae6fcc7d9bb 3160 #define SYSCFG_CFGR2_I2C_PB6_FMP ((uint32_t)0x00000100U) /*!< I2C PB6 Fast mode plus */
Kojto 119:aae6fcc7d9bb 3161 #define SYSCFG_CFGR2_I2C_PB7_FMP ((uint32_t)0x00000200U) /*!< I2C PB7 Fast mode plus */
Kojto 119:aae6fcc7d9bb 3162 #define SYSCFG_CFGR2_I2C_PB8_FMP ((uint32_t)0x00000400U) /*!< I2C PB8 Fast mode plus */
Kojto 119:aae6fcc7d9bb 3163 #define SYSCFG_CFGR2_I2C_PB9_FMP ((uint32_t)0x00000800U) /*!< I2C PB9 Fast mode plus */
Kojto 119:aae6fcc7d9bb 3164 #define SYSCFG_CFGR2_I2C1_FMP ((uint32_t)0x00001000U) /*!< I2C1 Fast mode plus */
Kojto 119:aae6fcc7d9bb 3165 #define SYSCFG_CFGR2_I2C2_FMP ((uint32_t)0x00002000U) /*!< I2C2 Fast mode plus */
Kojto 99:dbbf35b96557 3166
Kojto 99:dbbf35b96557 3167 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
Kojto 119:aae6fcc7d9bb 3168 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000FU) /*!< EXTI 0 configuration */
Kojto 119:aae6fcc7d9bb 3169 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0U) /*!< EXTI 1 configuration */
Kojto 119:aae6fcc7d9bb 3170 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00U) /*!< EXTI 2 configuration */
Kojto 119:aae6fcc7d9bb 3171 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000U) /*!< EXTI 3 configuration */
Kojto 99:dbbf35b96557 3172
Kojto 99:dbbf35b96557 3173 /**
Kojto 99:dbbf35b96557 3174 * @brief EXTI0 configuration
Kojto 99:dbbf35b96557 3175 */
Kojto 119:aae6fcc7d9bb 3176 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000U) /*!< PA[0] pin */
Kojto 119:aae6fcc7d9bb 3177 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001U) /*!< PB[0] pin */
Kojto 119:aae6fcc7d9bb 3178 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002U) /*!< PC[0] pin */
Kojto 119:aae6fcc7d9bb 3179 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000005U) /*!< PH[0] pin */
Kojto 99:dbbf35b96557 3180
Kojto 99:dbbf35b96557 3181 /**
Kojto 99:dbbf35b96557 3182 * @brief EXTI1 configuration
Kojto 99:dbbf35b96557 3183 */
Kojto 119:aae6fcc7d9bb 3184 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000U) /*!< PA[1] pin */
Kojto 119:aae6fcc7d9bb 3185 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010U) /*!< PB[1] pin */
Kojto 119:aae6fcc7d9bb 3186 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020U) /*!< PC[1] pin */
Kojto 119:aae6fcc7d9bb 3187 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000050U) /*!< PH[1] pin */
Kojto 99:dbbf35b96557 3188
Kojto 99:dbbf35b96557 3189 /**
Kojto 99:dbbf35b96557 3190 * @brief EXTI2 configuration
Kojto 99:dbbf35b96557 3191 */
Kojto 119:aae6fcc7d9bb 3192 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000U) /*!< PA[2] pin */
Kojto 119:aae6fcc7d9bb 3193 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100U) /*!< PB[2] pin */
Kojto 119:aae6fcc7d9bb 3194 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200U) /*!< PC[2] pin */
Kojto 119:aae6fcc7d9bb 3195 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300U) /*!< PD[2] pin */
Kojto 99:dbbf35b96557 3196
Kojto 99:dbbf35b96557 3197 /**
Kojto 99:dbbf35b96557 3198 * @brief EXTI3 configuration
Kojto 99:dbbf35b96557 3199 */
Kojto 119:aae6fcc7d9bb 3200 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000U) /*!< PA[3] pin */
Kojto 119:aae6fcc7d9bb 3201 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000U) /*!< PB[3] pin */
Kojto 119:aae6fcc7d9bb 3202 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000U) /*!< PC[3] pin */
Kojto 99:dbbf35b96557 3203
Kojto 99:dbbf35b96557 3204 /***************** Bit definition for SYSCFG_EXTICR2 register *****************/
Kojto 119:aae6fcc7d9bb 3205 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000FU) /*!< EXTI 4 configuration */
Kojto 119:aae6fcc7d9bb 3206 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0U) /*!< EXTI 5 configuration */
Kojto 119:aae6fcc7d9bb 3207 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00U) /*!< EXTI 6 configuration */
Kojto 119:aae6fcc7d9bb 3208 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000U) /*!< EXTI 7 configuration */
Kojto 99:dbbf35b96557 3209
Kojto 99:dbbf35b96557 3210 /**
Kojto 99:dbbf35b96557 3211 * @brief EXTI4 configuration
Kojto 99:dbbf35b96557 3212 */
Kojto 119:aae6fcc7d9bb 3213 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000U) /*!< PA[4] pin */
Kojto 119:aae6fcc7d9bb 3214 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001U) /*!< PB[4] pin */
Kojto 119:aae6fcc7d9bb 3215 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002U) /*!< PC[4] pin */
Kojto 99:dbbf35b96557 3216
Kojto 99:dbbf35b96557 3217 /**
Kojto 99:dbbf35b96557 3218 * @brief EXTI5 configuration
Kojto 99:dbbf35b96557 3219 */
Kojto 119:aae6fcc7d9bb 3220 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000U) /*!< PA[5] pin */
Kojto 119:aae6fcc7d9bb 3221 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010U) /*!< PB[5] pin */
Kojto 119:aae6fcc7d9bb 3222 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020U) /*!< PC[5] pin */
Kojto 99:dbbf35b96557 3223
Kojto 99:dbbf35b96557 3224 /**
Kojto 99:dbbf35b96557 3225 * @brief EXTI6 configuration
Kojto 99:dbbf35b96557 3226 */
Kojto 119:aae6fcc7d9bb 3227 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000U) /*!< PA[6] pin */
Kojto 119:aae6fcc7d9bb 3228 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100U) /*!< PB[6] pin */
Kojto 119:aae6fcc7d9bb 3229 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200U) /*!< PC[6] pin */
Kojto 99:dbbf35b96557 3230
Kojto 99:dbbf35b96557 3231 /**
Kojto 99:dbbf35b96557 3232 * @brief EXTI7 configuration
Kojto 99:dbbf35b96557 3233 */
Kojto 119:aae6fcc7d9bb 3234 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000U) /*!< PA[7] pin */
Kojto 119:aae6fcc7d9bb 3235 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000U) /*!< PB[7] pin */
Kojto 119:aae6fcc7d9bb 3236 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000U) /*!< PC[7] pin */
Kojto 99:dbbf35b96557 3237
Kojto 99:dbbf35b96557 3238 /***************** Bit definition for SYSCFG_EXTICR3 register *****************/
Kojto 119:aae6fcc7d9bb 3239 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000FU) /*!< EXTI 8 configuration */
Kojto 119:aae6fcc7d9bb 3240 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0U) /*!< EXTI 9 configuration */
Kojto 119:aae6fcc7d9bb 3241 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00U) /*!< EXTI 10 configuration */
Kojto 119:aae6fcc7d9bb 3242 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000U) /*!< EXTI 11 configuration */
Kojto 99:dbbf35b96557 3243
Kojto 99:dbbf35b96557 3244 /**
Kojto 99:dbbf35b96557 3245 * @brief EXTI8 configuration
Kojto 99:dbbf35b96557 3246 */
Kojto 119:aae6fcc7d9bb 3247 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000U) /*!< PA[8] pin */
Kojto 119:aae6fcc7d9bb 3248 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001U) /*!< PB[8] pin */
Kojto 119:aae6fcc7d9bb 3249 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002U) /*!< PC[8] pin */
Kojto 99:dbbf35b96557 3250
Kojto 99:dbbf35b96557 3251 /**
Kojto 99:dbbf35b96557 3252 * @brief EXTI9 configuration
Kojto 99:dbbf35b96557 3253 */
Kojto 119:aae6fcc7d9bb 3254 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000U) /*!< PA[9] pin */
Kojto 119:aae6fcc7d9bb 3255 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010U) /*!< PB[9] pin */
Kojto 119:aae6fcc7d9bb 3256 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020U) /*!< PC[9] pin */
Kojto 99:dbbf35b96557 3257
Kojto 99:dbbf35b96557 3258 /**
Kojto 99:dbbf35b96557 3259 * @brief EXTI10 configuration
Kojto 99:dbbf35b96557 3260 */
Kojto 119:aae6fcc7d9bb 3261 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000U) /*!< PA[10] pin */
Kojto 119:aae6fcc7d9bb 3262 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100U) /*!< PB[10] pin */
Kojto 119:aae6fcc7d9bb 3263 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200U) /*!< PC[10] pin */
Kojto 99:dbbf35b96557 3264
Kojto 99:dbbf35b96557 3265 /**
Kojto 99:dbbf35b96557 3266 * @brief EXTI11 configuration
Kojto 99:dbbf35b96557 3267 */
Kojto 119:aae6fcc7d9bb 3268 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000U) /*!< PA[11] pin */
Kojto 119:aae6fcc7d9bb 3269 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000U) /*!< PB[11] pin */
Kojto 119:aae6fcc7d9bb 3270 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000U) /*!< PC[11] pin */
Kojto 99:dbbf35b96557 3271
Kojto 99:dbbf35b96557 3272 /***************** Bit definition for SYSCFG_EXTICR4 register *****************/
Kojto 119:aae6fcc7d9bb 3273 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000FU) /*!< EXTI 12 configuration */
Kojto 119:aae6fcc7d9bb 3274 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0U) /*!< EXTI 13 configuration */
Kojto 119:aae6fcc7d9bb 3275 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00U) /*!< EXTI 14 configuration */
Kojto 119:aae6fcc7d9bb 3276 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000U) /*!< EXTI 15 configuration */
Kojto 99:dbbf35b96557 3277
Kojto 99:dbbf35b96557 3278 /**
Kojto 99:dbbf35b96557 3279 * @brief EXTI12 configuration
Kojto 99:dbbf35b96557 3280 */
Kojto 119:aae6fcc7d9bb 3281 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000U) /*!< PA[12] pin */
Kojto 119:aae6fcc7d9bb 3282 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001U) /*!< PB[12] pin */
Kojto 119:aae6fcc7d9bb 3283 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002U) /*!< PC[12] pin */
Kojto 99:dbbf35b96557 3284
Kojto 99:dbbf35b96557 3285 /**
Kojto 99:dbbf35b96557 3286 * @brief EXTI13 configuration
Kojto 99:dbbf35b96557 3287 */
Kojto 119:aae6fcc7d9bb 3288 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000U) /*!< PA[13] pin */
Kojto 119:aae6fcc7d9bb 3289 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010U) /*!< PB[13] pin */
Kojto 119:aae6fcc7d9bb 3290 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020U) /*!< PC[13] pin */
Kojto 99:dbbf35b96557 3291
Kojto 99:dbbf35b96557 3292 /**
Kojto 99:dbbf35b96557 3293 * @brief EXTI14 configuration
Kojto 99:dbbf35b96557 3294 */
Kojto 119:aae6fcc7d9bb 3295 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000U) /*!< PA[14] pin */
Kojto 119:aae6fcc7d9bb 3296 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100U) /*!< PB[14] pin */
Kojto 119:aae6fcc7d9bb 3297 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200U) /*!< PC[14] pin */
Kojto 99:dbbf35b96557 3298
Kojto 99:dbbf35b96557 3299 /**
Kojto 99:dbbf35b96557 3300 * @brief EXTI15 configuration
Kojto 99:dbbf35b96557 3301 */
Kojto 119:aae6fcc7d9bb 3302 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000U) /*!< PA[15] pin */
Kojto 119:aae6fcc7d9bb 3303 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000U) /*!< PB[15] pin */
Kojto 119:aae6fcc7d9bb 3304 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000U) /*!< PC[15] pin */
Kojto 99:dbbf35b96557 3305
Kojto 99:dbbf35b96557 3306
Kojto 99:dbbf35b96557 3307 /***************** Bit definition for SYSCFG_CFGR3 register ****************/
Kojto 119:aae6fcc7d9bb 3308 #define SYSCFG_CFGR3_EN_VREFINT ((uint32_t)0x00000001U) /*!< Vref Enable bit*/
Kojto 119:aae6fcc7d9bb 3309 #define SYSCFG_CFGR3_VREF_OUT ((uint32_t)0x00000030U) /*!< Verf_ADC connection bit */
Kojto 119:aae6fcc7d9bb 3310 #define SYSCFG_CFGR3_VREF_OUT_0 ((uint32_t)0x00000010U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3311 #define SYSCFG_CFGR3_VREF_OUT_1 ((uint32_t)0x00000020U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3312 #define SYSCFG_CFGR3_ENBUF_VREFINT_ADC ((uint32_t)0x00000100U) /*!< VREFINT reference for ADC enable bit */
Kojto 119:aae6fcc7d9bb 3313 #define SYSCFG_CFGR3_ENBUF_SENSOR_ADC ((uint32_t)0x00000200U) /*!< Sensor reference for ADC enable bit */
Kojto 119:aae6fcc7d9bb 3314 #define SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP ((uint32_t)0x00001000U) /*!< VREFINT reference for comparator 2 enable bit */
Kojto 119:aae6fcc7d9bb 3315 #define SYSCFG_CFGR3_ENREF_HSI48 ((uint32_t)0x00002000U) /*!< VREFINT reference or 48 MHz RC oscillator enable bit */
Kojto 119:aae6fcc7d9bb 3316 #define SYSCFG_CFGR3_REF_HSI48_RDYF ((uint32_t)0x04000000U) /*!< VREFINT for 48 MHz RC oscillator ready flag */
Kojto 119:aae6fcc7d9bb 3317 #define SYSCFG_CFGR3_SENSOR_ADC_RDYF ((uint32_t)0x08000000U) /*!< Sensor for ADC ready flag */
Kojto 119:aae6fcc7d9bb 3318 #define SYSCFG_CFGR3_VREFINT_ADC_RDYF ((uint32_t)0x10000000U) /*!< VREFINT for ADC ready flag */
Kojto 119:aae6fcc7d9bb 3319 #define SYSCFG_CFGR3_VREFINT_COMP_RDYF ((uint32_t)0x20000000U) /*!< VREFINT for comparator ready flag */
Kojto 119:aae6fcc7d9bb 3320 #define SYSCFG_CFGR3_VREFINT_RDYF ((uint32_t)0x40000000U) /*!< VREFINT ready flag */
Kojto 119:aae6fcc7d9bb 3321 #define SYSCFG_CFGR3_REF_LOCK ((uint32_t)0x80000000U) /*!< CFGR3 lock bit */
Kojto 119:aae6fcc7d9bb 3322
Kojto 119:aae6fcc7d9bb 3323 /* Legacy defines */
Kojto 99:dbbf35b96557 3324
Kojto 99:dbbf35b96557 3325 #define SYSCFG_CFGR3_EN_BGAP SYSCFG_CFGR3_EN_VREFINT
Kojto 99:dbbf35b96557 3326 #define SYSCFG_CFGR3_ENBUF_BGAP_ADC SYSCFG_CFGR3_ENBUF_VREFINT_ADC
Kojto 99:dbbf35b96557 3327 #define SYSCFG_CFGR3_ENBUFLP_BGAP_COMP SYSCFG_CFGR3_ENBUFLP_VREFINT_COMP
Kojto 99:dbbf35b96557 3328 #define SYSCFG_CFGR3_ENREF_RC48MHz SYSCFG_CFGR3_ENREF_HSI48
Kojto 99:dbbf35b96557 3329 #define SYSCFG_CFGR3_REF_RC48MHz_RDYF SYSCFG_CFGR3_REF_HSI48_RDYF
Kojto 99:dbbf35b96557 3330 #define SYSCFG_VREFINT_ADC_RDYF SYSCFG_CFGR3_VREFINT_ADC_RDYF
Kojto 99:dbbf35b96557 3331
Kojto 99:dbbf35b96557 3332 /******************************************************************************/
Kojto 99:dbbf35b96557 3333 /* */
Kojto 99:dbbf35b96557 3334 /* Timers (TIM) */
Kojto 99:dbbf35b96557 3335 /* */
Kojto 99:dbbf35b96557 3336 /******************************************************************************/
Kojto 119:aae6fcc7d9bb 3337 /*
Kojto 119:aae6fcc7d9bb 3338 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
Kojto 119:aae6fcc7d9bb 3339 */
Kojto 119:aae6fcc7d9bb 3340 #if defined (STM32L071xx) || defined (STM32L072xx) || defined (STM32L073xx) \
Kojto 119:aae6fcc7d9bb 3341 || defined (STM32L081xx) || defined (STM32L082xx) || defined (STM32L083xx)
Kojto 119:aae6fcc7d9bb 3342 #define TIM_TIM2_REMAP_HSI_SUPPORT /*!<Support remap HSI on TIM2 */
Kojto 119:aae6fcc7d9bb 3343 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
Kojto 119:aae6fcc7d9bb 3344 #else
Kojto 119:aae6fcc7d9bb 3345 #define TIM_TIM2_REMAP_HSI48_SUPPORT /*!<Support remap HSI48 on TIM2 */
Kojto 119:aae6fcc7d9bb 3346 #endif
Kojto 119:aae6fcc7d9bb 3347
Kojto 99:dbbf35b96557 3348 /******************* Bit definition for TIM_CR1 register ********************/
Kojto 119:aae6fcc7d9bb 3349 #define TIM_CR1_CEN ((uint32_t)0x00000001U) /*!<Counter enable */
Kojto 119:aae6fcc7d9bb 3350 #define TIM_CR1_UDIS ((uint32_t)0x00000002U) /*!<Update disable */
Kojto 119:aae6fcc7d9bb 3351 #define TIM_CR1_URS ((uint32_t)0x00000004U) /*!<Update request source */
Kojto 119:aae6fcc7d9bb 3352 #define TIM_CR1_OPM ((uint32_t)0x00000008U) /*!<One pulse mode */
Kojto 119:aae6fcc7d9bb 3353 #define TIM_CR1_DIR ((uint32_t)0x00000010U) /*!<Direction */
Kojto 119:aae6fcc7d9bb 3354
Kojto 119:aae6fcc7d9bb 3355 #define TIM_CR1_CMS ((uint32_t)0x00000060U) /*!<CMS[1:0] bits (Center-aligned mode selection) */
Kojto 119:aae6fcc7d9bb 3356 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3357 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3358
Kojto 119:aae6fcc7d9bb 3359 #define TIM_CR1_ARPE ((uint32_t)0x00000080U) /*!<Auto-reload preload enable */
Kojto 119:aae6fcc7d9bb 3360
Kojto 119:aae6fcc7d9bb 3361 #define TIM_CR1_CKD ((uint32_t)0x00000300U) /*!<CKD[1:0] bits (clock division) */
Kojto 119:aae6fcc7d9bb 3362 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3363 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 99:dbbf35b96557 3364
Kojto 99:dbbf35b96557 3365 /******************* Bit definition for TIM_CR2 register ********************/
Kojto 119:aae6fcc7d9bb 3366 #define TIM_CR2_CCDS ((uint32_t)0x00000008U) /*!<Capture/Compare DMA Selection */
Kojto 119:aae6fcc7d9bb 3367
Kojto 119:aae6fcc7d9bb 3368 #define TIM_CR2_MMS ((uint32_t)0x00000070U) /*!<MMS[2:0] bits (Master Mode Selection) */
Kojto 119:aae6fcc7d9bb 3369 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3370 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3371 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3372
Kojto 119:aae6fcc7d9bb 3373 #define TIM_CR2_TI1S ((uint32_t)0x00000080U) /*!<TI1 Selection */
Kojto 99:dbbf35b96557 3374
Kojto 99:dbbf35b96557 3375 /******************* Bit definition for TIM_SMCR register *******************/
Kojto 119:aae6fcc7d9bb 3376 #define TIM_SMCR_SMS ((uint32_t)0x00000007U) /*!<SMS[2:0] bits (Slave mode selection) */
Kojto 119:aae6fcc7d9bb 3377 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3378 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3379 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3380
Kojto 119:aae6fcc7d9bb 3381 #define TIM_SMCR_OCCS ((uint32_t)0x00000008U) /*!< OCREF clear selection */
Kojto 119:aae6fcc7d9bb 3382
Kojto 119:aae6fcc7d9bb 3383 #define TIM_SMCR_TS ((uint32_t)0x00000070U) /*!<TS[2:0] bits (Trigger selection) */
Kojto 119:aae6fcc7d9bb 3384 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3385 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3386 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3387
Kojto 119:aae6fcc7d9bb 3388 #define TIM_SMCR_MSM ((uint32_t)0x00000080U) /*!<Master/slave mode */
Kojto 119:aae6fcc7d9bb 3389
Kojto 119:aae6fcc7d9bb 3390 #define TIM_SMCR_ETF ((uint32_t)0x00000F00U) /*!<ETF[3:0] bits (External trigger filter) */
Kojto 119:aae6fcc7d9bb 3391 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3392 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3393 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3394 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
Kojto 119:aae6fcc7d9bb 3395
Kojto 119:aae6fcc7d9bb 3396 #define TIM_SMCR_ETPS ((uint32_t)0x00003000U) /*!<ETPS[1:0] bits (External trigger prescaler) */
Kojto 119:aae6fcc7d9bb 3397 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3398 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3399
Kojto 119:aae6fcc7d9bb 3400 #define TIM_SMCR_ECE ((uint32_t)0x00004000U) /*!<External clock enable */
Kojto 119:aae6fcc7d9bb 3401 #define TIM_SMCR_ETP ((uint32_t)0x00008000U) /*!<External trigger polarity */
Kojto 99:dbbf35b96557 3402
Kojto 99:dbbf35b96557 3403 /******************* Bit definition for TIM_DIER register *******************/
Kojto 119:aae6fcc7d9bb 3404 #define TIM_DIER_UIE ((uint32_t)0x00000001U) /*!<Update interrupt enable */
Kojto 119:aae6fcc7d9bb 3405 #define TIM_DIER_CC1IE ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt enable */
Kojto 119:aae6fcc7d9bb 3406 #define TIM_DIER_CC2IE ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt enable */
Kojto 119:aae6fcc7d9bb 3407 #define TIM_DIER_CC3IE ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt enable */
Kojto 119:aae6fcc7d9bb 3408 #define TIM_DIER_CC4IE ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt enable */
Kojto 119:aae6fcc7d9bb 3409 #define TIM_DIER_TIE ((uint32_t)0x00000040U) /*!<Trigger interrupt enable */
Kojto 119:aae6fcc7d9bb 3410 #define TIM_DIER_UDE ((uint32_t)0x00000100U) /*!<Update DMA request enable */
Kojto 119:aae6fcc7d9bb 3411 #define TIM_DIER_CC1DE ((uint32_t)0x00000200U) /*!<Capture/Compare 1 DMA request enable */
Kojto 119:aae6fcc7d9bb 3412 #define TIM_DIER_CC2DE ((uint32_t)0x00000400U) /*!<Capture/Compare 2 DMA request enable */
Kojto 119:aae6fcc7d9bb 3413 #define TIM_DIER_CC3DE ((uint32_t)0x00000800U) /*!<Capture/Compare 3 DMA request enable */
Kojto 119:aae6fcc7d9bb 3414 #define TIM_DIER_CC4DE ((uint32_t)0x00001000U) /*!<Capture/Compare 4 DMA request enable */
Kojto 119:aae6fcc7d9bb 3415 #define TIM_DIER_TDE ((uint32_t)0x00004000U) /*!<Trigger DMA request enable */
Kojto 99:dbbf35b96557 3416
Kojto 99:dbbf35b96557 3417 /******************** Bit definition for TIM_SR register ********************/
Kojto 119:aae6fcc7d9bb 3418 #define TIM_SR_UIF ((uint32_t)0x00000001U) /*!<Update interrupt Flag */
Kojto 119:aae6fcc7d9bb 3419 #define TIM_SR_CC1IF ((uint32_t)0x00000002U) /*!<Capture/Compare 1 interrupt Flag */
Kojto 119:aae6fcc7d9bb 3420 #define TIM_SR_CC2IF ((uint32_t)0x00000004U) /*!<Capture/Compare 2 interrupt Flag */
Kojto 119:aae6fcc7d9bb 3421 #define TIM_SR_CC3IF ((uint32_t)0x00000008U) /*!<Capture/Compare 3 interrupt Flag */
Kojto 119:aae6fcc7d9bb 3422 #define TIM_SR_CC4IF ((uint32_t)0x00000010U) /*!<Capture/Compare 4 interrupt Flag */
Kojto 119:aae6fcc7d9bb 3423 #define TIM_SR_TIF ((uint32_t)0x00000040U) /*!<Trigger interrupt Flag */
Kojto 119:aae6fcc7d9bb 3424 #define TIM_SR_CC1OF ((uint32_t)0x00000200U) /*!<Capture/Compare 1 Overcapture Flag */
Kojto 119:aae6fcc7d9bb 3425 #define TIM_SR_CC2OF ((uint32_t)0x00000400U) /*!<Capture/Compare 2 Overcapture Flag */
Kojto 119:aae6fcc7d9bb 3426 #define TIM_SR_CC3OF ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Overcapture Flag */
Kojto 119:aae6fcc7d9bb 3427 #define TIM_SR_CC4OF ((uint32_t)0x00001000U) /*!<Capture/Compare 4 Overcapture Flag */
Kojto 99:dbbf35b96557 3428
Kojto 99:dbbf35b96557 3429 /******************* Bit definition for TIM_EGR register ********************/
Kojto 119:aae6fcc7d9bb 3430 #define TIM_EGR_UG ((uint32_t)0x00000001U) /*!<Update Generation */
Kojto 119:aae6fcc7d9bb 3431 #define TIM_EGR_CC1G ((uint32_t)0x00000002U) /*!<Capture/Compare 1 Generation */
Kojto 119:aae6fcc7d9bb 3432 #define TIM_EGR_CC2G ((uint32_t)0x00000004U) /*!<Capture/Compare 2 Generation */
Kojto 119:aae6fcc7d9bb 3433 #define TIM_EGR_CC3G ((uint32_t)0x00000008U) /*!<Capture/Compare 3 Generation */
Kojto 119:aae6fcc7d9bb 3434 #define TIM_EGR_CC4G ((uint32_t)0x00000010U) /*!<Capture/Compare 4 Generation */
Kojto 119:aae6fcc7d9bb 3435 #define TIM_EGR_TG ((uint32_t)0x00000040U) /*!<Trigger Generation */
Kojto 99:dbbf35b96557 3436
Kojto 99:dbbf35b96557 3437 /****************** Bit definition for TIM_CCMR1 register *******************/
Kojto 119:aae6fcc7d9bb 3438 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003U) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
Kojto 119:aae6fcc7d9bb 3439 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3440 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3441
Kojto 119:aae6fcc7d9bb 3442 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004U) /*!<Output Compare 1 Fast enable */
Kojto 119:aae6fcc7d9bb 3443 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008U) /*!<Output Compare 1 Preload enable */
Kojto 119:aae6fcc7d9bb 3444
Kojto 119:aae6fcc7d9bb 3445 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070U) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
Kojto 119:aae6fcc7d9bb 3446 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3447 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3448 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3449
Kojto 119:aae6fcc7d9bb 3450 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080U) /*!<Output Compare 1Clear Enable */
Kojto 119:aae6fcc7d9bb 3451
Kojto 119:aae6fcc7d9bb 3452 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300U) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
Kojto 119:aae6fcc7d9bb 3453 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3454 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3455
Kojto 119:aae6fcc7d9bb 3456 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400U) /*!<Output Compare 2 Fast enable */
Kojto 119:aae6fcc7d9bb 3457 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800U) /*!<Output Compare 2 Preload enable */
Kojto 119:aae6fcc7d9bb 3458
Kojto 119:aae6fcc7d9bb 3459 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000U) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
Kojto 119:aae6fcc7d9bb 3460 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3461 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3462 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3463
Kojto 119:aae6fcc7d9bb 3464 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000U) /*!<Output Compare 2 Clear Enable */
Kojto 99:dbbf35b96557 3465
Kojto 99:dbbf35b96557 3466 /*----------------------------------------------------------------------------*/
Kojto 99:dbbf35b96557 3467
Kojto 119:aae6fcc7d9bb 3468 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000CU) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
Kojto 119:aae6fcc7d9bb 3469 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3470 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3471
Kojto 119:aae6fcc7d9bb 3472 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0U) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
Kojto 119:aae6fcc7d9bb 3473 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3474 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3475 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3476 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
Kojto 119:aae6fcc7d9bb 3477
Kojto 119:aae6fcc7d9bb 3478 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00U) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
Kojto 119:aae6fcc7d9bb 3479 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3480 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3481
Kojto 119:aae6fcc7d9bb 3482 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000U) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
Kojto 119:aae6fcc7d9bb 3483 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3484 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3485 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3486 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
Kojto 99:dbbf35b96557 3487
Kojto 99:dbbf35b96557 3488 /****************** Bit definition for TIM_CCMR2 register *******************/
Kojto 119:aae6fcc7d9bb 3489 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003U) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
Kojto 119:aae6fcc7d9bb 3490 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3491 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3492
Kojto 119:aae6fcc7d9bb 3493 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004U) /*!<Output Compare 3 Fast enable */
Kojto 119:aae6fcc7d9bb 3494 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008U) /*!<Output Compare 3 Preload enable */
Kojto 119:aae6fcc7d9bb 3495
Kojto 119:aae6fcc7d9bb 3496 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070U) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
Kojto 119:aae6fcc7d9bb 3497 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3498 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3499 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3500
Kojto 119:aae6fcc7d9bb 3501 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080U) /*!<Output Compare 3 Clear Enable */
Kojto 119:aae6fcc7d9bb 3502
Kojto 119:aae6fcc7d9bb 3503 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300U) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
Kojto 119:aae6fcc7d9bb 3504 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3505 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3506
Kojto 119:aae6fcc7d9bb 3507 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400U) /*!<Output Compare 4 Fast enable */
Kojto 119:aae6fcc7d9bb 3508 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800U) /*!<Output Compare 4 Preload enable */
Kojto 119:aae6fcc7d9bb 3509
Kojto 119:aae6fcc7d9bb 3510 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000U) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
Kojto 119:aae6fcc7d9bb 3511 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3512 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3513 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3514
Kojto 119:aae6fcc7d9bb 3515 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000U) /*!<Output Compare 4 Clear Enable */
Kojto 99:dbbf35b96557 3516
Kojto 99:dbbf35b96557 3517 /*----------------------------------------------------------------------------*/
Kojto 99:dbbf35b96557 3518
Kojto 119:aae6fcc7d9bb 3519 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000CU) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
Kojto 119:aae6fcc7d9bb 3520 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3521 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3522
Kojto 119:aae6fcc7d9bb 3523 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0U) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
Kojto 119:aae6fcc7d9bb 3524 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3525 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3526 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3527 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080U) /*!<Bit 3 */
Kojto 119:aae6fcc7d9bb 3528
Kojto 119:aae6fcc7d9bb 3529 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00U) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
Kojto 119:aae6fcc7d9bb 3530 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3531 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3532
Kojto 119:aae6fcc7d9bb 3533 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000U) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
Kojto 119:aae6fcc7d9bb 3534 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3535 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3536 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3537 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000U) /*!<Bit 3 */
Kojto 99:dbbf35b96557 3538
Kojto 99:dbbf35b96557 3539 /******************* Bit definition for TIM_CCER register *******************/
Kojto 119:aae6fcc7d9bb 3540 #define TIM_CCER_CC1E ((uint32_t)0x00000001U) /*!<Capture/Compare 1 output enable */
Kojto 119:aae6fcc7d9bb 3541 #define TIM_CCER_CC1P ((uint32_t)0x00000002U) /*!<Capture/Compare 1 output Polarity */
Kojto 119:aae6fcc7d9bb 3542 #define TIM_CCER_CC1NP ((uint32_t)0x00000008U) /*!<Capture/Compare 1 Complementary output Polarity */
Kojto 119:aae6fcc7d9bb 3543 #define TIM_CCER_CC2E ((uint32_t)0x00000010U) /*!<Capture/Compare 2 output enable */
Kojto 119:aae6fcc7d9bb 3544 #define TIM_CCER_CC2P ((uint32_t)0x00000020U) /*!<Capture/Compare 2 output Polarity */
Kojto 119:aae6fcc7d9bb 3545 #define TIM_CCER_CC2NP ((uint32_t)0x00000080U) /*!<Capture/Compare 2 Complementary output Polarity */
Kojto 119:aae6fcc7d9bb 3546 #define TIM_CCER_CC3E ((uint32_t)0x00000100U) /*!<Capture/Compare 3 output enable */
Kojto 119:aae6fcc7d9bb 3547 #define TIM_CCER_CC3P ((uint32_t)0x00000200U) /*!<Capture/Compare 3 output Polarity */
Kojto 119:aae6fcc7d9bb 3548 #define TIM_CCER_CC3NP ((uint32_t)0x00000800U) /*!<Capture/Compare 3 Complementary output Polarity */
Kojto 119:aae6fcc7d9bb 3549 #define TIM_CCER_CC4E ((uint32_t)0x00001000U) /*!<Capture/Compare 4 output enable */
Kojto 119:aae6fcc7d9bb 3550 #define TIM_CCER_CC4P ((uint32_t)0x00002000U) /*!<Capture/Compare 4 output Polarity */
Kojto 119:aae6fcc7d9bb 3551 #define TIM_CCER_CC4NP ((uint32_t)0x00008000U) /*!<Capture/Compare 4 Complementary output Polarity */
Kojto 99:dbbf35b96557 3552
Kojto 99:dbbf35b96557 3553 /******************* Bit definition for TIM_CNT register ********************/
Kojto 119:aae6fcc7d9bb 3554 #define TIM_CNT_CNT ((uint32_t)0x0000FFFFU) /*!<Counter Value */
Kojto 99:dbbf35b96557 3555
Kojto 99:dbbf35b96557 3556 /******************* Bit definition for TIM_PSC register ********************/
Kojto 119:aae6fcc7d9bb 3557 #define TIM_PSC_PSC ((uint32_t)0x0000FFFFU) /*!<Prescaler Value */
Kojto 99:dbbf35b96557 3558
Kojto 99:dbbf35b96557 3559 /******************* Bit definition for TIM_ARR register ********************/
Kojto 119:aae6fcc7d9bb 3560 #define TIM_ARR_ARR ((uint32_t)0x0000FFFFU) /*!<actual auto-reload Value */
Kojto 99:dbbf35b96557 3561
Kojto 99:dbbf35b96557 3562 /******************* Bit definition for TIM_CCR1 register *******************/
Kojto 119:aae6fcc7d9bb 3563 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 1 Value */
Kojto 99:dbbf35b96557 3564
Kojto 99:dbbf35b96557 3565 /******************* Bit definition for TIM_CCR2 register *******************/
Kojto 119:aae6fcc7d9bb 3566 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 2 Value */
Kojto 99:dbbf35b96557 3567
Kojto 99:dbbf35b96557 3568 /******************* Bit definition for TIM_CCR3 register *******************/
Kojto 119:aae6fcc7d9bb 3569 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 3 Value */
Kojto 99:dbbf35b96557 3570
Kojto 99:dbbf35b96557 3571 /******************* Bit definition for TIM_CCR4 register *******************/
Kojto 119:aae6fcc7d9bb 3572 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFFU) /*!<Capture/Compare 4 Value */
Kojto 99:dbbf35b96557 3573
Kojto 99:dbbf35b96557 3574 /******************* Bit definition for TIM_DCR register ********************/
Kojto 119:aae6fcc7d9bb 3575 #define TIM_DCR_DBA ((uint32_t)0x0000001FU) /*!<DBA[4:0] bits (DMA Base Address) */
Kojto 119:aae6fcc7d9bb 3576 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3577 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3578 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3579 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008U) /*!<Bit 3 */
Kojto 119:aae6fcc7d9bb 3580 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010U) /*!<Bit 4 */
Kojto 119:aae6fcc7d9bb 3581
Kojto 119:aae6fcc7d9bb 3582 #define TIM_DCR_DBL ((uint32_t)0x00001F00U) /*!<DBL[4:0] bits (DMA Burst Length) */
Kojto 119:aae6fcc7d9bb 3583 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3584 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3585 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3586 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800U) /*!<Bit 3 */
Kojto 119:aae6fcc7d9bb 3587 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000U) /*!<Bit 4 */
Kojto 99:dbbf35b96557 3588
Kojto 99:dbbf35b96557 3589 /******************* Bit definition for TIM_DMAR register *******************/
Kojto 119:aae6fcc7d9bb 3590 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFFU) /*!<DMA register for burst accesses */
Kojto 99:dbbf35b96557 3591
Kojto 99:dbbf35b96557 3592 /******************* Bit definition for TIM_OR register *********************/
Kojto 119:aae6fcc7d9bb 3593 #define TIM2_OR_ETR_RMP ((uint32_t)0x00000007U) /*!<ETR_RMP[1:0] bits (TIM2 ETR remap) */
Kojto 119:aae6fcc7d9bb 3594 #define TIM2_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3595 #define TIM2_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3596 #define TIM2_OR_ETR_RMP_2 ((uint32_t)0x00000004U) /*!<Bit 2 */
Kojto 99:dbbf35b96557 3597 #define TIM2_OR_TI4_RMP ((uint32_t)0x0000018) /*!<TI4_RMP[1:0] bits (TIM2 Input 4 remap) */
Kojto 119:aae6fcc7d9bb 3598 #define TIM2_OR_TI4_RMP_0 ((uint32_t)0x00000008U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3599 #define TIM2_OR_TI4_RMP_1 ((uint32_t)0x00000010U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3600
Kojto 119:aae6fcc7d9bb 3601 #define TIM21_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM21 ETR remap) */
Kojto 119:aae6fcc7d9bb 3602 #define TIM21_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3603 #define TIM21_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3604 #define TIM21_OR_TI1_RMP ((uint32_t)0x0000001CU) /*!<TI1_RMP[2:0] bits (TIM21 Input 1 remap) */
Kojto 119:aae6fcc7d9bb 3605 #define TIM21_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3606 #define TIM21_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3607 #define TIM21_OR_TI1_RMP_2 ((uint32_t)0x00000010U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3608 #define TIM21_OR_TI2_RMP ((uint32_t)0x00000020U) /*!<TI2_RMP bit (TIM21 Input 2 remap) */
Kojto 119:aae6fcc7d9bb 3609
Kojto 119:aae6fcc7d9bb 3610 #define TIM22_OR_ETR_RMP ((uint32_t)0x00000003U) /*!<ETR_RMP[1:0] bits (TIM22 ETR remap) */
Kojto 119:aae6fcc7d9bb 3611 #define TIM22_OR_ETR_RMP_0 ((uint32_t)0x00000001U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3612 #define TIM22_OR_ETR_RMP_1 ((uint32_t)0x00000002U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3613 #define TIM22_OR_TI1_RMP ((uint32_t)0x0000000CU) /*!<TI1_RMP[2:0] bits (TIM22 Input 1 remap) */
Kojto 119:aae6fcc7d9bb 3614 #define TIM22_OR_TI1_RMP_0 ((uint32_t)0x00000004U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3615 #define TIM22_OR_TI1_RMP_1 ((uint32_t)0x00000008U) /*!<Bit 1 */
Kojto 99:dbbf35b96557 3616
Kojto 99:dbbf35b96557 3617
Kojto 99:dbbf35b96557 3618 /******************************************************************************/
Kojto 99:dbbf35b96557 3619 /* */
Kojto 99:dbbf35b96557 3620 /* Touch Sensing Controller (TSC) */
Kojto 99:dbbf35b96557 3621 /* */
Kojto 99:dbbf35b96557 3622 /******************************************************************************/
Kojto 99:dbbf35b96557 3623 /******************* Bit definition for TSC_CR register *********************/
Kojto 119:aae6fcc7d9bb 3624 #define TSC_CR_TSCE ((uint32_t)0x00000001U) /*!<Touch sensing controller enable */
Kojto 119:aae6fcc7d9bb 3625 #define TSC_CR_START ((uint32_t)0x00000002U) /*!<Start acquisition */
Kojto 119:aae6fcc7d9bb 3626 #define TSC_CR_AM ((uint32_t)0x00000004U) /*!<Acquisition mode */
Kojto 119:aae6fcc7d9bb 3627 #define TSC_CR_SYNCPOL ((uint32_t)0x00000008U) /*!<Synchronization pin polarity */
Kojto 119:aae6fcc7d9bb 3628 #define TSC_CR_IODEF ((uint32_t)0x00000010U) /*!<IO default mode */
Kojto 119:aae6fcc7d9bb 3629
Kojto 119:aae6fcc7d9bb 3630 #define TSC_CR_MCV ((uint32_t)0x000000E0U) /*!<MCV[2:0] bits (Max Count Value) */
Kojto 119:aae6fcc7d9bb 3631 #define TSC_CR_MCV_0 ((uint32_t)0x00000020U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3632 #define TSC_CR_MCV_1 ((uint32_t)0x00000040U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3633 #define TSC_CR_MCV_2 ((uint32_t)0x00000080U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3634
Kojto 119:aae6fcc7d9bb 3635 #define TSC_CR_PGPSC ((uint32_t)0x00007000U) /*!<PGPSC[2:0] bits (Pulse Generator Prescaler) */
Kojto 119:aae6fcc7d9bb 3636 #define TSC_CR_PGPSC_0 ((uint32_t)0x00001000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3637 #define TSC_CR_PGPSC_1 ((uint32_t)0x00002000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3638 #define TSC_CR_PGPSC_2 ((uint32_t)0x00004000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3639
Kojto 119:aae6fcc7d9bb 3640 #define TSC_CR_SSPSC ((uint32_t)0x00008000U) /*!<Spread Spectrum Prescaler */
Kojto 119:aae6fcc7d9bb 3641 #define TSC_CR_SSE ((uint32_t)0x00010000U) /*!<Spread Spectrum Enable */
Kojto 119:aae6fcc7d9bb 3642
Kojto 119:aae6fcc7d9bb 3643 #define TSC_CR_SSD ((uint32_t)0x00FE0000U) /*!<SSD[6:0] bits (Spread Spectrum Deviation) */
Kojto 119:aae6fcc7d9bb 3644 #define TSC_CR_SSD_0 ((uint32_t)0x00020000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3645 #define TSC_CR_SSD_1 ((uint32_t)0x00040000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3646 #define TSC_CR_SSD_2 ((uint32_t)0x00080000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3647 #define TSC_CR_SSD_3 ((uint32_t)0x00100000U) /*!<Bit 3 */
Kojto 119:aae6fcc7d9bb 3648 #define TSC_CR_SSD_4 ((uint32_t)0x00200000U) /*!<Bit 4 */
Kojto 119:aae6fcc7d9bb 3649 #define TSC_CR_SSD_5 ((uint32_t)0x00400000U) /*!<Bit 5 */
Kojto 119:aae6fcc7d9bb 3650 #define TSC_CR_SSD_6 ((uint32_t)0x00800000U) /*!<Bit 6 */
Kojto 119:aae6fcc7d9bb 3651
Kojto 119:aae6fcc7d9bb 3652 #define TSC_CR_CTPL ((uint32_t)0x0F000000U) /*!<CTPL[3:0] bits (Charge Transfer pulse low) */
Kojto 119:aae6fcc7d9bb 3653 #define TSC_CR_CTPL_0 ((uint32_t)0x01000000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3654 #define TSC_CR_CTPL_1 ((uint32_t)0x02000000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3655 #define TSC_CR_CTPL_2 ((uint32_t)0x04000000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3656 #define TSC_CR_CTPL_3 ((uint32_t)0x08000000U) /*!<Bit 3 */
Kojto 119:aae6fcc7d9bb 3657
Kojto 119:aae6fcc7d9bb 3658 #define TSC_CR_CTPH ((uint32_t)0xF0000000U) /*!<CTPH[3:0] bits (Charge Transfer pulse high) */
Kojto 119:aae6fcc7d9bb 3659 #define TSC_CR_CTPH_0 ((uint32_t)0x10000000U) /*!<Bit 0 */
Kojto 119:aae6fcc7d9bb 3660 #define TSC_CR_CTPH_1 ((uint32_t)0x20000000U) /*!<Bit 1 */
Kojto 119:aae6fcc7d9bb 3661 #define TSC_CR_CTPH_2 ((uint32_t)0x40000000U) /*!<Bit 2 */
Kojto 119:aae6fcc7d9bb 3662 #define TSC_CR_CTPH_3 ((uint32_t)0x80000000U) /*!<Bit 3 */
Kojto 99:dbbf35b96557 3663
Kojto 99:dbbf35b96557 3664 /******************* Bit definition for TSC_IER register ********************/
Kojto 119:aae6fcc7d9bb 3665 #define TSC_IER_EOAIE ((uint32_t)0x00000001U) /*!<End of acquisition interrupt enable */
Kojto 119:aae6fcc7d9bb 3666 #define TSC_IER_MCEIE ((uint32_t)0x00000002U) /*!<Max count error interrupt enable */
Kojto 99:dbbf35b96557 3667
Kojto 99:dbbf35b96557 3668 /******************* Bit definition for TSC_ICR register ********************/
Kojto 119:aae6fcc7d9bb 3669 #define TSC_ICR_EOAIC ((uint32_t)0x00000001U) /*!<End of acquisition interrupt clear */
Kojto 119:aae6fcc7d9bb 3670 #define TSC_ICR_MCEIC ((uint32_t)0x00000002U) /*!<Max count error interrupt clear */
Kojto 99:dbbf35b96557 3671
Kojto 99:dbbf35b96557 3672 /******************* Bit definition for TSC_ISR register ********************/
Kojto 119:aae6fcc7d9bb 3673 #define TSC_ISR_EOAF ((uint32_t)0x00000001U) /*!<End of acquisition flag */
Kojto 119:aae6fcc7d9bb 3674 #define TSC_ISR_MCEF ((uint32_t)0x00000002U) /*!<Max count error flag */
Kojto 99:dbbf35b96557 3675
Kojto 99:dbbf35b96557 3676 /******************* Bit definition for TSC_IOHCR register ******************/
Kojto 119:aae6fcc7d9bb 3677 #define TSC_IOHCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3678 #define TSC_IOHCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3679 #define TSC_IOHCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3680 #define TSC_IOHCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3681 #define TSC_IOHCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3682 #define TSC_IOHCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3683 #define TSC_IOHCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3684 #define TSC_IOHCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3685 #define TSC_IOHCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3686 #define TSC_IOHCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3687 #define TSC_IOHCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3688 #define TSC_IOHCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3689 #define TSC_IOHCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3690 #define TSC_IOHCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3691 #define TSC_IOHCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3692 #define TSC_IOHCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3693 #define TSC_IOHCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3694 #define TSC_IOHCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3695 #define TSC_IOHCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3696 #define TSC_IOHCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3697 #define TSC_IOHCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3698 #define TSC_IOHCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3699 #define TSC_IOHCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3700 #define TSC_IOHCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3701 #define TSC_IOHCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3702 #define TSC_IOHCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3703 #define TSC_IOHCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3704 #define TSC_IOHCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3705 #define TSC_IOHCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3706 #define TSC_IOHCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3707 #define TSC_IOHCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 schmitt trigger hysteresis mode */
Kojto 119:aae6fcc7d9bb 3708 #define TSC_IOHCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 schmitt trigger hysteresis mode */
Kojto 99:dbbf35b96557 3709
Kojto 99:dbbf35b96557 3710 /******************* Bit definition for TSC_IOASCR register *****************/
Kojto 119:aae6fcc7d9bb 3711 #define TSC_IOASCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3712 #define TSC_IOASCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3713 #define TSC_IOASCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3714 #define TSC_IOASCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 analog switch enable */
Kojto 119:aae6fcc7d9bb 3715 #define TSC_IOASCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3716 #define TSC_IOASCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3717 #define TSC_IOASCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3718 #define TSC_IOASCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 analog switch enable */
Kojto 119:aae6fcc7d9bb 3719 #define TSC_IOASCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3720 #define TSC_IOASCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3721 #define TSC_IOASCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3722 #define TSC_IOASCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 analog switch enable */
Kojto 119:aae6fcc7d9bb 3723 #define TSC_IOASCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3724 #define TSC_IOASCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3725 #define TSC_IOASCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3726 #define TSC_IOASCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 analog switch enable */
Kojto 119:aae6fcc7d9bb 3727 #define TSC_IOASCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3728 #define TSC_IOASCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3729 #define TSC_IOASCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3730 #define TSC_IOASCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 analog switch enable */
Kojto 119:aae6fcc7d9bb 3731 #define TSC_IOASCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3732 #define TSC_IOASCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3733 #define TSC_IOASCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3734 #define TSC_IOASCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 analog switch enable */
Kojto 119:aae6fcc7d9bb 3735 #define TSC_IOASCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3736 #define TSC_IOASCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3737 #define TSC_IOASCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3738 #define TSC_IOASCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 analog switch enable */
Kojto 119:aae6fcc7d9bb 3739 #define TSC_IOASCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 analog switch enable */
Kojto 119:aae6fcc7d9bb 3740 #define TSC_IOASCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 analog switch enable */
Kojto 119:aae6fcc7d9bb 3741 #define TSC_IOASCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 analog switch enable */
Kojto 119:aae6fcc7d9bb 3742 #define TSC_IOASCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 analog switch enable */
Kojto 99:dbbf35b96557 3743
Kojto 99:dbbf35b96557 3744 /******************* Bit definition for TSC_IOSCR register ******************/
Kojto 119:aae6fcc7d9bb 3745 #define TSC_IOSCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3746 #define TSC_IOSCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3747 #define TSC_IOSCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3748 #define TSC_IOSCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 sampling mode */
Kojto 119:aae6fcc7d9bb 3749 #define TSC_IOSCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3750 #define TSC_IOSCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3751 #define TSC_IOSCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3752 #define TSC_IOSCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 sampling mode */
Kojto 119:aae6fcc7d9bb 3753 #define TSC_IOSCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3754 #define TSC_IOSCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3755 #define TSC_IOSCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3756 #define TSC_IOSCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 sampling mode */
Kojto 119:aae6fcc7d9bb 3757 #define TSC_IOSCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3758 #define TSC_IOSCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3759 #define TSC_IOSCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3760 #define TSC_IOSCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 sampling mode */
Kojto 119:aae6fcc7d9bb 3761 #define TSC_IOSCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3762 #define TSC_IOSCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3763 #define TSC_IOSCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3764 #define TSC_IOSCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 sampling mode */
Kojto 119:aae6fcc7d9bb 3765 #define TSC_IOSCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3766 #define TSC_IOSCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3767 #define TSC_IOSCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3768 #define TSC_IOSCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 sampling mode */
Kojto 119:aae6fcc7d9bb 3769 #define TSC_IOSCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3770 #define TSC_IOSCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3771 #define TSC_IOSCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3772 #define TSC_IOSCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 sampling mode */
Kojto 119:aae6fcc7d9bb 3773 #define TSC_IOSCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 sampling mode */
Kojto 119:aae6fcc7d9bb 3774 #define TSC_IOSCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 sampling mode */
Kojto 119:aae6fcc7d9bb 3775 #define TSC_IOSCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 sampling mode */
Kojto 119:aae6fcc7d9bb 3776 #define TSC_IOSCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 sampling mode */
Kojto 99:dbbf35b96557 3777
Kojto 99:dbbf35b96557 3778 /******************* Bit definition for TSC_IOCCR register ******************/
Kojto 119:aae6fcc7d9bb 3779 #define TSC_IOCCR_G1_IO1 ((uint32_t)0x00000001U) /*!<GROUP1_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3780 #define TSC_IOCCR_G1_IO2 ((uint32_t)0x00000002U) /*!<GROUP1_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3781 #define TSC_IOCCR_G1_IO3 ((uint32_t)0x00000004U) /*!<GROUP1_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3782 #define TSC_IOCCR_G1_IO4 ((uint32_t)0x00000008U) /*!<GROUP1_IO4 channel mode */
Kojto 119:aae6fcc7d9bb 3783 #define TSC_IOCCR_G2_IO1 ((uint32_t)0x00000010U) /*!<GROUP2_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3784 #define TSC_IOCCR_G2_IO2 ((uint32_t)0x00000020U) /*!<GROUP2_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3785 #define TSC_IOCCR_G2_IO3 ((uint32_t)0x00000040U) /*!<GROUP2_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3786 #define TSC_IOCCR_G2_IO4 ((uint32_t)0x00000080U) /*!<GROUP2_IO4 channel mode */
Kojto 119:aae6fcc7d9bb 3787 #define TSC_IOCCR_G3_IO1 ((uint32_t)0x00000100U) /*!<GROUP3_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3788 #define TSC_IOCCR_G3_IO2 ((uint32_t)0x00000200U) /*!<GROUP3_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3789 #define TSC_IOCCR_G3_IO3 ((uint32_t)0x00000400U) /*!<GROUP3_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3790 #define TSC_IOCCR_G3_IO4 ((uint32_t)0x00000800U) /*!<GROUP3_IO4 channel mode */
Kojto 119:aae6fcc7d9bb 3791 #define TSC_IOCCR_G4_IO1 ((uint32_t)0x00001000U) /*!<GROUP4_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3792 #define TSC_IOCCR_G4_IO2 ((uint32_t)0x00002000U) /*!<GROUP4_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3793 #define TSC_IOCCR_G4_IO3 ((uint32_t)0x00004000U) /*!<GROUP4_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3794 #define TSC_IOCCR_G4_IO4 ((uint32_t)0x00008000U) /*!<GROUP4_IO4 channel mode */
Kojto 119:aae6fcc7d9bb 3795 #define TSC_IOCCR_G5_IO1 ((uint32_t)0x00010000U) /*!<GROUP5_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3796 #define TSC_IOCCR_G5_IO2 ((uint32_t)0x00020000U) /*!<GROUP5_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3797 #define TSC_IOCCR_G5_IO3 ((uint32_t)0x00040000U) /*!<GROUP5_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3798 #define TSC_IOCCR_G5_IO4 ((uint32_t)0x00080000U) /*!<GROUP5_IO4 channel mode */
Kojto 119:aae6fcc7d9bb 3799 #define TSC_IOCCR_G6_IO1 ((uint32_t)0x00100000U) /*!<GROUP6_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3800 #define TSC_IOCCR_G6_IO2 ((uint32_t)0x00200000U) /*!<GROUP6_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3801 #define TSC_IOCCR_G6_IO3 ((uint32_t)0x00400000U) /*!<GROUP6_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3802 #define TSC_IOCCR_G6_IO4 ((uint32_t)0x00800000U) /*!<GROUP6_IO4 channel mode */
Kojto 119:aae6fcc7d9bb 3803 #define TSC_IOCCR_G7_IO1 ((uint32_t)0x01000000U) /*!<GROUP7_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3804 #define TSC_IOCCR_G7_IO2 ((uint32_t)0x02000000U) /*!<GROUP7_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3805 #define TSC_IOCCR_G7_IO3 ((uint32_t)0x04000000U) /*!<GROUP7_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3806 #define TSC_IOCCR_G7_IO4 ((uint32_t)0x08000000U) /*!<GROUP7_IO4 channel mode */
Kojto 119:aae6fcc7d9bb 3807 #define TSC_IOCCR_G8_IO1 ((uint32_t)0x10000000U) /*!<GROUP8_IO1 channel mode */
Kojto 119:aae6fcc7d9bb 3808 #define TSC_IOCCR_G8_IO2 ((uint32_t)0x20000000U) /*!<GROUP8_IO2 channel mode */
Kojto 119:aae6fcc7d9bb 3809 #define TSC_IOCCR_G8_IO3 ((uint32_t)0x40000000U) /*!<GROUP8_IO3 channel mode */
Kojto 119:aae6fcc7d9bb 3810 #define TSC_IOCCR_G8_IO4 ((uint32_t)0x80000000U) /*!<GROUP8_IO4 channel mode */
Kojto 99:dbbf35b96557 3811
Kojto 99:dbbf35b96557 3812 /******************* Bit definition for TSC_IOGCSR register *****************/
Kojto 119:aae6fcc7d9bb 3813 #define TSC_IOGCSR_G1E ((uint32_t)0x00000001U) /*!<Analog IO GROUP1 enable */
Kojto 119:aae6fcc7d9bb 3814 #define TSC_IOGCSR_G2E ((uint32_t)0x00000002U) /*!<Analog IO GROUP2 enable */
Kojto 119:aae6fcc7d9bb 3815 #define TSC_IOGCSR_G3E ((uint32_t)0x00000004U) /*!<Analog IO GROUP3 enable */
Kojto 119:aae6fcc7d9bb 3816 #define TSC_IOGCSR_G4E ((uint32_t)0x00000008U) /*!<Analog IO GROUP4 enable */
Kojto 119:aae6fcc7d9bb 3817 #define TSC_IOGCSR_G5E ((uint32_t)0x00000010U) /*!<Analog IO GROUP5 enable */
Kojto 119:aae6fcc7d9bb 3818 #define TSC_IOGCSR_G6E ((uint32_t)0x00000020U) /*!<Analog IO GROUP6 enable */
Kojto 119:aae6fcc7d9bb 3819 #define TSC_IOGCSR_G7E ((uint32_t)0x00000040U) /*!<Analog IO GROUP7 enable */
Kojto 119:aae6fcc7d9bb 3820 #define TSC_IOGCSR_G8E ((uint32_t)0x00000080U) /*!<Analog IO GROUP8 enable */
Kojto 119:aae6fcc7d9bb 3821 #define TSC_IOGCSR_G1S ((uint32_t)0x00010000U) /*!<Analog IO GROUP1 status */
Kojto 119:aae6fcc7d9bb 3822 #define TSC_IOGCSR_G2S ((uint32_t)0x00020000U) /*!<Analog IO GROUP2 status */
Kojto 119:aae6fcc7d9bb 3823 #define TSC_IOGCSR_G3S ((uint32_t)0x00040000U) /*!<Analog IO GROUP3 status */
Kojto 119:aae6fcc7d9bb 3824 #define TSC_IOGCSR_G4S ((uint32_t)0x00080000U) /*!<Analog IO GROUP4 status */
Kojto 119:aae6fcc7d9bb 3825 #define TSC_IOGCSR_G5S ((uint32_t)0x00100000U) /*!<Analog IO GROUP5 status */
Kojto 119:aae6fcc7d9bb 3826 #define TSC_IOGCSR_G6S ((uint32_t)0x00200000U) /*!<Analog IO GROUP6 status */
Kojto 119:aae6fcc7d9bb 3827 #define TSC_IOGCSR_G7S ((uint32_t)0x00400000U) /*!<Analog IO GROUP7 status */
Kojto 119:aae6fcc7d9bb 3828 #define TSC_IOGCSR_G8S ((uint32_t)0x00800000U) /*!<Analog IO GROUP8 status */
Kojto 99:dbbf35b96557 3829
Kojto 99:dbbf35b96557 3830 /******************* Bit definition for TSC_IOGXCR register *****************/
Kojto 119:aae6fcc7d9bb 3831 #define TSC_IOGXCR_CNT ((uint32_t)0x00003FFFU) /*!<CNT[13:0] bits (Counter value) */
Kojto 99:dbbf35b96557 3832
Kojto 99:dbbf35b96557 3833 /******************************************************************************/
Kojto 99:dbbf35b96557 3834 /* */
Kojto 99:dbbf35b96557 3835 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
Kojto 99:dbbf35b96557 3836 /* */
Kojto 99:dbbf35b96557 3837 /******************************************************************************/
Kojto 119:aae6fcc7d9bb 3838
Kojto 119:aae6fcc7d9bb 3839 /*
Kojto 119:aae6fcc7d9bb 3840 * @brief Specific device feature definitions (not present on all devices in the STM32L0 family)
Kojto 119:aae6fcc7d9bb 3841 */
Kojto 119:aae6fcc7d9bb 3842 /* Note: No specific macro feature on this device */
Kojto 119:aae6fcc7d9bb 3843
Kojto 99:dbbf35b96557 3844 /****************** Bit definition for USART_CR1 register *******************/
Kojto 119:aae6fcc7d9bb 3845 #define USART_CR1_UE ((uint32_t)0x00000001U) /*!< USART Enable */
Kojto 119:aae6fcc7d9bb 3846 #define USART_CR1_UESM ((uint32_t)0x00000002U) /*!< USART Enable in STOP Mode */
Kojto 119:aae6fcc7d9bb 3847 #define USART_CR1_RE ((uint32_t)0x00000004U) /*!< Receiver Enable */
Kojto 119:aae6fcc7d9bb 3848 #define USART_CR1_TE ((uint32_t)0x00000008U) /*!< Transmitter Enable */
Kojto 119:aae6fcc7d9bb 3849 #define USART_CR1_IDLEIE ((uint32_t)0x00000010U) /*!< IDLE Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3850 #define USART_CR1_RXNEIE ((uint32_t)0x00000020U) /*!< RXNE Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3851 #define USART_CR1_TCIE ((uint32_t)0x00000040U) /*!< Transmission Complete Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3852 #define USART_CR1_TXEIE ((uint32_t)0x00000080U) /*!< TXE Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3853 #define USART_CR1_PEIE ((uint32_t)0x00000100U) /*!< PE Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3854 #define USART_CR1_PS ((uint32_t)0x00000200U) /*!< Parity Selection */
Kojto 119:aae6fcc7d9bb 3855 #define USART_CR1_PCE ((uint32_t)0x00000400U) /*!< Parity Control Enable */
Kojto 119:aae6fcc7d9bb 3856 #define USART_CR1_WAKE ((uint32_t)0x00000800U) /*!< Receiver Wakeup method */
Kojto 119:aae6fcc7d9bb 3857 #define USART_CR1_M ((uint32_t)0x10001000U) /*!< Word length */
Kojto 119:aae6fcc7d9bb 3858 #define USART_CR1_M0 ((uint32_t)0x00001000U) /*!< Word length - Bit 0 */
Kojto 119:aae6fcc7d9bb 3859 #define USART_CR1_MME ((uint32_t)0x00002000U) /*!< Mute Mode Enable */
Kojto 119:aae6fcc7d9bb 3860 #define USART_CR1_CMIE ((uint32_t)0x00004000U) /*!< Character match interrupt enable */
Kojto 119:aae6fcc7d9bb 3861 #define USART_CR1_OVER8 ((uint32_t)0x00008000U) /*!< Oversampling by 8-bit or 16-bit mode */
Kojto 119:aae6fcc7d9bb 3862 #define USART_CR1_DEDT ((uint32_t)0x001F0000U) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
Kojto 119:aae6fcc7d9bb 3863 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3864 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3865 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 3866 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 3867 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000U) /*!< Bit 4 */
Kojto 119:aae6fcc7d9bb 3868 #define USART_CR1_DEAT ((uint32_t)0x03E00000U) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
Kojto 119:aae6fcc7d9bb 3869 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3870 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3871 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 3872 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 3873 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000U) /*!< Bit 4 */
Kojto 119:aae6fcc7d9bb 3874 #define USART_CR1_RTOIE ((uint32_t)0x04000000U) /*!< Receive Time Out interrupt enable */
Kojto 119:aae6fcc7d9bb 3875 #define USART_CR1_EOBIE ((uint32_t)0x08000000U) /*!< End of Block interrupt enable */
Kojto 119:aae6fcc7d9bb 3876 #define USART_CR1_M1 ((uint32_t)0x10000000U) /*!< Word length - Bit 1 */
Kojto 99:dbbf35b96557 3877 /****************** Bit definition for USART_CR2 register *******************/
Kojto 119:aae6fcc7d9bb 3878 #define USART_CR2_ADDM7 ((uint32_t)0x00000010U) /*!< 7-bit or 4-bit Address Detection */
Kojto 119:aae6fcc7d9bb 3879 #define USART_CR2_LBDL ((uint32_t)0x00000020U) /*!< LIN Break Detection Length */
Kojto 119:aae6fcc7d9bb 3880 #define USART_CR2_LBDIE ((uint32_t)0x00000040U) /*!< LIN Break Detection Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3881 #define USART_CR2_LBCL ((uint32_t)0x00000100U) /*!< Last Bit Clock pulse */
Kojto 119:aae6fcc7d9bb 3882 #define USART_CR2_CPHA ((uint32_t)0x00000200U) /*!< Clock Phase */
Kojto 119:aae6fcc7d9bb 3883 #define USART_CR2_CPOL ((uint32_t)0x00000400U) /*!< Clock Polarity */
Kojto 119:aae6fcc7d9bb 3884 #define USART_CR2_CLKEN ((uint32_t)0x00000800U) /*!< Clock Enable */
Kojto 119:aae6fcc7d9bb 3885 #define USART_CR2_STOP ((uint32_t)0x00003000U) /*!< STOP[1:0] bits (STOP bits) */
Kojto 119:aae6fcc7d9bb 3886 #define USART_CR2_STOP_0 ((uint32_t)0x00001000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3887 #define USART_CR2_STOP_1 ((uint32_t)0x00002000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3888 #define USART_CR2_LINEN ((uint32_t)0x00004000U) /*!< LIN mode enable */
Kojto 119:aae6fcc7d9bb 3889 #define USART_CR2_SWAP ((uint32_t)0x00008000U) /*!< SWAP TX/RX pins */
Kojto 119:aae6fcc7d9bb 3890 #define USART_CR2_RXINV ((uint32_t)0x00010000U) /*!< RX pin active level inversion */
Kojto 119:aae6fcc7d9bb 3891 #define USART_CR2_TXINV ((uint32_t)0x00020000U) /*!< TX pin active level inversion */
Kojto 119:aae6fcc7d9bb 3892 #define USART_CR2_DATAINV ((uint32_t)0x00040000U) /*!< Binary data inversion */
Kojto 119:aae6fcc7d9bb 3893 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000U) /*!< Most Significant Bit First */
Kojto 119:aae6fcc7d9bb 3894 #define USART_CR2_ABREN ((uint32_t)0x00100000U) /*!< Auto Baud-Rate Enable*/
Kojto 119:aae6fcc7d9bb 3895 #define USART_CR2_ABRMODE ((uint32_t)0x00600000U) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
Kojto 119:aae6fcc7d9bb 3896 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3897 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3898 #define USART_CR2_RTOEN ((uint32_t)0x00800000U) /*!< Receiver Time-Out enable */
Kojto 119:aae6fcc7d9bb 3899 #define USART_CR2_ADD ((uint32_t)0xFF000000U) /*!< Address of the USART node */
Kojto 99:dbbf35b96557 3900
Kojto 99:dbbf35b96557 3901 /****************** Bit definition for USART_CR3 register *******************/
Kojto 119:aae6fcc7d9bb 3902 #define USART_CR3_EIE ((uint32_t)0x00000001U) /*!< Error Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3903 #define USART_CR3_IREN ((uint32_t)0x00000002U) /*!< IrDA mode Enable */
Kojto 119:aae6fcc7d9bb 3904 #define USART_CR3_IRLP ((uint32_t)0x00000004U) /*!< IrDA Low-Power */
Kojto 119:aae6fcc7d9bb 3905 #define USART_CR3_HDSEL ((uint32_t)0x00000008U) /*!< Half-Duplex Selection */
Kojto 119:aae6fcc7d9bb 3906 #define USART_CR3_NACK ((uint32_t)0x00000010U) /*!< SmartCard NACK enable */
Kojto 119:aae6fcc7d9bb 3907 #define USART_CR3_SCEN ((uint32_t)0x00000020U) /*!< SmartCard mode enable */
Kojto 119:aae6fcc7d9bb 3908 #define USART_CR3_DMAR ((uint32_t)0x00000040U) /*!< DMA Enable Receiver */
Kojto 119:aae6fcc7d9bb 3909 #define USART_CR3_DMAT ((uint32_t)0x00000080U) /*!< DMA Enable Transmitter */
Kojto 119:aae6fcc7d9bb 3910 #define USART_CR3_RTSE ((uint32_t)0x00000100U) /*!< RTS Enable */
Kojto 119:aae6fcc7d9bb 3911 #define USART_CR3_CTSE ((uint32_t)0x00000200U) /*!< CTS Enable */
Kojto 119:aae6fcc7d9bb 3912 #define USART_CR3_CTSIE ((uint32_t)0x00000400U) /*!< CTS Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3913 #define USART_CR3_ONEBIT ((uint32_t)0x00000800U) /*!< One sample bit method enable */
Kojto 119:aae6fcc7d9bb 3914 #define USART_CR3_OVRDIS ((uint32_t)0x00001000U) /*!< Overrun Disable */
Kojto 119:aae6fcc7d9bb 3915 #define USART_CR3_DDRE ((uint32_t)0x00002000U) /*!< DMA Disable on Reception Error */
Kojto 119:aae6fcc7d9bb 3916 #define USART_CR3_DEM ((uint32_t)0x00004000U) /*!< Driver Enable Mode */
Kojto 119:aae6fcc7d9bb 3917 #define USART_CR3_DEP ((uint32_t)0x00008000U) /*!< Driver Enable Polarity Selection */
Kojto 119:aae6fcc7d9bb 3918 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000U) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
Kojto 119:aae6fcc7d9bb 3919 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3920 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3921 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 3922 #define USART_CR3_WUS ((uint32_t)0x00300000U) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
Kojto 119:aae6fcc7d9bb 3923 #define USART_CR3_WUS_0 ((uint32_t)0x00100000U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 3924 #define USART_CR3_WUS_1 ((uint32_t)0x00200000U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 3925 #define USART_CR3_WUFIE ((uint32_t)0x00400000U) /*!< Wake Up Interrupt Enable */
Kojto 119:aae6fcc7d9bb 3926 #define USART_CR3_UCESM ((uint32_t)0x00800000U) /*!< Clock Enable in Stop mode */
Kojto 99:dbbf35b96557 3927
Kojto 99:dbbf35b96557 3928 /****************** Bit definition for USART_BRR register *******************/
Kojto 119:aae6fcc7d9bb 3929 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000FU) /*!< Fraction of USARTDIV */
Kojto 119:aae6fcc7d9bb 3930 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0U) /*!< Mantissa of USARTDIV */
Kojto 99:dbbf35b96557 3931
Kojto 99:dbbf35b96557 3932 /****************** Bit definition for USART_GTPR register ******************/
Kojto 119:aae6fcc7d9bb 3933 #define USART_GTPR_PSC ((uint32_t)0x000000FFU) /*!< PSC[7:0] bits (Prescaler value) */
Kojto 119:aae6fcc7d9bb 3934 #define USART_GTPR_GT ((uint32_t)0x0000FF00U) /*!< GT[7:0] bits (Guard time value) */
Kojto 99:dbbf35b96557 3935
Kojto 99:dbbf35b96557 3936
Kojto 99:dbbf35b96557 3937 /******************* Bit definition for USART_RTOR register *****************/
Kojto 119:aae6fcc7d9bb 3938 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFFU) /*!< Receiver Time Out Value */
Kojto 119:aae6fcc7d9bb 3939 #define USART_RTOR_BLEN ((uint32_t)0xFF000000U) /*!< Block Length */
Kojto 99:dbbf35b96557 3940
Kojto 99:dbbf35b96557 3941 /******************* Bit definition for USART_RQR register ******************/
Kojto 119:aae6fcc7d9bb 3942 #define USART_RQR_ABRRQ ((uint32_t)0x00000001U) /*!< Auto-Baud Rate Request */
Kojto 119:aae6fcc7d9bb 3943 #define USART_RQR_SBKRQ ((uint32_t)0x00000002U) /*!< Send Break Request */
Kojto 119:aae6fcc7d9bb 3944 #define USART_RQR_MMRQ ((uint32_t)0x00000004U) /*!< Mute Mode Request */
Kojto 119:aae6fcc7d9bb 3945 #define USART_RQR_RXFRQ ((uint32_t)0x00000008U) /*!< Receive Data flush Request */
Kojto 119:aae6fcc7d9bb 3946 #define USART_RQR_TXFRQ ((uint32_t)0x00000010U) /*!< Transmit data flush Request */
Kojto 99:dbbf35b96557 3947
Kojto 99:dbbf35b96557 3948 /******************* Bit definition for USART_ISR register ******************/
Kojto 119:aae6fcc7d9bb 3949 #define USART_ISR_PE ((uint32_t)0x00000001U) /*!< Parity Error */
Kojto 119:aae6fcc7d9bb 3950 #define USART_ISR_FE ((uint32_t)0x00000002U) /*!< Framing Error */
Kojto 119:aae6fcc7d9bb 3951 #define USART_ISR_NE ((uint32_t)0x00000004U) /*!< Noise detected Flag */
Kojto 119:aae6fcc7d9bb 3952 #define USART_ISR_ORE ((uint32_t)0x00000008U) /*!< OverRun Error */
Kojto 119:aae6fcc7d9bb 3953 #define USART_ISR_IDLE ((uint32_t)0x00000010U) /*!< IDLE line detected */
Kojto 119:aae6fcc7d9bb 3954 #define USART_ISR_RXNE ((uint32_t)0x00000020U) /*!< Read Data Register Not Empty */
Kojto 119:aae6fcc7d9bb 3955 #define USART_ISR_TC ((uint32_t)0x00000040U) /*!< Transmission Complete */
Kojto 119:aae6fcc7d9bb 3956 #define USART_ISR_TXE ((uint32_t)0x00000080U) /*!< Transmit Data Register Empty */
Kojto 119:aae6fcc7d9bb 3957 #define USART_ISR_LBDF ((uint32_t)0x00000100U) /*!< LIN Break Detection Flag */
Kojto 119:aae6fcc7d9bb 3958 #define USART_ISR_CTSIF ((uint32_t)0x00000200U) /*!< CTS interrupt flag */
Kojto 119:aae6fcc7d9bb 3959 #define USART_ISR_CTS ((uint32_t)0x00000400U) /*!< CTS flag */
Kojto 119:aae6fcc7d9bb 3960 #define USART_ISR_RTOF ((uint32_t)0x00000800U) /*!< Receiver Time Out */
Kojto 119:aae6fcc7d9bb 3961 #define USART_ISR_EOBF ((uint32_t)0x00001000U) /*!< End Of Block Flag */
Kojto 119:aae6fcc7d9bb 3962 #define USART_ISR_ABRE ((uint32_t)0x00004000U) /*!< Auto-Baud Rate Error */
Kojto 119:aae6fcc7d9bb 3963 #define USART_ISR_ABRF ((uint32_t)0x00008000U) /*!< Auto-Baud Rate Flag */
Kojto 119:aae6fcc7d9bb 3964 #define USART_ISR_BUSY ((uint32_t)0x00010000U) /*!< Busy Flag */
Kojto 119:aae6fcc7d9bb 3965 #define USART_ISR_CMF ((uint32_t)0x00020000U) /*!< Character Match Flag */
Kojto 119:aae6fcc7d9bb 3966 #define USART_ISR_SBKF ((uint32_t)0x00040000U) /*!< Send Break Flag */
Kojto 119:aae6fcc7d9bb 3967 #define USART_ISR_RWU ((uint32_t)0x00080000U) /*!< Receive Wake Up from mute mode Flag */
Kojto 119:aae6fcc7d9bb 3968 #define USART_ISR_WUF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Flag */
Kojto 119:aae6fcc7d9bb 3969 #define USART_ISR_TEACK ((uint32_t)0x00200000U) /*!< Transmit Enable Acknowledge Flag */
Kojto 119:aae6fcc7d9bb 3970 #define USART_ISR_REACK ((uint32_t)0x00400000U) /*!< Receive Enable Acknowledge Flag */
Kojto 99:dbbf35b96557 3971
Kojto 99:dbbf35b96557 3972 /******************* Bit definition for USART_ICR register ******************/
Kojto 119:aae6fcc7d9bb 3973 #define USART_ICR_PECF ((uint32_t)0x00000001U) /*!< Parity Error Clear Flag */
Kojto 119:aae6fcc7d9bb 3974 #define USART_ICR_FECF ((uint32_t)0x00000002U) /*!< Framing Error Clear Flag */
Kojto 119:aae6fcc7d9bb 3975 #define USART_ICR_NCF ((uint32_t)0x00000004U) /*!< Noise detected Clear Flag */
Kojto 119:aae6fcc7d9bb 3976 #define USART_ICR_ORECF ((uint32_t)0x00000008U) /*!< OverRun Error Clear Flag */
Kojto 119:aae6fcc7d9bb 3977 #define USART_ICR_IDLECF ((uint32_t)0x00000010U) /*!< IDLE line detected Clear Flag */
Kojto 119:aae6fcc7d9bb 3978 #define USART_ICR_TCCF ((uint32_t)0x00000040U) /*!< Transmission Complete Clear Flag */
Kojto 119:aae6fcc7d9bb 3979 #define USART_ICR_LBDCF ((uint32_t)0x00000100U) /*!< LIN Break Detection Clear Flag */
Kojto 119:aae6fcc7d9bb 3980 #define USART_ICR_CTSCF ((uint32_t)0x00000200U) /*!< CTS Interrupt Clear Flag */
Kojto 119:aae6fcc7d9bb 3981 #define USART_ICR_RTOCF ((uint32_t)0x00000800U) /*!< Receiver Time Out Clear Flag */
Kojto 119:aae6fcc7d9bb 3982 #define USART_ICR_EOBCF ((uint32_t)0x00001000U) /*!< End Of Block Clear Flag */
Kojto 119:aae6fcc7d9bb 3983 #define USART_ICR_CMCF ((uint32_t)0x00020000U) /*!< Character Match Clear Flag */
Kojto 119:aae6fcc7d9bb 3984 #define USART_ICR_WUCF ((uint32_t)0x00100000U) /*!< Wake Up from stop mode Clear Flag */
Kojto 99:dbbf35b96557 3985
Kojto 99:dbbf35b96557 3986 /******************* Bit definition for USART_RDR register ******************/
Kojto 119:aae6fcc7d9bb 3987 #define USART_RDR_RDR ((uint32_t)0x000001FFU) /*!< RDR[8:0] bits (Receive Data value) */
Kojto 99:dbbf35b96557 3988
Kojto 99:dbbf35b96557 3989 /******************* Bit definition for USART_TDR register ******************/
Kojto 119:aae6fcc7d9bb 3990 #define USART_TDR_TDR ((uint32_t)0x000001FFU) /*!< TDR[8:0] bits (Transmit Data value) */
Kojto 99:dbbf35b96557 3991
Kojto 99:dbbf35b96557 3992 /******************************************************************************/
Kojto 99:dbbf35b96557 3993 /* */
Kojto 99:dbbf35b96557 3994 /* USB Device General registers */
Kojto 99:dbbf35b96557 3995 /* */
Kojto 99:dbbf35b96557 3996 /******************************************************************************/
Kojto 119:aae6fcc7d9bb 3997 #define USB_BASE ((uint32_t)0x40005C00U) /*!< USB_IP Peripheral Registers base address */
Kojto 119:aae6fcc7d9bb 3998 #define USB_PMAADDR ((uint32_t)0x40006000U) /*!< USB_IP Packet Memory Area base address */
Kojto 99:dbbf35b96557 3999
Kojto 99:dbbf35b96557 4000 #define USB_CNTR (USB_BASE + 0x40) /*!< Control register */
Kojto 99:dbbf35b96557 4001 #define USB_ISTR (USB_BASE + 0x44) /*!< Interrupt status register */
Kojto 99:dbbf35b96557 4002 #define USB_FNR (USB_BASE + 0x48) /*!< Frame number register */
Kojto 99:dbbf35b96557 4003 #define USB_DADDR (USB_BASE + 0x4C) /*!< Device address register */
Kojto 99:dbbf35b96557 4004 #define USB_BTABLE (USB_BASE + 0x50) /*!< Buffer Table address register */
Kojto 99:dbbf35b96557 4005 #define USB_LPMCSR (USB_BASE + 0x54) /*!< LPM Control and Status register */
Kojto 99:dbbf35b96557 4006 #define USB_BCDR (USB_BASE + 0x58) /*!< Battery Charging detector register*/
Kojto 99:dbbf35b96557 4007
Kojto 99:dbbf35b96557 4008 /**************************** ISTR interrupt events *************************/
Kojto 119:aae6fcc7d9bb 4009 #define USB_ISTR_CTR ((uint16_t)0x8000U) /*!< Correct TRansfer (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4010 #define USB_ISTR_PMAOVR ((uint16_t)0x4000U) /*!< DMA OVeR/underrun (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4011 #define USB_ISTR_ERR ((uint16_t)0x2000U) /*!< ERRor (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4012 #define USB_ISTR_WKUP ((uint16_t)0x1000U) /*!< WaKe UP (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4013 #define USB_ISTR_SUSP ((uint16_t)0x0800U) /*!< SUSPend (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4014 #define USB_ISTR_RESET ((uint16_t)0x0400U) /*!< RESET (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4015 #define USB_ISTR_SOF ((uint16_t)0x0200U) /*!< Start Of Frame (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4016 #define USB_ISTR_ESOF ((uint16_t)0x0100U) /*!< Expected Start Of Frame (clear-only bit) */
Kojto 119:aae6fcc7d9bb 4017 #define USB_ISTR_L1REQ ((uint16_t)0x0080U) /*!< LPM L1 state request */
Kojto 119:aae6fcc7d9bb 4018 #define USB_ISTR_DIR ((uint16_t)0x0010U) /*!< DIRection of transaction (read-only bit) */
Kojto 119:aae6fcc7d9bb 4019 #define USB_ISTR_EP_ID ((uint16_t)0x000FU) /*!< EndPoint IDentifier (read-only bit) */
Kojto 99:dbbf35b96557 4020
Kojto 99:dbbf35b96557 4021 #define USB_CLR_CTR (~USB_ISTR_CTR) /*!< clear Correct TRansfer bit */
Kojto 99:dbbf35b96557 4022 #define USB_CLR_PMAOVR (~USB_ISTR_PMAOVR) /*!< clear DMA OVeR/underrun bit*/
Kojto 99:dbbf35b96557 4023 #define USB_CLR_ERR (~USB_ISTR_ERR) /*!< clear ERRor bit */
Kojto 99:dbbf35b96557 4024 #define USB_CLR_WKUP (~USB_ISTR_WKUP) /*!< clear WaKe UP bit */
Kojto 99:dbbf35b96557 4025 #define USB_CLR_SUSP (~USB_ISTR_SUSP) /*!< clear SUSPend bit */
Kojto 99:dbbf35b96557 4026 #define USB_CLR_RESET (~USB_ISTR_RESET) /*!< clear RESET bit */
Kojto 99:dbbf35b96557 4027 #define USB_CLR_SOF (~USB_ISTR_SOF) /*!< clear Start Of Frame bit */
Kojto 99:dbbf35b96557 4028 #define USB_CLR_ESOF (~USB_ISTR_ESOF) /*!< clear Expected Start Of Frame bit */
Kojto 99:dbbf35b96557 4029 #define USB_CLR_L1REQ (~USB_ISTR_L1REQ) /*!< clear LPM L1 bit */
Kojto 99:dbbf35b96557 4030 /************************* CNTR control register bits definitions ***********/
Kojto 119:aae6fcc7d9bb 4031 #define USB_CNTR_CTRM ((uint16_t)0x8000U) /*!< Correct TRansfer Mask */
Kojto 119:aae6fcc7d9bb 4032 #define USB_CNTR_PMAOVRM ((uint16_t)0x4000U) /*!< DMA OVeR/underrun Mask */
Kojto 119:aae6fcc7d9bb 4033 #define USB_CNTR_ERRM ((uint16_t)0x2000U) /*!< ERRor Mask */
Kojto 119:aae6fcc7d9bb 4034 #define USB_CNTR_WKUPM ((uint16_t)0x1000U) /*!< WaKe UP Mask */
Kojto 119:aae6fcc7d9bb 4035 #define USB_CNTR_SUSPM ((uint16_t)0x0800U) /*!< SUSPend Mask */
Kojto 119:aae6fcc7d9bb 4036 #define USB_CNTR_RESETM ((uint16_t)0x0400U) /*!< RESET Mask */
Kojto 119:aae6fcc7d9bb 4037 #define USB_CNTR_SOFM ((uint16_t)0x0200U) /*!< Start Of Frame Mask */
Kojto 119:aae6fcc7d9bb 4038 #define USB_CNTR_ESOFM ((uint16_t)0x0100U) /*!< Expected Start Of Frame Mask */
Kojto 119:aae6fcc7d9bb 4039 #define USB_CNTR_L1REQM ((uint16_t)0x0080U) /*!< LPM L1 state request interrupt mask */
Kojto 119:aae6fcc7d9bb 4040 #define USB_CNTR_L1RESUME ((uint16_t)0x0020U) /*!< LPM L1 Resume request */
Kojto 119:aae6fcc7d9bb 4041 #define USB_CNTR_RESUME ((uint16_t)0x0010U) /*!< RESUME request */
Kojto 119:aae6fcc7d9bb 4042 #define USB_CNTR_FSUSP ((uint16_t)0x0008U) /*!< Force SUSPend */
Kojto 119:aae6fcc7d9bb 4043 #define USB_CNTR_LPMODE ((uint16_t)0x0004U) /*!< Low-power MODE */
Kojto 119:aae6fcc7d9bb 4044 #define USB_CNTR_PDWN ((uint16_t)0x0002U) /*!< Power DoWN */
Kojto 119:aae6fcc7d9bb 4045 #define USB_CNTR_FRES ((uint16_t)0x0001U) /*!< Force USB RESet */
Kojto 99:dbbf35b96557 4046 /************************* BCDR control register bits definitions ***********/
Kojto 119:aae6fcc7d9bb 4047 #define USB_BCDR_DPPU ((uint16_t)0x8000U) /*!< DP Pull-up Enable */
Kojto 119:aae6fcc7d9bb 4048 #define USB_BCDR_PS2DET ((uint16_t)0x0080U) /*!< PS2 port or proprietary charger detected */
Kojto 119:aae6fcc7d9bb 4049 #define USB_BCDR_SDET ((uint16_t)0x0040U) /*!< Secondary detection (SD) status */
Kojto 119:aae6fcc7d9bb 4050 #define USB_BCDR_PDET ((uint16_t)0x0020U) /*!< Primary detection (PD) status */
Kojto 119:aae6fcc7d9bb 4051 #define USB_BCDR_DCDET ((uint16_t)0x0010U) /*!< Data contact detection (DCD) status */
Kojto 119:aae6fcc7d9bb 4052 #define USB_BCDR_SDEN ((uint16_t)0x0008U) /*!< Secondary detection (SD) mode enable */
Kojto 119:aae6fcc7d9bb 4053 #define USB_BCDR_PDEN ((uint16_t)0x0004U) /*!< Primary detection (PD) mode enable */
Kojto 119:aae6fcc7d9bb 4054 #define USB_BCDR_DCDEN ((uint16_t)0x0002U) /*!< Data contact detection (DCD) mode enable */
Kojto 119:aae6fcc7d9bb 4055 #define USB_BCDR_BCDEN ((uint16_t)0x0001U) /*!< Battery charging detector (BCD) enable */
Kojto 99:dbbf35b96557 4056 /*************************** LPM register bits definitions ******************/
Kojto 119:aae6fcc7d9bb 4057 #define USB_LPMCSR_BESL ((uint16_t)0x00F0U) /*!< BESL value received with last ACKed LPM Token */
Kojto 119:aae6fcc7d9bb 4058 #define USB_LPMCSR_REMWAKE ((uint16_t)0x0008U) /*!< bRemoteWake value received with last ACKed LPM Token */
Kojto 119:aae6fcc7d9bb 4059 #define USB_LPMCSR_LPMACK ((uint16_t)0x0002U) /*!< LPM Token acknowledge enable*/
Kojto 119:aae6fcc7d9bb 4060 #define USB_LPMCSR_LMPEN ((uint16_t)0x0001U) /*!< LPM support enable */
Kojto 99:dbbf35b96557 4061 /******************** FNR Frame Number Register bit definitions ************/
Kojto 119:aae6fcc7d9bb 4062 #define USB_FNR_RXDP ((uint16_t)0x8000U) /*!< status of D+ data line */
Kojto 119:aae6fcc7d9bb 4063 #define USB_FNR_RXDM ((uint16_t)0x4000U) /*!< status of D- data line */
Kojto 119:aae6fcc7d9bb 4064 #define USB_FNR_LCK ((uint16_t)0x2000U) /*!< LoCKed */
Kojto 119:aae6fcc7d9bb 4065 #define USB_FNR_LSOF ((uint16_t)0x1800U) /*!< Lost SOF */
Kojto 119:aae6fcc7d9bb 4066 #define USB_FNR_FN ((uint16_t)0x07FFU) /*!< Frame Number */
Kojto 99:dbbf35b96557 4067 /******************** DADDR Device ADDRess bit definitions ****************/
Kojto 119:aae6fcc7d9bb 4068 #define USB_DADDR_EF ((uint8_t)0x80U) /*!< USB device address Enable Function */
Kojto 119:aae6fcc7d9bb 4069 #define USB_DADDR_ADD ((uint8_t)0x7FU) /*!< USB device address */
Kojto 99:dbbf35b96557 4070 /****************************** Endpoint register *************************/
Kojto 99:dbbf35b96557 4071 #define USB_EP0R USB_BASE /*!< endpoint 0 register address */
Kojto 99:dbbf35b96557 4072 #define USB_EP1R (USB_BASE + 0x04) /*!< endpoint 1 register address */
Kojto 99:dbbf35b96557 4073 #define USB_EP2R (USB_BASE + 0x08) /*!< endpoint 2 register address */
Kojto 99:dbbf35b96557 4074 #define USB_EP3R (USB_BASE + 0x0C) /*!< endpoint 3 register address */
Kojto 99:dbbf35b96557 4075 #define USB_EP4R (USB_BASE + 0x10) /*!< endpoint 4 register address */
Kojto 99:dbbf35b96557 4076 #define USB_EP5R (USB_BASE + 0x14) /*!< endpoint 5 register address */
Kojto 99:dbbf35b96557 4077 #define USB_EP6R (USB_BASE + 0x18) /*!< endpoint 6 register address */
Kojto 99:dbbf35b96557 4078 #define USB_EP7R (USB_BASE + 0x1C) /*!< endpoint 7 register address */
Kojto 99:dbbf35b96557 4079 /* bit positions */
Kojto 119:aae6fcc7d9bb 4080 #define USB_EP_CTR_RX ((uint16_t)0x8000U) /*!< EndPoint Correct TRansfer RX */
Kojto 119:aae6fcc7d9bb 4081 #define USB_EP_DTOG_RX ((uint16_t)0x4000U) /*!< EndPoint Data TOGGLE RX */
Kojto 119:aae6fcc7d9bb 4082 #define USB_EPRX_STAT ((uint16_t)0x3000U) /*!< EndPoint RX STATus bit field */
Kojto 119:aae6fcc7d9bb 4083 #define USB_EP_SETUP ((uint16_t)0x0800U) /*!< EndPoint SETUP */
Kojto 119:aae6fcc7d9bb 4084 #define USB_EP_T_FIELD ((uint16_t)0x0600U) /*!< EndPoint TYPE */
Kojto 119:aae6fcc7d9bb 4085 #define USB_EP_KIND ((uint16_t)0x0100U) /*!< EndPoint KIND */
Kojto 119:aae6fcc7d9bb 4086 #define USB_EP_CTR_TX ((uint16_t)0x0080U) /*!< EndPoint Correct TRansfer TX */
Kojto 119:aae6fcc7d9bb 4087 #define USB_EP_DTOG_TX ((uint16_t)0x0040U) /*!< EndPoint Data TOGGLE TX */
Kojto 119:aae6fcc7d9bb 4088 #define USB_EPTX_STAT ((uint16_t)0x0030U) /*!< EndPoint TX STATus bit field */
Kojto 119:aae6fcc7d9bb 4089 #define USB_EPADDR_FIELD ((uint16_t)0x000FU) /*!< EndPoint ADDRess FIELD */
Kojto 99:dbbf35b96557 4090
Kojto 99:dbbf35b96557 4091 /* EndPoint REGister MASK (no toggle fields) */
Kojto 99:dbbf35b96557 4092 #define USB_EPREG_MASK (USB_EP_CTR_RX|USB_EP_SETUP|USB_EP_T_FIELD|USB_EP_KIND|USB_EP_CTR_TX|USB_EPADDR_FIELD)
Kojto 99:dbbf35b96557 4093 /*!< EP_TYPE[1:0] EndPoint TYPE */
Kojto 119:aae6fcc7d9bb 4094 #define USB_EP_TYPE_MASK ((uint16_t)0x0600U) /*!< EndPoint TYPE Mask */
Kojto 119:aae6fcc7d9bb 4095 #define USB_EP_BULK ((uint16_t)0x0000U) /*!< EndPoint BULK */
Kojto 119:aae6fcc7d9bb 4096 #define USB_EP_CONTROL ((uint16_t)0x0200U) /*!< EndPoint CONTROL */
Kojto 119:aae6fcc7d9bb 4097 #define USB_EP_ISOCHRONOUS ((uint16_t)0x0400U) /*!< EndPoint ISOCHRONOUS */
Kojto 119:aae6fcc7d9bb 4098 #define USB_EP_INTERRUPT ((uint16_t)0x0600U) /*!< EndPoint INTERRUPT */
Kojto 119:aae6fcc7d9bb 4099 #define USB_EP_T_MASK ((uint16_t) ~USB_EP_T_FIELD & USB_EPREG_MASK)
Kojto 99:dbbf35b96557 4100
Kojto 119:aae6fcc7d9bb 4101 #define USB_EPKIND_MASK ((uint16_t)~USB_EP_KIND & USB_EPREG_MASK) /*!< EP_KIND EndPoint KIND */
Kojto 99:dbbf35b96557 4102 /*!< STAT_TX[1:0] STATus for TX transfer */
Kojto 119:aae6fcc7d9bb 4103 #define USB_EP_TX_DIS ((uint16_t)0x0000U) /*!< EndPoint TX DISabled */
Kojto 119:aae6fcc7d9bb 4104 #define USB_EP_TX_STALL ((uint16_t)0x0010U) /*!< EndPoint TX STALLed */
Kojto 119:aae6fcc7d9bb 4105 #define USB_EP_TX_NAK ((uint16_t)0x0020U) /*!< EndPoint TX NAKed */
Kojto 119:aae6fcc7d9bb 4106 #define USB_EP_TX_VALID ((uint16_t)0x0030U) /*!< EndPoint TX VALID */
Kojto 119:aae6fcc7d9bb 4107 #define USB_EPTX_DTOG1 ((uint16_t)0x0010U) /*!< EndPoint TX Data TOGgle bit1 */
Kojto 119:aae6fcc7d9bb 4108 #define USB_EPTX_DTOG2 ((uint16_t)0x0020U) /*!< EndPoint TX Data TOGgle bit2 */
Kojto 99:dbbf35b96557 4109 #define USB_EPTX_DTOGMASK (USB_EPTX_STAT|USB_EPREG_MASK)
Kojto 99:dbbf35b96557 4110 /*!< STAT_RX[1:0] STATus for RX transfer */
Kojto 119:aae6fcc7d9bb 4111 #define USB_EP_RX_DIS ((uint16_t)0x0000U) /*!< EndPoint RX DISabled */
Kojto 119:aae6fcc7d9bb 4112 #define USB_EP_RX_STALL ((uint16_t)0x1000U) /*!< EndPoint RX STALLed */
Kojto 119:aae6fcc7d9bb 4113 #define USB_EP_RX_NAK ((uint16_t)0x2000U) /*!< EndPoint RX NAKed */
Kojto 119:aae6fcc7d9bb 4114 #define USB_EP_RX_VALID ((uint16_t)0x3000U) /*!< EndPoint RX VALID */
Kojto 119:aae6fcc7d9bb 4115 #define USB_EPRX_DTOG1 ((uint16_t)0x1000U) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 119:aae6fcc7d9bb 4116 #define USB_EPRX_DTOG2 ((uint16_t)0x2000U) /*!< EndPoint RX Data TOGgle bit1 */
Kojto 99:dbbf35b96557 4117 #define USB_EPRX_DTOGMASK (USB_EPRX_STAT|USB_EPREG_MASK)
Kojto 99:dbbf35b96557 4118
Kojto 99:dbbf35b96557 4119 /******************************************************************************/
Kojto 99:dbbf35b96557 4120 /* */
Kojto 99:dbbf35b96557 4121 /* Window WATCHDOG (WWDG) */
Kojto 99:dbbf35b96557 4122 /* */
Kojto 99:dbbf35b96557 4123 /******************************************************************************/
Kojto 99:dbbf35b96557 4124
Kojto 99:dbbf35b96557 4125 /******************* Bit definition for WWDG_CR register ********************/
Kojto 119:aae6fcc7d9bb 4126 #define WWDG_CR_T ((uint32_t)0x0000007FU) /*!< T[6:0] bits (7-Bit counter (MSB to LSB)) */
Kojto 119:aae6fcc7d9bb 4127 #define WWDG_CR_T_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 4128 #define WWDG_CR_T_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 4129 #define WWDG_CR_T_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 4130 #define WWDG_CR_T_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 4131 #define WWDG_CR_T_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 119:aae6fcc7d9bb 4132 #define WWDG_CR_T_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 119:aae6fcc7d9bb 4133 #define WWDG_CR_T_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 119:aae6fcc7d9bb 4134
Kojto 119:aae6fcc7d9bb 4135 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 4136 #define WWDG_CR_T0 WWDG_CR_T_0
Kojto 119:aae6fcc7d9bb 4137 #define WWDG_CR_T1 WWDG_CR_T_1
Kojto 119:aae6fcc7d9bb 4138 #define WWDG_CR_T2 WWDG_CR_T_2
Kojto 119:aae6fcc7d9bb 4139 #define WWDG_CR_T3 WWDG_CR_T_3
Kojto 119:aae6fcc7d9bb 4140 #define WWDG_CR_T4 WWDG_CR_T_4
Kojto 119:aae6fcc7d9bb 4141 #define WWDG_CR_T5 WWDG_CR_T_5
Kojto 119:aae6fcc7d9bb 4142 #define WWDG_CR_T6 WWDG_CR_T_6
Kojto 119:aae6fcc7d9bb 4143
Kojto 119:aae6fcc7d9bb 4144 #define WWDG_CR_WDGA ((uint32_t)0x00000080U) /*!< Activation bit */
Kojto 99:dbbf35b96557 4145
Kojto 99:dbbf35b96557 4146 /******************* Bit definition for WWDG_CFR register *******************/
Kojto 119:aae6fcc7d9bb 4147 #define WWDG_CFR_W ((uint32_t)0x0000007FU) /*!< W[6:0] bits (7-bit window value) */
Kojto 119:aae6fcc7d9bb 4148 #define WWDG_CFR_W_0 ((uint32_t)0x00000001U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 4149 #define WWDG_CFR_W_1 ((uint32_t)0x00000002U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 4150 #define WWDG_CFR_W_2 ((uint32_t)0x00000004U) /*!< Bit 2 */
Kojto 119:aae6fcc7d9bb 4151 #define WWDG_CFR_W_3 ((uint32_t)0x00000008U) /*!< Bit 3 */
Kojto 119:aae6fcc7d9bb 4152 #define WWDG_CFR_W_4 ((uint32_t)0x00000010U) /*!< Bit 4 */
Kojto 119:aae6fcc7d9bb 4153 #define WWDG_CFR_W_5 ((uint32_t)0x00000020U) /*!< Bit 5 */
Kojto 119:aae6fcc7d9bb 4154 #define WWDG_CFR_W_6 ((uint32_t)0x00000040U) /*!< Bit 6 */
Kojto 119:aae6fcc7d9bb 4155
Kojto 119:aae6fcc7d9bb 4156 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 4157 #define WWDG_CFR_W0 WWDG_CFR_W_0
Kojto 119:aae6fcc7d9bb 4158 #define WWDG_CFR_W1 WWDG_CFR_W_1
Kojto 119:aae6fcc7d9bb 4159 #define WWDG_CFR_W2 WWDG_CFR_W_2
Kojto 119:aae6fcc7d9bb 4160 #define WWDG_CFR_W3 WWDG_CFR_W_3
Kojto 119:aae6fcc7d9bb 4161 #define WWDG_CFR_W4 WWDG_CFR_W_4
Kojto 119:aae6fcc7d9bb 4162 #define WWDG_CFR_W5 WWDG_CFR_W_5
Kojto 119:aae6fcc7d9bb 4163 #define WWDG_CFR_W6 WWDG_CFR_W_6
Kojto 119:aae6fcc7d9bb 4164
Kojto 119:aae6fcc7d9bb 4165 #define WWDG_CFR_WDGTB ((uint32_t)0x00000180U) /*!< WDGTB[1:0] bits (Timer Base) */
Kojto 119:aae6fcc7d9bb 4166 #define WWDG_CFR_WDGTB_0 ((uint32_t)0x00000080U) /*!< Bit 0 */
Kojto 119:aae6fcc7d9bb 4167 #define WWDG_CFR_WDGTB_1 ((uint32_t)0x00000100U) /*!< Bit 1 */
Kojto 119:aae6fcc7d9bb 4168
Kojto 119:aae6fcc7d9bb 4169 /* Legacy defines */
Kojto 119:aae6fcc7d9bb 4170 #define WWDG_CFR_WDGTB0 WWDG_CFR_WDGTB_0
Kojto 119:aae6fcc7d9bb 4171 #define WWDG_CFR_WDGTB1 WWDG_CFR_WDGTB_1
Kojto 119:aae6fcc7d9bb 4172
Kojto 119:aae6fcc7d9bb 4173 #define WWDG_CFR_EWI ((uint32_t)0x00000200U) /*!< Early Wakeup Interrupt */
Kojto 99:dbbf35b96557 4174
Kojto 99:dbbf35b96557 4175 /******************* Bit definition for WWDG_SR register ********************/
Kojto 119:aae6fcc7d9bb 4176 #define WWDG_SR_EWIF ((uint32_t)0x00000001U) /*!< Early Wakeup Interrupt Flag */
Kojto 99:dbbf35b96557 4177
Kojto 99:dbbf35b96557 4178 /**
Kojto 99:dbbf35b96557 4179 * @}
Kojto 99:dbbf35b96557 4180 */
Kojto 99:dbbf35b96557 4181
Kojto 99:dbbf35b96557 4182 /**
Kojto 99:dbbf35b96557 4183 * @}
Kojto 99:dbbf35b96557 4184 */
Kojto 99:dbbf35b96557 4185
Kojto 99:dbbf35b96557 4186 /** @addtogroup Exported_macros
Kojto 99:dbbf35b96557 4187 * @{
Kojto 99:dbbf35b96557 4188 */
Kojto 99:dbbf35b96557 4189
Kojto 99:dbbf35b96557 4190 /******************************* ADC Instances ********************************/
Kojto 99:dbbf35b96557 4191 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
Kojto 99:dbbf35b96557 4192
Kojto 99:dbbf35b96557 4193 /******************************* COMP Instances *******************************/
Kojto 99:dbbf35b96557 4194 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
Kojto 99:dbbf35b96557 4195 ((INSTANCE) == COMP2))
Kojto 99:dbbf35b96557 4196
Kojto 119:aae6fcc7d9bb 4197 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
Kojto 119:aae6fcc7d9bb 4198
Kojto 99:dbbf35b96557 4199 /******************************* CRC Instances ********************************/
Kojto 99:dbbf35b96557 4200 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
Kojto 99:dbbf35b96557 4201
Kojto 99:dbbf35b96557 4202 /******************************* DAC Instances *********************************/
Kojto 99:dbbf35b96557 4203 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC)
Kojto 99:dbbf35b96557 4204
Kojto 99:dbbf35b96557 4205 /******************************* DMA Instances *********************************/
Kojto 99:dbbf35b96557 4206 #define IS_DMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
Kojto 99:dbbf35b96557 4207 ((INSTANCE) == DMA1_Stream1) || \
Kojto 99:dbbf35b96557 4208 ((INSTANCE) == DMA1_Stream2) || \
Kojto 99:dbbf35b96557 4209 ((INSTANCE) == DMA1_Stream3) || \
Kojto 99:dbbf35b96557 4210 ((INSTANCE) == DMA1_Stream4) || \
Kojto 99:dbbf35b96557 4211 ((INSTANCE) == DMA1_Stream5) || \
Kojto 99:dbbf35b96557 4212 ((INSTANCE) == DMA1_Stream6) || \
Kojto 99:dbbf35b96557 4213 ((INSTANCE) == DMA1_Stream7))
Kojto 99:dbbf35b96557 4214
Kojto 99:dbbf35b96557 4215 /******************************* GPIO Instances *******************************/
Kojto 99:dbbf35b96557 4216 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 99:dbbf35b96557 4217 ((INSTANCE) == GPIOB) || \
Kojto 99:dbbf35b96557 4218 ((INSTANCE) == GPIOC) || \
Kojto 99:dbbf35b96557 4219 ((INSTANCE) == GPIOD) || \
Kojto 99:dbbf35b96557 4220 ((INSTANCE) == GPIOH))
Kojto 99:dbbf35b96557 4221
Kojto 119:aae6fcc7d9bb 4222 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
Kojto 119:aae6fcc7d9bb 4223 ((INSTANCE) == GPIOB) || \
Kojto 119:aae6fcc7d9bb 4224 ((INSTANCE) == GPIOC) || \
Kojto 119:aae6fcc7d9bb 4225 ((INSTANCE) == GPIOD) || \
Kojto 119:aae6fcc7d9bb 4226 ((INSTANCE) == GPIOH))
Kojto 119:aae6fcc7d9bb 4227
Kojto 99:dbbf35b96557 4228 /******************************** I2C Instances *******************************/
Kojto 99:dbbf35b96557 4229 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
Kojto 99:dbbf35b96557 4230 ((INSTANCE) == I2C2))
Kojto 99:dbbf35b96557 4231
Kojto 99:dbbf35b96557 4232 /******************************** I2S Instances *******************************/
Kojto 99:dbbf35b96557 4233 #define IS_I2S_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPI2)
Kojto 99:dbbf35b96557 4234
Kojto 99:dbbf35b96557 4235 /******************************* RNG Instances ********************************/
Kojto 99:dbbf35b96557 4236 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
Kojto 99:dbbf35b96557 4237
Kojto 99:dbbf35b96557 4238 /****************************** RTC Instances *********************************/
Kojto 99:dbbf35b96557 4239 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
Kojto 99:dbbf35b96557 4240
Kojto 99:dbbf35b96557 4241 /******************************** SMBUS Instances *****************************/
Kojto 99:dbbf35b96557 4242 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
Kojto 99:dbbf35b96557 4243
Kojto 99:dbbf35b96557 4244 /******************************** SPI Instances *******************************/
Kojto 99:dbbf35b96557 4245 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
Kojto 99:dbbf35b96557 4246 ((INSTANCE) == SPI2))
Kojto 99:dbbf35b96557 4247
Kojto 99:dbbf35b96557 4248 /****************** LPTIM Instances : All supported instances *****************/
Kojto 99:dbbf35b96557 4249 #define IS_LPTIM_INSTANCE(INSTANCE) ((INSTANCE) == LPTIM1)
Kojto 99:dbbf35b96557 4250
Kojto 99:dbbf35b96557 4251 /****************** TIM Instances : All supported instances *******************/
Kojto 99:dbbf35b96557 4252 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4253 ((INSTANCE) == TIM6) || \
Kojto 99:dbbf35b96557 4254 ((INSTANCE) == TIM21) || \
Kojto 99:dbbf35b96557 4255 ((INSTANCE) == TIM22))
Kojto 99:dbbf35b96557 4256
Kojto 119:aae6fcc7d9bb 4257 /****************** TIM Instances : supporting counting mode selection ********/
Kojto 119:aae6fcc7d9bb 4258 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 119:aae6fcc7d9bb 4259 ((INSTANCE) == TIM21) || \
Kojto 119:aae6fcc7d9bb 4260 ((INSTANCE) == TIM22))
Kojto 119:aae6fcc7d9bb 4261
Kojto 119:aae6fcc7d9bb 4262 /****************** TIM Instances : supporting clock division *****************/
Kojto 119:aae6fcc7d9bb 4263 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 119:aae6fcc7d9bb 4264 ((INSTANCE) == TIM21) || \
Kojto 119:aae6fcc7d9bb 4265 ((INSTANCE) == TIM22))
Kojto 119:aae6fcc7d9bb 4266
Kojto 119:aae6fcc7d9bb 4267 /****** TIM Instances : supporting external clock mode 1 for ETRF input *******/
Kojto 119:aae6fcc7d9bb 4268 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 119:aae6fcc7d9bb 4269 ((INSTANCE) == TIM21))
Kojto 119:aae6fcc7d9bb 4270
Kojto 119:aae6fcc7d9bb 4271 /****** TIM Instances : supporting external clock mode 2 for ETRF input *******/
Kojto 119:aae6fcc7d9bb 4272 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 119:aae6fcc7d9bb 4273 ((INSTANCE) == TIM21) || \
Kojto 119:aae6fcc7d9bb 4274 ((INSTANCE) == TIM22))
Kojto 119:aae6fcc7d9bb 4275
Kojto 119:aae6fcc7d9bb 4276 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
Kojto 119:aae6fcc7d9bb 4277 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 119:aae6fcc7d9bb 4278 ((INSTANCE) == TIM21))
Kojto 119:aae6fcc7d9bb 4279
Kojto 119:aae6fcc7d9bb 4280 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
Kojto 119:aae6fcc7d9bb 4281 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 119:aae6fcc7d9bb 4282 ((INSTANCE) == TIM21) || \
Kojto 119:aae6fcc7d9bb 4283 ((INSTANCE) == TIM22))
Kojto 119:aae6fcc7d9bb 4284
Kojto 99:dbbf35b96557 4285 /************* TIM Instances : at least 1 capture/compare channel *************/
Kojto 99:dbbf35b96557 4286 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4287 ((INSTANCE) == TIM21) || \
Kojto 99:dbbf35b96557 4288 ((INSTANCE) == TIM22))
Kojto 99:dbbf35b96557 4289
Kojto 99:dbbf35b96557 4290 /************ TIM Instances : at least 2 capture/compare channels *************/
Kojto 99:dbbf35b96557 4291 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4292 ((INSTANCE) == TIM21) || \
Kojto 99:dbbf35b96557 4293 ((INSTANCE) == TIM22))
Kojto 99:dbbf35b96557 4294
Kojto 99:dbbf35b96557 4295 /************ TIM Instances : at least 3 capture/compare channels *************/
Kojto 99:dbbf35b96557 4296 #define IS_TIM_CC3_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 99:dbbf35b96557 4297
Kojto 99:dbbf35b96557 4298 /************ TIM Instances : at least 4 capture/compare channels *************/
Kojto 99:dbbf35b96557 4299 #define IS_TIM_CC4_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 99:dbbf35b96557 4300
Kojto 99:dbbf35b96557 4301 /******************** TIM Instances : Advanced-control timers *****************/
Kojto 99:dbbf35b96557 4302
Kojto 99:dbbf35b96557 4303 /******************* TIM Instances : Timer input XOR function *****************/
Kojto 99:dbbf35b96557 4304 #define IS_TIM_XOR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 99:dbbf35b96557 4305
Kojto 99:dbbf35b96557 4306 /****************** TIM Instances : DMA requests generation (UDE) *************/
Kojto 99:dbbf35b96557 4307 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4308 ((INSTANCE) == TIM6))
Kojto 99:dbbf35b96557 4309
Kojto 99:dbbf35b96557 4310 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
Kojto 99:dbbf35b96557 4311 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 99:dbbf35b96557 4312
Kojto 99:dbbf35b96557 4313 /************ TIM Instances : DMA requests generation (COMDE) *****************/
Kojto 99:dbbf35b96557 4314 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 99:dbbf35b96557 4315
Kojto 99:dbbf35b96557 4316 /******************** TIM Instances : DMA burst feature ***********************/
Kojto 99:dbbf35b96557 4317 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 99:dbbf35b96557 4318
Kojto 99:dbbf35b96557 4319 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
Kojto 99:dbbf35b96557 4320 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4321 ((INSTANCE) == TIM6) || \
Kojto 99:dbbf35b96557 4322 ((INSTANCE) == TIM21) || \
Kojto 99:dbbf35b96557 4323 ((INSTANCE) == TIM22))
Kojto 99:dbbf35b96557 4324
Kojto 99:dbbf35b96557 4325 /*********** TIM Instances : Slave mode available (TIMx_SMCR available )*******/
Kojto 99:dbbf35b96557 4326 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4327 ((INSTANCE) == TIM21) || \
Kojto 99:dbbf35b96557 4328 ((INSTANCE) == TIM22))
Kojto 99:dbbf35b96557 4329
Kojto 99:dbbf35b96557 4330 /********************** TIM Instances : 32 bit Counter ************************/
Kojto 99:dbbf35b96557 4331
Kojto 99:dbbf35b96557 4332 /***************** TIM Instances : external trigger input availabe ************/
Kojto 99:dbbf35b96557 4333 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4334 ((INSTANCE) == TIM21) || \
Kojto 99:dbbf35b96557 4335 ((INSTANCE) == TIM22))
Kojto 99:dbbf35b96557 4336
Kojto 99:dbbf35b96557 4337 /****************** TIM Instances : remapping capability **********************/
Kojto 99:dbbf35b96557 4338 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 99:dbbf35b96557 4339 ((INSTANCE) == TIM21) || \
Kojto 99:dbbf35b96557 4340 ((INSTANCE) == TIM22))
Kojto 99:dbbf35b96557 4341
Kojto 119:aae6fcc7d9bb 4342 /****************** TIM Instances : supporting encoder interface **************/
Kojto 119:aae6fcc7d9bb 4343 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == TIM2) || \
Kojto 119:aae6fcc7d9bb 4344 ((INSTANCE) == TIM21) || \
Kojto 119:aae6fcc7d9bb 4345 ((INSTANCE) == TIM22))
Kojto 119:aae6fcc7d9bb 4346
Kojto 119:aae6fcc7d9bb 4347 /******************* TIM Instances : output(s) OCXEC register *****************/
Kojto 119:aae6fcc7d9bb 4348 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE) ((INSTANCE) == TIM2)
Kojto 119:aae6fcc7d9bb 4349
Kojto 99:dbbf35b96557 4350 /******************* TIM Instances : output(s) available **********************/
Kojto 99:dbbf35b96557 4351 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
Kojto 99:dbbf35b96557 4352 ((((INSTANCE) == TIM2) && \
Kojto 99:dbbf35b96557 4353 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 99:dbbf35b96557 4354 ((CHANNEL) == TIM_CHANNEL_2) || \
Kojto 99:dbbf35b96557 4355 ((CHANNEL) == TIM_CHANNEL_3) || \
Kojto 99:dbbf35b96557 4356 ((CHANNEL) == TIM_CHANNEL_4))) \
Kojto 99:dbbf35b96557 4357 || \
Kojto 99:dbbf35b96557 4358 (((INSTANCE) == TIM21) && \
Kojto 99:dbbf35b96557 4359 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 99:dbbf35b96557 4360 ((CHANNEL) == TIM_CHANNEL_2))) \
Kojto 99:dbbf35b96557 4361 || \
Kojto 99:dbbf35b96557 4362 (((INSTANCE) == TIM22) && \
Kojto 99:dbbf35b96557 4363 (((CHANNEL) == TIM_CHANNEL_1) || \
Kojto 99:dbbf35b96557 4364 ((CHANNEL) == TIM_CHANNEL_2))))
Kojto 99:dbbf35b96557 4365
Kojto 99:dbbf35b96557 4366 /******************** UART Instances : Asynchronous mode **********************/
Kojto 99:dbbf35b96557 4367 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4368 ((INSTANCE) == USART2) || \
Kojto 99:dbbf35b96557 4369 ((INSTANCE) == LPUART1))
Kojto 99:dbbf35b96557 4370
Kojto 99:dbbf35b96557 4371 /******************** USART Instances : Synchronous mode **********************/
Kojto 99:dbbf35b96557 4372 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4373 ((INSTANCE) == USART2))
Kojto 99:dbbf35b96557 4374
Kojto 99:dbbf35b96557 4375 /****************** USART Instances : Auto Baud Rate detection ****************/
Kojto 99:dbbf35b96557 4376
Kojto 99:dbbf35b96557 4377 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4378 ((INSTANCE) == USART2))
Kojto 99:dbbf35b96557 4379
Kojto 99:dbbf35b96557 4380 /******************** UART Instances : Half-Duplex mode **********************/
Kojto 99:dbbf35b96557 4381 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4382 ((INSTANCE) == USART2) || \
Kojto 99:dbbf35b96557 4383 ((INSTANCE) == LPUART1))
Kojto 99:dbbf35b96557 4384
Kojto 99:dbbf35b96557 4385 /******************** UART Instances : LIN mode **********************/
Kojto 99:dbbf35b96557 4386 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4387 ((INSTANCE) == USART2))
Kojto 99:dbbf35b96557 4388
Kojto 99:dbbf35b96557 4389 /******************** UART Instances : Wake-up from Stop mode **********************/
Kojto 99:dbbf35b96557 4390 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4391 ((INSTANCE) == USART2) || \
Kojto 99:dbbf35b96557 4392 ((INSTANCE) == LPUART1))
Kojto 99:dbbf35b96557 4393 /****************** UART Instances : Hardware Flow control ********************/
Kojto 99:dbbf35b96557 4394 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4395 ((INSTANCE) == USART2) || \
Kojto 99:dbbf35b96557 4396 ((INSTANCE) == LPUART1))
Kojto 99:dbbf35b96557 4397
Kojto 99:dbbf35b96557 4398 /********************* UART Instances : Smard card mode ***********************/
Kojto 99:dbbf35b96557 4399 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4400 ((INSTANCE) == USART2))
Kojto 99:dbbf35b96557 4401
Kojto 99:dbbf35b96557 4402 /*********************** UART Instances : IRDA mode ***************************/
Kojto 99:dbbf35b96557 4403 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
Kojto 99:dbbf35b96557 4404 ((INSTANCE) == USART2))
Kojto 99:dbbf35b96557 4405
Kojto 99:dbbf35b96557 4406 /****************************** IWDG Instances ********************************/
Kojto 99:dbbf35b96557 4407 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
Kojto 99:dbbf35b96557 4408
Kojto 99:dbbf35b96557 4409 /****************************** USB Instances ********************************/
Kojto 99:dbbf35b96557 4410 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
Kojto 99:dbbf35b96557 4411
Kojto 99:dbbf35b96557 4412 /****************************** WWDG Instances ********************************/
Kojto 99:dbbf35b96557 4413 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
Kojto 99:dbbf35b96557 4414
Kojto 99:dbbf35b96557 4415 /****************************** LCD Instances ********************************/
Kojto 99:dbbf35b96557 4416 #define IS_LCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LCD)
Kojto 99:dbbf35b96557 4417
Kojto 99:dbbf35b96557 4418 /**
Kojto 99:dbbf35b96557 4419 * @}
Kojto 99:dbbf35b96557 4420 */
Kojto 99:dbbf35b96557 4421
Kojto 99:dbbf35b96557 4422 /******************************************************************************/
Kojto 99:dbbf35b96557 4423 /* For a painless codes migration between the STM32L0xx device product */
Kojto 99:dbbf35b96557 4424 /* lines, the aliases defined below are put in place to overcome the */
Kojto 99:dbbf35b96557 4425 /* differences in the interrupt handlers and IRQn definitions. */
Kojto 99:dbbf35b96557 4426 /* No need to update developed interrupt code when moving across */
Kojto 99:dbbf35b96557 4427 /* product lines within the same STM32L0 Family */
Kojto 99:dbbf35b96557 4428 /******************************************************************************/
Kojto 99:dbbf35b96557 4429
Kojto 99:dbbf35b96557 4430 /* Aliases for __IRQn */
Kojto 99:dbbf35b96557 4431
Kojto 99:dbbf35b96557 4432 #define LPUART1_IRQn RNG_LPUART1_IRQn
Kojto 99:dbbf35b96557 4433 #define AES_LPUART1_IRQn RNG_LPUART1_IRQn
Kojto 99:dbbf35b96557 4434 #define AES_RNG_LPUART1_IRQn RNG_LPUART1_IRQn
Kojto 99:dbbf35b96557 4435 #define TIM6_IRQn TIM6_DAC_IRQn
Kojto 99:dbbf35b96557 4436 #define RCC_IRQn RCC_CRS_IRQn
Kojto 99:dbbf35b96557 4437
Kojto 99:dbbf35b96557 4438 /* Aliases for __IRQHandler */
Kojto 99:dbbf35b96557 4439 #define LPUART1_IRQHandler RNG_LPUART1_IRQHandler
Kojto 99:dbbf35b96557 4440 #define AES_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
Kojto 99:dbbf35b96557 4441 #define AES_RNG_LPUART1_IRQHandler RNG_LPUART1_IRQHandler
Kojto 99:dbbf35b96557 4442 #define TIM6_IRQHandler TIM6_DAC_IRQHandler
Kojto 99:dbbf35b96557 4443 #define RCC_IRQHandler RCC_CRS_IRQHandler
Kojto 99:dbbf35b96557 4444
Kojto 99:dbbf35b96557 4445 /**
Kojto 99:dbbf35b96557 4446 * @}
Kojto 99:dbbf35b96557 4447 */
Kojto 99:dbbf35b96557 4448
Kojto 99:dbbf35b96557 4449 /**
Kojto 99:dbbf35b96557 4450 * @}
Kojto 99:dbbf35b96557 4451 */
Kojto 99:dbbf35b96557 4452
Kojto 99:dbbf35b96557 4453 #ifdef __cplusplus
Kojto 99:dbbf35b96557 4454 }
Kojto 99:dbbf35b96557 4455 #endif /* __cplusplus */
Kojto 99:dbbf35b96557 4456
Kojto 99:dbbf35b96557 4457 #endif /* __STM32L053xx_H */
Kojto 99:dbbf35b96557 4458
Kojto 99:dbbf35b96557 4459
Kojto 99:dbbf35b96557 4460
Kojto 99:dbbf35b96557 4461 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/