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TARGET_EFM32WG_STK3800/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_emu.h@139:856d2700e60b, 2017-03-30 (annotated)
- Committer:
- <>
- Date:
- Thu Mar 30 13:26:47 2017 +0100
- Revision:
- 139:856d2700e60b
- Parent:
- 128:9bcdf88f62b0
Release 139 of the mbed library
Ports for Upcoming Targets
3934: [Silicon Labs] Update to HAL and devices https://github.com/ARMmbed/mbed-os/pull/3934
Known Issues
There is an issue with LPC1768 failing the 'Semihost file system' test with this release.
Fixes and Changes
3691: [TLS / hw acceleration] AES ECB for NUCLEO_F439ZI https://github.com/ARMmbed/mbed-os/pull/3691
3869: NCS36510: Default range changed from 0 to 950mV - ADC https://github.com/ARMmbed/mbed-os/pull/3869
3893: [STM32F7] Update STM32 Cube version v1.6.0 https://github.com/ARMmbed/mbed-os/pull/3893
3917: Fix mistake register setting in serial_format() https://github.com/ARMmbed/mbed-os/pull/3917
3927: [DELTA_DFBM_NQ620] Add RC calibration setting and revise mbed_overrides.c https://github.com/ARMmbed/mbed-os/pull/3927
3918: [NUC472/M453] Support unique locally administered MAC address and other driver updates https://github.com/ARMmbed/mbed-os/pull/3918
3920: Heap size adjusted to work for both tls-client and mbed-client https://github.com/ARMmbed/mbed-os/pull/3920
3969: NUCLEO_F302R8: Add missing PB_8/PB_9 CAN pins https://github.com/ARMmbed/mbed-os/pull/3969
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Kojto | 98:8ab26030e058 | 1 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 2 | * @file em_emu.h |
Kojto | 98:8ab26030e058 | 3 | * @brief Energy management unit (EMU) peripheral API |
<> | 139:856d2700e60b | 4 | * @version 5.1.2 |
Kojto | 98:8ab26030e058 | 5 | ******************************************************************************* |
Kojto | 98:8ab26030e058 | 6 | * @section License |
<> | 128:9bcdf88f62b0 | 7 | * <b>Copyright 2016 Silicon Laboratories, Inc. http://www.silabs.com</b> |
Kojto | 98:8ab26030e058 | 8 | ******************************************************************************* |
Kojto | 98:8ab26030e058 | 9 | * |
Kojto | 98:8ab26030e058 | 10 | * Permission is granted to anyone to use this software for any purpose, |
Kojto | 98:8ab26030e058 | 11 | * including commercial applications, and to alter it and redistribute it |
Kojto | 98:8ab26030e058 | 12 | * freely, subject to the following restrictions: |
Kojto | 98:8ab26030e058 | 13 | * |
Kojto | 98:8ab26030e058 | 14 | * 1. The origin of this software must not be misrepresented; you must not |
Kojto | 98:8ab26030e058 | 15 | * claim that you wrote the original software. |
Kojto | 98:8ab26030e058 | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
Kojto | 98:8ab26030e058 | 17 | * misrepresented as being the original software. |
Kojto | 98:8ab26030e058 | 18 | * 3. This notice may not be removed or altered from any source distribution. |
Kojto | 98:8ab26030e058 | 19 | * |
Kojto | 98:8ab26030e058 | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no |
Kojto | 98:8ab26030e058 | 21 | * obligation to support this Software. Silicon Labs is providing the |
Kojto | 98:8ab26030e058 | 22 | * Software "AS IS", with no express or implied warranties of any kind, |
Kojto | 98:8ab26030e058 | 23 | * including, but not limited to, any implied warranties of merchantability |
Kojto | 98:8ab26030e058 | 24 | * or fitness for any particular purpose or warranties against infringement |
Kojto | 98:8ab26030e058 | 25 | * of any proprietary rights of a third party. |
Kojto | 98:8ab26030e058 | 26 | * |
Kojto | 98:8ab26030e058 | 27 | * Silicon Labs will not be liable for any consequential, incidental, or |
Kojto | 98:8ab26030e058 | 28 | * special damages, or any other relief, or for any claim by any third party, |
Kojto | 98:8ab26030e058 | 29 | * arising from your use of this Software. |
Kojto | 98:8ab26030e058 | 30 | * |
Kojto | 98:8ab26030e058 | 31 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 32 | |
<> | 128:9bcdf88f62b0 | 33 | #ifndef EM_EMU_H |
<> | 128:9bcdf88f62b0 | 34 | #define EM_EMU_H |
Kojto | 98:8ab26030e058 | 35 | |
Kojto | 98:8ab26030e058 | 36 | #include "em_device.h" |
Kojto | 98:8ab26030e058 | 37 | #if defined( EMU_PRESENT ) |
Kojto | 98:8ab26030e058 | 38 | |
Kojto | 98:8ab26030e058 | 39 | #include <stdbool.h> |
Kojto | 113:f141b2784e32 | 40 | #include "em_bus.h" |
Kojto | 98:8ab26030e058 | 41 | |
Kojto | 98:8ab26030e058 | 42 | #ifdef __cplusplus |
Kojto | 98:8ab26030e058 | 43 | extern "C" { |
Kojto | 98:8ab26030e058 | 44 | #endif |
Kojto | 98:8ab26030e058 | 45 | |
Kojto | 98:8ab26030e058 | 46 | /***************************************************************************//** |
<> | 128:9bcdf88f62b0 | 47 | * @addtogroup emlib |
Kojto | 98:8ab26030e058 | 48 | * @{ |
Kojto | 98:8ab26030e058 | 49 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 50 | |
Kojto | 98:8ab26030e058 | 51 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 52 | * @addtogroup EMU |
Kojto | 98:8ab26030e058 | 53 | * @{ |
Kojto | 98:8ab26030e058 | 54 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 55 | |
Kojto | 98:8ab26030e058 | 56 | /******************************************************************************* |
Kojto | 98:8ab26030e058 | 57 | ******************************** ENUMS ************************************ |
Kojto | 98:8ab26030e058 | 58 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 59 | |
Kojto | 98:8ab26030e058 | 60 | #if defined( _EMU_EM4CONF_OSC_MASK ) |
Kojto | 98:8ab26030e058 | 61 | /** EM4 duty oscillator */ |
Kojto | 98:8ab26030e058 | 62 | typedef enum |
Kojto | 98:8ab26030e058 | 63 | { |
Kojto | 98:8ab26030e058 | 64 | /** Select ULFRCO as duty oscillator in EM4 */ |
Kojto | 98:8ab26030e058 | 65 | emuEM4Osc_ULFRCO = EMU_EM4CONF_OSC_ULFRCO, |
Kojto | 98:8ab26030e058 | 66 | /** Select LFXO as duty oscillator in EM4 */ |
Kojto | 98:8ab26030e058 | 67 | emuEM4Osc_LFXO = EMU_EM4CONF_OSC_LFXO, |
Kojto | 98:8ab26030e058 | 68 | /** Select LFRCO as duty oscillator in EM4 */ |
Kojto | 98:8ab26030e058 | 69 | emuEM4Osc_LFRCO = EMU_EM4CONF_OSC_LFRCO |
Kojto | 98:8ab26030e058 | 70 | } EMU_EM4Osc_TypeDef; |
Kojto | 98:8ab26030e058 | 71 | #endif |
Kojto | 98:8ab26030e058 | 72 | |
Kojto | 98:8ab26030e058 | 73 | #if defined( _EMU_BUCTRL_PROBE_MASK ) |
Kojto | 98:8ab26030e058 | 74 | /** Backup Power Voltage Probe types */ |
Kojto | 98:8ab26030e058 | 75 | typedef enum |
Kojto | 98:8ab26030e058 | 76 | { |
Kojto | 98:8ab26030e058 | 77 | /** Disable voltage probe */ |
Kojto | 98:8ab26030e058 | 78 | emuProbe_Disable = EMU_BUCTRL_PROBE_DISABLE, |
Kojto | 98:8ab26030e058 | 79 | /** Connect probe to VDD_DREG */ |
Kojto | 98:8ab26030e058 | 80 | emuProbe_VDDDReg = EMU_BUCTRL_PROBE_VDDDREG, |
Kojto | 98:8ab26030e058 | 81 | /** Connect probe to BU_IN */ |
Kojto | 98:8ab26030e058 | 82 | emuProbe_BUIN = EMU_BUCTRL_PROBE_BUIN, |
Kojto | 98:8ab26030e058 | 83 | /** Connect probe to BU_OUT */ |
Kojto | 98:8ab26030e058 | 84 | emuProbe_BUOUT = EMU_BUCTRL_PROBE_BUOUT |
Kojto | 98:8ab26030e058 | 85 | } EMU_Probe_TypeDef; |
Kojto | 98:8ab26030e058 | 86 | #endif |
Kojto | 98:8ab26030e058 | 87 | |
Kojto | 98:8ab26030e058 | 88 | #if defined( _EMU_PWRCONF_PWRRES_MASK ) |
Kojto | 98:8ab26030e058 | 89 | /** Backup Power Domain resistor selection */ |
Kojto | 98:8ab26030e058 | 90 | typedef enum |
Kojto | 98:8ab26030e058 | 91 | { |
Kojto | 98:8ab26030e058 | 92 | /** Main power and backup power connected with RES0 series resistance */ |
Kojto | 98:8ab26030e058 | 93 | emuRes_Res0 = EMU_PWRCONF_PWRRES_RES0, |
Kojto | 98:8ab26030e058 | 94 | /** Main power and backup power connected with RES1 series resistance */ |
Kojto | 98:8ab26030e058 | 95 | emuRes_Res1 = EMU_PWRCONF_PWRRES_RES1, |
Kojto | 98:8ab26030e058 | 96 | /** Main power and backup power connected with RES2 series resistance */ |
Kojto | 98:8ab26030e058 | 97 | emuRes_Res2 = EMU_PWRCONF_PWRRES_RES2, |
Kojto | 98:8ab26030e058 | 98 | /** Main power and backup power connected with RES3 series resistance */ |
Kojto | 98:8ab26030e058 | 99 | emuRes_Res3 = EMU_PWRCONF_PWRRES_RES3, |
Kojto | 98:8ab26030e058 | 100 | } EMU_Resistor_TypeDef; |
Kojto | 98:8ab26030e058 | 101 | #endif |
Kojto | 98:8ab26030e058 | 102 | |
Kojto | 98:8ab26030e058 | 103 | #if defined( BU_PRESENT ) |
Kojto | 98:8ab26030e058 | 104 | /** Backup Power Domain power connection */ |
Kojto | 98:8ab26030e058 | 105 | typedef enum |
Kojto | 98:8ab26030e058 | 106 | { |
Kojto | 98:8ab26030e058 | 107 | /** No connection between main and backup power */ |
Kojto | 98:8ab26030e058 | 108 | emuPower_None = EMU_BUINACT_PWRCON_NONE, |
Kojto | 98:8ab26030e058 | 109 | /** Main power and backup power connected through diode, |
Kojto | 98:8ab26030e058 | 110 | allowing current from backup to main only */ |
Kojto | 98:8ab26030e058 | 111 | emuPower_BUMain = EMU_BUINACT_PWRCON_BUMAIN, |
Kojto | 98:8ab26030e058 | 112 | /** Main power and backup power connected through diode, |
Kojto | 98:8ab26030e058 | 113 | allowing current from main to backup only */ |
Kojto | 98:8ab26030e058 | 114 | emuPower_MainBU = EMU_BUINACT_PWRCON_MAINBU, |
Kojto | 98:8ab26030e058 | 115 | /** Main power and backup power connected without diode */ |
Kojto | 98:8ab26030e058 | 116 | emuPower_NoDiode = EMU_BUINACT_PWRCON_NODIODE, |
Kojto | 98:8ab26030e058 | 117 | } EMU_Power_TypeDef; |
Kojto | 98:8ab26030e058 | 118 | #endif |
Kojto | 98:8ab26030e058 | 119 | |
Kojto | 98:8ab26030e058 | 120 | /** BOD threshold setting selector, active or inactive mode */ |
Kojto | 98:8ab26030e058 | 121 | typedef enum |
Kojto | 98:8ab26030e058 | 122 | { |
Kojto | 98:8ab26030e058 | 123 | /** Configure BOD threshold for active mode */ |
Kojto | 98:8ab26030e058 | 124 | emuBODMode_Active, |
Kojto | 98:8ab26030e058 | 125 | /** Configure BOD threshold for inactive mode */ |
Kojto | 98:8ab26030e058 | 126 | emuBODMode_Inactive, |
Kojto | 98:8ab26030e058 | 127 | } EMU_BODMode_TypeDef; |
Kojto | 98:8ab26030e058 | 128 | |
Kojto | 113:f141b2784e32 | 129 | #if defined( _EMU_EM4CTRL_EM4STATE_MASK ) |
Kojto | 113:f141b2784e32 | 130 | /** EM4 modes */ |
Kojto | 113:f141b2784e32 | 131 | typedef enum |
Kojto | 113:f141b2784e32 | 132 | { |
Kojto | 113:f141b2784e32 | 133 | /** EM4 Hibernate */ |
Kojto | 113:f141b2784e32 | 134 | emuEM4Hibernate = EMU_EM4CTRL_EM4STATE_EM4H, |
Kojto | 113:f141b2784e32 | 135 | /** EM4 Shutoff */ |
Kojto | 113:f141b2784e32 | 136 | emuEM4Shutoff = EMU_EM4CTRL_EM4STATE_EM4S, |
Kojto | 113:f141b2784e32 | 137 | } EMU_EM4State_TypeDef; |
Kojto | 113:f141b2784e32 | 138 | #endif |
Kojto | 98:8ab26030e058 | 139 | |
Kojto | 98:8ab26030e058 | 140 | |
Kojto | 113:f141b2784e32 | 141 | #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK ) |
Kojto | 113:f141b2784e32 | 142 | typedef enum |
Kojto | 113:f141b2784e32 | 143 | { |
Kojto | 113:f141b2784e32 | 144 | /** No Retention: Pads enter reset state when entering EM4 */ |
Kojto | 113:f141b2784e32 | 145 | emuPinRetentionDisable = EMU_EM4CTRL_EM4IORETMODE_DISABLE, |
Kojto | 113:f141b2784e32 | 146 | /** Retention through EM4: Pads enter reset state when exiting EM4 */ |
Kojto | 113:f141b2784e32 | 147 | emuPinRetentionEm4Exit = EMU_EM4CTRL_EM4IORETMODE_EM4EXIT, |
Kojto | 113:f141b2784e32 | 148 | /** Retention through EM4 and wakeup: call EMU_UnlatchPinRetention() to |
Kojto | 113:f141b2784e32 | 149 | release pins from retention after EM4 wakeup */ |
Kojto | 113:f141b2784e32 | 150 | emuPinRetentionLatch = EMU_EM4CTRL_EM4IORETMODE_SWUNLATCH, |
Kojto | 113:f141b2784e32 | 151 | } EMU_EM4PinRetention_TypeDef; |
Kojto | 113:f141b2784e32 | 152 | #endif |
Kojto | 113:f141b2784e32 | 153 | |
<> | 139:856d2700e60b | 154 | /** Power configurations. DCDC-to-DVDD is currently the only supported mode. */ |
Kojto | 113:f141b2784e32 | 155 | typedef enum |
Kojto | 113:f141b2784e32 | 156 | { |
Kojto | 113:f141b2784e32 | 157 | /** DCDC is connected to DVDD */ |
<> | 139:856d2700e60b | 158 | emuPowerConfig_DcdcToDvdd, |
Kojto | 113:f141b2784e32 | 159 | } EMU_PowerConfig_TypeDef; |
<> | 139:856d2700e60b | 160 | |
Kojto | 113:f141b2784e32 | 161 | |
Kojto | 113:f141b2784e32 | 162 | #if defined( _EMU_DCDCCTRL_MASK ) |
Kojto | 113:f141b2784e32 | 163 | /** DCDC operating modes */ |
Kojto | 113:f141b2784e32 | 164 | typedef enum |
Kojto | 113:f141b2784e32 | 165 | { |
Kojto | 113:f141b2784e32 | 166 | /** DCDC regulator bypass */ |
Kojto | 113:f141b2784e32 | 167 | emuDcdcMode_Bypass = EMU_DCDCCTRL_DCDCMODE_BYPASS, |
Kojto | 113:f141b2784e32 | 168 | /** DCDC low-noise mode */ |
Kojto | 113:f141b2784e32 | 169 | emuDcdcMode_LowNoise = EMU_DCDCCTRL_DCDCMODE_LOWNOISE, |
<> | 128:9bcdf88f62b0 | 170 | #if defined(_EMU_DCDCLPEM01CFG_MASK) |
<> | 128:9bcdf88f62b0 | 171 | /** DCDC low-power mode */ |
<> | 128:9bcdf88f62b0 | 172 | emuDcdcMode_LowPower = EMU_DCDCCTRL_DCDCMODE_LOWPOWER, |
<> | 128:9bcdf88f62b0 | 173 | #endif |
Kojto | 113:f141b2784e32 | 174 | } EMU_DcdcMode_TypeDef; |
Kojto | 113:f141b2784e32 | 175 | #endif |
Kojto | 113:f141b2784e32 | 176 | |
<> | 139:856d2700e60b | 177 | #if defined( _EMU_DCDCCTRL_MASK ) |
<> | 139:856d2700e60b | 178 | /** DCDC conduction modes */ |
<> | 139:856d2700e60b | 179 | typedef enum |
<> | 139:856d2700e60b | 180 | { |
<> | 139:856d2700e60b | 181 | /** DCDC Low-Noise Continuous Conduction Mode (CCM). EFR32 interference minimization |
<> | 139:856d2700e60b | 182 | features are available in this mode. */ |
<> | 139:856d2700e60b | 183 | emuDcdcConductionMode_ContinuousLN, |
<> | 139:856d2700e60b | 184 | /** DCDC Low-Noise Discontinuous Conduction Mode (DCM). This mode should be used for EFM32 or |
<> | 139:856d2700e60b | 185 | when the EFR32 radio is not enabled. */ |
<> | 139:856d2700e60b | 186 | emuDcdcConductionMode_DiscontinuousLN, |
<> | 139:856d2700e60b | 187 | } EMU_DcdcConductionMode_TypeDef; |
<> | 139:856d2700e60b | 188 | #endif |
<> | 139:856d2700e60b | 189 | |
Kojto | 113:f141b2784e32 | 190 | #if defined( _EMU_PWRCTRL_MASK ) |
Kojto | 113:f141b2784e32 | 191 | /** DCDC to DVDD mode analog peripheral power supply select */ |
Kojto | 113:f141b2784e32 | 192 | typedef enum |
Kojto | 113:f141b2784e32 | 193 | { |
Kojto | 113:f141b2784e32 | 194 | /** Select AVDD as analog power supply. Typically lower noise, but less energy efficient. */ |
Kojto | 113:f141b2784e32 | 195 | emuDcdcAnaPeripheralPower_AVDD = EMU_PWRCTRL_ANASW_AVDD, |
Kojto | 113:f141b2784e32 | 196 | /** Select DCDC (DVDD) as analog power supply. Typically more energy efficient, but more noise. */ |
Kojto | 113:f141b2784e32 | 197 | emuDcdcAnaPeripheralPower_DCDC = EMU_PWRCTRL_ANASW_DVDD |
Kojto | 113:f141b2784e32 | 198 | } EMU_DcdcAnaPeripheralPower_TypeDef; |
Kojto | 113:f141b2784e32 | 199 | #endif |
Kojto | 113:f141b2784e32 | 200 | |
Kojto | 113:f141b2784e32 | 201 | #if defined( _EMU_DCDCMISCCTRL_MASK ) |
<> | 128:9bcdf88f62b0 | 202 | /** DCDC Forced CCM and reverse current limiter control. Positive values have unit mA. */ |
<> | 128:9bcdf88f62b0 | 203 | typedef int16_t EMU_DcdcLnReverseCurrentControl_TypeDef; |
<> | 128:9bcdf88f62b0 | 204 | |
<> | 128:9bcdf88f62b0 | 205 | /** High efficiency mode. EMU_DCDCZDETCTRL_ZDETILIMSEL is "don't care". */ |
<> | 128:9bcdf88f62b0 | 206 | #define emuDcdcLnHighEfficiency -1 |
<> | 128:9bcdf88f62b0 | 207 | |
<> | 139:856d2700e60b | 208 | /** Default reverse current for fast transient response mode (low noise). */ |
<> | 128:9bcdf88f62b0 | 209 | #define emuDcdcLnFastTransient 160 |
Kojto | 113:f141b2784e32 | 210 | #endif |
<> | 128:9bcdf88f62b0 | 211 | |
Kojto | 113:f141b2784e32 | 212 | |
Kojto | 113:f141b2784e32 | 213 | #if defined( _EMU_DCDCCTRL_MASK ) |
Kojto | 113:f141b2784e32 | 214 | /** DCDC Low-noise RCO band select */ |
Kojto | 113:f141b2784e32 | 215 | typedef enum |
Kojto | 113:f141b2784e32 | 216 | { |
Kojto | 113:f141b2784e32 | 217 | /** Set RCO to 3MHz */ |
<> | 128:9bcdf88f62b0 | 218 | emuDcdcLnRcoBand_3MHz = 0, |
Kojto | 113:f141b2784e32 | 219 | /** Set RCO to 4MHz */ |
<> | 128:9bcdf88f62b0 | 220 | emuDcdcLnRcoBand_4MHz = 1, |
Kojto | 113:f141b2784e32 | 221 | /** Set RCO to 5MHz */ |
<> | 128:9bcdf88f62b0 | 222 | emuDcdcLnRcoBand_5MHz = 2, |
Kojto | 113:f141b2784e32 | 223 | /** Set RCO to 6MHz */ |
<> | 128:9bcdf88f62b0 | 224 | emuDcdcLnRcoBand_6MHz = 3, |
Kojto | 113:f141b2784e32 | 225 | /** Set RCO to 7MHz */ |
<> | 128:9bcdf88f62b0 | 226 | emuDcdcLnRcoBand_7MHz = 4, |
Kojto | 113:f141b2784e32 | 227 | /** Set RCO to 8MHz */ |
<> | 128:9bcdf88f62b0 | 228 | emuDcdcLnRcoBand_8MHz = 5, |
Kojto | 113:f141b2784e32 | 229 | /** Set RCO to 9MHz */ |
<> | 128:9bcdf88f62b0 | 230 | emuDcdcLnRcoBand_9MHz = 6, |
Kojto | 113:f141b2784e32 | 231 | /** Set RCO to 10MHz */ |
<> | 128:9bcdf88f62b0 | 232 | emuDcdcLnRcoBand_10MHz = 7, |
Kojto | 113:f141b2784e32 | 233 | } EMU_DcdcLnRcoBand_TypeDef; |
Kojto | 113:f141b2784e32 | 234 | |
<> | 128:9bcdf88f62b0 | 235 | /** @cond DO_NOT_INCLUDE_WITH_DOXYGEN */ |
<> | 128:9bcdf88f62b0 | 236 | /* Deprecated. */ |
<> | 128:9bcdf88f62b0 | 237 | #define EMU_DcdcLnRcoBand_3MHz emuDcdcLnRcoBand_3MHz |
<> | 128:9bcdf88f62b0 | 238 | #define EMU_DcdcLnRcoBand_4MHz emuDcdcLnRcoBand_4MHz |
<> | 128:9bcdf88f62b0 | 239 | #define EMU_DcdcLnRcoBand_5MHz emuDcdcLnRcoBand_5MHz |
<> | 128:9bcdf88f62b0 | 240 | #define EMU_DcdcLnRcoBand_6MHz emuDcdcLnRcoBand_6MHz |
<> | 128:9bcdf88f62b0 | 241 | #define EMU_DcdcLnRcoBand_7MHz emuDcdcLnRcoBand_7MHz |
<> | 128:9bcdf88f62b0 | 242 | #define EMU_DcdcLnRcoBand_8MHz emuDcdcLnRcoBand_8MHz |
<> | 128:9bcdf88f62b0 | 243 | #define EMU_DcdcLnRcoBand_9MHz emuDcdcLnRcoBand_9MHz |
<> | 128:9bcdf88f62b0 | 244 | #define EMU_DcdcLnRcoBand_10MHz emuDcdcLnRcoBand_10MHz |
<> | 128:9bcdf88f62b0 | 245 | /** @endcond */ |
Kojto | 113:f141b2784e32 | 246 | #endif |
Kojto | 113:f141b2784e32 | 247 | |
<> | 128:9bcdf88f62b0 | 248 | |
<> | 128:9bcdf88f62b0 | 249 | #if defined( _EMU_DCDCCTRL_MASK ) |
<> | 128:9bcdf88f62b0 | 250 | /** DCDC Low Noise Compensator Control register. */ |
<> | 128:9bcdf88f62b0 | 251 | typedef enum |
<> | 128:9bcdf88f62b0 | 252 | { |
<> | 128:9bcdf88f62b0 | 253 | /** DCDC capacitor is 1uF. */ |
<> | 128:9bcdf88f62b0 | 254 | emuDcdcLnCompCtrl_1u0F, |
<> | 128:9bcdf88f62b0 | 255 | /** DCDC capacitor is 4.7uF. */ |
<> | 128:9bcdf88f62b0 | 256 | emuDcdcLnCompCtrl_4u7F, |
<> | 128:9bcdf88f62b0 | 257 | } EMU_DcdcLnCompCtrl_TypeDef; |
<> | 128:9bcdf88f62b0 | 258 | #endif |
<> | 128:9bcdf88f62b0 | 259 | |
<> | 128:9bcdf88f62b0 | 260 | |
Kojto | 113:f141b2784e32 | 261 | #if defined( EMU_STATUS_VMONRDY ) |
Kojto | 113:f141b2784e32 | 262 | /** VMON channels */ |
Kojto | 113:f141b2784e32 | 263 | typedef enum |
Kojto | 113:f141b2784e32 | 264 | { |
Kojto | 113:f141b2784e32 | 265 | emuVmonChannel_AVDD, |
Kojto | 113:f141b2784e32 | 266 | emuVmonChannel_ALTAVDD, |
Kojto | 113:f141b2784e32 | 267 | emuVmonChannel_DVDD, |
Kojto | 113:f141b2784e32 | 268 | emuVmonChannel_IOVDD0 |
Kojto | 113:f141b2784e32 | 269 | } EMU_VmonChannel_TypeDef; |
Kojto | 113:f141b2784e32 | 270 | #endif /* EMU_STATUS_VMONRDY */ |
Kojto | 113:f141b2784e32 | 271 | |
<> | 139:856d2700e60b | 272 | #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) |
<> | 128:9bcdf88f62b0 | 273 | /** Bias mode configurations */ |
<> | 128:9bcdf88f62b0 | 274 | typedef enum |
<> | 128:9bcdf88f62b0 | 275 | { |
<> | 128:9bcdf88f62b0 | 276 | emuBiasMode_1KHz, |
<> | 128:9bcdf88f62b0 | 277 | emuBiasMode_4KHz, |
<> | 128:9bcdf88f62b0 | 278 | emuBiasMode_Continuous |
<> | 128:9bcdf88f62b0 | 279 | } EMU_BiasMode_TypeDef; |
<> | 128:9bcdf88f62b0 | 280 | #endif |
<> | 128:9bcdf88f62b0 | 281 | |
<> | 139:856d2700e60b | 282 | #if defined( _EMU_CMD_EM01VSCALE0_MASK ) |
<> | 139:856d2700e60b | 283 | /** Supported EM0/1 Voltage Scaling Levels */ |
<> | 139:856d2700e60b | 284 | typedef enum |
<> | 139:856d2700e60b | 285 | { |
<> | 139:856d2700e60b | 286 | /** High-performance voltage level. HF clock can be set to any frequency. */ |
<> | 139:856d2700e60b | 287 | emuVScaleEM01_HighPerformance = _EMU_STATUS_VSCALE_VSCALE2, |
<> | 139:856d2700e60b | 288 | /** Low-power optimized voltage level. The HF clock must be limited |
<> | 139:856d2700e60b | 289 | to @ref CMU_VSCALEEM01_LOWPOWER_VOLTAGE_CLOCK_MAX Hz at this voltage. |
<> | 139:856d2700e60b | 290 | EM0/1 voltage scaling is applied when the core clock frequency is |
<> | 139:856d2700e60b | 291 | changed from @ref CMU or when calling @ref EMU_EM01Init() when the HF |
<> | 139:856d2700e60b | 292 | clock is already below the limit. */ |
<> | 139:856d2700e60b | 293 | emuVScaleEM01_LowPower = _EMU_STATUS_VSCALE_VSCALE0, |
<> | 139:856d2700e60b | 294 | } EMU_VScaleEM01_TypeDef; |
<> | 139:856d2700e60b | 295 | #endif |
<> | 139:856d2700e60b | 296 | |
<> | 139:856d2700e60b | 297 | #if defined( _EMU_CTRL_EM23VSCALE_MASK ) |
<> | 139:856d2700e60b | 298 | /** Supported EM2/3 Voltage Scaling Levels */ |
<> | 139:856d2700e60b | 299 | typedef enum |
<> | 139:856d2700e60b | 300 | { |
<> | 139:856d2700e60b | 301 | /** Fast-wakeup voltage level. */ |
<> | 139:856d2700e60b | 302 | emuVScaleEM23_FastWakeup = _EMU_CTRL_EM23VSCALE_VSCALE2, |
<> | 139:856d2700e60b | 303 | /** Low-power optimized voltage level. Using this voltage level in EM2 and 3 |
<> | 139:856d2700e60b | 304 | adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled |
<> | 139:856d2700e60b | 305 | up to @ref emuVScaleEM01_HighPerformance on EM2 or 3 exit. */ |
<> | 139:856d2700e60b | 306 | emuVScaleEM23_LowPower = _EMU_CTRL_EM23VSCALE_VSCALE0, |
<> | 139:856d2700e60b | 307 | } EMU_VScaleEM23_TypeDef; |
<> | 139:856d2700e60b | 308 | #endif |
<> | 139:856d2700e60b | 309 | |
<> | 139:856d2700e60b | 310 | #if defined( _EMU_CTRL_EM4HVSCALE_MASK ) |
<> | 139:856d2700e60b | 311 | /** Supported EM4H Voltage Scaling Levels */ |
<> | 139:856d2700e60b | 312 | typedef enum |
<> | 139:856d2700e60b | 313 | { |
<> | 139:856d2700e60b | 314 | /** Fast-wakeup voltage level. */ |
<> | 139:856d2700e60b | 315 | emuVScaleEM4H_FastWakeup = _EMU_CTRL_EM4HVSCALE_VSCALE2, |
<> | 139:856d2700e60b | 316 | /** Low-power optimized voltage level. Using this voltage level in EM4H |
<> | 139:856d2700e60b | 317 | adds 20-25us to wakeup time if the EM0 and 1 voltage must be scaled |
<> | 139:856d2700e60b | 318 | up to @ref emuVScaleEM01_HighPerformance on EM4H exit. */ |
<> | 139:856d2700e60b | 319 | emuVScaleEM4H_LowPower = _EMU_CTRL_EM4HVSCALE_VSCALE0, |
<> | 139:856d2700e60b | 320 | } EMU_VScaleEM4H_TypeDef; |
<> | 139:856d2700e60b | 321 | #endif |
<> | 139:856d2700e60b | 322 | |
<> | 139:856d2700e60b | 323 | #if defined(_EMU_EM23PERNORETAINCTRL_MASK) |
<> | 139:856d2700e60b | 324 | /** Peripheral EM2 and 3 retention control */ |
<> | 139:856d2700e60b | 325 | typedef enum |
<> | 139:856d2700e60b | 326 | { |
<> | 139:856d2700e60b | 327 | emuPeripheralRetention_LEUART0 = _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK, /* Select LEUART0 retention control */ |
<> | 139:856d2700e60b | 328 | emuPeripheralRetention_CSEN = _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK, /* Select CSEN retention control */ |
<> | 139:856d2700e60b | 329 | emuPeripheralRetention_LESENSE0 = _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK, /* Select LESENSE0 retention control */ |
<> | 139:856d2700e60b | 330 | emuPeripheralRetention_LETIMER0 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK, /* Select LETIMER0 retention control */ |
<> | 139:856d2700e60b | 331 | emuPeripheralRetention_ADC0 = _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK, /* Select ADC0 retention control */ |
<> | 139:856d2700e60b | 332 | emuPeripheralRetention_IDAC0 = _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK, /* Select IDAC0 retention control */ |
<> | 139:856d2700e60b | 333 | emuPeripheralRetention_VDAC0 = _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK, /* Select DAC0 retention control */ |
<> | 139:856d2700e60b | 334 | emuPeripheralRetention_I2C1 = _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select I2C1 retention control */ |
<> | 139:856d2700e60b | 335 | emuPeripheralRetention_I2C0 = _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK, /* Select I2C0 retention control */ |
<> | 139:856d2700e60b | 336 | emuPeripheralRetention_ACMP1 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK, /* Select ACMP1 retention control */ |
<> | 139:856d2700e60b | 337 | emuPeripheralRetention_ACMP0 = _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK, /* Select ACMP0 retention control */ |
<> | 139:856d2700e60b | 338 | #if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) |
<> | 139:856d2700e60b | 339 | emuPeripheralRetention_PCNT2 = _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK, /* Select PCNT2 retention control */ |
<> | 139:856d2700e60b | 340 | emuPeripheralRetention_PCNT1 = _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK, /* Select PCNT1 retention control */ |
<> | 139:856d2700e60b | 341 | #endif |
<> | 139:856d2700e60b | 342 | emuPeripheralRetention_PCNT0 = _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK, /* Select PCNT0 retention control */ |
<> | 139:856d2700e60b | 343 | |
<> | 139:856d2700e60b | 344 | emuPeripheralRetention_D1 = _EMU_EM23PERNORETAINCTRL_LETIMER0DIS_MASK |
<> | 139:856d2700e60b | 345 | | _EMU_EM23PERNORETAINCTRL_PCNT0DIS_MASK |
<> | 139:856d2700e60b | 346 | | _EMU_EM23PERNORETAINCTRL_ADC0DIS_MASK |
<> | 139:856d2700e60b | 347 | | _EMU_EM23PERNORETAINCTRL_ACMP0DIS_MASK |
<> | 139:856d2700e60b | 348 | | _EMU_EM23PERNORETAINCTRL_LESENSE0DIS_MASK,/* Select all peripherals in domain 1 */ |
<> | 139:856d2700e60b | 349 | emuPeripheralRetention_D2 = _EMU_EM23PERNORETAINCTRL_ACMP1DIS_MASK |
<> | 139:856d2700e60b | 350 | | _EMU_EM23PERNORETAINCTRL_IDAC0DIS_MASK |
<> | 139:856d2700e60b | 351 | | _EMU_EM23PERNORETAINCTRL_DAC0DIS_MASK |
<> | 139:856d2700e60b | 352 | | _EMU_EM23PERNORETAINCTRL_CSENDIS_MASK |
<> | 139:856d2700e60b | 353 | | _EMU_EM23PERNORETAINCTRL_LEUART0DIS_MASK |
<> | 139:856d2700e60b | 354 | #if defined( _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK ) |
<> | 139:856d2700e60b | 355 | | _EMU_EM23PERNORETAINCTRL_PCNT1DIS_MASK |
<> | 139:856d2700e60b | 356 | | _EMU_EM23PERNORETAINCTRL_PCNT2DIS_MASK |
<> | 139:856d2700e60b | 357 | #endif |
<> | 139:856d2700e60b | 358 | | _EMU_EM23PERNORETAINCTRL_I2C0DIS_MASK |
<> | 139:856d2700e60b | 359 | | _EMU_EM23PERNORETAINCTRL_I2C1DIS_MASK, /* Select all peripherals in domain 2 */ |
<> | 139:856d2700e60b | 360 | emuPeripheralRetention_ALL = emuPeripheralRetention_D1 |
<> | 139:856d2700e60b | 361 | | emuPeripheralRetention_D2, /* Select all peripherals with retention control */ |
<> | 139:856d2700e60b | 362 | } EMU_PeripheralRetention_TypeDef; |
<> | 139:856d2700e60b | 363 | #endif |
<> | 139:856d2700e60b | 364 | |
Kojto | 98:8ab26030e058 | 365 | /******************************************************************************* |
Kojto | 98:8ab26030e058 | 366 | ******************************* STRUCTS *********************************** |
Kojto | 98:8ab26030e058 | 367 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 368 | |
<> | 139:856d2700e60b | 369 | #if defined( _EMU_CMD_EM01VSCALE0_MASK ) |
<> | 139:856d2700e60b | 370 | /** EM0 and 1 initialization structure. Voltage scaling is applied when |
<> | 139:856d2700e60b | 371 | the core clock frequency is changed from @ref CMU. EM0 an 1 emuVScaleEM01_HighPerformance |
<> | 139:856d2700e60b | 372 | is always enabled. */ |
Kojto | 98:8ab26030e058 | 373 | typedef struct |
Kojto | 98:8ab26030e058 | 374 | { |
<> | 139:856d2700e60b | 375 | bool vScaleEM01LowPowerVoltageEnable; /**< EM0/1 low power voltage status */ |
<> | 139:856d2700e60b | 376 | } EMU_EM01Init_TypeDef; |
<> | 139:856d2700e60b | 377 | #endif |
<> | 139:856d2700e60b | 378 | |
<> | 139:856d2700e60b | 379 | #if defined( _EMU_CMD_EM01VSCALE0_MASK ) |
<> | 139:856d2700e60b | 380 | /** Default initialization of EM0 and 1 configuration */ |
<> | 139:856d2700e60b | 381 | #define EMU_EM01INIT_DEFAULT \ |
<> | 139:856d2700e60b | 382 | { \ |
<> | 139:856d2700e60b | 383 | false /** Do not scale down in EM0/1 */ \ |
<> | 139:856d2700e60b | 384 | } |
<> | 139:856d2700e60b | 385 | #endif |
<> | 139:856d2700e60b | 386 | |
<> | 139:856d2700e60b | 387 | /** EM2 and 3 initialization structure */ |
<> | 139:856d2700e60b | 388 | typedef struct |
<> | 139:856d2700e60b | 389 | { |
<> | 139:856d2700e60b | 390 | bool em23VregFullEn; /**< Enable full VREG drive strength in EM2/3 */ |
<> | 139:856d2700e60b | 391 | #if defined( _EMU_CTRL_EM23VSCALE_MASK ) |
<> | 139:856d2700e60b | 392 | EMU_VScaleEM23_TypeDef vScaleEM23Voltage; /**< EM2/3 voltage scaling level */ |
<> | 139:856d2700e60b | 393 | #endif |
Kojto | 98:8ab26030e058 | 394 | } EMU_EM23Init_TypeDef; |
Kojto | 98:8ab26030e058 | 395 | |
Kojto | 98:8ab26030e058 | 396 | /** Default initialization of EM2 and 3 configuration */ |
<> | 139:856d2700e60b | 397 | #if defined( _EMU_CTRL_EM4HVSCALE_MASK ) |
<> | 139:856d2700e60b | 398 | #define EMU_EM23INIT_DEFAULT \ |
<> | 139:856d2700e60b | 399 | { \ |
<> | 139:856d2700e60b | 400 | false, /* Reduced voltage regulator drive strength in EM2/3 */ \ |
<> | 139:856d2700e60b | 401 | emuVScaleEM23_FastWakeup, /* Do not scale down in EM2/3 */ \ |
<> | 139:856d2700e60b | 402 | } |
<> | 139:856d2700e60b | 403 | #else |
<> | 139:856d2700e60b | 404 | #define EMU_EM23INIT_DEFAULT \ |
<> | 139:856d2700e60b | 405 | { \ |
<> | 139:856d2700e60b | 406 | false, /* Reduced voltage regulator drive strength in EM2/3 */ \ |
<> | 139:856d2700e60b | 407 | } |
<> | 139:856d2700e60b | 408 | #endif |
Kojto | 98:8ab26030e058 | 409 | |
Kojto | 113:f141b2784e32 | 410 | #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) |
<> | 139:856d2700e60b | 411 | /** EM4 initialization structure */ |
Kojto | 98:8ab26030e058 | 412 | typedef struct |
Kojto | 98:8ab26030e058 | 413 | { |
Kojto | 113:f141b2784e32 | 414 | #if defined( _EMU_EM4CONF_MASK ) |
<> | 139:856d2700e60b | 415 | /* Init parameters for platforms with EMU->EM4CONF register (Series 0) */ |
<> | 139:856d2700e60b | 416 | bool lockConfig; /**< Lock configuration of regulator, BOD and oscillator */ |
<> | 139:856d2700e60b | 417 | bool buBodRstDis; /**< When set, no reset will be asserted due to Brownout when in EM4 */ |
<> | 139:856d2700e60b | 418 | EMU_EM4Osc_TypeDef osc; /**< EM4 duty oscillator */ |
<> | 139:856d2700e60b | 419 | bool buRtcWakeup; /**< Wake up on EM4 BURTC interrupt */ |
<> | 139:856d2700e60b | 420 | bool vreg; /**< Enable EM4 voltage regulator */ |
Kojto | 113:f141b2784e32 | 421 | #elif defined( _EMU_EM4CTRL_MASK ) |
<> | 139:856d2700e60b | 422 | /* Init parameters for platforms with EMU->EM4CTRL register (Series 1) */ |
Kojto | 113:f141b2784e32 | 423 | bool retainLfxo; /**< Disable the LFXO upon EM4 entry */ |
Kojto | 113:f141b2784e32 | 424 | bool retainLfrco; /**< Disable the LFRCO upon EM4 entry */ |
Kojto | 113:f141b2784e32 | 425 | bool retainUlfrco; /**< Disable the ULFRCO upon EM4 entry */ |
Kojto | 113:f141b2784e32 | 426 | EMU_EM4State_TypeDef em4State; /**< Hibernate or shutoff EM4 state */ |
Kojto | 113:f141b2784e32 | 427 | EMU_EM4PinRetention_TypeDef pinRetentionMode; /**< EM4 pin retention mode */ |
Kojto | 98:8ab26030e058 | 428 | #endif |
<> | 139:856d2700e60b | 429 | #if defined( _EMU_CTRL_EM4HVSCALE_MASK ) |
<> | 139:856d2700e60b | 430 | EMU_VScaleEM4H_TypeDef vScaleEM4HVoltage;/**< EM4H voltage scaling level */ |
<> | 139:856d2700e60b | 431 | #endif |
Kojto | 98:8ab26030e058 | 432 | } EMU_EM4Init_TypeDef; |
Kojto | 113:f141b2784e32 | 433 | #endif |
Kojto | 98:8ab26030e058 | 434 | |
Kojto | 98:8ab26030e058 | 435 | #if defined( _EMU_EM4CONF_MASK ) |
<> | 139:856d2700e60b | 436 | /** Default initialization of EM4 configuration (Series 0) */ |
Kojto | 113:f141b2784e32 | 437 | #define EMU_EM4INIT_DEFAULT \ |
Kojto | 113:f141b2784e32 | 438 | { \ |
Kojto | 113:f141b2784e32 | 439 | false, /* Dont't lock configuration after it's been set */ \ |
<> | 139:856d2700e60b | 440 | false, /* No reset will be asserted due to BOD in EM4 */ \ |
Kojto | 113:f141b2784e32 | 441 | emuEM4Osc_ULFRCO, /* Use default ULFRCO oscillator */ \ |
Kojto | 113:f141b2784e32 | 442 | true, /* Wake up on EM4 BURTC interrupt */ \ |
Kojto | 113:f141b2784e32 | 443 | true, /* Enable VREG */ \ |
Kojto | 113:f141b2784e32 | 444 | } |
<> | 139:856d2700e60b | 445 | |
<> | 139:856d2700e60b | 446 | #elif defined( _EMU_CTRL_EM4HVSCALE_MASK ) |
<> | 139:856d2700e60b | 447 | /** Default initialization of EM4 configuration (Series 1 with VSCALE) */ |
<> | 139:856d2700e60b | 448 | #define EMU_EM4INIT_DEFAULT \ |
<> | 139:856d2700e60b | 449 | { \ |
<> | 139:856d2700e60b | 450 | false, /* Retain LFXO configuration upon EM4 entry */ \ |
<> | 139:856d2700e60b | 451 | false, /* Retain LFRCO configuration upon EM4 entry */ \ |
<> | 139:856d2700e60b | 452 | false, /* Retain ULFRCO configuration upon EM4 entry */ \ |
<> | 139:856d2700e60b | 453 | emuEM4Shutoff, /* Use EM4 shutoff state */ \ |
<> | 139:856d2700e60b | 454 | emuPinRetentionDisable, /* Do not retain pins in EM4 */ \ |
<> | 139:856d2700e60b | 455 | emuVScaleEM4H_FastWakeup, /* Do not scale down in EM4H */ \ |
<> | 139:856d2700e60b | 456 | } |
<> | 139:856d2700e60b | 457 | |
<> | 139:856d2700e60b | 458 | #elif defined( _EMU_EM4CTRL_MASK ) |
<> | 139:856d2700e60b | 459 | /** Default initialization of EM4 configuration (Series 1 without VSCALE) */ |
Kojto | 113:f141b2784e32 | 460 | #define EMU_EM4INIT_DEFAULT \ |
Kojto | 113:f141b2784e32 | 461 | { \ |
Kojto | 113:f141b2784e32 | 462 | false, /* Retain LFXO configuration upon EM4 entry */ \ |
Kojto | 113:f141b2784e32 | 463 | false, /* Retain LFRCO configuration upon EM4 entry */ \ |
Kojto | 113:f141b2784e32 | 464 | false, /* Retain ULFRCO configuration upon EM4 entry */ \ |
Kojto | 113:f141b2784e32 | 465 | emuEM4Shutoff, /* Use EM4 shutoff state */ \ |
Kojto | 113:f141b2784e32 | 466 | emuPinRetentionDisable, /* Do not retain pins in EM4 */ \ |
Kojto | 113:f141b2784e32 | 467 | } |
Kojto | 113:f141b2784e32 | 468 | #endif |
Kojto | 98:8ab26030e058 | 469 | |
Kojto | 98:8ab26030e058 | 470 | #if defined( BU_PRESENT ) |
Kojto | 98:8ab26030e058 | 471 | /** Backup Power Domain Initialization structure */ |
Kojto | 98:8ab26030e058 | 472 | typedef struct |
Kojto | 98:8ab26030e058 | 473 | { |
Kojto | 98:8ab26030e058 | 474 | /* Backup Power Domain power configuration */ |
Kojto | 98:8ab26030e058 | 475 | |
Kojto | 98:8ab26030e058 | 476 | /** Voltage probe select, selects ADC voltage */ |
Kojto | 98:8ab26030e058 | 477 | EMU_Probe_TypeDef probe; |
Kojto | 98:8ab26030e058 | 478 | /** Enable BOD calibration mode */ |
Kojto | 98:8ab26030e058 | 479 | bool bodCal; |
Kojto | 98:8ab26030e058 | 480 | /** Enable BU_STAT status pin for active BU mode */ |
Kojto | 98:8ab26030e058 | 481 | bool statusPinEnable; |
Kojto | 98:8ab26030e058 | 482 | |
Kojto | 98:8ab26030e058 | 483 | /* Backup Power Domain connection configuration */ |
Kojto | 98:8ab26030e058 | 484 | /** Power domain resistor */ |
Kojto | 98:8ab26030e058 | 485 | EMU_Resistor_TypeDef resistor; |
Kojto | 98:8ab26030e058 | 486 | /** BU_VOUT strong enable */ |
Kojto | 98:8ab26030e058 | 487 | bool voutStrong; |
Kojto | 98:8ab26030e058 | 488 | /** BU_VOUT medium enable */ |
Kojto | 98:8ab26030e058 | 489 | bool voutMed; |
Kojto | 98:8ab26030e058 | 490 | /** BU_VOUT weak enable */ |
Kojto | 98:8ab26030e058 | 491 | bool voutWeak; |
Kojto | 98:8ab26030e058 | 492 | /** Power connection, when not in Backup Mode */ |
Kojto | 98:8ab26030e058 | 493 | EMU_Power_TypeDef inactivePower; |
Kojto | 98:8ab26030e058 | 494 | /** Power connection, when in Backup Mode */ |
Kojto | 98:8ab26030e058 | 495 | EMU_Power_TypeDef activePower; |
Kojto | 98:8ab26030e058 | 496 | /** Enable backup power domain, and release reset, enable BU_VIN pin */ |
Kojto | 98:8ab26030e058 | 497 | bool enable; |
Kojto | 98:8ab26030e058 | 498 | } EMU_BUPDInit_TypeDef; |
Kojto | 98:8ab26030e058 | 499 | |
Kojto | 113:f141b2784e32 | 500 | /** Default Backup Power Domain configuration */ |
Kojto | 113:f141b2784e32 | 501 | #define EMU_BUPDINIT_DEFAULT \ |
Kojto | 113:f141b2784e32 | 502 | { \ |
Kojto | 113:f141b2784e32 | 503 | emuProbe_Disable, /* Do not enable voltage probe */ \ |
Kojto | 113:f141b2784e32 | 504 | false, /* Disable BOD calibration mode */ \ |
Kojto | 113:f141b2784e32 | 505 | false, /* Disable BU_STAT pin for backup mode indication */ \ |
Kojto | 113:f141b2784e32 | 506 | \ |
Kojto | 113:f141b2784e32 | 507 | emuRes_Res0, /* RES0 series resistance between main and backup power */ \ |
Kojto | 113:f141b2784e32 | 508 | false, /* Don't enable strong switch */ \ |
Kojto | 113:f141b2784e32 | 509 | false, /* Don't enable medium switch */ \ |
Kojto | 113:f141b2784e32 | 510 | false, /* Don't enable weak switch */ \ |
Kojto | 113:f141b2784e32 | 511 | \ |
Kojto | 113:f141b2784e32 | 512 | emuPower_None, /* No connection between main and backup power (inactive mode) */ \ |
Kojto | 113:f141b2784e32 | 513 | emuPower_None, /* No connection between main and backup power (active mode) */ \ |
Kojto | 113:f141b2784e32 | 514 | true /* Enable BUPD enter on BOD, enable BU_VIN pin, release BU reset */ \ |
Kojto | 113:f141b2784e32 | 515 | } |
Kojto | 98:8ab26030e058 | 516 | #endif |
Kojto | 98:8ab26030e058 | 517 | |
Kojto | 113:f141b2784e32 | 518 | #if defined( _EMU_DCDCCTRL_MASK ) |
Kojto | 113:f141b2784e32 | 519 | /** DCDC initialization structure */ |
Kojto | 113:f141b2784e32 | 520 | typedef struct |
Kojto | 113:f141b2784e32 | 521 | { |
<> | 139:856d2700e60b | 522 | EMU_PowerConfig_TypeDef powerConfig; /**< Device external power configuration. |
<> | 139:856d2700e60b | 523 | @ref emuPowerConfig_DcdcToDvdd is currently the only supported mode. */ |
<> | 128:9bcdf88f62b0 | 524 | EMU_DcdcMode_TypeDef dcdcMode; /**< DCDC regulator operating mode in EM0/1 */ |
Kojto | 113:f141b2784e32 | 525 | uint16_t mVout; /**< Target output voltage (mV) */ |
<> | 128:9bcdf88f62b0 | 526 | uint16_t em01LoadCurrent_mA; /**< Estimated average load current in EM0/1 (mA). |
Kojto | 113:f141b2784e32 | 527 | This estimate is also used for EM1 optimization, |
Kojto | 113:f141b2784e32 | 528 | so if EM1 current is expected to be higher than EM0, |
Kojto | 113:f141b2784e32 | 529 | then this parameter should hold the higher EM1 current. */ |
Kojto | 113:f141b2784e32 | 530 | uint16_t em234LoadCurrent_uA; /**< Estimated average load current in EM2 (uA). |
Kojto | 113:f141b2784e32 | 531 | This estimate is also used for EM3 and 4 optimization, |
Kojto | 113:f141b2784e32 | 532 | so if EM3 or 4 current is expected to be higher than EM2, |
Kojto | 113:f141b2784e32 | 533 | then this parameter should hold the higher EM3 or 4 current. */ |
<> | 128:9bcdf88f62b0 | 534 | uint16_t maxCurrent_mA; /**< Maximum average DCDC output current (mA). |
Kojto | 113:f141b2784e32 | 535 | This can be set to the maximum for the power source, |
Kojto | 113:f141b2784e32 | 536 | for example the maximum for a battery. */ |
<> | 128:9bcdf88f62b0 | 537 | EMU_DcdcAnaPeripheralPower_TypeDef |
<> | 128:9bcdf88f62b0 | 538 | anaPeripheralPower; /**< Select analog peripheral power in DCDC-to-DVDD mode */ |
<> | 128:9bcdf88f62b0 | 539 | EMU_DcdcLnReverseCurrentControl_TypeDef |
<> | 128:9bcdf88f62b0 | 540 | reverseCurrentControl; /**< Low-noise reverse current control. |
<> | 128:9bcdf88f62b0 | 541 | NOTE: this parameter uses special encoding: |
<> | 128:9bcdf88f62b0 | 542 | >= 0 is forced CCM mode where the parameter is used as the |
<> | 128:9bcdf88f62b0 | 543 | reverse current threshold in mA. |
<> | 128:9bcdf88f62b0 | 544 | -1 is encoded as emuDcdcLnHighEfficiencyMode (EFM32 only) */ |
<> | 128:9bcdf88f62b0 | 545 | EMU_DcdcLnCompCtrl_TypeDef dcdcLnCompCtrl; /**< DCDC Low-noise mode compensator control. */ |
Kojto | 113:f141b2784e32 | 546 | } EMU_DCDCInit_TypeDef; |
Kojto | 113:f141b2784e32 | 547 | |
Kojto | 113:f141b2784e32 | 548 | /** Default DCDC initialization */ |
Kojto | 113:f141b2784e32 | 549 | #if defined( _EFM_DEVICE ) |
<> | 139:856d2700e60b | 550 | #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) |
<> | 128:9bcdf88f62b0 | 551 | #define EMU_DCDCINIT_DEFAULT \ |
<> | 128:9bcdf88f62b0 | 552 | { \ |
<> | 128:9bcdf88f62b0 | 553 | emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ |
<> | 139:856d2700e60b | 554 | emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ |
<> | 139:856d2700e60b | 555 | 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ |
<> | 139:856d2700e60b | 556 | 5, /* Nominal EM0/1 load current of less than 5mA */ \ |
<> | 139:856d2700e60b | 557 | 10, /* Nominal EM2/3/4 load current less than 10uA */ \ |
<> | 139:856d2700e60b | 558 | 200, /* Maximum average current of 200mA |
<> | 139:856d2700e60b | 559 | (assume strong battery or other power source) */ \ |
<> | 139:856d2700e60b | 560 | emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ |
<> | 139:856d2700e60b | 561 | emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ |
<> | 139:856d2700e60b | 562 | emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ |
<> | 139:856d2700e60b | 563 | } |
<> | 139:856d2700e60b | 564 | #else |
<> | 139:856d2700e60b | 565 | #define EMU_DCDCINIT_DEFAULT \ |
<> | 139:856d2700e60b | 566 | { \ |
<> | 139:856d2700e60b | 567 | emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ |
<> | 139:856d2700e60b | 568 | emuDcdcMode_LowPower, /* Low-power mode in EM0 */ \ |
<> | 128:9bcdf88f62b0 | 569 | 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ |
<> | 128:9bcdf88f62b0 | 570 | 5, /* Nominal EM0/1 load current of less than 5mA */ \ |
<> | 128:9bcdf88f62b0 | 571 | 10, /* Nominal EM2/3/4 load current less than 10uA */ \ |
<> | 128:9bcdf88f62b0 | 572 | 200, /* Maximum average current of 200mA |
<> | 128:9bcdf88f62b0 | 573 | (assume strong battery or other power source) */ \ |
<> | 128:9bcdf88f62b0 | 574 | emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ |
<> | 128:9bcdf88f62b0 | 575 | emuDcdcLnHighEfficiency, /* Use high-efficiency mode */ \ |
<> | 128:9bcdf88f62b0 | 576 | emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ |
<> | 128:9bcdf88f62b0 | 577 | } |
<> | 139:856d2700e60b | 578 | #endif |
<> | 128:9bcdf88f62b0 | 579 | |
<> | 139:856d2700e60b | 580 | #else /* EFR32 device */ |
<> | 139:856d2700e60b | 581 | #if defined(_SILICON_LABS_GECKO_INTERNAL_SDID_80) |
Kojto | 113:f141b2784e32 | 582 | #define EMU_DCDCINIT_DEFAULT \ |
Kojto | 113:f141b2784e32 | 583 | { \ |
Kojto | 113:f141b2784e32 | 584 | emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ |
<> | 139:856d2700e60b | 585 | emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ |
Kojto | 113:f141b2784e32 | 586 | 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ |
<> | 139:856d2700e60b | 587 | 15, /* Nominal EM0/1 load current of less than 15mA */ \ |
<> | 128:9bcdf88f62b0 | 588 | 10, /* Nominal EM2/3/4 load current less than 10uA */ \ |
<> | 128:9bcdf88f62b0 | 589 | 200, /* Maximum average current of 200mA |
<> | 128:9bcdf88f62b0 | 590 | (assume strong battery or other power source) */ \ |
Kojto | 113:f141b2784e32 | 591 | emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ |
<> | 139:856d2700e60b | 592 | 160, /* Maximum reverse current of 160mA */ \ |
<> | 128:9bcdf88f62b0 | 593 | emuDcdcLnCompCtrl_1u0F, /* 1uF DCDC capacitor */ \ |
Kojto | 113:f141b2784e32 | 594 | } |
<> | 139:856d2700e60b | 595 | #else |
Kojto | 113:f141b2784e32 | 596 | #define EMU_DCDCINIT_DEFAULT \ |
Kojto | 113:f141b2784e32 | 597 | { \ |
Kojto | 113:f141b2784e32 | 598 | emuPowerConfig_DcdcToDvdd, /* DCDC to DVDD */ \ |
Kojto | 113:f141b2784e32 | 599 | emuDcdcMode_LowNoise, /* Low-niose mode in EM0 */ \ |
Kojto | 113:f141b2784e32 | 600 | 1800, /* Nominal output voltage for DVDD mode, 1.8V */ \ |
<> | 128:9bcdf88f62b0 | 601 | 15, /* Nominal EM0/1 load current of less than 15mA */ \ |
<> | 128:9bcdf88f62b0 | 602 | 10, /* Nominal EM2/3/4 load current less than 10uA */ \ |
<> | 128:9bcdf88f62b0 | 603 | 200, /* Maximum average current of 200mA |
<> | 128:9bcdf88f62b0 | 604 | (assume strong battery or other power source) */ \ |
<> | 128:9bcdf88f62b0 | 605 | emuDcdcAnaPeripheralPower_DCDC,/* Select DCDC as analog power supply (lower power) */ \ |
<> | 128:9bcdf88f62b0 | 606 | 160, /* Maximum reverse current of 160mA */ \ |
<> | 128:9bcdf88f62b0 | 607 | emuDcdcLnCompCtrl_4u7F, /* 4.7uF DCDC capacitor */ \ |
<> | 128:9bcdf88f62b0 | 608 | } |
Kojto | 113:f141b2784e32 | 609 | #endif |
<> | 128:9bcdf88f62b0 | 610 | #endif |
Kojto | 113:f141b2784e32 | 611 | #endif |
Kojto | 113:f141b2784e32 | 612 | |
Kojto | 113:f141b2784e32 | 613 | #if defined( EMU_STATUS_VMONRDY ) |
Kojto | 113:f141b2784e32 | 614 | /** VMON initialization structure */ |
Kojto | 113:f141b2784e32 | 615 | typedef struct |
Kojto | 113:f141b2784e32 | 616 | { |
<> | 128:9bcdf88f62b0 | 617 | EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */ |
<> | 128:9bcdf88f62b0 | 618 | int threshold; /**< Trigger threshold (mV) */ |
<> | 128:9bcdf88f62b0 | 619 | bool riseWakeup; /**< Wake up from EM4H on rising edge */ |
<> | 128:9bcdf88f62b0 | 620 | bool fallWakeup; /**< Wake up from EM4H on falling edge */ |
<> | 128:9bcdf88f62b0 | 621 | bool enable; /**< Enable VMON channel */ |
<> | 128:9bcdf88f62b0 | 622 | bool retDisable; /**< Disable IO0 retention when voltage drops below threshold (IOVDD only) */ |
Kojto | 113:f141b2784e32 | 623 | } EMU_VmonInit_TypeDef; |
Kojto | 113:f141b2784e32 | 624 | |
Kojto | 113:f141b2784e32 | 625 | /** Default VMON initialization structure */ |
<> | 128:9bcdf88f62b0 | 626 | #define EMU_VMONINIT_DEFAULT \ |
<> | 128:9bcdf88f62b0 | 627 | { \ |
<> | 128:9bcdf88f62b0 | 628 | emuVmonChannel_AVDD, /* AVDD VMON channel */ \ |
<> | 128:9bcdf88f62b0 | 629 | 3200, /* 3.2 V threshold */ \ |
<> | 128:9bcdf88f62b0 | 630 | false, /* Don't wake from EM4H on rising edge */ \ |
<> | 128:9bcdf88f62b0 | 631 | false, /* Don't wake from EM4H on falling edge */ \ |
<> | 128:9bcdf88f62b0 | 632 | true, /* Enable VMON channel */ \ |
<> | 128:9bcdf88f62b0 | 633 | false /* Don't disable IO0 retention */ \ |
Kojto | 113:f141b2784e32 | 634 | } |
Kojto | 113:f141b2784e32 | 635 | |
Kojto | 113:f141b2784e32 | 636 | /** VMON Hysteresis initialization structure */ |
Kojto | 113:f141b2784e32 | 637 | typedef struct |
Kojto | 113:f141b2784e32 | 638 | { |
<> | 128:9bcdf88f62b0 | 639 | EMU_VmonChannel_TypeDef channel; /**< VMON channel to configure */ |
<> | 128:9bcdf88f62b0 | 640 | int riseThreshold; /**< Rising threshold (mV) */ |
<> | 128:9bcdf88f62b0 | 641 | int fallThreshold; /**< Falling threshold (mV) */ |
<> | 128:9bcdf88f62b0 | 642 | bool riseWakeup; /**< Wake up from EM4H on rising edge */ |
<> | 128:9bcdf88f62b0 | 643 | bool fallWakeup; /**< Wake up from EM4H on falling edge */ |
<> | 128:9bcdf88f62b0 | 644 | bool enable; /**< Enable VMON channel */ |
Kojto | 113:f141b2784e32 | 645 | } EMU_VmonHystInit_TypeDef; |
Kojto | 113:f141b2784e32 | 646 | |
Kojto | 113:f141b2784e32 | 647 | /** Default VMON Hysteresis initialization structure */ |
<> | 128:9bcdf88f62b0 | 648 | #define EMU_VMONHYSTINIT_DEFAULT \ |
<> | 128:9bcdf88f62b0 | 649 | { \ |
<> | 128:9bcdf88f62b0 | 650 | emuVmonChannel_AVDD, /* AVDD VMON channel */ \ |
<> | 128:9bcdf88f62b0 | 651 | 3200, /* 3.2 V rise threshold */ \ |
<> | 128:9bcdf88f62b0 | 652 | 3200, /* 3.2 V fall threshold */ \ |
<> | 128:9bcdf88f62b0 | 653 | false, /* Don't wake from EM4H on rising edge */ \ |
<> | 128:9bcdf88f62b0 | 654 | false, /* Don't wake from EM4H on falling edge */ \ |
<> | 128:9bcdf88f62b0 | 655 | true /* Enable VMON channel */ \ |
Kojto | 113:f141b2784e32 | 656 | } |
Kojto | 113:f141b2784e32 | 657 | #endif /* EMU_STATUS_VMONRDY */ |
Kojto | 98:8ab26030e058 | 658 | |
Kojto | 98:8ab26030e058 | 659 | /******************************************************************************* |
Kojto | 98:8ab26030e058 | 660 | ***************************** PROTOTYPES ********************************** |
Kojto | 98:8ab26030e058 | 661 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 662 | |
<> | 139:856d2700e60b | 663 | #if defined( _EMU_CMD_EM01VSCALE0_MASK ) |
<> | 139:856d2700e60b | 664 | void EMU_EM01Init(const EMU_EM01Init_TypeDef *em01Init); |
<> | 139:856d2700e60b | 665 | #endif |
<> | 139:856d2700e60b | 666 | void EMU_EM23Init(const EMU_EM23Init_TypeDef *em23Init); |
<> | 139:856d2700e60b | 667 | #if defined( _EMU_EM4CONF_MASK ) || defined( _EMU_EM4CTRL_MASK ) |
<> | 139:856d2700e60b | 668 | void EMU_EM4Init(const EMU_EM4Init_TypeDef *em4Init); |
<> | 139:856d2700e60b | 669 | #endif |
<> | 139:856d2700e60b | 670 | void EMU_EnterEM2(bool restore); |
<> | 139:856d2700e60b | 671 | void EMU_EnterEM3(bool restore); |
<> | 139:856d2700e60b | 672 | void EMU_Restore(void); |
<> | 139:856d2700e60b | 673 | void EMU_EnterEM4(void); |
<> | 139:856d2700e60b | 674 | #if defined( _EMU_EM4CTRL_MASK ) |
<> | 139:856d2700e60b | 675 | void EMU_EnterEM4H(void); |
<> | 139:856d2700e60b | 676 | void EMU_EnterEM4S(void); |
<> | 139:856d2700e60b | 677 | #endif |
<> | 139:856d2700e60b | 678 | void EMU_MemPwrDown(uint32_t blocks); |
<> | 139:856d2700e60b | 679 | void EMU_RamPowerDown(uint32_t start, uint32_t end); |
<> | 139:856d2700e60b | 680 | #if defined(_EMU_EM23PERNORETAINCTRL_MASK) |
<> | 139:856d2700e60b | 681 | void EMU_PeripheralRetention(EMU_PeripheralRetention_TypeDef periMask, bool enable); |
<> | 139:856d2700e60b | 682 | #endif |
<> | 139:856d2700e60b | 683 | void EMU_UpdateOscConfig(void); |
<> | 139:856d2700e60b | 684 | #if defined( _EMU_CMD_EM01VSCALE0_MASK ) |
<> | 139:856d2700e60b | 685 | void EMU_VScaleEM01ByClock(uint32_t clockFrequency, bool wait); |
<> | 139:856d2700e60b | 686 | void EMU_VScaleEM01(EMU_VScaleEM01_TypeDef voltage, bool wait); |
<> | 139:856d2700e60b | 687 | #endif |
<> | 139:856d2700e60b | 688 | #if defined( BU_PRESENT ) |
<> | 139:856d2700e60b | 689 | void EMU_BUPDInit(const EMU_BUPDInit_TypeDef *bupdInit); |
<> | 139:856d2700e60b | 690 | void EMU_BUThresholdSet(EMU_BODMode_TypeDef mode, uint32_t value); |
<> | 139:856d2700e60b | 691 | void EMU_BUThresRangeSet(EMU_BODMode_TypeDef mode, uint32_t value); |
<> | 139:856d2700e60b | 692 | #endif |
<> | 139:856d2700e60b | 693 | #if defined( _EMU_DCDCCTRL_MASK ) |
<> | 139:856d2700e60b | 694 | bool EMU_DCDCInit(const EMU_DCDCInit_TypeDef *dcdcInit); |
<> | 139:856d2700e60b | 695 | void EMU_DCDCModeSet(EMU_DcdcMode_TypeDef dcdcMode); |
<> | 139:856d2700e60b | 696 | void EMU_DCDCConductionModeSet(EMU_DcdcConductionMode_TypeDef conductionMode, bool rcoDefaultSet); |
<> | 139:856d2700e60b | 697 | bool EMU_DCDCOutputVoltageSet(uint32_t mV, bool setLpVoltage, bool setLnVoltage); |
<> | 139:856d2700e60b | 698 | void EMU_DCDCOptimizeSlice(uint32_t mALoadCurrent); |
<> | 139:856d2700e60b | 699 | void EMU_DCDCLnRcoBandSet(EMU_DcdcLnRcoBand_TypeDef band); |
<> | 139:856d2700e60b | 700 | bool EMU_DCDCPowerOff(void); |
<> | 139:856d2700e60b | 701 | #endif |
<> | 139:856d2700e60b | 702 | #if defined( EMU_STATUS_VMONRDY ) |
<> | 139:856d2700e60b | 703 | void EMU_VmonInit(const EMU_VmonInit_TypeDef *vmonInit); |
<> | 139:856d2700e60b | 704 | void EMU_VmonHystInit(const EMU_VmonHystInit_TypeDef *vmonInit); |
<> | 139:856d2700e60b | 705 | void EMU_VmonEnable(EMU_VmonChannel_TypeDef channel, bool enable); |
<> | 139:856d2700e60b | 706 | bool EMU_VmonChannelStatusGet(EMU_VmonChannel_TypeDef channel); |
<> | 139:856d2700e60b | 707 | #endif |
<> | 139:856d2700e60b | 708 | |
Kojto | 98:8ab26030e058 | 709 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 710 | * @brief |
Kojto | 98:8ab26030e058 | 711 | * Enter energy mode 1 (EM1). |
Kojto | 98:8ab26030e058 | 712 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 713 | __STATIC_INLINE void EMU_EnterEM1(void) |
Kojto | 98:8ab26030e058 | 714 | { |
Kojto | 113:f141b2784e32 | 715 | /* Enter sleep mode */ |
Kojto | 98:8ab26030e058 | 716 | SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; |
Kojto | 98:8ab26030e058 | 717 | __WFI(); |
Kojto | 98:8ab26030e058 | 718 | } |
Kojto | 98:8ab26030e058 | 719 | |
<> | 139:856d2700e60b | 720 | |
<> | 139:856d2700e60b | 721 | #if defined( _EMU_STATUS_VSCALE_MASK ) |
<> | 139:856d2700e60b | 722 | /***************************************************************************//** |
<> | 139:856d2700e60b | 723 | * @brief |
<> | 139:856d2700e60b | 724 | * Wait for voltage scaling to complete |
<> | 139:856d2700e60b | 725 | ******************************************************************************/ |
<> | 139:856d2700e60b | 726 | __STATIC_INLINE void EMU_VScaleWait(void) |
<> | 139:856d2700e60b | 727 | { |
<> | 139:856d2700e60b | 728 | while (BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VSCALEBUSY_SHIFT)); |
<> | 139:856d2700e60b | 729 | } |
<> | 128:9bcdf88f62b0 | 730 | #endif |
<> | 139:856d2700e60b | 731 | |
<> | 139:856d2700e60b | 732 | #if defined( _EMU_STATUS_VSCALE_MASK ) |
<> | 139:856d2700e60b | 733 | /***************************************************************************//** |
<> | 139:856d2700e60b | 734 | * @brief |
<> | 139:856d2700e60b | 735 | * Get current voltage scaling level |
<> | 139:856d2700e60b | 736 | * |
<> | 139:856d2700e60b | 737 | * @return |
<> | 139:856d2700e60b | 738 | * Current voltage scaling level |
<> | 139:856d2700e60b | 739 | ******************************************************************************/ |
<> | 139:856d2700e60b | 740 | __STATIC_INLINE EMU_VScaleEM01_TypeDef EMU_VScaleGet(void) |
<> | 139:856d2700e60b | 741 | { |
<> | 139:856d2700e60b | 742 | EMU_VScaleWait(); |
<> | 139:856d2700e60b | 743 | return (EMU_VScaleEM01_TypeDef)((EMU->STATUS & _EMU_STATUS_VSCALE_MASK) |
<> | 139:856d2700e60b | 744 | >> _EMU_STATUS_VSCALE_SHIFT); |
<> | 139:856d2700e60b | 745 | } |
Kojto | 98:8ab26030e058 | 746 | #endif |
Kojto | 98:8ab26030e058 | 747 | |
<> | 139:856d2700e60b | 748 | #if defined( _EMU_STATUS_VMONRDY_MASK ) |
Kojto | 113:f141b2784e32 | 749 | /***************************************************************************//** |
Kojto | 113:f141b2784e32 | 750 | * @brief |
Kojto | 113:f141b2784e32 | 751 | * Get the status of the voltage monitor (VMON). |
Kojto | 113:f141b2784e32 | 752 | * |
Kojto | 113:f141b2784e32 | 753 | * @return |
Kojto | 113:f141b2784e32 | 754 | * Status of the VMON. True if all the enabled channels are ready, false if |
Kojto | 113:f141b2784e32 | 755 | * one or more of the enabled channels are not ready. |
Kojto | 113:f141b2784e32 | 756 | ******************************************************************************/ |
Kojto | 113:f141b2784e32 | 757 | __STATIC_INLINE bool EMU_VmonStatusGet(void) |
Kojto | 113:f141b2784e32 | 758 | { |
Kojto | 113:f141b2784e32 | 759 | return BUS_RegBitRead(&EMU->STATUS, _EMU_STATUS_VMONRDY_SHIFT); |
Kojto | 113:f141b2784e32 | 760 | } |
<> | 139:856d2700e60b | 761 | #endif /* _EMU_STATUS_VMONRDY_MASK */ |
Kojto | 98:8ab26030e058 | 762 | |
Kojto | 98:8ab26030e058 | 763 | #if defined( _EMU_IF_MASK ) |
Kojto | 98:8ab26030e058 | 764 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 765 | * @brief |
Kojto | 98:8ab26030e058 | 766 | * Clear one or more pending EMU interrupts. |
Kojto | 98:8ab26030e058 | 767 | * |
Kojto | 98:8ab26030e058 | 768 | * @param[in] flags |
Kojto | 98:8ab26030e058 | 769 | * Pending EMU interrupt sources to clear. Use one or more valid |
Kojto | 98:8ab26030e058 | 770 | * interrupt flags for the EMU module (EMU_IFC_nnn). |
Kojto | 98:8ab26030e058 | 771 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 772 | __STATIC_INLINE void EMU_IntClear(uint32_t flags) |
Kojto | 98:8ab26030e058 | 773 | { |
Kojto | 98:8ab26030e058 | 774 | EMU->IFC = flags; |
Kojto | 98:8ab26030e058 | 775 | } |
Kojto | 98:8ab26030e058 | 776 | |
Kojto | 98:8ab26030e058 | 777 | |
Kojto | 98:8ab26030e058 | 778 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 779 | * @brief |
Kojto | 98:8ab26030e058 | 780 | * Disable one or more EMU interrupts. |
Kojto | 98:8ab26030e058 | 781 | * |
Kojto | 98:8ab26030e058 | 782 | * @param[in] flags |
Kojto | 98:8ab26030e058 | 783 | * EMU interrupt sources to disable. Use one or more valid |
Kojto | 98:8ab26030e058 | 784 | * interrupt flags for the EMU module (EMU_IEN_nnn). |
Kojto | 98:8ab26030e058 | 785 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 786 | __STATIC_INLINE void EMU_IntDisable(uint32_t flags) |
Kojto | 98:8ab26030e058 | 787 | { |
Kojto | 113:f141b2784e32 | 788 | EMU->IEN &= ~flags; |
Kojto | 98:8ab26030e058 | 789 | } |
Kojto | 98:8ab26030e058 | 790 | |
Kojto | 98:8ab26030e058 | 791 | |
Kojto | 98:8ab26030e058 | 792 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 793 | * @brief |
Kojto | 98:8ab26030e058 | 794 | * Enable one or more EMU interrupts. |
Kojto | 98:8ab26030e058 | 795 | * |
Kojto | 98:8ab26030e058 | 796 | * @note |
Kojto | 98:8ab26030e058 | 797 | * Depending on the use, a pending interrupt may already be set prior to |
Kojto | 98:8ab26030e058 | 798 | * enabling the interrupt. Consider using EMU_IntClear() prior to enabling |
Kojto | 98:8ab26030e058 | 799 | * if such a pending interrupt should be ignored. |
Kojto | 98:8ab26030e058 | 800 | * |
Kojto | 98:8ab26030e058 | 801 | * @param[in] flags |
Kojto | 98:8ab26030e058 | 802 | * EMU interrupt sources to enable. Use one or more valid |
Kojto | 98:8ab26030e058 | 803 | * interrupt flags for the EMU module (EMU_IEN_nnn). |
Kojto | 98:8ab26030e058 | 804 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 805 | __STATIC_INLINE void EMU_IntEnable(uint32_t flags) |
Kojto | 98:8ab26030e058 | 806 | { |
Kojto | 98:8ab26030e058 | 807 | EMU->IEN |= flags; |
Kojto | 98:8ab26030e058 | 808 | } |
Kojto | 98:8ab26030e058 | 809 | |
Kojto | 98:8ab26030e058 | 810 | |
Kojto | 98:8ab26030e058 | 811 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 812 | * @brief |
Kojto | 98:8ab26030e058 | 813 | * Get pending EMU interrupt flags. |
Kojto | 98:8ab26030e058 | 814 | * |
Kojto | 98:8ab26030e058 | 815 | * @note |
Kojto | 98:8ab26030e058 | 816 | * The event bits are not cleared by the use of this function. |
Kojto | 98:8ab26030e058 | 817 | * |
Kojto | 98:8ab26030e058 | 818 | * @return |
Kojto | 98:8ab26030e058 | 819 | * EMU interrupt sources pending. Returns one or more valid |
Kojto | 98:8ab26030e058 | 820 | * interrupt flags for the EMU module (EMU_IF_nnn). |
Kojto | 98:8ab26030e058 | 821 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 822 | __STATIC_INLINE uint32_t EMU_IntGet(void) |
Kojto | 98:8ab26030e058 | 823 | { |
Kojto | 98:8ab26030e058 | 824 | return EMU->IF; |
Kojto | 98:8ab26030e058 | 825 | } |
Kojto | 98:8ab26030e058 | 826 | |
Kojto | 98:8ab26030e058 | 827 | |
Kojto | 98:8ab26030e058 | 828 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 829 | * @brief |
Kojto | 98:8ab26030e058 | 830 | * Get enabled and pending EMU interrupt flags. |
Kojto | 98:8ab26030e058 | 831 | * Useful for handling more interrupt sources in the same interrupt handler. |
Kojto | 98:8ab26030e058 | 832 | * |
Kojto | 98:8ab26030e058 | 833 | * @note |
Kojto | 98:8ab26030e058 | 834 | * Interrupt flags are not cleared by the use of this function. |
Kojto | 98:8ab26030e058 | 835 | * |
Kojto | 98:8ab26030e058 | 836 | * @return |
Kojto | 98:8ab26030e058 | 837 | * Pending and enabled EMU interrupt sources |
Kojto | 98:8ab26030e058 | 838 | * The return value is the bitwise AND of |
Kojto | 98:8ab26030e058 | 839 | * - the enabled interrupt sources in EMU_IEN and |
Kojto | 98:8ab26030e058 | 840 | * - the pending interrupt flags EMU_IF |
Kojto | 98:8ab26030e058 | 841 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 842 | __STATIC_INLINE uint32_t EMU_IntGetEnabled(void) |
Kojto | 98:8ab26030e058 | 843 | { |
Kojto | 98:8ab26030e058 | 844 | uint32_t ien; |
Kojto | 98:8ab26030e058 | 845 | |
Kojto | 98:8ab26030e058 | 846 | ien = EMU->IEN; |
Kojto | 98:8ab26030e058 | 847 | return EMU->IF & ien; |
Kojto | 98:8ab26030e058 | 848 | } |
Kojto | 98:8ab26030e058 | 849 | |
Kojto | 98:8ab26030e058 | 850 | |
Kojto | 98:8ab26030e058 | 851 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 852 | * @brief |
Kojto | 98:8ab26030e058 | 853 | * Set one or more pending EMU interrupts |
Kojto | 98:8ab26030e058 | 854 | * |
Kojto | 98:8ab26030e058 | 855 | * @param[in] flags |
Kojto | 98:8ab26030e058 | 856 | * EMU interrupt sources to set to pending. Use one or more valid |
Kojto | 98:8ab26030e058 | 857 | * interrupt flags for the EMU module (EMU_IFS_nnn). |
Kojto | 98:8ab26030e058 | 858 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 859 | __STATIC_INLINE void EMU_IntSet(uint32_t flags) |
Kojto | 98:8ab26030e058 | 860 | { |
Kojto | 98:8ab26030e058 | 861 | EMU->IFS = flags; |
Kojto | 98:8ab26030e058 | 862 | } |
Kojto | 98:8ab26030e058 | 863 | #endif /* _EMU_IF_MASK */ |
Kojto | 98:8ab26030e058 | 864 | |
Kojto | 98:8ab26030e058 | 865 | |
Kojto | 98:8ab26030e058 | 866 | #if defined( _EMU_EM4CONF_LOCKCONF_MASK ) |
Kojto | 98:8ab26030e058 | 867 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 868 | * @brief |
Kojto | 98:8ab26030e058 | 869 | * Enable or disable EM4 lock configuration |
Kojto | 98:8ab26030e058 | 870 | * @param[in] enable |
Kojto | 98:8ab26030e058 | 871 | * If true, locks down EM4 configuration |
Kojto | 98:8ab26030e058 | 872 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 873 | __STATIC_INLINE void EMU_EM4Lock(bool enable) |
Kojto | 98:8ab26030e058 | 874 | { |
Kojto | 113:f141b2784e32 | 875 | BUS_RegBitWrite(&(EMU->EM4CONF), _EMU_EM4CONF_LOCKCONF_SHIFT, enable); |
Kojto | 98:8ab26030e058 | 876 | } |
Kojto | 98:8ab26030e058 | 877 | #endif |
Kojto | 98:8ab26030e058 | 878 | |
Kojto | 98:8ab26030e058 | 879 | #if defined( _EMU_STATUS_BURDY_MASK ) |
Kojto | 98:8ab26030e058 | 880 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 881 | * @brief |
Kojto | 98:8ab26030e058 | 882 | * Halts until backup power functionality is ready |
Kojto | 98:8ab26030e058 | 883 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 884 | __STATIC_INLINE void EMU_BUReady(void) |
Kojto | 98:8ab26030e058 | 885 | { |
Kojto | 113:f141b2784e32 | 886 | while(!(EMU->STATUS & EMU_STATUS_BURDY)) |
Kojto | 113:f141b2784e32 | 887 | ; |
Kojto | 98:8ab26030e058 | 888 | } |
Kojto | 98:8ab26030e058 | 889 | #endif |
Kojto | 98:8ab26030e058 | 890 | |
Kojto | 98:8ab26030e058 | 891 | #if defined( _EMU_ROUTE_BUVINPEN_MASK ) |
Kojto | 98:8ab26030e058 | 892 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 893 | * @brief |
Kojto | 98:8ab26030e058 | 894 | * Disable BU_VIN support |
Kojto | 98:8ab26030e058 | 895 | * @param[in] enable |
Kojto | 98:8ab26030e058 | 896 | * If true, enables BU_VIN input pin support, if false disables it |
Kojto | 98:8ab26030e058 | 897 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 898 | __STATIC_INLINE void EMU_BUPinEnable(bool enable) |
Kojto | 98:8ab26030e058 | 899 | { |
Kojto | 113:f141b2784e32 | 900 | BUS_RegBitWrite(&(EMU->ROUTE), _EMU_ROUTE_BUVINPEN_SHIFT, enable); |
Kojto | 98:8ab26030e058 | 901 | } |
Kojto | 98:8ab26030e058 | 902 | #endif |
Kojto | 98:8ab26030e058 | 903 | |
Kojto | 98:8ab26030e058 | 904 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 905 | * @brief |
Kojto | 113:f141b2784e32 | 906 | * Lock the EMU in order to protect its registers against unintended |
Kojto | 98:8ab26030e058 | 907 | * modification. |
Kojto | 98:8ab26030e058 | 908 | * |
Kojto | 98:8ab26030e058 | 909 | * @note |
Kojto | 98:8ab26030e058 | 910 | * If locking the EMU registers, they must be unlocked prior to using any |
Kojto | 113:f141b2784e32 | 911 | * EMU API functions modifying EMU registers, excluding interrupt control |
Kojto | 113:f141b2784e32 | 912 | * and regulator control if the architecture has a EMU_PWRCTRL register. |
Kojto | 113:f141b2784e32 | 913 | * An exception to this is the energy mode entering API (EMU_EnterEMn()), |
Kojto | 113:f141b2784e32 | 914 | * which can be used when the EMU registers are locked. |
Kojto | 98:8ab26030e058 | 915 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 916 | __STATIC_INLINE void EMU_Lock(void) |
Kojto | 98:8ab26030e058 | 917 | { |
Kojto | 98:8ab26030e058 | 918 | EMU->LOCK = EMU_LOCK_LOCKKEY_LOCK; |
Kojto | 98:8ab26030e058 | 919 | } |
Kojto | 98:8ab26030e058 | 920 | |
Kojto | 98:8ab26030e058 | 921 | |
Kojto | 98:8ab26030e058 | 922 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 923 | * @brief |
Kojto | 98:8ab26030e058 | 924 | * Unlock the EMU so that writing to locked registers again is possible. |
Kojto | 98:8ab26030e058 | 925 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 926 | __STATIC_INLINE void EMU_Unlock(void) |
Kojto | 98:8ab26030e058 | 927 | { |
Kojto | 98:8ab26030e058 | 928 | EMU->LOCK = EMU_LOCK_LOCKKEY_UNLOCK; |
Kojto | 98:8ab26030e058 | 929 | } |
Kojto | 98:8ab26030e058 | 930 | |
Kojto | 113:f141b2784e32 | 931 | |
Kojto | 113:f141b2784e32 | 932 | #if defined( _EMU_PWRLOCK_MASK ) |
Kojto | 113:f141b2784e32 | 933 | /***************************************************************************//** |
Kojto | 113:f141b2784e32 | 934 | * @brief |
Kojto | 113:f141b2784e32 | 935 | * Lock the EMU regulator control registers in order to protect against |
Kojto | 113:f141b2784e32 | 936 | * unintended modification. |
Kojto | 113:f141b2784e32 | 937 | ******************************************************************************/ |
Kojto | 113:f141b2784e32 | 938 | __STATIC_INLINE void EMU_PowerLock(void) |
Kojto | 113:f141b2784e32 | 939 | { |
Kojto | 113:f141b2784e32 | 940 | EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_LOCK; |
Kojto | 113:f141b2784e32 | 941 | } |
Kojto | 113:f141b2784e32 | 942 | |
Kojto | 113:f141b2784e32 | 943 | |
Kojto | 113:f141b2784e32 | 944 | /***************************************************************************//** |
Kojto | 113:f141b2784e32 | 945 | * @brief |
Kojto | 113:f141b2784e32 | 946 | * Unlock the EMU power control registers so that writing to |
Kojto | 113:f141b2784e32 | 947 | * locked registers again is possible. |
Kojto | 113:f141b2784e32 | 948 | ******************************************************************************/ |
Kojto | 113:f141b2784e32 | 949 | __STATIC_INLINE void EMU_PowerUnlock(void) |
Kojto | 113:f141b2784e32 | 950 | { |
Kojto | 113:f141b2784e32 | 951 | EMU->PWRLOCK = EMU_PWRLOCK_LOCKKEY_UNLOCK; |
Kojto | 113:f141b2784e32 | 952 | } |
Kojto | 113:f141b2784e32 | 953 | #endif |
Kojto | 113:f141b2784e32 | 954 | |
Kojto | 113:f141b2784e32 | 955 | |
Kojto | 98:8ab26030e058 | 956 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 957 | * @brief |
Kojto | 98:8ab26030e058 | 958 | * Block entering EM2 or higher number energy modes. |
Kojto | 98:8ab26030e058 | 959 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 960 | __STATIC_INLINE void EMU_EM2Block(void) |
Kojto | 98:8ab26030e058 | 961 | { |
Kojto | 113:f141b2784e32 | 962 | BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 1U); |
Kojto | 98:8ab26030e058 | 963 | } |
Kojto | 98:8ab26030e058 | 964 | |
Kojto | 98:8ab26030e058 | 965 | /***************************************************************************//** |
Kojto | 98:8ab26030e058 | 966 | * @brief |
Kojto | 98:8ab26030e058 | 967 | * Unblock entering EM2 or higher number energy modes. |
Kojto | 98:8ab26030e058 | 968 | ******************************************************************************/ |
Kojto | 98:8ab26030e058 | 969 | __STATIC_INLINE void EMU_EM2UnBlock(void) |
Kojto | 98:8ab26030e058 | 970 | { |
Kojto | 113:f141b2784e32 | 971 | BUS_RegBitWrite(&(EMU->CTRL), _EMU_CTRL_EM2BLOCK_SHIFT, 0U); |
Kojto | 98:8ab26030e058 | 972 | } |
Kojto | 98:8ab26030e058 | 973 | |
Kojto | 113:f141b2784e32 | 974 | #if defined( _EMU_EM4CTRL_EM4IORETMODE_MASK ) |
Kojto | 113:f141b2784e32 | 975 | /***************************************************************************//** |
Kojto | 113:f141b2784e32 | 976 | * @brief |
Kojto | 113:f141b2784e32 | 977 | * When EM4 pin retention is set to emuPinRetentionLatch, then pins are retained |
Kojto | 113:f141b2784e32 | 978 | * through EM4 entry and wakeup. The pin state is released by calling this function. |
Kojto | 113:f141b2784e32 | 979 | * The feature allows peripherals or GPIO to be re-initialized after EM4 exit (reset), |
Kojto | 113:f141b2784e32 | 980 | * and when the initialization is done, this function can release pins and return control |
Kojto | 113:f141b2784e32 | 981 | * to the peripherals or GPIO. |
Kojto | 113:f141b2784e32 | 982 | ******************************************************************************/ |
Kojto | 113:f141b2784e32 | 983 | __STATIC_INLINE void EMU_UnlatchPinRetention(void) |
Kojto | 113:f141b2784e32 | 984 | { |
Kojto | 113:f141b2784e32 | 985 | EMU->CMD = EMU_CMD_EM4UNLATCH; |
Kojto | 113:f141b2784e32 | 986 | } |
Kojto | 113:f141b2784e32 | 987 | #endif |
Kojto | 98:8ab26030e058 | 988 | |
<> | 139:856d2700e60b | 989 | #if defined( _SILICON_LABS_GECKO_INTERNAL_SDID_80 ) |
<> | 128:9bcdf88f62b0 | 990 | void EMU_SetBiasMode(EMU_BiasMode_TypeDef mode); |
<> | 128:9bcdf88f62b0 | 991 | #endif |
<> | 128:9bcdf88f62b0 | 992 | |
Kojto | 98:8ab26030e058 | 993 | /** @} (end addtogroup EMU) */ |
<> | 128:9bcdf88f62b0 | 994 | /** @} (end addtogroup emlib) */ |
Kojto | 98:8ab26030e058 | 995 | |
Kojto | 98:8ab26030e058 | 996 | #ifdef __cplusplus |
Kojto | 98:8ab26030e058 | 997 | } |
Kojto | 98:8ab26030e058 | 998 | #endif |
Kojto | 98:8ab26030e058 | 999 | |
Kojto | 98:8ab26030e058 | 1000 | #endif /* defined( EMU_PRESENT ) */ |
<> | 128:9bcdf88f62b0 | 1001 | #endif /* EM_EMU_H */ |