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TARGET_SDT32620B/TOOLCHAIN_IAR/spim_regs.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 167:84c0a372a020 1 /*******************************************************************************
AnnaBridge 167:84c0a372a020 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
AnnaBridge 167:84c0a372a020 3 *
AnnaBridge 167:84c0a372a020 4 * Permission is hereby granted, free of charge, to any person obtaining a
AnnaBridge 167:84c0a372a020 5 * copy of this software and associated documentation files (the "Software"),
AnnaBridge 167:84c0a372a020 6 * to deal in the Software without restriction, including without limitation
AnnaBridge 167:84c0a372a020 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
AnnaBridge 167:84c0a372a020 8 * and/or sell copies of the Software, and to permit persons to whom the
AnnaBridge 167:84c0a372a020 9 * Software is furnished to do so, subject to the following conditions:
AnnaBridge 167:84c0a372a020 10 *
AnnaBridge 167:84c0a372a020 11 * The above copyright notice and this permission notice shall be included
AnnaBridge 167:84c0a372a020 12 * in all copies or substantial portions of the Software.
AnnaBridge 167:84c0a372a020 13 *
AnnaBridge 167:84c0a372a020 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
AnnaBridge 167:84c0a372a020 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
AnnaBridge 167:84c0a372a020 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
AnnaBridge 167:84c0a372a020 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
AnnaBridge 167:84c0a372a020 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
AnnaBridge 167:84c0a372a020 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
AnnaBridge 167:84c0a372a020 20 * OTHER DEALINGS IN THE SOFTWARE.
AnnaBridge 167:84c0a372a020 21 *
AnnaBridge 167:84c0a372a020 22 * Except as contained in this notice, the name of Maxim Integrated
AnnaBridge 167:84c0a372a020 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
AnnaBridge 167:84c0a372a020 24 * Products, Inc. Branding Policy.
AnnaBridge 167:84c0a372a020 25 *
AnnaBridge 167:84c0a372a020 26 * The mere transfer of this software does not imply any licenses
AnnaBridge 167:84c0a372a020 27 * of trade secrets, proprietary technology, copyrights, patents,
AnnaBridge 167:84c0a372a020 28 * trademarks, maskwork rights, or any other form of intellectual
AnnaBridge 167:84c0a372a020 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
AnnaBridge 167:84c0a372a020 30 * ownership rights.
AnnaBridge 167:84c0a372a020 31 *
AnnaBridge 167:84c0a372a020 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
AnnaBridge 167:84c0a372a020 33 * $Revision: 21839 $
AnnaBridge 167:84c0a372a020 34 *
AnnaBridge 167:84c0a372a020 35 ******************************************************************************/
AnnaBridge 167:84c0a372a020 36
AnnaBridge 167:84c0a372a020 37 #ifndef _MXC_SPIM_REGS_H_
AnnaBridge 167:84c0a372a020 38 #define _MXC_SPIM_REGS_H_
AnnaBridge 167:84c0a372a020 39
AnnaBridge 167:84c0a372a020 40 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 41 extern "C" {
AnnaBridge 167:84c0a372a020 42 #endif
AnnaBridge 167:84c0a372a020 43
AnnaBridge 167:84c0a372a020 44 #include <stdint.h>
AnnaBridge 167:84c0a372a020 45
AnnaBridge 167:84c0a372a020 46 /*
AnnaBridge 167:84c0a372a020 47 If types are not defined elsewhere (CMSIS) define them here
AnnaBridge 167:84c0a372a020 48 */
AnnaBridge 167:84c0a372a020 49 #ifndef __IO
AnnaBridge 167:84c0a372a020 50 #define __IO volatile
AnnaBridge 167:84c0a372a020 51 #endif
AnnaBridge 167:84c0a372a020 52 #ifndef __I
AnnaBridge 167:84c0a372a020 53 #define __I volatile const
AnnaBridge 167:84c0a372a020 54 #endif
AnnaBridge 167:84c0a372a020 55 #ifndef __O
AnnaBridge 167:84c0a372a020 56 #define __O volatile
AnnaBridge 167:84c0a372a020 57 #endif
AnnaBridge 167:84c0a372a020 58 #ifndef __RO
AnnaBridge 167:84c0a372a020 59 #define __RO volatile const
AnnaBridge 167:84c0a372a020 60 #endif
AnnaBridge 167:84c0a372a020 61
AnnaBridge 167:84c0a372a020 62
AnnaBridge 167:84c0a372a020 63 /*
AnnaBridge 167:84c0a372a020 64 Typedefed structure(s) for module registers (per instance or section) with direct 32-bit
AnnaBridge 167:84c0a372a020 65 access to each register in module.
AnnaBridge 167:84c0a372a020 66 */
AnnaBridge 167:84c0a372a020 67
AnnaBridge 167:84c0a372a020 68 /* Offset Register Description
AnnaBridge 167:84c0a372a020 69 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 70 typedef struct {
AnnaBridge 167:84c0a372a020 71 __IO uint32_t mstr_cfg; /* 0x0000 SPI Master Configuration Register */
AnnaBridge 167:84c0a372a020 72 __IO uint32_t ss_sr_polarity; /* 0x0004 SPI Master Polarity Control for SS and SR Signals */
AnnaBridge 167:84c0a372a020 73 __IO uint32_t gen_ctrl; /* 0x0008 SPI Master General Control Register */
AnnaBridge 167:84c0a372a020 74 __IO uint32_t fifo_ctrl; /* 0x000C SPI Master FIFO Control Register */
AnnaBridge 167:84c0a372a020 75 __IO uint32_t spcl_ctrl; /* 0x0010 SPI Master Special Mode Controls */
AnnaBridge 167:84c0a372a020 76 __IO uint32_t intfl; /* 0x0014 SPI Master Interrupt Flags */
AnnaBridge 167:84c0a372a020 77 __IO uint32_t inten; /* 0x0018 SPI Master Interrupt Enable/Disable Settings */
AnnaBridge 167:84c0a372a020 78 __IO uint32_t simple_headers; /* 0x001C SPI Master Simple Mode Transaction Headers */
AnnaBridge 167:84c0a372a020 79 } mxc_spim_regs_t;
AnnaBridge 167:84c0a372a020 80
AnnaBridge 167:84c0a372a020 81
AnnaBridge 167:84c0a372a020 82 /* Offset Register Description
AnnaBridge 167:84c0a372a020 83 ============= ============================================================================ */
AnnaBridge 167:84c0a372a020 84 typedef struct {
AnnaBridge 167:84c0a372a020 85 union { /* 0x0000-0x07FC SPI Master FIFO Write Space for Transaction Setup */
AnnaBridge 167:84c0a372a020 86 __IO uint8_t trans_8[2048];
AnnaBridge 167:84c0a372a020 87 __IO uint16_t trans_16[1024];
AnnaBridge 167:84c0a372a020 88 __IO uint32_t trans_32[512];
AnnaBridge 167:84c0a372a020 89 };
AnnaBridge 167:84c0a372a020 90 union { /* 0x0800-0x0FFC SPI Master FIFO Read Space for Results Data */
AnnaBridge 167:84c0a372a020 91 __IO uint8_t rslts_8[2048];
AnnaBridge 167:84c0a372a020 92 __IO uint16_t rslts_16[1024];
AnnaBridge 167:84c0a372a020 93 __IO uint32_t rslts_32[512];
AnnaBridge 167:84c0a372a020 94 };
AnnaBridge 167:84c0a372a020 95 } mxc_spim_fifo_regs_t;
AnnaBridge 167:84c0a372a020 96
AnnaBridge 167:84c0a372a020 97
AnnaBridge 167:84c0a372a020 98 /*
AnnaBridge 167:84c0a372a020 99 Register offsets for module SPIM.
AnnaBridge 167:84c0a372a020 100 */
AnnaBridge 167:84c0a372a020 101
AnnaBridge 167:84c0a372a020 102 #define MXC_R_SPIM_OFFS_MSTR_CFG ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 103 #define MXC_R_SPIM_OFFS_SS_SR_POLARITY ((uint32_t)0x00000004UL)
AnnaBridge 167:84c0a372a020 104 #define MXC_R_SPIM_OFFS_GEN_CTRL ((uint32_t)0x00000008UL)
AnnaBridge 167:84c0a372a020 105 #define MXC_R_SPIM_OFFS_FIFO_CTRL ((uint32_t)0x0000000CUL)
AnnaBridge 167:84c0a372a020 106 #define MXC_R_SPIM_OFFS_SPCL_CTRL ((uint32_t)0x00000010UL)
AnnaBridge 167:84c0a372a020 107 #define MXC_R_SPIM_OFFS_INTFL ((uint32_t)0x00000014UL)
AnnaBridge 167:84c0a372a020 108 #define MXC_R_SPIM_OFFS_INTEN ((uint32_t)0x00000018UL)
AnnaBridge 167:84c0a372a020 109 #define MXC_R_SPIM_OFFS_SIMPLE_HEADERS ((uint32_t)0x0000001CUL)
AnnaBridge 167:84c0a372a020 110 #define MXC_R_SPIM_FIFO_OFFS_TRANS ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 111 #define MXC_R_SPIM_FIFO_OFFS_RSLTS ((uint32_t)0x00000800UL)
AnnaBridge 167:84c0a372a020 112
AnnaBridge 167:84c0a372a020 113
AnnaBridge 167:84c0a372a020 114 /*
AnnaBridge 167:84c0a372a020 115 Field positions and masks for module SPIM.
AnnaBridge 167:84c0a372a020 116 */
AnnaBridge 167:84c0a372a020 117
AnnaBridge 167:84c0a372a020 118 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS 0
AnnaBridge 167:84c0a372a020 119 #define MXC_F_SPIM_MSTR_CFG_SLAVE_SEL ((uint32_t)(0x00000007UL << MXC_F_SPIM_MSTR_CFG_SLAVE_SEL_POS))
AnnaBridge 167:84c0a372a020 120 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS 3
AnnaBridge 167:84c0a372a020 121 #define MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_MSTR_CFG_THREE_WIRE_MODE_POS))
AnnaBridge 167:84c0a372a020 122 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS 4
AnnaBridge 167:84c0a372a020 123 #define MXC_F_SPIM_MSTR_CFG_SPI_MODE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_SPI_MODE_POS))
AnnaBridge 167:84c0a372a020 124 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS 6
AnnaBridge 167:84c0a372a020 125 #define MXC_F_SPIM_MSTR_CFG_PAGE_SIZE ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS))
AnnaBridge 167:84c0a372a020 126 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS 8
AnnaBridge 167:84c0a372a020 127 #define MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_HI_CLK_POS))
AnnaBridge 167:84c0a372a020 128 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS 12
AnnaBridge 167:84c0a372a020 129 #define MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SCK_LO_CLK_POS))
AnnaBridge 167:84c0a372a020 130 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS 16
AnnaBridge 167:84c0a372a020 131 #define MXC_F_SPIM_MSTR_CFG_ACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_ACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 132 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS 18
AnnaBridge 167:84c0a372a020 133 #define MXC_F_SPIM_MSTR_CFG_INACT_DELAY ((uint32_t)(0x00000003UL << MXC_F_SPIM_MSTR_CFG_INACT_DELAY_POS))
AnnaBridge 167:84c0a372a020 134 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS 20
AnnaBridge 167:84c0a372a020 135 #define MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_MSTR_CFG_SDIO_SAMPLE_POINT_POS))
AnnaBridge 167:84c0a372a020 136
AnnaBridge 167:84c0a372a020 137 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B ((uint32_t)0x00000000UL)
AnnaBridge 167:84c0a372a020 138 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B ((uint32_t)0x00000001UL)
AnnaBridge 167:84c0a372a020 139 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B ((uint32_t)0x00000002UL)
AnnaBridge 167:84c0a372a020 140 #define MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B ((uint32_t)0x00000003UL)
AnnaBridge 167:84c0a372a020 141
AnnaBridge 167:84c0a372a020 142 #define MXC_S_SPIM_MSTR_CFG_PAGE_4B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_4B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 167:84c0a372a020 143 #define MXC_S_SPIM_MSTR_CFG_PAGE_8B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_8B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 167:84c0a372a020 144 #define MXC_S_SPIM_MSTR_CFG_PAGE_16B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_16B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 167:84c0a372a020 145 #define MXC_S_SPIM_MSTR_CFG_PAGE_32B (MXC_V_SPIM_MSTR_CFG_PAGE_SIZE_32B << MXC_F_SPIM_MSTR_CFG_PAGE_SIZE_POS)
AnnaBridge 167:84c0a372a020 146
AnnaBridge 167:84c0a372a020 147 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS 0
AnnaBridge 167:84c0a372a020 148 #define MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_SS_POLARITY_POS))
AnnaBridge 167:84c0a372a020 149 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS 8
AnnaBridge 167:84c0a372a020 150 #define MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY ((uint32_t)(0x000000FFUL << MXC_F_SPIM_SS_SR_POLARITY_FC_POLARITY_POS))
AnnaBridge 167:84c0a372a020 151
AnnaBridge 167:84c0a372a020 152 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS 0
AnnaBridge 167:84c0a372a020 153 #define MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SPI_MSTR_EN_POS))
AnnaBridge 167:84c0a372a020 154 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS 1
AnnaBridge 167:84c0a372a020 155 #define MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_TX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 156 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS 2
AnnaBridge 167:84c0a372a020 157 #define MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_RX_FIFO_EN_POS))
AnnaBridge 167:84c0a372a020 158 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS 3
AnnaBridge 167:84c0a372a020 159 #define MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BIT_BANG_MODE_POS))
AnnaBridge 167:84c0a372a020 160 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS 4
AnnaBridge 167:84c0a372a020 161 #define MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SS_IN_OUT_POS))
AnnaBridge 167:84c0a372a020 162 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS 5
AnnaBridge 167:84c0a372a020 163 #define MXC_F_SPIM_GEN_CTRL_BB_SR_IN ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SR_IN_POS))
AnnaBridge 167:84c0a372a020 164 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS 6
AnnaBridge 167:84c0a372a020 165 #define MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_BB_SCK_IN_OUT_POS))
AnnaBridge 167:84c0a372a020 166 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS 8
AnnaBridge 167:84c0a372a020 167 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_IN_POS))
AnnaBridge 167:84c0a372a020 168 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS 12
AnnaBridge 167:84c0a372a020 169 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_OUT_POS))
AnnaBridge 167:84c0a372a020 170 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS 16
AnnaBridge 167:84c0a372a020 171 #define MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_GEN_CTRL_BB_SDIO_DR_EN_POS))
AnnaBridge 167:84c0a372a020 172 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS 20
AnnaBridge 167:84c0a372a020 173 #define MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_SIMPLE_MODE_POS))
AnnaBridge 167:84c0a372a020 174 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS 21
AnnaBridge 167:84c0a372a020 175 #define MXC_F_SPIM_GEN_CTRL_START_RX_ONLY ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_START_RX_ONLY_POS))
AnnaBridge 167:84c0a372a020 176 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS 22
AnnaBridge 167:84c0a372a020 177 #define MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_DEASSERT_ACT_SS_POS))
AnnaBridge 167:84c0a372a020 178 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS 24
AnnaBridge 167:84c0a372a020 179 #define MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_ENABLE_SCK_FB_MODE_POS))
AnnaBridge 167:84c0a372a020 180 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS 25
AnnaBridge 167:84c0a372a020 181 #define MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK ((uint32_t)(0x00000001UL << MXC_F_SPIM_GEN_CTRL_INVERT_SCK_FB_CLK_POS))
AnnaBridge 167:84c0a372a020 182
AnnaBridge 167:84c0a372a020 183 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS 0
AnnaBridge 167:84c0a372a020 184 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL ((uint32_t)(0x0000000FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_AE_LVL_POS))
AnnaBridge 167:84c0a372a020 185 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS 8
AnnaBridge 167:84c0a372a020 186 #define MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_TX_FIFO_USED_POS))
AnnaBridge 167:84c0a372a020 187 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS 16
AnnaBridge 167:84c0a372a020 188 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL ((uint32_t)(0x0000001FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_AF_LVL_POS))
AnnaBridge 167:84c0a372a020 189 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS 24
AnnaBridge 167:84c0a372a020 190 #define MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED ((uint32_t)(0x0000003FUL << MXC_F_SPIM_FIFO_CTRL_RX_FIFO_USED_POS))
AnnaBridge 167:84c0a372a020 191
AnnaBridge 167:84c0a372a020 192 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS 0
AnnaBridge 167:84c0a372a020 193 #define MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SS_SAMPLE_MODE_POS))
AnnaBridge 167:84c0a372a020 194 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS 1
AnnaBridge 167:84c0a372a020 195 #define MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_MISO_FC_EN_POS))
AnnaBridge 167:84c0a372a020 196 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS 4
AnnaBridge 167:84c0a372a020 197 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_OUT_POS))
AnnaBridge 167:84c0a372a020 198 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS 8
AnnaBridge 167:84c0a372a020 199 #define MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SS_SA_SDIO_DR_EN_POS))
AnnaBridge 167:84c0a372a020 200
AnnaBridge 167:84c0a372a020 201 #if (MXC_SPIM_REV == 0)
AnnaBridge 167:84c0a372a020 202 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS 16
AnnaBridge 167:84c0a372a020 203 #define MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN ((uint32_t)(0x00000001UL << MXC_F_SPIM_SPCL_CTRL_SPECIAL_MODE_3_EN_POS))
AnnaBridge 167:84c0a372a020 204 #else
AnnaBridge 167:84c0a372a020 205 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS 12
AnnaBridge 167:84c0a372a020 206 #define MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN ((uint32_t)(0x00000007UL << MXC_F_SPIM_SPCL_CTRL_RX_FIFO_MARGIN_POS))
AnnaBridge 167:84c0a372a020 207 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS 16
AnnaBridge 167:84c0a372a020 208 #define MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY ((uint32_t)(0x0000000FUL << MXC_F_SPIM_SPCL_CTRL_SCK_FB_DELAY_POS))
AnnaBridge 167:84c0a372a020 209 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS 20
AnnaBridge 167:84c0a372a020 210 #define MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED ((uint32_t)(0x00000FFFUL << MXC_F_SPIM_SPCL_CTRL_SPARE_RESERVED_POS))
AnnaBridge 167:84c0a372a020 211 #endif
AnnaBridge 167:84c0a372a020 212
AnnaBridge 167:84c0a372a020 213 #define MXC_F_SPIM_INTFL_TX_STALLED_POS 0
AnnaBridge 167:84c0a372a020 214 #define MXC_F_SPIM_INTFL_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_STALLED_POS))
AnnaBridge 167:84c0a372a020 215 #define MXC_F_SPIM_INTFL_RX_STALLED_POS 1
AnnaBridge 167:84c0a372a020 216 #define MXC_F_SPIM_INTFL_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_STALLED_POS))
AnnaBridge 167:84c0a372a020 217 #define MXC_F_SPIM_INTFL_TX_READY_POS 2
AnnaBridge 167:84c0a372a020 218 #define MXC_F_SPIM_INTFL_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_READY_POS))
AnnaBridge 167:84c0a372a020 219 #define MXC_F_SPIM_INTFL_RX_DONE_POS 3
AnnaBridge 167:84c0a372a020 220 #define MXC_F_SPIM_INTFL_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_DONE_POS))
AnnaBridge 167:84c0a372a020 221 #define MXC_F_SPIM_INTFL_TX_FIFO_AE_POS 4
AnnaBridge 167:84c0a372a020 222 #define MXC_F_SPIM_INTFL_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_TX_FIFO_AE_POS))
AnnaBridge 167:84c0a372a020 223 #define MXC_F_SPIM_INTFL_RX_FIFO_AF_POS 5
AnnaBridge 167:84c0a372a020 224 #define MXC_F_SPIM_INTFL_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTFL_RX_FIFO_AF_POS))
AnnaBridge 167:84c0a372a020 225
AnnaBridge 167:84c0a372a020 226 #define MXC_F_SPIM_INTEN_TX_STALLED_POS 0
AnnaBridge 167:84c0a372a020 227 #define MXC_F_SPIM_INTEN_TX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_STALLED_POS))
AnnaBridge 167:84c0a372a020 228 #define MXC_F_SPIM_INTEN_RX_STALLED_POS 1
AnnaBridge 167:84c0a372a020 229 #define MXC_F_SPIM_INTEN_RX_STALLED ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_STALLED_POS))
AnnaBridge 167:84c0a372a020 230 #define MXC_F_SPIM_INTEN_TX_READY_POS 2
AnnaBridge 167:84c0a372a020 231 #define MXC_F_SPIM_INTEN_TX_READY ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_READY_POS))
AnnaBridge 167:84c0a372a020 232 #define MXC_F_SPIM_INTEN_RX_DONE_POS 3
AnnaBridge 167:84c0a372a020 233 #define MXC_F_SPIM_INTEN_RX_DONE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_DONE_POS))
AnnaBridge 167:84c0a372a020 234 #define MXC_F_SPIM_INTEN_TX_FIFO_AE_POS 4
AnnaBridge 167:84c0a372a020 235 #define MXC_F_SPIM_INTEN_TX_FIFO_AE ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_TX_FIFO_AE_POS))
AnnaBridge 167:84c0a372a020 236 #define MXC_F_SPIM_INTEN_RX_FIFO_AF_POS 5
AnnaBridge 167:84c0a372a020 237 #define MXC_F_SPIM_INTEN_RX_FIFO_AF ((uint32_t)(0x00000001UL << MXC_F_SPIM_INTEN_RX_FIFO_AF_POS))
AnnaBridge 167:84c0a372a020 238
AnnaBridge 167:84c0a372a020 239 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS 0
AnnaBridge 167:84c0a372a020 240 #define MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_TX_BIDIR_HEADER_POS))
AnnaBridge 167:84c0a372a020 241 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS 16
AnnaBridge 167:84c0a372a020 242 #define MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER ((uint32_t)(0x00003FFFUL << MXC_F_SPIM_SIMPLE_HEADERS_RX_ONLY_HEADER_POS))
AnnaBridge 167:84c0a372a020 243
AnnaBridge 167:84c0a372a020 244
AnnaBridge 167:84c0a372a020 245
AnnaBridge 167:84c0a372a020 246 #ifdef __cplusplus
AnnaBridge 167:84c0a372a020 247 }
AnnaBridge 167:84c0a372a020 248 #endif
AnnaBridge 167:84c0a372a020 249
AnnaBridge 167:84c0a372a020 250 #endif /* _MXC_SPIM_REGS_H_ */
AnnaBridge 167:84c0a372a020 251