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TARGET_RO359B/TOOLCHAIN_GCC_ARM/MK24F12.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 143:86740a56073b 1 /*
AnnaBridge 143:86740a56073b 2 ** ###################################################################
AnnaBridge 143:86740a56073b 3 ** Processors: MK24FN1M0CAJ12
AnnaBridge 143:86740a56073b 4 ** MK24FN1M0VDC12
AnnaBridge 143:86740a56073b 5 ** MK24FN1M0VLL12
AnnaBridge 143:86740a56073b 6 ** MK24FN1M0VLQ12
AnnaBridge 143:86740a56073b 7 **
AnnaBridge 143:86740a56073b 8 ** Compilers: Keil ARM C/C++ Compiler
AnnaBridge 143:86740a56073b 9 ** Freescale C/C++ for Embedded ARM
AnnaBridge 143:86740a56073b 10 ** GNU C Compiler
AnnaBridge 143:86740a56073b 11 ** IAR ANSI C/C++ Compiler for ARM
AnnaBridge 143:86740a56073b 12 ** MCUXpresso Compiler
AnnaBridge 143:86740a56073b 13 **
AnnaBridge 143:86740a56073b 14 ** Reference manual: K24P144M120SF5RM, Rev.2, January 2014
AnnaBridge 143:86740a56073b 15 ** Version: rev. 2.8, 2016-03-21
AnnaBridge 143:86740a56073b 16 ** Build: b170112
AnnaBridge 143:86740a56073b 17 **
AnnaBridge 143:86740a56073b 18 ** Abstract:
AnnaBridge 143:86740a56073b 19 ** CMSIS Peripheral Access Layer for MK24F12
AnnaBridge 143:86740a56073b 20 **
AnnaBridge 143:86740a56073b 21 ** Copyright (c) 1997 - 2016 Freescale Semiconductor, Inc.
AnnaBridge 143:86740a56073b 22 ** Copyright 2016 - 2017 NXP
AnnaBridge 143:86740a56073b 23 ** Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 143:86740a56073b 24 ** are permitted provided that the following conditions are met:
AnnaBridge 143:86740a56073b 25 **
AnnaBridge 143:86740a56073b 26 ** o Redistributions of source code must retain the above copyright notice, this list
AnnaBridge 143:86740a56073b 27 ** of conditions and the following disclaimer.
AnnaBridge 143:86740a56073b 28 **
AnnaBridge 143:86740a56073b 29 ** o Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 143:86740a56073b 30 ** list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 143:86740a56073b 31 ** other materials provided with the distribution.
AnnaBridge 143:86740a56073b 32 **
AnnaBridge 143:86740a56073b 33 ** o Neither the name of the copyright holder nor the names of its
AnnaBridge 143:86740a56073b 34 ** contributors may be used to endorse or promote products derived from this
AnnaBridge 143:86740a56073b 35 ** software without specific prior written permission.
AnnaBridge 143:86740a56073b 36 **
AnnaBridge 143:86740a56073b 37 ** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 143:86740a56073b 38 ** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 143:86740a56073b 39 ** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 143:86740a56073b 40 ** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 143:86740a56073b 41 ** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 143:86740a56073b 42 ** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 143:86740a56073b 43 ** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 143:86740a56073b 44 ** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 143:86740a56073b 45 ** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 143:86740a56073b 46 ** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 143:86740a56073b 47 **
AnnaBridge 143:86740a56073b 48 ** http: www.nxp.com
AnnaBridge 143:86740a56073b 49 ** mail: support@nxp.com
AnnaBridge 143:86740a56073b 50 **
AnnaBridge 143:86740a56073b 51 ** Revisions:
AnnaBridge 143:86740a56073b 52 ** - rev. 1.0 (2013-08-12)
AnnaBridge 143:86740a56073b 53 ** Initial version.
AnnaBridge 143:86740a56073b 54 ** - rev. 2.0 (2013-10-29)
AnnaBridge 143:86740a56073b 55 ** Register accessor macros added to the memory map.
AnnaBridge 143:86740a56073b 56 ** Symbols for Processor Expert memory map compatibility added to the memory map.
AnnaBridge 143:86740a56073b 57 ** Startup file for gcc has been updated according to CMSIS 3.2.
AnnaBridge 143:86740a56073b 58 ** System initialization updated.
AnnaBridge 143:86740a56073b 59 ** MCG - registers updated.
AnnaBridge 143:86740a56073b 60 ** PORTA, PORTB, PORTC, PORTE - registers for digital filter removed.
AnnaBridge 143:86740a56073b 61 ** - rev. 2.1 (2013-10-30)
AnnaBridge 143:86740a56073b 62 ** Definition of BITBAND macros updated to support peripherals with 32-bit acces disabled.
AnnaBridge 143:86740a56073b 63 ** - rev. 2.2 (2013-12-09)
AnnaBridge 143:86740a56073b 64 ** DMA - EARS register removed.
AnnaBridge 143:86740a56073b 65 ** AIPS0, AIPS1 - MPRA register updated.
AnnaBridge 143:86740a56073b 66 ** - rev. 2.3 (2014-01-24)
AnnaBridge 143:86740a56073b 67 ** Update according to reference manual rev. 2
AnnaBridge 143:86740a56073b 68 ** ENET, MCG, MCM, SIM, USB - registers updated
AnnaBridge 143:86740a56073b 69 ** - rev. 2.4 (2014-02-10)
AnnaBridge 143:86740a56073b 70 ** The declaration of clock configurations has been moved to separate header file system_MK24F12.h
AnnaBridge 143:86740a56073b 71 ** Update of SystemInit() and SystemCoreClockUpdate() functions.
AnnaBridge 143:86740a56073b 72 ** Module access macro module_BASES replaced by module_BASE_PTRS.
AnnaBridge 143:86740a56073b 73 ** - rev. 2.5 (2014-08-28)
AnnaBridge 143:86740a56073b 74 ** Update of system files - default clock configuration changed.
AnnaBridge 143:86740a56073b 75 ** Update of startup files - possibility to override DefaultISR added.
AnnaBridge 143:86740a56073b 76 ** - rev. 2.6 (2014-10-14)
AnnaBridge 143:86740a56073b 77 ** Interrupt INT_LPTimer renamed to INT_LPTMR0, interrupt INT_Watchdog renamed to INT_WDOG_EWM.
AnnaBridge 143:86740a56073b 78 ** - rev. 2.7 (2015-02-19)
AnnaBridge 143:86740a56073b 79 ** Renamed interrupt vector LLW to LLWU.
AnnaBridge 143:86740a56073b 80 ** - rev. 2.8 (2016-03-21)
AnnaBridge 143:86740a56073b 81 ** Added MK24FN1M0CAJ12 part.
AnnaBridge 143:86740a56073b 82 ** GPIO - renamed port instances: PTx -> GPIOx.
AnnaBridge 143:86740a56073b 83 **
AnnaBridge 143:86740a56073b 84 ** ###################################################################
AnnaBridge 143:86740a56073b 85 */
AnnaBridge 143:86740a56073b 86
AnnaBridge 143:86740a56073b 87 /*!
AnnaBridge 143:86740a56073b 88 * @file MK24F12.h
AnnaBridge 143:86740a56073b 89 * @version 2.8
AnnaBridge 143:86740a56073b 90 * @date 2016-03-21
AnnaBridge 143:86740a56073b 91 * @brief CMSIS Peripheral Access Layer for MK24F12
AnnaBridge 143:86740a56073b 92 *
AnnaBridge 143:86740a56073b 93 * CMSIS Peripheral Access Layer for MK24F12
AnnaBridge 143:86740a56073b 94 */
AnnaBridge 143:86740a56073b 95
AnnaBridge 143:86740a56073b 96 #ifndef _MK24F12_H_
AnnaBridge 143:86740a56073b 97 #define _MK24F12_H_ /**< Symbol preventing repeated inclusion */
AnnaBridge 143:86740a56073b 98
AnnaBridge 143:86740a56073b 99 /** Memory map major version (memory maps with equal major version number are
AnnaBridge 143:86740a56073b 100 * compatible) */
AnnaBridge 143:86740a56073b 101 #define MCU_MEM_MAP_VERSION 0x0200U
AnnaBridge 143:86740a56073b 102 /** Memory map minor version */
AnnaBridge 143:86740a56073b 103 #define MCU_MEM_MAP_VERSION_MINOR 0x0008U
AnnaBridge 143:86740a56073b 104
AnnaBridge 143:86740a56073b 105 /**
AnnaBridge 143:86740a56073b 106 * @brief Macro to calculate address of an aliased word in the peripheral
AnnaBridge 143:86740a56073b 107 * bitband area for a peripheral register and bit (bit band region 0x40000000 to
AnnaBridge 143:86740a56073b 108 * 0x400FFFFF).
AnnaBridge 143:86740a56073b 109 * @param Reg Register to access.
AnnaBridge 143:86740a56073b 110 * @param Bit Bit number to access.
AnnaBridge 143:86740a56073b 111 * @return Address of the aliased word in the peripheral bitband area.
AnnaBridge 143:86740a56073b 112 */
AnnaBridge 143:86740a56073b 113 #define BITBAND_REGADDR(Reg,Bit) (0x42000000u + (32u*((uint32_t)&(Reg) - (uint32_t)0x40000000u)) + (4u*((uint32_t)(Bit))))
AnnaBridge 143:86740a56073b 114 /**
AnnaBridge 143:86740a56073b 115 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 143:86740a56073b 116 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 143:86740a56073b 117 * be used for peripherals with 32bit access allowed.
AnnaBridge 143:86740a56073b 118 * @param Reg Register to access.
AnnaBridge 143:86740a56073b 119 * @param Bit Bit number to access.
AnnaBridge 143:86740a56073b 120 * @return Value of the targeted bit in the bit band region.
AnnaBridge 143:86740a56073b 121 */
AnnaBridge 143:86740a56073b 122 #define BITBAND_REG32(Reg,Bit) (*((uint32_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 143:86740a56073b 123 #define BITBAND_REG(Reg,Bit) (BITBAND_REG32((Reg),(Bit)))
AnnaBridge 143:86740a56073b 124 /**
AnnaBridge 143:86740a56073b 125 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 143:86740a56073b 126 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 143:86740a56073b 127 * be used for peripherals with 16bit access allowed.
AnnaBridge 143:86740a56073b 128 * @param Reg Register to access.
AnnaBridge 143:86740a56073b 129 * @param Bit Bit number to access.
AnnaBridge 143:86740a56073b 130 * @return Value of the targeted bit in the bit band region.
AnnaBridge 143:86740a56073b 131 */
AnnaBridge 143:86740a56073b 132 #define BITBAND_REG16(Reg,Bit) (*((uint16_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 143:86740a56073b 133 /**
AnnaBridge 143:86740a56073b 134 * @brief Macro to access a single bit of a peripheral register (bit band region
AnnaBridge 143:86740a56073b 135 * 0x40000000 to 0x400FFFFF) using the bit-band alias region access. Can
AnnaBridge 143:86740a56073b 136 * be used for peripherals with 8bit access allowed.
AnnaBridge 143:86740a56073b 137 * @param Reg Register to access.
AnnaBridge 143:86740a56073b 138 * @param Bit Bit number to access.
AnnaBridge 143:86740a56073b 139 * @return Value of the targeted bit in the bit band region.
AnnaBridge 143:86740a56073b 140 */
AnnaBridge 143:86740a56073b 141 #define BITBAND_REG8(Reg,Bit) (*((uint8_t volatile*)(BITBAND_REGADDR((Reg),(Bit)))))
AnnaBridge 143:86740a56073b 142
AnnaBridge 143:86740a56073b 143 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 144 -- Interrupt vector numbers
AnnaBridge 143:86740a56073b 145 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 146
AnnaBridge 143:86740a56073b 147 /*!
AnnaBridge 143:86740a56073b 148 * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
AnnaBridge 143:86740a56073b 149 * @{
AnnaBridge 143:86740a56073b 150 */
AnnaBridge 143:86740a56073b 151
AnnaBridge 143:86740a56073b 152 /** Interrupt Number Definitions */
AnnaBridge 143:86740a56073b 153 #define NUMBER_OF_INT_VECTORS 102 /**< Number of interrupts in the Vector table */
AnnaBridge 143:86740a56073b 154
AnnaBridge 143:86740a56073b 155 typedef enum IRQn {
AnnaBridge 143:86740a56073b 156 /* Auxiliary constants */
AnnaBridge 143:86740a56073b 157 NotAvail_IRQn = -128, /**< Not available device specific interrupt */
AnnaBridge 143:86740a56073b 158
AnnaBridge 143:86740a56073b 159 /* Core interrupts */
AnnaBridge 143:86740a56073b 160 NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
AnnaBridge 143:86740a56073b 161 HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
AnnaBridge 143:86740a56073b 162 MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
AnnaBridge 143:86740a56073b 163 BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
AnnaBridge 143:86740a56073b 164 UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
AnnaBridge 143:86740a56073b 165 SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
AnnaBridge 143:86740a56073b 166 DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
AnnaBridge 143:86740a56073b 167 PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
AnnaBridge 143:86740a56073b 168 SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
AnnaBridge 143:86740a56073b 169
AnnaBridge 143:86740a56073b 170 /* Device specific interrupts */
AnnaBridge 143:86740a56073b 171 DMA0_IRQn = 0, /**< DMA Channel 0 Transfer Complete */
AnnaBridge 143:86740a56073b 172 DMA1_IRQn = 1, /**< DMA Channel 1 Transfer Complete */
AnnaBridge 143:86740a56073b 173 DMA2_IRQn = 2, /**< DMA Channel 2 Transfer Complete */
AnnaBridge 143:86740a56073b 174 DMA3_IRQn = 3, /**< DMA Channel 3 Transfer Complete */
AnnaBridge 143:86740a56073b 175 DMA4_IRQn = 4, /**< DMA Channel 4 Transfer Complete */
AnnaBridge 143:86740a56073b 176 DMA5_IRQn = 5, /**< DMA Channel 5 Transfer Complete */
AnnaBridge 143:86740a56073b 177 DMA6_IRQn = 6, /**< DMA Channel 6 Transfer Complete */
AnnaBridge 143:86740a56073b 178 DMA7_IRQn = 7, /**< DMA Channel 7 Transfer Complete */
AnnaBridge 143:86740a56073b 179 DMA8_IRQn = 8, /**< DMA Channel 8 Transfer Complete */
AnnaBridge 143:86740a56073b 180 DMA9_IRQn = 9, /**< DMA Channel 9 Transfer Complete */
AnnaBridge 143:86740a56073b 181 DMA10_IRQn = 10, /**< DMA Channel 10 Transfer Complete */
AnnaBridge 143:86740a56073b 182 DMA11_IRQn = 11, /**< DMA Channel 11 Transfer Complete */
AnnaBridge 143:86740a56073b 183 DMA12_IRQn = 12, /**< DMA Channel 12 Transfer Complete */
AnnaBridge 143:86740a56073b 184 DMA13_IRQn = 13, /**< DMA Channel 13 Transfer Complete */
AnnaBridge 143:86740a56073b 185 DMA14_IRQn = 14, /**< DMA Channel 14 Transfer Complete */
AnnaBridge 143:86740a56073b 186 DMA15_IRQn = 15, /**< DMA Channel 15 Transfer Complete */
AnnaBridge 143:86740a56073b 187 DMA_Error_IRQn = 16, /**< DMA Error Interrupt */
AnnaBridge 143:86740a56073b 188 MCM_IRQn = 17, /**< Normal Interrupt */
AnnaBridge 143:86740a56073b 189 FTFE_IRQn = 18, /**< FTFE Command complete interrupt */
AnnaBridge 143:86740a56073b 190 Read_Collision_IRQn = 19, /**< Read Collision Interrupt */
AnnaBridge 143:86740a56073b 191 LVD_LVW_IRQn = 20, /**< Low Voltage Detect, Low Voltage Warning */
AnnaBridge 143:86740a56073b 192 LLWU_IRQn = 21, /**< Low Leakage Wakeup Unit */
AnnaBridge 143:86740a56073b 193 WDOG_EWM_IRQn = 22, /**< WDOG Interrupt */
AnnaBridge 143:86740a56073b 194 RNG_IRQn = 23, /**< RNG Interrupt */
AnnaBridge 143:86740a56073b 195 I2C0_IRQn = 24, /**< I2C0 interrupt */
AnnaBridge 143:86740a56073b 196 I2C1_IRQn = 25, /**< I2C1 interrupt */
AnnaBridge 143:86740a56073b 197 SPI0_IRQn = 26, /**< SPI0 Interrupt */
AnnaBridge 143:86740a56073b 198 SPI1_IRQn = 27, /**< SPI1 Interrupt */
AnnaBridge 143:86740a56073b 199 I2S0_Tx_IRQn = 28, /**< I2S0 transmit interrupt */
AnnaBridge 143:86740a56073b 200 I2S0_Rx_IRQn = 29, /**< I2S0 receive interrupt */
AnnaBridge 143:86740a56073b 201 UART0_LON_IRQn = 30, /**< UART0 LON interrupt */
AnnaBridge 143:86740a56073b 202 UART0_RX_TX_IRQn = 31, /**< UART0 Receive/Transmit interrupt */
AnnaBridge 143:86740a56073b 203 UART0_ERR_IRQn = 32, /**< UART0 Error interrupt */
AnnaBridge 143:86740a56073b 204 UART1_RX_TX_IRQn = 33, /**< UART1 Receive/Transmit interrupt */
AnnaBridge 143:86740a56073b 205 UART1_ERR_IRQn = 34, /**< UART1 Error interrupt */
AnnaBridge 143:86740a56073b 206 UART2_RX_TX_IRQn = 35, /**< UART2 Receive/Transmit interrupt */
AnnaBridge 143:86740a56073b 207 UART2_ERR_IRQn = 36, /**< UART2 Error interrupt */
AnnaBridge 143:86740a56073b 208 UART3_RX_TX_IRQn = 37, /**< UART3 Receive/Transmit interrupt */
AnnaBridge 143:86740a56073b 209 UART3_ERR_IRQn = 38, /**< UART3 Error interrupt */
AnnaBridge 143:86740a56073b 210 ADC0_IRQn = 39, /**< ADC0 interrupt */
AnnaBridge 143:86740a56073b 211 CMP0_IRQn = 40, /**< CMP0 interrupt */
AnnaBridge 143:86740a56073b 212 CMP1_IRQn = 41, /**< CMP1 interrupt */
AnnaBridge 143:86740a56073b 213 FTM0_IRQn = 42, /**< FTM0 fault, overflow and channels interrupt */
AnnaBridge 143:86740a56073b 214 FTM1_IRQn = 43, /**< FTM1 fault, overflow and channels interrupt */
AnnaBridge 143:86740a56073b 215 FTM2_IRQn = 44, /**< FTM2 fault, overflow and channels interrupt */
AnnaBridge 143:86740a56073b 216 CMT_IRQn = 45, /**< CMT interrupt */
AnnaBridge 143:86740a56073b 217 RTC_IRQn = 46, /**< RTC interrupt */
AnnaBridge 143:86740a56073b 218 RTC_Seconds_IRQn = 47, /**< RTC seconds interrupt */
AnnaBridge 143:86740a56073b 219 PIT0_IRQn = 48, /**< PIT timer channel 0 interrupt */
AnnaBridge 143:86740a56073b 220 PIT1_IRQn = 49, /**< PIT timer channel 1 interrupt */
AnnaBridge 143:86740a56073b 221 PIT2_IRQn = 50, /**< PIT timer channel 2 interrupt */
AnnaBridge 143:86740a56073b 222 PIT3_IRQn = 51, /**< PIT timer channel 3 interrupt */
AnnaBridge 143:86740a56073b 223 PDB0_IRQn = 52, /**< PDB0 Interrupt */
AnnaBridge 143:86740a56073b 224 USB0_IRQn = 53, /**< USB0 interrupt */
AnnaBridge 143:86740a56073b 225 USBDCD_IRQn = 54, /**< USBDCD Interrupt */
AnnaBridge 143:86740a56073b 226 Reserved71_IRQn = 55, /**< Reserved interrupt 71 */
AnnaBridge 143:86740a56073b 227 DAC0_IRQn = 56, /**< DAC0 interrupt */
AnnaBridge 143:86740a56073b 228 MCG_IRQn = 57, /**< MCG Interrupt */
AnnaBridge 143:86740a56073b 229 LPTMR0_IRQn = 58, /**< LPTimer interrupt */
AnnaBridge 143:86740a56073b 230 PORTA_IRQn = 59, /**< Port A interrupt */
AnnaBridge 143:86740a56073b 231 PORTB_IRQn = 60, /**< Port B interrupt */
AnnaBridge 143:86740a56073b 232 PORTC_IRQn = 61, /**< Port C interrupt */
AnnaBridge 143:86740a56073b 233 PORTD_IRQn = 62, /**< Port D interrupt */
AnnaBridge 143:86740a56073b 234 PORTE_IRQn = 63, /**< Port E interrupt */
AnnaBridge 143:86740a56073b 235 SWI_IRQn = 64, /**< Software interrupt */
AnnaBridge 143:86740a56073b 236 SPI2_IRQn = 65, /**< SPI2 Interrupt */
AnnaBridge 143:86740a56073b 237 UART4_RX_TX_IRQn = 66, /**< UART4 Receive/Transmit interrupt */
AnnaBridge 143:86740a56073b 238 UART4_ERR_IRQn = 67, /**< UART4 Error interrupt */
AnnaBridge 143:86740a56073b 239 UART5_RX_TX_IRQn = 68, /**< UART5 Receive/Transmit interrupt */
AnnaBridge 143:86740a56073b 240 UART5_ERR_IRQn = 69, /**< UART5 Error interrupt */
AnnaBridge 143:86740a56073b 241 CMP2_IRQn = 70, /**< CMP2 interrupt */
AnnaBridge 143:86740a56073b 242 FTM3_IRQn = 71, /**< FTM3 fault, overflow and channels interrupt */
AnnaBridge 143:86740a56073b 243 DAC1_IRQn = 72, /**< DAC1 interrupt */
AnnaBridge 143:86740a56073b 244 ADC1_IRQn = 73, /**< ADC1 interrupt */
AnnaBridge 143:86740a56073b 245 I2C2_IRQn = 74, /**< I2C2 interrupt */
AnnaBridge 143:86740a56073b 246 CAN0_ORed_Message_buffer_IRQn = 75, /**< CAN0 OR'd message buffers interrupt */
AnnaBridge 143:86740a56073b 247 CAN0_Bus_Off_IRQn = 76, /**< CAN0 bus off interrupt */
AnnaBridge 143:86740a56073b 248 CAN0_Error_IRQn = 77, /**< CAN0 error interrupt */
AnnaBridge 143:86740a56073b 249 CAN0_Tx_Warning_IRQn = 78, /**< CAN0 Tx warning interrupt */
AnnaBridge 143:86740a56073b 250 CAN0_Rx_Warning_IRQn = 79, /**< CAN0 Rx warning interrupt */
AnnaBridge 143:86740a56073b 251 CAN0_Wake_Up_IRQn = 80, /**< CAN0 wake up interrupt */
AnnaBridge 143:86740a56073b 252 SDHC_IRQn = 81, /**< SDHC interrupt */
AnnaBridge 143:86740a56073b 253 Reserved98_IRQn = 82, /**< Reserved interrupt 98 */
AnnaBridge 143:86740a56073b 254 Reserved99_IRQn = 83, /**< Reserved interrupt 99 */
AnnaBridge 143:86740a56073b 255 Reserved100_IRQn = 84, /**< Reserved interrupt 100 */
AnnaBridge 143:86740a56073b 256 Reserved101_IRQn = 85 /**< Reserved interrupt 101 */
AnnaBridge 143:86740a56073b 257 } IRQn_Type;
AnnaBridge 143:86740a56073b 258
AnnaBridge 143:86740a56073b 259 /*!
AnnaBridge 143:86740a56073b 260 * @}
AnnaBridge 143:86740a56073b 261 */ /* end of group Interrupt_vector_numbers */
AnnaBridge 143:86740a56073b 262
AnnaBridge 143:86740a56073b 263
AnnaBridge 143:86740a56073b 264 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 265 -- Cortex M4 Core Configuration
AnnaBridge 143:86740a56073b 266 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 267
AnnaBridge 143:86740a56073b 268 /*!
AnnaBridge 143:86740a56073b 269 * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
AnnaBridge 143:86740a56073b 270 * @{
AnnaBridge 143:86740a56073b 271 */
AnnaBridge 143:86740a56073b 272
AnnaBridge 143:86740a56073b 273 #define __MPU_PRESENT 0 /**< Defines if an MPU is present or not */
AnnaBridge 143:86740a56073b 274 #define __NVIC_PRIO_BITS 4 /**< Number of priority bits implemented in the NVIC */
AnnaBridge 143:86740a56073b 275 #define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
AnnaBridge 143:86740a56073b 276 #define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
AnnaBridge 143:86740a56073b 277
AnnaBridge 143:86740a56073b 278 #include "core_cm4.h" /* Core Peripheral Access Layer */
AnnaBridge 143:86740a56073b 279 #include "system_MK24F12.h" /* Device specific configuration file */
AnnaBridge 143:86740a56073b 280
AnnaBridge 143:86740a56073b 281 /*!
AnnaBridge 143:86740a56073b 282 * @}
AnnaBridge 143:86740a56073b 283 */ /* end of group Cortex_Core_Configuration */
AnnaBridge 143:86740a56073b 284
AnnaBridge 143:86740a56073b 285
AnnaBridge 143:86740a56073b 286 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 287 -- Mapping Information
AnnaBridge 143:86740a56073b 288 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 289
AnnaBridge 143:86740a56073b 290 /*!
AnnaBridge 143:86740a56073b 291 * @addtogroup Mapping_Information Mapping Information
AnnaBridge 143:86740a56073b 292 * @{
AnnaBridge 143:86740a56073b 293 */
AnnaBridge 143:86740a56073b 294
AnnaBridge 143:86740a56073b 295 /** Mapping Information */
AnnaBridge 143:86740a56073b 296 /*!
AnnaBridge 143:86740a56073b 297 * @addtogroup edma_request
AnnaBridge 143:86740a56073b 298 * @{
AnnaBridge 143:86740a56073b 299 */
AnnaBridge 143:86740a56073b 300
AnnaBridge 143:86740a56073b 301 /*******************************************************************************
AnnaBridge 143:86740a56073b 302 * Definitions
AnnaBridge 143:86740a56073b 303 ******************************************************************************/
AnnaBridge 143:86740a56073b 304
AnnaBridge 143:86740a56073b 305 /*!
AnnaBridge 143:86740a56073b 306 * @brief Structure for the DMA hardware request
AnnaBridge 143:86740a56073b 307 *
AnnaBridge 143:86740a56073b 308 * Defines the structure for the DMA hardware request collections. The user can configure the
AnnaBridge 143:86740a56073b 309 * hardware request into DMAMUX to trigger the DMA transfer accordingly. The index
AnnaBridge 143:86740a56073b 310 * of the hardware request varies according to the to SoC.
AnnaBridge 143:86740a56073b 311 */
AnnaBridge 143:86740a56073b 312 typedef enum _dma_request_source
AnnaBridge 143:86740a56073b 313 {
AnnaBridge 143:86740a56073b 314 kDmaRequestMux0Disable = 0|0x100U, /**< DMAMUX TriggerDisabled. */
AnnaBridge 143:86740a56073b 315 kDmaRequestMux0Reserved1 = 1|0x100U, /**< Reserved1 */
AnnaBridge 143:86740a56073b 316 kDmaRequestMux0UART0Rx = 2|0x100U, /**< UART0 Receive. */
AnnaBridge 143:86740a56073b 317 kDmaRequestMux0UART0Tx = 3|0x100U, /**< UART0 Transmit. */
AnnaBridge 143:86740a56073b 318 kDmaRequestMux0UART1Rx = 4|0x100U, /**< UART1 Receive. */
AnnaBridge 143:86740a56073b 319 kDmaRequestMux0UART1Tx = 5|0x100U, /**< UART1 Transmit. */
AnnaBridge 143:86740a56073b 320 kDmaRequestMux0UART2Rx = 6|0x100U, /**< UART2 Receive. */
AnnaBridge 143:86740a56073b 321 kDmaRequestMux0UART2Tx = 7|0x100U, /**< UART2 Transmit. */
AnnaBridge 143:86740a56073b 322 kDmaRequestMux0UART3Rx = 8|0x100U, /**< UART3 Receive. */
AnnaBridge 143:86740a56073b 323 kDmaRequestMux0UART3Tx = 9|0x100U, /**< UART3 Transmit. */
AnnaBridge 143:86740a56073b 324 kDmaRequestMux0UART4 = 10|0x100U, /**< UART4 Transmit or Receive. */
AnnaBridge 143:86740a56073b 325 kDmaRequestMux0UART5 = 11|0x100U, /**< UART5 Transmit or Receive. */
AnnaBridge 143:86740a56073b 326 kDmaRequestMux0I2S0Rx = 12|0x100U, /**< I2S0 Receive. */
AnnaBridge 143:86740a56073b 327 kDmaRequestMux0I2S0Tx = 13|0x100U, /**< I2S0 Transmit. */
AnnaBridge 143:86740a56073b 328 kDmaRequestMux0SPI0Rx = 14|0x100U, /**< SPI0 Receive. */
AnnaBridge 143:86740a56073b 329 kDmaRequestMux0SPI0Tx = 15|0x100U, /**< SPI0 Transmit. */
AnnaBridge 143:86740a56073b 330 kDmaRequestMux0SPI1 = 16|0x100U, /**< SPI1 Transmit or Receive. */
AnnaBridge 143:86740a56073b 331 kDmaRequestMux0SPI2 = 17|0x100U, /**< SPI2 Transmit or Receive. */
AnnaBridge 143:86740a56073b 332 kDmaRequestMux0I2C0 = 18|0x100U, /**< I2C0. */
AnnaBridge 143:86740a56073b 333 kDmaRequestMux0I2C1I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 143:86740a56073b 334 kDmaRequestMux0I2C1 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 143:86740a56073b 335 kDmaRequestMux0I2C2 = 19|0x100U, /**< I2C1 and I2C2. */
AnnaBridge 143:86740a56073b 336 kDmaRequestMux0FTM0Channel0 = 20|0x100U, /**< FTM0 C0V. */
AnnaBridge 143:86740a56073b 337 kDmaRequestMux0FTM0Channel1 = 21|0x100U, /**< FTM0 C1V. */
AnnaBridge 143:86740a56073b 338 kDmaRequestMux0FTM0Channel2 = 22|0x100U, /**< FTM0 C2V. */
AnnaBridge 143:86740a56073b 339 kDmaRequestMux0FTM0Channel3 = 23|0x100U, /**< FTM0 C3V. */
AnnaBridge 143:86740a56073b 340 kDmaRequestMux0FTM0Channel4 = 24|0x100U, /**< FTM0 C4V. */
AnnaBridge 143:86740a56073b 341 kDmaRequestMux0FTM0Channel5 = 25|0x100U, /**< FTM0 C5V. */
AnnaBridge 143:86740a56073b 342 kDmaRequestMux0FTM0Channel6 = 26|0x100U, /**< FTM0 C6V. */
AnnaBridge 143:86740a56073b 343 kDmaRequestMux0FTM0Channel7 = 27|0x100U, /**< FTM0 C7V. */
AnnaBridge 143:86740a56073b 344 kDmaRequestMux0FTM1Channel0 = 28|0x100U, /**< FTM1 C0V. */
AnnaBridge 143:86740a56073b 345 kDmaRequestMux0FTM1Channel1 = 29|0x100U, /**< FTM1 C1V. */
AnnaBridge 143:86740a56073b 346 kDmaRequestMux0FTM2Channel0 = 30|0x100U, /**< FTM2 C0V. */
AnnaBridge 143:86740a56073b 347 kDmaRequestMux0FTM2Channel1 = 31|0x100U, /**< FTM2 C1V. */
AnnaBridge 143:86740a56073b 348 kDmaRequestMux0FTM3Channel0 = 32|0x100U, /**< FTM3 C0V. */
AnnaBridge 143:86740a56073b 349 kDmaRequestMux0FTM3Channel1 = 33|0x100U, /**< FTM3 C1V. */
AnnaBridge 143:86740a56073b 350 kDmaRequestMux0FTM3Channel2 = 34|0x100U, /**< FTM3 C2V. */
AnnaBridge 143:86740a56073b 351 kDmaRequestMux0FTM3Channel3 = 35|0x100U, /**< FTM3 C3V. */
AnnaBridge 143:86740a56073b 352 kDmaRequestMux0FTM3Channel4 = 36|0x100U, /**< FTM3 C4V. */
AnnaBridge 143:86740a56073b 353 kDmaRequestMux0FTM3Channel5 = 37|0x100U, /**< FTM3 C5V. */
AnnaBridge 143:86740a56073b 354 kDmaRequestMux0FTM3Channel6 = 38|0x100U, /**< FTM3 C6V. */
AnnaBridge 143:86740a56073b 355 kDmaRequestMux0FTM3Channel7 = 39|0x100U, /**< FTM3 C7V. */
AnnaBridge 143:86740a56073b 356 kDmaRequestMux0ADC0 = 40|0x100U, /**< ADC0. */
AnnaBridge 143:86740a56073b 357 kDmaRequestMux0ADC1 = 41|0x100U, /**< ADC1. */
AnnaBridge 143:86740a56073b 358 kDmaRequestMux0CMP0 = 42|0x100U, /**< CMP0. */
AnnaBridge 143:86740a56073b 359 kDmaRequestMux0CMP1 = 43|0x100U, /**< CMP1. */
AnnaBridge 143:86740a56073b 360 kDmaRequestMux0CMP2 = 44|0x100U, /**< CMP2. */
AnnaBridge 143:86740a56073b 361 kDmaRequestMux0DAC0 = 45|0x100U, /**< DAC0. */
AnnaBridge 143:86740a56073b 362 kDmaRequestMux0DAC1 = 46|0x100U, /**< DAC1. */
AnnaBridge 143:86740a56073b 363 kDmaRequestMux0CMT = 47|0x100U, /**< CMT. */
AnnaBridge 143:86740a56073b 364 kDmaRequestMux0PDB = 48|0x100U, /**< PDB0. */
AnnaBridge 143:86740a56073b 365 kDmaRequestMux0PortA = 49|0x100U, /**< PTA. */
AnnaBridge 143:86740a56073b 366 kDmaRequestMux0PortB = 50|0x100U, /**< PTB. */
AnnaBridge 143:86740a56073b 367 kDmaRequestMux0PortC = 51|0x100U, /**< PTC. */
AnnaBridge 143:86740a56073b 368 kDmaRequestMux0PortD = 52|0x100U, /**< PTD. */
AnnaBridge 143:86740a56073b 369 kDmaRequestMux0PortE = 53|0x100U, /**< PTE. */
AnnaBridge 143:86740a56073b 370 kDmaRequestMux0Reserved54 = 54|0x100U, /**< Reserved54 */
AnnaBridge 143:86740a56073b 371 kDmaRequestMux0Reserved55 = 55|0x100U, /**< Reserved55 */
AnnaBridge 143:86740a56073b 372 kDmaRequestMux0Reserved56 = 56|0x100U, /**< Reserved56 */
AnnaBridge 143:86740a56073b 373 kDmaRequestMux0Reserved57 = 57|0x100U, /**< Reserved57 */
AnnaBridge 143:86740a56073b 374 kDmaRequestMux0AlwaysOn58 = 58|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 143:86740a56073b 375 kDmaRequestMux0AlwaysOn59 = 59|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 143:86740a56073b 376 kDmaRequestMux0AlwaysOn60 = 60|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 143:86740a56073b 377 kDmaRequestMux0AlwaysOn61 = 61|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 143:86740a56073b 378 kDmaRequestMux0AlwaysOn62 = 62|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 143:86740a56073b 379 kDmaRequestMux0AlwaysOn63 = 63|0x100U, /**< DMAMUX Always Enabled slot. */
AnnaBridge 143:86740a56073b 380 } dma_request_source_t;
AnnaBridge 143:86740a56073b 381
AnnaBridge 143:86740a56073b 382 /* @} */
AnnaBridge 143:86740a56073b 383
AnnaBridge 143:86740a56073b 384
AnnaBridge 143:86740a56073b 385 /*!
AnnaBridge 143:86740a56073b 386 * @}
AnnaBridge 143:86740a56073b 387 */ /* end of group Mapping_Information */
AnnaBridge 143:86740a56073b 388
AnnaBridge 143:86740a56073b 389
AnnaBridge 143:86740a56073b 390 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 391 -- Device Peripheral Access Layer
AnnaBridge 143:86740a56073b 392 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 393
AnnaBridge 143:86740a56073b 394 /*!
AnnaBridge 143:86740a56073b 395 * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
AnnaBridge 143:86740a56073b 396 * @{
AnnaBridge 143:86740a56073b 397 */
AnnaBridge 143:86740a56073b 398
AnnaBridge 143:86740a56073b 399
AnnaBridge 143:86740a56073b 400 /*
AnnaBridge 143:86740a56073b 401 ** Start of section using anonymous unions
AnnaBridge 143:86740a56073b 402 */
AnnaBridge 143:86740a56073b 403
AnnaBridge 143:86740a56073b 404 #if defined(__ARMCC_VERSION)
AnnaBridge 143:86740a56073b 405 #pragma push
AnnaBridge 143:86740a56073b 406 #pragma anon_unions
AnnaBridge 143:86740a56073b 407 #elif defined(__CWCC__)
AnnaBridge 143:86740a56073b 408 #pragma push
AnnaBridge 143:86740a56073b 409 #pragma cpp_extensions on
AnnaBridge 143:86740a56073b 410 #elif defined(__GNUC__)
AnnaBridge 143:86740a56073b 411 /* anonymous unions are enabled by default */
AnnaBridge 143:86740a56073b 412 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 143:86740a56073b 413 #pragma language=extended
AnnaBridge 143:86740a56073b 414 #else
AnnaBridge 143:86740a56073b 415 #error Not supported compiler type
AnnaBridge 143:86740a56073b 416 #endif
AnnaBridge 143:86740a56073b 417
AnnaBridge 143:86740a56073b 418 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 419 -- ADC Peripheral Access Layer
AnnaBridge 143:86740a56073b 420 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 421
AnnaBridge 143:86740a56073b 422 /*!
AnnaBridge 143:86740a56073b 423 * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
AnnaBridge 143:86740a56073b 424 * @{
AnnaBridge 143:86740a56073b 425 */
AnnaBridge 143:86740a56073b 426
AnnaBridge 143:86740a56073b 427 /** ADC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 428 typedef struct {
AnnaBridge 143:86740a56073b 429 __IO uint32_t SC1[2]; /**< ADC Status and Control Registers 1, array offset: 0x0, array step: 0x4 */
AnnaBridge 143:86740a56073b 430 __IO uint32_t CFG1; /**< ADC Configuration Register 1, offset: 0x8 */
AnnaBridge 143:86740a56073b 431 __IO uint32_t CFG2; /**< ADC Configuration Register 2, offset: 0xC */
AnnaBridge 143:86740a56073b 432 __I uint32_t R[2]; /**< ADC Data Result Register, array offset: 0x10, array step: 0x4 */
AnnaBridge 143:86740a56073b 433 __IO uint32_t CV1; /**< Compare Value Registers, offset: 0x18 */
AnnaBridge 143:86740a56073b 434 __IO uint32_t CV2; /**< Compare Value Registers, offset: 0x1C */
AnnaBridge 143:86740a56073b 435 __IO uint32_t SC2; /**< Status and Control Register 2, offset: 0x20 */
AnnaBridge 143:86740a56073b 436 __IO uint32_t SC3; /**< Status and Control Register 3, offset: 0x24 */
AnnaBridge 143:86740a56073b 437 __IO uint32_t OFS; /**< ADC Offset Correction Register, offset: 0x28 */
AnnaBridge 143:86740a56073b 438 __IO uint32_t PG; /**< ADC Plus-Side Gain Register, offset: 0x2C */
AnnaBridge 143:86740a56073b 439 __IO uint32_t MG; /**< ADC Minus-Side Gain Register, offset: 0x30 */
AnnaBridge 143:86740a56073b 440 __IO uint32_t CLPD; /**< ADC Plus-Side General Calibration Value Register, offset: 0x34 */
AnnaBridge 143:86740a56073b 441 __IO uint32_t CLPS; /**< ADC Plus-Side General Calibration Value Register, offset: 0x38 */
AnnaBridge 143:86740a56073b 442 __IO uint32_t CLP4; /**< ADC Plus-Side General Calibration Value Register, offset: 0x3C */
AnnaBridge 143:86740a56073b 443 __IO uint32_t CLP3; /**< ADC Plus-Side General Calibration Value Register, offset: 0x40 */
AnnaBridge 143:86740a56073b 444 __IO uint32_t CLP2; /**< ADC Plus-Side General Calibration Value Register, offset: 0x44 */
AnnaBridge 143:86740a56073b 445 __IO uint32_t CLP1; /**< ADC Plus-Side General Calibration Value Register, offset: 0x48 */
AnnaBridge 143:86740a56073b 446 __IO uint32_t CLP0; /**< ADC Plus-Side General Calibration Value Register, offset: 0x4C */
AnnaBridge 143:86740a56073b 447 uint8_t RESERVED_0[4];
AnnaBridge 143:86740a56073b 448 __IO uint32_t CLMD; /**< ADC Minus-Side General Calibration Value Register, offset: 0x54 */
AnnaBridge 143:86740a56073b 449 __IO uint32_t CLMS; /**< ADC Minus-Side General Calibration Value Register, offset: 0x58 */
AnnaBridge 143:86740a56073b 450 __IO uint32_t CLM4; /**< ADC Minus-Side General Calibration Value Register, offset: 0x5C */
AnnaBridge 143:86740a56073b 451 __IO uint32_t CLM3; /**< ADC Minus-Side General Calibration Value Register, offset: 0x60 */
AnnaBridge 143:86740a56073b 452 __IO uint32_t CLM2; /**< ADC Minus-Side General Calibration Value Register, offset: 0x64 */
AnnaBridge 143:86740a56073b 453 __IO uint32_t CLM1; /**< ADC Minus-Side General Calibration Value Register, offset: 0x68 */
AnnaBridge 143:86740a56073b 454 __IO uint32_t CLM0; /**< ADC Minus-Side General Calibration Value Register, offset: 0x6C */
AnnaBridge 143:86740a56073b 455 } ADC_Type;
AnnaBridge 143:86740a56073b 456
AnnaBridge 143:86740a56073b 457 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 458 -- ADC Register Masks
AnnaBridge 143:86740a56073b 459 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 460
AnnaBridge 143:86740a56073b 461 /*!
AnnaBridge 143:86740a56073b 462 * @addtogroup ADC_Register_Masks ADC Register Masks
AnnaBridge 143:86740a56073b 463 * @{
AnnaBridge 143:86740a56073b 464 */
AnnaBridge 143:86740a56073b 465
AnnaBridge 143:86740a56073b 466 /*! @name SC1 - ADC Status and Control Registers 1 */
AnnaBridge 143:86740a56073b 467 #define ADC_SC1_ADCH_MASK (0x1FU)
AnnaBridge 143:86740a56073b 468 #define ADC_SC1_ADCH_SHIFT (0U)
AnnaBridge 143:86740a56073b 469 #define ADC_SC1_ADCH(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_ADCH_SHIFT)) & ADC_SC1_ADCH_MASK)
AnnaBridge 143:86740a56073b 470 #define ADC_SC1_DIFF_MASK (0x20U)
AnnaBridge 143:86740a56073b 471 #define ADC_SC1_DIFF_SHIFT (5U)
AnnaBridge 143:86740a56073b 472 #define ADC_SC1_DIFF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_DIFF_SHIFT)) & ADC_SC1_DIFF_MASK)
AnnaBridge 143:86740a56073b 473 #define ADC_SC1_AIEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 474 #define ADC_SC1_AIEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 475 #define ADC_SC1_AIEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_AIEN_SHIFT)) & ADC_SC1_AIEN_MASK)
AnnaBridge 143:86740a56073b 476 #define ADC_SC1_COCO_MASK (0x80U)
AnnaBridge 143:86740a56073b 477 #define ADC_SC1_COCO_SHIFT (7U)
AnnaBridge 143:86740a56073b 478 #define ADC_SC1_COCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC1_COCO_SHIFT)) & ADC_SC1_COCO_MASK)
AnnaBridge 143:86740a56073b 479
AnnaBridge 143:86740a56073b 480 /* The count of ADC_SC1 */
AnnaBridge 143:86740a56073b 481 #define ADC_SC1_COUNT (2U)
AnnaBridge 143:86740a56073b 482
AnnaBridge 143:86740a56073b 483 /*! @name CFG1 - ADC Configuration Register 1 */
AnnaBridge 143:86740a56073b 484 #define ADC_CFG1_ADICLK_MASK (0x3U)
AnnaBridge 143:86740a56073b 485 #define ADC_CFG1_ADICLK_SHIFT (0U)
AnnaBridge 143:86740a56073b 486 #define ADC_CFG1_ADICLK(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADICLK_SHIFT)) & ADC_CFG1_ADICLK_MASK)
AnnaBridge 143:86740a56073b 487 #define ADC_CFG1_MODE_MASK (0xCU)
AnnaBridge 143:86740a56073b 488 #define ADC_CFG1_MODE_SHIFT (2U)
AnnaBridge 143:86740a56073b 489 #define ADC_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_MODE_SHIFT)) & ADC_CFG1_MODE_MASK)
AnnaBridge 143:86740a56073b 490 #define ADC_CFG1_ADLSMP_MASK (0x10U)
AnnaBridge 143:86740a56073b 491 #define ADC_CFG1_ADLSMP_SHIFT (4U)
AnnaBridge 143:86740a56073b 492 #define ADC_CFG1_ADLSMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLSMP_SHIFT)) & ADC_CFG1_ADLSMP_MASK)
AnnaBridge 143:86740a56073b 493 #define ADC_CFG1_ADIV_MASK (0x60U)
AnnaBridge 143:86740a56073b 494 #define ADC_CFG1_ADIV_SHIFT (5U)
AnnaBridge 143:86740a56073b 495 #define ADC_CFG1_ADIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADIV_SHIFT)) & ADC_CFG1_ADIV_MASK)
AnnaBridge 143:86740a56073b 496 #define ADC_CFG1_ADLPC_MASK (0x80U)
AnnaBridge 143:86740a56073b 497 #define ADC_CFG1_ADLPC_SHIFT (7U)
AnnaBridge 143:86740a56073b 498 #define ADC_CFG1_ADLPC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG1_ADLPC_SHIFT)) & ADC_CFG1_ADLPC_MASK)
AnnaBridge 143:86740a56073b 499
AnnaBridge 143:86740a56073b 500 /*! @name CFG2 - ADC Configuration Register 2 */
AnnaBridge 143:86740a56073b 501 #define ADC_CFG2_ADLSTS_MASK (0x3U)
AnnaBridge 143:86740a56073b 502 #define ADC_CFG2_ADLSTS_SHIFT (0U)
AnnaBridge 143:86740a56073b 503 #define ADC_CFG2_ADLSTS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADLSTS_SHIFT)) & ADC_CFG2_ADLSTS_MASK)
AnnaBridge 143:86740a56073b 504 #define ADC_CFG2_ADHSC_MASK (0x4U)
AnnaBridge 143:86740a56073b 505 #define ADC_CFG2_ADHSC_SHIFT (2U)
AnnaBridge 143:86740a56073b 506 #define ADC_CFG2_ADHSC(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADHSC_SHIFT)) & ADC_CFG2_ADHSC_MASK)
AnnaBridge 143:86740a56073b 507 #define ADC_CFG2_ADACKEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 508 #define ADC_CFG2_ADACKEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 509 #define ADC_CFG2_ADACKEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_ADACKEN_SHIFT)) & ADC_CFG2_ADACKEN_MASK)
AnnaBridge 143:86740a56073b 510 #define ADC_CFG2_MUXSEL_MASK (0x10U)
AnnaBridge 143:86740a56073b 511 #define ADC_CFG2_MUXSEL_SHIFT (4U)
AnnaBridge 143:86740a56073b 512 #define ADC_CFG2_MUXSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CFG2_MUXSEL_SHIFT)) & ADC_CFG2_MUXSEL_MASK)
AnnaBridge 143:86740a56073b 513
AnnaBridge 143:86740a56073b 514 /*! @name R - ADC Data Result Register */
AnnaBridge 143:86740a56073b 515 #define ADC_R_D_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 516 #define ADC_R_D_SHIFT (0U)
AnnaBridge 143:86740a56073b 517 #define ADC_R_D(x) (((uint32_t)(((uint32_t)(x)) << ADC_R_D_SHIFT)) & ADC_R_D_MASK)
AnnaBridge 143:86740a56073b 518
AnnaBridge 143:86740a56073b 519 /* The count of ADC_R */
AnnaBridge 143:86740a56073b 520 #define ADC_R_COUNT (2U)
AnnaBridge 143:86740a56073b 521
AnnaBridge 143:86740a56073b 522 /*! @name CV1 - Compare Value Registers */
AnnaBridge 143:86740a56073b 523 #define ADC_CV1_CV_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 524 #define ADC_CV1_CV_SHIFT (0U)
AnnaBridge 143:86740a56073b 525 #define ADC_CV1_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV1_CV_SHIFT)) & ADC_CV1_CV_MASK)
AnnaBridge 143:86740a56073b 526
AnnaBridge 143:86740a56073b 527 /*! @name CV2 - Compare Value Registers */
AnnaBridge 143:86740a56073b 528 #define ADC_CV2_CV_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 529 #define ADC_CV2_CV_SHIFT (0U)
AnnaBridge 143:86740a56073b 530 #define ADC_CV2_CV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CV2_CV_SHIFT)) & ADC_CV2_CV_MASK)
AnnaBridge 143:86740a56073b 531
AnnaBridge 143:86740a56073b 532 /*! @name SC2 - Status and Control Register 2 */
AnnaBridge 143:86740a56073b 533 #define ADC_SC2_REFSEL_MASK (0x3U)
AnnaBridge 143:86740a56073b 534 #define ADC_SC2_REFSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 535 #define ADC_SC2_REFSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_REFSEL_SHIFT)) & ADC_SC2_REFSEL_MASK)
AnnaBridge 143:86740a56073b 536 #define ADC_SC2_DMAEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 537 #define ADC_SC2_DMAEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 538 #define ADC_SC2_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_DMAEN_SHIFT)) & ADC_SC2_DMAEN_MASK)
AnnaBridge 143:86740a56073b 539 #define ADC_SC2_ACREN_MASK (0x8U)
AnnaBridge 143:86740a56073b 540 #define ADC_SC2_ACREN_SHIFT (3U)
AnnaBridge 143:86740a56073b 541 #define ADC_SC2_ACREN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACREN_SHIFT)) & ADC_SC2_ACREN_MASK)
AnnaBridge 143:86740a56073b 542 #define ADC_SC2_ACFGT_MASK (0x10U)
AnnaBridge 143:86740a56073b 543 #define ADC_SC2_ACFGT_SHIFT (4U)
AnnaBridge 143:86740a56073b 544 #define ADC_SC2_ACFGT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFGT_SHIFT)) & ADC_SC2_ACFGT_MASK)
AnnaBridge 143:86740a56073b 545 #define ADC_SC2_ACFE_MASK (0x20U)
AnnaBridge 143:86740a56073b 546 #define ADC_SC2_ACFE_SHIFT (5U)
AnnaBridge 143:86740a56073b 547 #define ADC_SC2_ACFE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ACFE_SHIFT)) & ADC_SC2_ACFE_MASK)
AnnaBridge 143:86740a56073b 548 #define ADC_SC2_ADTRG_MASK (0x40U)
AnnaBridge 143:86740a56073b 549 #define ADC_SC2_ADTRG_SHIFT (6U)
AnnaBridge 143:86740a56073b 550 #define ADC_SC2_ADTRG(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADTRG_SHIFT)) & ADC_SC2_ADTRG_MASK)
AnnaBridge 143:86740a56073b 551 #define ADC_SC2_ADACT_MASK (0x80U)
AnnaBridge 143:86740a56073b 552 #define ADC_SC2_ADACT_SHIFT (7U)
AnnaBridge 143:86740a56073b 553 #define ADC_SC2_ADACT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC2_ADACT_SHIFT)) & ADC_SC2_ADACT_MASK)
AnnaBridge 143:86740a56073b 554
AnnaBridge 143:86740a56073b 555 /*! @name SC3 - Status and Control Register 3 */
AnnaBridge 143:86740a56073b 556 #define ADC_SC3_AVGS_MASK (0x3U)
AnnaBridge 143:86740a56073b 557 #define ADC_SC3_AVGS_SHIFT (0U)
AnnaBridge 143:86740a56073b 558 #define ADC_SC3_AVGS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGS_SHIFT)) & ADC_SC3_AVGS_MASK)
AnnaBridge 143:86740a56073b 559 #define ADC_SC3_AVGE_MASK (0x4U)
AnnaBridge 143:86740a56073b 560 #define ADC_SC3_AVGE_SHIFT (2U)
AnnaBridge 143:86740a56073b 561 #define ADC_SC3_AVGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_AVGE_SHIFT)) & ADC_SC3_AVGE_MASK)
AnnaBridge 143:86740a56073b 562 #define ADC_SC3_ADCO_MASK (0x8U)
AnnaBridge 143:86740a56073b 563 #define ADC_SC3_ADCO_SHIFT (3U)
AnnaBridge 143:86740a56073b 564 #define ADC_SC3_ADCO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_ADCO_SHIFT)) & ADC_SC3_ADCO_MASK)
AnnaBridge 143:86740a56073b 565 #define ADC_SC3_CALF_MASK (0x40U)
AnnaBridge 143:86740a56073b 566 #define ADC_SC3_CALF_SHIFT (6U)
AnnaBridge 143:86740a56073b 567 #define ADC_SC3_CALF(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CALF_SHIFT)) & ADC_SC3_CALF_MASK)
AnnaBridge 143:86740a56073b 568 #define ADC_SC3_CAL_MASK (0x80U)
AnnaBridge 143:86740a56073b 569 #define ADC_SC3_CAL_SHIFT (7U)
AnnaBridge 143:86740a56073b 570 #define ADC_SC3_CAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SC3_CAL_SHIFT)) & ADC_SC3_CAL_MASK)
AnnaBridge 143:86740a56073b 571
AnnaBridge 143:86740a56073b 572 /*! @name OFS - ADC Offset Correction Register */
AnnaBridge 143:86740a56073b 573 #define ADC_OFS_OFS_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 574 #define ADC_OFS_OFS_SHIFT (0U)
AnnaBridge 143:86740a56073b 575 #define ADC_OFS_OFS(x) (((uint32_t)(((uint32_t)(x)) << ADC_OFS_OFS_SHIFT)) & ADC_OFS_OFS_MASK)
AnnaBridge 143:86740a56073b 576
AnnaBridge 143:86740a56073b 577 /*! @name PG - ADC Plus-Side Gain Register */
AnnaBridge 143:86740a56073b 578 #define ADC_PG_PG_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 579 #define ADC_PG_PG_SHIFT (0U)
AnnaBridge 143:86740a56073b 580 #define ADC_PG_PG(x) (((uint32_t)(((uint32_t)(x)) << ADC_PG_PG_SHIFT)) & ADC_PG_PG_MASK)
AnnaBridge 143:86740a56073b 581
AnnaBridge 143:86740a56073b 582 /*! @name MG - ADC Minus-Side Gain Register */
AnnaBridge 143:86740a56073b 583 #define ADC_MG_MG_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 584 #define ADC_MG_MG_SHIFT (0U)
AnnaBridge 143:86740a56073b 585 #define ADC_MG_MG(x) (((uint32_t)(((uint32_t)(x)) << ADC_MG_MG_SHIFT)) & ADC_MG_MG_MASK)
AnnaBridge 143:86740a56073b 586
AnnaBridge 143:86740a56073b 587 /*! @name CLPD - ADC Plus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 588 #define ADC_CLPD_CLPD_MASK (0x3FU)
AnnaBridge 143:86740a56073b 589 #define ADC_CLPD_CLPD_SHIFT (0U)
AnnaBridge 143:86740a56073b 590 #define ADC_CLPD_CLPD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPD_CLPD_SHIFT)) & ADC_CLPD_CLPD_MASK)
AnnaBridge 143:86740a56073b 591
AnnaBridge 143:86740a56073b 592 /*! @name CLPS - ADC Plus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 593 #define ADC_CLPS_CLPS_MASK (0x3FU)
AnnaBridge 143:86740a56073b 594 #define ADC_CLPS_CLPS_SHIFT (0U)
AnnaBridge 143:86740a56073b 595 #define ADC_CLPS_CLPS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLPS_CLPS_SHIFT)) & ADC_CLPS_CLPS_MASK)
AnnaBridge 143:86740a56073b 596
AnnaBridge 143:86740a56073b 597 /*! @name CLP4 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 598 #define ADC_CLP4_CLP4_MASK (0x3FFU)
AnnaBridge 143:86740a56073b 599 #define ADC_CLP4_CLP4_SHIFT (0U)
AnnaBridge 143:86740a56073b 600 #define ADC_CLP4_CLP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP4_CLP4_SHIFT)) & ADC_CLP4_CLP4_MASK)
AnnaBridge 143:86740a56073b 601
AnnaBridge 143:86740a56073b 602 /*! @name CLP3 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 603 #define ADC_CLP3_CLP3_MASK (0x1FFU)
AnnaBridge 143:86740a56073b 604 #define ADC_CLP3_CLP3_SHIFT (0U)
AnnaBridge 143:86740a56073b 605 #define ADC_CLP3_CLP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP3_CLP3_SHIFT)) & ADC_CLP3_CLP3_MASK)
AnnaBridge 143:86740a56073b 606
AnnaBridge 143:86740a56073b 607 /*! @name CLP2 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 608 #define ADC_CLP2_CLP2_MASK (0xFFU)
AnnaBridge 143:86740a56073b 609 #define ADC_CLP2_CLP2_SHIFT (0U)
AnnaBridge 143:86740a56073b 610 #define ADC_CLP2_CLP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP2_CLP2_SHIFT)) & ADC_CLP2_CLP2_MASK)
AnnaBridge 143:86740a56073b 611
AnnaBridge 143:86740a56073b 612 /*! @name CLP1 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 613 #define ADC_CLP1_CLP1_MASK (0x7FU)
AnnaBridge 143:86740a56073b 614 #define ADC_CLP1_CLP1_SHIFT (0U)
AnnaBridge 143:86740a56073b 615 #define ADC_CLP1_CLP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP1_CLP1_SHIFT)) & ADC_CLP1_CLP1_MASK)
AnnaBridge 143:86740a56073b 616
AnnaBridge 143:86740a56073b 617 /*! @name CLP0 - ADC Plus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 618 #define ADC_CLP0_CLP0_MASK (0x3FU)
AnnaBridge 143:86740a56073b 619 #define ADC_CLP0_CLP0_SHIFT (0U)
AnnaBridge 143:86740a56073b 620 #define ADC_CLP0_CLP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLP0_CLP0_SHIFT)) & ADC_CLP0_CLP0_MASK)
AnnaBridge 143:86740a56073b 621
AnnaBridge 143:86740a56073b 622 /*! @name CLMD - ADC Minus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 623 #define ADC_CLMD_CLMD_MASK (0x3FU)
AnnaBridge 143:86740a56073b 624 #define ADC_CLMD_CLMD_SHIFT (0U)
AnnaBridge 143:86740a56073b 625 #define ADC_CLMD_CLMD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMD_CLMD_SHIFT)) & ADC_CLMD_CLMD_MASK)
AnnaBridge 143:86740a56073b 626
AnnaBridge 143:86740a56073b 627 /*! @name CLMS - ADC Minus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 628 #define ADC_CLMS_CLMS_MASK (0x3FU)
AnnaBridge 143:86740a56073b 629 #define ADC_CLMS_CLMS_SHIFT (0U)
AnnaBridge 143:86740a56073b 630 #define ADC_CLMS_CLMS(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLMS_CLMS_SHIFT)) & ADC_CLMS_CLMS_MASK)
AnnaBridge 143:86740a56073b 631
AnnaBridge 143:86740a56073b 632 /*! @name CLM4 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 633 #define ADC_CLM4_CLM4_MASK (0x3FFU)
AnnaBridge 143:86740a56073b 634 #define ADC_CLM4_CLM4_SHIFT (0U)
AnnaBridge 143:86740a56073b 635 #define ADC_CLM4_CLM4(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM4_CLM4_SHIFT)) & ADC_CLM4_CLM4_MASK)
AnnaBridge 143:86740a56073b 636
AnnaBridge 143:86740a56073b 637 /*! @name CLM3 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 638 #define ADC_CLM3_CLM3_MASK (0x1FFU)
AnnaBridge 143:86740a56073b 639 #define ADC_CLM3_CLM3_SHIFT (0U)
AnnaBridge 143:86740a56073b 640 #define ADC_CLM3_CLM3(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM3_CLM3_SHIFT)) & ADC_CLM3_CLM3_MASK)
AnnaBridge 143:86740a56073b 641
AnnaBridge 143:86740a56073b 642 /*! @name CLM2 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 643 #define ADC_CLM2_CLM2_MASK (0xFFU)
AnnaBridge 143:86740a56073b 644 #define ADC_CLM2_CLM2_SHIFT (0U)
AnnaBridge 143:86740a56073b 645 #define ADC_CLM2_CLM2(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM2_CLM2_SHIFT)) & ADC_CLM2_CLM2_MASK)
AnnaBridge 143:86740a56073b 646
AnnaBridge 143:86740a56073b 647 /*! @name CLM1 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 648 #define ADC_CLM1_CLM1_MASK (0x7FU)
AnnaBridge 143:86740a56073b 649 #define ADC_CLM1_CLM1_SHIFT (0U)
AnnaBridge 143:86740a56073b 650 #define ADC_CLM1_CLM1(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM1_CLM1_SHIFT)) & ADC_CLM1_CLM1_MASK)
AnnaBridge 143:86740a56073b 651
AnnaBridge 143:86740a56073b 652 /*! @name CLM0 - ADC Minus-Side General Calibration Value Register */
AnnaBridge 143:86740a56073b 653 #define ADC_CLM0_CLM0_MASK (0x3FU)
AnnaBridge 143:86740a56073b 654 #define ADC_CLM0_CLM0_SHIFT (0U)
AnnaBridge 143:86740a56073b 655 #define ADC_CLM0_CLM0(x) (((uint32_t)(((uint32_t)(x)) << ADC_CLM0_CLM0_SHIFT)) & ADC_CLM0_CLM0_MASK)
AnnaBridge 143:86740a56073b 656
AnnaBridge 143:86740a56073b 657
AnnaBridge 143:86740a56073b 658 /*!
AnnaBridge 143:86740a56073b 659 * @}
AnnaBridge 143:86740a56073b 660 */ /* end of group ADC_Register_Masks */
AnnaBridge 143:86740a56073b 661
AnnaBridge 143:86740a56073b 662
AnnaBridge 143:86740a56073b 663 /* ADC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 664 /** Peripheral ADC0 base address */
AnnaBridge 143:86740a56073b 665 #define ADC0_BASE (0x4003B000u)
AnnaBridge 143:86740a56073b 666 /** Peripheral ADC0 base pointer */
AnnaBridge 143:86740a56073b 667 #define ADC0 ((ADC_Type *)ADC0_BASE)
AnnaBridge 143:86740a56073b 668 /** Peripheral ADC1 base address */
AnnaBridge 143:86740a56073b 669 #define ADC1_BASE (0x400BB000u)
AnnaBridge 143:86740a56073b 670 /** Peripheral ADC1 base pointer */
AnnaBridge 143:86740a56073b 671 #define ADC1 ((ADC_Type *)ADC1_BASE)
AnnaBridge 143:86740a56073b 672 /** Array initializer of ADC peripheral base addresses */
AnnaBridge 143:86740a56073b 673 #define ADC_BASE_ADDRS { ADC0_BASE, ADC1_BASE }
AnnaBridge 143:86740a56073b 674 /** Array initializer of ADC peripheral base pointers */
AnnaBridge 143:86740a56073b 675 #define ADC_BASE_PTRS { ADC0, ADC1 }
AnnaBridge 143:86740a56073b 676 /** Interrupt vectors for the ADC peripheral type */
AnnaBridge 143:86740a56073b 677 #define ADC_IRQS { ADC0_IRQn, ADC1_IRQn }
AnnaBridge 143:86740a56073b 678
AnnaBridge 143:86740a56073b 679 /*!
AnnaBridge 143:86740a56073b 680 * @}
AnnaBridge 143:86740a56073b 681 */ /* end of group ADC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 682
AnnaBridge 143:86740a56073b 683
AnnaBridge 143:86740a56073b 684 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 685 -- AIPS Peripheral Access Layer
AnnaBridge 143:86740a56073b 686 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 687
AnnaBridge 143:86740a56073b 688 /*!
AnnaBridge 143:86740a56073b 689 * @addtogroup AIPS_Peripheral_Access_Layer AIPS Peripheral Access Layer
AnnaBridge 143:86740a56073b 690 * @{
AnnaBridge 143:86740a56073b 691 */
AnnaBridge 143:86740a56073b 692
AnnaBridge 143:86740a56073b 693 /** AIPS - Register Layout Typedef */
AnnaBridge 143:86740a56073b 694 typedef struct {
AnnaBridge 143:86740a56073b 695 __IO uint32_t MPRA; /**< Master Privilege Register A, offset: 0x0 */
AnnaBridge 143:86740a56073b 696 uint8_t RESERVED_0[28];
AnnaBridge 143:86740a56073b 697 __IO uint32_t PACRA; /**< Peripheral Access Control Register, offset: 0x20 */
AnnaBridge 143:86740a56073b 698 __IO uint32_t PACRB; /**< Peripheral Access Control Register, offset: 0x24 */
AnnaBridge 143:86740a56073b 699 __IO uint32_t PACRC; /**< Peripheral Access Control Register, offset: 0x28 */
AnnaBridge 143:86740a56073b 700 __IO uint32_t PACRD; /**< Peripheral Access Control Register, offset: 0x2C */
AnnaBridge 143:86740a56073b 701 uint8_t RESERVED_1[16];
AnnaBridge 143:86740a56073b 702 __IO uint32_t PACRE; /**< Peripheral Access Control Register, offset: 0x40 */
AnnaBridge 143:86740a56073b 703 __IO uint32_t PACRF; /**< Peripheral Access Control Register, offset: 0x44 */
AnnaBridge 143:86740a56073b 704 __IO uint32_t PACRG; /**< Peripheral Access Control Register, offset: 0x48 */
AnnaBridge 143:86740a56073b 705 __IO uint32_t PACRH; /**< Peripheral Access Control Register, offset: 0x4C */
AnnaBridge 143:86740a56073b 706 __IO uint32_t PACRI; /**< Peripheral Access Control Register, offset: 0x50 */
AnnaBridge 143:86740a56073b 707 __IO uint32_t PACRJ; /**< Peripheral Access Control Register, offset: 0x54 */
AnnaBridge 143:86740a56073b 708 __IO uint32_t PACRK; /**< Peripheral Access Control Register, offset: 0x58 */
AnnaBridge 143:86740a56073b 709 __IO uint32_t PACRL; /**< Peripheral Access Control Register, offset: 0x5C */
AnnaBridge 143:86740a56073b 710 __IO uint32_t PACRM; /**< Peripheral Access Control Register, offset: 0x60 */
AnnaBridge 143:86740a56073b 711 __IO uint32_t PACRN; /**< Peripheral Access Control Register, offset: 0x64 */
AnnaBridge 143:86740a56073b 712 __IO uint32_t PACRO; /**< Peripheral Access Control Register, offset: 0x68 */
AnnaBridge 143:86740a56073b 713 __IO uint32_t PACRP; /**< Peripheral Access Control Register, offset: 0x6C */
AnnaBridge 143:86740a56073b 714 uint8_t RESERVED_2[16];
AnnaBridge 143:86740a56073b 715 __IO uint32_t PACRU; /**< Peripheral Access Control Register, offset: 0x80 */
AnnaBridge 143:86740a56073b 716 } AIPS_Type;
AnnaBridge 143:86740a56073b 717
AnnaBridge 143:86740a56073b 718 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 719 -- AIPS Register Masks
AnnaBridge 143:86740a56073b 720 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 721
AnnaBridge 143:86740a56073b 722 /*!
AnnaBridge 143:86740a56073b 723 * @addtogroup AIPS_Register_Masks AIPS Register Masks
AnnaBridge 143:86740a56073b 724 * @{
AnnaBridge 143:86740a56073b 725 */
AnnaBridge 143:86740a56073b 726
AnnaBridge 143:86740a56073b 727 /*! @name MPRA - Master Privilege Register A */
AnnaBridge 143:86740a56073b 728 #define AIPS_MPRA_MPL5_MASK (0x100U)
AnnaBridge 143:86740a56073b 729 #define AIPS_MPRA_MPL5_SHIFT (8U)
AnnaBridge 143:86740a56073b 730 #define AIPS_MPRA_MPL5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL5_SHIFT)) & AIPS_MPRA_MPL5_MASK)
AnnaBridge 143:86740a56073b 731 #define AIPS_MPRA_MTW5_MASK (0x200U)
AnnaBridge 143:86740a56073b 732 #define AIPS_MPRA_MTW5_SHIFT (9U)
AnnaBridge 143:86740a56073b 733 #define AIPS_MPRA_MTW5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW5_SHIFT)) & AIPS_MPRA_MTW5_MASK)
AnnaBridge 143:86740a56073b 734 #define AIPS_MPRA_MTR5_MASK (0x400U)
AnnaBridge 143:86740a56073b 735 #define AIPS_MPRA_MTR5_SHIFT (10U)
AnnaBridge 143:86740a56073b 736 #define AIPS_MPRA_MTR5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR5_SHIFT)) & AIPS_MPRA_MTR5_MASK)
AnnaBridge 143:86740a56073b 737 #define AIPS_MPRA_MPL4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 738 #define AIPS_MPRA_MPL4_SHIFT (12U)
AnnaBridge 143:86740a56073b 739 #define AIPS_MPRA_MPL4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL4_SHIFT)) & AIPS_MPRA_MPL4_MASK)
AnnaBridge 143:86740a56073b 740 #define AIPS_MPRA_MTW4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 741 #define AIPS_MPRA_MTW4_SHIFT (13U)
AnnaBridge 143:86740a56073b 742 #define AIPS_MPRA_MTW4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW4_SHIFT)) & AIPS_MPRA_MTW4_MASK)
AnnaBridge 143:86740a56073b 743 #define AIPS_MPRA_MTR4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 744 #define AIPS_MPRA_MTR4_SHIFT (14U)
AnnaBridge 143:86740a56073b 745 #define AIPS_MPRA_MTR4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR4_SHIFT)) & AIPS_MPRA_MTR4_MASK)
AnnaBridge 143:86740a56073b 746 #define AIPS_MPRA_MPL3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 747 #define AIPS_MPRA_MPL3_SHIFT (16U)
AnnaBridge 143:86740a56073b 748 #define AIPS_MPRA_MPL3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL3_SHIFT)) & AIPS_MPRA_MPL3_MASK)
AnnaBridge 143:86740a56073b 749 #define AIPS_MPRA_MTW3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 750 #define AIPS_MPRA_MTW3_SHIFT (17U)
AnnaBridge 143:86740a56073b 751 #define AIPS_MPRA_MTW3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW3_SHIFT)) & AIPS_MPRA_MTW3_MASK)
AnnaBridge 143:86740a56073b 752 #define AIPS_MPRA_MTR3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 753 #define AIPS_MPRA_MTR3_SHIFT (18U)
AnnaBridge 143:86740a56073b 754 #define AIPS_MPRA_MTR3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR3_SHIFT)) & AIPS_MPRA_MTR3_MASK)
AnnaBridge 143:86740a56073b 755 #define AIPS_MPRA_MPL2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 756 #define AIPS_MPRA_MPL2_SHIFT (20U)
AnnaBridge 143:86740a56073b 757 #define AIPS_MPRA_MPL2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL2_SHIFT)) & AIPS_MPRA_MPL2_MASK)
AnnaBridge 143:86740a56073b 758 #define AIPS_MPRA_MTW2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 759 #define AIPS_MPRA_MTW2_SHIFT (21U)
AnnaBridge 143:86740a56073b 760 #define AIPS_MPRA_MTW2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW2_SHIFT)) & AIPS_MPRA_MTW2_MASK)
AnnaBridge 143:86740a56073b 761 #define AIPS_MPRA_MTR2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 762 #define AIPS_MPRA_MTR2_SHIFT (22U)
AnnaBridge 143:86740a56073b 763 #define AIPS_MPRA_MTR2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR2_SHIFT)) & AIPS_MPRA_MTR2_MASK)
AnnaBridge 143:86740a56073b 764 #define AIPS_MPRA_MPL1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 765 #define AIPS_MPRA_MPL1_SHIFT (24U)
AnnaBridge 143:86740a56073b 766 #define AIPS_MPRA_MPL1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL1_SHIFT)) & AIPS_MPRA_MPL1_MASK)
AnnaBridge 143:86740a56073b 767 #define AIPS_MPRA_MTW1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 768 #define AIPS_MPRA_MTW1_SHIFT (25U)
AnnaBridge 143:86740a56073b 769 #define AIPS_MPRA_MTW1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW1_SHIFT)) & AIPS_MPRA_MTW1_MASK)
AnnaBridge 143:86740a56073b 770 #define AIPS_MPRA_MTR1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 771 #define AIPS_MPRA_MTR1_SHIFT (26U)
AnnaBridge 143:86740a56073b 772 #define AIPS_MPRA_MTR1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR1_SHIFT)) & AIPS_MPRA_MTR1_MASK)
AnnaBridge 143:86740a56073b 773 #define AIPS_MPRA_MPL0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 774 #define AIPS_MPRA_MPL0_SHIFT (28U)
AnnaBridge 143:86740a56073b 775 #define AIPS_MPRA_MPL0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MPL0_SHIFT)) & AIPS_MPRA_MPL0_MASK)
AnnaBridge 143:86740a56073b 776 #define AIPS_MPRA_MTW0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 777 #define AIPS_MPRA_MTW0_SHIFT (29U)
AnnaBridge 143:86740a56073b 778 #define AIPS_MPRA_MTW0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTW0_SHIFT)) & AIPS_MPRA_MTW0_MASK)
AnnaBridge 143:86740a56073b 779 #define AIPS_MPRA_MTR0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 780 #define AIPS_MPRA_MTR0_SHIFT (30U)
AnnaBridge 143:86740a56073b 781 #define AIPS_MPRA_MTR0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_MPRA_MTR0_SHIFT)) & AIPS_MPRA_MTR0_MASK)
AnnaBridge 143:86740a56073b 782
AnnaBridge 143:86740a56073b 783 /*! @name PACRA - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 784 #define AIPS_PACRA_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 785 #define AIPS_PACRA_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 786 #define AIPS_PACRA_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP7_SHIFT)) & AIPS_PACRA_TP7_MASK)
AnnaBridge 143:86740a56073b 787 #define AIPS_PACRA_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 788 #define AIPS_PACRA_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 789 #define AIPS_PACRA_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP7_SHIFT)) & AIPS_PACRA_WP7_MASK)
AnnaBridge 143:86740a56073b 790 #define AIPS_PACRA_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 791 #define AIPS_PACRA_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 792 #define AIPS_PACRA_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP7_SHIFT)) & AIPS_PACRA_SP7_MASK)
AnnaBridge 143:86740a56073b 793 #define AIPS_PACRA_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 794 #define AIPS_PACRA_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 795 #define AIPS_PACRA_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP6_SHIFT)) & AIPS_PACRA_TP6_MASK)
AnnaBridge 143:86740a56073b 796 #define AIPS_PACRA_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 797 #define AIPS_PACRA_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 798 #define AIPS_PACRA_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP6_SHIFT)) & AIPS_PACRA_WP6_MASK)
AnnaBridge 143:86740a56073b 799 #define AIPS_PACRA_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 800 #define AIPS_PACRA_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 801 #define AIPS_PACRA_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP6_SHIFT)) & AIPS_PACRA_SP6_MASK)
AnnaBridge 143:86740a56073b 802 #define AIPS_PACRA_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 803 #define AIPS_PACRA_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 804 #define AIPS_PACRA_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP5_SHIFT)) & AIPS_PACRA_TP5_MASK)
AnnaBridge 143:86740a56073b 805 #define AIPS_PACRA_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 806 #define AIPS_PACRA_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 807 #define AIPS_PACRA_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP5_SHIFT)) & AIPS_PACRA_WP5_MASK)
AnnaBridge 143:86740a56073b 808 #define AIPS_PACRA_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 809 #define AIPS_PACRA_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 810 #define AIPS_PACRA_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP5_SHIFT)) & AIPS_PACRA_SP5_MASK)
AnnaBridge 143:86740a56073b 811 #define AIPS_PACRA_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 812 #define AIPS_PACRA_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 813 #define AIPS_PACRA_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP4_SHIFT)) & AIPS_PACRA_TP4_MASK)
AnnaBridge 143:86740a56073b 814 #define AIPS_PACRA_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 815 #define AIPS_PACRA_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 816 #define AIPS_PACRA_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP4_SHIFT)) & AIPS_PACRA_WP4_MASK)
AnnaBridge 143:86740a56073b 817 #define AIPS_PACRA_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 818 #define AIPS_PACRA_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 819 #define AIPS_PACRA_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP4_SHIFT)) & AIPS_PACRA_SP4_MASK)
AnnaBridge 143:86740a56073b 820 #define AIPS_PACRA_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 821 #define AIPS_PACRA_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 822 #define AIPS_PACRA_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP3_SHIFT)) & AIPS_PACRA_TP3_MASK)
AnnaBridge 143:86740a56073b 823 #define AIPS_PACRA_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 824 #define AIPS_PACRA_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 825 #define AIPS_PACRA_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP3_SHIFT)) & AIPS_PACRA_WP3_MASK)
AnnaBridge 143:86740a56073b 826 #define AIPS_PACRA_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 827 #define AIPS_PACRA_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 828 #define AIPS_PACRA_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP3_SHIFT)) & AIPS_PACRA_SP3_MASK)
AnnaBridge 143:86740a56073b 829 #define AIPS_PACRA_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 830 #define AIPS_PACRA_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 831 #define AIPS_PACRA_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP2_SHIFT)) & AIPS_PACRA_TP2_MASK)
AnnaBridge 143:86740a56073b 832 #define AIPS_PACRA_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 833 #define AIPS_PACRA_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 834 #define AIPS_PACRA_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP2_SHIFT)) & AIPS_PACRA_WP2_MASK)
AnnaBridge 143:86740a56073b 835 #define AIPS_PACRA_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 836 #define AIPS_PACRA_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 837 #define AIPS_PACRA_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP2_SHIFT)) & AIPS_PACRA_SP2_MASK)
AnnaBridge 143:86740a56073b 838 #define AIPS_PACRA_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 839 #define AIPS_PACRA_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 840 #define AIPS_PACRA_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP1_SHIFT)) & AIPS_PACRA_TP1_MASK)
AnnaBridge 143:86740a56073b 841 #define AIPS_PACRA_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 842 #define AIPS_PACRA_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 843 #define AIPS_PACRA_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP1_SHIFT)) & AIPS_PACRA_WP1_MASK)
AnnaBridge 143:86740a56073b 844 #define AIPS_PACRA_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 845 #define AIPS_PACRA_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 846 #define AIPS_PACRA_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP1_SHIFT)) & AIPS_PACRA_SP1_MASK)
AnnaBridge 143:86740a56073b 847 #define AIPS_PACRA_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 848 #define AIPS_PACRA_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 849 #define AIPS_PACRA_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_TP0_SHIFT)) & AIPS_PACRA_TP0_MASK)
AnnaBridge 143:86740a56073b 850 #define AIPS_PACRA_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 851 #define AIPS_PACRA_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 852 #define AIPS_PACRA_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_WP0_SHIFT)) & AIPS_PACRA_WP0_MASK)
AnnaBridge 143:86740a56073b 853 #define AIPS_PACRA_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 854 #define AIPS_PACRA_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 855 #define AIPS_PACRA_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRA_SP0_SHIFT)) & AIPS_PACRA_SP0_MASK)
AnnaBridge 143:86740a56073b 856
AnnaBridge 143:86740a56073b 857 /*! @name PACRB - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 858 #define AIPS_PACRB_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 859 #define AIPS_PACRB_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 860 #define AIPS_PACRB_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP7_SHIFT)) & AIPS_PACRB_TP7_MASK)
AnnaBridge 143:86740a56073b 861 #define AIPS_PACRB_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 862 #define AIPS_PACRB_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 863 #define AIPS_PACRB_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP7_SHIFT)) & AIPS_PACRB_WP7_MASK)
AnnaBridge 143:86740a56073b 864 #define AIPS_PACRB_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 865 #define AIPS_PACRB_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 866 #define AIPS_PACRB_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP7_SHIFT)) & AIPS_PACRB_SP7_MASK)
AnnaBridge 143:86740a56073b 867 #define AIPS_PACRB_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 868 #define AIPS_PACRB_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 869 #define AIPS_PACRB_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP6_SHIFT)) & AIPS_PACRB_TP6_MASK)
AnnaBridge 143:86740a56073b 870 #define AIPS_PACRB_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 871 #define AIPS_PACRB_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 872 #define AIPS_PACRB_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP6_SHIFT)) & AIPS_PACRB_WP6_MASK)
AnnaBridge 143:86740a56073b 873 #define AIPS_PACRB_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 874 #define AIPS_PACRB_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 875 #define AIPS_PACRB_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP6_SHIFT)) & AIPS_PACRB_SP6_MASK)
AnnaBridge 143:86740a56073b 876 #define AIPS_PACRB_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 877 #define AIPS_PACRB_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 878 #define AIPS_PACRB_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP5_SHIFT)) & AIPS_PACRB_TP5_MASK)
AnnaBridge 143:86740a56073b 879 #define AIPS_PACRB_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 880 #define AIPS_PACRB_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 881 #define AIPS_PACRB_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP5_SHIFT)) & AIPS_PACRB_WP5_MASK)
AnnaBridge 143:86740a56073b 882 #define AIPS_PACRB_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 883 #define AIPS_PACRB_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 884 #define AIPS_PACRB_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP5_SHIFT)) & AIPS_PACRB_SP5_MASK)
AnnaBridge 143:86740a56073b 885 #define AIPS_PACRB_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 886 #define AIPS_PACRB_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 887 #define AIPS_PACRB_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP4_SHIFT)) & AIPS_PACRB_TP4_MASK)
AnnaBridge 143:86740a56073b 888 #define AIPS_PACRB_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 889 #define AIPS_PACRB_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 890 #define AIPS_PACRB_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP4_SHIFT)) & AIPS_PACRB_WP4_MASK)
AnnaBridge 143:86740a56073b 891 #define AIPS_PACRB_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 892 #define AIPS_PACRB_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 893 #define AIPS_PACRB_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP4_SHIFT)) & AIPS_PACRB_SP4_MASK)
AnnaBridge 143:86740a56073b 894 #define AIPS_PACRB_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 895 #define AIPS_PACRB_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 896 #define AIPS_PACRB_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP3_SHIFT)) & AIPS_PACRB_TP3_MASK)
AnnaBridge 143:86740a56073b 897 #define AIPS_PACRB_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 898 #define AIPS_PACRB_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 899 #define AIPS_PACRB_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP3_SHIFT)) & AIPS_PACRB_WP3_MASK)
AnnaBridge 143:86740a56073b 900 #define AIPS_PACRB_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 901 #define AIPS_PACRB_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 902 #define AIPS_PACRB_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP3_SHIFT)) & AIPS_PACRB_SP3_MASK)
AnnaBridge 143:86740a56073b 903 #define AIPS_PACRB_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 904 #define AIPS_PACRB_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 905 #define AIPS_PACRB_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP2_SHIFT)) & AIPS_PACRB_TP2_MASK)
AnnaBridge 143:86740a56073b 906 #define AIPS_PACRB_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 907 #define AIPS_PACRB_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 908 #define AIPS_PACRB_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP2_SHIFT)) & AIPS_PACRB_WP2_MASK)
AnnaBridge 143:86740a56073b 909 #define AIPS_PACRB_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 910 #define AIPS_PACRB_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 911 #define AIPS_PACRB_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP2_SHIFT)) & AIPS_PACRB_SP2_MASK)
AnnaBridge 143:86740a56073b 912 #define AIPS_PACRB_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 913 #define AIPS_PACRB_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 914 #define AIPS_PACRB_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP1_SHIFT)) & AIPS_PACRB_TP1_MASK)
AnnaBridge 143:86740a56073b 915 #define AIPS_PACRB_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 916 #define AIPS_PACRB_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 917 #define AIPS_PACRB_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP1_SHIFT)) & AIPS_PACRB_WP1_MASK)
AnnaBridge 143:86740a56073b 918 #define AIPS_PACRB_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 919 #define AIPS_PACRB_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 920 #define AIPS_PACRB_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP1_SHIFT)) & AIPS_PACRB_SP1_MASK)
AnnaBridge 143:86740a56073b 921 #define AIPS_PACRB_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 922 #define AIPS_PACRB_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 923 #define AIPS_PACRB_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_TP0_SHIFT)) & AIPS_PACRB_TP0_MASK)
AnnaBridge 143:86740a56073b 924 #define AIPS_PACRB_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 925 #define AIPS_PACRB_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 926 #define AIPS_PACRB_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_WP0_SHIFT)) & AIPS_PACRB_WP0_MASK)
AnnaBridge 143:86740a56073b 927 #define AIPS_PACRB_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 928 #define AIPS_PACRB_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 929 #define AIPS_PACRB_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRB_SP0_SHIFT)) & AIPS_PACRB_SP0_MASK)
AnnaBridge 143:86740a56073b 930
AnnaBridge 143:86740a56073b 931 /*! @name PACRC - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 932 #define AIPS_PACRC_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 933 #define AIPS_PACRC_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 934 #define AIPS_PACRC_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP7_SHIFT)) & AIPS_PACRC_TP7_MASK)
AnnaBridge 143:86740a56073b 935 #define AIPS_PACRC_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 936 #define AIPS_PACRC_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 937 #define AIPS_PACRC_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP7_SHIFT)) & AIPS_PACRC_WP7_MASK)
AnnaBridge 143:86740a56073b 938 #define AIPS_PACRC_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 939 #define AIPS_PACRC_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 940 #define AIPS_PACRC_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP7_SHIFT)) & AIPS_PACRC_SP7_MASK)
AnnaBridge 143:86740a56073b 941 #define AIPS_PACRC_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 942 #define AIPS_PACRC_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 943 #define AIPS_PACRC_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP6_SHIFT)) & AIPS_PACRC_TP6_MASK)
AnnaBridge 143:86740a56073b 944 #define AIPS_PACRC_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 945 #define AIPS_PACRC_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 946 #define AIPS_PACRC_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP6_SHIFT)) & AIPS_PACRC_WP6_MASK)
AnnaBridge 143:86740a56073b 947 #define AIPS_PACRC_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 948 #define AIPS_PACRC_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 949 #define AIPS_PACRC_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP6_SHIFT)) & AIPS_PACRC_SP6_MASK)
AnnaBridge 143:86740a56073b 950 #define AIPS_PACRC_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 951 #define AIPS_PACRC_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 952 #define AIPS_PACRC_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP5_SHIFT)) & AIPS_PACRC_TP5_MASK)
AnnaBridge 143:86740a56073b 953 #define AIPS_PACRC_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 954 #define AIPS_PACRC_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 955 #define AIPS_PACRC_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP5_SHIFT)) & AIPS_PACRC_WP5_MASK)
AnnaBridge 143:86740a56073b 956 #define AIPS_PACRC_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 957 #define AIPS_PACRC_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 958 #define AIPS_PACRC_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP5_SHIFT)) & AIPS_PACRC_SP5_MASK)
AnnaBridge 143:86740a56073b 959 #define AIPS_PACRC_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 960 #define AIPS_PACRC_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 961 #define AIPS_PACRC_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP4_SHIFT)) & AIPS_PACRC_TP4_MASK)
AnnaBridge 143:86740a56073b 962 #define AIPS_PACRC_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 963 #define AIPS_PACRC_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 964 #define AIPS_PACRC_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP4_SHIFT)) & AIPS_PACRC_WP4_MASK)
AnnaBridge 143:86740a56073b 965 #define AIPS_PACRC_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 966 #define AIPS_PACRC_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 967 #define AIPS_PACRC_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP4_SHIFT)) & AIPS_PACRC_SP4_MASK)
AnnaBridge 143:86740a56073b 968 #define AIPS_PACRC_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 969 #define AIPS_PACRC_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 970 #define AIPS_PACRC_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP3_SHIFT)) & AIPS_PACRC_TP3_MASK)
AnnaBridge 143:86740a56073b 971 #define AIPS_PACRC_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 972 #define AIPS_PACRC_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 973 #define AIPS_PACRC_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP3_SHIFT)) & AIPS_PACRC_WP3_MASK)
AnnaBridge 143:86740a56073b 974 #define AIPS_PACRC_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 975 #define AIPS_PACRC_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 976 #define AIPS_PACRC_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP3_SHIFT)) & AIPS_PACRC_SP3_MASK)
AnnaBridge 143:86740a56073b 977 #define AIPS_PACRC_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 978 #define AIPS_PACRC_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 979 #define AIPS_PACRC_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP2_SHIFT)) & AIPS_PACRC_TP2_MASK)
AnnaBridge 143:86740a56073b 980 #define AIPS_PACRC_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 981 #define AIPS_PACRC_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 982 #define AIPS_PACRC_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP2_SHIFT)) & AIPS_PACRC_WP2_MASK)
AnnaBridge 143:86740a56073b 983 #define AIPS_PACRC_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 984 #define AIPS_PACRC_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 985 #define AIPS_PACRC_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP2_SHIFT)) & AIPS_PACRC_SP2_MASK)
AnnaBridge 143:86740a56073b 986 #define AIPS_PACRC_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 987 #define AIPS_PACRC_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 988 #define AIPS_PACRC_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP1_SHIFT)) & AIPS_PACRC_TP1_MASK)
AnnaBridge 143:86740a56073b 989 #define AIPS_PACRC_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 990 #define AIPS_PACRC_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 991 #define AIPS_PACRC_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP1_SHIFT)) & AIPS_PACRC_WP1_MASK)
AnnaBridge 143:86740a56073b 992 #define AIPS_PACRC_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 993 #define AIPS_PACRC_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 994 #define AIPS_PACRC_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP1_SHIFT)) & AIPS_PACRC_SP1_MASK)
AnnaBridge 143:86740a56073b 995 #define AIPS_PACRC_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 996 #define AIPS_PACRC_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 997 #define AIPS_PACRC_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_TP0_SHIFT)) & AIPS_PACRC_TP0_MASK)
AnnaBridge 143:86740a56073b 998 #define AIPS_PACRC_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 999 #define AIPS_PACRC_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1000 #define AIPS_PACRC_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_WP0_SHIFT)) & AIPS_PACRC_WP0_MASK)
AnnaBridge 143:86740a56073b 1001 #define AIPS_PACRC_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1002 #define AIPS_PACRC_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1003 #define AIPS_PACRC_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRC_SP0_SHIFT)) & AIPS_PACRC_SP0_MASK)
AnnaBridge 143:86740a56073b 1004
AnnaBridge 143:86740a56073b 1005 /*! @name PACRD - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1006 #define AIPS_PACRD_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1007 #define AIPS_PACRD_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1008 #define AIPS_PACRD_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP7_SHIFT)) & AIPS_PACRD_TP7_MASK)
AnnaBridge 143:86740a56073b 1009 #define AIPS_PACRD_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1010 #define AIPS_PACRD_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1011 #define AIPS_PACRD_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP7_SHIFT)) & AIPS_PACRD_WP7_MASK)
AnnaBridge 143:86740a56073b 1012 #define AIPS_PACRD_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1013 #define AIPS_PACRD_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1014 #define AIPS_PACRD_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP7_SHIFT)) & AIPS_PACRD_SP7_MASK)
AnnaBridge 143:86740a56073b 1015 #define AIPS_PACRD_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1016 #define AIPS_PACRD_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1017 #define AIPS_PACRD_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP6_SHIFT)) & AIPS_PACRD_TP6_MASK)
AnnaBridge 143:86740a56073b 1018 #define AIPS_PACRD_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1019 #define AIPS_PACRD_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1020 #define AIPS_PACRD_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP6_SHIFT)) & AIPS_PACRD_WP6_MASK)
AnnaBridge 143:86740a56073b 1021 #define AIPS_PACRD_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1022 #define AIPS_PACRD_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1023 #define AIPS_PACRD_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP6_SHIFT)) & AIPS_PACRD_SP6_MASK)
AnnaBridge 143:86740a56073b 1024 #define AIPS_PACRD_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1025 #define AIPS_PACRD_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1026 #define AIPS_PACRD_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP5_SHIFT)) & AIPS_PACRD_TP5_MASK)
AnnaBridge 143:86740a56073b 1027 #define AIPS_PACRD_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1028 #define AIPS_PACRD_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1029 #define AIPS_PACRD_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP5_SHIFT)) & AIPS_PACRD_WP5_MASK)
AnnaBridge 143:86740a56073b 1030 #define AIPS_PACRD_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1031 #define AIPS_PACRD_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1032 #define AIPS_PACRD_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP5_SHIFT)) & AIPS_PACRD_SP5_MASK)
AnnaBridge 143:86740a56073b 1033 #define AIPS_PACRD_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1034 #define AIPS_PACRD_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1035 #define AIPS_PACRD_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP4_SHIFT)) & AIPS_PACRD_TP4_MASK)
AnnaBridge 143:86740a56073b 1036 #define AIPS_PACRD_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1037 #define AIPS_PACRD_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1038 #define AIPS_PACRD_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP4_SHIFT)) & AIPS_PACRD_WP4_MASK)
AnnaBridge 143:86740a56073b 1039 #define AIPS_PACRD_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1040 #define AIPS_PACRD_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1041 #define AIPS_PACRD_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP4_SHIFT)) & AIPS_PACRD_SP4_MASK)
AnnaBridge 143:86740a56073b 1042 #define AIPS_PACRD_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1043 #define AIPS_PACRD_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1044 #define AIPS_PACRD_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP3_SHIFT)) & AIPS_PACRD_TP3_MASK)
AnnaBridge 143:86740a56073b 1045 #define AIPS_PACRD_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1046 #define AIPS_PACRD_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1047 #define AIPS_PACRD_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP3_SHIFT)) & AIPS_PACRD_WP3_MASK)
AnnaBridge 143:86740a56073b 1048 #define AIPS_PACRD_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1049 #define AIPS_PACRD_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1050 #define AIPS_PACRD_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP3_SHIFT)) & AIPS_PACRD_SP3_MASK)
AnnaBridge 143:86740a56073b 1051 #define AIPS_PACRD_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1052 #define AIPS_PACRD_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1053 #define AIPS_PACRD_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP2_SHIFT)) & AIPS_PACRD_TP2_MASK)
AnnaBridge 143:86740a56073b 1054 #define AIPS_PACRD_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1055 #define AIPS_PACRD_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1056 #define AIPS_PACRD_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP2_SHIFT)) & AIPS_PACRD_WP2_MASK)
AnnaBridge 143:86740a56073b 1057 #define AIPS_PACRD_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1058 #define AIPS_PACRD_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1059 #define AIPS_PACRD_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP2_SHIFT)) & AIPS_PACRD_SP2_MASK)
AnnaBridge 143:86740a56073b 1060 #define AIPS_PACRD_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1061 #define AIPS_PACRD_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1062 #define AIPS_PACRD_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP1_SHIFT)) & AIPS_PACRD_TP1_MASK)
AnnaBridge 143:86740a56073b 1063 #define AIPS_PACRD_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1064 #define AIPS_PACRD_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1065 #define AIPS_PACRD_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP1_SHIFT)) & AIPS_PACRD_WP1_MASK)
AnnaBridge 143:86740a56073b 1066 #define AIPS_PACRD_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1067 #define AIPS_PACRD_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1068 #define AIPS_PACRD_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP1_SHIFT)) & AIPS_PACRD_SP1_MASK)
AnnaBridge 143:86740a56073b 1069 #define AIPS_PACRD_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1070 #define AIPS_PACRD_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1071 #define AIPS_PACRD_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_TP0_SHIFT)) & AIPS_PACRD_TP0_MASK)
AnnaBridge 143:86740a56073b 1072 #define AIPS_PACRD_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1073 #define AIPS_PACRD_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1074 #define AIPS_PACRD_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_WP0_SHIFT)) & AIPS_PACRD_WP0_MASK)
AnnaBridge 143:86740a56073b 1075 #define AIPS_PACRD_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1076 #define AIPS_PACRD_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1077 #define AIPS_PACRD_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRD_SP0_SHIFT)) & AIPS_PACRD_SP0_MASK)
AnnaBridge 143:86740a56073b 1078
AnnaBridge 143:86740a56073b 1079 /*! @name PACRE - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1080 #define AIPS_PACRE_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1081 #define AIPS_PACRE_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1082 #define AIPS_PACRE_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP7_SHIFT)) & AIPS_PACRE_TP7_MASK)
AnnaBridge 143:86740a56073b 1083 #define AIPS_PACRE_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1084 #define AIPS_PACRE_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1085 #define AIPS_PACRE_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP7_SHIFT)) & AIPS_PACRE_WP7_MASK)
AnnaBridge 143:86740a56073b 1086 #define AIPS_PACRE_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1087 #define AIPS_PACRE_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1088 #define AIPS_PACRE_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP7_SHIFT)) & AIPS_PACRE_SP7_MASK)
AnnaBridge 143:86740a56073b 1089 #define AIPS_PACRE_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1090 #define AIPS_PACRE_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1091 #define AIPS_PACRE_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP6_SHIFT)) & AIPS_PACRE_TP6_MASK)
AnnaBridge 143:86740a56073b 1092 #define AIPS_PACRE_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1093 #define AIPS_PACRE_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1094 #define AIPS_PACRE_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP6_SHIFT)) & AIPS_PACRE_WP6_MASK)
AnnaBridge 143:86740a56073b 1095 #define AIPS_PACRE_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1096 #define AIPS_PACRE_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1097 #define AIPS_PACRE_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP6_SHIFT)) & AIPS_PACRE_SP6_MASK)
AnnaBridge 143:86740a56073b 1098 #define AIPS_PACRE_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1099 #define AIPS_PACRE_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1100 #define AIPS_PACRE_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP5_SHIFT)) & AIPS_PACRE_TP5_MASK)
AnnaBridge 143:86740a56073b 1101 #define AIPS_PACRE_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1102 #define AIPS_PACRE_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1103 #define AIPS_PACRE_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP5_SHIFT)) & AIPS_PACRE_WP5_MASK)
AnnaBridge 143:86740a56073b 1104 #define AIPS_PACRE_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1105 #define AIPS_PACRE_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1106 #define AIPS_PACRE_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP5_SHIFT)) & AIPS_PACRE_SP5_MASK)
AnnaBridge 143:86740a56073b 1107 #define AIPS_PACRE_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1108 #define AIPS_PACRE_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1109 #define AIPS_PACRE_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP4_SHIFT)) & AIPS_PACRE_TP4_MASK)
AnnaBridge 143:86740a56073b 1110 #define AIPS_PACRE_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1111 #define AIPS_PACRE_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1112 #define AIPS_PACRE_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP4_SHIFT)) & AIPS_PACRE_WP4_MASK)
AnnaBridge 143:86740a56073b 1113 #define AIPS_PACRE_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1114 #define AIPS_PACRE_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1115 #define AIPS_PACRE_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP4_SHIFT)) & AIPS_PACRE_SP4_MASK)
AnnaBridge 143:86740a56073b 1116 #define AIPS_PACRE_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1117 #define AIPS_PACRE_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1118 #define AIPS_PACRE_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP3_SHIFT)) & AIPS_PACRE_TP3_MASK)
AnnaBridge 143:86740a56073b 1119 #define AIPS_PACRE_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1120 #define AIPS_PACRE_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1121 #define AIPS_PACRE_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP3_SHIFT)) & AIPS_PACRE_WP3_MASK)
AnnaBridge 143:86740a56073b 1122 #define AIPS_PACRE_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1123 #define AIPS_PACRE_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1124 #define AIPS_PACRE_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP3_SHIFT)) & AIPS_PACRE_SP3_MASK)
AnnaBridge 143:86740a56073b 1125 #define AIPS_PACRE_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1126 #define AIPS_PACRE_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1127 #define AIPS_PACRE_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP2_SHIFT)) & AIPS_PACRE_TP2_MASK)
AnnaBridge 143:86740a56073b 1128 #define AIPS_PACRE_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1129 #define AIPS_PACRE_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1130 #define AIPS_PACRE_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP2_SHIFT)) & AIPS_PACRE_WP2_MASK)
AnnaBridge 143:86740a56073b 1131 #define AIPS_PACRE_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1132 #define AIPS_PACRE_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1133 #define AIPS_PACRE_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP2_SHIFT)) & AIPS_PACRE_SP2_MASK)
AnnaBridge 143:86740a56073b 1134 #define AIPS_PACRE_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1135 #define AIPS_PACRE_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1136 #define AIPS_PACRE_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP1_SHIFT)) & AIPS_PACRE_TP1_MASK)
AnnaBridge 143:86740a56073b 1137 #define AIPS_PACRE_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1138 #define AIPS_PACRE_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1139 #define AIPS_PACRE_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP1_SHIFT)) & AIPS_PACRE_WP1_MASK)
AnnaBridge 143:86740a56073b 1140 #define AIPS_PACRE_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1141 #define AIPS_PACRE_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1142 #define AIPS_PACRE_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP1_SHIFT)) & AIPS_PACRE_SP1_MASK)
AnnaBridge 143:86740a56073b 1143 #define AIPS_PACRE_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1144 #define AIPS_PACRE_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1145 #define AIPS_PACRE_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_TP0_SHIFT)) & AIPS_PACRE_TP0_MASK)
AnnaBridge 143:86740a56073b 1146 #define AIPS_PACRE_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1147 #define AIPS_PACRE_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1148 #define AIPS_PACRE_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_WP0_SHIFT)) & AIPS_PACRE_WP0_MASK)
AnnaBridge 143:86740a56073b 1149 #define AIPS_PACRE_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1150 #define AIPS_PACRE_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1151 #define AIPS_PACRE_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRE_SP0_SHIFT)) & AIPS_PACRE_SP0_MASK)
AnnaBridge 143:86740a56073b 1152
AnnaBridge 143:86740a56073b 1153 /*! @name PACRF - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1154 #define AIPS_PACRF_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1155 #define AIPS_PACRF_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1156 #define AIPS_PACRF_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP7_SHIFT)) & AIPS_PACRF_TP7_MASK)
AnnaBridge 143:86740a56073b 1157 #define AIPS_PACRF_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1158 #define AIPS_PACRF_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1159 #define AIPS_PACRF_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP7_SHIFT)) & AIPS_PACRF_WP7_MASK)
AnnaBridge 143:86740a56073b 1160 #define AIPS_PACRF_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1161 #define AIPS_PACRF_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1162 #define AIPS_PACRF_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP7_SHIFT)) & AIPS_PACRF_SP7_MASK)
AnnaBridge 143:86740a56073b 1163 #define AIPS_PACRF_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1164 #define AIPS_PACRF_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1165 #define AIPS_PACRF_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP6_SHIFT)) & AIPS_PACRF_TP6_MASK)
AnnaBridge 143:86740a56073b 1166 #define AIPS_PACRF_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1167 #define AIPS_PACRF_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1168 #define AIPS_PACRF_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP6_SHIFT)) & AIPS_PACRF_WP6_MASK)
AnnaBridge 143:86740a56073b 1169 #define AIPS_PACRF_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1170 #define AIPS_PACRF_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1171 #define AIPS_PACRF_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP6_SHIFT)) & AIPS_PACRF_SP6_MASK)
AnnaBridge 143:86740a56073b 1172 #define AIPS_PACRF_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1173 #define AIPS_PACRF_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1174 #define AIPS_PACRF_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP5_SHIFT)) & AIPS_PACRF_TP5_MASK)
AnnaBridge 143:86740a56073b 1175 #define AIPS_PACRF_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1176 #define AIPS_PACRF_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1177 #define AIPS_PACRF_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP5_SHIFT)) & AIPS_PACRF_WP5_MASK)
AnnaBridge 143:86740a56073b 1178 #define AIPS_PACRF_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1179 #define AIPS_PACRF_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1180 #define AIPS_PACRF_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP5_SHIFT)) & AIPS_PACRF_SP5_MASK)
AnnaBridge 143:86740a56073b 1181 #define AIPS_PACRF_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1182 #define AIPS_PACRF_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1183 #define AIPS_PACRF_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP4_SHIFT)) & AIPS_PACRF_TP4_MASK)
AnnaBridge 143:86740a56073b 1184 #define AIPS_PACRF_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1185 #define AIPS_PACRF_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1186 #define AIPS_PACRF_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP4_SHIFT)) & AIPS_PACRF_WP4_MASK)
AnnaBridge 143:86740a56073b 1187 #define AIPS_PACRF_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1188 #define AIPS_PACRF_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1189 #define AIPS_PACRF_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP4_SHIFT)) & AIPS_PACRF_SP4_MASK)
AnnaBridge 143:86740a56073b 1190 #define AIPS_PACRF_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1191 #define AIPS_PACRF_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1192 #define AIPS_PACRF_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP3_SHIFT)) & AIPS_PACRF_TP3_MASK)
AnnaBridge 143:86740a56073b 1193 #define AIPS_PACRF_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1194 #define AIPS_PACRF_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1195 #define AIPS_PACRF_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP3_SHIFT)) & AIPS_PACRF_WP3_MASK)
AnnaBridge 143:86740a56073b 1196 #define AIPS_PACRF_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1197 #define AIPS_PACRF_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1198 #define AIPS_PACRF_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP3_SHIFT)) & AIPS_PACRF_SP3_MASK)
AnnaBridge 143:86740a56073b 1199 #define AIPS_PACRF_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1200 #define AIPS_PACRF_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1201 #define AIPS_PACRF_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP2_SHIFT)) & AIPS_PACRF_TP2_MASK)
AnnaBridge 143:86740a56073b 1202 #define AIPS_PACRF_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1203 #define AIPS_PACRF_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1204 #define AIPS_PACRF_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP2_SHIFT)) & AIPS_PACRF_WP2_MASK)
AnnaBridge 143:86740a56073b 1205 #define AIPS_PACRF_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1206 #define AIPS_PACRF_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1207 #define AIPS_PACRF_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP2_SHIFT)) & AIPS_PACRF_SP2_MASK)
AnnaBridge 143:86740a56073b 1208 #define AIPS_PACRF_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1209 #define AIPS_PACRF_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1210 #define AIPS_PACRF_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP1_SHIFT)) & AIPS_PACRF_TP1_MASK)
AnnaBridge 143:86740a56073b 1211 #define AIPS_PACRF_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1212 #define AIPS_PACRF_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1213 #define AIPS_PACRF_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP1_SHIFT)) & AIPS_PACRF_WP1_MASK)
AnnaBridge 143:86740a56073b 1214 #define AIPS_PACRF_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1215 #define AIPS_PACRF_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1216 #define AIPS_PACRF_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP1_SHIFT)) & AIPS_PACRF_SP1_MASK)
AnnaBridge 143:86740a56073b 1217 #define AIPS_PACRF_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1218 #define AIPS_PACRF_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1219 #define AIPS_PACRF_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_TP0_SHIFT)) & AIPS_PACRF_TP0_MASK)
AnnaBridge 143:86740a56073b 1220 #define AIPS_PACRF_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1221 #define AIPS_PACRF_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1222 #define AIPS_PACRF_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_WP0_SHIFT)) & AIPS_PACRF_WP0_MASK)
AnnaBridge 143:86740a56073b 1223 #define AIPS_PACRF_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1224 #define AIPS_PACRF_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1225 #define AIPS_PACRF_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRF_SP0_SHIFT)) & AIPS_PACRF_SP0_MASK)
AnnaBridge 143:86740a56073b 1226
AnnaBridge 143:86740a56073b 1227 /*! @name PACRG - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1228 #define AIPS_PACRG_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1229 #define AIPS_PACRG_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1230 #define AIPS_PACRG_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP7_SHIFT)) & AIPS_PACRG_TP7_MASK)
AnnaBridge 143:86740a56073b 1231 #define AIPS_PACRG_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1232 #define AIPS_PACRG_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1233 #define AIPS_PACRG_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP7_SHIFT)) & AIPS_PACRG_WP7_MASK)
AnnaBridge 143:86740a56073b 1234 #define AIPS_PACRG_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1235 #define AIPS_PACRG_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1236 #define AIPS_PACRG_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP7_SHIFT)) & AIPS_PACRG_SP7_MASK)
AnnaBridge 143:86740a56073b 1237 #define AIPS_PACRG_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1238 #define AIPS_PACRG_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1239 #define AIPS_PACRG_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP6_SHIFT)) & AIPS_PACRG_TP6_MASK)
AnnaBridge 143:86740a56073b 1240 #define AIPS_PACRG_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1241 #define AIPS_PACRG_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1242 #define AIPS_PACRG_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP6_SHIFT)) & AIPS_PACRG_WP6_MASK)
AnnaBridge 143:86740a56073b 1243 #define AIPS_PACRG_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1244 #define AIPS_PACRG_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1245 #define AIPS_PACRG_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP6_SHIFT)) & AIPS_PACRG_SP6_MASK)
AnnaBridge 143:86740a56073b 1246 #define AIPS_PACRG_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1247 #define AIPS_PACRG_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1248 #define AIPS_PACRG_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP5_SHIFT)) & AIPS_PACRG_TP5_MASK)
AnnaBridge 143:86740a56073b 1249 #define AIPS_PACRG_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1250 #define AIPS_PACRG_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1251 #define AIPS_PACRG_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP5_SHIFT)) & AIPS_PACRG_WP5_MASK)
AnnaBridge 143:86740a56073b 1252 #define AIPS_PACRG_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1253 #define AIPS_PACRG_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1254 #define AIPS_PACRG_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP5_SHIFT)) & AIPS_PACRG_SP5_MASK)
AnnaBridge 143:86740a56073b 1255 #define AIPS_PACRG_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1256 #define AIPS_PACRG_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1257 #define AIPS_PACRG_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP4_SHIFT)) & AIPS_PACRG_TP4_MASK)
AnnaBridge 143:86740a56073b 1258 #define AIPS_PACRG_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1259 #define AIPS_PACRG_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1260 #define AIPS_PACRG_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP4_SHIFT)) & AIPS_PACRG_WP4_MASK)
AnnaBridge 143:86740a56073b 1261 #define AIPS_PACRG_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1262 #define AIPS_PACRG_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1263 #define AIPS_PACRG_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP4_SHIFT)) & AIPS_PACRG_SP4_MASK)
AnnaBridge 143:86740a56073b 1264 #define AIPS_PACRG_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1265 #define AIPS_PACRG_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1266 #define AIPS_PACRG_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP3_SHIFT)) & AIPS_PACRG_TP3_MASK)
AnnaBridge 143:86740a56073b 1267 #define AIPS_PACRG_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1268 #define AIPS_PACRG_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1269 #define AIPS_PACRG_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP3_SHIFT)) & AIPS_PACRG_WP3_MASK)
AnnaBridge 143:86740a56073b 1270 #define AIPS_PACRG_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1271 #define AIPS_PACRG_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1272 #define AIPS_PACRG_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP3_SHIFT)) & AIPS_PACRG_SP3_MASK)
AnnaBridge 143:86740a56073b 1273 #define AIPS_PACRG_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1274 #define AIPS_PACRG_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1275 #define AIPS_PACRG_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP2_SHIFT)) & AIPS_PACRG_TP2_MASK)
AnnaBridge 143:86740a56073b 1276 #define AIPS_PACRG_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1277 #define AIPS_PACRG_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1278 #define AIPS_PACRG_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP2_SHIFT)) & AIPS_PACRG_WP2_MASK)
AnnaBridge 143:86740a56073b 1279 #define AIPS_PACRG_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1280 #define AIPS_PACRG_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1281 #define AIPS_PACRG_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP2_SHIFT)) & AIPS_PACRG_SP2_MASK)
AnnaBridge 143:86740a56073b 1282 #define AIPS_PACRG_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1283 #define AIPS_PACRG_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1284 #define AIPS_PACRG_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP1_SHIFT)) & AIPS_PACRG_TP1_MASK)
AnnaBridge 143:86740a56073b 1285 #define AIPS_PACRG_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1286 #define AIPS_PACRG_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1287 #define AIPS_PACRG_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP1_SHIFT)) & AIPS_PACRG_WP1_MASK)
AnnaBridge 143:86740a56073b 1288 #define AIPS_PACRG_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1289 #define AIPS_PACRG_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1290 #define AIPS_PACRG_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP1_SHIFT)) & AIPS_PACRG_SP1_MASK)
AnnaBridge 143:86740a56073b 1291 #define AIPS_PACRG_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1292 #define AIPS_PACRG_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1293 #define AIPS_PACRG_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_TP0_SHIFT)) & AIPS_PACRG_TP0_MASK)
AnnaBridge 143:86740a56073b 1294 #define AIPS_PACRG_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1295 #define AIPS_PACRG_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1296 #define AIPS_PACRG_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_WP0_SHIFT)) & AIPS_PACRG_WP0_MASK)
AnnaBridge 143:86740a56073b 1297 #define AIPS_PACRG_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1298 #define AIPS_PACRG_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1299 #define AIPS_PACRG_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRG_SP0_SHIFT)) & AIPS_PACRG_SP0_MASK)
AnnaBridge 143:86740a56073b 1300
AnnaBridge 143:86740a56073b 1301 /*! @name PACRH - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1302 #define AIPS_PACRH_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1303 #define AIPS_PACRH_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1304 #define AIPS_PACRH_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP7_SHIFT)) & AIPS_PACRH_TP7_MASK)
AnnaBridge 143:86740a56073b 1305 #define AIPS_PACRH_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1306 #define AIPS_PACRH_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1307 #define AIPS_PACRH_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP7_SHIFT)) & AIPS_PACRH_WP7_MASK)
AnnaBridge 143:86740a56073b 1308 #define AIPS_PACRH_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1309 #define AIPS_PACRH_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1310 #define AIPS_PACRH_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP7_SHIFT)) & AIPS_PACRH_SP7_MASK)
AnnaBridge 143:86740a56073b 1311 #define AIPS_PACRH_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1312 #define AIPS_PACRH_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1313 #define AIPS_PACRH_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP6_SHIFT)) & AIPS_PACRH_TP6_MASK)
AnnaBridge 143:86740a56073b 1314 #define AIPS_PACRH_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1315 #define AIPS_PACRH_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1316 #define AIPS_PACRH_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP6_SHIFT)) & AIPS_PACRH_WP6_MASK)
AnnaBridge 143:86740a56073b 1317 #define AIPS_PACRH_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1318 #define AIPS_PACRH_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1319 #define AIPS_PACRH_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP6_SHIFT)) & AIPS_PACRH_SP6_MASK)
AnnaBridge 143:86740a56073b 1320 #define AIPS_PACRH_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1321 #define AIPS_PACRH_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1322 #define AIPS_PACRH_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP5_SHIFT)) & AIPS_PACRH_TP5_MASK)
AnnaBridge 143:86740a56073b 1323 #define AIPS_PACRH_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1324 #define AIPS_PACRH_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1325 #define AIPS_PACRH_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP5_SHIFT)) & AIPS_PACRH_WP5_MASK)
AnnaBridge 143:86740a56073b 1326 #define AIPS_PACRH_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1327 #define AIPS_PACRH_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1328 #define AIPS_PACRH_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP5_SHIFT)) & AIPS_PACRH_SP5_MASK)
AnnaBridge 143:86740a56073b 1329 #define AIPS_PACRH_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1330 #define AIPS_PACRH_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1331 #define AIPS_PACRH_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP4_SHIFT)) & AIPS_PACRH_TP4_MASK)
AnnaBridge 143:86740a56073b 1332 #define AIPS_PACRH_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1333 #define AIPS_PACRH_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1334 #define AIPS_PACRH_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP4_SHIFT)) & AIPS_PACRH_WP4_MASK)
AnnaBridge 143:86740a56073b 1335 #define AIPS_PACRH_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1336 #define AIPS_PACRH_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1337 #define AIPS_PACRH_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP4_SHIFT)) & AIPS_PACRH_SP4_MASK)
AnnaBridge 143:86740a56073b 1338 #define AIPS_PACRH_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1339 #define AIPS_PACRH_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1340 #define AIPS_PACRH_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP3_SHIFT)) & AIPS_PACRH_TP3_MASK)
AnnaBridge 143:86740a56073b 1341 #define AIPS_PACRH_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1342 #define AIPS_PACRH_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1343 #define AIPS_PACRH_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP3_SHIFT)) & AIPS_PACRH_WP3_MASK)
AnnaBridge 143:86740a56073b 1344 #define AIPS_PACRH_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1345 #define AIPS_PACRH_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1346 #define AIPS_PACRH_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP3_SHIFT)) & AIPS_PACRH_SP3_MASK)
AnnaBridge 143:86740a56073b 1347 #define AIPS_PACRH_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1348 #define AIPS_PACRH_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1349 #define AIPS_PACRH_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP2_SHIFT)) & AIPS_PACRH_TP2_MASK)
AnnaBridge 143:86740a56073b 1350 #define AIPS_PACRH_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1351 #define AIPS_PACRH_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1352 #define AIPS_PACRH_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP2_SHIFT)) & AIPS_PACRH_WP2_MASK)
AnnaBridge 143:86740a56073b 1353 #define AIPS_PACRH_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1354 #define AIPS_PACRH_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1355 #define AIPS_PACRH_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP2_SHIFT)) & AIPS_PACRH_SP2_MASK)
AnnaBridge 143:86740a56073b 1356 #define AIPS_PACRH_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1357 #define AIPS_PACRH_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1358 #define AIPS_PACRH_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP1_SHIFT)) & AIPS_PACRH_TP1_MASK)
AnnaBridge 143:86740a56073b 1359 #define AIPS_PACRH_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1360 #define AIPS_PACRH_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1361 #define AIPS_PACRH_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP1_SHIFT)) & AIPS_PACRH_WP1_MASK)
AnnaBridge 143:86740a56073b 1362 #define AIPS_PACRH_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1363 #define AIPS_PACRH_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1364 #define AIPS_PACRH_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP1_SHIFT)) & AIPS_PACRH_SP1_MASK)
AnnaBridge 143:86740a56073b 1365 #define AIPS_PACRH_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1366 #define AIPS_PACRH_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1367 #define AIPS_PACRH_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_TP0_SHIFT)) & AIPS_PACRH_TP0_MASK)
AnnaBridge 143:86740a56073b 1368 #define AIPS_PACRH_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1369 #define AIPS_PACRH_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1370 #define AIPS_PACRH_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_WP0_SHIFT)) & AIPS_PACRH_WP0_MASK)
AnnaBridge 143:86740a56073b 1371 #define AIPS_PACRH_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1372 #define AIPS_PACRH_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1373 #define AIPS_PACRH_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRH_SP0_SHIFT)) & AIPS_PACRH_SP0_MASK)
AnnaBridge 143:86740a56073b 1374
AnnaBridge 143:86740a56073b 1375 /*! @name PACRI - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1376 #define AIPS_PACRI_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1377 #define AIPS_PACRI_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1378 #define AIPS_PACRI_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP7_SHIFT)) & AIPS_PACRI_TP7_MASK)
AnnaBridge 143:86740a56073b 1379 #define AIPS_PACRI_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1380 #define AIPS_PACRI_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1381 #define AIPS_PACRI_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP7_SHIFT)) & AIPS_PACRI_WP7_MASK)
AnnaBridge 143:86740a56073b 1382 #define AIPS_PACRI_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1383 #define AIPS_PACRI_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1384 #define AIPS_PACRI_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP7_SHIFT)) & AIPS_PACRI_SP7_MASK)
AnnaBridge 143:86740a56073b 1385 #define AIPS_PACRI_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1386 #define AIPS_PACRI_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1387 #define AIPS_PACRI_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP6_SHIFT)) & AIPS_PACRI_TP6_MASK)
AnnaBridge 143:86740a56073b 1388 #define AIPS_PACRI_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1389 #define AIPS_PACRI_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1390 #define AIPS_PACRI_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP6_SHIFT)) & AIPS_PACRI_WP6_MASK)
AnnaBridge 143:86740a56073b 1391 #define AIPS_PACRI_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1392 #define AIPS_PACRI_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1393 #define AIPS_PACRI_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP6_SHIFT)) & AIPS_PACRI_SP6_MASK)
AnnaBridge 143:86740a56073b 1394 #define AIPS_PACRI_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1395 #define AIPS_PACRI_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1396 #define AIPS_PACRI_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP5_SHIFT)) & AIPS_PACRI_TP5_MASK)
AnnaBridge 143:86740a56073b 1397 #define AIPS_PACRI_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1398 #define AIPS_PACRI_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1399 #define AIPS_PACRI_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP5_SHIFT)) & AIPS_PACRI_WP5_MASK)
AnnaBridge 143:86740a56073b 1400 #define AIPS_PACRI_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1401 #define AIPS_PACRI_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1402 #define AIPS_PACRI_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP5_SHIFT)) & AIPS_PACRI_SP5_MASK)
AnnaBridge 143:86740a56073b 1403 #define AIPS_PACRI_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1404 #define AIPS_PACRI_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1405 #define AIPS_PACRI_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP4_SHIFT)) & AIPS_PACRI_TP4_MASK)
AnnaBridge 143:86740a56073b 1406 #define AIPS_PACRI_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1407 #define AIPS_PACRI_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1408 #define AIPS_PACRI_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP4_SHIFT)) & AIPS_PACRI_WP4_MASK)
AnnaBridge 143:86740a56073b 1409 #define AIPS_PACRI_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1410 #define AIPS_PACRI_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1411 #define AIPS_PACRI_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP4_SHIFT)) & AIPS_PACRI_SP4_MASK)
AnnaBridge 143:86740a56073b 1412 #define AIPS_PACRI_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1413 #define AIPS_PACRI_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1414 #define AIPS_PACRI_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP3_SHIFT)) & AIPS_PACRI_TP3_MASK)
AnnaBridge 143:86740a56073b 1415 #define AIPS_PACRI_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1416 #define AIPS_PACRI_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1417 #define AIPS_PACRI_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP3_SHIFT)) & AIPS_PACRI_WP3_MASK)
AnnaBridge 143:86740a56073b 1418 #define AIPS_PACRI_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1419 #define AIPS_PACRI_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1420 #define AIPS_PACRI_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP3_SHIFT)) & AIPS_PACRI_SP3_MASK)
AnnaBridge 143:86740a56073b 1421 #define AIPS_PACRI_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1422 #define AIPS_PACRI_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1423 #define AIPS_PACRI_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP2_SHIFT)) & AIPS_PACRI_TP2_MASK)
AnnaBridge 143:86740a56073b 1424 #define AIPS_PACRI_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1425 #define AIPS_PACRI_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1426 #define AIPS_PACRI_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP2_SHIFT)) & AIPS_PACRI_WP2_MASK)
AnnaBridge 143:86740a56073b 1427 #define AIPS_PACRI_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1428 #define AIPS_PACRI_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1429 #define AIPS_PACRI_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP2_SHIFT)) & AIPS_PACRI_SP2_MASK)
AnnaBridge 143:86740a56073b 1430 #define AIPS_PACRI_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1431 #define AIPS_PACRI_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1432 #define AIPS_PACRI_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP1_SHIFT)) & AIPS_PACRI_TP1_MASK)
AnnaBridge 143:86740a56073b 1433 #define AIPS_PACRI_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1434 #define AIPS_PACRI_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1435 #define AIPS_PACRI_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP1_SHIFT)) & AIPS_PACRI_WP1_MASK)
AnnaBridge 143:86740a56073b 1436 #define AIPS_PACRI_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1437 #define AIPS_PACRI_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1438 #define AIPS_PACRI_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP1_SHIFT)) & AIPS_PACRI_SP1_MASK)
AnnaBridge 143:86740a56073b 1439 #define AIPS_PACRI_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1440 #define AIPS_PACRI_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1441 #define AIPS_PACRI_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_TP0_SHIFT)) & AIPS_PACRI_TP0_MASK)
AnnaBridge 143:86740a56073b 1442 #define AIPS_PACRI_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1443 #define AIPS_PACRI_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1444 #define AIPS_PACRI_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_WP0_SHIFT)) & AIPS_PACRI_WP0_MASK)
AnnaBridge 143:86740a56073b 1445 #define AIPS_PACRI_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1446 #define AIPS_PACRI_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1447 #define AIPS_PACRI_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRI_SP0_SHIFT)) & AIPS_PACRI_SP0_MASK)
AnnaBridge 143:86740a56073b 1448
AnnaBridge 143:86740a56073b 1449 /*! @name PACRJ - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1450 #define AIPS_PACRJ_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1451 #define AIPS_PACRJ_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1452 #define AIPS_PACRJ_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP7_SHIFT)) & AIPS_PACRJ_TP7_MASK)
AnnaBridge 143:86740a56073b 1453 #define AIPS_PACRJ_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1454 #define AIPS_PACRJ_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1455 #define AIPS_PACRJ_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP7_SHIFT)) & AIPS_PACRJ_WP7_MASK)
AnnaBridge 143:86740a56073b 1456 #define AIPS_PACRJ_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1457 #define AIPS_PACRJ_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1458 #define AIPS_PACRJ_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP7_SHIFT)) & AIPS_PACRJ_SP7_MASK)
AnnaBridge 143:86740a56073b 1459 #define AIPS_PACRJ_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1460 #define AIPS_PACRJ_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1461 #define AIPS_PACRJ_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP6_SHIFT)) & AIPS_PACRJ_TP6_MASK)
AnnaBridge 143:86740a56073b 1462 #define AIPS_PACRJ_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1463 #define AIPS_PACRJ_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1464 #define AIPS_PACRJ_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP6_SHIFT)) & AIPS_PACRJ_WP6_MASK)
AnnaBridge 143:86740a56073b 1465 #define AIPS_PACRJ_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1466 #define AIPS_PACRJ_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1467 #define AIPS_PACRJ_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP6_SHIFT)) & AIPS_PACRJ_SP6_MASK)
AnnaBridge 143:86740a56073b 1468 #define AIPS_PACRJ_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1469 #define AIPS_PACRJ_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1470 #define AIPS_PACRJ_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP5_SHIFT)) & AIPS_PACRJ_TP5_MASK)
AnnaBridge 143:86740a56073b 1471 #define AIPS_PACRJ_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1472 #define AIPS_PACRJ_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1473 #define AIPS_PACRJ_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP5_SHIFT)) & AIPS_PACRJ_WP5_MASK)
AnnaBridge 143:86740a56073b 1474 #define AIPS_PACRJ_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1475 #define AIPS_PACRJ_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1476 #define AIPS_PACRJ_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP5_SHIFT)) & AIPS_PACRJ_SP5_MASK)
AnnaBridge 143:86740a56073b 1477 #define AIPS_PACRJ_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1478 #define AIPS_PACRJ_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1479 #define AIPS_PACRJ_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP4_SHIFT)) & AIPS_PACRJ_TP4_MASK)
AnnaBridge 143:86740a56073b 1480 #define AIPS_PACRJ_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1481 #define AIPS_PACRJ_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1482 #define AIPS_PACRJ_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP4_SHIFT)) & AIPS_PACRJ_WP4_MASK)
AnnaBridge 143:86740a56073b 1483 #define AIPS_PACRJ_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1484 #define AIPS_PACRJ_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1485 #define AIPS_PACRJ_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP4_SHIFT)) & AIPS_PACRJ_SP4_MASK)
AnnaBridge 143:86740a56073b 1486 #define AIPS_PACRJ_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1487 #define AIPS_PACRJ_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1488 #define AIPS_PACRJ_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP3_SHIFT)) & AIPS_PACRJ_TP3_MASK)
AnnaBridge 143:86740a56073b 1489 #define AIPS_PACRJ_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1490 #define AIPS_PACRJ_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1491 #define AIPS_PACRJ_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP3_SHIFT)) & AIPS_PACRJ_WP3_MASK)
AnnaBridge 143:86740a56073b 1492 #define AIPS_PACRJ_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1493 #define AIPS_PACRJ_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1494 #define AIPS_PACRJ_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP3_SHIFT)) & AIPS_PACRJ_SP3_MASK)
AnnaBridge 143:86740a56073b 1495 #define AIPS_PACRJ_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1496 #define AIPS_PACRJ_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1497 #define AIPS_PACRJ_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP2_SHIFT)) & AIPS_PACRJ_TP2_MASK)
AnnaBridge 143:86740a56073b 1498 #define AIPS_PACRJ_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1499 #define AIPS_PACRJ_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1500 #define AIPS_PACRJ_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP2_SHIFT)) & AIPS_PACRJ_WP2_MASK)
AnnaBridge 143:86740a56073b 1501 #define AIPS_PACRJ_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1502 #define AIPS_PACRJ_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1503 #define AIPS_PACRJ_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP2_SHIFT)) & AIPS_PACRJ_SP2_MASK)
AnnaBridge 143:86740a56073b 1504 #define AIPS_PACRJ_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1505 #define AIPS_PACRJ_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1506 #define AIPS_PACRJ_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP1_SHIFT)) & AIPS_PACRJ_TP1_MASK)
AnnaBridge 143:86740a56073b 1507 #define AIPS_PACRJ_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1508 #define AIPS_PACRJ_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1509 #define AIPS_PACRJ_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP1_SHIFT)) & AIPS_PACRJ_WP1_MASK)
AnnaBridge 143:86740a56073b 1510 #define AIPS_PACRJ_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1511 #define AIPS_PACRJ_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1512 #define AIPS_PACRJ_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP1_SHIFT)) & AIPS_PACRJ_SP1_MASK)
AnnaBridge 143:86740a56073b 1513 #define AIPS_PACRJ_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1514 #define AIPS_PACRJ_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1515 #define AIPS_PACRJ_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_TP0_SHIFT)) & AIPS_PACRJ_TP0_MASK)
AnnaBridge 143:86740a56073b 1516 #define AIPS_PACRJ_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1517 #define AIPS_PACRJ_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1518 #define AIPS_PACRJ_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_WP0_SHIFT)) & AIPS_PACRJ_WP0_MASK)
AnnaBridge 143:86740a56073b 1519 #define AIPS_PACRJ_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1520 #define AIPS_PACRJ_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1521 #define AIPS_PACRJ_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRJ_SP0_SHIFT)) & AIPS_PACRJ_SP0_MASK)
AnnaBridge 143:86740a56073b 1522
AnnaBridge 143:86740a56073b 1523 /*! @name PACRK - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1524 #define AIPS_PACRK_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1525 #define AIPS_PACRK_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1526 #define AIPS_PACRK_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP7_SHIFT)) & AIPS_PACRK_TP7_MASK)
AnnaBridge 143:86740a56073b 1527 #define AIPS_PACRK_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1528 #define AIPS_PACRK_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1529 #define AIPS_PACRK_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP7_SHIFT)) & AIPS_PACRK_WP7_MASK)
AnnaBridge 143:86740a56073b 1530 #define AIPS_PACRK_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1531 #define AIPS_PACRK_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1532 #define AIPS_PACRK_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP7_SHIFT)) & AIPS_PACRK_SP7_MASK)
AnnaBridge 143:86740a56073b 1533 #define AIPS_PACRK_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1534 #define AIPS_PACRK_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1535 #define AIPS_PACRK_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP6_SHIFT)) & AIPS_PACRK_TP6_MASK)
AnnaBridge 143:86740a56073b 1536 #define AIPS_PACRK_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1537 #define AIPS_PACRK_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1538 #define AIPS_PACRK_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP6_SHIFT)) & AIPS_PACRK_WP6_MASK)
AnnaBridge 143:86740a56073b 1539 #define AIPS_PACRK_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1540 #define AIPS_PACRK_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1541 #define AIPS_PACRK_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP6_SHIFT)) & AIPS_PACRK_SP6_MASK)
AnnaBridge 143:86740a56073b 1542 #define AIPS_PACRK_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1543 #define AIPS_PACRK_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1544 #define AIPS_PACRK_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP5_SHIFT)) & AIPS_PACRK_TP5_MASK)
AnnaBridge 143:86740a56073b 1545 #define AIPS_PACRK_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1546 #define AIPS_PACRK_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1547 #define AIPS_PACRK_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP5_SHIFT)) & AIPS_PACRK_WP5_MASK)
AnnaBridge 143:86740a56073b 1548 #define AIPS_PACRK_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1549 #define AIPS_PACRK_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1550 #define AIPS_PACRK_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP5_SHIFT)) & AIPS_PACRK_SP5_MASK)
AnnaBridge 143:86740a56073b 1551 #define AIPS_PACRK_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1552 #define AIPS_PACRK_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1553 #define AIPS_PACRK_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP4_SHIFT)) & AIPS_PACRK_TP4_MASK)
AnnaBridge 143:86740a56073b 1554 #define AIPS_PACRK_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1555 #define AIPS_PACRK_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1556 #define AIPS_PACRK_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP4_SHIFT)) & AIPS_PACRK_WP4_MASK)
AnnaBridge 143:86740a56073b 1557 #define AIPS_PACRK_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1558 #define AIPS_PACRK_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1559 #define AIPS_PACRK_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP4_SHIFT)) & AIPS_PACRK_SP4_MASK)
AnnaBridge 143:86740a56073b 1560 #define AIPS_PACRK_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1561 #define AIPS_PACRK_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1562 #define AIPS_PACRK_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP3_SHIFT)) & AIPS_PACRK_TP3_MASK)
AnnaBridge 143:86740a56073b 1563 #define AIPS_PACRK_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1564 #define AIPS_PACRK_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1565 #define AIPS_PACRK_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP3_SHIFT)) & AIPS_PACRK_WP3_MASK)
AnnaBridge 143:86740a56073b 1566 #define AIPS_PACRK_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1567 #define AIPS_PACRK_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1568 #define AIPS_PACRK_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP3_SHIFT)) & AIPS_PACRK_SP3_MASK)
AnnaBridge 143:86740a56073b 1569 #define AIPS_PACRK_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1570 #define AIPS_PACRK_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1571 #define AIPS_PACRK_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP2_SHIFT)) & AIPS_PACRK_TP2_MASK)
AnnaBridge 143:86740a56073b 1572 #define AIPS_PACRK_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1573 #define AIPS_PACRK_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1574 #define AIPS_PACRK_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP2_SHIFT)) & AIPS_PACRK_WP2_MASK)
AnnaBridge 143:86740a56073b 1575 #define AIPS_PACRK_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1576 #define AIPS_PACRK_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1577 #define AIPS_PACRK_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP2_SHIFT)) & AIPS_PACRK_SP2_MASK)
AnnaBridge 143:86740a56073b 1578 #define AIPS_PACRK_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1579 #define AIPS_PACRK_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1580 #define AIPS_PACRK_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP1_SHIFT)) & AIPS_PACRK_TP1_MASK)
AnnaBridge 143:86740a56073b 1581 #define AIPS_PACRK_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1582 #define AIPS_PACRK_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1583 #define AIPS_PACRK_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP1_SHIFT)) & AIPS_PACRK_WP1_MASK)
AnnaBridge 143:86740a56073b 1584 #define AIPS_PACRK_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1585 #define AIPS_PACRK_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1586 #define AIPS_PACRK_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP1_SHIFT)) & AIPS_PACRK_SP1_MASK)
AnnaBridge 143:86740a56073b 1587 #define AIPS_PACRK_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1588 #define AIPS_PACRK_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1589 #define AIPS_PACRK_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_TP0_SHIFT)) & AIPS_PACRK_TP0_MASK)
AnnaBridge 143:86740a56073b 1590 #define AIPS_PACRK_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1591 #define AIPS_PACRK_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1592 #define AIPS_PACRK_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_WP0_SHIFT)) & AIPS_PACRK_WP0_MASK)
AnnaBridge 143:86740a56073b 1593 #define AIPS_PACRK_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1594 #define AIPS_PACRK_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1595 #define AIPS_PACRK_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRK_SP0_SHIFT)) & AIPS_PACRK_SP0_MASK)
AnnaBridge 143:86740a56073b 1596
AnnaBridge 143:86740a56073b 1597 /*! @name PACRL - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1598 #define AIPS_PACRL_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1599 #define AIPS_PACRL_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1600 #define AIPS_PACRL_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP7_SHIFT)) & AIPS_PACRL_TP7_MASK)
AnnaBridge 143:86740a56073b 1601 #define AIPS_PACRL_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1602 #define AIPS_PACRL_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1603 #define AIPS_PACRL_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP7_SHIFT)) & AIPS_PACRL_WP7_MASK)
AnnaBridge 143:86740a56073b 1604 #define AIPS_PACRL_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1605 #define AIPS_PACRL_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1606 #define AIPS_PACRL_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP7_SHIFT)) & AIPS_PACRL_SP7_MASK)
AnnaBridge 143:86740a56073b 1607 #define AIPS_PACRL_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1608 #define AIPS_PACRL_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1609 #define AIPS_PACRL_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP6_SHIFT)) & AIPS_PACRL_TP6_MASK)
AnnaBridge 143:86740a56073b 1610 #define AIPS_PACRL_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1611 #define AIPS_PACRL_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1612 #define AIPS_PACRL_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP6_SHIFT)) & AIPS_PACRL_WP6_MASK)
AnnaBridge 143:86740a56073b 1613 #define AIPS_PACRL_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1614 #define AIPS_PACRL_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1615 #define AIPS_PACRL_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP6_SHIFT)) & AIPS_PACRL_SP6_MASK)
AnnaBridge 143:86740a56073b 1616 #define AIPS_PACRL_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1617 #define AIPS_PACRL_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1618 #define AIPS_PACRL_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP5_SHIFT)) & AIPS_PACRL_TP5_MASK)
AnnaBridge 143:86740a56073b 1619 #define AIPS_PACRL_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1620 #define AIPS_PACRL_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1621 #define AIPS_PACRL_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP5_SHIFT)) & AIPS_PACRL_WP5_MASK)
AnnaBridge 143:86740a56073b 1622 #define AIPS_PACRL_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1623 #define AIPS_PACRL_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1624 #define AIPS_PACRL_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP5_SHIFT)) & AIPS_PACRL_SP5_MASK)
AnnaBridge 143:86740a56073b 1625 #define AIPS_PACRL_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1626 #define AIPS_PACRL_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1627 #define AIPS_PACRL_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP4_SHIFT)) & AIPS_PACRL_TP4_MASK)
AnnaBridge 143:86740a56073b 1628 #define AIPS_PACRL_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1629 #define AIPS_PACRL_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1630 #define AIPS_PACRL_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP4_SHIFT)) & AIPS_PACRL_WP4_MASK)
AnnaBridge 143:86740a56073b 1631 #define AIPS_PACRL_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1632 #define AIPS_PACRL_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1633 #define AIPS_PACRL_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP4_SHIFT)) & AIPS_PACRL_SP4_MASK)
AnnaBridge 143:86740a56073b 1634 #define AIPS_PACRL_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1635 #define AIPS_PACRL_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1636 #define AIPS_PACRL_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP3_SHIFT)) & AIPS_PACRL_TP3_MASK)
AnnaBridge 143:86740a56073b 1637 #define AIPS_PACRL_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1638 #define AIPS_PACRL_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1639 #define AIPS_PACRL_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP3_SHIFT)) & AIPS_PACRL_WP3_MASK)
AnnaBridge 143:86740a56073b 1640 #define AIPS_PACRL_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1641 #define AIPS_PACRL_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1642 #define AIPS_PACRL_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP3_SHIFT)) & AIPS_PACRL_SP3_MASK)
AnnaBridge 143:86740a56073b 1643 #define AIPS_PACRL_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1644 #define AIPS_PACRL_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1645 #define AIPS_PACRL_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP2_SHIFT)) & AIPS_PACRL_TP2_MASK)
AnnaBridge 143:86740a56073b 1646 #define AIPS_PACRL_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1647 #define AIPS_PACRL_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1648 #define AIPS_PACRL_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP2_SHIFT)) & AIPS_PACRL_WP2_MASK)
AnnaBridge 143:86740a56073b 1649 #define AIPS_PACRL_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1650 #define AIPS_PACRL_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1651 #define AIPS_PACRL_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP2_SHIFT)) & AIPS_PACRL_SP2_MASK)
AnnaBridge 143:86740a56073b 1652 #define AIPS_PACRL_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1653 #define AIPS_PACRL_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1654 #define AIPS_PACRL_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP1_SHIFT)) & AIPS_PACRL_TP1_MASK)
AnnaBridge 143:86740a56073b 1655 #define AIPS_PACRL_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1656 #define AIPS_PACRL_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1657 #define AIPS_PACRL_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP1_SHIFT)) & AIPS_PACRL_WP1_MASK)
AnnaBridge 143:86740a56073b 1658 #define AIPS_PACRL_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1659 #define AIPS_PACRL_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1660 #define AIPS_PACRL_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP1_SHIFT)) & AIPS_PACRL_SP1_MASK)
AnnaBridge 143:86740a56073b 1661 #define AIPS_PACRL_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1662 #define AIPS_PACRL_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1663 #define AIPS_PACRL_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_TP0_SHIFT)) & AIPS_PACRL_TP0_MASK)
AnnaBridge 143:86740a56073b 1664 #define AIPS_PACRL_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1665 #define AIPS_PACRL_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1666 #define AIPS_PACRL_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_WP0_SHIFT)) & AIPS_PACRL_WP0_MASK)
AnnaBridge 143:86740a56073b 1667 #define AIPS_PACRL_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1668 #define AIPS_PACRL_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1669 #define AIPS_PACRL_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRL_SP0_SHIFT)) & AIPS_PACRL_SP0_MASK)
AnnaBridge 143:86740a56073b 1670
AnnaBridge 143:86740a56073b 1671 /*! @name PACRM - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1672 #define AIPS_PACRM_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1673 #define AIPS_PACRM_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1674 #define AIPS_PACRM_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP7_SHIFT)) & AIPS_PACRM_TP7_MASK)
AnnaBridge 143:86740a56073b 1675 #define AIPS_PACRM_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1676 #define AIPS_PACRM_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1677 #define AIPS_PACRM_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP7_SHIFT)) & AIPS_PACRM_WP7_MASK)
AnnaBridge 143:86740a56073b 1678 #define AIPS_PACRM_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1679 #define AIPS_PACRM_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1680 #define AIPS_PACRM_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP7_SHIFT)) & AIPS_PACRM_SP7_MASK)
AnnaBridge 143:86740a56073b 1681 #define AIPS_PACRM_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1682 #define AIPS_PACRM_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1683 #define AIPS_PACRM_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP6_SHIFT)) & AIPS_PACRM_TP6_MASK)
AnnaBridge 143:86740a56073b 1684 #define AIPS_PACRM_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1685 #define AIPS_PACRM_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1686 #define AIPS_PACRM_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP6_SHIFT)) & AIPS_PACRM_WP6_MASK)
AnnaBridge 143:86740a56073b 1687 #define AIPS_PACRM_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1688 #define AIPS_PACRM_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1689 #define AIPS_PACRM_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP6_SHIFT)) & AIPS_PACRM_SP6_MASK)
AnnaBridge 143:86740a56073b 1690 #define AIPS_PACRM_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1691 #define AIPS_PACRM_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1692 #define AIPS_PACRM_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP5_SHIFT)) & AIPS_PACRM_TP5_MASK)
AnnaBridge 143:86740a56073b 1693 #define AIPS_PACRM_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1694 #define AIPS_PACRM_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1695 #define AIPS_PACRM_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP5_SHIFT)) & AIPS_PACRM_WP5_MASK)
AnnaBridge 143:86740a56073b 1696 #define AIPS_PACRM_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1697 #define AIPS_PACRM_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1698 #define AIPS_PACRM_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP5_SHIFT)) & AIPS_PACRM_SP5_MASK)
AnnaBridge 143:86740a56073b 1699 #define AIPS_PACRM_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1700 #define AIPS_PACRM_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1701 #define AIPS_PACRM_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP4_SHIFT)) & AIPS_PACRM_TP4_MASK)
AnnaBridge 143:86740a56073b 1702 #define AIPS_PACRM_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1703 #define AIPS_PACRM_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1704 #define AIPS_PACRM_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP4_SHIFT)) & AIPS_PACRM_WP4_MASK)
AnnaBridge 143:86740a56073b 1705 #define AIPS_PACRM_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1706 #define AIPS_PACRM_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1707 #define AIPS_PACRM_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP4_SHIFT)) & AIPS_PACRM_SP4_MASK)
AnnaBridge 143:86740a56073b 1708 #define AIPS_PACRM_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1709 #define AIPS_PACRM_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1710 #define AIPS_PACRM_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP3_SHIFT)) & AIPS_PACRM_TP3_MASK)
AnnaBridge 143:86740a56073b 1711 #define AIPS_PACRM_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1712 #define AIPS_PACRM_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1713 #define AIPS_PACRM_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP3_SHIFT)) & AIPS_PACRM_WP3_MASK)
AnnaBridge 143:86740a56073b 1714 #define AIPS_PACRM_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1715 #define AIPS_PACRM_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1716 #define AIPS_PACRM_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP3_SHIFT)) & AIPS_PACRM_SP3_MASK)
AnnaBridge 143:86740a56073b 1717 #define AIPS_PACRM_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1718 #define AIPS_PACRM_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1719 #define AIPS_PACRM_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP2_SHIFT)) & AIPS_PACRM_TP2_MASK)
AnnaBridge 143:86740a56073b 1720 #define AIPS_PACRM_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1721 #define AIPS_PACRM_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1722 #define AIPS_PACRM_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP2_SHIFT)) & AIPS_PACRM_WP2_MASK)
AnnaBridge 143:86740a56073b 1723 #define AIPS_PACRM_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1724 #define AIPS_PACRM_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1725 #define AIPS_PACRM_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP2_SHIFT)) & AIPS_PACRM_SP2_MASK)
AnnaBridge 143:86740a56073b 1726 #define AIPS_PACRM_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1727 #define AIPS_PACRM_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1728 #define AIPS_PACRM_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP1_SHIFT)) & AIPS_PACRM_TP1_MASK)
AnnaBridge 143:86740a56073b 1729 #define AIPS_PACRM_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1730 #define AIPS_PACRM_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1731 #define AIPS_PACRM_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP1_SHIFT)) & AIPS_PACRM_WP1_MASK)
AnnaBridge 143:86740a56073b 1732 #define AIPS_PACRM_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1733 #define AIPS_PACRM_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1734 #define AIPS_PACRM_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP1_SHIFT)) & AIPS_PACRM_SP1_MASK)
AnnaBridge 143:86740a56073b 1735 #define AIPS_PACRM_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1736 #define AIPS_PACRM_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1737 #define AIPS_PACRM_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_TP0_SHIFT)) & AIPS_PACRM_TP0_MASK)
AnnaBridge 143:86740a56073b 1738 #define AIPS_PACRM_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1739 #define AIPS_PACRM_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1740 #define AIPS_PACRM_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_WP0_SHIFT)) & AIPS_PACRM_WP0_MASK)
AnnaBridge 143:86740a56073b 1741 #define AIPS_PACRM_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1742 #define AIPS_PACRM_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1743 #define AIPS_PACRM_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRM_SP0_SHIFT)) & AIPS_PACRM_SP0_MASK)
AnnaBridge 143:86740a56073b 1744
AnnaBridge 143:86740a56073b 1745 /*! @name PACRN - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1746 #define AIPS_PACRN_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1747 #define AIPS_PACRN_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1748 #define AIPS_PACRN_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP7_SHIFT)) & AIPS_PACRN_TP7_MASK)
AnnaBridge 143:86740a56073b 1749 #define AIPS_PACRN_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1750 #define AIPS_PACRN_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1751 #define AIPS_PACRN_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP7_SHIFT)) & AIPS_PACRN_WP7_MASK)
AnnaBridge 143:86740a56073b 1752 #define AIPS_PACRN_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1753 #define AIPS_PACRN_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1754 #define AIPS_PACRN_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP7_SHIFT)) & AIPS_PACRN_SP7_MASK)
AnnaBridge 143:86740a56073b 1755 #define AIPS_PACRN_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1756 #define AIPS_PACRN_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1757 #define AIPS_PACRN_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP6_SHIFT)) & AIPS_PACRN_TP6_MASK)
AnnaBridge 143:86740a56073b 1758 #define AIPS_PACRN_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1759 #define AIPS_PACRN_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1760 #define AIPS_PACRN_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP6_SHIFT)) & AIPS_PACRN_WP6_MASK)
AnnaBridge 143:86740a56073b 1761 #define AIPS_PACRN_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1762 #define AIPS_PACRN_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1763 #define AIPS_PACRN_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP6_SHIFT)) & AIPS_PACRN_SP6_MASK)
AnnaBridge 143:86740a56073b 1764 #define AIPS_PACRN_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1765 #define AIPS_PACRN_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1766 #define AIPS_PACRN_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP5_SHIFT)) & AIPS_PACRN_TP5_MASK)
AnnaBridge 143:86740a56073b 1767 #define AIPS_PACRN_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1768 #define AIPS_PACRN_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1769 #define AIPS_PACRN_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP5_SHIFT)) & AIPS_PACRN_WP5_MASK)
AnnaBridge 143:86740a56073b 1770 #define AIPS_PACRN_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1771 #define AIPS_PACRN_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1772 #define AIPS_PACRN_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP5_SHIFT)) & AIPS_PACRN_SP5_MASK)
AnnaBridge 143:86740a56073b 1773 #define AIPS_PACRN_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1774 #define AIPS_PACRN_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1775 #define AIPS_PACRN_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP4_SHIFT)) & AIPS_PACRN_TP4_MASK)
AnnaBridge 143:86740a56073b 1776 #define AIPS_PACRN_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1777 #define AIPS_PACRN_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1778 #define AIPS_PACRN_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP4_SHIFT)) & AIPS_PACRN_WP4_MASK)
AnnaBridge 143:86740a56073b 1779 #define AIPS_PACRN_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1780 #define AIPS_PACRN_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1781 #define AIPS_PACRN_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP4_SHIFT)) & AIPS_PACRN_SP4_MASK)
AnnaBridge 143:86740a56073b 1782 #define AIPS_PACRN_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1783 #define AIPS_PACRN_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1784 #define AIPS_PACRN_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP3_SHIFT)) & AIPS_PACRN_TP3_MASK)
AnnaBridge 143:86740a56073b 1785 #define AIPS_PACRN_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1786 #define AIPS_PACRN_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1787 #define AIPS_PACRN_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP3_SHIFT)) & AIPS_PACRN_WP3_MASK)
AnnaBridge 143:86740a56073b 1788 #define AIPS_PACRN_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1789 #define AIPS_PACRN_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1790 #define AIPS_PACRN_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP3_SHIFT)) & AIPS_PACRN_SP3_MASK)
AnnaBridge 143:86740a56073b 1791 #define AIPS_PACRN_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1792 #define AIPS_PACRN_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1793 #define AIPS_PACRN_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP2_SHIFT)) & AIPS_PACRN_TP2_MASK)
AnnaBridge 143:86740a56073b 1794 #define AIPS_PACRN_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1795 #define AIPS_PACRN_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1796 #define AIPS_PACRN_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP2_SHIFT)) & AIPS_PACRN_WP2_MASK)
AnnaBridge 143:86740a56073b 1797 #define AIPS_PACRN_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1798 #define AIPS_PACRN_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1799 #define AIPS_PACRN_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP2_SHIFT)) & AIPS_PACRN_SP2_MASK)
AnnaBridge 143:86740a56073b 1800 #define AIPS_PACRN_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1801 #define AIPS_PACRN_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1802 #define AIPS_PACRN_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP1_SHIFT)) & AIPS_PACRN_TP1_MASK)
AnnaBridge 143:86740a56073b 1803 #define AIPS_PACRN_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1804 #define AIPS_PACRN_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1805 #define AIPS_PACRN_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP1_SHIFT)) & AIPS_PACRN_WP1_MASK)
AnnaBridge 143:86740a56073b 1806 #define AIPS_PACRN_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1807 #define AIPS_PACRN_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1808 #define AIPS_PACRN_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP1_SHIFT)) & AIPS_PACRN_SP1_MASK)
AnnaBridge 143:86740a56073b 1809 #define AIPS_PACRN_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1810 #define AIPS_PACRN_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1811 #define AIPS_PACRN_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_TP0_SHIFT)) & AIPS_PACRN_TP0_MASK)
AnnaBridge 143:86740a56073b 1812 #define AIPS_PACRN_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1813 #define AIPS_PACRN_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1814 #define AIPS_PACRN_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_WP0_SHIFT)) & AIPS_PACRN_WP0_MASK)
AnnaBridge 143:86740a56073b 1815 #define AIPS_PACRN_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1816 #define AIPS_PACRN_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1817 #define AIPS_PACRN_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRN_SP0_SHIFT)) & AIPS_PACRN_SP0_MASK)
AnnaBridge 143:86740a56073b 1818
AnnaBridge 143:86740a56073b 1819 /*! @name PACRO - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1820 #define AIPS_PACRO_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1821 #define AIPS_PACRO_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1822 #define AIPS_PACRO_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP7_SHIFT)) & AIPS_PACRO_TP7_MASK)
AnnaBridge 143:86740a56073b 1823 #define AIPS_PACRO_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1824 #define AIPS_PACRO_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1825 #define AIPS_PACRO_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP7_SHIFT)) & AIPS_PACRO_WP7_MASK)
AnnaBridge 143:86740a56073b 1826 #define AIPS_PACRO_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1827 #define AIPS_PACRO_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1828 #define AIPS_PACRO_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP7_SHIFT)) & AIPS_PACRO_SP7_MASK)
AnnaBridge 143:86740a56073b 1829 #define AIPS_PACRO_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1830 #define AIPS_PACRO_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1831 #define AIPS_PACRO_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP6_SHIFT)) & AIPS_PACRO_TP6_MASK)
AnnaBridge 143:86740a56073b 1832 #define AIPS_PACRO_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1833 #define AIPS_PACRO_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1834 #define AIPS_PACRO_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP6_SHIFT)) & AIPS_PACRO_WP6_MASK)
AnnaBridge 143:86740a56073b 1835 #define AIPS_PACRO_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1836 #define AIPS_PACRO_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1837 #define AIPS_PACRO_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP6_SHIFT)) & AIPS_PACRO_SP6_MASK)
AnnaBridge 143:86740a56073b 1838 #define AIPS_PACRO_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1839 #define AIPS_PACRO_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1840 #define AIPS_PACRO_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP5_SHIFT)) & AIPS_PACRO_TP5_MASK)
AnnaBridge 143:86740a56073b 1841 #define AIPS_PACRO_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1842 #define AIPS_PACRO_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1843 #define AIPS_PACRO_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP5_SHIFT)) & AIPS_PACRO_WP5_MASK)
AnnaBridge 143:86740a56073b 1844 #define AIPS_PACRO_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1845 #define AIPS_PACRO_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1846 #define AIPS_PACRO_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP5_SHIFT)) & AIPS_PACRO_SP5_MASK)
AnnaBridge 143:86740a56073b 1847 #define AIPS_PACRO_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1848 #define AIPS_PACRO_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1849 #define AIPS_PACRO_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP4_SHIFT)) & AIPS_PACRO_TP4_MASK)
AnnaBridge 143:86740a56073b 1850 #define AIPS_PACRO_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1851 #define AIPS_PACRO_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1852 #define AIPS_PACRO_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP4_SHIFT)) & AIPS_PACRO_WP4_MASK)
AnnaBridge 143:86740a56073b 1853 #define AIPS_PACRO_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1854 #define AIPS_PACRO_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1855 #define AIPS_PACRO_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP4_SHIFT)) & AIPS_PACRO_SP4_MASK)
AnnaBridge 143:86740a56073b 1856 #define AIPS_PACRO_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1857 #define AIPS_PACRO_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1858 #define AIPS_PACRO_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP3_SHIFT)) & AIPS_PACRO_TP3_MASK)
AnnaBridge 143:86740a56073b 1859 #define AIPS_PACRO_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1860 #define AIPS_PACRO_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1861 #define AIPS_PACRO_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP3_SHIFT)) & AIPS_PACRO_WP3_MASK)
AnnaBridge 143:86740a56073b 1862 #define AIPS_PACRO_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1863 #define AIPS_PACRO_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1864 #define AIPS_PACRO_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP3_SHIFT)) & AIPS_PACRO_SP3_MASK)
AnnaBridge 143:86740a56073b 1865 #define AIPS_PACRO_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1866 #define AIPS_PACRO_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1867 #define AIPS_PACRO_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP2_SHIFT)) & AIPS_PACRO_TP2_MASK)
AnnaBridge 143:86740a56073b 1868 #define AIPS_PACRO_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1869 #define AIPS_PACRO_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1870 #define AIPS_PACRO_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP2_SHIFT)) & AIPS_PACRO_WP2_MASK)
AnnaBridge 143:86740a56073b 1871 #define AIPS_PACRO_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1872 #define AIPS_PACRO_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1873 #define AIPS_PACRO_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP2_SHIFT)) & AIPS_PACRO_SP2_MASK)
AnnaBridge 143:86740a56073b 1874 #define AIPS_PACRO_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1875 #define AIPS_PACRO_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1876 #define AIPS_PACRO_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP1_SHIFT)) & AIPS_PACRO_TP1_MASK)
AnnaBridge 143:86740a56073b 1877 #define AIPS_PACRO_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1878 #define AIPS_PACRO_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1879 #define AIPS_PACRO_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP1_SHIFT)) & AIPS_PACRO_WP1_MASK)
AnnaBridge 143:86740a56073b 1880 #define AIPS_PACRO_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1881 #define AIPS_PACRO_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1882 #define AIPS_PACRO_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP1_SHIFT)) & AIPS_PACRO_SP1_MASK)
AnnaBridge 143:86740a56073b 1883 #define AIPS_PACRO_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1884 #define AIPS_PACRO_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1885 #define AIPS_PACRO_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_TP0_SHIFT)) & AIPS_PACRO_TP0_MASK)
AnnaBridge 143:86740a56073b 1886 #define AIPS_PACRO_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1887 #define AIPS_PACRO_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1888 #define AIPS_PACRO_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_WP0_SHIFT)) & AIPS_PACRO_WP0_MASK)
AnnaBridge 143:86740a56073b 1889 #define AIPS_PACRO_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1890 #define AIPS_PACRO_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1891 #define AIPS_PACRO_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRO_SP0_SHIFT)) & AIPS_PACRO_SP0_MASK)
AnnaBridge 143:86740a56073b 1892
AnnaBridge 143:86740a56073b 1893 /*! @name PACRP - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1894 #define AIPS_PACRP_TP7_MASK (0x1U)
AnnaBridge 143:86740a56073b 1895 #define AIPS_PACRP_TP7_SHIFT (0U)
AnnaBridge 143:86740a56073b 1896 #define AIPS_PACRP_TP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP7_SHIFT)) & AIPS_PACRP_TP7_MASK)
AnnaBridge 143:86740a56073b 1897 #define AIPS_PACRP_WP7_MASK (0x2U)
AnnaBridge 143:86740a56073b 1898 #define AIPS_PACRP_WP7_SHIFT (1U)
AnnaBridge 143:86740a56073b 1899 #define AIPS_PACRP_WP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP7_SHIFT)) & AIPS_PACRP_WP7_MASK)
AnnaBridge 143:86740a56073b 1900 #define AIPS_PACRP_SP7_MASK (0x4U)
AnnaBridge 143:86740a56073b 1901 #define AIPS_PACRP_SP7_SHIFT (2U)
AnnaBridge 143:86740a56073b 1902 #define AIPS_PACRP_SP7(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP7_SHIFT)) & AIPS_PACRP_SP7_MASK)
AnnaBridge 143:86740a56073b 1903 #define AIPS_PACRP_TP6_MASK (0x10U)
AnnaBridge 143:86740a56073b 1904 #define AIPS_PACRP_TP6_SHIFT (4U)
AnnaBridge 143:86740a56073b 1905 #define AIPS_PACRP_TP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP6_SHIFT)) & AIPS_PACRP_TP6_MASK)
AnnaBridge 143:86740a56073b 1906 #define AIPS_PACRP_WP6_MASK (0x20U)
AnnaBridge 143:86740a56073b 1907 #define AIPS_PACRP_WP6_SHIFT (5U)
AnnaBridge 143:86740a56073b 1908 #define AIPS_PACRP_WP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP6_SHIFT)) & AIPS_PACRP_WP6_MASK)
AnnaBridge 143:86740a56073b 1909 #define AIPS_PACRP_SP6_MASK (0x40U)
AnnaBridge 143:86740a56073b 1910 #define AIPS_PACRP_SP6_SHIFT (6U)
AnnaBridge 143:86740a56073b 1911 #define AIPS_PACRP_SP6(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP6_SHIFT)) & AIPS_PACRP_SP6_MASK)
AnnaBridge 143:86740a56073b 1912 #define AIPS_PACRP_TP5_MASK (0x100U)
AnnaBridge 143:86740a56073b 1913 #define AIPS_PACRP_TP5_SHIFT (8U)
AnnaBridge 143:86740a56073b 1914 #define AIPS_PACRP_TP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP5_SHIFT)) & AIPS_PACRP_TP5_MASK)
AnnaBridge 143:86740a56073b 1915 #define AIPS_PACRP_WP5_MASK (0x200U)
AnnaBridge 143:86740a56073b 1916 #define AIPS_PACRP_WP5_SHIFT (9U)
AnnaBridge 143:86740a56073b 1917 #define AIPS_PACRP_WP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP5_SHIFT)) & AIPS_PACRP_WP5_MASK)
AnnaBridge 143:86740a56073b 1918 #define AIPS_PACRP_SP5_MASK (0x400U)
AnnaBridge 143:86740a56073b 1919 #define AIPS_PACRP_SP5_SHIFT (10U)
AnnaBridge 143:86740a56073b 1920 #define AIPS_PACRP_SP5(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP5_SHIFT)) & AIPS_PACRP_SP5_MASK)
AnnaBridge 143:86740a56073b 1921 #define AIPS_PACRP_TP4_MASK (0x1000U)
AnnaBridge 143:86740a56073b 1922 #define AIPS_PACRP_TP4_SHIFT (12U)
AnnaBridge 143:86740a56073b 1923 #define AIPS_PACRP_TP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP4_SHIFT)) & AIPS_PACRP_TP4_MASK)
AnnaBridge 143:86740a56073b 1924 #define AIPS_PACRP_WP4_MASK (0x2000U)
AnnaBridge 143:86740a56073b 1925 #define AIPS_PACRP_WP4_SHIFT (13U)
AnnaBridge 143:86740a56073b 1926 #define AIPS_PACRP_WP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP4_SHIFT)) & AIPS_PACRP_WP4_MASK)
AnnaBridge 143:86740a56073b 1927 #define AIPS_PACRP_SP4_MASK (0x4000U)
AnnaBridge 143:86740a56073b 1928 #define AIPS_PACRP_SP4_SHIFT (14U)
AnnaBridge 143:86740a56073b 1929 #define AIPS_PACRP_SP4(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP4_SHIFT)) & AIPS_PACRP_SP4_MASK)
AnnaBridge 143:86740a56073b 1930 #define AIPS_PACRP_TP3_MASK (0x10000U)
AnnaBridge 143:86740a56073b 1931 #define AIPS_PACRP_TP3_SHIFT (16U)
AnnaBridge 143:86740a56073b 1932 #define AIPS_PACRP_TP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP3_SHIFT)) & AIPS_PACRP_TP3_MASK)
AnnaBridge 143:86740a56073b 1933 #define AIPS_PACRP_WP3_MASK (0x20000U)
AnnaBridge 143:86740a56073b 1934 #define AIPS_PACRP_WP3_SHIFT (17U)
AnnaBridge 143:86740a56073b 1935 #define AIPS_PACRP_WP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP3_SHIFT)) & AIPS_PACRP_WP3_MASK)
AnnaBridge 143:86740a56073b 1936 #define AIPS_PACRP_SP3_MASK (0x40000U)
AnnaBridge 143:86740a56073b 1937 #define AIPS_PACRP_SP3_SHIFT (18U)
AnnaBridge 143:86740a56073b 1938 #define AIPS_PACRP_SP3(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP3_SHIFT)) & AIPS_PACRP_SP3_MASK)
AnnaBridge 143:86740a56073b 1939 #define AIPS_PACRP_TP2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 1940 #define AIPS_PACRP_TP2_SHIFT (20U)
AnnaBridge 143:86740a56073b 1941 #define AIPS_PACRP_TP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP2_SHIFT)) & AIPS_PACRP_TP2_MASK)
AnnaBridge 143:86740a56073b 1942 #define AIPS_PACRP_WP2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 1943 #define AIPS_PACRP_WP2_SHIFT (21U)
AnnaBridge 143:86740a56073b 1944 #define AIPS_PACRP_WP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP2_SHIFT)) & AIPS_PACRP_WP2_MASK)
AnnaBridge 143:86740a56073b 1945 #define AIPS_PACRP_SP2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 1946 #define AIPS_PACRP_SP2_SHIFT (22U)
AnnaBridge 143:86740a56073b 1947 #define AIPS_PACRP_SP2(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP2_SHIFT)) & AIPS_PACRP_SP2_MASK)
AnnaBridge 143:86740a56073b 1948 #define AIPS_PACRP_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1949 #define AIPS_PACRP_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1950 #define AIPS_PACRP_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP1_SHIFT)) & AIPS_PACRP_TP1_MASK)
AnnaBridge 143:86740a56073b 1951 #define AIPS_PACRP_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1952 #define AIPS_PACRP_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1953 #define AIPS_PACRP_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP1_SHIFT)) & AIPS_PACRP_WP1_MASK)
AnnaBridge 143:86740a56073b 1954 #define AIPS_PACRP_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1955 #define AIPS_PACRP_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1956 #define AIPS_PACRP_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP1_SHIFT)) & AIPS_PACRP_SP1_MASK)
AnnaBridge 143:86740a56073b 1957 #define AIPS_PACRP_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1958 #define AIPS_PACRP_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1959 #define AIPS_PACRP_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_TP0_SHIFT)) & AIPS_PACRP_TP0_MASK)
AnnaBridge 143:86740a56073b 1960 #define AIPS_PACRP_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1961 #define AIPS_PACRP_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1962 #define AIPS_PACRP_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_WP0_SHIFT)) & AIPS_PACRP_WP0_MASK)
AnnaBridge 143:86740a56073b 1963 #define AIPS_PACRP_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1964 #define AIPS_PACRP_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1965 #define AIPS_PACRP_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRP_SP0_SHIFT)) & AIPS_PACRP_SP0_MASK)
AnnaBridge 143:86740a56073b 1966
AnnaBridge 143:86740a56073b 1967 /*! @name PACRU - Peripheral Access Control Register */
AnnaBridge 143:86740a56073b 1968 #define AIPS_PACRU_TP1_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 1969 #define AIPS_PACRU_TP1_SHIFT (24U)
AnnaBridge 143:86740a56073b 1970 #define AIPS_PACRU_TP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP1_SHIFT)) & AIPS_PACRU_TP1_MASK)
AnnaBridge 143:86740a56073b 1971 #define AIPS_PACRU_WP1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 1972 #define AIPS_PACRU_WP1_SHIFT (25U)
AnnaBridge 143:86740a56073b 1973 #define AIPS_PACRU_WP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP1_SHIFT)) & AIPS_PACRU_WP1_MASK)
AnnaBridge 143:86740a56073b 1974 #define AIPS_PACRU_SP1_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 1975 #define AIPS_PACRU_SP1_SHIFT (26U)
AnnaBridge 143:86740a56073b 1976 #define AIPS_PACRU_SP1(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP1_SHIFT)) & AIPS_PACRU_SP1_MASK)
AnnaBridge 143:86740a56073b 1977 #define AIPS_PACRU_TP0_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 1978 #define AIPS_PACRU_TP0_SHIFT (28U)
AnnaBridge 143:86740a56073b 1979 #define AIPS_PACRU_TP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_TP0_SHIFT)) & AIPS_PACRU_TP0_MASK)
AnnaBridge 143:86740a56073b 1980 #define AIPS_PACRU_WP0_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 1981 #define AIPS_PACRU_WP0_SHIFT (29U)
AnnaBridge 143:86740a56073b 1982 #define AIPS_PACRU_WP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_WP0_SHIFT)) & AIPS_PACRU_WP0_MASK)
AnnaBridge 143:86740a56073b 1983 #define AIPS_PACRU_SP0_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 1984 #define AIPS_PACRU_SP0_SHIFT (30U)
AnnaBridge 143:86740a56073b 1985 #define AIPS_PACRU_SP0(x) (((uint32_t)(((uint32_t)(x)) << AIPS_PACRU_SP0_SHIFT)) & AIPS_PACRU_SP0_MASK)
AnnaBridge 143:86740a56073b 1986
AnnaBridge 143:86740a56073b 1987
AnnaBridge 143:86740a56073b 1988 /*!
AnnaBridge 143:86740a56073b 1989 * @}
AnnaBridge 143:86740a56073b 1990 */ /* end of group AIPS_Register_Masks */
AnnaBridge 143:86740a56073b 1991
AnnaBridge 143:86740a56073b 1992
AnnaBridge 143:86740a56073b 1993 /* AIPS - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 1994 /** Peripheral AIPS0 base address */
AnnaBridge 143:86740a56073b 1995 #define AIPS0_BASE (0x40000000u)
AnnaBridge 143:86740a56073b 1996 /** Peripheral AIPS0 base pointer */
AnnaBridge 143:86740a56073b 1997 #define AIPS0 ((AIPS_Type *)AIPS0_BASE)
AnnaBridge 143:86740a56073b 1998 /** Peripheral AIPS1 base address */
AnnaBridge 143:86740a56073b 1999 #define AIPS1_BASE (0x40080000u)
AnnaBridge 143:86740a56073b 2000 /** Peripheral AIPS1 base pointer */
AnnaBridge 143:86740a56073b 2001 #define AIPS1 ((AIPS_Type *)AIPS1_BASE)
AnnaBridge 143:86740a56073b 2002 /** Array initializer of AIPS peripheral base addresses */
AnnaBridge 143:86740a56073b 2003 #define AIPS_BASE_ADDRS { AIPS0_BASE, AIPS1_BASE }
AnnaBridge 143:86740a56073b 2004 /** Array initializer of AIPS peripheral base pointers */
AnnaBridge 143:86740a56073b 2005 #define AIPS_BASE_PTRS { AIPS0, AIPS1 }
AnnaBridge 143:86740a56073b 2006
AnnaBridge 143:86740a56073b 2007 /*!
AnnaBridge 143:86740a56073b 2008 * @}
AnnaBridge 143:86740a56073b 2009 */ /* end of group AIPS_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 2010
AnnaBridge 143:86740a56073b 2011
AnnaBridge 143:86740a56073b 2012 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 2013 -- AXBS Peripheral Access Layer
AnnaBridge 143:86740a56073b 2014 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 2015
AnnaBridge 143:86740a56073b 2016 /*!
AnnaBridge 143:86740a56073b 2017 * @addtogroup AXBS_Peripheral_Access_Layer AXBS Peripheral Access Layer
AnnaBridge 143:86740a56073b 2018 * @{
AnnaBridge 143:86740a56073b 2019 */
AnnaBridge 143:86740a56073b 2020
AnnaBridge 143:86740a56073b 2021 /** AXBS - Register Layout Typedef */
AnnaBridge 143:86740a56073b 2022 typedef struct {
AnnaBridge 143:86740a56073b 2023 struct { /* offset: 0x0, array step: 0x100 */
AnnaBridge 143:86740a56073b 2024 __IO uint32_t PRS; /**< Priority Registers Slave, array offset: 0x0, array step: 0x100 */
AnnaBridge 143:86740a56073b 2025 uint8_t RESERVED_0[12];
AnnaBridge 143:86740a56073b 2026 __IO uint32_t CRS; /**< Control Register, array offset: 0x10, array step: 0x100 */
AnnaBridge 143:86740a56073b 2027 uint8_t RESERVED_1[236];
AnnaBridge 143:86740a56073b 2028 } SLAVE[5];
AnnaBridge 143:86740a56073b 2029 uint8_t RESERVED_0[768];
AnnaBridge 143:86740a56073b 2030 __IO uint32_t MGPCR0; /**< Master General Purpose Control Register, offset: 0x800 */
AnnaBridge 143:86740a56073b 2031 uint8_t RESERVED_1[252];
AnnaBridge 143:86740a56073b 2032 __IO uint32_t MGPCR1; /**< Master General Purpose Control Register, offset: 0x900 */
AnnaBridge 143:86740a56073b 2033 uint8_t RESERVED_2[252];
AnnaBridge 143:86740a56073b 2034 __IO uint32_t MGPCR2; /**< Master General Purpose Control Register, offset: 0xA00 */
AnnaBridge 143:86740a56073b 2035 uint8_t RESERVED_3[508];
AnnaBridge 143:86740a56073b 2036 __IO uint32_t MGPCR4; /**< Master General Purpose Control Register, offset: 0xC00 */
AnnaBridge 143:86740a56073b 2037 uint8_t RESERVED_4[252];
AnnaBridge 143:86740a56073b 2038 __IO uint32_t MGPCR5; /**< Master General Purpose Control Register, offset: 0xD00 */
AnnaBridge 143:86740a56073b 2039 } AXBS_Type;
AnnaBridge 143:86740a56073b 2040
AnnaBridge 143:86740a56073b 2041 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 2042 -- AXBS Register Masks
AnnaBridge 143:86740a56073b 2043 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 2044
AnnaBridge 143:86740a56073b 2045 /*!
AnnaBridge 143:86740a56073b 2046 * @addtogroup AXBS_Register_Masks AXBS Register Masks
AnnaBridge 143:86740a56073b 2047 * @{
AnnaBridge 143:86740a56073b 2048 */
AnnaBridge 143:86740a56073b 2049
AnnaBridge 143:86740a56073b 2050 /*! @name PRS - Priority Registers Slave */
AnnaBridge 143:86740a56073b 2051 #define AXBS_PRS_M0_MASK (0x7U)
AnnaBridge 143:86740a56073b 2052 #define AXBS_PRS_M0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2053 #define AXBS_PRS_M0(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M0_SHIFT)) & AXBS_PRS_M0_MASK)
AnnaBridge 143:86740a56073b 2054 #define AXBS_PRS_M1_MASK (0x70U)
AnnaBridge 143:86740a56073b 2055 #define AXBS_PRS_M1_SHIFT (4U)
AnnaBridge 143:86740a56073b 2056 #define AXBS_PRS_M1(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M1_SHIFT)) & AXBS_PRS_M1_MASK)
AnnaBridge 143:86740a56073b 2057 #define AXBS_PRS_M2_MASK (0x700U)
AnnaBridge 143:86740a56073b 2058 #define AXBS_PRS_M2_SHIFT (8U)
AnnaBridge 143:86740a56073b 2059 #define AXBS_PRS_M2(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M2_SHIFT)) & AXBS_PRS_M2_MASK)
AnnaBridge 143:86740a56073b 2060 #define AXBS_PRS_M4_MASK (0x70000U)
AnnaBridge 143:86740a56073b 2061 #define AXBS_PRS_M4_SHIFT (16U)
AnnaBridge 143:86740a56073b 2062 #define AXBS_PRS_M4(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M4_SHIFT)) & AXBS_PRS_M4_MASK)
AnnaBridge 143:86740a56073b 2063 #define AXBS_PRS_M5_MASK (0x700000U)
AnnaBridge 143:86740a56073b 2064 #define AXBS_PRS_M5_SHIFT (20U)
AnnaBridge 143:86740a56073b 2065 #define AXBS_PRS_M5(x) (((uint32_t)(((uint32_t)(x)) << AXBS_PRS_M5_SHIFT)) & AXBS_PRS_M5_MASK)
AnnaBridge 143:86740a56073b 2066
AnnaBridge 143:86740a56073b 2067 /* The count of AXBS_PRS */
AnnaBridge 143:86740a56073b 2068 #define AXBS_PRS_COUNT (5U)
AnnaBridge 143:86740a56073b 2069
AnnaBridge 143:86740a56073b 2070 /*! @name CRS - Control Register */
AnnaBridge 143:86740a56073b 2071 #define AXBS_CRS_PARK_MASK (0x7U)
AnnaBridge 143:86740a56073b 2072 #define AXBS_CRS_PARK_SHIFT (0U)
AnnaBridge 143:86740a56073b 2073 #define AXBS_CRS_PARK(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PARK_SHIFT)) & AXBS_CRS_PARK_MASK)
AnnaBridge 143:86740a56073b 2074 #define AXBS_CRS_PCTL_MASK (0x30U)
AnnaBridge 143:86740a56073b 2075 #define AXBS_CRS_PCTL_SHIFT (4U)
AnnaBridge 143:86740a56073b 2076 #define AXBS_CRS_PCTL(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_PCTL_SHIFT)) & AXBS_CRS_PCTL_MASK)
AnnaBridge 143:86740a56073b 2077 #define AXBS_CRS_ARB_MASK (0x300U)
AnnaBridge 143:86740a56073b 2078 #define AXBS_CRS_ARB_SHIFT (8U)
AnnaBridge 143:86740a56073b 2079 #define AXBS_CRS_ARB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_ARB_SHIFT)) & AXBS_CRS_ARB_MASK)
AnnaBridge 143:86740a56073b 2080 #define AXBS_CRS_HLP_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 2081 #define AXBS_CRS_HLP_SHIFT (30U)
AnnaBridge 143:86740a56073b 2082 #define AXBS_CRS_HLP(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_HLP_SHIFT)) & AXBS_CRS_HLP_MASK)
AnnaBridge 143:86740a56073b 2083 #define AXBS_CRS_RO_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 2084 #define AXBS_CRS_RO_SHIFT (31U)
AnnaBridge 143:86740a56073b 2085 #define AXBS_CRS_RO(x) (((uint32_t)(((uint32_t)(x)) << AXBS_CRS_RO_SHIFT)) & AXBS_CRS_RO_MASK)
AnnaBridge 143:86740a56073b 2086
AnnaBridge 143:86740a56073b 2087 /* The count of AXBS_CRS */
AnnaBridge 143:86740a56073b 2088 #define AXBS_CRS_COUNT (5U)
AnnaBridge 143:86740a56073b 2089
AnnaBridge 143:86740a56073b 2090 /*! @name MGPCR0 - Master General Purpose Control Register */
AnnaBridge 143:86740a56073b 2091 #define AXBS_MGPCR0_AULB_MASK (0x7U)
AnnaBridge 143:86740a56073b 2092 #define AXBS_MGPCR0_AULB_SHIFT (0U)
AnnaBridge 143:86740a56073b 2093 #define AXBS_MGPCR0_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR0_AULB_SHIFT)) & AXBS_MGPCR0_AULB_MASK)
AnnaBridge 143:86740a56073b 2094
AnnaBridge 143:86740a56073b 2095 /*! @name MGPCR1 - Master General Purpose Control Register */
AnnaBridge 143:86740a56073b 2096 #define AXBS_MGPCR1_AULB_MASK (0x7U)
AnnaBridge 143:86740a56073b 2097 #define AXBS_MGPCR1_AULB_SHIFT (0U)
AnnaBridge 143:86740a56073b 2098 #define AXBS_MGPCR1_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR1_AULB_SHIFT)) & AXBS_MGPCR1_AULB_MASK)
AnnaBridge 143:86740a56073b 2099
AnnaBridge 143:86740a56073b 2100 /*! @name MGPCR2 - Master General Purpose Control Register */
AnnaBridge 143:86740a56073b 2101 #define AXBS_MGPCR2_AULB_MASK (0x7U)
AnnaBridge 143:86740a56073b 2102 #define AXBS_MGPCR2_AULB_SHIFT (0U)
AnnaBridge 143:86740a56073b 2103 #define AXBS_MGPCR2_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR2_AULB_SHIFT)) & AXBS_MGPCR2_AULB_MASK)
AnnaBridge 143:86740a56073b 2104
AnnaBridge 143:86740a56073b 2105 /*! @name MGPCR4 - Master General Purpose Control Register */
AnnaBridge 143:86740a56073b 2106 #define AXBS_MGPCR4_AULB_MASK (0x7U)
AnnaBridge 143:86740a56073b 2107 #define AXBS_MGPCR4_AULB_SHIFT (0U)
AnnaBridge 143:86740a56073b 2108 #define AXBS_MGPCR4_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR4_AULB_SHIFT)) & AXBS_MGPCR4_AULB_MASK)
AnnaBridge 143:86740a56073b 2109
AnnaBridge 143:86740a56073b 2110 /*! @name MGPCR5 - Master General Purpose Control Register */
AnnaBridge 143:86740a56073b 2111 #define AXBS_MGPCR5_AULB_MASK (0x7U)
AnnaBridge 143:86740a56073b 2112 #define AXBS_MGPCR5_AULB_SHIFT (0U)
AnnaBridge 143:86740a56073b 2113 #define AXBS_MGPCR5_AULB(x) (((uint32_t)(((uint32_t)(x)) << AXBS_MGPCR5_AULB_SHIFT)) & AXBS_MGPCR5_AULB_MASK)
AnnaBridge 143:86740a56073b 2114
AnnaBridge 143:86740a56073b 2115
AnnaBridge 143:86740a56073b 2116 /*!
AnnaBridge 143:86740a56073b 2117 * @}
AnnaBridge 143:86740a56073b 2118 */ /* end of group AXBS_Register_Masks */
AnnaBridge 143:86740a56073b 2119
AnnaBridge 143:86740a56073b 2120
AnnaBridge 143:86740a56073b 2121 /* AXBS - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 2122 /** Peripheral AXBS base address */
AnnaBridge 143:86740a56073b 2123 #define AXBS_BASE (0x40004000u)
AnnaBridge 143:86740a56073b 2124 /** Peripheral AXBS base pointer */
AnnaBridge 143:86740a56073b 2125 #define AXBS ((AXBS_Type *)AXBS_BASE)
AnnaBridge 143:86740a56073b 2126 /** Array initializer of AXBS peripheral base addresses */
AnnaBridge 143:86740a56073b 2127 #define AXBS_BASE_ADDRS { AXBS_BASE }
AnnaBridge 143:86740a56073b 2128 /** Array initializer of AXBS peripheral base pointers */
AnnaBridge 143:86740a56073b 2129 #define AXBS_BASE_PTRS { AXBS }
AnnaBridge 143:86740a56073b 2130
AnnaBridge 143:86740a56073b 2131 /*!
AnnaBridge 143:86740a56073b 2132 * @}
AnnaBridge 143:86740a56073b 2133 */ /* end of group AXBS_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 2134
AnnaBridge 143:86740a56073b 2135
AnnaBridge 143:86740a56073b 2136 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 2137 -- CAN Peripheral Access Layer
AnnaBridge 143:86740a56073b 2138 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 2139
AnnaBridge 143:86740a56073b 2140 /*!
AnnaBridge 143:86740a56073b 2141 * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
AnnaBridge 143:86740a56073b 2142 * @{
AnnaBridge 143:86740a56073b 2143 */
AnnaBridge 143:86740a56073b 2144
AnnaBridge 143:86740a56073b 2145 /** CAN - Register Layout Typedef */
AnnaBridge 143:86740a56073b 2146 typedef struct {
AnnaBridge 143:86740a56073b 2147 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 2148 __IO uint32_t CTRL1; /**< Control 1 register, offset: 0x4 */
AnnaBridge 143:86740a56073b 2149 __IO uint32_t TIMER; /**< Free Running Timer, offset: 0x8 */
AnnaBridge 143:86740a56073b 2150 uint8_t RESERVED_0[4];
AnnaBridge 143:86740a56073b 2151 __IO uint32_t RXMGMASK; /**< Rx Mailboxes Global Mask Register, offset: 0x10 */
AnnaBridge 143:86740a56073b 2152 __IO uint32_t RX14MASK; /**< Rx 14 Mask register, offset: 0x14 */
AnnaBridge 143:86740a56073b 2153 __IO uint32_t RX15MASK; /**< Rx 15 Mask register, offset: 0x18 */
AnnaBridge 143:86740a56073b 2154 __IO uint32_t ECR; /**< Error Counter, offset: 0x1C */
AnnaBridge 143:86740a56073b 2155 __IO uint32_t ESR1; /**< Error and Status 1 register, offset: 0x20 */
AnnaBridge 143:86740a56073b 2156 uint8_t RESERVED_1[4];
AnnaBridge 143:86740a56073b 2157 __IO uint32_t IMASK1; /**< Interrupt Masks 1 register, offset: 0x28 */
AnnaBridge 143:86740a56073b 2158 uint8_t RESERVED_2[4];
AnnaBridge 143:86740a56073b 2159 __IO uint32_t IFLAG1; /**< Interrupt Flags 1 register, offset: 0x30 */
AnnaBridge 143:86740a56073b 2160 __IO uint32_t CTRL2; /**< Control 2 register, offset: 0x34 */
AnnaBridge 143:86740a56073b 2161 __I uint32_t ESR2; /**< Error and Status 2 register, offset: 0x38 */
AnnaBridge 143:86740a56073b 2162 uint8_t RESERVED_3[8];
AnnaBridge 143:86740a56073b 2163 __I uint32_t CRCR; /**< CRC Register, offset: 0x44 */
AnnaBridge 143:86740a56073b 2164 __IO uint32_t RXFGMASK; /**< Rx FIFO Global Mask register, offset: 0x48 */
AnnaBridge 143:86740a56073b 2165 __I uint32_t RXFIR; /**< Rx FIFO Information Register, offset: 0x4C */
AnnaBridge 143:86740a56073b 2166 uint8_t RESERVED_4[48];
AnnaBridge 143:86740a56073b 2167 struct { /* offset: 0x80, array step: 0x10 */
AnnaBridge 143:86740a56073b 2168 __IO uint32_t CS; /**< Message Buffer 0 CS Register..Message Buffer 15 CS Register, array offset: 0x80, array step: 0x10 */
AnnaBridge 143:86740a56073b 2169 __IO uint32_t ID; /**< Message Buffer 0 ID Register..Message Buffer 15 ID Register, array offset: 0x84, array step: 0x10 */
AnnaBridge 143:86740a56073b 2170 __IO uint32_t WORD0; /**< Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register, array offset: 0x88, array step: 0x10 */
AnnaBridge 143:86740a56073b 2171 __IO uint32_t WORD1; /**< Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register, array offset: 0x8C, array step: 0x10 */
AnnaBridge 143:86740a56073b 2172 } MB[16];
AnnaBridge 143:86740a56073b 2173 uint8_t RESERVED_5[1792];
AnnaBridge 143:86740a56073b 2174 __IO uint32_t RXIMR[16]; /**< Rx Individual Mask Registers, array offset: 0x880, array step: 0x4 */
AnnaBridge 143:86740a56073b 2175 } CAN_Type;
AnnaBridge 143:86740a56073b 2176
AnnaBridge 143:86740a56073b 2177 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 2178 -- CAN Register Masks
AnnaBridge 143:86740a56073b 2179 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 2180
AnnaBridge 143:86740a56073b 2181 /*!
AnnaBridge 143:86740a56073b 2182 * @addtogroup CAN_Register_Masks CAN Register Masks
AnnaBridge 143:86740a56073b 2183 * @{
AnnaBridge 143:86740a56073b 2184 */
AnnaBridge 143:86740a56073b 2185
AnnaBridge 143:86740a56073b 2186 /*! @name MCR - Module Configuration Register */
AnnaBridge 143:86740a56073b 2187 #define CAN_MCR_MAXMB_MASK (0x7FU)
AnnaBridge 143:86740a56073b 2188 #define CAN_MCR_MAXMB_SHIFT (0U)
AnnaBridge 143:86740a56073b 2189 #define CAN_MCR_MAXMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MAXMB_SHIFT)) & CAN_MCR_MAXMB_MASK)
AnnaBridge 143:86740a56073b 2190 #define CAN_MCR_IDAM_MASK (0x300U)
AnnaBridge 143:86740a56073b 2191 #define CAN_MCR_IDAM_SHIFT (8U)
AnnaBridge 143:86740a56073b 2192 #define CAN_MCR_IDAM(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IDAM_SHIFT)) & CAN_MCR_IDAM_MASK)
AnnaBridge 143:86740a56073b 2193 #define CAN_MCR_AEN_MASK (0x1000U)
AnnaBridge 143:86740a56073b 2194 #define CAN_MCR_AEN_SHIFT (12U)
AnnaBridge 143:86740a56073b 2195 #define CAN_MCR_AEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_AEN_SHIFT)) & CAN_MCR_AEN_MASK)
AnnaBridge 143:86740a56073b 2196 #define CAN_MCR_LPRIOEN_MASK (0x2000U)
AnnaBridge 143:86740a56073b 2197 #define CAN_MCR_LPRIOEN_SHIFT (13U)
AnnaBridge 143:86740a56073b 2198 #define CAN_MCR_LPRIOEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPRIOEN_SHIFT)) & CAN_MCR_LPRIOEN_MASK)
AnnaBridge 143:86740a56073b 2199 #define CAN_MCR_IRMQ_MASK (0x10000U)
AnnaBridge 143:86740a56073b 2200 #define CAN_MCR_IRMQ_SHIFT (16U)
AnnaBridge 143:86740a56073b 2201 #define CAN_MCR_IRMQ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_IRMQ_SHIFT)) & CAN_MCR_IRMQ_MASK)
AnnaBridge 143:86740a56073b 2202 #define CAN_MCR_SRXDIS_MASK (0x20000U)
AnnaBridge 143:86740a56073b 2203 #define CAN_MCR_SRXDIS_SHIFT (17U)
AnnaBridge 143:86740a56073b 2204 #define CAN_MCR_SRXDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SRXDIS_SHIFT)) & CAN_MCR_SRXDIS_MASK)
AnnaBridge 143:86740a56073b 2205 #define CAN_MCR_WAKSRC_MASK (0x80000U)
AnnaBridge 143:86740a56073b 2206 #define CAN_MCR_WAKSRC_SHIFT (19U)
AnnaBridge 143:86740a56073b 2207 #define CAN_MCR_WAKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKSRC_SHIFT)) & CAN_MCR_WAKSRC_MASK)
AnnaBridge 143:86740a56073b 2208 #define CAN_MCR_LPMACK_MASK (0x100000U)
AnnaBridge 143:86740a56073b 2209 #define CAN_MCR_LPMACK_SHIFT (20U)
AnnaBridge 143:86740a56073b 2210 #define CAN_MCR_LPMACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_LPMACK_SHIFT)) & CAN_MCR_LPMACK_MASK)
AnnaBridge 143:86740a56073b 2211 #define CAN_MCR_WRNEN_MASK (0x200000U)
AnnaBridge 143:86740a56073b 2212 #define CAN_MCR_WRNEN_SHIFT (21U)
AnnaBridge 143:86740a56073b 2213 #define CAN_MCR_WRNEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WRNEN_SHIFT)) & CAN_MCR_WRNEN_MASK)
AnnaBridge 143:86740a56073b 2214 #define CAN_MCR_SLFWAK_MASK (0x400000U)
AnnaBridge 143:86740a56073b 2215 #define CAN_MCR_SLFWAK_SHIFT (22U)
AnnaBridge 143:86740a56073b 2216 #define CAN_MCR_SLFWAK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SLFWAK_SHIFT)) & CAN_MCR_SLFWAK_MASK)
AnnaBridge 143:86740a56073b 2217 #define CAN_MCR_SUPV_MASK (0x800000U)
AnnaBridge 143:86740a56073b 2218 #define CAN_MCR_SUPV_SHIFT (23U)
AnnaBridge 143:86740a56073b 2219 #define CAN_MCR_SUPV(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SUPV_SHIFT)) & CAN_MCR_SUPV_MASK)
AnnaBridge 143:86740a56073b 2220 #define CAN_MCR_FRZACK_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 2221 #define CAN_MCR_FRZACK_SHIFT (24U)
AnnaBridge 143:86740a56073b 2222 #define CAN_MCR_FRZACK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZACK_SHIFT)) & CAN_MCR_FRZACK_MASK)
AnnaBridge 143:86740a56073b 2223 #define CAN_MCR_SOFTRST_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 2224 #define CAN_MCR_SOFTRST_SHIFT (25U)
AnnaBridge 143:86740a56073b 2225 #define CAN_MCR_SOFTRST(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_SOFTRST_SHIFT)) & CAN_MCR_SOFTRST_MASK)
AnnaBridge 143:86740a56073b 2226 #define CAN_MCR_WAKMSK_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 2227 #define CAN_MCR_WAKMSK_SHIFT (26U)
AnnaBridge 143:86740a56073b 2228 #define CAN_MCR_WAKMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_WAKMSK_SHIFT)) & CAN_MCR_WAKMSK_MASK)
AnnaBridge 143:86740a56073b 2229 #define CAN_MCR_NOTRDY_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 2230 #define CAN_MCR_NOTRDY_SHIFT (27U)
AnnaBridge 143:86740a56073b 2231 #define CAN_MCR_NOTRDY(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_NOTRDY_SHIFT)) & CAN_MCR_NOTRDY_MASK)
AnnaBridge 143:86740a56073b 2232 #define CAN_MCR_HALT_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 2233 #define CAN_MCR_HALT_SHIFT (28U)
AnnaBridge 143:86740a56073b 2234 #define CAN_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_HALT_SHIFT)) & CAN_MCR_HALT_MASK)
AnnaBridge 143:86740a56073b 2235 #define CAN_MCR_RFEN_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 2236 #define CAN_MCR_RFEN_SHIFT (29U)
AnnaBridge 143:86740a56073b 2237 #define CAN_MCR_RFEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_RFEN_SHIFT)) & CAN_MCR_RFEN_MASK)
AnnaBridge 143:86740a56073b 2238 #define CAN_MCR_FRZ_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 2239 #define CAN_MCR_FRZ_SHIFT (30U)
AnnaBridge 143:86740a56073b 2240 #define CAN_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_FRZ_SHIFT)) & CAN_MCR_FRZ_MASK)
AnnaBridge 143:86740a56073b 2241 #define CAN_MCR_MDIS_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 2242 #define CAN_MCR_MDIS_SHIFT (31U)
AnnaBridge 143:86740a56073b 2243 #define CAN_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << CAN_MCR_MDIS_SHIFT)) & CAN_MCR_MDIS_MASK)
AnnaBridge 143:86740a56073b 2244
AnnaBridge 143:86740a56073b 2245 /*! @name CTRL1 - Control 1 register */
AnnaBridge 143:86740a56073b 2246 #define CAN_CTRL1_PROPSEG_MASK (0x7U)
AnnaBridge 143:86740a56073b 2247 #define CAN_CTRL1_PROPSEG_SHIFT (0U)
AnnaBridge 143:86740a56073b 2248 #define CAN_CTRL1_PROPSEG(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PROPSEG_SHIFT)) & CAN_CTRL1_PROPSEG_MASK)
AnnaBridge 143:86740a56073b 2249 #define CAN_CTRL1_LOM_MASK (0x8U)
AnnaBridge 143:86740a56073b 2250 #define CAN_CTRL1_LOM_SHIFT (3U)
AnnaBridge 143:86740a56073b 2251 #define CAN_CTRL1_LOM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LOM_SHIFT)) & CAN_CTRL1_LOM_MASK)
AnnaBridge 143:86740a56073b 2252 #define CAN_CTRL1_LBUF_MASK (0x10U)
AnnaBridge 143:86740a56073b 2253 #define CAN_CTRL1_LBUF_SHIFT (4U)
AnnaBridge 143:86740a56073b 2254 #define CAN_CTRL1_LBUF(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LBUF_SHIFT)) & CAN_CTRL1_LBUF_MASK)
AnnaBridge 143:86740a56073b 2255 #define CAN_CTRL1_TSYN_MASK (0x20U)
AnnaBridge 143:86740a56073b 2256 #define CAN_CTRL1_TSYN_SHIFT (5U)
AnnaBridge 143:86740a56073b 2257 #define CAN_CTRL1_TSYN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TSYN_SHIFT)) & CAN_CTRL1_TSYN_MASK)
AnnaBridge 143:86740a56073b 2258 #define CAN_CTRL1_BOFFREC_MASK (0x40U)
AnnaBridge 143:86740a56073b 2259 #define CAN_CTRL1_BOFFREC_SHIFT (6U)
AnnaBridge 143:86740a56073b 2260 #define CAN_CTRL1_BOFFREC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFREC_SHIFT)) & CAN_CTRL1_BOFFREC_MASK)
AnnaBridge 143:86740a56073b 2261 #define CAN_CTRL1_SMP_MASK (0x80U)
AnnaBridge 143:86740a56073b 2262 #define CAN_CTRL1_SMP_SHIFT (7U)
AnnaBridge 143:86740a56073b 2263 #define CAN_CTRL1_SMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_SMP_SHIFT)) & CAN_CTRL1_SMP_MASK)
AnnaBridge 143:86740a56073b 2264 #define CAN_CTRL1_RWRNMSK_MASK (0x400U)
AnnaBridge 143:86740a56073b 2265 #define CAN_CTRL1_RWRNMSK_SHIFT (10U)
AnnaBridge 143:86740a56073b 2266 #define CAN_CTRL1_RWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RWRNMSK_SHIFT)) & CAN_CTRL1_RWRNMSK_MASK)
AnnaBridge 143:86740a56073b 2267 #define CAN_CTRL1_TWRNMSK_MASK (0x800U)
AnnaBridge 143:86740a56073b 2268 #define CAN_CTRL1_TWRNMSK_SHIFT (11U)
AnnaBridge 143:86740a56073b 2269 #define CAN_CTRL1_TWRNMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_TWRNMSK_SHIFT)) & CAN_CTRL1_TWRNMSK_MASK)
AnnaBridge 143:86740a56073b 2270 #define CAN_CTRL1_LPB_MASK (0x1000U)
AnnaBridge 143:86740a56073b 2271 #define CAN_CTRL1_LPB_SHIFT (12U)
AnnaBridge 143:86740a56073b 2272 #define CAN_CTRL1_LPB(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_LPB_SHIFT)) & CAN_CTRL1_LPB_MASK)
AnnaBridge 143:86740a56073b 2273 #define CAN_CTRL1_CLKSRC_MASK (0x2000U)
AnnaBridge 143:86740a56073b 2274 #define CAN_CTRL1_CLKSRC_SHIFT (13U)
AnnaBridge 143:86740a56073b 2275 #define CAN_CTRL1_CLKSRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_CLKSRC_SHIFT)) & CAN_CTRL1_CLKSRC_MASK)
AnnaBridge 143:86740a56073b 2276 #define CAN_CTRL1_ERRMSK_MASK (0x4000U)
AnnaBridge 143:86740a56073b 2277 #define CAN_CTRL1_ERRMSK_SHIFT (14U)
AnnaBridge 143:86740a56073b 2278 #define CAN_CTRL1_ERRMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_ERRMSK_SHIFT)) & CAN_CTRL1_ERRMSK_MASK)
AnnaBridge 143:86740a56073b 2279 #define CAN_CTRL1_BOFFMSK_MASK (0x8000U)
AnnaBridge 143:86740a56073b 2280 #define CAN_CTRL1_BOFFMSK_SHIFT (15U)
AnnaBridge 143:86740a56073b 2281 #define CAN_CTRL1_BOFFMSK(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_BOFFMSK_SHIFT)) & CAN_CTRL1_BOFFMSK_MASK)
AnnaBridge 143:86740a56073b 2282 #define CAN_CTRL1_PSEG2_MASK (0x70000U)
AnnaBridge 143:86740a56073b 2283 #define CAN_CTRL1_PSEG2_SHIFT (16U)
AnnaBridge 143:86740a56073b 2284 #define CAN_CTRL1_PSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG2_SHIFT)) & CAN_CTRL1_PSEG2_MASK)
AnnaBridge 143:86740a56073b 2285 #define CAN_CTRL1_PSEG1_MASK (0x380000U)
AnnaBridge 143:86740a56073b 2286 #define CAN_CTRL1_PSEG1_SHIFT (19U)
AnnaBridge 143:86740a56073b 2287 #define CAN_CTRL1_PSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PSEG1_SHIFT)) & CAN_CTRL1_PSEG1_MASK)
AnnaBridge 143:86740a56073b 2288 #define CAN_CTRL1_RJW_MASK (0xC00000U)
AnnaBridge 143:86740a56073b 2289 #define CAN_CTRL1_RJW_SHIFT (22U)
AnnaBridge 143:86740a56073b 2290 #define CAN_CTRL1_RJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_RJW_SHIFT)) & CAN_CTRL1_RJW_MASK)
AnnaBridge 143:86740a56073b 2291 #define CAN_CTRL1_PRESDIV_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 2292 #define CAN_CTRL1_PRESDIV_SHIFT (24U)
AnnaBridge 143:86740a56073b 2293 #define CAN_CTRL1_PRESDIV(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL1_PRESDIV_SHIFT)) & CAN_CTRL1_PRESDIV_MASK)
AnnaBridge 143:86740a56073b 2294
AnnaBridge 143:86740a56073b 2295 /*! @name TIMER - Free Running Timer */
AnnaBridge 143:86740a56073b 2296 #define CAN_TIMER_TIMER_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 2297 #define CAN_TIMER_TIMER_SHIFT (0U)
AnnaBridge 143:86740a56073b 2298 #define CAN_TIMER_TIMER(x) (((uint32_t)(((uint32_t)(x)) << CAN_TIMER_TIMER_SHIFT)) & CAN_TIMER_TIMER_MASK)
AnnaBridge 143:86740a56073b 2299
AnnaBridge 143:86740a56073b 2300 /*! @name RXMGMASK - Rx Mailboxes Global Mask Register */
AnnaBridge 143:86740a56073b 2301 #define CAN_RXMGMASK_MG_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2302 #define CAN_RXMGMASK_MG_SHIFT (0U)
AnnaBridge 143:86740a56073b 2303 #define CAN_RXMGMASK_MG(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXMGMASK_MG_SHIFT)) & CAN_RXMGMASK_MG_MASK)
AnnaBridge 143:86740a56073b 2304
AnnaBridge 143:86740a56073b 2305 /*! @name RX14MASK - Rx 14 Mask register */
AnnaBridge 143:86740a56073b 2306 #define CAN_RX14MASK_RX14M_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2307 #define CAN_RX14MASK_RX14M_SHIFT (0U)
AnnaBridge 143:86740a56073b 2308 #define CAN_RX14MASK_RX14M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX14MASK_RX14M_SHIFT)) & CAN_RX14MASK_RX14M_MASK)
AnnaBridge 143:86740a56073b 2309
AnnaBridge 143:86740a56073b 2310 /*! @name RX15MASK - Rx 15 Mask register */
AnnaBridge 143:86740a56073b 2311 #define CAN_RX15MASK_RX15M_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2312 #define CAN_RX15MASK_RX15M_SHIFT (0U)
AnnaBridge 143:86740a56073b 2313 #define CAN_RX15MASK_RX15M(x) (((uint32_t)(((uint32_t)(x)) << CAN_RX15MASK_RX15M_SHIFT)) & CAN_RX15MASK_RX15M_MASK)
AnnaBridge 143:86740a56073b 2314
AnnaBridge 143:86740a56073b 2315 /*! @name ECR - Error Counter */
AnnaBridge 143:86740a56073b 2316 #define CAN_ECR_TXERRCNT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 2317 #define CAN_ECR_TXERRCNT_SHIFT (0U)
AnnaBridge 143:86740a56073b 2318 #define CAN_ECR_TXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TXERRCNT_SHIFT)) & CAN_ECR_TXERRCNT_MASK)
AnnaBridge 143:86740a56073b 2319 #define CAN_ECR_RXERRCNT_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 2320 #define CAN_ECR_RXERRCNT_SHIFT (8U)
AnnaBridge 143:86740a56073b 2321 #define CAN_ECR_RXERRCNT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RXERRCNT_SHIFT)) & CAN_ECR_RXERRCNT_MASK)
AnnaBridge 143:86740a56073b 2322
AnnaBridge 143:86740a56073b 2323 /*! @name ESR1 - Error and Status 1 register */
AnnaBridge 143:86740a56073b 2324 #define CAN_ESR1_WAKINT_MASK (0x1U)
AnnaBridge 143:86740a56073b 2325 #define CAN_ESR1_WAKINT_SHIFT (0U)
AnnaBridge 143:86740a56073b 2326 #define CAN_ESR1_WAKINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_WAKINT_SHIFT)) & CAN_ESR1_WAKINT_MASK)
AnnaBridge 143:86740a56073b 2327 #define CAN_ESR1_ERRINT_MASK (0x2U)
AnnaBridge 143:86740a56073b 2328 #define CAN_ESR1_ERRINT_SHIFT (1U)
AnnaBridge 143:86740a56073b 2329 #define CAN_ESR1_ERRINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ERRINT_SHIFT)) & CAN_ESR1_ERRINT_MASK)
AnnaBridge 143:86740a56073b 2330 #define CAN_ESR1_BOFFINT_MASK (0x4U)
AnnaBridge 143:86740a56073b 2331 #define CAN_ESR1_BOFFINT_SHIFT (2U)
AnnaBridge 143:86740a56073b 2332 #define CAN_ESR1_BOFFINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BOFFINT_SHIFT)) & CAN_ESR1_BOFFINT_MASK)
AnnaBridge 143:86740a56073b 2333 #define CAN_ESR1_RX_MASK (0x8U)
AnnaBridge 143:86740a56073b 2334 #define CAN_ESR1_RX_SHIFT (3U)
AnnaBridge 143:86740a56073b 2335 #define CAN_ESR1_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RX_SHIFT)) & CAN_ESR1_RX_MASK)
AnnaBridge 143:86740a56073b 2336 #define CAN_ESR1_FLTCONF_MASK (0x30U)
AnnaBridge 143:86740a56073b 2337 #define CAN_ESR1_FLTCONF_SHIFT (4U)
AnnaBridge 143:86740a56073b 2338 #define CAN_ESR1_FLTCONF(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FLTCONF_SHIFT)) & CAN_ESR1_FLTCONF_MASK)
AnnaBridge 143:86740a56073b 2339 #define CAN_ESR1_TX_MASK (0x40U)
AnnaBridge 143:86740a56073b 2340 #define CAN_ESR1_TX_SHIFT (6U)
AnnaBridge 143:86740a56073b 2341 #define CAN_ESR1_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TX_SHIFT)) & CAN_ESR1_TX_MASK)
AnnaBridge 143:86740a56073b 2342 #define CAN_ESR1_IDLE_MASK (0x80U)
AnnaBridge 143:86740a56073b 2343 #define CAN_ESR1_IDLE_SHIFT (7U)
AnnaBridge 143:86740a56073b 2344 #define CAN_ESR1_IDLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_IDLE_SHIFT)) & CAN_ESR1_IDLE_MASK)
AnnaBridge 143:86740a56073b 2345 #define CAN_ESR1_RXWRN_MASK (0x100U)
AnnaBridge 143:86740a56073b 2346 #define CAN_ESR1_RXWRN_SHIFT (8U)
AnnaBridge 143:86740a56073b 2347 #define CAN_ESR1_RXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RXWRN_SHIFT)) & CAN_ESR1_RXWRN_MASK)
AnnaBridge 143:86740a56073b 2348 #define CAN_ESR1_TXWRN_MASK (0x200U)
AnnaBridge 143:86740a56073b 2349 #define CAN_ESR1_TXWRN_SHIFT (9U)
AnnaBridge 143:86740a56073b 2350 #define CAN_ESR1_TXWRN(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TXWRN_SHIFT)) & CAN_ESR1_TXWRN_MASK)
AnnaBridge 143:86740a56073b 2351 #define CAN_ESR1_STFERR_MASK (0x400U)
AnnaBridge 143:86740a56073b 2352 #define CAN_ESR1_STFERR_SHIFT (10U)
AnnaBridge 143:86740a56073b 2353 #define CAN_ESR1_STFERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_STFERR_SHIFT)) & CAN_ESR1_STFERR_MASK)
AnnaBridge 143:86740a56073b 2354 #define CAN_ESR1_FRMERR_MASK (0x800U)
AnnaBridge 143:86740a56073b 2355 #define CAN_ESR1_FRMERR_SHIFT (11U)
AnnaBridge 143:86740a56073b 2356 #define CAN_ESR1_FRMERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_FRMERR_SHIFT)) & CAN_ESR1_FRMERR_MASK)
AnnaBridge 143:86740a56073b 2357 #define CAN_ESR1_CRCERR_MASK (0x1000U)
AnnaBridge 143:86740a56073b 2358 #define CAN_ESR1_CRCERR_SHIFT (12U)
AnnaBridge 143:86740a56073b 2359 #define CAN_ESR1_CRCERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_CRCERR_SHIFT)) & CAN_ESR1_CRCERR_MASK)
AnnaBridge 143:86740a56073b 2360 #define CAN_ESR1_ACKERR_MASK (0x2000U)
AnnaBridge 143:86740a56073b 2361 #define CAN_ESR1_ACKERR_SHIFT (13U)
AnnaBridge 143:86740a56073b 2362 #define CAN_ESR1_ACKERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_ACKERR_SHIFT)) & CAN_ESR1_ACKERR_MASK)
AnnaBridge 143:86740a56073b 2363 #define CAN_ESR1_BIT0ERR_MASK (0x4000U)
AnnaBridge 143:86740a56073b 2364 #define CAN_ESR1_BIT0ERR_SHIFT (14U)
AnnaBridge 143:86740a56073b 2365 #define CAN_ESR1_BIT0ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT0ERR_SHIFT)) & CAN_ESR1_BIT0ERR_MASK)
AnnaBridge 143:86740a56073b 2366 #define CAN_ESR1_BIT1ERR_MASK (0x8000U)
AnnaBridge 143:86740a56073b 2367 #define CAN_ESR1_BIT1ERR_SHIFT (15U)
AnnaBridge 143:86740a56073b 2368 #define CAN_ESR1_BIT1ERR(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_BIT1ERR_SHIFT)) & CAN_ESR1_BIT1ERR_MASK)
AnnaBridge 143:86740a56073b 2369 #define CAN_ESR1_RWRNINT_MASK (0x10000U)
AnnaBridge 143:86740a56073b 2370 #define CAN_ESR1_RWRNINT_SHIFT (16U)
AnnaBridge 143:86740a56073b 2371 #define CAN_ESR1_RWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_RWRNINT_SHIFT)) & CAN_ESR1_RWRNINT_MASK)
AnnaBridge 143:86740a56073b 2372 #define CAN_ESR1_TWRNINT_MASK (0x20000U)
AnnaBridge 143:86740a56073b 2373 #define CAN_ESR1_TWRNINT_SHIFT (17U)
AnnaBridge 143:86740a56073b 2374 #define CAN_ESR1_TWRNINT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_TWRNINT_SHIFT)) & CAN_ESR1_TWRNINT_MASK)
AnnaBridge 143:86740a56073b 2375 #define CAN_ESR1_SYNCH_MASK (0x40000U)
AnnaBridge 143:86740a56073b 2376 #define CAN_ESR1_SYNCH_SHIFT (18U)
AnnaBridge 143:86740a56073b 2377 #define CAN_ESR1_SYNCH(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR1_SYNCH_SHIFT)) & CAN_ESR1_SYNCH_MASK)
AnnaBridge 143:86740a56073b 2378
AnnaBridge 143:86740a56073b 2379 /*! @name IMASK1 - Interrupt Masks 1 register */
AnnaBridge 143:86740a56073b 2380 #define CAN_IMASK1_BUFLM_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2381 #define CAN_IMASK1_BUFLM_SHIFT (0U)
AnnaBridge 143:86740a56073b 2382 #define CAN_IMASK1_BUFLM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IMASK1_BUFLM_SHIFT)) & CAN_IMASK1_BUFLM_MASK)
AnnaBridge 143:86740a56073b 2383
AnnaBridge 143:86740a56073b 2384 /*! @name IFLAG1 - Interrupt Flags 1 register */
AnnaBridge 143:86740a56073b 2385 #define CAN_IFLAG1_BUF0I_MASK (0x1U)
AnnaBridge 143:86740a56073b 2386 #define CAN_IFLAG1_BUF0I_SHIFT (0U)
AnnaBridge 143:86740a56073b 2387 #define CAN_IFLAG1_BUF0I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF0I_SHIFT)) & CAN_IFLAG1_BUF0I_MASK)
AnnaBridge 143:86740a56073b 2388 #define CAN_IFLAG1_BUF4TO1I_MASK (0x1EU)
AnnaBridge 143:86740a56073b 2389 #define CAN_IFLAG1_BUF4TO1I_SHIFT (1U)
AnnaBridge 143:86740a56073b 2390 #define CAN_IFLAG1_BUF4TO1I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF4TO1I_SHIFT)) & CAN_IFLAG1_BUF4TO1I_MASK)
AnnaBridge 143:86740a56073b 2391 #define CAN_IFLAG1_BUF5I_MASK (0x20U)
AnnaBridge 143:86740a56073b 2392 #define CAN_IFLAG1_BUF5I_SHIFT (5U)
AnnaBridge 143:86740a56073b 2393 #define CAN_IFLAG1_BUF5I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF5I_SHIFT)) & CAN_IFLAG1_BUF5I_MASK)
AnnaBridge 143:86740a56073b 2394 #define CAN_IFLAG1_BUF6I_MASK (0x40U)
AnnaBridge 143:86740a56073b 2395 #define CAN_IFLAG1_BUF6I_SHIFT (6U)
AnnaBridge 143:86740a56073b 2396 #define CAN_IFLAG1_BUF6I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF6I_SHIFT)) & CAN_IFLAG1_BUF6I_MASK)
AnnaBridge 143:86740a56073b 2397 #define CAN_IFLAG1_BUF7I_MASK (0x80U)
AnnaBridge 143:86740a56073b 2398 #define CAN_IFLAG1_BUF7I_SHIFT (7U)
AnnaBridge 143:86740a56073b 2399 #define CAN_IFLAG1_BUF7I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF7I_SHIFT)) & CAN_IFLAG1_BUF7I_MASK)
AnnaBridge 143:86740a56073b 2400 #define CAN_IFLAG1_BUF31TO8I_MASK (0xFFFFFF00U)
AnnaBridge 143:86740a56073b 2401 #define CAN_IFLAG1_BUF31TO8I_SHIFT (8U)
AnnaBridge 143:86740a56073b 2402 #define CAN_IFLAG1_BUF31TO8I(x) (((uint32_t)(((uint32_t)(x)) << CAN_IFLAG1_BUF31TO8I_SHIFT)) & CAN_IFLAG1_BUF31TO8I_MASK)
AnnaBridge 143:86740a56073b 2403
AnnaBridge 143:86740a56073b 2404 /*! @name CTRL2 - Control 2 register */
AnnaBridge 143:86740a56073b 2405 #define CAN_CTRL2_EACEN_MASK (0x10000U)
AnnaBridge 143:86740a56073b 2406 #define CAN_CTRL2_EACEN_SHIFT (16U)
AnnaBridge 143:86740a56073b 2407 #define CAN_CTRL2_EACEN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_EACEN_SHIFT)) & CAN_CTRL2_EACEN_MASK)
AnnaBridge 143:86740a56073b 2408 #define CAN_CTRL2_RRS_MASK (0x20000U)
AnnaBridge 143:86740a56073b 2409 #define CAN_CTRL2_RRS_SHIFT (17U)
AnnaBridge 143:86740a56073b 2410 #define CAN_CTRL2_RRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RRS_SHIFT)) & CAN_CTRL2_RRS_MASK)
AnnaBridge 143:86740a56073b 2411 #define CAN_CTRL2_MRP_MASK (0x40000U)
AnnaBridge 143:86740a56073b 2412 #define CAN_CTRL2_MRP_SHIFT (18U)
AnnaBridge 143:86740a56073b 2413 #define CAN_CTRL2_MRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_MRP_SHIFT)) & CAN_CTRL2_MRP_MASK)
AnnaBridge 143:86740a56073b 2414 #define CAN_CTRL2_TASD_MASK (0xF80000U)
AnnaBridge 143:86740a56073b 2415 #define CAN_CTRL2_TASD_SHIFT (19U)
AnnaBridge 143:86740a56073b 2416 #define CAN_CTRL2_TASD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_TASD_SHIFT)) & CAN_CTRL2_TASD_MASK)
AnnaBridge 143:86740a56073b 2417 #define CAN_CTRL2_RFFN_MASK (0xF000000U)
AnnaBridge 143:86740a56073b 2418 #define CAN_CTRL2_RFFN_SHIFT (24U)
AnnaBridge 143:86740a56073b 2419 #define CAN_CTRL2_RFFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_RFFN_SHIFT)) & CAN_CTRL2_RFFN_MASK)
AnnaBridge 143:86740a56073b 2420 #define CAN_CTRL2_WRMFRZ_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 2421 #define CAN_CTRL2_WRMFRZ_SHIFT (28U)
AnnaBridge 143:86740a56073b 2422 #define CAN_CTRL2_WRMFRZ(x) (((uint32_t)(((uint32_t)(x)) << CAN_CTRL2_WRMFRZ_SHIFT)) & CAN_CTRL2_WRMFRZ_MASK)
AnnaBridge 143:86740a56073b 2423
AnnaBridge 143:86740a56073b 2424 /*! @name ESR2 - Error and Status 2 register */
AnnaBridge 143:86740a56073b 2425 #define CAN_ESR2_IMB_MASK (0x2000U)
AnnaBridge 143:86740a56073b 2426 #define CAN_ESR2_IMB_SHIFT (13U)
AnnaBridge 143:86740a56073b 2427 #define CAN_ESR2_IMB(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_IMB_SHIFT)) & CAN_ESR2_IMB_MASK)
AnnaBridge 143:86740a56073b 2428 #define CAN_ESR2_VPS_MASK (0x4000U)
AnnaBridge 143:86740a56073b 2429 #define CAN_ESR2_VPS_SHIFT (14U)
AnnaBridge 143:86740a56073b 2430 #define CAN_ESR2_VPS(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_VPS_SHIFT)) & CAN_ESR2_VPS_MASK)
AnnaBridge 143:86740a56073b 2431 #define CAN_ESR2_LPTM_MASK (0x7F0000U)
AnnaBridge 143:86740a56073b 2432 #define CAN_ESR2_LPTM_SHIFT (16U)
AnnaBridge 143:86740a56073b 2433 #define CAN_ESR2_LPTM(x) (((uint32_t)(((uint32_t)(x)) << CAN_ESR2_LPTM_SHIFT)) & CAN_ESR2_LPTM_MASK)
AnnaBridge 143:86740a56073b 2434
AnnaBridge 143:86740a56073b 2435 /*! @name CRCR - CRC Register */
AnnaBridge 143:86740a56073b 2436 #define CAN_CRCR_TXCRC_MASK (0x7FFFU)
AnnaBridge 143:86740a56073b 2437 #define CAN_CRCR_TXCRC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2438 #define CAN_CRCR_TXCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_TXCRC_SHIFT)) & CAN_CRCR_TXCRC_MASK)
AnnaBridge 143:86740a56073b 2439 #define CAN_CRCR_MBCRC_MASK (0x7F0000U)
AnnaBridge 143:86740a56073b 2440 #define CAN_CRCR_MBCRC_SHIFT (16U)
AnnaBridge 143:86740a56073b 2441 #define CAN_CRCR_MBCRC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CRCR_MBCRC_SHIFT)) & CAN_CRCR_MBCRC_MASK)
AnnaBridge 143:86740a56073b 2442
AnnaBridge 143:86740a56073b 2443 /*! @name RXFGMASK - Rx FIFO Global Mask register */
AnnaBridge 143:86740a56073b 2444 #define CAN_RXFGMASK_FGM_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2445 #define CAN_RXFGMASK_FGM_SHIFT (0U)
AnnaBridge 143:86740a56073b 2446 #define CAN_RXFGMASK_FGM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFGMASK_FGM_SHIFT)) & CAN_RXFGMASK_FGM_MASK)
AnnaBridge 143:86740a56073b 2447
AnnaBridge 143:86740a56073b 2448 /*! @name RXFIR - Rx FIFO Information Register */
AnnaBridge 143:86740a56073b 2449 #define CAN_RXFIR_IDHIT_MASK (0x1FFU)
AnnaBridge 143:86740a56073b 2450 #define CAN_RXFIR_IDHIT_SHIFT (0U)
AnnaBridge 143:86740a56073b 2451 #define CAN_RXFIR_IDHIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXFIR_IDHIT_SHIFT)) & CAN_RXFIR_IDHIT_MASK)
AnnaBridge 143:86740a56073b 2452
AnnaBridge 143:86740a56073b 2453 /*! @name CS - Message Buffer 0 CS Register..Message Buffer 15 CS Register */
AnnaBridge 143:86740a56073b 2454 #define CAN_CS_TIME_STAMP_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 2455 #define CAN_CS_TIME_STAMP_SHIFT (0U)
AnnaBridge 143:86740a56073b 2456 #define CAN_CS_TIME_STAMP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_TIME_STAMP_SHIFT)) & CAN_CS_TIME_STAMP_MASK)
AnnaBridge 143:86740a56073b 2457 #define CAN_CS_DLC_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 2458 #define CAN_CS_DLC_SHIFT (16U)
AnnaBridge 143:86740a56073b 2459 #define CAN_CS_DLC(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_DLC_SHIFT)) & CAN_CS_DLC_MASK)
AnnaBridge 143:86740a56073b 2460 #define CAN_CS_RTR_MASK (0x100000U)
AnnaBridge 143:86740a56073b 2461 #define CAN_CS_RTR_SHIFT (20U)
AnnaBridge 143:86740a56073b 2462 #define CAN_CS_RTR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_RTR_SHIFT)) & CAN_CS_RTR_MASK)
AnnaBridge 143:86740a56073b 2463 #define CAN_CS_IDE_MASK (0x200000U)
AnnaBridge 143:86740a56073b 2464 #define CAN_CS_IDE_SHIFT (21U)
AnnaBridge 143:86740a56073b 2465 #define CAN_CS_IDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_IDE_SHIFT)) & CAN_CS_IDE_MASK)
AnnaBridge 143:86740a56073b 2466 #define CAN_CS_SRR_MASK (0x400000U)
AnnaBridge 143:86740a56073b 2467 #define CAN_CS_SRR_SHIFT (22U)
AnnaBridge 143:86740a56073b 2468 #define CAN_CS_SRR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_SRR_SHIFT)) & CAN_CS_SRR_MASK)
AnnaBridge 143:86740a56073b 2469 #define CAN_CS_CODE_MASK (0xF000000U)
AnnaBridge 143:86740a56073b 2470 #define CAN_CS_CODE_SHIFT (24U)
AnnaBridge 143:86740a56073b 2471 #define CAN_CS_CODE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CS_CODE_SHIFT)) & CAN_CS_CODE_MASK)
AnnaBridge 143:86740a56073b 2472
AnnaBridge 143:86740a56073b 2473 /* The count of CAN_CS */
AnnaBridge 143:86740a56073b 2474 #define CAN_CS_COUNT (16U)
AnnaBridge 143:86740a56073b 2475
AnnaBridge 143:86740a56073b 2476 /*! @name ID - Message Buffer 0 ID Register..Message Buffer 15 ID Register */
AnnaBridge 143:86740a56073b 2477 #define CAN_ID_EXT_MASK (0x3FFFFU)
AnnaBridge 143:86740a56073b 2478 #define CAN_ID_EXT_SHIFT (0U)
AnnaBridge 143:86740a56073b 2479 #define CAN_ID_EXT(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_EXT_SHIFT)) & CAN_ID_EXT_MASK)
AnnaBridge 143:86740a56073b 2480 #define CAN_ID_STD_MASK (0x1FFC0000U)
AnnaBridge 143:86740a56073b 2481 #define CAN_ID_STD_SHIFT (18U)
AnnaBridge 143:86740a56073b 2482 #define CAN_ID_STD(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_STD_SHIFT)) & CAN_ID_STD_MASK)
AnnaBridge 143:86740a56073b 2483 #define CAN_ID_PRIO_MASK (0xE0000000U)
AnnaBridge 143:86740a56073b 2484 #define CAN_ID_PRIO_SHIFT (29U)
AnnaBridge 143:86740a56073b 2485 #define CAN_ID_PRIO(x) (((uint32_t)(((uint32_t)(x)) << CAN_ID_PRIO_SHIFT)) & CAN_ID_PRIO_MASK)
AnnaBridge 143:86740a56073b 2486
AnnaBridge 143:86740a56073b 2487 /* The count of CAN_ID */
AnnaBridge 143:86740a56073b 2488 #define CAN_ID_COUNT (16U)
AnnaBridge 143:86740a56073b 2489
AnnaBridge 143:86740a56073b 2490 /*! @name WORD0 - Message Buffer 0 WORD0 Register..Message Buffer 15 WORD0 Register */
AnnaBridge 143:86740a56073b 2491 #define CAN_WORD0_DATA_BYTE_3_MASK (0xFFU)
AnnaBridge 143:86740a56073b 2492 #define CAN_WORD0_DATA_BYTE_3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2493 #define CAN_WORD0_DATA_BYTE_3(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_3_SHIFT)) & CAN_WORD0_DATA_BYTE_3_MASK)
AnnaBridge 143:86740a56073b 2494 #define CAN_WORD0_DATA_BYTE_2_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 2495 #define CAN_WORD0_DATA_BYTE_2_SHIFT (8U)
AnnaBridge 143:86740a56073b 2496 #define CAN_WORD0_DATA_BYTE_2(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_2_SHIFT)) & CAN_WORD0_DATA_BYTE_2_MASK)
AnnaBridge 143:86740a56073b 2497 #define CAN_WORD0_DATA_BYTE_1_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 2498 #define CAN_WORD0_DATA_BYTE_1_SHIFT (16U)
AnnaBridge 143:86740a56073b 2499 #define CAN_WORD0_DATA_BYTE_1(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_1_SHIFT)) & CAN_WORD0_DATA_BYTE_1_MASK)
AnnaBridge 143:86740a56073b 2500 #define CAN_WORD0_DATA_BYTE_0_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 2501 #define CAN_WORD0_DATA_BYTE_0_SHIFT (24U)
AnnaBridge 143:86740a56073b 2502 #define CAN_WORD0_DATA_BYTE_0(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD0_DATA_BYTE_0_SHIFT)) & CAN_WORD0_DATA_BYTE_0_MASK)
AnnaBridge 143:86740a56073b 2503
AnnaBridge 143:86740a56073b 2504 /* The count of CAN_WORD0 */
AnnaBridge 143:86740a56073b 2505 #define CAN_WORD0_COUNT (16U)
AnnaBridge 143:86740a56073b 2506
AnnaBridge 143:86740a56073b 2507 /*! @name WORD1 - Message Buffer 0 WORD1 Register..Message Buffer 15 WORD1 Register */
AnnaBridge 143:86740a56073b 2508 #define CAN_WORD1_DATA_BYTE_7_MASK (0xFFU)
AnnaBridge 143:86740a56073b 2509 #define CAN_WORD1_DATA_BYTE_7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2510 #define CAN_WORD1_DATA_BYTE_7(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_7_SHIFT)) & CAN_WORD1_DATA_BYTE_7_MASK)
AnnaBridge 143:86740a56073b 2511 #define CAN_WORD1_DATA_BYTE_6_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 2512 #define CAN_WORD1_DATA_BYTE_6_SHIFT (8U)
AnnaBridge 143:86740a56073b 2513 #define CAN_WORD1_DATA_BYTE_6(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_6_SHIFT)) & CAN_WORD1_DATA_BYTE_6_MASK)
AnnaBridge 143:86740a56073b 2514 #define CAN_WORD1_DATA_BYTE_5_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 2515 #define CAN_WORD1_DATA_BYTE_5_SHIFT (16U)
AnnaBridge 143:86740a56073b 2516 #define CAN_WORD1_DATA_BYTE_5(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_5_SHIFT)) & CAN_WORD1_DATA_BYTE_5_MASK)
AnnaBridge 143:86740a56073b 2517 #define CAN_WORD1_DATA_BYTE_4_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 2518 #define CAN_WORD1_DATA_BYTE_4_SHIFT (24U)
AnnaBridge 143:86740a56073b 2519 #define CAN_WORD1_DATA_BYTE_4(x) (((uint32_t)(((uint32_t)(x)) << CAN_WORD1_DATA_BYTE_4_SHIFT)) & CAN_WORD1_DATA_BYTE_4_MASK)
AnnaBridge 143:86740a56073b 2520
AnnaBridge 143:86740a56073b 2521 /* The count of CAN_WORD1 */
AnnaBridge 143:86740a56073b 2522 #define CAN_WORD1_COUNT (16U)
AnnaBridge 143:86740a56073b 2523
AnnaBridge 143:86740a56073b 2524 /*! @name RXIMR - Rx Individual Mask Registers */
AnnaBridge 143:86740a56073b 2525 #define CAN_RXIMR_MI_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2526 #define CAN_RXIMR_MI_SHIFT (0U)
AnnaBridge 143:86740a56073b 2527 #define CAN_RXIMR_MI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXIMR_MI_SHIFT)) & CAN_RXIMR_MI_MASK)
AnnaBridge 143:86740a56073b 2528
AnnaBridge 143:86740a56073b 2529 /* The count of CAN_RXIMR */
AnnaBridge 143:86740a56073b 2530 #define CAN_RXIMR_COUNT (16U)
AnnaBridge 143:86740a56073b 2531
AnnaBridge 143:86740a56073b 2532
AnnaBridge 143:86740a56073b 2533 /*!
AnnaBridge 143:86740a56073b 2534 * @}
AnnaBridge 143:86740a56073b 2535 */ /* end of group CAN_Register_Masks */
AnnaBridge 143:86740a56073b 2536
AnnaBridge 143:86740a56073b 2537
AnnaBridge 143:86740a56073b 2538 /* CAN - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 2539 /** Peripheral CAN0 base address */
AnnaBridge 143:86740a56073b 2540 #define CAN0_BASE (0x40024000u)
AnnaBridge 143:86740a56073b 2541 /** Peripheral CAN0 base pointer */
AnnaBridge 143:86740a56073b 2542 #define CAN0 ((CAN_Type *)CAN0_BASE)
AnnaBridge 143:86740a56073b 2543 /** Array initializer of CAN peripheral base addresses */
AnnaBridge 143:86740a56073b 2544 #define CAN_BASE_ADDRS { CAN0_BASE }
AnnaBridge 143:86740a56073b 2545 /** Array initializer of CAN peripheral base pointers */
AnnaBridge 143:86740a56073b 2546 #define CAN_BASE_PTRS { CAN0 }
AnnaBridge 143:86740a56073b 2547 /** Interrupt vectors for the CAN peripheral type */
AnnaBridge 143:86740a56073b 2548 #define CAN_Rx_Warning_IRQS { CAN0_Rx_Warning_IRQn }
AnnaBridge 143:86740a56073b 2549 #define CAN_Tx_Warning_IRQS { CAN0_Tx_Warning_IRQn }
AnnaBridge 143:86740a56073b 2550 #define CAN_Wake_Up_IRQS { CAN0_Wake_Up_IRQn }
AnnaBridge 143:86740a56073b 2551 #define CAN_Error_IRQS { CAN0_Error_IRQn }
AnnaBridge 143:86740a56073b 2552 #define CAN_Bus_Off_IRQS { CAN0_Bus_Off_IRQn }
AnnaBridge 143:86740a56073b 2553 #define CAN_ORed_Message_buffer_IRQS { CAN0_ORed_Message_buffer_IRQn }
AnnaBridge 143:86740a56073b 2554
AnnaBridge 143:86740a56073b 2555 /*!
AnnaBridge 143:86740a56073b 2556 * @}
AnnaBridge 143:86740a56073b 2557 */ /* end of group CAN_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 2558
AnnaBridge 143:86740a56073b 2559
AnnaBridge 143:86740a56073b 2560 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 2561 -- CAU Peripheral Access Layer
AnnaBridge 143:86740a56073b 2562 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 2563
AnnaBridge 143:86740a56073b 2564 /*!
AnnaBridge 143:86740a56073b 2565 * @addtogroup CAU_Peripheral_Access_Layer CAU Peripheral Access Layer
AnnaBridge 143:86740a56073b 2566 * @{
AnnaBridge 143:86740a56073b 2567 */
AnnaBridge 143:86740a56073b 2568
AnnaBridge 143:86740a56073b 2569 /** CAU - Register Layout Typedef */
AnnaBridge 143:86740a56073b 2570 typedef struct {
AnnaBridge 143:86740a56073b 2571 __O uint32_t DIRECT[16]; /**< Direct access register 0..Direct access register 15, array offset: 0x0, array step: 0x4 */
AnnaBridge 143:86740a56073b 2572 uint8_t RESERVED_0[2048];
AnnaBridge 143:86740a56073b 2573 __O uint32_t LDR_CASR; /**< Status register - Load Register command, offset: 0x840 */
AnnaBridge 143:86740a56073b 2574 __O uint32_t LDR_CAA; /**< Accumulator register - Load Register command, offset: 0x844 */
AnnaBridge 143:86740a56073b 2575 __O uint32_t LDR_CA[9]; /**< General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command, array offset: 0x848, array step: 0x4 */
AnnaBridge 143:86740a56073b 2576 uint8_t RESERVED_1[20];
AnnaBridge 143:86740a56073b 2577 __I uint32_t STR_CASR; /**< Status register - Store Register command, offset: 0x880 */
AnnaBridge 143:86740a56073b 2578 __I uint32_t STR_CAA; /**< Accumulator register - Store Register command, offset: 0x884 */
AnnaBridge 143:86740a56073b 2579 __I uint32_t STR_CA[9]; /**< General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command, array offset: 0x888, array step: 0x4 */
AnnaBridge 143:86740a56073b 2580 uint8_t RESERVED_2[20];
AnnaBridge 143:86740a56073b 2581 __O uint32_t ADR_CASR; /**< Status register - Add Register command, offset: 0x8C0 */
AnnaBridge 143:86740a56073b 2582 __O uint32_t ADR_CAA; /**< Accumulator register - Add to register command, offset: 0x8C4 */
AnnaBridge 143:86740a56073b 2583 __O uint32_t ADR_CA[9]; /**< General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command, array offset: 0x8C8, array step: 0x4 */
AnnaBridge 143:86740a56073b 2584 uint8_t RESERVED_3[20];
AnnaBridge 143:86740a56073b 2585 __O uint32_t RADR_CASR; /**< Status register - Reverse and Add to Register command, offset: 0x900 */
AnnaBridge 143:86740a56073b 2586 __O uint32_t RADR_CAA; /**< Accumulator register - Reverse and Add to Register command, offset: 0x904 */
AnnaBridge 143:86740a56073b 2587 __O uint32_t RADR_CA[9]; /**< General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command, array offset: 0x908, array step: 0x4 */
AnnaBridge 143:86740a56073b 2588 uint8_t RESERVED_4[84];
AnnaBridge 143:86740a56073b 2589 __O uint32_t XOR_CASR; /**< Status register - Exclusive Or command, offset: 0x980 */
AnnaBridge 143:86740a56073b 2590 __O uint32_t XOR_CAA; /**< Accumulator register - Exclusive Or command, offset: 0x984 */
AnnaBridge 143:86740a56073b 2591 __O uint32_t XOR_CA[9]; /**< General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command, array offset: 0x988, array step: 0x4 */
AnnaBridge 143:86740a56073b 2592 uint8_t RESERVED_5[20];
AnnaBridge 143:86740a56073b 2593 __O uint32_t ROTL_CASR; /**< Status register - Rotate Left command, offset: 0x9C0 */
AnnaBridge 143:86740a56073b 2594 __O uint32_t ROTL_CAA; /**< Accumulator register - Rotate Left command, offset: 0x9C4 */
AnnaBridge 143:86740a56073b 2595 __O uint32_t ROTL_CA[9]; /**< General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command, array offset: 0x9C8, array step: 0x4 */
AnnaBridge 143:86740a56073b 2596 uint8_t RESERVED_6[276];
AnnaBridge 143:86740a56073b 2597 __O uint32_t AESC_CASR; /**< Status register - AES Column Operation command, offset: 0xB00 */
AnnaBridge 143:86740a56073b 2598 __O uint32_t AESC_CAA; /**< Accumulator register - AES Column Operation command, offset: 0xB04 */
AnnaBridge 143:86740a56073b 2599 __O uint32_t AESC_CA[9]; /**< General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command, array offset: 0xB08, array step: 0x4 */
AnnaBridge 143:86740a56073b 2600 uint8_t RESERVED_7[20];
AnnaBridge 143:86740a56073b 2601 __O uint32_t AESIC_CASR; /**< Status register - AES Inverse Column Operation command, offset: 0xB40 */
AnnaBridge 143:86740a56073b 2602 __O uint32_t AESIC_CAA; /**< Accumulator register - AES Inverse Column Operation command, offset: 0xB44 */
AnnaBridge 143:86740a56073b 2603 __O uint32_t AESIC_CA[9]; /**< General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command, array offset: 0xB48, array step: 0x4 */
AnnaBridge 143:86740a56073b 2604 } CAU_Type;
AnnaBridge 143:86740a56073b 2605
AnnaBridge 143:86740a56073b 2606 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 2607 -- CAU Register Masks
AnnaBridge 143:86740a56073b 2608 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 2609
AnnaBridge 143:86740a56073b 2610 /*!
AnnaBridge 143:86740a56073b 2611 * @addtogroup CAU_Register_Masks CAU Register Masks
AnnaBridge 143:86740a56073b 2612 * @{
AnnaBridge 143:86740a56073b 2613 */
AnnaBridge 143:86740a56073b 2614
AnnaBridge 143:86740a56073b 2615 /*! @name DIRECT - Direct access register 0..Direct access register 15 */
AnnaBridge 143:86740a56073b 2616 #define CAU_DIRECT_CAU_DIRECT0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2617 #define CAU_DIRECT_CAU_DIRECT0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2618 #define CAU_DIRECT_CAU_DIRECT0(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT0_SHIFT)) & CAU_DIRECT_CAU_DIRECT0_MASK)
AnnaBridge 143:86740a56073b 2619 #define CAU_DIRECT_CAU_DIRECT1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2620 #define CAU_DIRECT_CAU_DIRECT1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2621 #define CAU_DIRECT_CAU_DIRECT1(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT1_SHIFT)) & CAU_DIRECT_CAU_DIRECT1_MASK)
AnnaBridge 143:86740a56073b 2622 #define CAU_DIRECT_CAU_DIRECT2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2623 #define CAU_DIRECT_CAU_DIRECT2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2624 #define CAU_DIRECT_CAU_DIRECT2(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT2_SHIFT)) & CAU_DIRECT_CAU_DIRECT2_MASK)
AnnaBridge 143:86740a56073b 2625 #define CAU_DIRECT_CAU_DIRECT3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2626 #define CAU_DIRECT_CAU_DIRECT3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2627 #define CAU_DIRECT_CAU_DIRECT3(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT3_SHIFT)) & CAU_DIRECT_CAU_DIRECT3_MASK)
AnnaBridge 143:86740a56073b 2628 #define CAU_DIRECT_CAU_DIRECT4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2629 #define CAU_DIRECT_CAU_DIRECT4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2630 #define CAU_DIRECT_CAU_DIRECT4(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT4_SHIFT)) & CAU_DIRECT_CAU_DIRECT4_MASK)
AnnaBridge 143:86740a56073b 2631 #define CAU_DIRECT_CAU_DIRECT5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2632 #define CAU_DIRECT_CAU_DIRECT5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2633 #define CAU_DIRECT_CAU_DIRECT5(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT5_SHIFT)) & CAU_DIRECT_CAU_DIRECT5_MASK)
AnnaBridge 143:86740a56073b 2634 #define CAU_DIRECT_CAU_DIRECT6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2635 #define CAU_DIRECT_CAU_DIRECT6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2636 #define CAU_DIRECT_CAU_DIRECT6(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT6_SHIFT)) & CAU_DIRECT_CAU_DIRECT6_MASK)
AnnaBridge 143:86740a56073b 2637 #define CAU_DIRECT_CAU_DIRECT7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2638 #define CAU_DIRECT_CAU_DIRECT7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2639 #define CAU_DIRECT_CAU_DIRECT7(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT7_SHIFT)) & CAU_DIRECT_CAU_DIRECT7_MASK)
AnnaBridge 143:86740a56073b 2640 #define CAU_DIRECT_CAU_DIRECT8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2641 #define CAU_DIRECT_CAU_DIRECT8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2642 #define CAU_DIRECT_CAU_DIRECT8(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT8_SHIFT)) & CAU_DIRECT_CAU_DIRECT8_MASK)
AnnaBridge 143:86740a56073b 2643 #define CAU_DIRECT_CAU_DIRECT9_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2644 #define CAU_DIRECT_CAU_DIRECT9_SHIFT (0U)
AnnaBridge 143:86740a56073b 2645 #define CAU_DIRECT_CAU_DIRECT9(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT9_SHIFT)) & CAU_DIRECT_CAU_DIRECT9_MASK)
AnnaBridge 143:86740a56073b 2646 #define CAU_DIRECT_CAU_DIRECT10_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2647 #define CAU_DIRECT_CAU_DIRECT10_SHIFT (0U)
AnnaBridge 143:86740a56073b 2648 #define CAU_DIRECT_CAU_DIRECT10(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT10_SHIFT)) & CAU_DIRECT_CAU_DIRECT10_MASK)
AnnaBridge 143:86740a56073b 2649 #define CAU_DIRECT_CAU_DIRECT11_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2650 #define CAU_DIRECT_CAU_DIRECT11_SHIFT (0U)
AnnaBridge 143:86740a56073b 2651 #define CAU_DIRECT_CAU_DIRECT11(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT11_SHIFT)) & CAU_DIRECT_CAU_DIRECT11_MASK)
AnnaBridge 143:86740a56073b 2652 #define CAU_DIRECT_CAU_DIRECT12_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2653 #define CAU_DIRECT_CAU_DIRECT12_SHIFT (0U)
AnnaBridge 143:86740a56073b 2654 #define CAU_DIRECT_CAU_DIRECT12(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT12_SHIFT)) & CAU_DIRECT_CAU_DIRECT12_MASK)
AnnaBridge 143:86740a56073b 2655 #define CAU_DIRECT_CAU_DIRECT13_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2656 #define CAU_DIRECT_CAU_DIRECT13_SHIFT (0U)
AnnaBridge 143:86740a56073b 2657 #define CAU_DIRECT_CAU_DIRECT13(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT13_SHIFT)) & CAU_DIRECT_CAU_DIRECT13_MASK)
AnnaBridge 143:86740a56073b 2658 #define CAU_DIRECT_CAU_DIRECT14_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2659 #define CAU_DIRECT_CAU_DIRECT14_SHIFT (0U)
AnnaBridge 143:86740a56073b 2660 #define CAU_DIRECT_CAU_DIRECT14(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT14_SHIFT)) & CAU_DIRECT_CAU_DIRECT14_MASK)
AnnaBridge 143:86740a56073b 2661 #define CAU_DIRECT_CAU_DIRECT15_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2662 #define CAU_DIRECT_CAU_DIRECT15_SHIFT (0U)
AnnaBridge 143:86740a56073b 2663 #define CAU_DIRECT_CAU_DIRECT15(x) (((uint32_t)(((uint32_t)(x)) << CAU_DIRECT_CAU_DIRECT15_SHIFT)) & CAU_DIRECT_CAU_DIRECT15_MASK)
AnnaBridge 143:86740a56073b 2664
AnnaBridge 143:86740a56073b 2665 /* The count of CAU_DIRECT */
AnnaBridge 143:86740a56073b 2666 #define CAU_DIRECT_COUNT (16U)
AnnaBridge 143:86740a56073b 2667
AnnaBridge 143:86740a56073b 2668 /*! @name LDR_CASR - Status register - Load Register command */
AnnaBridge 143:86740a56073b 2669 #define CAU_LDR_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 2670 #define CAU_LDR_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2671 #define CAU_LDR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_IC_SHIFT)) & CAU_LDR_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 2672 #define CAU_LDR_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 2673 #define CAU_LDR_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 2674 #define CAU_LDR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_DPE_SHIFT)) & CAU_LDR_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 2675 #define CAU_LDR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 2676 #define CAU_LDR_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 2677 #define CAU_LDR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CASR_VER_SHIFT)) & CAU_LDR_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 2678
AnnaBridge 143:86740a56073b 2679 /*! @name LDR_CAA - Accumulator register - Load Register command */
AnnaBridge 143:86740a56073b 2680 #define CAU_LDR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2681 #define CAU_LDR_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2682 #define CAU_LDR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CAA_ACC_SHIFT)) & CAU_LDR_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 2683
AnnaBridge 143:86740a56073b 2684 /*! @name LDR_CA - General Purpose Register 0 - Load Register command..General Purpose Register 8 - Load Register command */
AnnaBridge 143:86740a56073b 2685 #define CAU_LDR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2686 #define CAU_LDR_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2687 #define CAU_LDR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA0_SHIFT)) & CAU_LDR_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 2688 #define CAU_LDR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2689 #define CAU_LDR_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2690 #define CAU_LDR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA1_SHIFT)) & CAU_LDR_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 2691 #define CAU_LDR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2692 #define CAU_LDR_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2693 #define CAU_LDR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA2_SHIFT)) & CAU_LDR_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 2694 #define CAU_LDR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2695 #define CAU_LDR_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2696 #define CAU_LDR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA3_SHIFT)) & CAU_LDR_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 2697 #define CAU_LDR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2698 #define CAU_LDR_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2699 #define CAU_LDR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA4_SHIFT)) & CAU_LDR_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 2700 #define CAU_LDR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2701 #define CAU_LDR_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2702 #define CAU_LDR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA5_SHIFT)) & CAU_LDR_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 2703 #define CAU_LDR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2704 #define CAU_LDR_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2705 #define CAU_LDR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA6_SHIFT)) & CAU_LDR_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 2706 #define CAU_LDR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2707 #define CAU_LDR_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2708 #define CAU_LDR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA7_SHIFT)) & CAU_LDR_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 2709 #define CAU_LDR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2710 #define CAU_LDR_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2711 #define CAU_LDR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_LDR_CA_CA8_SHIFT)) & CAU_LDR_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 2712
AnnaBridge 143:86740a56073b 2713 /* The count of CAU_LDR_CA */
AnnaBridge 143:86740a56073b 2714 #define CAU_LDR_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 2715
AnnaBridge 143:86740a56073b 2716 /*! @name STR_CASR - Status register - Store Register command */
AnnaBridge 143:86740a56073b 2717 #define CAU_STR_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 2718 #define CAU_STR_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2719 #define CAU_STR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_IC_SHIFT)) & CAU_STR_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 2720 #define CAU_STR_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 2721 #define CAU_STR_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 2722 #define CAU_STR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_DPE_SHIFT)) & CAU_STR_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 2723 #define CAU_STR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 2724 #define CAU_STR_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 2725 #define CAU_STR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CASR_VER_SHIFT)) & CAU_STR_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 2726
AnnaBridge 143:86740a56073b 2727 /*! @name STR_CAA - Accumulator register - Store Register command */
AnnaBridge 143:86740a56073b 2728 #define CAU_STR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2729 #define CAU_STR_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2730 #define CAU_STR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CAA_ACC_SHIFT)) & CAU_STR_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 2731
AnnaBridge 143:86740a56073b 2732 /*! @name STR_CA - General Purpose Register 0 - Store Register command..General Purpose Register 8 - Store Register command */
AnnaBridge 143:86740a56073b 2733 #define CAU_STR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2734 #define CAU_STR_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2735 #define CAU_STR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA0_SHIFT)) & CAU_STR_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 2736 #define CAU_STR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2737 #define CAU_STR_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2738 #define CAU_STR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA1_SHIFT)) & CAU_STR_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 2739 #define CAU_STR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2740 #define CAU_STR_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2741 #define CAU_STR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA2_SHIFT)) & CAU_STR_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 2742 #define CAU_STR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2743 #define CAU_STR_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2744 #define CAU_STR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA3_SHIFT)) & CAU_STR_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 2745 #define CAU_STR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2746 #define CAU_STR_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2747 #define CAU_STR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA4_SHIFT)) & CAU_STR_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 2748 #define CAU_STR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2749 #define CAU_STR_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2750 #define CAU_STR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA5_SHIFT)) & CAU_STR_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 2751 #define CAU_STR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2752 #define CAU_STR_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2753 #define CAU_STR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA6_SHIFT)) & CAU_STR_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 2754 #define CAU_STR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2755 #define CAU_STR_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2756 #define CAU_STR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA7_SHIFT)) & CAU_STR_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 2757 #define CAU_STR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2758 #define CAU_STR_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2759 #define CAU_STR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_STR_CA_CA8_SHIFT)) & CAU_STR_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 2760
AnnaBridge 143:86740a56073b 2761 /* The count of CAU_STR_CA */
AnnaBridge 143:86740a56073b 2762 #define CAU_STR_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 2763
AnnaBridge 143:86740a56073b 2764 /*! @name ADR_CASR - Status register - Add Register command */
AnnaBridge 143:86740a56073b 2765 #define CAU_ADR_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 2766 #define CAU_ADR_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2767 #define CAU_ADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_IC_SHIFT)) & CAU_ADR_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 2768 #define CAU_ADR_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 2769 #define CAU_ADR_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 2770 #define CAU_ADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_DPE_SHIFT)) & CAU_ADR_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 2771 #define CAU_ADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 2772 #define CAU_ADR_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 2773 #define CAU_ADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CASR_VER_SHIFT)) & CAU_ADR_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 2774
AnnaBridge 143:86740a56073b 2775 /*! @name ADR_CAA - Accumulator register - Add to register command */
AnnaBridge 143:86740a56073b 2776 #define CAU_ADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2777 #define CAU_ADR_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2778 #define CAU_ADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CAA_ACC_SHIFT)) & CAU_ADR_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 2779
AnnaBridge 143:86740a56073b 2780 /*! @name ADR_CA - General Purpose Register 0 - Add to register command..General Purpose Register 8 - Add to register command */
AnnaBridge 143:86740a56073b 2781 #define CAU_ADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2782 #define CAU_ADR_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2783 #define CAU_ADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA0_SHIFT)) & CAU_ADR_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 2784 #define CAU_ADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2785 #define CAU_ADR_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2786 #define CAU_ADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA1_SHIFT)) & CAU_ADR_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 2787 #define CAU_ADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2788 #define CAU_ADR_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2789 #define CAU_ADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA2_SHIFT)) & CAU_ADR_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 2790 #define CAU_ADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2791 #define CAU_ADR_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2792 #define CAU_ADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA3_SHIFT)) & CAU_ADR_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 2793 #define CAU_ADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2794 #define CAU_ADR_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2795 #define CAU_ADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA4_SHIFT)) & CAU_ADR_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 2796 #define CAU_ADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2797 #define CAU_ADR_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2798 #define CAU_ADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA5_SHIFT)) & CAU_ADR_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 2799 #define CAU_ADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2800 #define CAU_ADR_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2801 #define CAU_ADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA6_SHIFT)) & CAU_ADR_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 2802 #define CAU_ADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2803 #define CAU_ADR_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2804 #define CAU_ADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA7_SHIFT)) & CAU_ADR_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 2805 #define CAU_ADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2806 #define CAU_ADR_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2807 #define CAU_ADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ADR_CA_CA8_SHIFT)) & CAU_ADR_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 2808
AnnaBridge 143:86740a56073b 2809 /* The count of CAU_ADR_CA */
AnnaBridge 143:86740a56073b 2810 #define CAU_ADR_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 2811
AnnaBridge 143:86740a56073b 2812 /*! @name RADR_CASR - Status register - Reverse and Add to Register command */
AnnaBridge 143:86740a56073b 2813 #define CAU_RADR_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 2814 #define CAU_RADR_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2815 #define CAU_RADR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_IC_SHIFT)) & CAU_RADR_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 2816 #define CAU_RADR_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 2817 #define CAU_RADR_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 2818 #define CAU_RADR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_DPE_SHIFT)) & CAU_RADR_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 2819 #define CAU_RADR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 2820 #define CAU_RADR_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 2821 #define CAU_RADR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CASR_VER_SHIFT)) & CAU_RADR_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 2822
AnnaBridge 143:86740a56073b 2823 /*! @name RADR_CAA - Accumulator register - Reverse and Add to Register command */
AnnaBridge 143:86740a56073b 2824 #define CAU_RADR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2825 #define CAU_RADR_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2826 #define CAU_RADR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CAA_ACC_SHIFT)) & CAU_RADR_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 2827
AnnaBridge 143:86740a56073b 2828 /*! @name RADR_CA - General Purpose Register 0 - Reverse and Add to Register command..General Purpose Register 8 - Reverse and Add to Register command */
AnnaBridge 143:86740a56073b 2829 #define CAU_RADR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2830 #define CAU_RADR_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2831 #define CAU_RADR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA0_SHIFT)) & CAU_RADR_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 2832 #define CAU_RADR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2833 #define CAU_RADR_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2834 #define CAU_RADR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA1_SHIFT)) & CAU_RADR_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 2835 #define CAU_RADR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2836 #define CAU_RADR_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2837 #define CAU_RADR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA2_SHIFT)) & CAU_RADR_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 2838 #define CAU_RADR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2839 #define CAU_RADR_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2840 #define CAU_RADR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA3_SHIFT)) & CAU_RADR_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 2841 #define CAU_RADR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2842 #define CAU_RADR_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2843 #define CAU_RADR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA4_SHIFT)) & CAU_RADR_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 2844 #define CAU_RADR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2845 #define CAU_RADR_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2846 #define CAU_RADR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA5_SHIFT)) & CAU_RADR_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 2847 #define CAU_RADR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2848 #define CAU_RADR_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2849 #define CAU_RADR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA6_SHIFT)) & CAU_RADR_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 2850 #define CAU_RADR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2851 #define CAU_RADR_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2852 #define CAU_RADR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA7_SHIFT)) & CAU_RADR_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 2853 #define CAU_RADR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2854 #define CAU_RADR_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2855 #define CAU_RADR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_RADR_CA_CA8_SHIFT)) & CAU_RADR_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 2856
AnnaBridge 143:86740a56073b 2857 /* The count of CAU_RADR_CA */
AnnaBridge 143:86740a56073b 2858 #define CAU_RADR_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 2859
AnnaBridge 143:86740a56073b 2860 /*! @name XOR_CASR - Status register - Exclusive Or command */
AnnaBridge 143:86740a56073b 2861 #define CAU_XOR_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 2862 #define CAU_XOR_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2863 #define CAU_XOR_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_IC_SHIFT)) & CAU_XOR_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 2864 #define CAU_XOR_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 2865 #define CAU_XOR_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 2866 #define CAU_XOR_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_DPE_SHIFT)) & CAU_XOR_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 2867 #define CAU_XOR_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 2868 #define CAU_XOR_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 2869 #define CAU_XOR_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CASR_VER_SHIFT)) & CAU_XOR_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 2870
AnnaBridge 143:86740a56073b 2871 /*! @name XOR_CAA - Accumulator register - Exclusive Or command */
AnnaBridge 143:86740a56073b 2872 #define CAU_XOR_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2873 #define CAU_XOR_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2874 #define CAU_XOR_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CAA_ACC_SHIFT)) & CAU_XOR_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 2875
AnnaBridge 143:86740a56073b 2876 /*! @name XOR_CA - General Purpose Register 0 - Exclusive Or command..General Purpose Register 8 - Exclusive Or command */
AnnaBridge 143:86740a56073b 2877 #define CAU_XOR_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2878 #define CAU_XOR_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2879 #define CAU_XOR_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA0_SHIFT)) & CAU_XOR_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 2880 #define CAU_XOR_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2881 #define CAU_XOR_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2882 #define CAU_XOR_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA1_SHIFT)) & CAU_XOR_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 2883 #define CAU_XOR_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2884 #define CAU_XOR_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2885 #define CAU_XOR_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA2_SHIFT)) & CAU_XOR_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 2886 #define CAU_XOR_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2887 #define CAU_XOR_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2888 #define CAU_XOR_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA3_SHIFT)) & CAU_XOR_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 2889 #define CAU_XOR_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2890 #define CAU_XOR_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2891 #define CAU_XOR_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA4_SHIFT)) & CAU_XOR_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 2892 #define CAU_XOR_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2893 #define CAU_XOR_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2894 #define CAU_XOR_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA5_SHIFT)) & CAU_XOR_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 2895 #define CAU_XOR_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2896 #define CAU_XOR_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2897 #define CAU_XOR_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA6_SHIFT)) & CAU_XOR_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 2898 #define CAU_XOR_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2899 #define CAU_XOR_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2900 #define CAU_XOR_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA7_SHIFT)) & CAU_XOR_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 2901 #define CAU_XOR_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2902 #define CAU_XOR_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2903 #define CAU_XOR_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_XOR_CA_CA8_SHIFT)) & CAU_XOR_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 2904
AnnaBridge 143:86740a56073b 2905 /* The count of CAU_XOR_CA */
AnnaBridge 143:86740a56073b 2906 #define CAU_XOR_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 2907
AnnaBridge 143:86740a56073b 2908 /*! @name ROTL_CASR - Status register - Rotate Left command */
AnnaBridge 143:86740a56073b 2909 #define CAU_ROTL_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 2910 #define CAU_ROTL_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2911 #define CAU_ROTL_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_IC_SHIFT)) & CAU_ROTL_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 2912 #define CAU_ROTL_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 2913 #define CAU_ROTL_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 2914 #define CAU_ROTL_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_DPE_SHIFT)) & CAU_ROTL_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 2915 #define CAU_ROTL_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 2916 #define CAU_ROTL_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 2917 #define CAU_ROTL_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CASR_VER_SHIFT)) & CAU_ROTL_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 2918
AnnaBridge 143:86740a56073b 2919 /*! @name ROTL_CAA - Accumulator register - Rotate Left command */
AnnaBridge 143:86740a56073b 2920 #define CAU_ROTL_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2921 #define CAU_ROTL_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2922 #define CAU_ROTL_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CAA_ACC_SHIFT)) & CAU_ROTL_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 2923
AnnaBridge 143:86740a56073b 2924 /*! @name ROTL_CA - General Purpose Register 0 - Rotate Left command..General Purpose Register 8 - Rotate Left command */
AnnaBridge 143:86740a56073b 2925 #define CAU_ROTL_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2926 #define CAU_ROTL_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2927 #define CAU_ROTL_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA0_SHIFT)) & CAU_ROTL_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 2928 #define CAU_ROTL_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2929 #define CAU_ROTL_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2930 #define CAU_ROTL_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA1_SHIFT)) & CAU_ROTL_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 2931 #define CAU_ROTL_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2932 #define CAU_ROTL_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2933 #define CAU_ROTL_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA2_SHIFT)) & CAU_ROTL_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 2934 #define CAU_ROTL_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2935 #define CAU_ROTL_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2936 #define CAU_ROTL_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA3_SHIFT)) & CAU_ROTL_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 2937 #define CAU_ROTL_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2938 #define CAU_ROTL_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2939 #define CAU_ROTL_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA4_SHIFT)) & CAU_ROTL_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 2940 #define CAU_ROTL_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2941 #define CAU_ROTL_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2942 #define CAU_ROTL_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA5_SHIFT)) & CAU_ROTL_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 2943 #define CAU_ROTL_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2944 #define CAU_ROTL_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2945 #define CAU_ROTL_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA6_SHIFT)) & CAU_ROTL_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 2946 #define CAU_ROTL_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2947 #define CAU_ROTL_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2948 #define CAU_ROTL_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA7_SHIFT)) & CAU_ROTL_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 2949 #define CAU_ROTL_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2950 #define CAU_ROTL_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2951 #define CAU_ROTL_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_ROTL_CA_CA8_SHIFT)) & CAU_ROTL_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 2952
AnnaBridge 143:86740a56073b 2953 /* The count of CAU_ROTL_CA */
AnnaBridge 143:86740a56073b 2954 #define CAU_ROTL_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 2955
AnnaBridge 143:86740a56073b 2956 /*! @name AESC_CASR - Status register - AES Column Operation command */
AnnaBridge 143:86740a56073b 2957 #define CAU_AESC_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 2958 #define CAU_AESC_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2959 #define CAU_AESC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_IC_SHIFT)) & CAU_AESC_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 2960 #define CAU_AESC_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 2961 #define CAU_AESC_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 2962 #define CAU_AESC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_DPE_SHIFT)) & CAU_AESC_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 2963 #define CAU_AESC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 2964 #define CAU_AESC_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 2965 #define CAU_AESC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CASR_VER_SHIFT)) & CAU_AESC_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 2966
AnnaBridge 143:86740a56073b 2967 /*! @name AESC_CAA - Accumulator register - AES Column Operation command */
AnnaBridge 143:86740a56073b 2968 #define CAU_AESC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2969 #define CAU_AESC_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 2970 #define CAU_AESC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CAA_ACC_SHIFT)) & CAU_AESC_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 2971
AnnaBridge 143:86740a56073b 2972 /*! @name AESC_CA - General Purpose Register 0 - AES Column Operation command..General Purpose Register 8 - AES Column Operation command */
AnnaBridge 143:86740a56073b 2973 #define CAU_AESC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2974 #define CAU_AESC_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 2975 #define CAU_AESC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA0_SHIFT)) & CAU_AESC_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 2976 #define CAU_AESC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2977 #define CAU_AESC_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 2978 #define CAU_AESC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA1_SHIFT)) & CAU_AESC_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 2979 #define CAU_AESC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2980 #define CAU_AESC_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 2981 #define CAU_AESC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA2_SHIFT)) & CAU_AESC_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 2982 #define CAU_AESC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2983 #define CAU_AESC_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 2984 #define CAU_AESC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA3_SHIFT)) & CAU_AESC_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 2985 #define CAU_AESC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2986 #define CAU_AESC_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 2987 #define CAU_AESC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA4_SHIFT)) & CAU_AESC_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 2988 #define CAU_AESC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2989 #define CAU_AESC_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 2990 #define CAU_AESC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA5_SHIFT)) & CAU_AESC_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 2991 #define CAU_AESC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2992 #define CAU_AESC_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 2993 #define CAU_AESC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA6_SHIFT)) & CAU_AESC_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 2994 #define CAU_AESC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2995 #define CAU_AESC_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 2996 #define CAU_AESC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA7_SHIFT)) & CAU_AESC_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 2997 #define CAU_AESC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 2998 #define CAU_AESC_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 2999 #define CAU_AESC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESC_CA_CA8_SHIFT)) & CAU_AESC_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 3000
AnnaBridge 143:86740a56073b 3001 /* The count of CAU_AESC_CA */
AnnaBridge 143:86740a56073b 3002 #define CAU_AESC_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 3003
AnnaBridge 143:86740a56073b 3004 /*! @name AESIC_CASR - Status register - AES Inverse Column Operation command */
AnnaBridge 143:86740a56073b 3005 #define CAU_AESIC_CASR_IC_MASK (0x1U)
AnnaBridge 143:86740a56073b 3006 #define CAU_AESIC_CASR_IC_SHIFT (0U)
AnnaBridge 143:86740a56073b 3007 #define CAU_AESIC_CASR_IC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_IC_SHIFT)) & CAU_AESIC_CASR_IC_MASK)
AnnaBridge 143:86740a56073b 3008 #define CAU_AESIC_CASR_DPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 3009 #define CAU_AESIC_CASR_DPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 3010 #define CAU_AESIC_CASR_DPE(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_DPE_SHIFT)) & CAU_AESIC_CASR_DPE_MASK)
AnnaBridge 143:86740a56073b 3011 #define CAU_AESIC_CASR_VER_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 3012 #define CAU_AESIC_CASR_VER_SHIFT (28U)
AnnaBridge 143:86740a56073b 3013 #define CAU_AESIC_CASR_VER(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CASR_VER_SHIFT)) & CAU_AESIC_CASR_VER_MASK)
AnnaBridge 143:86740a56073b 3014
AnnaBridge 143:86740a56073b 3015 /*! @name AESIC_CAA - Accumulator register - AES Inverse Column Operation command */
AnnaBridge 143:86740a56073b 3016 #define CAU_AESIC_CAA_ACC_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3017 #define CAU_AESIC_CAA_ACC_SHIFT (0U)
AnnaBridge 143:86740a56073b 3018 #define CAU_AESIC_CAA_ACC(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CAA_ACC_SHIFT)) & CAU_AESIC_CAA_ACC_MASK)
AnnaBridge 143:86740a56073b 3019
AnnaBridge 143:86740a56073b 3020 /*! @name AESIC_CA - General Purpose Register 0 - AES Inverse Column Operation command..General Purpose Register 8 - AES Inverse Column Operation command */
AnnaBridge 143:86740a56073b 3021 #define CAU_AESIC_CA_CA0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3022 #define CAU_AESIC_CA_CA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 3023 #define CAU_AESIC_CA_CA0(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA0_SHIFT)) & CAU_AESIC_CA_CA0_MASK)
AnnaBridge 143:86740a56073b 3024 #define CAU_AESIC_CA_CA1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3025 #define CAU_AESIC_CA_CA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 3026 #define CAU_AESIC_CA_CA1(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA1_SHIFT)) & CAU_AESIC_CA_CA1_MASK)
AnnaBridge 143:86740a56073b 3027 #define CAU_AESIC_CA_CA2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3028 #define CAU_AESIC_CA_CA2_SHIFT (0U)
AnnaBridge 143:86740a56073b 3029 #define CAU_AESIC_CA_CA2(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA2_SHIFT)) & CAU_AESIC_CA_CA2_MASK)
AnnaBridge 143:86740a56073b 3030 #define CAU_AESIC_CA_CA3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3031 #define CAU_AESIC_CA_CA3_SHIFT (0U)
AnnaBridge 143:86740a56073b 3032 #define CAU_AESIC_CA_CA3(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA3_SHIFT)) & CAU_AESIC_CA_CA3_MASK)
AnnaBridge 143:86740a56073b 3033 #define CAU_AESIC_CA_CA4_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3034 #define CAU_AESIC_CA_CA4_SHIFT (0U)
AnnaBridge 143:86740a56073b 3035 #define CAU_AESIC_CA_CA4(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA4_SHIFT)) & CAU_AESIC_CA_CA4_MASK)
AnnaBridge 143:86740a56073b 3036 #define CAU_AESIC_CA_CA5_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3037 #define CAU_AESIC_CA_CA5_SHIFT (0U)
AnnaBridge 143:86740a56073b 3038 #define CAU_AESIC_CA_CA5(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA5_SHIFT)) & CAU_AESIC_CA_CA5_MASK)
AnnaBridge 143:86740a56073b 3039 #define CAU_AESIC_CA_CA6_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3040 #define CAU_AESIC_CA_CA6_SHIFT (0U)
AnnaBridge 143:86740a56073b 3041 #define CAU_AESIC_CA_CA6(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA6_SHIFT)) & CAU_AESIC_CA_CA6_MASK)
AnnaBridge 143:86740a56073b 3042 #define CAU_AESIC_CA_CA7_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3043 #define CAU_AESIC_CA_CA7_SHIFT (0U)
AnnaBridge 143:86740a56073b 3044 #define CAU_AESIC_CA_CA7(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA7_SHIFT)) & CAU_AESIC_CA_CA7_MASK)
AnnaBridge 143:86740a56073b 3045 #define CAU_AESIC_CA_CA8_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 3046 #define CAU_AESIC_CA_CA8_SHIFT (0U)
AnnaBridge 143:86740a56073b 3047 #define CAU_AESIC_CA_CA8(x) (((uint32_t)(((uint32_t)(x)) << CAU_AESIC_CA_CA8_SHIFT)) & CAU_AESIC_CA_CA8_MASK)
AnnaBridge 143:86740a56073b 3048
AnnaBridge 143:86740a56073b 3049 /* The count of CAU_AESIC_CA */
AnnaBridge 143:86740a56073b 3050 #define CAU_AESIC_CA_COUNT (9U)
AnnaBridge 143:86740a56073b 3051
AnnaBridge 143:86740a56073b 3052
AnnaBridge 143:86740a56073b 3053 /*!
AnnaBridge 143:86740a56073b 3054 * @}
AnnaBridge 143:86740a56073b 3055 */ /* end of group CAU_Register_Masks */
AnnaBridge 143:86740a56073b 3056
AnnaBridge 143:86740a56073b 3057
AnnaBridge 143:86740a56073b 3058 /* CAU - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 3059 /** Peripheral CAU base address */
AnnaBridge 143:86740a56073b 3060 #define CAU_BASE (0xE0081000u)
AnnaBridge 143:86740a56073b 3061 /** Peripheral CAU base pointer */
AnnaBridge 143:86740a56073b 3062 #define CAU ((CAU_Type *)CAU_BASE)
AnnaBridge 143:86740a56073b 3063 /** Array initializer of CAU peripheral base addresses */
AnnaBridge 143:86740a56073b 3064 #define CAU_BASE_ADDRS { CAU_BASE }
AnnaBridge 143:86740a56073b 3065 /** Array initializer of CAU peripheral base pointers */
AnnaBridge 143:86740a56073b 3066 #define CAU_BASE_PTRS { CAU }
AnnaBridge 143:86740a56073b 3067
AnnaBridge 143:86740a56073b 3068 /*!
AnnaBridge 143:86740a56073b 3069 * @}
AnnaBridge 143:86740a56073b 3070 */ /* end of group CAU_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 3071
AnnaBridge 143:86740a56073b 3072
AnnaBridge 143:86740a56073b 3073 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3074 -- CMP Peripheral Access Layer
AnnaBridge 143:86740a56073b 3075 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3076
AnnaBridge 143:86740a56073b 3077 /*!
AnnaBridge 143:86740a56073b 3078 * @addtogroup CMP_Peripheral_Access_Layer CMP Peripheral Access Layer
AnnaBridge 143:86740a56073b 3079 * @{
AnnaBridge 143:86740a56073b 3080 */
AnnaBridge 143:86740a56073b 3081
AnnaBridge 143:86740a56073b 3082 /** CMP - Register Layout Typedef */
AnnaBridge 143:86740a56073b 3083 typedef struct {
AnnaBridge 143:86740a56073b 3084 __IO uint8_t CR0; /**< CMP Control Register 0, offset: 0x0 */
AnnaBridge 143:86740a56073b 3085 __IO uint8_t CR1; /**< CMP Control Register 1, offset: 0x1 */
AnnaBridge 143:86740a56073b 3086 __IO uint8_t FPR; /**< CMP Filter Period Register, offset: 0x2 */
AnnaBridge 143:86740a56073b 3087 __IO uint8_t SCR; /**< CMP Status and Control Register, offset: 0x3 */
AnnaBridge 143:86740a56073b 3088 __IO uint8_t DACCR; /**< DAC Control Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 3089 __IO uint8_t MUXCR; /**< MUX Control Register, offset: 0x5 */
AnnaBridge 143:86740a56073b 3090 } CMP_Type;
AnnaBridge 143:86740a56073b 3091
AnnaBridge 143:86740a56073b 3092 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3093 -- CMP Register Masks
AnnaBridge 143:86740a56073b 3094 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3095
AnnaBridge 143:86740a56073b 3096 /*!
AnnaBridge 143:86740a56073b 3097 * @addtogroup CMP_Register_Masks CMP Register Masks
AnnaBridge 143:86740a56073b 3098 * @{
AnnaBridge 143:86740a56073b 3099 */
AnnaBridge 143:86740a56073b 3100
AnnaBridge 143:86740a56073b 3101 /*! @name CR0 - CMP Control Register 0 */
AnnaBridge 143:86740a56073b 3102 #define CMP_CR0_HYSTCTR_MASK (0x3U)
AnnaBridge 143:86740a56073b 3103 #define CMP_CR0_HYSTCTR_SHIFT (0U)
AnnaBridge 143:86740a56073b 3104 #define CMP_CR0_HYSTCTR(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_HYSTCTR_SHIFT)) & CMP_CR0_HYSTCTR_MASK)
AnnaBridge 143:86740a56073b 3105 #define CMP_CR0_FILTER_CNT_MASK (0x70U)
AnnaBridge 143:86740a56073b 3106 #define CMP_CR0_FILTER_CNT_SHIFT (4U)
AnnaBridge 143:86740a56073b 3107 #define CMP_CR0_FILTER_CNT(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR0_FILTER_CNT_SHIFT)) & CMP_CR0_FILTER_CNT_MASK)
AnnaBridge 143:86740a56073b 3108
AnnaBridge 143:86740a56073b 3109 /*! @name CR1 - CMP Control Register 1 */
AnnaBridge 143:86740a56073b 3110 #define CMP_CR1_EN_MASK (0x1U)
AnnaBridge 143:86740a56073b 3111 #define CMP_CR1_EN_SHIFT (0U)
AnnaBridge 143:86740a56073b 3112 #define CMP_CR1_EN(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_EN_SHIFT)) & CMP_CR1_EN_MASK)
AnnaBridge 143:86740a56073b 3113 #define CMP_CR1_OPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 3114 #define CMP_CR1_OPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 3115 #define CMP_CR1_OPE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_OPE_SHIFT)) & CMP_CR1_OPE_MASK)
AnnaBridge 143:86740a56073b 3116 #define CMP_CR1_COS_MASK (0x4U)
AnnaBridge 143:86740a56073b 3117 #define CMP_CR1_COS_SHIFT (2U)
AnnaBridge 143:86740a56073b 3118 #define CMP_CR1_COS(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_COS_SHIFT)) & CMP_CR1_COS_MASK)
AnnaBridge 143:86740a56073b 3119 #define CMP_CR1_INV_MASK (0x8U)
AnnaBridge 143:86740a56073b 3120 #define CMP_CR1_INV_SHIFT (3U)
AnnaBridge 143:86740a56073b 3121 #define CMP_CR1_INV(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_INV_SHIFT)) & CMP_CR1_INV_MASK)
AnnaBridge 143:86740a56073b 3122 #define CMP_CR1_PMODE_MASK (0x10U)
AnnaBridge 143:86740a56073b 3123 #define CMP_CR1_PMODE_SHIFT (4U)
AnnaBridge 143:86740a56073b 3124 #define CMP_CR1_PMODE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_PMODE_SHIFT)) & CMP_CR1_PMODE_MASK)
AnnaBridge 143:86740a56073b 3125 #define CMP_CR1_WE_MASK (0x40U)
AnnaBridge 143:86740a56073b 3126 #define CMP_CR1_WE_SHIFT (6U)
AnnaBridge 143:86740a56073b 3127 #define CMP_CR1_WE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_WE_SHIFT)) & CMP_CR1_WE_MASK)
AnnaBridge 143:86740a56073b 3128 #define CMP_CR1_SE_MASK (0x80U)
AnnaBridge 143:86740a56073b 3129 #define CMP_CR1_SE_SHIFT (7U)
AnnaBridge 143:86740a56073b 3130 #define CMP_CR1_SE(x) (((uint8_t)(((uint8_t)(x)) << CMP_CR1_SE_SHIFT)) & CMP_CR1_SE_MASK)
AnnaBridge 143:86740a56073b 3131
AnnaBridge 143:86740a56073b 3132 /*! @name FPR - CMP Filter Period Register */
AnnaBridge 143:86740a56073b 3133 #define CMP_FPR_FILT_PER_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3134 #define CMP_FPR_FILT_PER_SHIFT (0U)
AnnaBridge 143:86740a56073b 3135 #define CMP_FPR_FILT_PER(x) (((uint8_t)(((uint8_t)(x)) << CMP_FPR_FILT_PER_SHIFT)) & CMP_FPR_FILT_PER_MASK)
AnnaBridge 143:86740a56073b 3136
AnnaBridge 143:86740a56073b 3137 /*! @name SCR - CMP Status and Control Register */
AnnaBridge 143:86740a56073b 3138 #define CMP_SCR_COUT_MASK (0x1U)
AnnaBridge 143:86740a56073b 3139 #define CMP_SCR_COUT_SHIFT (0U)
AnnaBridge 143:86740a56073b 3140 #define CMP_SCR_COUT(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_COUT_SHIFT)) & CMP_SCR_COUT_MASK)
AnnaBridge 143:86740a56073b 3141 #define CMP_SCR_CFF_MASK (0x2U)
AnnaBridge 143:86740a56073b 3142 #define CMP_SCR_CFF_SHIFT (1U)
AnnaBridge 143:86740a56073b 3143 #define CMP_SCR_CFF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFF_SHIFT)) & CMP_SCR_CFF_MASK)
AnnaBridge 143:86740a56073b 3144 #define CMP_SCR_CFR_MASK (0x4U)
AnnaBridge 143:86740a56073b 3145 #define CMP_SCR_CFR_SHIFT (2U)
AnnaBridge 143:86740a56073b 3146 #define CMP_SCR_CFR(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_CFR_SHIFT)) & CMP_SCR_CFR_MASK)
AnnaBridge 143:86740a56073b 3147 #define CMP_SCR_IEF_MASK (0x8U)
AnnaBridge 143:86740a56073b 3148 #define CMP_SCR_IEF_SHIFT (3U)
AnnaBridge 143:86740a56073b 3149 #define CMP_SCR_IEF(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IEF_SHIFT)) & CMP_SCR_IEF_MASK)
AnnaBridge 143:86740a56073b 3150 #define CMP_SCR_IER_MASK (0x10U)
AnnaBridge 143:86740a56073b 3151 #define CMP_SCR_IER_SHIFT (4U)
AnnaBridge 143:86740a56073b 3152 #define CMP_SCR_IER(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_IER_SHIFT)) & CMP_SCR_IER_MASK)
AnnaBridge 143:86740a56073b 3153 #define CMP_SCR_DMAEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 3154 #define CMP_SCR_DMAEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 3155 #define CMP_SCR_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_SCR_DMAEN_SHIFT)) & CMP_SCR_DMAEN_MASK)
AnnaBridge 143:86740a56073b 3156
AnnaBridge 143:86740a56073b 3157 /*! @name DACCR - DAC Control Register */
AnnaBridge 143:86740a56073b 3158 #define CMP_DACCR_VOSEL_MASK (0x3FU)
AnnaBridge 143:86740a56073b 3159 #define CMP_DACCR_VOSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3160 #define CMP_DACCR_VOSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VOSEL_SHIFT)) & CMP_DACCR_VOSEL_MASK)
AnnaBridge 143:86740a56073b 3161 #define CMP_DACCR_VRSEL_MASK (0x40U)
AnnaBridge 143:86740a56073b 3162 #define CMP_DACCR_VRSEL_SHIFT (6U)
AnnaBridge 143:86740a56073b 3163 #define CMP_DACCR_VRSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_VRSEL_SHIFT)) & CMP_DACCR_VRSEL_MASK)
AnnaBridge 143:86740a56073b 3164 #define CMP_DACCR_DACEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 3165 #define CMP_DACCR_DACEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 3166 #define CMP_DACCR_DACEN(x) (((uint8_t)(((uint8_t)(x)) << CMP_DACCR_DACEN_SHIFT)) & CMP_DACCR_DACEN_MASK)
AnnaBridge 143:86740a56073b 3167
AnnaBridge 143:86740a56073b 3168 /*! @name MUXCR - MUX Control Register */
AnnaBridge 143:86740a56073b 3169 #define CMP_MUXCR_MSEL_MASK (0x7U)
AnnaBridge 143:86740a56073b 3170 #define CMP_MUXCR_MSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3171 #define CMP_MUXCR_MSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_MSEL_SHIFT)) & CMP_MUXCR_MSEL_MASK)
AnnaBridge 143:86740a56073b 3172 #define CMP_MUXCR_PSEL_MASK (0x38U)
AnnaBridge 143:86740a56073b 3173 #define CMP_MUXCR_PSEL_SHIFT (3U)
AnnaBridge 143:86740a56073b 3174 #define CMP_MUXCR_PSEL(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSEL_SHIFT)) & CMP_MUXCR_PSEL_MASK)
AnnaBridge 143:86740a56073b 3175 #define CMP_MUXCR_PSTM_MASK (0x80U)
AnnaBridge 143:86740a56073b 3176 #define CMP_MUXCR_PSTM_SHIFT (7U)
AnnaBridge 143:86740a56073b 3177 #define CMP_MUXCR_PSTM(x) (((uint8_t)(((uint8_t)(x)) << CMP_MUXCR_PSTM_SHIFT)) & CMP_MUXCR_PSTM_MASK)
AnnaBridge 143:86740a56073b 3178
AnnaBridge 143:86740a56073b 3179
AnnaBridge 143:86740a56073b 3180 /*!
AnnaBridge 143:86740a56073b 3181 * @}
AnnaBridge 143:86740a56073b 3182 */ /* end of group CMP_Register_Masks */
AnnaBridge 143:86740a56073b 3183
AnnaBridge 143:86740a56073b 3184
AnnaBridge 143:86740a56073b 3185 /* CMP - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 3186 /** Peripheral CMP0 base address */
AnnaBridge 143:86740a56073b 3187 #define CMP0_BASE (0x40073000u)
AnnaBridge 143:86740a56073b 3188 /** Peripheral CMP0 base pointer */
AnnaBridge 143:86740a56073b 3189 #define CMP0 ((CMP_Type *)CMP0_BASE)
AnnaBridge 143:86740a56073b 3190 /** Peripheral CMP1 base address */
AnnaBridge 143:86740a56073b 3191 #define CMP1_BASE (0x40073008u)
AnnaBridge 143:86740a56073b 3192 /** Peripheral CMP1 base pointer */
AnnaBridge 143:86740a56073b 3193 #define CMP1 ((CMP_Type *)CMP1_BASE)
AnnaBridge 143:86740a56073b 3194 /** Peripheral CMP2 base address */
AnnaBridge 143:86740a56073b 3195 #define CMP2_BASE (0x40073010u)
AnnaBridge 143:86740a56073b 3196 /** Peripheral CMP2 base pointer */
AnnaBridge 143:86740a56073b 3197 #define CMP2 ((CMP_Type *)CMP2_BASE)
AnnaBridge 143:86740a56073b 3198 /** Array initializer of CMP peripheral base addresses */
AnnaBridge 143:86740a56073b 3199 #define CMP_BASE_ADDRS { CMP0_BASE, CMP1_BASE, CMP2_BASE }
AnnaBridge 143:86740a56073b 3200 /** Array initializer of CMP peripheral base pointers */
AnnaBridge 143:86740a56073b 3201 #define CMP_BASE_PTRS { CMP0, CMP1, CMP2 }
AnnaBridge 143:86740a56073b 3202 /** Interrupt vectors for the CMP peripheral type */
AnnaBridge 143:86740a56073b 3203 #define CMP_IRQS { CMP0_IRQn, CMP1_IRQn, CMP2_IRQn }
AnnaBridge 143:86740a56073b 3204
AnnaBridge 143:86740a56073b 3205 /*!
AnnaBridge 143:86740a56073b 3206 * @}
AnnaBridge 143:86740a56073b 3207 */ /* end of group CMP_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 3208
AnnaBridge 143:86740a56073b 3209
AnnaBridge 143:86740a56073b 3210 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3211 -- CMT Peripheral Access Layer
AnnaBridge 143:86740a56073b 3212 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3213
AnnaBridge 143:86740a56073b 3214 /*!
AnnaBridge 143:86740a56073b 3215 * @addtogroup CMT_Peripheral_Access_Layer CMT Peripheral Access Layer
AnnaBridge 143:86740a56073b 3216 * @{
AnnaBridge 143:86740a56073b 3217 */
AnnaBridge 143:86740a56073b 3218
AnnaBridge 143:86740a56073b 3219 /** CMT - Register Layout Typedef */
AnnaBridge 143:86740a56073b 3220 typedef struct {
AnnaBridge 143:86740a56073b 3221 __IO uint8_t CGH1; /**< CMT Carrier Generator High Data Register 1, offset: 0x0 */
AnnaBridge 143:86740a56073b 3222 __IO uint8_t CGL1; /**< CMT Carrier Generator Low Data Register 1, offset: 0x1 */
AnnaBridge 143:86740a56073b 3223 __IO uint8_t CGH2; /**< CMT Carrier Generator High Data Register 2, offset: 0x2 */
AnnaBridge 143:86740a56073b 3224 __IO uint8_t CGL2; /**< CMT Carrier Generator Low Data Register 2, offset: 0x3 */
AnnaBridge 143:86740a56073b 3225 __IO uint8_t OC; /**< CMT Output Control Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 3226 __IO uint8_t MSC; /**< CMT Modulator Status and Control Register, offset: 0x5 */
AnnaBridge 143:86740a56073b 3227 __IO uint8_t CMD1; /**< CMT Modulator Data Register Mark High, offset: 0x6 */
AnnaBridge 143:86740a56073b 3228 __IO uint8_t CMD2; /**< CMT Modulator Data Register Mark Low, offset: 0x7 */
AnnaBridge 143:86740a56073b 3229 __IO uint8_t CMD3; /**< CMT Modulator Data Register Space High, offset: 0x8 */
AnnaBridge 143:86740a56073b 3230 __IO uint8_t CMD4; /**< CMT Modulator Data Register Space Low, offset: 0x9 */
AnnaBridge 143:86740a56073b 3231 __IO uint8_t PPS; /**< CMT Primary Prescaler Register, offset: 0xA */
AnnaBridge 143:86740a56073b 3232 __IO uint8_t DMA; /**< CMT Direct Memory Access Register, offset: 0xB */
AnnaBridge 143:86740a56073b 3233 } CMT_Type;
AnnaBridge 143:86740a56073b 3234
AnnaBridge 143:86740a56073b 3235 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3236 -- CMT Register Masks
AnnaBridge 143:86740a56073b 3237 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3238
AnnaBridge 143:86740a56073b 3239 /*!
AnnaBridge 143:86740a56073b 3240 * @addtogroup CMT_Register_Masks CMT Register Masks
AnnaBridge 143:86740a56073b 3241 * @{
AnnaBridge 143:86740a56073b 3242 */
AnnaBridge 143:86740a56073b 3243
AnnaBridge 143:86740a56073b 3244 /*! @name CGH1 - CMT Carrier Generator High Data Register 1 */
AnnaBridge 143:86740a56073b 3245 #define CMT_CGH1_PH_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3246 #define CMT_CGH1_PH_SHIFT (0U)
AnnaBridge 143:86740a56073b 3247 #define CMT_CGH1_PH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH1_PH_SHIFT)) & CMT_CGH1_PH_MASK)
AnnaBridge 143:86740a56073b 3248
AnnaBridge 143:86740a56073b 3249 /*! @name CGL1 - CMT Carrier Generator Low Data Register 1 */
AnnaBridge 143:86740a56073b 3250 #define CMT_CGL1_PL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3251 #define CMT_CGL1_PL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3252 #define CMT_CGL1_PL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL1_PL_SHIFT)) & CMT_CGL1_PL_MASK)
AnnaBridge 143:86740a56073b 3253
AnnaBridge 143:86740a56073b 3254 /*! @name CGH2 - CMT Carrier Generator High Data Register 2 */
AnnaBridge 143:86740a56073b 3255 #define CMT_CGH2_SH_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3256 #define CMT_CGH2_SH_SHIFT (0U)
AnnaBridge 143:86740a56073b 3257 #define CMT_CGH2_SH(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGH2_SH_SHIFT)) & CMT_CGH2_SH_MASK)
AnnaBridge 143:86740a56073b 3258
AnnaBridge 143:86740a56073b 3259 /*! @name CGL2 - CMT Carrier Generator Low Data Register 2 */
AnnaBridge 143:86740a56073b 3260 #define CMT_CGL2_SL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3261 #define CMT_CGL2_SL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3262 #define CMT_CGL2_SL(x) (((uint8_t)(((uint8_t)(x)) << CMT_CGL2_SL_SHIFT)) & CMT_CGL2_SL_MASK)
AnnaBridge 143:86740a56073b 3263
AnnaBridge 143:86740a56073b 3264 /*! @name OC - CMT Output Control Register */
AnnaBridge 143:86740a56073b 3265 #define CMT_OC_IROPEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 3266 #define CMT_OC_IROPEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 3267 #define CMT_OC_IROPEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROPEN_SHIFT)) & CMT_OC_IROPEN_MASK)
AnnaBridge 143:86740a56073b 3268 #define CMT_OC_CMTPOL_MASK (0x40U)
AnnaBridge 143:86740a56073b 3269 #define CMT_OC_CMTPOL_SHIFT (6U)
AnnaBridge 143:86740a56073b 3270 #define CMT_OC_CMTPOL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_CMTPOL_SHIFT)) & CMT_OC_CMTPOL_MASK)
AnnaBridge 143:86740a56073b 3271 #define CMT_OC_IROL_MASK (0x80U)
AnnaBridge 143:86740a56073b 3272 #define CMT_OC_IROL_SHIFT (7U)
AnnaBridge 143:86740a56073b 3273 #define CMT_OC_IROL(x) (((uint8_t)(((uint8_t)(x)) << CMT_OC_IROL_SHIFT)) & CMT_OC_IROL_MASK)
AnnaBridge 143:86740a56073b 3274
AnnaBridge 143:86740a56073b 3275 /*! @name MSC - CMT Modulator Status and Control Register */
AnnaBridge 143:86740a56073b 3276 #define CMT_MSC_MCGEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 3277 #define CMT_MSC_MCGEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 3278 #define CMT_MSC_MCGEN(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_MCGEN_SHIFT)) & CMT_MSC_MCGEN_MASK)
AnnaBridge 143:86740a56073b 3279 #define CMT_MSC_EOCIE_MASK (0x2U)
AnnaBridge 143:86740a56073b 3280 #define CMT_MSC_EOCIE_SHIFT (1U)
AnnaBridge 143:86740a56073b 3281 #define CMT_MSC_EOCIE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCIE_SHIFT)) & CMT_MSC_EOCIE_MASK)
AnnaBridge 143:86740a56073b 3282 #define CMT_MSC_FSK_MASK (0x4U)
AnnaBridge 143:86740a56073b 3283 #define CMT_MSC_FSK_SHIFT (2U)
AnnaBridge 143:86740a56073b 3284 #define CMT_MSC_FSK(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_FSK_SHIFT)) & CMT_MSC_FSK_MASK)
AnnaBridge 143:86740a56073b 3285 #define CMT_MSC_BASE_MASK (0x8U)
AnnaBridge 143:86740a56073b 3286 #define CMT_MSC_BASE_SHIFT (3U)
AnnaBridge 143:86740a56073b 3287 #define CMT_MSC_BASE(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_BASE_SHIFT)) & CMT_MSC_BASE_MASK)
AnnaBridge 143:86740a56073b 3288 #define CMT_MSC_EXSPC_MASK (0x10U)
AnnaBridge 143:86740a56073b 3289 #define CMT_MSC_EXSPC_SHIFT (4U)
AnnaBridge 143:86740a56073b 3290 #define CMT_MSC_EXSPC(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EXSPC_SHIFT)) & CMT_MSC_EXSPC_MASK)
AnnaBridge 143:86740a56073b 3291 #define CMT_MSC_CMTDIV_MASK (0x60U)
AnnaBridge 143:86740a56073b 3292 #define CMT_MSC_CMTDIV_SHIFT (5U)
AnnaBridge 143:86740a56073b 3293 #define CMT_MSC_CMTDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_CMTDIV_SHIFT)) & CMT_MSC_CMTDIV_MASK)
AnnaBridge 143:86740a56073b 3294 #define CMT_MSC_EOCF_MASK (0x80U)
AnnaBridge 143:86740a56073b 3295 #define CMT_MSC_EOCF_SHIFT (7U)
AnnaBridge 143:86740a56073b 3296 #define CMT_MSC_EOCF(x) (((uint8_t)(((uint8_t)(x)) << CMT_MSC_EOCF_SHIFT)) & CMT_MSC_EOCF_MASK)
AnnaBridge 143:86740a56073b 3297
AnnaBridge 143:86740a56073b 3298 /*! @name CMD1 - CMT Modulator Data Register Mark High */
AnnaBridge 143:86740a56073b 3299 #define CMT_CMD1_MB_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3300 #define CMT_CMD1_MB_SHIFT (0U)
AnnaBridge 143:86740a56073b 3301 #define CMT_CMD1_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD1_MB_SHIFT)) & CMT_CMD1_MB_MASK)
AnnaBridge 143:86740a56073b 3302
AnnaBridge 143:86740a56073b 3303 /*! @name CMD2 - CMT Modulator Data Register Mark Low */
AnnaBridge 143:86740a56073b 3304 #define CMT_CMD2_MB_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3305 #define CMT_CMD2_MB_SHIFT (0U)
AnnaBridge 143:86740a56073b 3306 #define CMT_CMD2_MB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD2_MB_SHIFT)) & CMT_CMD2_MB_MASK)
AnnaBridge 143:86740a56073b 3307
AnnaBridge 143:86740a56073b 3308 /*! @name CMD3 - CMT Modulator Data Register Space High */
AnnaBridge 143:86740a56073b 3309 #define CMT_CMD3_SB_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3310 #define CMT_CMD3_SB_SHIFT (0U)
AnnaBridge 143:86740a56073b 3311 #define CMT_CMD3_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD3_SB_SHIFT)) & CMT_CMD3_SB_MASK)
AnnaBridge 143:86740a56073b 3312
AnnaBridge 143:86740a56073b 3313 /*! @name CMD4 - CMT Modulator Data Register Space Low */
AnnaBridge 143:86740a56073b 3314 #define CMT_CMD4_SB_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3315 #define CMT_CMD4_SB_SHIFT (0U)
AnnaBridge 143:86740a56073b 3316 #define CMT_CMD4_SB(x) (((uint8_t)(((uint8_t)(x)) << CMT_CMD4_SB_SHIFT)) & CMT_CMD4_SB_MASK)
AnnaBridge 143:86740a56073b 3317
AnnaBridge 143:86740a56073b 3318 /*! @name PPS - CMT Primary Prescaler Register */
AnnaBridge 143:86740a56073b 3319 #define CMT_PPS_PPSDIV_MASK (0xFU)
AnnaBridge 143:86740a56073b 3320 #define CMT_PPS_PPSDIV_SHIFT (0U)
AnnaBridge 143:86740a56073b 3321 #define CMT_PPS_PPSDIV(x) (((uint8_t)(((uint8_t)(x)) << CMT_PPS_PPSDIV_SHIFT)) & CMT_PPS_PPSDIV_MASK)
AnnaBridge 143:86740a56073b 3322
AnnaBridge 143:86740a56073b 3323 /*! @name DMA - CMT Direct Memory Access Register */
AnnaBridge 143:86740a56073b 3324 #define CMT_DMA_DMA_MASK (0x1U)
AnnaBridge 143:86740a56073b 3325 #define CMT_DMA_DMA_SHIFT (0U)
AnnaBridge 143:86740a56073b 3326 #define CMT_DMA_DMA(x) (((uint8_t)(((uint8_t)(x)) << CMT_DMA_DMA_SHIFT)) & CMT_DMA_DMA_MASK)
AnnaBridge 143:86740a56073b 3327
AnnaBridge 143:86740a56073b 3328
AnnaBridge 143:86740a56073b 3329 /*!
AnnaBridge 143:86740a56073b 3330 * @}
AnnaBridge 143:86740a56073b 3331 */ /* end of group CMT_Register_Masks */
AnnaBridge 143:86740a56073b 3332
AnnaBridge 143:86740a56073b 3333
AnnaBridge 143:86740a56073b 3334 /* CMT - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 3335 /** Peripheral CMT base address */
AnnaBridge 143:86740a56073b 3336 #define CMT_BASE (0x40062000u)
AnnaBridge 143:86740a56073b 3337 /** Peripheral CMT base pointer */
AnnaBridge 143:86740a56073b 3338 #define CMT ((CMT_Type *)CMT_BASE)
AnnaBridge 143:86740a56073b 3339 /** Array initializer of CMT peripheral base addresses */
AnnaBridge 143:86740a56073b 3340 #define CMT_BASE_ADDRS { CMT_BASE }
AnnaBridge 143:86740a56073b 3341 /** Array initializer of CMT peripheral base pointers */
AnnaBridge 143:86740a56073b 3342 #define CMT_BASE_PTRS { CMT }
AnnaBridge 143:86740a56073b 3343 /** Interrupt vectors for the CMT peripheral type */
AnnaBridge 143:86740a56073b 3344 #define CMT_IRQS { CMT_IRQn }
AnnaBridge 143:86740a56073b 3345
AnnaBridge 143:86740a56073b 3346 /*!
AnnaBridge 143:86740a56073b 3347 * @}
AnnaBridge 143:86740a56073b 3348 */ /* end of group CMT_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 3349
AnnaBridge 143:86740a56073b 3350
AnnaBridge 143:86740a56073b 3351 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3352 -- CRC Peripheral Access Layer
AnnaBridge 143:86740a56073b 3353 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3354
AnnaBridge 143:86740a56073b 3355 /*!
AnnaBridge 143:86740a56073b 3356 * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
AnnaBridge 143:86740a56073b 3357 * @{
AnnaBridge 143:86740a56073b 3358 */
AnnaBridge 143:86740a56073b 3359
AnnaBridge 143:86740a56073b 3360 /** CRC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 3361 typedef struct {
AnnaBridge 143:86740a56073b 3362 union { /* offset: 0x0 */
AnnaBridge 143:86740a56073b 3363 struct { /* offset: 0x0 */
AnnaBridge 143:86740a56073b 3364 __IO uint16_t DATAL; /**< CRC_DATAL register., offset: 0x0 */
AnnaBridge 143:86740a56073b 3365 __IO uint16_t DATAH; /**< CRC_DATAH register., offset: 0x2 */
AnnaBridge 143:86740a56073b 3366 } ACCESS16BIT;
AnnaBridge 143:86740a56073b 3367 __IO uint32_t DATA; /**< CRC Data register, offset: 0x0 */
AnnaBridge 143:86740a56073b 3368 struct { /* offset: 0x0 */
AnnaBridge 143:86740a56073b 3369 __IO uint8_t DATALL; /**< CRC_DATALL register., offset: 0x0 */
AnnaBridge 143:86740a56073b 3370 __IO uint8_t DATALU; /**< CRC_DATALU register., offset: 0x1 */
AnnaBridge 143:86740a56073b 3371 __IO uint8_t DATAHL; /**< CRC_DATAHL register., offset: 0x2 */
AnnaBridge 143:86740a56073b 3372 __IO uint8_t DATAHU; /**< CRC_DATAHU register., offset: 0x3 */
AnnaBridge 143:86740a56073b 3373 } ACCESS8BIT;
AnnaBridge 143:86740a56073b 3374 };
AnnaBridge 143:86740a56073b 3375 union { /* offset: 0x4 */
AnnaBridge 143:86740a56073b 3376 struct { /* offset: 0x4 */
AnnaBridge 143:86740a56073b 3377 __IO uint16_t GPOLYL; /**< CRC_GPOLYL register., offset: 0x4 */
AnnaBridge 143:86740a56073b 3378 __IO uint16_t GPOLYH; /**< CRC_GPOLYH register., offset: 0x6 */
AnnaBridge 143:86740a56073b 3379 } GPOLY_ACCESS16BIT;
AnnaBridge 143:86740a56073b 3380 __IO uint32_t GPOLY; /**< CRC Polynomial register, offset: 0x4 */
AnnaBridge 143:86740a56073b 3381 struct { /* offset: 0x4 */
AnnaBridge 143:86740a56073b 3382 __IO uint8_t GPOLYLL; /**< CRC_GPOLYLL register., offset: 0x4 */
AnnaBridge 143:86740a56073b 3383 __IO uint8_t GPOLYLU; /**< CRC_GPOLYLU register., offset: 0x5 */
AnnaBridge 143:86740a56073b 3384 __IO uint8_t GPOLYHL; /**< CRC_GPOLYHL register., offset: 0x6 */
AnnaBridge 143:86740a56073b 3385 __IO uint8_t GPOLYHU; /**< CRC_GPOLYHU register., offset: 0x7 */
AnnaBridge 143:86740a56073b 3386 } GPOLY_ACCESS8BIT;
AnnaBridge 143:86740a56073b 3387 };
AnnaBridge 143:86740a56073b 3388 union { /* offset: 0x8 */
AnnaBridge 143:86740a56073b 3389 __IO uint32_t CTRL; /**< CRC Control register, offset: 0x8 */
AnnaBridge 143:86740a56073b 3390 struct { /* offset: 0x8 */
AnnaBridge 143:86740a56073b 3391 uint8_t RESERVED_0[3];
AnnaBridge 143:86740a56073b 3392 __IO uint8_t CTRLHU; /**< CRC_CTRLHU register., offset: 0xB */
AnnaBridge 143:86740a56073b 3393 } CTRL_ACCESS8BIT;
AnnaBridge 143:86740a56073b 3394 };
AnnaBridge 143:86740a56073b 3395 } CRC_Type;
AnnaBridge 143:86740a56073b 3396
AnnaBridge 143:86740a56073b 3397 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3398 -- CRC Register Masks
AnnaBridge 143:86740a56073b 3399 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3400
AnnaBridge 143:86740a56073b 3401 /*!
AnnaBridge 143:86740a56073b 3402 * @addtogroup CRC_Register_Masks CRC Register Masks
AnnaBridge 143:86740a56073b 3403 * @{
AnnaBridge 143:86740a56073b 3404 */
AnnaBridge 143:86740a56073b 3405
AnnaBridge 143:86740a56073b 3406 /*! @name DATAL - CRC_DATAL register. */
AnnaBridge 143:86740a56073b 3407 #define CRC_DATAL_DATAL_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 3408 #define CRC_DATAL_DATAL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3409 #define CRC_DATAL_DATAL(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAL_DATAL_SHIFT)) & CRC_DATAL_DATAL_MASK)
AnnaBridge 143:86740a56073b 3410
AnnaBridge 143:86740a56073b 3411 /*! @name DATAH - CRC_DATAH register. */
AnnaBridge 143:86740a56073b 3412 #define CRC_DATAH_DATAH_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 3413 #define CRC_DATAH_DATAH_SHIFT (0U)
AnnaBridge 143:86740a56073b 3414 #define CRC_DATAH_DATAH(x) (((uint16_t)(((uint16_t)(x)) << CRC_DATAH_DATAH_SHIFT)) & CRC_DATAH_DATAH_MASK)
AnnaBridge 143:86740a56073b 3415
AnnaBridge 143:86740a56073b 3416 /*! @name DATA - CRC Data register */
AnnaBridge 143:86740a56073b 3417 #define CRC_DATA_LL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3418 #define CRC_DATA_LL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3419 #define CRC_DATA_LL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LL_SHIFT)) & CRC_DATA_LL_MASK)
AnnaBridge 143:86740a56073b 3420 #define CRC_DATA_LU_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 3421 #define CRC_DATA_LU_SHIFT (8U)
AnnaBridge 143:86740a56073b 3422 #define CRC_DATA_LU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_LU_SHIFT)) & CRC_DATA_LU_MASK)
AnnaBridge 143:86740a56073b 3423 #define CRC_DATA_HL_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 3424 #define CRC_DATA_HL_SHIFT (16U)
AnnaBridge 143:86740a56073b 3425 #define CRC_DATA_HL(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HL_SHIFT)) & CRC_DATA_HL_MASK)
AnnaBridge 143:86740a56073b 3426 #define CRC_DATA_HU_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 3427 #define CRC_DATA_HU_SHIFT (24U)
AnnaBridge 143:86740a56073b 3428 #define CRC_DATA_HU(x) (((uint32_t)(((uint32_t)(x)) << CRC_DATA_HU_SHIFT)) & CRC_DATA_HU_MASK)
AnnaBridge 143:86740a56073b 3429
AnnaBridge 143:86740a56073b 3430 /*! @name DATALL - CRC_DATALL register. */
AnnaBridge 143:86740a56073b 3431 #define CRC_DATALL_DATALL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3432 #define CRC_DATALL_DATALL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3433 #define CRC_DATALL_DATALL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALL_DATALL_SHIFT)) & CRC_DATALL_DATALL_MASK)
AnnaBridge 143:86740a56073b 3434
AnnaBridge 143:86740a56073b 3435 /*! @name DATALU - CRC_DATALU register. */
AnnaBridge 143:86740a56073b 3436 #define CRC_DATALU_DATALU_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3437 #define CRC_DATALU_DATALU_SHIFT (0U)
AnnaBridge 143:86740a56073b 3438 #define CRC_DATALU_DATALU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATALU_DATALU_SHIFT)) & CRC_DATALU_DATALU_MASK)
AnnaBridge 143:86740a56073b 3439
AnnaBridge 143:86740a56073b 3440 /*! @name DATAHL - CRC_DATAHL register. */
AnnaBridge 143:86740a56073b 3441 #define CRC_DATAHL_DATAHL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3442 #define CRC_DATAHL_DATAHL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3443 #define CRC_DATAHL_DATAHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHL_DATAHL_SHIFT)) & CRC_DATAHL_DATAHL_MASK)
AnnaBridge 143:86740a56073b 3444
AnnaBridge 143:86740a56073b 3445 /*! @name DATAHU - CRC_DATAHU register. */
AnnaBridge 143:86740a56073b 3446 #define CRC_DATAHU_DATAHU_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3447 #define CRC_DATAHU_DATAHU_SHIFT (0U)
AnnaBridge 143:86740a56073b 3448 #define CRC_DATAHU_DATAHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_DATAHU_DATAHU_SHIFT)) & CRC_DATAHU_DATAHU_MASK)
AnnaBridge 143:86740a56073b 3449
AnnaBridge 143:86740a56073b 3450 /*! @name GPOLYL - CRC_GPOLYL register. */
AnnaBridge 143:86740a56073b 3451 #define CRC_GPOLYL_GPOLYL_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 3452 #define CRC_GPOLYL_GPOLYL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3453 #define CRC_GPOLYL_GPOLYL(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYL_GPOLYL_SHIFT)) & CRC_GPOLYL_GPOLYL_MASK)
AnnaBridge 143:86740a56073b 3454
AnnaBridge 143:86740a56073b 3455 /*! @name GPOLYH - CRC_GPOLYH register. */
AnnaBridge 143:86740a56073b 3456 #define CRC_GPOLYH_GPOLYH_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 3457 #define CRC_GPOLYH_GPOLYH_SHIFT (0U)
AnnaBridge 143:86740a56073b 3458 #define CRC_GPOLYH_GPOLYH(x) (((uint16_t)(((uint16_t)(x)) << CRC_GPOLYH_GPOLYH_SHIFT)) & CRC_GPOLYH_GPOLYH_MASK)
AnnaBridge 143:86740a56073b 3459
AnnaBridge 143:86740a56073b 3460 /*! @name GPOLY - CRC Polynomial register */
AnnaBridge 143:86740a56073b 3461 #define CRC_GPOLY_LOW_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 3462 #define CRC_GPOLY_LOW_SHIFT (0U)
AnnaBridge 143:86740a56073b 3463 #define CRC_GPOLY_LOW(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_LOW_SHIFT)) & CRC_GPOLY_LOW_MASK)
AnnaBridge 143:86740a56073b 3464 #define CRC_GPOLY_HIGH_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 3465 #define CRC_GPOLY_HIGH_SHIFT (16U)
AnnaBridge 143:86740a56073b 3466 #define CRC_GPOLY_HIGH(x) (((uint32_t)(((uint32_t)(x)) << CRC_GPOLY_HIGH_SHIFT)) & CRC_GPOLY_HIGH_MASK)
AnnaBridge 143:86740a56073b 3467
AnnaBridge 143:86740a56073b 3468 /*! @name GPOLYLL - CRC_GPOLYLL register. */
AnnaBridge 143:86740a56073b 3469 #define CRC_GPOLYLL_GPOLYLL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3470 #define CRC_GPOLYLL_GPOLYLL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3471 #define CRC_GPOLYLL_GPOLYLL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLL_GPOLYLL_SHIFT)) & CRC_GPOLYLL_GPOLYLL_MASK)
AnnaBridge 143:86740a56073b 3472
AnnaBridge 143:86740a56073b 3473 /*! @name GPOLYLU - CRC_GPOLYLU register. */
AnnaBridge 143:86740a56073b 3474 #define CRC_GPOLYLU_GPOLYLU_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3475 #define CRC_GPOLYLU_GPOLYLU_SHIFT (0U)
AnnaBridge 143:86740a56073b 3476 #define CRC_GPOLYLU_GPOLYLU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYLU_GPOLYLU_SHIFT)) & CRC_GPOLYLU_GPOLYLU_MASK)
AnnaBridge 143:86740a56073b 3477
AnnaBridge 143:86740a56073b 3478 /*! @name GPOLYHL - CRC_GPOLYHL register. */
AnnaBridge 143:86740a56073b 3479 #define CRC_GPOLYHL_GPOLYHL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3480 #define CRC_GPOLYHL_GPOLYHL_SHIFT (0U)
AnnaBridge 143:86740a56073b 3481 #define CRC_GPOLYHL_GPOLYHL(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHL_GPOLYHL_SHIFT)) & CRC_GPOLYHL_GPOLYHL_MASK)
AnnaBridge 143:86740a56073b 3482
AnnaBridge 143:86740a56073b 3483 /*! @name GPOLYHU - CRC_GPOLYHU register. */
AnnaBridge 143:86740a56073b 3484 #define CRC_GPOLYHU_GPOLYHU_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3485 #define CRC_GPOLYHU_GPOLYHU_SHIFT (0U)
AnnaBridge 143:86740a56073b 3486 #define CRC_GPOLYHU_GPOLYHU(x) (((uint8_t)(((uint8_t)(x)) << CRC_GPOLYHU_GPOLYHU_SHIFT)) & CRC_GPOLYHU_GPOLYHU_MASK)
AnnaBridge 143:86740a56073b 3487
AnnaBridge 143:86740a56073b 3488 /*! @name CTRL - CRC Control register */
AnnaBridge 143:86740a56073b 3489 #define CRC_CTRL_TCRC_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 3490 #define CRC_CTRL_TCRC_SHIFT (24U)
AnnaBridge 143:86740a56073b 3491 #define CRC_CTRL_TCRC(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TCRC_SHIFT)) & CRC_CTRL_TCRC_MASK)
AnnaBridge 143:86740a56073b 3492 #define CRC_CTRL_WAS_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 3493 #define CRC_CTRL_WAS_SHIFT (25U)
AnnaBridge 143:86740a56073b 3494 #define CRC_CTRL_WAS(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_WAS_SHIFT)) & CRC_CTRL_WAS_MASK)
AnnaBridge 143:86740a56073b 3495 #define CRC_CTRL_FXOR_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 3496 #define CRC_CTRL_FXOR_SHIFT (26U)
AnnaBridge 143:86740a56073b 3497 #define CRC_CTRL_FXOR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_FXOR_SHIFT)) & CRC_CTRL_FXOR_MASK)
AnnaBridge 143:86740a56073b 3498 #define CRC_CTRL_TOTR_MASK (0x30000000U)
AnnaBridge 143:86740a56073b 3499 #define CRC_CTRL_TOTR_SHIFT (28U)
AnnaBridge 143:86740a56073b 3500 #define CRC_CTRL_TOTR(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOTR_SHIFT)) & CRC_CTRL_TOTR_MASK)
AnnaBridge 143:86740a56073b 3501 #define CRC_CTRL_TOT_MASK (0xC0000000U)
AnnaBridge 143:86740a56073b 3502 #define CRC_CTRL_TOT_SHIFT (30U)
AnnaBridge 143:86740a56073b 3503 #define CRC_CTRL_TOT(x) (((uint32_t)(((uint32_t)(x)) << CRC_CTRL_TOT_SHIFT)) & CRC_CTRL_TOT_MASK)
AnnaBridge 143:86740a56073b 3504
AnnaBridge 143:86740a56073b 3505 /*! @name CTRLHU - CRC_CTRLHU register. */
AnnaBridge 143:86740a56073b 3506 #define CRC_CTRLHU_TCRC_MASK (0x1U)
AnnaBridge 143:86740a56073b 3507 #define CRC_CTRLHU_TCRC_SHIFT (0U)
AnnaBridge 143:86740a56073b 3508 #define CRC_CTRLHU_TCRC(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TCRC_SHIFT)) & CRC_CTRLHU_TCRC_MASK)
AnnaBridge 143:86740a56073b 3509 #define CRC_CTRLHU_WAS_MASK (0x2U)
AnnaBridge 143:86740a56073b 3510 #define CRC_CTRLHU_WAS_SHIFT (1U)
AnnaBridge 143:86740a56073b 3511 #define CRC_CTRLHU_WAS(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_WAS_SHIFT)) & CRC_CTRLHU_WAS_MASK)
AnnaBridge 143:86740a56073b 3512 #define CRC_CTRLHU_FXOR_MASK (0x4U)
AnnaBridge 143:86740a56073b 3513 #define CRC_CTRLHU_FXOR_SHIFT (2U)
AnnaBridge 143:86740a56073b 3514 #define CRC_CTRLHU_FXOR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_FXOR_SHIFT)) & CRC_CTRLHU_FXOR_MASK)
AnnaBridge 143:86740a56073b 3515 #define CRC_CTRLHU_TOTR_MASK (0x30U)
AnnaBridge 143:86740a56073b 3516 #define CRC_CTRLHU_TOTR_SHIFT (4U)
AnnaBridge 143:86740a56073b 3517 #define CRC_CTRLHU_TOTR(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOTR_SHIFT)) & CRC_CTRLHU_TOTR_MASK)
AnnaBridge 143:86740a56073b 3518 #define CRC_CTRLHU_TOT_MASK (0xC0U)
AnnaBridge 143:86740a56073b 3519 #define CRC_CTRLHU_TOT_SHIFT (6U)
AnnaBridge 143:86740a56073b 3520 #define CRC_CTRLHU_TOT(x) (((uint8_t)(((uint8_t)(x)) << CRC_CTRLHU_TOT_SHIFT)) & CRC_CTRLHU_TOT_MASK)
AnnaBridge 143:86740a56073b 3521
AnnaBridge 143:86740a56073b 3522
AnnaBridge 143:86740a56073b 3523 /*!
AnnaBridge 143:86740a56073b 3524 * @}
AnnaBridge 143:86740a56073b 3525 */ /* end of group CRC_Register_Masks */
AnnaBridge 143:86740a56073b 3526
AnnaBridge 143:86740a56073b 3527
AnnaBridge 143:86740a56073b 3528 /* CRC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 3529 /** Peripheral CRC base address */
AnnaBridge 143:86740a56073b 3530 #define CRC_BASE (0x40032000u)
AnnaBridge 143:86740a56073b 3531 /** Peripheral CRC base pointer */
AnnaBridge 143:86740a56073b 3532 #define CRC0 ((CRC_Type *)CRC_BASE)
AnnaBridge 143:86740a56073b 3533 /** Array initializer of CRC peripheral base addresses */
AnnaBridge 143:86740a56073b 3534 #define CRC_BASE_ADDRS { CRC_BASE }
AnnaBridge 143:86740a56073b 3535 /** Array initializer of CRC peripheral base pointers */
AnnaBridge 143:86740a56073b 3536 #define CRC_BASE_PTRS { CRC0 }
AnnaBridge 143:86740a56073b 3537
AnnaBridge 143:86740a56073b 3538 /*!
AnnaBridge 143:86740a56073b 3539 * @}
AnnaBridge 143:86740a56073b 3540 */ /* end of group CRC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 3541
AnnaBridge 143:86740a56073b 3542
AnnaBridge 143:86740a56073b 3543 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3544 -- DAC Peripheral Access Layer
AnnaBridge 143:86740a56073b 3545 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3546
AnnaBridge 143:86740a56073b 3547 /*!
AnnaBridge 143:86740a56073b 3548 * @addtogroup DAC_Peripheral_Access_Layer DAC Peripheral Access Layer
AnnaBridge 143:86740a56073b 3549 * @{
AnnaBridge 143:86740a56073b 3550 */
AnnaBridge 143:86740a56073b 3551
AnnaBridge 143:86740a56073b 3552 /** DAC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 3553 typedef struct {
AnnaBridge 143:86740a56073b 3554 struct { /* offset: 0x0, array step: 0x2 */
AnnaBridge 143:86740a56073b 3555 __IO uint8_t DATL; /**< DAC Data Low Register, array offset: 0x0, array step: 0x2 */
AnnaBridge 143:86740a56073b 3556 __IO uint8_t DATH; /**< DAC Data High Register, array offset: 0x1, array step: 0x2 */
AnnaBridge 143:86740a56073b 3557 } DAT[16];
AnnaBridge 143:86740a56073b 3558 __IO uint8_t SR; /**< DAC Status Register, offset: 0x20 */
AnnaBridge 143:86740a56073b 3559 __IO uint8_t C0; /**< DAC Control Register, offset: 0x21 */
AnnaBridge 143:86740a56073b 3560 __IO uint8_t C1; /**< DAC Control Register 1, offset: 0x22 */
AnnaBridge 143:86740a56073b 3561 __IO uint8_t C2; /**< DAC Control Register 2, offset: 0x23 */
AnnaBridge 143:86740a56073b 3562 } DAC_Type;
AnnaBridge 143:86740a56073b 3563
AnnaBridge 143:86740a56073b 3564 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3565 -- DAC Register Masks
AnnaBridge 143:86740a56073b 3566 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3567
AnnaBridge 143:86740a56073b 3568 /*!
AnnaBridge 143:86740a56073b 3569 * @addtogroup DAC_Register_Masks DAC Register Masks
AnnaBridge 143:86740a56073b 3570 * @{
AnnaBridge 143:86740a56073b 3571 */
AnnaBridge 143:86740a56073b 3572
AnnaBridge 143:86740a56073b 3573 /*! @name DATL - DAC Data Low Register */
AnnaBridge 143:86740a56073b 3574 #define DAC_DATL_DATA0_MASK (0xFFU)
AnnaBridge 143:86740a56073b 3575 #define DAC_DATL_DATA0_SHIFT (0U)
AnnaBridge 143:86740a56073b 3576 #define DAC_DATL_DATA0(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATL_DATA0_SHIFT)) & DAC_DATL_DATA0_MASK)
AnnaBridge 143:86740a56073b 3577
AnnaBridge 143:86740a56073b 3578 /* The count of DAC_DATL */
AnnaBridge 143:86740a56073b 3579 #define DAC_DATL_COUNT (16U)
AnnaBridge 143:86740a56073b 3580
AnnaBridge 143:86740a56073b 3581 /*! @name DATH - DAC Data High Register */
AnnaBridge 143:86740a56073b 3582 #define DAC_DATH_DATA1_MASK (0xFU)
AnnaBridge 143:86740a56073b 3583 #define DAC_DATH_DATA1_SHIFT (0U)
AnnaBridge 143:86740a56073b 3584 #define DAC_DATH_DATA1(x) (((uint8_t)(((uint8_t)(x)) << DAC_DATH_DATA1_SHIFT)) & DAC_DATH_DATA1_MASK)
AnnaBridge 143:86740a56073b 3585
AnnaBridge 143:86740a56073b 3586 /* The count of DAC_DATH */
AnnaBridge 143:86740a56073b 3587 #define DAC_DATH_COUNT (16U)
AnnaBridge 143:86740a56073b 3588
AnnaBridge 143:86740a56073b 3589 /*! @name SR - DAC Status Register */
AnnaBridge 143:86740a56073b 3590 #define DAC_SR_DACBFRPBF_MASK (0x1U)
AnnaBridge 143:86740a56073b 3591 #define DAC_SR_DACBFRPBF_SHIFT (0U)
AnnaBridge 143:86740a56073b 3592 #define DAC_SR_DACBFRPBF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPBF_SHIFT)) & DAC_SR_DACBFRPBF_MASK)
AnnaBridge 143:86740a56073b 3593 #define DAC_SR_DACBFRPTF_MASK (0x2U)
AnnaBridge 143:86740a56073b 3594 #define DAC_SR_DACBFRPTF_SHIFT (1U)
AnnaBridge 143:86740a56073b 3595 #define DAC_SR_DACBFRPTF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFRPTF_SHIFT)) & DAC_SR_DACBFRPTF_MASK)
AnnaBridge 143:86740a56073b 3596 #define DAC_SR_DACBFWMF_MASK (0x4U)
AnnaBridge 143:86740a56073b 3597 #define DAC_SR_DACBFWMF_SHIFT (2U)
AnnaBridge 143:86740a56073b 3598 #define DAC_SR_DACBFWMF(x) (((uint8_t)(((uint8_t)(x)) << DAC_SR_DACBFWMF_SHIFT)) & DAC_SR_DACBFWMF_MASK)
AnnaBridge 143:86740a56073b 3599
AnnaBridge 143:86740a56073b 3600 /*! @name C0 - DAC Control Register */
AnnaBridge 143:86740a56073b 3601 #define DAC_C0_DACBBIEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 3602 #define DAC_C0_DACBBIEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 3603 #define DAC_C0_DACBBIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBBIEN_SHIFT)) & DAC_C0_DACBBIEN_MASK)
AnnaBridge 143:86740a56073b 3604 #define DAC_C0_DACBTIEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 3605 #define DAC_C0_DACBTIEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 3606 #define DAC_C0_DACBTIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBTIEN_SHIFT)) & DAC_C0_DACBTIEN_MASK)
AnnaBridge 143:86740a56073b 3607 #define DAC_C0_DACBWIEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 3608 #define DAC_C0_DACBWIEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 3609 #define DAC_C0_DACBWIEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACBWIEN_SHIFT)) & DAC_C0_DACBWIEN_MASK)
AnnaBridge 143:86740a56073b 3610 #define DAC_C0_LPEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 3611 #define DAC_C0_LPEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 3612 #define DAC_C0_LPEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_LPEN_SHIFT)) & DAC_C0_LPEN_MASK)
AnnaBridge 143:86740a56073b 3613 #define DAC_C0_DACSWTRG_MASK (0x10U)
AnnaBridge 143:86740a56073b 3614 #define DAC_C0_DACSWTRG_SHIFT (4U)
AnnaBridge 143:86740a56073b 3615 #define DAC_C0_DACSWTRG(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACSWTRG_SHIFT)) & DAC_C0_DACSWTRG_MASK)
AnnaBridge 143:86740a56073b 3616 #define DAC_C0_DACTRGSEL_MASK (0x20U)
AnnaBridge 143:86740a56073b 3617 #define DAC_C0_DACTRGSEL_SHIFT (5U)
AnnaBridge 143:86740a56073b 3618 #define DAC_C0_DACTRGSEL(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACTRGSEL_SHIFT)) & DAC_C0_DACTRGSEL_MASK)
AnnaBridge 143:86740a56073b 3619 #define DAC_C0_DACRFS_MASK (0x40U)
AnnaBridge 143:86740a56073b 3620 #define DAC_C0_DACRFS_SHIFT (6U)
AnnaBridge 143:86740a56073b 3621 #define DAC_C0_DACRFS(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACRFS_SHIFT)) & DAC_C0_DACRFS_MASK)
AnnaBridge 143:86740a56073b 3622 #define DAC_C0_DACEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 3623 #define DAC_C0_DACEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 3624 #define DAC_C0_DACEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C0_DACEN_SHIFT)) & DAC_C0_DACEN_MASK)
AnnaBridge 143:86740a56073b 3625
AnnaBridge 143:86740a56073b 3626 /*! @name C1 - DAC Control Register 1 */
AnnaBridge 143:86740a56073b 3627 #define DAC_C1_DACBFEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 3628 #define DAC_C1_DACBFEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 3629 #define DAC_C1_DACBFEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFEN_SHIFT)) & DAC_C1_DACBFEN_MASK)
AnnaBridge 143:86740a56073b 3630 #define DAC_C1_DACBFMD_MASK (0x6U)
AnnaBridge 143:86740a56073b 3631 #define DAC_C1_DACBFMD_SHIFT (1U)
AnnaBridge 143:86740a56073b 3632 #define DAC_C1_DACBFMD(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFMD_SHIFT)) & DAC_C1_DACBFMD_MASK)
AnnaBridge 143:86740a56073b 3633 #define DAC_C1_DACBFWM_MASK (0x18U)
AnnaBridge 143:86740a56073b 3634 #define DAC_C1_DACBFWM_SHIFT (3U)
AnnaBridge 143:86740a56073b 3635 #define DAC_C1_DACBFWM(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DACBFWM_SHIFT)) & DAC_C1_DACBFWM_MASK)
AnnaBridge 143:86740a56073b 3636 #define DAC_C1_DMAEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 3637 #define DAC_C1_DMAEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 3638 #define DAC_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << DAC_C1_DMAEN_SHIFT)) & DAC_C1_DMAEN_MASK)
AnnaBridge 143:86740a56073b 3639
AnnaBridge 143:86740a56073b 3640 /*! @name C2 - DAC Control Register 2 */
AnnaBridge 143:86740a56073b 3641 #define DAC_C2_DACBFUP_MASK (0xFU)
AnnaBridge 143:86740a56073b 3642 #define DAC_C2_DACBFUP_SHIFT (0U)
AnnaBridge 143:86740a56073b 3643 #define DAC_C2_DACBFUP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFUP_SHIFT)) & DAC_C2_DACBFUP_MASK)
AnnaBridge 143:86740a56073b 3644 #define DAC_C2_DACBFRP_MASK (0xF0U)
AnnaBridge 143:86740a56073b 3645 #define DAC_C2_DACBFRP_SHIFT (4U)
AnnaBridge 143:86740a56073b 3646 #define DAC_C2_DACBFRP(x) (((uint8_t)(((uint8_t)(x)) << DAC_C2_DACBFRP_SHIFT)) & DAC_C2_DACBFRP_MASK)
AnnaBridge 143:86740a56073b 3647
AnnaBridge 143:86740a56073b 3648
AnnaBridge 143:86740a56073b 3649 /*!
AnnaBridge 143:86740a56073b 3650 * @}
AnnaBridge 143:86740a56073b 3651 */ /* end of group DAC_Register_Masks */
AnnaBridge 143:86740a56073b 3652
AnnaBridge 143:86740a56073b 3653
AnnaBridge 143:86740a56073b 3654 /* DAC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 3655 /** Peripheral DAC0 base address */
AnnaBridge 143:86740a56073b 3656 #define DAC0_BASE (0x400CC000u)
AnnaBridge 143:86740a56073b 3657 /** Peripheral DAC0 base pointer */
AnnaBridge 143:86740a56073b 3658 #define DAC0 ((DAC_Type *)DAC0_BASE)
AnnaBridge 143:86740a56073b 3659 /** Peripheral DAC1 base address */
AnnaBridge 143:86740a56073b 3660 #define DAC1_BASE (0x400CD000u)
AnnaBridge 143:86740a56073b 3661 /** Peripheral DAC1 base pointer */
AnnaBridge 143:86740a56073b 3662 #define DAC1 ((DAC_Type *)DAC1_BASE)
AnnaBridge 143:86740a56073b 3663 /** Array initializer of DAC peripheral base addresses */
AnnaBridge 143:86740a56073b 3664 #define DAC_BASE_ADDRS { DAC0_BASE, DAC1_BASE }
AnnaBridge 143:86740a56073b 3665 /** Array initializer of DAC peripheral base pointers */
AnnaBridge 143:86740a56073b 3666 #define DAC_BASE_PTRS { DAC0, DAC1 }
AnnaBridge 143:86740a56073b 3667 /** Interrupt vectors for the DAC peripheral type */
AnnaBridge 143:86740a56073b 3668 #define DAC_IRQS { DAC0_IRQn, DAC1_IRQn }
AnnaBridge 143:86740a56073b 3669
AnnaBridge 143:86740a56073b 3670 /*!
AnnaBridge 143:86740a56073b 3671 * @}
AnnaBridge 143:86740a56073b 3672 */ /* end of group DAC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 3673
AnnaBridge 143:86740a56073b 3674
AnnaBridge 143:86740a56073b 3675 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3676 -- DMA Peripheral Access Layer
AnnaBridge 143:86740a56073b 3677 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3678
AnnaBridge 143:86740a56073b 3679 /*!
AnnaBridge 143:86740a56073b 3680 * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
AnnaBridge 143:86740a56073b 3681 * @{
AnnaBridge 143:86740a56073b 3682 */
AnnaBridge 143:86740a56073b 3683
AnnaBridge 143:86740a56073b 3684 /** DMA - Register Layout Typedef */
AnnaBridge 143:86740a56073b 3685 typedef struct {
AnnaBridge 143:86740a56073b 3686 __IO uint32_t CR; /**< Control Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 3687 __I uint32_t ES; /**< Error Status Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 3688 uint8_t RESERVED_0[4];
AnnaBridge 143:86740a56073b 3689 __IO uint32_t ERQ; /**< Enable Request Register, offset: 0xC */
AnnaBridge 143:86740a56073b 3690 uint8_t RESERVED_1[4];
AnnaBridge 143:86740a56073b 3691 __IO uint32_t EEI; /**< Enable Error Interrupt Register, offset: 0x14 */
AnnaBridge 143:86740a56073b 3692 __O uint8_t CEEI; /**< Clear Enable Error Interrupt Register, offset: 0x18 */
AnnaBridge 143:86740a56073b 3693 __O uint8_t SEEI; /**< Set Enable Error Interrupt Register, offset: 0x19 */
AnnaBridge 143:86740a56073b 3694 __O uint8_t CERQ; /**< Clear Enable Request Register, offset: 0x1A */
AnnaBridge 143:86740a56073b 3695 __O uint8_t SERQ; /**< Set Enable Request Register, offset: 0x1B */
AnnaBridge 143:86740a56073b 3696 __O uint8_t CDNE; /**< Clear DONE Status Bit Register, offset: 0x1C */
AnnaBridge 143:86740a56073b 3697 __O uint8_t SSRT; /**< Set START Bit Register, offset: 0x1D */
AnnaBridge 143:86740a56073b 3698 __O uint8_t CERR; /**< Clear Error Register, offset: 0x1E */
AnnaBridge 143:86740a56073b 3699 __O uint8_t CINT; /**< Clear Interrupt Request Register, offset: 0x1F */
AnnaBridge 143:86740a56073b 3700 uint8_t RESERVED_2[4];
AnnaBridge 143:86740a56073b 3701 __IO uint32_t INT; /**< Interrupt Request Register, offset: 0x24 */
AnnaBridge 143:86740a56073b 3702 uint8_t RESERVED_3[4];
AnnaBridge 143:86740a56073b 3703 __IO uint32_t ERR; /**< Error Register, offset: 0x2C */
AnnaBridge 143:86740a56073b 3704 uint8_t RESERVED_4[4];
AnnaBridge 143:86740a56073b 3705 __I uint32_t HRS; /**< Hardware Request Status Register, offset: 0x34 */
AnnaBridge 143:86740a56073b 3706 uint8_t RESERVED_5[200];
AnnaBridge 143:86740a56073b 3707 __IO uint8_t DCHPRI3; /**< Channel n Priority Register, offset: 0x100 */
AnnaBridge 143:86740a56073b 3708 __IO uint8_t DCHPRI2; /**< Channel n Priority Register, offset: 0x101 */
AnnaBridge 143:86740a56073b 3709 __IO uint8_t DCHPRI1; /**< Channel n Priority Register, offset: 0x102 */
AnnaBridge 143:86740a56073b 3710 __IO uint8_t DCHPRI0; /**< Channel n Priority Register, offset: 0x103 */
AnnaBridge 143:86740a56073b 3711 __IO uint8_t DCHPRI7; /**< Channel n Priority Register, offset: 0x104 */
AnnaBridge 143:86740a56073b 3712 __IO uint8_t DCHPRI6; /**< Channel n Priority Register, offset: 0x105 */
AnnaBridge 143:86740a56073b 3713 __IO uint8_t DCHPRI5; /**< Channel n Priority Register, offset: 0x106 */
AnnaBridge 143:86740a56073b 3714 __IO uint8_t DCHPRI4; /**< Channel n Priority Register, offset: 0x107 */
AnnaBridge 143:86740a56073b 3715 __IO uint8_t DCHPRI11; /**< Channel n Priority Register, offset: 0x108 */
AnnaBridge 143:86740a56073b 3716 __IO uint8_t DCHPRI10; /**< Channel n Priority Register, offset: 0x109 */
AnnaBridge 143:86740a56073b 3717 __IO uint8_t DCHPRI9; /**< Channel n Priority Register, offset: 0x10A */
AnnaBridge 143:86740a56073b 3718 __IO uint8_t DCHPRI8; /**< Channel n Priority Register, offset: 0x10B */
AnnaBridge 143:86740a56073b 3719 __IO uint8_t DCHPRI15; /**< Channel n Priority Register, offset: 0x10C */
AnnaBridge 143:86740a56073b 3720 __IO uint8_t DCHPRI14; /**< Channel n Priority Register, offset: 0x10D */
AnnaBridge 143:86740a56073b 3721 __IO uint8_t DCHPRI13; /**< Channel n Priority Register, offset: 0x10E */
AnnaBridge 143:86740a56073b 3722 __IO uint8_t DCHPRI12; /**< Channel n Priority Register, offset: 0x10F */
AnnaBridge 143:86740a56073b 3723 uint8_t RESERVED_6[3824];
AnnaBridge 143:86740a56073b 3724 struct { /* offset: 0x1000, array step: 0x20 */
AnnaBridge 143:86740a56073b 3725 __IO uint32_t SADDR; /**< TCD Source Address, array offset: 0x1000, array step: 0x20 */
AnnaBridge 143:86740a56073b 3726 __IO uint16_t SOFF; /**< TCD Signed Source Address Offset, array offset: 0x1004, array step: 0x20 */
AnnaBridge 143:86740a56073b 3727 __IO uint16_t ATTR; /**< TCD Transfer Attributes, array offset: 0x1006, array step: 0x20 */
AnnaBridge 143:86740a56073b 3728 union { /* offset: 0x1008, array step: 0x20 */
AnnaBridge 143:86740a56073b 3729 __IO uint32_t NBYTES_MLNO; /**< TCD Minor Byte Count (Minor Loop Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 143:86740a56073b 3730 __IO uint32_t NBYTES_MLOFFNO; /**< TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 143:86740a56073b 3731 __IO uint32_t NBYTES_MLOFFYES; /**< TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled), array offset: 0x1008, array step: 0x20 */
AnnaBridge 143:86740a56073b 3732 };
AnnaBridge 143:86740a56073b 3733 __IO uint32_t SLAST; /**< TCD Last Source Address Adjustment, array offset: 0x100C, array step: 0x20 */
AnnaBridge 143:86740a56073b 3734 __IO uint32_t DADDR; /**< TCD Destination Address, array offset: 0x1010, array step: 0x20 */
AnnaBridge 143:86740a56073b 3735 __IO uint16_t DOFF; /**< TCD Signed Destination Address Offset, array offset: 0x1014, array step: 0x20 */
AnnaBridge 143:86740a56073b 3736 union { /* offset: 0x1016, array step: 0x20 */
AnnaBridge 143:86740a56073b 3737 __IO uint16_t CITER_ELINKNO; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 143:86740a56073b 3738 __IO uint16_t CITER_ELINKYES; /**< TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x1016, array step: 0x20 */
AnnaBridge 143:86740a56073b 3739 };
AnnaBridge 143:86740a56073b 3740 __IO uint32_t DLAST_SGA; /**< TCD Last Destination Address Adjustment/Scatter Gather Address, array offset: 0x1018, array step: 0x20 */
AnnaBridge 143:86740a56073b 3741 __IO uint16_t CSR; /**< TCD Control and Status, array offset: 0x101C, array step: 0x20 */
AnnaBridge 143:86740a56073b 3742 union { /* offset: 0x101E, array step: 0x20 */
AnnaBridge 143:86740a56073b 3743 __IO uint16_t BITER_ELINKNO; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 143:86740a56073b 3744 __IO uint16_t BITER_ELINKYES; /**< TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled), array offset: 0x101E, array step: 0x20 */
AnnaBridge 143:86740a56073b 3745 };
AnnaBridge 143:86740a56073b 3746 } TCD[16];
AnnaBridge 143:86740a56073b 3747 } DMA_Type;
AnnaBridge 143:86740a56073b 3748
AnnaBridge 143:86740a56073b 3749 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 3750 -- DMA Register Masks
AnnaBridge 143:86740a56073b 3751 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 3752
AnnaBridge 143:86740a56073b 3753 /*!
AnnaBridge 143:86740a56073b 3754 * @addtogroup DMA_Register_Masks DMA Register Masks
AnnaBridge 143:86740a56073b 3755 * @{
AnnaBridge 143:86740a56073b 3756 */
AnnaBridge 143:86740a56073b 3757
AnnaBridge 143:86740a56073b 3758 /*! @name CR - Control Register */
AnnaBridge 143:86740a56073b 3759 #define DMA_CR_EDBG_MASK (0x2U)
AnnaBridge 143:86740a56073b 3760 #define DMA_CR_EDBG_SHIFT (1U)
AnnaBridge 143:86740a56073b 3761 #define DMA_CR_EDBG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EDBG_SHIFT)) & DMA_CR_EDBG_MASK)
AnnaBridge 143:86740a56073b 3762 #define DMA_CR_ERCA_MASK (0x4U)
AnnaBridge 143:86740a56073b 3763 #define DMA_CR_ERCA_SHIFT (2U)
AnnaBridge 143:86740a56073b 3764 #define DMA_CR_ERCA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ERCA_SHIFT)) & DMA_CR_ERCA_MASK)
AnnaBridge 143:86740a56073b 3765 #define DMA_CR_HOE_MASK (0x10U)
AnnaBridge 143:86740a56073b 3766 #define DMA_CR_HOE_SHIFT (4U)
AnnaBridge 143:86740a56073b 3767 #define DMA_CR_HOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HOE_SHIFT)) & DMA_CR_HOE_MASK)
AnnaBridge 143:86740a56073b 3768 #define DMA_CR_HALT_MASK (0x20U)
AnnaBridge 143:86740a56073b 3769 #define DMA_CR_HALT_SHIFT (5U)
AnnaBridge 143:86740a56073b 3770 #define DMA_CR_HALT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_HALT_SHIFT)) & DMA_CR_HALT_MASK)
AnnaBridge 143:86740a56073b 3771 #define DMA_CR_CLM_MASK (0x40U)
AnnaBridge 143:86740a56073b 3772 #define DMA_CR_CLM_SHIFT (6U)
AnnaBridge 143:86740a56073b 3773 #define DMA_CR_CLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CLM_SHIFT)) & DMA_CR_CLM_MASK)
AnnaBridge 143:86740a56073b 3774 #define DMA_CR_EMLM_MASK (0x80U)
AnnaBridge 143:86740a56073b 3775 #define DMA_CR_EMLM_SHIFT (7U)
AnnaBridge 143:86740a56073b 3776 #define DMA_CR_EMLM(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_EMLM_SHIFT)) & DMA_CR_EMLM_MASK)
AnnaBridge 143:86740a56073b 3777 #define DMA_CR_ECX_MASK (0x10000U)
AnnaBridge 143:86740a56073b 3778 #define DMA_CR_ECX_SHIFT (16U)
AnnaBridge 143:86740a56073b 3779 #define DMA_CR_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_ECX_SHIFT)) & DMA_CR_ECX_MASK)
AnnaBridge 143:86740a56073b 3780 #define DMA_CR_CX_MASK (0x20000U)
AnnaBridge 143:86740a56073b 3781 #define DMA_CR_CX_SHIFT (17U)
AnnaBridge 143:86740a56073b 3782 #define DMA_CR_CX(x) (((uint32_t)(((uint32_t)(x)) << DMA_CR_CX_SHIFT)) & DMA_CR_CX_MASK)
AnnaBridge 143:86740a56073b 3783
AnnaBridge 143:86740a56073b 3784 /*! @name ES - Error Status Register */
AnnaBridge 143:86740a56073b 3785 #define DMA_ES_DBE_MASK (0x1U)
AnnaBridge 143:86740a56073b 3786 #define DMA_ES_DBE_SHIFT (0U)
AnnaBridge 143:86740a56073b 3787 #define DMA_ES_DBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DBE_SHIFT)) & DMA_ES_DBE_MASK)
AnnaBridge 143:86740a56073b 3788 #define DMA_ES_SBE_MASK (0x2U)
AnnaBridge 143:86740a56073b 3789 #define DMA_ES_SBE_SHIFT (1U)
AnnaBridge 143:86740a56073b 3790 #define DMA_ES_SBE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SBE_SHIFT)) & DMA_ES_SBE_MASK)
AnnaBridge 143:86740a56073b 3791 #define DMA_ES_SGE_MASK (0x4U)
AnnaBridge 143:86740a56073b 3792 #define DMA_ES_SGE_SHIFT (2U)
AnnaBridge 143:86740a56073b 3793 #define DMA_ES_SGE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SGE_SHIFT)) & DMA_ES_SGE_MASK)
AnnaBridge 143:86740a56073b 3794 #define DMA_ES_NCE_MASK (0x8U)
AnnaBridge 143:86740a56073b 3795 #define DMA_ES_NCE_SHIFT (3U)
AnnaBridge 143:86740a56073b 3796 #define DMA_ES_NCE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_NCE_SHIFT)) & DMA_ES_NCE_MASK)
AnnaBridge 143:86740a56073b 3797 #define DMA_ES_DOE_MASK (0x10U)
AnnaBridge 143:86740a56073b 3798 #define DMA_ES_DOE_SHIFT (4U)
AnnaBridge 143:86740a56073b 3799 #define DMA_ES_DOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DOE_SHIFT)) & DMA_ES_DOE_MASK)
AnnaBridge 143:86740a56073b 3800 #define DMA_ES_DAE_MASK (0x20U)
AnnaBridge 143:86740a56073b 3801 #define DMA_ES_DAE_SHIFT (5U)
AnnaBridge 143:86740a56073b 3802 #define DMA_ES_DAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_DAE_SHIFT)) & DMA_ES_DAE_MASK)
AnnaBridge 143:86740a56073b 3803 #define DMA_ES_SOE_MASK (0x40U)
AnnaBridge 143:86740a56073b 3804 #define DMA_ES_SOE_SHIFT (6U)
AnnaBridge 143:86740a56073b 3805 #define DMA_ES_SOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SOE_SHIFT)) & DMA_ES_SOE_MASK)
AnnaBridge 143:86740a56073b 3806 #define DMA_ES_SAE_MASK (0x80U)
AnnaBridge 143:86740a56073b 3807 #define DMA_ES_SAE_SHIFT (7U)
AnnaBridge 143:86740a56073b 3808 #define DMA_ES_SAE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_SAE_SHIFT)) & DMA_ES_SAE_MASK)
AnnaBridge 143:86740a56073b 3809 #define DMA_ES_ERRCHN_MASK (0xF00U)
AnnaBridge 143:86740a56073b 3810 #define DMA_ES_ERRCHN_SHIFT (8U)
AnnaBridge 143:86740a56073b 3811 #define DMA_ES_ERRCHN(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ERRCHN_SHIFT)) & DMA_ES_ERRCHN_MASK)
AnnaBridge 143:86740a56073b 3812 #define DMA_ES_CPE_MASK (0x4000U)
AnnaBridge 143:86740a56073b 3813 #define DMA_ES_CPE_SHIFT (14U)
AnnaBridge 143:86740a56073b 3814 #define DMA_ES_CPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_CPE_SHIFT)) & DMA_ES_CPE_MASK)
AnnaBridge 143:86740a56073b 3815 #define DMA_ES_ECX_MASK (0x10000U)
AnnaBridge 143:86740a56073b 3816 #define DMA_ES_ECX_SHIFT (16U)
AnnaBridge 143:86740a56073b 3817 #define DMA_ES_ECX(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_ECX_SHIFT)) & DMA_ES_ECX_MASK)
AnnaBridge 143:86740a56073b 3818 #define DMA_ES_VLD_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 3819 #define DMA_ES_VLD_SHIFT (31U)
AnnaBridge 143:86740a56073b 3820 #define DMA_ES_VLD(x) (((uint32_t)(((uint32_t)(x)) << DMA_ES_VLD_SHIFT)) & DMA_ES_VLD_MASK)
AnnaBridge 143:86740a56073b 3821
AnnaBridge 143:86740a56073b 3822 /*! @name ERQ - Enable Request Register */
AnnaBridge 143:86740a56073b 3823 #define DMA_ERQ_ERQ0_MASK (0x1U)
AnnaBridge 143:86740a56073b 3824 #define DMA_ERQ_ERQ0_SHIFT (0U)
AnnaBridge 143:86740a56073b 3825 #define DMA_ERQ_ERQ0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ0_SHIFT)) & DMA_ERQ_ERQ0_MASK)
AnnaBridge 143:86740a56073b 3826 #define DMA_ERQ_ERQ1_MASK (0x2U)
AnnaBridge 143:86740a56073b 3827 #define DMA_ERQ_ERQ1_SHIFT (1U)
AnnaBridge 143:86740a56073b 3828 #define DMA_ERQ_ERQ1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ1_SHIFT)) & DMA_ERQ_ERQ1_MASK)
AnnaBridge 143:86740a56073b 3829 #define DMA_ERQ_ERQ2_MASK (0x4U)
AnnaBridge 143:86740a56073b 3830 #define DMA_ERQ_ERQ2_SHIFT (2U)
AnnaBridge 143:86740a56073b 3831 #define DMA_ERQ_ERQ2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ2_SHIFT)) & DMA_ERQ_ERQ2_MASK)
AnnaBridge 143:86740a56073b 3832 #define DMA_ERQ_ERQ3_MASK (0x8U)
AnnaBridge 143:86740a56073b 3833 #define DMA_ERQ_ERQ3_SHIFT (3U)
AnnaBridge 143:86740a56073b 3834 #define DMA_ERQ_ERQ3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ3_SHIFT)) & DMA_ERQ_ERQ3_MASK)
AnnaBridge 143:86740a56073b 3835 #define DMA_ERQ_ERQ4_MASK (0x10U)
AnnaBridge 143:86740a56073b 3836 #define DMA_ERQ_ERQ4_SHIFT (4U)
AnnaBridge 143:86740a56073b 3837 #define DMA_ERQ_ERQ4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ4_SHIFT)) & DMA_ERQ_ERQ4_MASK)
AnnaBridge 143:86740a56073b 3838 #define DMA_ERQ_ERQ5_MASK (0x20U)
AnnaBridge 143:86740a56073b 3839 #define DMA_ERQ_ERQ5_SHIFT (5U)
AnnaBridge 143:86740a56073b 3840 #define DMA_ERQ_ERQ5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ5_SHIFT)) & DMA_ERQ_ERQ5_MASK)
AnnaBridge 143:86740a56073b 3841 #define DMA_ERQ_ERQ6_MASK (0x40U)
AnnaBridge 143:86740a56073b 3842 #define DMA_ERQ_ERQ6_SHIFT (6U)
AnnaBridge 143:86740a56073b 3843 #define DMA_ERQ_ERQ6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ6_SHIFT)) & DMA_ERQ_ERQ6_MASK)
AnnaBridge 143:86740a56073b 3844 #define DMA_ERQ_ERQ7_MASK (0x80U)
AnnaBridge 143:86740a56073b 3845 #define DMA_ERQ_ERQ7_SHIFT (7U)
AnnaBridge 143:86740a56073b 3846 #define DMA_ERQ_ERQ7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ7_SHIFT)) & DMA_ERQ_ERQ7_MASK)
AnnaBridge 143:86740a56073b 3847 #define DMA_ERQ_ERQ8_MASK (0x100U)
AnnaBridge 143:86740a56073b 3848 #define DMA_ERQ_ERQ8_SHIFT (8U)
AnnaBridge 143:86740a56073b 3849 #define DMA_ERQ_ERQ8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ8_SHIFT)) & DMA_ERQ_ERQ8_MASK)
AnnaBridge 143:86740a56073b 3850 #define DMA_ERQ_ERQ9_MASK (0x200U)
AnnaBridge 143:86740a56073b 3851 #define DMA_ERQ_ERQ9_SHIFT (9U)
AnnaBridge 143:86740a56073b 3852 #define DMA_ERQ_ERQ9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ9_SHIFT)) & DMA_ERQ_ERQ9_MASK)
AnnaBridge 143:86740a56073b 3853 #define DMA_ERQ_ERQ10_MASK (0x400U)
AnnaBridge 143:86740a56073b 3854 #define DMA_ERQ_ERQ10_SHIFT (10U)
AnnaBridge 143:86740a56073b 3855 #define DMA_ERQ_ERQ10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ10_SHIFT)) & DMA_ERQ_ERQ10_MASK)
AnnaBridge 143:86740a56073b 3856 #define DMA_ERQ_ERQ11_MASK (0x800U)
AnnaBridge 143:86740a56073b 3857 #define DMA_ERQ_ERQ11_SHIFT (11U)
AnnaBridge 143:86740a56073b 3858 #define DMA_ERQ_ERQ11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ11_SHIFT)) & DMA_ERQ_ERQ11_MASK)
AnnaBridge 143:86740a56073b 3859 #define DMA_ERQ_ERQ12_MASK (0x1000U)
AnnaBridge 143:86740a56073b 3860 #define DMA_ERQ_ERQ12_SHIFT (12U)
AnnaBridge 143:86740a56073b 3861 #define DMA_ERQ_ERQ12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ12_SHIFT)) & DMA_ERQ_ERQ12_MASK)
AnnaBridge 143:86740a56073b 3862 #define DMA_ERQ_ERQ13_MASK (0x2000U)
AnnaBridge 143:86740a56073b 3863 #define DMA_ERQ_ERQ13_SHIFT (13U)
AnnaBridge 143:86740a56073b 3864 #define DMA_ERQ_ERQ13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ13_SHIFT)) & DMA_ERQ_ERQ13_MASK)
AnnaBridge 143:86740a56073b 3865 #define DMA_ERQ_ERQ14_MASK (0x4000U)
AnnaBridge 143:86740a56073b 3866 #define DMA_ERQ_ERQ14_SHIFT (14U)
AnnaBridge 143:86740a56073b 3867 #define DMA_ERQ_ERQ14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ14_SHIFT)) & DMA_ERQ_ERQ14_MASK)
AnnaBridge 143:86740a56073b 3868 #define DMA_ERQ_ERQ15_MASK (0x8000U)
AnnaBridge 143:86740a56073b 3869 #define DMA_ERQ_ERQ15_SHIFT (15U)
AnnaBridge 143:86740a56073b 3870 #define DMA_ERQ_ERQ15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERQ_ERQ15_SHIFT)) & DMA_ERQ_ERQ15_MASK)
AnnaBridge 143:86740a56073b 3871
AnnaBridge 143:86740a56073b 3872 /*! @name EEI - Enable Error Interrupt Register */
AnnaBridge 143:86740a56073b 3873 #define DMA_EEI_EEI0_MASK (0x1U)
AnnaBridge 143:86740a56073b 3874 #define DMA_EEI_EEI0_SHIFT (0U)
AnnaBridge 143:86740a56073b 3875 #define DMA_EEI_EEI0(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI0_SHIFT)) & DMA_EEI_EEI0_MASK)
AnnaBridge 143:86740a56073b 3876 #define DMA_EEI_EEI1_MASK (0x2U)
AnnaBridge 143:86740a56073b 3877 #define DMA_EEI_EEI1_SHIFT (1U)
AnnaBridge 143:86740a56073b 3878 #define DMA_EEI_EEI1(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI1_SHIFT)) & DMA_EEI_EEI1_MASK)
AnnaBridge 143:86740a56073b 3879 #define DMA_EEI_EEI2_MASK (0x4U)
AnnaBridge 143:86740a56073b 3880 #define DMA_EEI_EEI2_SHIFT (2U)
AnnaBridge 143:86740a56073b 3881 #define DMA_EEI_EEI2(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI2_SHIFT)) & DMA_EEI_EEI2_MASK)
AnnaBridge 143:86740a56073b 3882 #define DMA_EEI_EEI3_MASK (0x8U)
AnnaBridge 143:86740a56073b 3883 #define DMA_EEI_EEI3_SHIFT (3U)
AnnaBridge 143:86740a56073b 3884 #define DMA_EEI_EEI3(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI3_SHIFT)) & DMA_EEI_EEI3_MASK)
AnnaBridge 143:86740a56073b 3885 #define DMA_EEI_EEI4_MASK (0x10U)
AnnaBridge 143:86740a56073b 3886 #define DMA_EEI_EEI4_SHIFT (4U)
AnnaBridge 143:86740a56073b 3887 #define DMA_EEI_EEI4(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI4_SHIFT)) & DMA_EEI_EEI4_MASK)
AnnaBridge 143:86740a56073b 3888 #define DMA_EEI_EEI5_MASK (0x20U)
AnnaBridge 143:86740a56073b 3889 #define DMA_EEI_EEI5_SHIFT (5U)
AnnaBridge 143:86740a56073b 3890 #define DMA_EEI_EEI5(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI5_SHIFT)) & DMA_EEI_EEI5_MASK)
AnnaBridge 143:86740a56073b 3891 #define DMA_EEI_EEI6_MASK (0x40U)
AnnaBridge 143:86740a56073b 3892 #define DMA_EEI_EEI6_SHIFT (6U)
AnnaBridge 143:86740a56073b 3893 #define DMA_EEI_EEI6(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI6_SHIFT)) & DMA_EEI_EEI6_MASK)
AnnaBridge 143:86740a56073b 3894 #define DMA_EEI_EEI7_MASK (0x80U)
AnnaBridge 143:86740a56073b 3895 #define DMA_EEI_EEI7_SHIFT (7U)
AnnaBridge 143:86740a56073b 3896 #define DMA_EEI_EEI7(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI7_SHIFT)) & DMA_EEI_EEI7_MASK)
AnnaBridge 143:86740a56073b 3897 #define DMA_EEI_EEI8_MASK (0x100U)
AnnaBridge 143:86740a56073b 3898 #define DMA_EEI_EEI8_SHIFT (8U)
AnnaBridge 143:86740a56073b 3899 #define DMA_EEI_EEI8(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI8_SHIFT)) & DMA_EEI_EEI8_MASK)
AnnaBridge 143:86740a56073b 3900 #define DMA_EEI_EEI9_MASK (0x200U)
AnnaBridge 143:86740a56073b 3901 #define DMA_EEI_EEI9_SHIFT (9U)
AnnaBridge 143:86740a56073b 3902 #define DMA_EEI_EEI9(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI9_SHIFT)) & DMA_EEI_EEI9_MASK)
AnnaBridge 143:86740a56073b 3903 #define DMA_EEI_EEI10_MASK (0x400U)
AnnaBridge 143:86740a56073b 3904 #define DMA_EEI_EEI10_SHIFT (10U)
AnnaBridge 143:86740a56073b 3905 #define DMA_EEI_EEI10(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI10_SHIFT)) & DMA_EEI_EEI10_MASK)
AnnaBridge 143:86740a56073b 3906 #define DMA_EEI_EEI11_MASK (0x800U)
AnnaBridge 143:86740a56073b 3907 #define DMA_EEI_EEI11_SHIFT (11U)
AnnaBridge 143:86740a56073b 3908 #define DMA_EEI_EEI11(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI11_SHIFT)) & DMA_EEI_EEI11_MASK)
AnnaBridge 143:86740a56073b 3909 #define DMA_EEI_EEI12_MASK (0x1000U)
AnnaBridge 143:86740a56073b 3910 #define DMA_EEI_EEI12_SHIFT (12U)
AnnaBridge 143:86740a56073b 3911 #define DMA_EEI_EEI12(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI12_SHIFT)) & DMA_EEI_EEI12_MASK)
AnnaBridge 143:86740a56073b 3912 #define DMA_EEI_EEI13_MASK (0x2000U)
AnnaBridge 143:86740a56073b 3913 #define DMA_EEI_EEI13_SHIFT (13U)
AnnaBridge 143:86740a56073b 3914 #define DMA_EEI_EEI13(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI13_SHIFT)) & DMA_EEI_EEI13_MASK)
AnnaBridge 143:86740a56073b 3915 #define DMA_EEI_EEI14_MASK (0x4000U)
AnnaBridge 143:86740a56073b 3916 #define DMA_EEI_EEI14_SHIFT (14U)
AnnaBridge 143:86740a56073b 3917 #define DMA_EEI_EEI14(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI14_SHIFT)) & DMA_EEI_EEI14_MASK)
AnnaBridge 143:86740a56073b 3918 #define DMA_EEI_EEI15_MASK (0x8000U)
AnnaBridge 143:86740a56073b 3919 #define DMA_EEI_EEI15_SHIFT (15U)
AnnaBridge 143:86740a56073b 3920 #define DMA_EEI_EEI15(x) (((uint32_t)(((uint32_t)(x)) << DMA_EEI_EEI15_SHIFT)) & DMA_EEI_EEI15_MASK)
AnnaBridge 143:86740a56073b 3921
AnnaBridge 143:86740a56073b 3922 /*! @name CEEI - Clear Enable Error Interrupt Register */
AnnaBridge 143:86740a56073b 3923 #define DMA_CEEI_CEEI_MASK (0xFU)
AnnaBridge 143:86740a56073b 3924 #define DMA_CEEI_CEEI_SHIFT (0U)
AnnaBridge 143:86740a56073b 3925 #define DMA_CEEI_CEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CEEI_SHIFT)) & DMA_CEEI_CEEI_MASK)
AnnaBridge 143:86740a56073b 3926 #define DMA_CEEI_CAEE_MASK (0x40U)
AnnaBridge 143:86740a56073b 3927 #define DMA_CEEI_CAEE_SHIFT (6U)
AnnaBridge 143:86740a56073b 3928 #define DMA_CEEI_CAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_CAEE_SHIFT)) & DMA_CEEI_CAEE_MASK)
AnnaBridge 143:86740a56073b 3929 #define DMA_CEEI_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 3930 #define DMA_CEEI_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 3931 #define DMA_CEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CEEI_NOP_SHIFT)) & DMA_CEEI_NOP_MASK)
AnnaBridge 143:86740a56073b 3932
AnnaBridge 143:86740a56073b 3933 /*! @name SEEI - Set Enable Error Interrupt Register */
AnnaBridge 143:86740a56073b 3934 #define DMA_SEEI_SEEI_MASK (0xFU)
AnnaBridge 143:86740a56073b 3935 #define DMA_SEEI_SEEI_SHIFT (0U)
AnnaBridge 143:86740a56073b 3936 #define DMA_SEEI_SEEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SEEI_SHIFT)) & DMA_SEEI_SEEI_MASK)
AnnaBridge 143:86740a56073b 3937 #define DMA_SEEI_SAEE_MASK (0x40U)
AnnaBridge 143:86740a56073b 3938 #define DMA_SEEI_SAEE_SHIFT (6U)
AnnaBridge 143:86740a56073b 3939 #define DMA_SEEI_SAEE(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_SAEE_SHIFT)) & DMA_SEEI_SAEE_MASK)
AnnaBridge 143:86740a56073b 3940 #define DMA_SEEI_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 3941 #define DMA_SEEI_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 3942 #define DMA_SEEI_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SEEI_NOP_SHIFT)) & DMA_SEEI_NOP_MASK)
AnnaBridge 143:86740a56073b 3943
AnnaBridge 143:86740a56073b 3944 /*! @name CERQ - Clear Enable Request Register */
AnnaBridge 143:86740a56073b 3945 #define DMA_CERQ_CERQ_MASK (0xFU)
AnnaBridge 143:86740a56073b 3946 #define DMA_CERQ_CERQ_SHIFT (0U)
AnnaBridge 143:86740a56073b 3947 #define DMA_CERQ_CERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CERQ_SHIFT)) & DMA_CERQ_CERQ_MASK)
AnnaBridge 143:86740a56073b 3948 #define DMA_CERQ_CAER_MASK (0x40U)
AnnaBridge 143:86740a56073b 3949 #define DMA_CERQ_CAER_SHIFT (6U)
AnnaBridge 143:86740a56073b 3950 #define DMA_CERQ_CAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_CAER_SHIFT)) & DMA_CERQ_CAER_MASK)
AnnaBridge 143:86740a56073b 3951 #define DMA_CERQ_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 3952 #define DMA_CERQ_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 3953 #define DMA_CERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERQ_NOP_SHIFT)) & DMA_CERQ_NOP_MASK)
AnnaBridge 143:86740a56073b 3954
AnnaBridge 143:86740a56073b 3955 /*! @name SERQ - Set Enable Request Register */
AnnaBridge 143:86740a56073b 3956 #define DMA_SERQ_SERQ_MASK (0xFU)
AnnaBridge 143:86740a56073b 3957 #define DMA_SERQ_SERQ_SHIFT (0U)
AnnaBridge 143:86740a56073b 3958 #define DMA_SERQ_SERQ(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SERQ_SHIFT)) & DMA_SERQ_SERQ_MASK)
AnnaBridge 143:86740a56073b 3959 #define DMA_SERQ_SAER_MASK (0x40U)
AnnaBridge 143:86740a56073b 3960 #define DMA_SERQ_SAER_SHIFT (6U)
AnnaBridge 143:86740a56073b 3961 #define DMA_SERQ_SAER(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_SAER_SHIFT)) & DMA_SERQ_SAER_MASK)
AnnaBridge 143:86740a56073b 3962 #define DMA_SERQ_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 3963 #define DMA_SERQ_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 3964 #define DMA_SERQ_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SERQ_NOP_SHIFT)) & DMA_SERQ_NOP_MASK)
AnnaBridge 143:86740a56073b 3965
AnnaBridge 143:86740a56073b 3966 /*! @name CDNE - Clear DONE Status Bit Register */
AnnaBridge 143:86740a56073b 3967 #define DMA_CDNE_CDNE_MASK (0xFU)
AnnaBridge 143:86740a56073b 3968 #define DMA_CDNE_CDNE_SHIFT (0U)
AnnaBridge 143:86740a56073b 3969 #define DMA_CDNE_CDNE(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CDNE_SHIFT)) & DMA_CDNE_CDNE_MASK)
AnnaBridge 143:86740a56073b 3970 #define DMA_CDNE_CADN_MASK (0x40U)
AnnaBridge 143:86740a56073b 3971 #define DMA_CDNE_CADN_SHIFT (6U)
AnnaBridge 143:86740a56073b 3972 #define DMA_CDNE_CADN(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_CADN_SHIFT)) & DMA_CDNE_CADN_MASK)
AnnaBridge 143:86740a56073b 3973 #define DMA_CDNE_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 3974 #define DMA_CDNE_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 3975 #define DMA_CDNE_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CDNE_NOP_SHIFT)) & DMA_CDNE_NOP_MASK)
AnnaBridge 143:86740a56073b 3976
AnnaBridge 143:86740a56073b 3977 /*! @name SSRT - Set START Bit Register */
AnnaBridge 143:86740a56073b 3978 #define DMA_SSRT_SSRT_MASK (0xFU)
AnnaBridge 143:86740a56073b 3979 #define DMA_SSRT_SSRT_SHIFT (0U)
AnnaBridge 143:86740a56073b 3980 #define DMA_SSRT_SSRT(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SSRT_SHIFT)) & DMA_SSRT_SSRT_MASK)
AnnaBridge 143:86740a56073b 3981 #define DMA_SSRT_SAST_MASK (0x40U)
AnnaBridge 143:86740a56073b 3982 #define DMA_SSRT_SAST_SHIFT (6U)
AnnaBridge 143:86740a56073b 3983 #define DMA_SSRT_SAST(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_SAST_SHIFT)) & DMA_SSRT_SAST_MASK)
AnnaBridge 143:86740a56073b 3984 #define DMA_SSRT_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 3985 #define DMA_SSRT_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 3986 #define DMA_SSRT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_SSRT_NOP_SHIFT)) & DMA_SSRT_NOP_MASK)
AnnaBridge 143:86740a56073b 3987
AnnaBridge 143:86740a56073b 3988 /*! @name CERR - Clear Error Register */
AnnaBridge 143:86740a56073b 3989 #define DMA_CERR_CERR_MASK (0xFU)
AnnaBridge 143:86740a56073b 3990 #define DMA_CERR_CERR_SHIFT (0U)
AnnaBridge 143:86740a56073b 3991 #define DMA_CERR_CERR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CERR_SHIFT)) & DMA_CERR_CERR_MASK)
AnnaBridge 143:86740a56073b 3992 #define DMA_CERR_CAEI_MASK (0x40U)
AnnaBridge 143:86740a56073b 3993 #define DMA_CERR_CAEI_SHIFT (6U)
AnnaBridge 143:86740a56073b 3994 #define DMA_CERR_CAEI(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_CAEI_SHIFT)) & DMA_CERR_CAEI_MASK)
AnnaBridge 143:86740a56073b 3995 #define DMA_CERR_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 3996 #define DMA_CERR_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 3997 #define DMA_CERR_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CERR_NOP_SHIFT)) & DMA_CERR_NOP_MASK)
AnnaBridge 143:86740a56073b 3998
AnnaBridge 143:86740a56073b 3999 /*! @name CINT - Clear Interrupt Request Register */
AnnaBridge 143:86740a56073b 4000 #define DMA_CINT_CINT_MASK (0xFU)
AnnaBridge 143:86740a56073b 4001 #define DMA_CINT_CINT_SHIFT (0U)
AnnaBridge 143:86740a56073b 4002 #define DMA_CINT_CINT(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CINT_SHIFT)) & DMA_CINT_CINT_MASK)
AnnaBridge 143:86740a56073b 4003 #define DMA_CINT_CAIR_MASK (0x40U)
AnnaBridge 143:86740a56073b 4004 #define DMA_CINT_CAIR_SHIFT (6U)
AnnaBridge 143:86740a56073b 4005 #define DMA_CINT_CAIR(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_CAIR_SHIFT)) & DMA_CINT_CAIR_MASK)
AnnaBridge 143:86740a56073b 4006 #define DMA_CINT_NOP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4007 #define DMA_CINT_NOP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4008 #define DMA_CINT_NOP(x) (((uint8_t)(((uint8_t)(x)) << DMA_CINT_NOP_SHIFT)) & DMA_CINT_NOP_MASK)
AnnaBridge 143:86740a56073b 4009
AnnaBridge 143:86740a56073b 4010 /*! @name INT - Interrupt Request Register */
AnnaBridge 143:86740a56073b 4011 #define DMA_INT_INT0_MASK (0x1U)
AnnaBridge 143:86740a56073b 4012 #define DMA_INT_INT0_SHIFT (0U)
AnnaBridge 143:86740a56073b 4013 #define DMA_INT_INT0(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT0_SHIFT)) & DMA_INT_INT0_MASK)
AnnaBridge 143:86740a56073b 4014 #define DMA_INT_INT1_MASK (0x2U)
AnnaBridge 143:86740a56073b 4015 #define DMA_INT_INT1_SHIFT (1U)
AnnaBridge 143:86740a56073b 4016 #define DMA_INT_INT1(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT1_SHIFT)) & DMA_INT_INT1_MASK)
AnnaBridge 143:86740a56073b 4017 #define DMA_INT_INT2_MASK (0x4U)
AnnaBridge 143:86740a56073b 4018 #define DMA_INT_INT2_SHIFT (2U)
AnnaBridge 143:86740a56073b 4019 #define DMA_INT_INT2(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT2_SHIFT)) & DMA_INT_INT2_MASK)
AnnaBridge 143:86740a56073b 4020 #define DMA_INT_INT3_MASK (0x8U)
AnnaBridge 143:86740a56073b 4021 #define DMA_INT_INT3_SHIFT (3U)
AnnaBridge 143:86740a56073b 4022 #define DMA_INT_INT3(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT3_SHIFT)) & DMA_INT_INT3_MASK)
AnnaBridge 143:86740a56073b 4023 #define DMA_INT_INT4_MASK (0x10U)
AnnaBridge 143:86740a56073b 4024 #define DMA_INT_INT4_SHIFT (4U)
AnnaBridge 143:86740a56073b 4025 #define DMA_INT_INT4(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT4_SHIFT)) & DMA_INT_INT4_MASK)
AnnaBridge 143:86740a56073b 4026 #define DMA_INT_INT5_MASK (0x20U)
AnnaBridge 143:86740a56073b 4027 #define DMA_INT_INT5_SHIFT (5U)
AnnaBridge 143:86740a56073b 4028 #define DMA_INT_INT5(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT5_SHIFT)) & DMA_INT_INT5_MASK)
AnnaBridge 143:86740a56073b 4029 #define DMA_INT_INT6_MASK (0x40U)
AnnaBridge 143:86740a56073b 4030 #define DMA_INT_INT6_SHIFT (6U)
AnnaBridge 143:86740a56073b 4031 #define DMA_INT_INT6(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT6_SHIFT)) & DMA_INT_INT6_MASK)
AnnaBridge 143:86740a56073b 4032 #define DMA_INT_INT7_MASK (0x80U)
AnnaBridge 143:86740a56073b 4033 #define DMA_INT_INT7_SHIFT (7U)
AnnaBridge 143:86740a56073b 4034 #define DMA_INT_INT7(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT7_SHIFT)) & DMA_INT_INT7_MASK)
AnnaBridge 143:86740a56073b 4035 #define DMA_INT_INT8_MASK (0x100U)
AnnaBridge 143:86740a56073b 4036 #define DMA_INT_INT8_SHIFT (8U)
AnnaBridge 143:86740a56073b 4037 #define DMA_INT_INT8(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT8_SHIFT)) & DMA_INT_INT8_MASK)
AnnaBridge 143:86740a56073b 4038 #define DMA_INT_INT9_MASK (0x200U)
AnnaBridge 143:86740a56073b 4039 #define DMA_INT_INT9_SHIFT (9U)
AnnaBridge 143:86740a56073b 4040 #define DMA_INT_INT9(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT9_SHIFT)) & DMA_INT_INT9_MASK)
AnnaBridge 143:86740a56073b 4041 #define DMA_INT_INT10_MASK (0x400U)
AnnaBridge 143:86740a56073b 4042 #define DMA_INT_INT10_SHIFT (10U)
AnnaBridge 143:86740a56073b 4043 #define DMA_INT_INT10(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT10_SHIFT)) & DMA_INT_INT10_MASK)
AnnaBridge 143:86740a56073b 4044 #define DMA_INT_INT11_MASK (0x800U)
AnnaBridge 143:86740a56073b 4045 #define DMA_INT_INT11_SHIFT (11U)
AnnaBridge 143:86740a56073b 4046 #define DMA_INT_INT11(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT11_SHIFT)) & DMA_INT_INT11_MASK)
AnnaBridge 143:86740a56073b 4047 #define DMA_INT_INT12_MASK (0x1000U)
AnnaBridge 143:86740a56073b 4048 #define DMA_INT_INT12_SHIFT (12U)
AnnaBridge 143:86740a56073b 4049 #define DMA_INT_INT12(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT12_SHIFT)) & DMA_INT_INT12_MASK)
AnnaBridge 143:86740a56073b 4050 #define DMA_INT_INT13_MASK (0x2000U)
AnnaBridge 143:86740a56073b 4051 #define DMA_INT_INT13_SHIFT (13U)
AnnaBridge 143:86740a56073b 4052 #define DMA_INT_INT13(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT13_SHIFT)) & DMA_INT_INT13_MASK)
AnnaBridge 143:86740a56073b 4053 #define DMA_INT_INT14_MASK (0x4000U)
AnnaBridge 143:86740a56073b 4054 #define DMA_INT_INT14_SHIFT (14U)
AnnaBridge 143:86740a56073b 4055 #define DMA_INT_INT14(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT14_SHIFT)) & DMA_INT_INT14_MASK)
AnnaBridge 143:86740a56073b 4056 #define DMA_INT_INT15_MASK (0x8000U)
AnnaBridge 143:86740a56073b 4057 #define DMA_INT_INT15_SHIFT (15U)
AnnaBridge 143:86740a56073b 4058 #define DMA_INT_INT15(x) (((uint32_t)(((uint32_t)(x)) << DMA_INT_INT15_SHIFT)) & DMA_INT_INT15_MASK)
AnnaBridge 143:86740a56073b 4059
AnnaBridge 143:86740a56073b 4060 /*! @name ERR - Error Register */
AnnaBridge 143:86740a56073b 4061 #define DMA_ERR_ERR0_MASK (0x1U)
AnnaBridge 143:86740a56073b 4062 #define DMA_ERR_ERR0_SHIFT (0U)
AnnaBridge 143:86740a56073b 4063 #define DMA_ERR_ERR0(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR0_SHIFT)) & DMA_ERR_ERR0_MASK)
AnnaBridge 143:86740a56073b 4064 #define DMA_ERR_ERR1_MASK (0x2U)
AnnaBridge 143:86740a56073b 4065 #define DMA_ERR_ERR1_SHIFT (1U)
AnnaBridge 143:86740a56073b 4066 #define DMA_ERR_ERR1(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR1_SHIFT)) & DMA_ERR_ERR1_MASK)
AnnaBridge 143:86740a56073b 4067 #define DMA_ERR_ERR2_MASK (0x4U)
AnnaBridge 143:86740a56073b 4068 #define DMA_ERR_ERR2_SHIFT (2U)
AnnaBridge 143:86740a56073b 4069 #define DMA_ERR_ERR2(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR2_SHIFT)) & DMA_ERR_ERR2_MASK)
AnnaBridge 143:86740a56073b 4070 #define DMA_ERR_ERR3_MASK (0x8U)
AnnaBridge 143:86740a56073b 4071 #define DMA_ERR_ERR3_SHIFT (3U)
AnnaBridge 143:86740a56073b 4072 #define DMA_ERR_ERR3(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR3_SHIFT)) & DMA_ERR_ERR3_MASK)
AnnaBridge 143:86740a56073b 4073 #define DMA_ERR_ERR4_MASK (0x10U)
AnnaBridge 143:86740a56073b 4074 #define DMA_ERR_ERR4_SHIFT (4U)
AnnaBridge 143:86740a56073b 4075 #define DMA_ERR_ERR4(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR4_SHIFT)) & DMA_ERR_ERR4_MASK)
AnnaBridge 143:86740a56073b 4076 #define DMA_ERR_ERR5_MASK (0x20U)
AnnaBridge 143:86740a56073b 4077 #define DMA_ERR_ERR5_SHIFT (5U)
AnnaBridge 143:86740a56073b 4078 #define DMA_ERR_ERR5(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR5_SHIFT)) & DMA_ERR_ERR5_MASK)
AnnaBridge 143:86740a56073b 4079 #define DMA_ERR_ERR6_MASK (0x40U)
AnnaBridge 143:86740a56073b 4080 #define DMA_ERR_ERR6_SHIFT (6U)
AnnaBridge 143:86740a56073b 4081 #define DMA_ERR_ERR6(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR6_SHIFT)) & DMA_ERR_ERR6_MASK)
AnnaBridge 143:86740a56073b 4082 #define DMA_ERR_ERR7_MASK (0x80U)
AnnaBridge 143:86740a56073b 4083 #define DMA_ERR_ERR7_SHIFT (7U)
AnnaBridge 143:86740a56073b 4084 #define DMA_ERR_ERR7(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR7_SHIFT)) & DMA_ERR_ERR7_MASK)
AnnaBridge 143:86740a56073b 4085 #define DMA_ERR_ERR8_MASK (0x100U)
AnnaBridge 143:86740a56073b 4086 #define DMA_ERR_ERR8_SHIFT (8U)
AnnaBridge 143:86740a56073b 4087 #define DMA_ERR_ERR8(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR8_SHIFT)) & DMA_ERR_ERR8_MASK)
AnnaBridge 143:86740a56073b 4088 #define DMA_ERR_ERR9_MASK (0x200U)
AnnaBridge 143:86740a56073b 4089 #define DMA_ERR_ERR9_SHIFT (9U)
AnnaBridge 143:86740a56073b 4090 #define DMA_ERR_ERR9(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR9_SHIFT)) & DMA_ERR_ERR9_MASK)
AnnaBridge 143:86740a56073b 4091 #define DMA_ERR_ERR10_MASK (0x400U)
AnnaBridge 143:86740a56073b 4092 #define DMA_ERR_ERR10_SHIFT (10U)
AnnaBridge 143:86740a56073b 4093 #define DMA_ERR_ERR10(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR10_SHIFT)) & DMA_ERR_ERR10_MASK)
AnnaBridge 143:86740a56073b 4094 #define DMA_ERR_ERR11_MASK (0x800U)
AnnaBridge 143:86740a56073b 4095 #define DMA_ERR_ERR11_SHIFT (11U)
AnnaBridge 143:86740a56073b 4096 #define DMA_ERR_ERR11(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR11_SHIFT)) & DMA_ERR_ERR11_MASK)
AnnaBridge 143:86740a56073b 4097 #define DMA_ERR_ERR12_MASK (0x1000U)
AnnaBridge 143:86740a56073b 4098 #define DMA_ERR_ERR12_SHIFT (12U)
AnnaBridge 143:86740a56073b 4099 #define DMA_ERR_ERR12(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR12_SHIFT)) & DMA_ERR_ERR12_MASK)
AnnaBridge 143:86740a56073b 4100 #define DMA_ERR_ERR13_MASK (0x2000U)
AnnaBridge 143:86740a56073b 4101 #define DMA_ERR_ERR13_SHIFT (13U)
AnnaBridge 143:86740a56073b 4102 #define DMA_ERR_ERR13(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR13_SHIFT)) & DMA_ERR_ERR13_MASK)
AnnaBridge 143:86740a56073b 4103 #define DMA_ERR_ERR14_MASK (0x4000U)
AnnaBridge 143:86740a56073b 4104 #define DMA_ERR_ERR14_SHIFT (14U)
AnnaBridge 143:86740a56073b 4105 #define DMA_ERR_ERR14(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR14_SHIFT)) & DMA_ERR_ERR14_MASK)
AnnaBridge 143:86740a56073b 4106 #define DMA_ERR_ERR15_MASK (0x8000U)
AnnaBridge 143:86740a56073b 4107 #define DMA_ERR_ERR15_SHIFT (15U)
AnnaBridge 143:86740a56073b 4108 #define DMA_ERR_ERR15(x) (((uint32_t)(((uint32_t)(x)) << DMA_ERR_ERR15_SHIFT)) & DMA_ERR_ERR15_MASK)
AnnaBridge 143:86740a56073b 4109
AnnaBridge 143:86740a56073b 4110 /*! @name HRS - Hardware Request Status Register */
AnnaBridge 143:86740a56073b 4111 #define DMA_HRS_HRS0_MASK (0x1U)
AnnaBridge 143:86740a56073b 4112 #define DMA_HRS_HRS0_SHIFT (0U)
AnnaBridge 143:86740a56073b 4113 #define DMA_HRS_HRS0(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS0_SHIFT)) & DMA_HRS_HRS0_MASK)
AnnaBridge 143:86740a56073b 4114 #define DMA_HRS_HRS1_MASK (0x2U)
AnnaBridge 143:86740a56073b 4115 #define DMA_HRS_HRS1_SHIFT (1U)
AnnaBridge 143:86740a56073b 4116 #define DMA_HRS_HRS1(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS1_SHIFT)) & DMA_HRS_HRS1_MASK)
AnnaBridge 143:86740a56073b 4117 #define DMA_HRS_HRS2_MASK (0x4U)
AnnaBridge 143:86740a56073b 4118 #define DMA_HRS_HRS2_SHIFT (2U)
AnnaBridge 143:86740a56073b 4119 #define DMA_HRS_HRS2(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS2_SHIFT)) & DMA_HRS_HRS2_MASK)
AnnaBridge 143:86740a56073b 4120 #define DMA_HRS_HRS3_MASK (0x8U)
AnnaBridge 143:86740a56073b 4121 #define DMA_HRS_HRS3_SHIFT (3U)
AnnaBridge 143:86740a56073b 4122 #define DMA_HRS_HRS3(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS3_SHIFT)) & DMA_HRS_HRS3_MASK)
AnnaBridge 143:86740a56073b 4123 #define DMA_HRS_HRS4_MASK (0x10U)
AnnaBridge 143:86740a56073b 4124 #define DMA_HRS_HRS4_SHIFT (4U)
AnnaBridge 143:86740a56073b 4125 #define DMA_HRS_HRS4(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS4_SHIFT)) & DMA_HRS_HRS4_MASK)
AnnaBridge 143:86740a56073b 4126 #define DMA_HRS_HRS5_MASK (0x20U)
AnnaBridge 143:86740a56073b 4127 #define DMA_HRS_HRS5_SHIFT (5U)
AnnaBridge 143:86740a56073b 4128 #define DMA_HRS_HRS5(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS5_SHIFT)) & DMA_HRS_HRS5_MASK)
AnnaBridge 143:86740a56073b 4129 #define DMA_HRS_HRS6_MASK (0x40U)
AnnaBridge 143:86740a56073b 4130 #define DMA_HRS_HRS6_SHIFT (6U)
AnnaBridge 143:86740a56073b 4131 #define DMA_HRS_HRS6(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS6_SHIFT)) & DMA_HRS_HRS6_MASK)
AnnaBridge 143:86740a56073b 4132 #define DMA_HRS_HRS7_MASK (0x80U)
AnnaBridge 143:86740a56073b 4133 #define DMA_HRS_HRS7_SHIFT (7U)
AnnaBridge 143:86740a56073b 4134 #define DMA_HRS_HRS7(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS7_SHIFT)) & DMA_HRS_HRS7_MASK)
AnnaBridge 143:86740a56073b 4135 #define DMA_HRS_HRS8_MASK (0x100U)
AnnaBridge 143:86740a56073b 4136 #define DMA_HRS_HRS8_SHIFT (8U)
AnnaBridge 143:86740a56073b 4137 #define DMA_HRS_HRS8(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS8_SHIFT)) & DMA_HRS_HRS8_MASK)
AnnaBridge 143:86740a56073b 4138 #define DMA_HRS_HRS9_MASK (0x200U)
AnnaBridge 143:86740a56073b 4139 #define DMA_HRS_HRS9_SHIFT (9U)
AnnaBridge 143:86740a56073b 4140 #define DMA_HRS_HRS9(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS9_SHIFT)) & DMA_HRS_HRS9_MASK)
AnnaBridge 143:86740a56073b 4141 #define DMA_HRS_HRS10_MASK (0x400U)
AnnaBridge 143:86740a56073b 4142 #define DMA_HRS_HRS10_SHIFT (10U)
AnnaBridge 143:86740a56073b 4143 #define DMA_HRS_HRS10(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS10_SHIFT)) & DMA_HRS_HRS10_MASK)
AnnaBridge 143:86740a56073b 4144 #define DMA_HRS_HRS11_MASK (0x800U)
AnnaBridge 143:86740a56073b 4145 #define DMA_HRS_HRS11_SHIFT (11U)
AnnaBridge 143:86740a56073b 4146 #define DMA_HRS_HRS11(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS11_SHIFT)) & DMA_HRS_HRS11_MASK)
AnnaBridge 143:86740a56073b 4147 #define DMA_HRS_HRS12_MASK (0x1000U)
AnnaBridge 143:86740a56073b 4148 #define DMA_HRS_HRS12_SHIFT (12U)
AnnaBridge 143:86740a56073b 4149 #define DMA_HRS_HRS12(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS12_SHIFT)) & DMA_HRS_HRS12_MASK)
AnnaBridge 143:86740a56073b 4150 #define DMA_HRS_HRS13_MASK (0x2000U)
AnnaBridge 143:86740a56073b 4151 #define DMA_HRS_HRS13_SHIFT (13U)
AnnaBridge 143:86740a56073b 4152 #define DMA_HRS_HRS13(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS13_SHIFT)) & DMA_HRS_HRS13_MASK)
AnnaBridge 143:86740a56073b 4153 #define DMA_HRS_HRS14_MASK (0x4000U)
AnnaBridge 143:86740a56073b 4154 #define DMA_HRS_HRS14_SHIFT (14U)
AnnaBridge 143:86740a56073b 4155 #define DMA_HRS_HRS14(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS14_SHIFT)) & DMA_HRS_HRS14_MASK)
AnnaBridge 143:86740a56073b 4156 #define DMA_HRS_HRS15_MASK (0x8000U)
AnnaBridge 143:86740a56073b 4157 #define DMA_HRS_HRS15_SHIFT (15U)
AnnaBridge 143:86740a56073b 4158 #define DMA_HRS_HRS15(x) (((uint32_t)(((uint32_t)(x)) << DMA_HRS_HRS15_SHIFT)) & DMA_HRS_HRS15_MASK)
AnnaBridge 143:86740a56073b 4159
AnnaBridge 143:86740a56073b 4160 /*! @name DCHPRI3 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4161 #define DMA_DCHPRI3_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4162 #define DMA_DCHPRI3_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4163 #define DMA_DCHPRI3_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_CHPRI_SHIFT)) & DMA_DCHPRI3_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4164 #define DMA_DCHPRI3_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4165 #define DMA_DCHPRI3_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4166 #define DMA_DCHPRI3_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_DPA_SHIFT)) & DMA_DCHPRI3_DPA_MASK)
AnnaBridge 143:86740a56073b 4167 #define DMA_DCHPRI3_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4168 #define DMA_DCHPRI3_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4169 #define DMA_DCHPRI3_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI3_ECP_SHIFT)) & DMA_DCHPRI3_ECP_MASK)
AnnaBridge 143:86740a56073b 4170
AnnaBridge 143:86740a56073b 4171 /*! @name DCHPRI2 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4172 #define DMA_DCHPRI2_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4173 #define DMA_DCHPRI2_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4174 #define DMA_DCHPRI2_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_CHPRI_SHIFT)) & DMA_DCHPRI2_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4175 #define DMA_DCHPRI2_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4176 #define DMA_DCHPRI2_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4177 #define DMA_DCHPRI2_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_DPA_SHIFT)) & DMA_DCHPRI2_DPA_MASK)
AnnaBridge 143:86740a56073b 4178 #define DMA_DCHPRI2_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4179 #define DMA_DCHPRI2_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4180 #define DMA_DCHPRI2_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI2_ECP_SHIFT)) & DMA_DCHPRI2_ECP_MASK)
AnnaBridge 143:86740a56073b 4181
AnnaBridge 143:86740a56073b 4182 /*! @name DCHPRI1 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4183 #define DMA_DCHPRI1_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4184 #define DMA_DCHPRI1_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4185 #define DMA_DCHPRI1_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_CHPRI_SHIFT)) & DMA_DCHPRI1_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4186 #define DMA_DCHPRI1_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4187 #define DMA_DCHPRI1_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4188 #define DMA_DCHPRI1_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_DPA_SHIFT)) & DMA_DCHPRI1_DPA_MASK)
AnnaBridge 143:86740a56073b 4189 #define DMA_DCHPRI1_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4190 #define DMA_DCHPRI1_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4191 #define DMA_DCHPRI1_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI1_ECP_SHIFT)) & DMA_DCHPRI1_ECP_MASK)
AnnaBridge 143:86740a56073b 4192
AnnaBridge 143:86740a56073b 4193 /*! @name DCHPRI0 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4194 #define DMA_DCHPRI0_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4195 #define DMA_DCHPRI0_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4196 #define DMA_DCHPRI0_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_CHPRI_SHIFT)) & DMA_DCHPRI0_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4197 #define DMA_DCHPRI0_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4198 #define DMA_DCHPRI0_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4199 #define DMA_DCHPRI0_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_DPA_SHIFT)) & DMA_DCHPRI0_DPA_MASK)
AnnaBridge 143:86740a56073b 4200 #define DMA_DCHPRI0_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4201 #define DMA_DCHPRI0_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4202 #define DMA_DCHPRI0_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI0_ECP_SHIFT)) & DMA_DCHPRI0_ECP_MASK)
AnnaBridge 143:86740a56073b 4203
AnnaBridge 143:86740a56073b 4204 /*! @name DCHPRI7 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4205 #define DMA_DCHPRI7_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4206 #define DMA_DCHPRI7_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4207 #define DMA_DCHPRI7_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_CHPRI_SHIFT)) & DMA_DCHPRI7_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4208 #define DMA_DCHPRI7_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4209 #define DMA_DCHPRI7_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4210 #define DMA_DCHPRI7_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_DPA_SHIFT)) & DMA_DCHPRI7_DPA_MASK)
AnnaBridge 143:86740a56073b 4211 #define DMA_DCHPRI7_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4212 #define DMA_DCHPRI7_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4213 #define DMA_DCHPRI7_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI7_ECP_SHIFT)) & DMA_DCHPRI7_ECP_MASK)
AnnaBridge 143:86740a56073b 4214
AnnaBridge 143:86740a56073b 4215 /*! @name DCHPRI6 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4216 #define DMA_DCHPRI6_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4217 #define DMA_DCHPRI6_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4218 #define DMA_DCHPRI6_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_CHPRI_SHIFT)) & DMA_DCHPRI6_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4219 #define DMA_DCHPRI6_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4220 #define DMA_DCHPRI6_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4221 #define DMA_DCHPRI6_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_DPA_SHIFT)) & DMA_DCHPRI6_DPA_MASK)
AnnaBridge 143:86740a56073b 4222 #define DMA_DCHPRI6_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4223 #define DMA_DCHPRI6_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4224 #define DMA_DCHPRI6_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI6_ECP_SHIFT)) & DMA_DCHPRI6_ECP_MASK)
AnnaBridge 143:86740a56073b 4225
AnnaBridge 143:86740a56073b 4226 /*! @name DCHPRI5 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4227 #define DMA_DCHPRI5_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4228 #define DMA_DCHPRI5_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4229 #define DMA_DCHPRI5_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_CHPRI_SHIFT)) & DMA_DCHPRI5_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4230 #define DMA_DCHPRI5_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4231 #define DMA_DCHPRI5_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4232 #define DMA_DCHPRI5_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_DPA_SHIFT)) & DMA_DCHPRI5_DPA_MASK)
AnnaBridge 143:86740a56073b 4233 #define DMA_DCHPRI5_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4234 #define DMA_DCHPRI5_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4235 #define DMA_DCHPRI5_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI5_ECP_SHIFT)) & DMA_DCHPRI5_ECP_MASK)
AnnaBridge 143:86740a56073b 4236
AnnaBridge 143:86740a56073b 4237 /*! @name DCHPRI4 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4238 #define DMA_DCHPRI4_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4239 #define DMA_DCHPRI4_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4240 #define DMA_DCHPRI4_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_CHPRI_SHIFT)) & DMA_DCHPRI4_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4241 #define DMA_DCHPRI4_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4242 #define DMA_DCHPRI4_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4243 #define DMA_DCHPRI4_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_DPA_SHIFT)) & DMA_DCHPRI4_DPA_MASK)
AnnaBridge 143:86740a56073b 4244 #define DMA_DCHPRI4_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4245 #define DMA_DCHPRI4_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4246 #define DMA_DCHPRI4_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI4_ECP_SHIFT)) & DMA_DCHPRI4_ECP_MASK)
AnnaBridge 143:86740a56073b 4247
AnnaBridge 143:86740a56073b 4248 /*! @name DCHPRI11 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4249 #define DMA_DCHPRI11_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4250 #define DMA_DCHPRI11_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4251 #define DMA_DCHPRI11_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_CHPRI_SHIFT)) & DMA_DCHPRI11_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4252 #define DMA_DCHPRI11_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4253 #define DMA_DCHPRI11_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4254 #define DMA_DCHPRI11_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_DPA_SHIFT)) & DMA_DCHPRI11_DPA_MASK)
AnnaBridge 143:86740a56073b 4255 #define DMA_DCHPRI11_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4256 #define DMA_DCHPRI11_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4257 #define DMA_DCHPRI11_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI11_ECP_SHIFT)) & DMA_DCHPRI11_ECP_MASK)
AnnaBridge 143:86740a56073b 4258
AnnaBridge 143:86740a56073b 4259 /*! @name DCHPRI10 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4260 #define DMA_DCHPRI10_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4261 #define DMA_DCHPRI10_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4262 #define DMA_DCHPRI10_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_CHPRI_SHIFT)) & DMA_DCHPRI10_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4263 #define DMA_DCHPRI10_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4264 #define DMA_DCHPRI10_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4265 #define DMA_DCHPRI10_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_DPA_SHIFT)) & DMA_DCHPRI10_DPA_MASK)
AnnaBridge 143:86740a56073b 4266 #define DMA_DCHPRI10_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4267 #define DMA_DCHPRI10_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4268 #define DMA_DCHPRI10_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI10_ECP_SHIFT)) & DMA_DCHPRI10_ECP_MASK)
AnnaBridge 143:86740a56073b 4269
AnnaBridge 143:86740a56073b 4270 /*! @name DCHPRI9 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4271 #define DMA_DCHPRI9_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4272 #define DMA_DCHPRI9_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4273 #define DMA_DCHPRI9_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_CHPRI_SHIFT)) & DMA_DCHPRI9_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4274 #define DMA_DCHPRI9_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4275 #define DMA_DCHPRI9_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4276 #define DMA_DCHPRI9_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_DPA_SHIFT)) & DMA_DCHPRI9_DPA_MASK)
AnnaBridge 143:86740a56073b 4277 #define DMA_DCHPRI9_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4278 #define DMA_DCHPRI9_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4279 #define DMA_DCHPRI9_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI9_ECP_SHIFT)) & DMA_DCHPRI9_ECP_MASK)
AnnaBridge 143:86740a56073b 4280
AnnaBridge 143:86740a56073b 4281 /*! @name DCHPRI8 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4282 #define DMA_DCHPRI8_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4283 #define DMA_DCHPRI8_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4284 #define DMA_DCHPRI8_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_CHPRI_SHIFT)) & DMA_DCHPRI8_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4285 #define DMA_DCHPRI8_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4286 #define DMA_DCHPRI8_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4287 #define DMA_DCHPRI8_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_DPA_SHIFT)) & DMA_DCHPRI8_DPA_MASK)
AnnaBridge 143:86740a56073b 4288 #define DMA_DCHPRI8_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4289 #define DMA_DCHPRI8_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4290 #define DMA_DCHPRI8_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI8_ECP_SHIFT)) & DMA_DCHPRI8_ECP_MASK)
AnnaBridge 143:86740a56073b 4291
AnnaBridge 143:86740a56073b 4292 /*! @name DCHPRI15 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4293 #define DMA_DCHPRI15_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4294 #define DMA_DCHPRI15_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4295 #define DMA_DCHPRI15_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_CHPRI_SHIFT)) & DMA_DCHPRI15_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4296 #define DMA_DCHPRI15_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4297 #define DMA_DCHPRI15_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4298 #define DMA_DCHPRI15_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_DPA_SHIFT)) & DMA_DCHPRI15_DPA_MASK)
AnnaBridge 143:86740a56073b 4299 #define DMA_DCHPRI15_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4300 #define DMA_DCHPRI15_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4301 #define DMA_DCHPRI15_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI15_ECP_SHIFT)) & DMA_DCHPRI15_ECP_MASK)
AnnaBridge 143:86740a56073b 4302
AnnaBridge 143:86740a56073b 4303 /*! @name DCHPRI14 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4304 #define DMA_DCHPRI14_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4305 #define DMA_DCHPRI14_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4306 #define DMA_DCHPRI14_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_CHPRI_SHIFT)) & DMA_DCHPRI14_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4307 #define DMA_DCHPRI14_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4308 #define DMA_DCHPRI14_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4309 #define DMA_DCHPRI14_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_DPA_SHIFT)) & DMA_DCHPRI14_DPA_MASK)
AnnaBridge 143:86740a56073b 4310 #define DMA_DCHPRI14_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4311 #define DMA_DCHPRI14_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4312 #define DMA_DCHPRI14_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI14_ECP_SHIFT)) & DMA_DCHPRI14_ECP_MASK)
AnnaBridge 143:86740a56073b 4313
AnnaBridge 143:86740a56073b 4314 /*! @name DCHPRI13 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4315 #define DMA_DCHPRI13_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4316 #define DMA_DCHPRI13_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4317 #define DMA_DCHPRI13_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_CHPRI_SHIFT)) & DMA_DCHPRI13_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4318 #define DMA_DCHPRI13_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4319 #define DMA_DCHPRI13_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4320 #define DMA_DCHPRI13_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_DPA_SHIFT)) & DMA_DCHPRI13_DPA_MASK)
AnnaBridge 143:86740a56073b 4321 #define DMA_DCHPRI13_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4322 #define DMA_DCHPRI13_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4323 #define DMA_DCHPRI13_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI13_ECP_SHIFT)) & DMA_DCHPRI13_ECP_MASK)
AnnaBridge 143:86740a56073b 4324
AnnaBridge 143:86740a56073b 4325 /*! @name DCHPRI12 - Channel n Priority Register */
AnnaBridge 143:86740a56073b 4326 #define DMA_DCHPRI12_CHPRI_MASK (0xFU)
AnnaBridge 143:86740a56073b 4327 #define DMA_DCHPRI12_CHPRI_SHIFT (0U)
AnnaBridge 143:86740a56073b 4328 #define DMA_DCHPRI12_CHPRI(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_CHPRI_SHIFT)) & DMA_DCHPRI12_CHPRI_MASK)
AnnaBridge 143:86740a56073b 4329 #define DMA_DCHPRI12_DPA_MASK (0x40U)
AnnaBridge 143:86740a56073b 4330 #define DMA_DCHPRI12_DPA_SHIFT (6U)
AnnaBridge 143:86740a56073b 4331 #define DMA_DCHPRI12_DPA(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_DPA_SHIFT)) & DMA_DCHPRI12_DPA_MASK)
AnnaBridge 143:86740a56073b 4332 #define DMA_DCHPRI12_ECP_MASK (0x80U)
AnnaBridge 143:86740a56073b 4333 #define DMA_DCHPRI12_ECP_SHIFT (7U)
AnnaBridge 143:86740a56073b 4334 #define DMA_DCHPRI12_ECP(x) (((uint8_t)(((uint8_t)(x)) << DMA_DCHPRI12_ECP_SHIFT)) & DMA_DCHPRI12_ECP_MASK)
AnnaBridge 143:86740a56073b 4335
AnnaBridge 143:86740a56073b 4336 /*! @name SADDR - TCD Source Address */
AnnaBridge 143:86740a56073b 4337 #define DMA_SADDR_SADDR_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 4338 #define DMA_SADDR_SADDR_SHIFT (0U)
AnnaBridge 143:86740a56073b 4339 #define DMA_SADDR_SADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_SADDR_SADDR_SHIFT)) & DMA_SADDR_SADDR_MASK)
AnnaBridge 143:86740a56073b 4340
AnnaBridge 143:86740a56073b 4341 /* The count of DMA_SADDR */
AnnaBridge 143:86740a56073b 4342 #define DMA_SADDR_COUNT (16U)
AnnaBridge 143:86740a56073b 4343
AnnaBridge 143:86740a56073b 4344 /*! @name SOFF - TCD Signed Source Address Offset */
AnnaBridge 143:86740a56073b 4345 #define DMA_SOFF_SOFF_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 4346 #define DMA_SOFF_SOFF_SHIFT (0U)
AnnaBridge 143:86740a56073b 4347 #define DMA_SOFF_SOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_SOFF_SOFF_SHIFT)) & DMA_SOFF_SOFF_MASK)
AnnaBridge 143:86740a56073b 4348
AnnaBridge 143:86740a56073b 4349 /* The count of DMA_SOFF */
AnnaBridge 143:86740a56073b 4350 #define DMA_SOFF_COUNT (16U)
AnnaBridge 143:86740a56073b 4351
AnnaBridge 143:86740a56073b 4352 /*! @name ATTR - TCD Transfer Attributes */
AnnaBridge 143:86740a56073b 4353 #define DMA_ATTR_DSIZE_MASK (0x7U)
AnnaBridge 143:86740a56073b 4354 #define DMA_ATTR_DSIZE_SHIFT (0U)
AnnaBridge 143:86740a56073b 4355 #define DMA_ATTR_DSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DSIZE_SHIFT)) & DMA_ATTR_DSIZE_MASK)
AnnaBridge 143:86740a56073b 4356 #define DMA_ATTR_DMOD_MASK (0xF8U)
AnnaBridge 143:86740a56073b 4357 #define DMA_ATTR_DMOD_SHIFT (3U)
AnnaBridge 143:86740a56073b 4358 #define DMA_ATTR_DMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_DMOD_SHIFT)) & DMA_ATTR_DMOD_MASK)
AnnaBridge 143:86740a56073b 4359 #define DMA_ATTR_SSIZE_MASK (0x700U)
AnnaBridge 143:86740a56073b 4360 #define DMA_ATTR_SSIZE_SHIFT (8U)
AnnaBridge 143:86740a56073b 4361 #define DMA_ATTR_SSIZE(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SSIZE_SHIFT)) & DMA_ATTR_SSIZE_MASK)
AnnaBridge 143:86740a56073b 4362 #define DMA_ATTR_SMOD_MASK (0xF800U)
AnnaBridge 143:86740a56073b 4363 #define DMA_ATTR_SMOD_SHIFT (11U)
AnnaBridge 143:86740a56073b 4364 #define DMA_ATTR_SMOD(x) (((uint16_t)(((uint16_t)(x)) << DMA_ATTR_SMOD_SHIFT)) & DMA_ATTR_SMOD_MASK)
AnnaBridge 143:86740a56073b 4365
AnnaBridge 143:86740a56073b 4366 /* The count of DMA_ATTR */
AnnaBridge 143:86740a56073b 4367 #define DMA_ATTR_COUNT (16U)
AnnaBridge 143:86740a56073b 4368
AnnaBridge 143:86740a56073b 4369 /*! @name NBYTES_MLNO - TCD Minor Byte Count (Minor Loop Disabled) */
AnnaBridge 143:86740a56073b 4370 #define DMA_NBYTES_MLNO_NBYTES_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 4371 #define DMA_NBYTES_MLNO_NBYTES_SHIFT (0U)
AnnaBridge 143:86740a56073b 4372 #define DMA_NBYTES_MLNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLNO_NBYTES_SHIFT)) & DMA_NBYTES_MLNO_NBYTES_MASK)
AnnaBridge 143:86740a56073b 4373
AnnaBridge 143:86740a56073b 4374 /* The count of DMA_NBYTES_MLNO */
AnnaBridge 143:86740a56073b 4375 #define DMA_NBYTES_MLNO_COUNT (16U)
AnnaBridge 143:86740a56073b 4376
AnnaBridge 143:86740a56073b 4377 /*! @name NBYTES_MLOFFNO - TCD Signed Minor Loop Offset (Minor Loop Enabled and Offset Disabled) */
AnnaBridge 143:86740a56073b 4378 #define DMA_NBYTES_MLOFFNO_NBYTES_MASK (0x3FFFFFFFU)
AnnaBridge 143:86740a56073b 4379 #define DMA_NBYTES_MLOFFNO_NBYTES_SHIFT (0U)
AnnaBridge 143:86740a56073b 4380 #define DMA_NBYTES_MLOFFNO_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFNO_NBYTES_MASK)
AnnaBridge 143:86740a56073b 4381 #define DMA_NBYTES_MLOFFNO_DMLOE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 4382 #define DMA_NBYTES_MLOFFNO_DMLOE_SHIFT (30U)
AnnaBridge 143:86740a56073b 4383 #define DMA_NBYTES_MLOFFNO_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_DMLOE_MASK)
AnnaBridge 143:86740a56073b 4384 #define DMA_NBYTES_MLOFFNO_SMLOE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 4385 #define DMA_NBYTES_MLOFFNO_SMLOE_SHIFT (31U)
AnnaBridge 143:86740a56073b 4386 #define DMA_NBYTES_MLOFFNO_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFNO_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFNO_SMLOE_MASK)
AnnaBridge 143:86740a56073b 4387
AnnaBridge 143:86740a56073b 4388 /* The count of DMA_NBYTES_MLOFFNO */
AnnaBridge 143:86740a56073b 4389 #define DMA_NBYTES_MLOFFNO_COUNT (16U)
AnnaBridge 143:86740a56073b 4390
AnnaBridge 143:86740a56073b 4391 /*! @name NBYTES_MLOFFYES - TCD Signed Minor Loop Offset (Minor Loop and Offset Enabled) */
AnnaBridge 143:86740a56073b 4392 #define DMA_NBYTES_MLOFFYES_NBYTES_MASK (0x3FFU)
AnnaBridge 143:86740a56073b 4393 #define DMA_NBYTES_MLOFFYES_NBYTES_SHIFT (0U)
AnnaBridge 143:86740a56073b 4394 #define DMA_NBYTES_MLOFFYES_NBYTES(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_NBYTES_SHIFT)) & DMA_NBYTES_MLOFFYES_NBYTES_MASK)
AnnaBridge 143:86740a56073b 4395 #define DMA_NBYTES_MLOFFYES_MLOFF_MASK (0x3FFFFC00U)
AnnaBridge 143:86740a56073b 4396 #define DMA_NBYTES_MLOFFYES_MLOFF_SHIFT (10U)
AnnaBridge 143:86740a56073b 4397 #define DMA_NBYTES_MLOFFYES_MLOFF(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_MLOFF_SHIFT)) & DMA_NBYTES_MLOFFYES_MLOFF_MASK)
AnnaBridge 143:86740a56073b 4398 #define DMA_NBYTES_MLOFFYES_DMLOE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 4399 #define DMA_NBYTES_MLOFFYES_DMLOE_SHIFT (30U)
AnnaBridge 143:86740a56073b 4400 #define DMA_NBYTES_MLOFFYES_DMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_DMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_DMLOE_MASK)
AnnaBridge 143:86740a56073b 4401 #define DMA_NBYTES_MLOFFYES_SMLOE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 4402 #define DMA_NBYTES_MLOFFYES_SMLOE_SHIFT (31U)
AnnaBridge 143:86740a56073b 4403 #define DMA_NBYTES_MLOFFYES_SMLOE(x) (((uint32_t)(((uint32_t)(x)) << DMA_NBYTES_MLOFFYES_SMLOE_SHIFT)) & DMA_NBYTES_MLOFFYES_SMLOE_MASK)
AnnaBridge 143:86740a56073b 4404
AnnaBridge 143:86740a56073b 4405 /* The count of DMA_NBYTES_MLOFFYES */
AnnaBridge 143:86740a56073b 4406 #define DMA_NBYTES_MLOFFYES_COUNT (16U)
AnnaBridge 143:86740a56073b 4407
AnnaBridge 143:86740a56073b 4408 /*! @name SLAST - TCD Last Source Address Adjustment */
AnnaBridge 143:86740a56073b 4409 #define DMA_SLAST_SLAST_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 4410 #define DMA_SLAST_SLAST_SHIFT (0U)
AnnaBridge 143:86740a56073b 4411 #define DMA_SLAST_SLAST(x) (((uint32_t)(((uint32_t)(x)) << DMA_SLAST_SLAST_SHIFT)) & DMA_SLAST_SLAST_MASK)
AnnaBridge 143:86740a56073b 4412
AnnaBridge 143:86740a56073b 4413 /* The count of DMA_SLAST */
AnnaBridge 143:86740a56073b 4414 #define DMA_SLAST_COUNT (16U)
AnnaBridge 143:86740a56073b 4415
AnnaBridge 143:86740a56073b 4416 /*! @name DADDR - TCD Destination Address */
AnnaBridge 143:86740a56073b 4417 #define DMA_DADDR_DADDR_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 4418 #define DMA_DADDR_DADDR_SHIFT (0U)
AnnaBridge 143:86740a56073b 4419 #define DMA_DADDR_DADDR(x) (((uint32_t)(((uint32_t)(x)) << DMA_DADDR_DADDR_SHIFT)) & DMA_DADDR_DADDR_MASK)
AnnaBridge 143:86740a56073b 4420
AnnaBridge 143:86740a56073b 4421 /* The count of DMA_DADDR */
AnnaBridge 143:86740a56073b 4422 #define DMA_DADDR_COUNT (16U)
AnnaBridge 143:86740a56073b 4423
AnnaBridge 143:86740a56073b 4424 /*! @name DOFF - TCD Signed Destination Address Offset */
AnnaBridge 143:86740a56073b 4425 #define DMA_DOFF_DOFF_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 4426 #define DMA_DOFF_DOFF_SHIFT (0U)
AnnaBridge 143:86740a56073b 4427 #define DMA_DOFF_DOFF(x) (((uint16_t)(((uint16_t)(x)) << DMA_DOFF_DOFF_SHIFT)) & DMA_DOFF_DOFF_MASK)
AnnaBridge 143:86740a56073b 4428
AnnaBridge 143:86740a56073b 4429 /* The count of DMA_DOFF */
AnnaBridge 143:86740a56073b 4430 #define DMA_DOFF_COUNT (16U)
AnnaBridge 143:86740a56073b 4431
AnnaBridge 143:86740a56073b 4432 /*! @name CITER_ELINKNO - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 143:86740a56073b 4433 #define DMA_CITER_ELINKNO_CITER_MASK (0x7FFFU)
AnnaBridge 143:86740a56073b 4434 #define DMA_CITER_ELINKNO_CITER_SHIFT (0U)
AnnaBridge 143:86740a56073b 4435 #define DMA_CITER_ELINKNO_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_CITER_SHIFT)) & DMA_CITER_ELINKNO_CITER_MASK)
AnnaBridge 143:86740a56073b 4436 #define DMA_CITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 143:86740a56073b 4437 #define DMA_CITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 143:86740a56073b 4438 #define DMA_CITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKNO_ELINK_SHIFT)) & DMA_CITER_ELINKNO_ELINK_MASK)
AnnaBridge 143:86740a56073b 4439
AnnaBridge 143:86740a56073b 4440 /* The count of DMA_CITER_ELINKNO */
AnnaBridge 143:86740a56073b 4441 #define DMA_CITER_ELINKNO_COUNT (16U)
AnnaBridge 143:86740a56073b 4442
AnnaBridge 143:86740a56073b 4443 /*! @name CITER_ELINKYES - TCD Current Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 143:86740a56073b 4444 #define DMA_CITER_ELINKYES_CITER_MASK (0x1FFU)
AnnaBridge 143:86740a56073b 4445 #define DMA_CITER_ELINKYES_CITER_SHIFT (0U)
AnnaBridge 143:86740a56073b 4446 #define DMA_CITER_ELINKYES_CITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_CITER_SHIFT)) & DMA_CITER_ELINKYES_CITER_MASK)
AnnaBridge 143:86740a56073b 4447 #define DMA_CITER_ELINKYES_LINKCH_MASK (0x1E00U)
AnnaBridge 143:86740a56073b 4448 #define DMA_CITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 143:86740a56073b 4449 #define DMA_CITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_LINKCH_SHIFT)) & DMA_CITER_ELINKYES_LINKCH_MASK)
AnnaBridge 143:86740a56073b 4450 #define DMA_CITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 143:86740a56073b 4451 #define DMA_CITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 143:86740a56073b 4452 #define DMA_CITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CITER_ELINKYES_ELINK_SHIFT)) & DMA_CITER_ELINKYES_ELINK_MASK)
AnnaBridge 143:86740a56073b 4453
AnnaBridge 143:86740a56073b 4454 /* The count of DMA_CITER_ELINKYES */
AnnaBridge 143:86740a56073b 4455 #define DMA_CITER_ELINKYES_COUNT (16U)
AnnaBridge 143:86740a56073b 4456
AnnaBridge 143:86740a56073b 4457 /*! @name DLAST_SGA - TCD Last Destination Address Adjustment/Scatter Gather Address */
AnnaBridge 143:86740a56073b 4458 #define DMA_DLAST_SGA_DLASTSGA_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 4459 #define DMA_DLAST_SGA_DLASTSGA_SHIFT (0U)
AnnaBridge 143:86740a56073b 4460 #define DMA_DLAST_SGA_DLASTSGA(x) (((uint32_t)(((uint32_t)(x)) << DMA_DLAST_SGA_DLASTSGA_SHIFT)) & DMA_DLAST_SGA_DLASTSGA_MASK)
AnnaBridge 143:86740a56073b 4461
AnnaBridge 143:86740a56073b 4462 /* The count of DMA_DLAST_SGA */
AnnaBridge 143:86740a56073b 4463 #define DMA_DLAST_SGA_COUNT (16U)
AnnaBridge 143:86740a56073b 4464
AnnaBridge 143:86740a56073b 4465 /*! @name CSR - TCD Control and Status */
AnnaBridge 143:86740a56073b 4466 #define DMA_CSR_START_MASK (0x1U)
AnnaBridge 143:86740a56073b 4467 #define DMA_CSR_START_SHIFT (0U)
AnnaBridge 143:86740a56073b 4468 #define DMA_CSR_START(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_START_SHIFT)) & DMA_CSR_START_MASK)
AnnaBridge 143:86740a56073b 4469 #define DMA_CSR_INTMAJOR_MASK (0x2U)
AnnaBridge 143:86740a56073b 4470 #define DMA_CSR_INTMAJOR_SHIFT (1U)
AnnaBridge 143:86740a56073b 4471 #define DMA_CSR_INTMAJOR(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTMAJOR_SHIFT)) & DMA_CSR_INTMAJOR_MASK)
AnnaBridge 143:86740a56073b 4472 #define DMA_CSR_INTHALF_MASK (0x4U)
AnnaBridge 143:86740a56073b 4473 #define DMA_CSR_INTHALF_SHIFT (2U)
AnnaBridge 143:86740a56073b 4474 #define DMA_CSR_INTHALF(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_INTHALF_SHIFT)) & DMA_CSR_INTHALF_MASK)
AnnaBridge 143:86740a56073b 4475 #define DMA_CSR_DREQ_MASK (0x8U)
AnnaBridge 143:86740a56073b 4476 #define DMA_CSR_DREQ_SHIFT (3U)
AnnaBridge 143:86740a56073b 4477 #define DMA_CSR_DREQ(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DREQ_SHIFT)) & DMA_CSR_DREQ_MASK)
AnnaBridge 143:86740a56073b 4478 #define DMA_CSR_ESG_MASK (0x10U)
AnnaBridge 143:86740a56073b 4479 #define DMA_CSR_ESG_SHIFT (4U)
AnnaBridge 143:86740a56073b 4480 #define DMA_CSR_ESG(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ESG_SHIFT)) & DMA_CSR_ESG_MASK)
AnnaBridge 143:86740a56073b 4481 #define DMA_CSR_MAJORELINK_MASK (0x20U)
AnnaBridge 143:86740a56073b 4482 #define DMA_CSR_MAJORELINK_SHIFT (5U)
AnnaBridge 143:86740a56073b 4483 #define DMA_CSR_MAJORELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORELINK_SHIFT)) & DMA_CSR_MAJORELINK_MASK)
AnnaBridge 143:86740a56073b 4484 #define DMA_CSR_ACTIVE_MASK (0x40U)
AnnaBridge 143:86740a56073b 4485 #define DMA_CSR_ACTIVE_SHIFT (6U)
AnnaBridge 143:86740a56073b 4486 #define DMA_CSR_ACTIVE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_ACTIVE_SHIFT)) & DMA_CSR_ACTIVE_MASK)
AnnaBridge 143:86740a56073b 4487 #define DMA_CSR_DONE_MASK (0x80U)
AnnaBridge 143:86740a56073b 4488 #define DMA_CSR_DONE_SHIFT (7U)
AnnaBridge 143:86740a56073b 4489 #define DMA_CSR_DONE(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_DONE_SHIFT)) & DMA_CSR_DONE_MASK)
AnnaBridge 143:86740a56073b 4490 #define DMA_CSR_MAJORLINKCH_MASK (0xF00U)
AnnaBridge 143:86740a56073b 4491 #define DMA_CSR_MAJORLINKCH_SHIFT (8U)
AnnaBridge 143:86740a56073b 4492 #define DMA_CSR_MAJORLINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_MAJORLINKCH_SHIFT)) & DMA_CSR_MAJORLINKCH_MASK)
AnnaBridge 143:86740a56073b 4493 #define DMA_CSR_BWC_MASK (0xC000U)
AnnaBridge 143:86740a56073b 4494 #define DMA_CSR_BWC_SHIFT (14U)
AnnaBridge 143:86740a56073b 4495 #define DMA_CSR_BWC(x) (((uint16_t)(((uint16_t)(x)) << DMA_CSR_BWC_SHIFT)) & DMA_CSR_BWC_MASK)
AnnaBridge 143:86740a56073b 4496
AnnaBridge 143:86740a56073b 4497 /* The count of DMA_CSR */
AnnaBridge 143:86740a56073b 4498 #define DMA_CSR_COUNT (16U)
AnnaBridge 143:86740a56073b 4499
AnnaBridge 143:86740a56073b 4500 /*! @name BITER_ELINKNO - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Disabled) */
AnnaBridge 143:86740a56073b 4501 #define DMA_BITER_ELINKNO_BITER_MASK (0x7FFFU)
AnnaBridge 143:86740a56073b 4502 #define DMA_BITER_ELINKNO_BITER_SHIFT (0U)
AnnaBridge 143:86740a56073b 4503 #define DMA_BITER_ELINKNO_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_BITER_SHIFT)) & DMA_BITER_ELINKNO_BITER_MASK)
AnnaBridge 143:86740a56073b 4504 #define DMA_BITER_ELINKNO_ELINK_MASK (0x8000U)
AnnaBridge 143:86740a56073b 4505 #define DMA_BITER_ELINKNO_ELINK_SHIFT (15U)
AnnaBridge 143:86740a56073b 4506 #define DMA_BITER_ELINKNO_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKNO_ELINK_SHIFT)) & DMA_BITER_ELINKNO_ELINK_MASK)
AnnaBridge 143:86740a56073b 4507
AnnaBridge 143:86740a56073b 4508 /* The count of DMA_BITER_ELINKNO */
AnnaBridge 143:86740a56073b 4509 #define DMA_BITER_ELINKNO_COUNT (16U)
AnnaBridge 143:86740a56073b 4510
AnnaBridge 143:86740a56073b 4511 /*! @name BITER_ELINKYES - TCD Beginning Minor Loop Link, Major Loop Count (Channel Linking Enabled) */
AnnaBridge 143:86740a56073b 4512 #define DMA_BITER_ELINKYES_BITER_MASK (0x1FFU)
AnnaBridge 143:86740a56073b 4513 #define DMA_BITER_ELINKYES_BITER_SHIFT (0U)
AnnaBridge 143:86740a56073b 4514 #define DMA_BITER_ELINKYES_BITER(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_BITER_SHIFT)) & DMA_BITER_ELINKYES_BITER_MASK)
AnnaBridge 143:86740a56073b 4515 #define DMA_BITER_ELINKYES_LINKCH_MASK (0x1E00U)
AnnaBridge 143:86740a56073b 4516 #define DMA_BITER_ELINKYES_LINKCH_SHIFT (9U)
AnnaBridge 143:86740a56073b 4517 #define DMA_BITER_ELINKYES_LINKCH(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_LINKCH_SHIFT)) & DMA_BITER_ELINKYES_LINKCH_MASK)
AnnaBridge 143:86740a56073b 4518 #define DMA_BITER_ELINKYES_ELINK_MASK (0x8000U)
AnnaBridge 143:86740a56073b 4519 #define DMA_BITER_ELINKYES_ELINK_SHIFT (15U)
AnnaBridge 143:86740a56073b 4520 #define DMA_BITER_ELINKYES_ELINK(x) (((uint16_t)(((uint16_t)(x)) << DMA_BITER_ELINKYES_ELINK_SHIFT)) & DMA_BITER_ELINKYES_ELINK_MASK)
AnnaBridge 143:86740a56073b 4521
AnnaBridge 143:86740a56073b 4522 /* The count of DMA_BITER_ELINKYES */
AnnaBridge 143:86740a56073b 4523 #define DMA_BITER_ELINKYES_COUNT (16U)
AnnaBridge 143:86740a56073b 4524
AnnaBridge 143:86740a56073b 4525
AnnaBridge 143:86740a56073b 4526 /*!
AnnaBridge 143:86740a56073b 4527 * @}
AnnaBridge 143:86740a56073b 4528 */ /* end of group DMA_Register_Masks */
AnnaBridge 143:86740a56073b 4529
AnnaBridge 143:86740a56073b 4530
AnnaBridge 143:86740a56073b 4531 /* DMA - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 4532 /** Peripheral DMA base address */
AnnaBridge 143:86740a56073b 4533 #define DMA_BASE (0x40008000u)
AnnaBridge 143:86740a56073b 4534 /** Peripheral DMA base pointer */
AnnaBridge 143:86740a56073b 4535 #define DMA0 ((DMA_Type *)DMA_BASE)
AnnaBridge 143:86740a56073b 4536 /** Array initializer of DMA peripheral base addresses */
AnnaBridge 143:86740a56073b 4537 #define DMA_BASE_ADDRS { DMA_BASE }
AnnaBridge 143:86740a56073b 4538 /** Array initializer of DMA peripheral base pointers */
AnnaBridge 143:86740a56073b 4539 #define DMA_BASE_PTRS { DMA0 }
AnnaBridge 143:86740a56073b 4540 /** Interrupt vectors for the DMA peripheral type */
AnnaBridge 143:86740a56073b 4541 #define DMA_CHN_IRQS { { DMA0_IRQn, DMA1_IRQn, DMA2_IRQn, DMA3_IRQn, DMA4_IRQn, DMA5_IRQn, DMA6_IRQn, DMA7_IRQn, DMA8_IRQn, DMA9_IRQn, DMA10_IRQn, DMA11_IRQn, DMA12_IRQn, DMA13_IRQn, DMA14_IRQn, DMA15_IRQn } }
AnnaBridge 143:86740a56073b 4542 #define DMA_ERROR_IRQS { DMA_Error_IRQn }
AnnaBridge 143:86740a56073b 4543
AnnaBridge 143:86740a56073b 4544 /*!
AnnaBridge 143:86740a56073b 4545 * @}
AnnaBridge 143:86740a56073b 4546 */ /* end of group DMA_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 4547
AnnaBridge 143:86740a56073b 4548
AnnaBridge 143:86740a56073b 4549 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4550 -- DMAMUX Peripheral Access Layer
AnnaBridge 143:86740a56073b 4551 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4552
AnnaBridge 143:86740a56073b 4553 /*!
AnnaBridge 143:86740a56073b 4554 * @addtogroup DMAMUX_Peripheral_Access_Layer DMAMUX Peripheral Access Layer
AnnaBridge 143:86740a56073b 4555 * @{
AnnaBridge 143:86740a56073b 4556 */
AnnaBridge 143:86740a56073b 4557
AnnaBridge 143:86740a56073b 4558 /** DMAMUX - Register Layout Typedef */
AnnaBridge 143:86740a56073b 4559 typedef struct {
AnnaBridge 143:86740a56073b 4560 __IO uint8_t CHCFG[16]; /**< Channel Configuration register, array offset: 0x0, array step: 0x1 */
AnnaBridge 143:86740a56073b 4561 } DMAMUX_Type;
AnnaBridge 143:86740a56073b 4562
AnnaBridge 143:86740a56073b 4563 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4564 -- DMAMUX Register Masks
AnnaBridge 143:86740a56073b 4565 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4566
AnnaBridge 143:86740a56073b 4567 /*!
AnnaBridge 143:86740a56073b 4568 * @addtogroup DMAMUX_Register_Masks DMAMUX Register Masks
AnnaBridge 143:86740a56073b 4569 * @{
AnnaBridge 143:86740a56073b 4570 */
AnnaBridge 143:86740a56073b 4571
AnnaBridge 143:86740a56073b 4572 /*! @name CHCFG - Channel Configuration register */
AnnaBridge 143:86740a56073b 4573 #define DMAMUX_CHCFG_SOURCE_MASK (0x3FU)
AnnaBridge 143:86740a56073b 4574 #define DMAMUX_CHCFG_SOURCE_SHIFT (0U)
AnnaBridge 143:86740a56073b 4575 #define DMAMUX_CHCFG_SOURCE(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_SOURCE_SHIFT)) & DMAMUX_CHCFG_SOURCE_MASK)
AnnaBridge 143:86740a56073b 4576 #define DMAMUX_CHCFG_TRIG_MASK (0x40U)
AnnaBridge 143:86740a56073b 4577 #define DMAMUX_CHCFG_TRIG_SHIFT (6U)
AnnaBridge 143:86740a56073b 4578 #define DMAMUX_CHCFG_TRIG(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_TRIG_SHIFT)) & DMAMUX_CHCFG_TRIG_MASK)
AnnaBridge 143:86740a56073b 4579 #define DMAMUX_CHCFG_ENBL_MASK (0x80U)
AnnaBridge 143:86740a56073b 4580 #define DMAMUX_CHCFG_ENBL_SHIFT (7U)
AnnaBridge 143:86740a56073b 4581 #define DMAMUX_CHCFG_ENBL(x) (((uint8_t)(((uint8_t)(x)) << DMAMUX_CHCFG_ENBL_SHIFT)) & DMAMUX_CHCFG_ENBL_MASK)
AnnaBridge 143:86740a56073b 4582
AnnaBridge 143:86740a56073b 4583 /* The count of DMAMUX_CHCFG */
AnnaBridge 143:86740a56073b 4584 #define DMAMUX_CHCFG_COUNT (16U)
AnnaBridge 143:86740a56073b 4585
AnnaBridge 143:86740a56073b 4586
AnnaBridge 143:86740a56073b 4587 /*!
AnnaBridge 143:86740a56073b 4588 * @}
AnnaBridge 143:86740a56073b 4589 */ /* end of group DMAMUX_Register_Masks */
AnnaBridge 143:86740a56073b 4590
AnnaBridge 143:86740a56073b 4591
AnnaBridge 143:86740a56073b 4592 /* DMAMUX - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 4593 /** Peripheral DMAMUX base address */
AnnaBridge 143:86740a56073b 4594 #define DMAMUX_BASE (0x40021000u)
AnnaBridge 143:86740a56073b 4595 /** Peripheral DMAMUX base pointer */
AnnaBridge 143:86740a56073b 4596 #define DMAMUX ((DMAMUX_Type *)DMAMUX_BASE)
AnnaBridge 143:86740a56073b 4597 /** Array initializer of DMAMUX peripheral base addresses */
AnnaBridge 143:86740a56073b 4598 #define DMAMUX_BASE_ADDRS { DMAMUX_BASE }
AnnaBridge 143:86740a56073b 4599 /** Array initializer of DMAMUX peripheral base pointers */
AnnaBridge 143:86740a56073b 4600 #define DMAMUX_BASE_PTRS { DMAMUX }
AnnaBridge 143:86740a56073b 4601
AnnaBridge 143:86740a56073b 4602 /*!
AnnaBridge 143:86740a56073b 4603 * @}
AnnaBridge 143:86740a56073b 4604 */ /* end of group DMAMUX_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 4605
AnnaBridge 143:86740a56073b 4606
AnnaBridge 143:86740a56073b 4607 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4608 -- EWM Peripheral Access Layer
AnnaBridge 143:86740a56073b 4609 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4610
AnnaBridge 143:86740a56073b 4611 /*!
AnnaBridge 143:86740a56073b 4612 * @addtogroup EWM_Peripheral_Access_Layer EWM Peripheral Access Layer
AnnaBridge 143:86740a56073b 4613 * @{
AnnaBridge 143:86740a56073b 4614 */
AnnaBridge 143:86740a56073b 4615
AnnaBridge 143:86740a56073b 4616 /** EWM - Register Layout Typedef */
AnnaBridge 143:86740a56073b 4617 typedef struct {
AnnaBridge 143:86740a56073b 4618 __IO uint8_t CTRL; /**< Control Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 4619 __O uint8_t SERV; /**< Service Register, offset: 0x1 */
AnnaBridge 143:86740a56073b 4620 __IO uint8_t CMPL; /**< Compare Low Register, offset: 0x2 */
AnnaBridge 143:86740a56073b 4621 __IO uint8_t CMPH; /**< Compare High Register, offset: 0x3 */
AnnaBridge 143:86740a56073b 4622 } EWM_Type;
AnnaBridge 143:86740a56073b 4623
AnnaBridge 143:86740a56073b 4624 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4625 -- EWM Register Masks
AnnaBridge 143:86740a56073b 4626 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4627
AnnaBridge 143:86740a56073b 4628 /*!
AnnaBridge 143:86740a56073b 4629 * @addtogroup EWM_Register_Masks EWM Register Masks
AnnaBridge 143:86740a56073b 4630 * @{
AnnaBridge 143:86740a56073b 4631 */
AnnaBridge 143:86740a56073b 4632
AnnaBridge 143:86740a56073b 4633 /*! @name CTRL - Control Register */
AnnaBridge 143:86740a56073b 4634 #define EWM_CTRL_EWMEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 4635 #define EWM_CTRL_EWMEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 4636 #define EWM_CTRL_EWMEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_EWMEN_SHIFT)) & EWM_CTRL_EWMEN_MASK)
AnnaBridge 143:86740a56073b 4637 #define EWM_CTRL_ASSIN_MASK (0x2U)
AnnaBridge 143:86740a56073b 4638 #define EWM_CTRL_ASSIN_SHIFT (1U)
AnnaBridge 143:86740a56073b 4639 #define EWM_CTRL_ASSIN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_ASSIN_SHIFT)) & EWM_CTRL_ASSIN_MASK)
AnnaBridge 143:86740a56073b 4640 #define EWM_CTRL_INEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 4641 #define EWM_CTRL_INEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 4642 #define EWM_CTRL_INEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INEN_SHIFT)) & EWM_CTRL_INEN_MASK)
AnnaBridge 143:86740a56073b 4643 #define EWM_CTRL_INTEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 4644 #define EWM_CTRL_INTEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 4645 #define EWM_CTRL_INTEN(x) (((uint8_t)(((uint8_t)(x)) << EWM_CTRL_INTEN_SHIFT)) & EWM_CTRL_INTEN_MASK)
AnnaBridge 143:86740a56073b 4646
AnnaBridge 143:86740a56073b 4647 /*! @name SERV - Service Register */
AnnaBridge 143:86740a56073b 4648 #define EWM_SERV_SERVICE_MASK (0xFFU)
AnnaBridge 143:86740a56073b 4649 #define EWM_SERV_SERVICE_SHIFT (0U)
AnnaBridge 143:86740a56073b 4650 #define EWM_SERV_SERVICE(x) (((uint8_t)(((uint8_t)(x)) << EWM_SERV_SERVICE_SHIFT)) & EWM_SERV_SERVICE_MASK)
AnnaBridge 143:86740a56073b 4651
AnnaBridge 143:86740a56073b 4652 /*! @name CMPL - Compare Low Register */
AnnaBridge 143:86740a56073b 4653 #define EWM_CMPL_COMPAREL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 4654 #define EWM_CMPL_COMPAREL_SHIFT (0U)
AnnaBridge 143:86740a56073b 4655 #define EWM_CMPL_COMPAREL(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPL_COMPAREL_SHIFT)) & EWM_CMPL_COMPAREL_MASK)
AnnaBridge 143:86740a56073b 4656
AnnaBridge 143:86740a56073b 4657 /*! @name CMPH - Compare High Register */
AnnaBridge 143:86740a56073b 4658 #define EWM_CMPH_COMPAREH_MASK (0xFFU)
AnnaBridge 143:86740a56073b 4659 #define EWM_CMPH_COMPAREH_SHIFT (0U)
AnnaBridge 143:86740a56073b 4660 #define EWM_CMPH_COMPAREH(x) (((uint8_t)(((uint8_t)(x)) << EWM_CMPH_COMPAREH_SHIFT)) & EWM_CMPH_COMPAREH_MASK)
AnnaBridge 143:86740a56073b 4661
AnnaBridge 143:86740a56073b 4662
AnnaBridge 143:86740a56073b 4663 /*!
AnnaBridge 143:86740a56073b 4664 * @}
AnnaBridge 143:86740a56073b 4665 */ /* end of group EWM_Register_Masks */
AnnaBridge 143:86740a56073b 4666
AnnaBridge 143:86740a56073b 4667
AnnaBridge 143:86740a56073b 4668 /* EWM - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 4669 /** Peripheral EWM base address */
AnnaBridge 143:86740a56073b 4670 #define EWM_BASE (0x40061000u)
AnnaBridge 143:86740a56073b 4671 /** Peripheral EWM base pointer */
AnnaBridge 143:86740a56073b 4672 #define EWM ((EWM_Type *)EWM_BASE)
AnnaBridge 143:86740a56073b 4673 /** Array initializer of EWM peripheral base addresses */
AnnaBridge 143:86740a56073b 4674 #define EWM_BASE_ADDRS { EWM_BASE }
AnnaBridge 143:86740a56073b 4675 /** Array initializer of EWM peripheral base pointers */
AnnaBridge 143:86740a56073b 4676 #define EWM_BASE_PTRS { EWM }
AnnaBridge 143:86740a56073b 4677 /** Interrupt vectors for the EWM peripheral type */
AnnaBridge 143:86740a56073b 4678 #define EWM_IRQS { WDOG_EWM_IRQn }
AnnaBridge 143:86740a56073b 4679
AnnaBridge 143:86740a56073b 4680 /*!
AnnaBridge 143:86740a56073b 4681 * @}
AnnaBridge 143:86740a56073b 4682 */ /* end of group EWM_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 4683
AnnaBridge 143:86740a56073b 4684
AnnaBridge 143:86740a56073b 4685 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4686 -- FB Peripheral Access Layer
AnnaBridge 143:86740a56073b 4687 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4688
AnnaBridge 143:86740a56073b 4689 /*!
AnnaBridge 143:86740a56073b 4690 * @addtogroup FB_Peripheral_Access_Layer FB Peripheral Access Layer
AnnaBridge 143:86740a56073b 4691 * @{
AnnaBridge 143:86740a56073b 4692 */
AnnaBridge 143:86740a56073b 4693
AnnaBridge 143:86740a56073b 4694 /** FB - Register Layout Typedef */
AnnaBridge 143:86740a56073b 4695 typedef struct {
AnnaBridge 143:86740a56073b 4696 struct { /* offset: 0x0, array step: 0xC */
AnnaBridge 143:86740a56073b 4697 __IO uint32_t CSAR; /**< Chip Select Address Register, array offset: 0x0, array step: 0xC */
AnnaBridge 143:86740a56073b 4698 __IO uint32_t CSMR; /**< Chip Select Mask Register, array offset: 0x4, array step: 0xC */
AnnaBridge 143:86740a56073b 4699 __IO uint32_t CSCR; /**< Chip Select Control Register, array offset: 0x8, array step: 0xC */
AnnaBridge 143:86740a56073b 4700 } CS[6];
AnnaBridge 143:86740a56073b 4701 uint8_t RESERVED_0[24];
AnnaBridge 143:86740a56073b 4702 __IO uint32_t CSPMCR; /**< Chip Select port Multiplexing Control Register, offset: 0x60 */
AnnaBridge 143:86740a56073b 4703 } FB_Type;
AnnaBridge 143:86740a56073b 4704
AnnaBridge 143:86740a56073b 4705 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4706 -- FB Register Masks
AnnaBridge 143:86740a56073b 4707 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4708
AnnaBridge 143:86740a56073b 4709 /*!
AnnaBridge 143:86740a56073b 4710 * @addtogroup FB_Register_Masks FB Register Masks
AnnaBridge 143:86740a56073b 4711 * @{
AnnaBridge 143:86740a56073b 4712 */
AnnaBridge 143:86740a56073b 4713
AnnaBridge 143:86740a56073b 4714 /*! @name CSAR - Chip Select Address Register */
AnnaBridge 143:86740a56073b 4715 #define FB_CSAR_BA_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 4716 #define FB_CSAR_BA_SHIFT (16U)
AnnaBridge 143:86740a56073b 4717 #define FB_CSAR_BA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSAR_BA_SHIFT)) & FB_CSAR_BA_MASK)
AnnaBridge 143:86740a56073b 4718
AnnaBridge 143:86740a56073b 4719 /* The count of FB_CSAR */
AnnaBridge 143:86740a56073b 4720 #define FB_CSAR_COUNT (6U)
AnnaBridge 143:86740a56073b 4721
AnnaBridge 143:86740a56073b 4722 /*! @name CSMR - Chip Select Mask Register */
AnnaBridge 143:86740a56073b 4723 #define FB_CSMR_V_MASK (0x1U)
AnnaBridge 143:86740a56073b 4724 #define FB_CSMR_V_SHIFT (0U)
AnnaBridge 143:86740a56073b 4725 #define FB_CSMR_V(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_V_SHIFT)) & FB_CSMR_V_MASK)
AnnaBridge 143:86740a56073b 4726 #define FB_CSMR_WP_MASK (0x100U)
AnnaBridge 143:86740a56073b 4727 #define FB_CSMR_WP_SHIFT (8U)
AnnaBridge 143:86740a56073b 4728 #define FB_CSMR_WP(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_WP_SHIFT)) & FB_CSMR_WP_MASK)
AnnaBridge 143:86740a56073b 4729 #define FB_CSMR_BAM_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 4730 #define FB_CSMR_BAM_SHIFT (16U)
AnnaBridge 143:86740a56073b 4731 #define FB_CSMR_BAM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSMR_BAM_SHIFT)) & FB_CSMR_BAM_MASK)
AnnaBridge 143:86740a56073b 4732
AnnaBridge 143:86740a56073b 4733 /* The count of FB_CSMR */
AnnaBridge 143:86740a56073b 4734 #define FB_CSMR_COUNT (6U)
AnnaBridge 143:86740a56073b 4735
AnnaBridge 143:86740a56073b 4736 /*! @name CSCR - Chip Select Control Register */
AnnaBridge 143:86740a56073b 4737 #define FB_CSCR_BSTW_MASK (0x8U)
AnnaBridge 143:86740a56073b 4738 #define FB_CSCR_BSTW_SHIFT (3U)
AnnaBridge 143:86740a56073b 4739 #define FB_CSCR_BSTW(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTW_SHIFT)) & FB_CSCR_BSTW_MASK)
AnnaBridge 143:86740a56073b 4740 #define FB_CSCR_BSTR_MASK (0x10U)
AnnaBridge 143:86740a56073b 4741 #define FB_CSCR_BSTR_SHIFT (4U)
AnnaBridge 143:86740a56073b 4742 #define FB_CSCR_BSTR(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BSTR_SHIFT)) & FB_CSCR_BSTR_MASK)
AnnaBridge 143:86740a56073b 4743 #define FB_CSCR_BEM_MASK (0x20U)
AnnaBridge 143:86740a56073b 4744 #define FB_CSCR_BEM_SHIFT (5U)
AnnaBridge 143:86740a56073b 4745 #define FB_CSCR_BEM(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BEM_SHIFT)) & FB_CSCR_BEM_MASK)
AnnaBridge 143:86740a56073b 4746 #define FB_CSCR_PS_MASK (0xC0U)
AnnaBridge 143:86740a56073b 4747 #define FB_CSCR_PS_SHIFT (6U)
AnnaBridge 143:86740a56073b 4748 #define FB_CSCR_PS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_PS_SHIFT)) & FB_CSCR_PS_MASK)
AnnaBridge 143:86740a56073b 4749 #define FB_CSCR_AA_MASK (0x100U)
AnnaBridge 143:86740a56073b 4750 #define FB_CSCR_AA_SHIFT (8U)
AnnaBridge 143:86740a56073b 4751 #define FB_CSCR_AA(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_AA_SHIFT)) & FB_CSCR_AA_MASK)
AnnaBridge 143:86740a56073b 4752 #define FB_CSCR_BLS_MASK (0x200U)
AnnaBridge 143:86740a56073b 4753 #define FB_CSCR_BLS_SHIFT (9U)
AnnaBridge 143:86740a56073b 4754 #define FB_CSCR_BLS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_BLS_SHIFT)) & FB_CSCR_BLS_MASK)
AnnaBridge 143:86740a56073b 4755 #define FB_CSCR_WS_MASK (0xFC00U)
AnnaBridge 143:86740a56073b 4756 #define FB_CSCR_WS_SHIFT (10U)
AnnaBridge 143:86740a56073b 4757 #define FB_CSCR_WS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WS_SHIFT)) & FB_CSCR_WS_MASK)
AnnaBridge 143:86740a56073b 4758 #define FB_CSCR_WRAH_MASK (0x30000U)
AnnaBridge 143:86740a56073b 4759 #define FB_CSCR_WRAH_SHIFT (16U)
AnnaBridge 143:86740a56073b 4760 #define FB_CSCR_WRAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_WRAH_SHIFT)) & FB_CSCR_WRAH_MASK)
AnnaBridge 143:86740a56073b 4761 #define FB_CSCR_RDAH_MASK (0xC0000U)
AnnaBridge 143:86740a56073b 4762 #define FB_CSCR_RDAH_SHIFT (18U)
AnnaBridge 143:86740a56073b 4763 #define FB_CSCR_RDAH(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_RDAH_SHIFT)) & FB_CSCR_RDAH_MASK)
AnnaBridge 143:86740a56073b 4764 #define FB_CSCR_ASET_MASK (0x300000U)
AnnaBridge 143:86740a56073b 4765 #define FB_CSCR_ASET_SHIFT (20U)
AnnaBridge 143:86740a56073b 4766 #define FB_CSCR_ASET(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_ASET_SHIFT)) & FB_CSCR_ASET_MASK)
AnnaBridge 143:86740a56073b 4767 #define FB_CSCR_EXTS_MASK (0x400000U)
AnnaBridge 143:86740a56073b 4768 #define FB_CSCR_EXTS_SHIFT (22U)
AnnaBridge 143:86740a56073b 4769 #define FB_CSCR_EXTS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_EXTS_SHIFT)) & FB_CSCR_EXTS_MASK)
AnnaBridge 143:86740a56073b 4770 #define FB_CSCR_SWSEN_MASK (0x800000U)
AnnaBridge 143:86740a56073b 4771 #define FB_CSCR_SWSEN_SHIFT (23U)
AnnaBridge 143:86740a56073b 4772 #define FB_CSCR_SWSEN(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWSEN_SHIFT)) & FB_CSCR_SWSEN_MASK)
AnnaBridge 143:86740a56073b 4773 #define FB_CSCR_SWS_MASK (0xFC000000U)
AnnaBridge 143:86740a56073b 4774 #define FB_CSCR_SWS_SHIFT (26U)
AnnaBridge 143:86740a56073b 4775 #define FB_CSCR_SWS(x) (((uint32_t)(((uint32_t)(x)) << FB_CSCR_SWS_SHIFT)) & FB_CSCR_SWS_MASK)
AnnaBridge 143:86740a56073b 4776
AnnaBridge 143:86740a56073b 4777 /* The count of FB_CSCR */
AnnaBridge 143:86740a56073b 4778 #define FB_CSCR_COUNT (6U)
AnnaBridge 143:86740a56073b 4779
AnnaBridge 143:86740a56073b 4780 /*! @name CSPMCR - Chip Select port Multiplexing Control Register */
AnnaBridge 143:86740a56073b 4781 #define FB_CSPMCR_GROUP5_MASK (0xF000U)
AnnaBridge 143:86740a56073b 4782 #define FB_CSPMCR_GROUP5_SHIFT (12U)
AnnaBridge 143:86740a56073b 4783 #define FB_CSPMCR_GROUP5(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP5_SHIFT)) & FB_CSPMCR_GROUP5_MASK)
AnnaBridge 143:86740a56073b 4784 #define FB_CSPMCR_GROUP4_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 4785 #define FB_CSPMCR_GROUP4_SHIFT (16U)
AnnaBridge 143:86740a56073b 4786 #define FB_CSPMCR_GROUP4(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP4_SHIFT)) & FB_CSPMCR_GROUP4_MASK)
AnnaBridge 143:86740a56073b 4787 #define FB_CSPMCR_GROUP3_MASK (0xF00000U)
AnnaBridge 143:86740a56073b 4788 #define FB_CSPMCR_GROUP3_SHIFT (20U)
AnnaBridge 143:86740a56073b 4789 #define FB_CSPMCR_GROUP3(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP3_SHIFT)) & FB_CSPMCR_GROUP3_MASK)
AnnaBridge 143:86740a56073b 4790 #define FB_CSPMCR_GROUP2_MASK (0xF000000U)
AnnaBridge 143:86740a56073b 4791 #define FB_CSPMCR_GROUP2_SHIFT (24U)
AnnaBridge 143:86740a56073b 4792 #define FB_CSPMCR_GROUP2(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP2_SHIFT)) & FB_CSPMCR_GROUP2_MASK)
AnnaBridge 143:86740a56073b 4793 #define FB_CSPMCR_GROUP1_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 4794 #define FB_CSPMCR_GROUP1_SHIFT (28U)
AnnaBridge 143:86740a56073b 4795 #define FB_CSPMCR_GROUP1(x) (((uint32_t)(((uint32_t)(x)) << FB_CSPMCR_GROUP1_SHIFT)) & FB_CSPMCR_GROUP1_MASK)
AnnaBridge 143:86740a56073b 4796
AnnaBridge 143:86740a56073b 4797
AnnaBridge 143:86740a56073b 4798 /*!
AnnaBridge 143:86740a56073b 4799 * @}
AnnaBridge 143:86740a56073b 4800 */ /* end of group FB_Register_Masks */
AnnaBridge 143:86740a56073b 4801
AnnaBridge 143:86740a56073b 4802
AnnaBridge 143:86740a56073b 4803 /* FB - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 4804 /** Peripheral FB base address */
AnnaBridge 143:86740a56073b 4805 #define FB_BASE (0x4000C000u)
AnnaBridge 143:86740a56073b 4806 /** Peripheral FB base pointer */
AnnaBridge 143:86740a56073b 4807 #define FB ((FB_Type *)FB_BASE)
AnnaBridge 143:86740a56073b 4808 /** Array initializer of FB peripheral base addresses */
AnnaBridge 143:86740a56073b 4809 #define FB_BASE_ADDRS { FB_BASE }
AnnaBridge 143:86740a56073b 4810 /** Array initializer of FB peripheral base pointers */
AnnaBridge 143:86740a56073b 4811 #define FB_BASE_PTRS { FB }
AnnaBridge 143:86740a56073b 4812
AnnaBridge 143:86740a56073b 4813 /*!
AnnaBridge 143:86740a56073b 4814 * @}
AnnaBridge 143:86740a56073b 4815 */ /* end of group FB_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 4816
AnnaBridge 143:86740a56073b 4817
AnnaBridge 143:86740a56073b 4818 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4819 -- FMC Peripheral Access Layer
AnnaBridge 143:86740a56073b 4820 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4821
AnnaBridge 143:86740a56073b 4822 /*!
AnnaBridge 143:86740a56073b 4823 * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
AnnaBridge 143:86740a56073b 4824 * @{
AnnaBridge 143:86740a56073b 4825 */
AnnaBridge 143:86740a56073b 4826
AnnaBridge 143:86740a56073b 4827 /** FMC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 4828 typedef struct {
AnnaBridge 143:86740a56073b 4829 __IO uint32_t PFAPR; /**< Flash Access Protection Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 4830 __IO uint32_t PFB0CR; /**< Flash Bank 0 Control Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 4831 __IO uint32_t PFB1CR; /**< Flash Bank 1 Control Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 4832 uint8_t RESERVED_0[244];
AnnaBridge 143:86740a56073b 4833 __IO uint32_t TAGVDW0S[4]; /**< Cache Tag Storage, array offset: 0x100, array step: 0x4 */
AnnaBridge 143:86740a56073b 4834 __IO uint32_t TAGVDW1S[4]; /**< Cache Tag Storage, array offset: 0x110, array step: 0x4 */
AnnaBridge 143:86740a56073b 4835 __IO uint32_t TAGVDW2S[4]; /**< Cache Tag Storage, array offset: 0x120, array step: 0x4 */
AnnaBridge 143:86740a56073b 4836 __IO uint32_t TAGVDW3S[4]; /**< Cache Tag Storage, array offset: 0x130, array step: 0x4 */
AnnaBridge 143:86740a56073b 4837 uint8_t RESERVED_1[192];
AnnaBridge 143:86740a56073b 4838 struct { /* offset: 0x200, array step: index*0x20, index2*0x8 */
AnnaBridge 143:86740a56073b 4839 __IO uint32_t DATA_U; /**< Cache Data Storage (upper word), array offset: 0x200, array step: index*0x20, index2*0x8 */
AnnaBridge 143:86740a56073b 4840 __IO uint32_t DATA_L; /**< Cache Data Storage (lower word), array offset: 0x204, array step: index*0x20, index2*0x8 */
AnnaBridge 143:86740a56073b 4841 } SET[4][4];
AnnaBridge 143:86740a56073b 4842 } FMC_Type;
AnnaBridge 143:86740a56073b 4843
AnnaBridge 143:86740a56073b 4844 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 4845 -- FMC Register Masks
AnnaBridge 143:86740a56073b 4846 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 4847
AnnaBridge 143:86740a56073b 4848 /*!
AnnaBridge 143:86740a56073b 4849 * @addtogroup FMC_Register_Masks FMC Register Masks
AnnaBridge 143:86740a56073b 4850 * @{
AnnaBridge 143:86740a56073b 4851 */
AnnaBridge 143:86740a56073b 4852
AnnaBridge 143:86740a56073b 4853 /*! @name PFAPR - Flash Access Protection Register */
AnnaBridge 143:86740a56073b 4854 #define FMC_PFAPR_M0AP_MASK (0x3U)
AnnaBridge 143:86740a56073b 4855 #define FMC_PFAPR_M0AP_SHIFT (0U)
AnnaBridge 143:86740a56073b 4856 #define FMC_PFAPR_M0AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0AP_SHIFT)) & FMC_PFAPR_M0AP_MASK)
AnnaBridge 143:86740a56073b 4857 #define FMC_PFAPR_M1AP_MASK (0xCU)
AnnaBridge 143:86740a56073b 4858 #define FMC_PFAPR_M1AP_SHIFT (2U)
AnnaBridge 143:86740a56073b 4859 #define FMC_PFAPR_M1AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1AP_SHIFT)) & FMC_PFAPR_M1AP_MASK)
AnnaBridge 143:86740a56073b 4860 #define FMC_PFAPR_M2AP_MASK (0x30U)
AnnaBridge 143:86740a56073b 4861 #define FMC_PFAPR_M2AP_SHIFT (4U)
AnnaBridge 143:86740a56073b 4862 #define FMC_PFAPR_M2AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2AP_SHIFT)) & FMC_PFAPR_M2AP_MASK)
AnnaBridge 143:86740a56073b 4863 #define FMC_PFAPR_M3AP_MASK (0xC0U)
AnnaBridge 143:86740a56073b 4864 #define FMC_PFAPR_M3AP_SHIFT (6U)
AnnaBridge 143:86740a56073b 4865 #define FMC_PFAPR_M3AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3AP_SHIFT)) & FMC_PFAPR_M3AP_MASK)
AnnaBridge 143:86740a56073b 4866 #define FMC_PFAPR_M4AP_MASK (0x300U)
AnnaBridge 143:86740a56073b 4867 #define FMC_PFAPR_M4AP_SHIFT (8U)
AnnaBridge 143:86740a56073b 4868 #define FMC_PFAPR_M4AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4AP_SHIFT)) & FMC_PFAPR_M4AP_MASK)
AnnaBridge 143:86740a56073b 4869 #define FMC_PFAPR_M5AP_MASK (0xC00U)
AnnaBridge 143:86740a56073b 4870 #define FMC_PFAPR_M5AP_SHIFT (10U)
AnnaBridge 143:86740a56073b 4871 #define FMC_PFAPR_M5AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5AP_SHIFT)) & FMC_PFAPR_M5AP_MASK)
AnnaBridge 143:86740a56073b 4872 #define FMC_PFAPR_M6AP_MASK (0x3000U)
AnnaBridge 143:86740a56073b 4873 #define FMC_PFAPR_M6AP_SHIFT (12U)
AnnaBridge 143:86740a56073b 4874 #define FMC_PFAPR_M6AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6AP_SHIFT)) & FMC_PFAPR_M6AP_MASK)
AnnaBridge 143:86740a56073b 4875 #define FMC_PFAPR_M7AP_MASK (0xC000U)
AnnaBridge 143:86740a56073b 4876 #define FMC_PFAPR_M7AP_SHIFT (14U)
AnnaBridge 143:86740a56073b 4877 #define FMC_PFAPR_M7AP(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7AP_SHIFT)) & FMC_PFAPR_M7AP_MASK)
AnnaBridge 143:86740a56073b 4878 #define FMC_PFAPR_M0PFD_MASK (0x10000U)
AnnaBridge 143:86740a56073b 4879 #define FMC_PFAPR_M0PFD_SHIFT (16U)
AnnaBridge 143:86740a56073b 4880 #define FMC_PFAPR_M0PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M0PFD_SHIFT)) & FMC_PFAPR_M0PFD_MASK)
AnnaBridge 143:86740a56073b 4881 #define FMC_PFAPR_M1PFD_MASK (0x20000U)
AnnaBridge 143:86740a56073b 4882 #define FMC_PFAPR_M1PFD_SHIFT (17U)
AnnaBridge 143:86740a56073b 4883 #define FMC_PFAPR_M1PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M1PFD_SHIFT)) & FMC_PFAPR_M1PFD_MASK)
AnnaBridge 143:86740a56073b 4884 #define FMC_PFAPR_M2PFD_MASK (0x40000U)
AnnaBridge 143:86740a56073b 4885 #define FMC_PFAPR_M2PFD_SHIFT (18U)
AnnaBridge 143:86740a56073b 4886 #define FMC_PFAPR_M2PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M2PFD_SHIFT)) & FMC_PFAPR_M2PFD_MASK)
AnnaBridge 143:86740a56073b 4887 #define FMC_PFAPR_M3PFD_MASK (0x80000U)
AnnaBridge 143:86740a56073b 4888 #define FMC_PFAPR_M3PFD_SHIFT (19U)
AnnaBridge 143:86740a56073b 4889 #define FMC_PFAPR_M3PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M3PFD_SHIFT)) & FMC_PFAPR_M3PFD_MASK)
AnnaBridge 143:86740a56073b 4890 #define FMC_PFAPR_M4PFD_MASK (0x100000U)
AnnaBridge 143:86740a56073b 4891 #define FMC_PFAPR_M4PFD_SHIFT (20U)
AnnaBridge 143:86740a56073b 4892 #define FMC_PFAPR_M4PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M4PFD_SHIFT)) & FMC_PFAPR_M4PFD_MASK)
AnnaBridge 143:86740a56073b 4893 #define FMC_PFAPR_M5PFD_MASK (0x200000U)
AnnaBridge 143:86740a56073b 4894 #define FMC_PFAPR_M5PFD_SHIFT (21U)
AnnaBridge 143:86740a56073b 4895 #define FMC_PFAPR_M5PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M5PFD_SHIFT)) & FMC_PFAPR_M5PFD_MASK)
AnnaBridge 143:86740a56073b 4896 #define FMC_PFAPR_M6PFD_MASK (0x400000U)
AnnaBridge 143:86740a56073b 4897 #define FMC_PFAPR_M6PFD_SHIFT (22U)
AnnaBridge 143:86740a56073b 4898 #define FMC_PFAPR_M6PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M6PFD_SHIFT)) & FMC_PFAPR_M6PFD_MASK)
AnnaBridge 143:86740a56073b 4899 #define FMC_PFAPR_M7PFD_MASK (0x800000U)
AnnaBridge 143:86740a56073b 4900 #define FMC_PFAPR_M7PFD_SHIFT (23U)
AnnaBridge 143:86740a56073b 4901 #define FMC_PFAPR_M7PFD(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFAPR_M7PFD_SHIFT)) & FMC_PFAPR_M7PFD_MASK)
AnnaBridge 143:86740a56073b 4902
AnnaBridge 143:86740a56073b 4903 /*! @name PFB0CR - Flash Bank 0 Control Register */
AnnaBridge 143:86740a56073b 4904 #define FMC_PFB0CR_B0SEBE_MASK (0x1U)
AnnaBridge 143:86740a56073b 4905 #define FMC_PFB0CR_B0SEBE_SHIFT (0U)
AnnaBridge 143:86740a56073b 4906 #define FMC_PFB0CR_B0SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0SEBE_SHIFT)) & FMC_PFB0CR_B0SEBE_MASK)
AnnaBridge 143:86740a56073b 4907 #define FMC_PFB0CR_B0IPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 4908 #define FMC_PFB0CR_B0IPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 4909 #define FMC_PFB0CR_B0IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0IPE_SHIFT)) & FMC_PFB0CR_B0IPE_MASK)
AnnaBridge 143:86740a56073b 4910 #define FMC_PFB0CR_B0DPE_MASK (0x4U)
AnnaBridge 143:86740a56073b 4911 #define FMC_PFB0CR_B0DPE_SHIFT (2U)
AnnaBridge 143:86740a56073b 4912 #define FMC_PFB0CR_B0DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DPE_SHIFT)) & FMC_PFB0CR_B0DPE_MASK)
AnnaBridge 143:86740a56073b 4913 #define FMC_PFB0CR_B0ICE_MASK (0x8U)
AnnaBridge 143:86740a56073b 4914 #define FMC_PFB0CR_B0ICE_SHIFT (3U)
AnnaBridge 143:86740a56073b 4915 #define FMC_PFB0CR_B0ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0ICE_SHIFT)) & FMC_PFB0CR_B0ICE_MASK)
AnnaBridge 143:86740a56073b 4916 #define FMC_PFB0CR_B0DCE_MASK (0x10U)
AnnaBridge 143:86740a56073b 4917 #define FMC_PFB0CR_B0DCE_SHIFT (4U)
AnnaBridge 143:86740a56073b 4918 #define FMC_PFB0CR_B0DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0DCE_SHIFT)) & FMC_PFB0CR_B0DCE_MASK)
AnnaBridge 143:86740a56073b 4919 #define FMC_PFB0CR_CRC_MASK (0xE0U)
AnnaBridge 143:86740a56073b 4920 #define FMC_PFB0CR_CRC_SHIFT (5U)
AnnaBridge 143:86740a56073b 4921 #define FMC_PFB0CR_CRC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CRC_SHIFT)) & FMC_PFB0CR_CRC_MASK)
AnnaBridge 143:86740a56073b 4922 #define FMC_PFB0CR_B0MW_MASK (0x60000U)
AnnaBridge 143:86740a56073b 4923 #define FMC_PFB0CR_B0MW_SHIFT (17U)
AnnaBridge 143:86740a56073b 4924 #define FMC_PFB0CR_B0MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0MW_SHIFT)) & FMC_PFB0CR_B0MW_MASK)
AnnaBridge 143:86740a56073b 4925 #define FMC_PFB0CR_S_B_INV_MASK (0x80000U)
AnnaBridge 143:86740a56073b 4926 #define FMC_PFB0CR_S_B_INV_SHIFT (19U)
AnnaBridge 143:86740a56073b 4927 #define FMC_PFB0CR_S_B_INV(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_S_B_INV_SHIFT)) & FMC_PFB0CR_S_B_INV_MASK)
AnnaBridge 143:86740a56073b 4928 #define FMC_PFB0CR_CINV_WAY_MASK (0xF00000U)
AnnaBridge 143:86740a56073b 4929 #define FMC_PFB0CR_CINV_WAY_SHIFT (20U)
AnnaBridge 143:86740a56073b 4930 #define FMC_PFB0CR_CINV_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CINV_WAY_SHIFT)) & FMC_PFB0CR_CINV_WAY_MASK)
AnnaBridge 143:86740a56073b 4931 #define FMC_PFB0CR_CLCK_WAY_MASK (0xF000000U)
AnnaBridge 143:86740a56073b 4932 #define FMC_PFB0CR_CLCK_WAY_SHIFT (24U)
AnnaBridge 143:86740a56073b 4933 #define FMC_PFB0CR_CLCK_WAY(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_CLCK_WAY_SHIFT)) & FMC_PFB0CR_CLCK_WAY_MASK)
AnnaBridge 143:86740a56073b 4934 #define FMC_PFB0CR_B0RWSC_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 4935 #define FMC_PFB0CR_B0RWSC_SHIFT (28U)
AnnaBridge 143:86740a56073b 4936 #define FMC_PFB0CR_B0RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB0CR_B0RWSC_SHIFT)) & FMC_PFB0CR_B0RWSC_MASK)
AnnaBridge 143:86740a56073b 4937
AnnaBridge 143:86740a56073b 4938 /*! @name PFB1CR - Flash Bank 1 Control Register */
AnnaBridge 143:86740a56073b 4939 #define FMC_PFB1CR_B1SEBE_MASK (0x1U)
AnnaBridge 143:86740a56073b 4940 #define FMC_PFB1CR_B1SEBE_SHIFT (0U)
AnnaBridge 143:86740a56073b 4941 #define FMC_PFB1CR_B1SEBE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1SEBE_SHIFT)) & FMC_PFB1CR_B1SEBE_MASK)
AnnaBridge 143:86740a56073b 4942 #define FMC_PFB1CR_B1IPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 4943 #define FMC_PFB1CR_B1IPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 4944 #define FMC_PFB1CR_B1IPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1IPE_SHIFT)) & FMC_PFB1CR_B1IPE_MASK)
AnnaBridge 143:86740a56073b 4945 #define FMC_PFB1CR_B1DPE_MASK (0x4U)
AnnaBridge 143:86740a56073b 4946 #define FMC_PFB1CR_B1DPE_SHIFT (2U)
AnnaBridge 143:86740a56073b 4947 #define FMC_PFB1CR_B1DPE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DPE_SHIFT)) & FMC_PFB1CR_B1DPE_MASK)
AnnaBridge 143:86740a56073b 4948 #define FMC_PFB1CR_B1ICE_MASK (0x8U)
AnnaBridge 143:86740a56073b 4949 #define FMC_PFB1CR_B1ICE_SHIFT (3U)
AnnaBridge 143:86740a56073b 4950 #define FMC_PFB1CR_B1ICE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1ICE_SHIFT)) & FMC_PFB1CR_B1ICE_MASK)
AnnaBridge 143:86740a56073b 4951 #define FMC_PFB1CR_B1DCE_MASK (0x10U)
AnnaBridge 143:86740a56073b 4952 #define FMC_PFB1CR_B1DCE_SHIFT (4U)
AnnaBridge 143:86740a56073b 4953 #define FMC_PFB1CR_B1DCE(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1DCE_SHIFT)) & FMC_PFB1CR_B1DCE_MASK)
AnnaBridge 143:86740a56073b 4954 #define FMC_PFB1CR_B1MW_MASK (0x60000U)
AnnaBridge 143:86740a56073b 4955 #define FMC_PFB1CR_B1MW_SHIFT (17U)
AnnaBridge 143:86740a56073b 4956 #define FMC_PFB1CR_B1MW(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1MW_SHIFT)) & FMC_PFB1CR_B1MW_MASK)
AnnaBridge 143:86740a56073b 4957 #define FMC_PFB1CR_B1RWSC_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 4958 #define FMC_PFB1CR_B1RWSC_SHIFT (28U)
AnnaBridge 143:86740a56073b 4959 #define FMC_PFB1CR_B1RWSC(x) (((uint32_t)(((uint32_t)(x)) << FMC_PFB1CR_B1RWSC_SHIFT)) & FMC_PFB1CR_B1RWSC_MASK)
AnnaBridge 143:86740a56073b 4960
AnnaBridge 143:86740a56073b 4961 /*! @name TAGVDW0S - Cache Tag Storage */
AnnaBridge 143:86740a56073b 4962 #define FMC_TAGVDW0S_valid_MASK (0x1U)
AnnaBridge 143:86740a56073b 4963 #define FMC_TAGVDW0S_valid_SHIFT (0U)
AnnaBridge 143:86740a56073b 4964 #define FMC_TAGVDW0S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_valid_SHIFT)) & FMC_TAGVDW0S_valid_MASK)
AnnaBridge 143:86740a56073b 4965 #define FMC_TAGVDW0S_tag_MASK (0x7FFE0U)
AnnaBridge 143:86740a56073b 4966 #define FMC_TAGVDW0S_tag_SHIFT (5U)
AnnaBridge 143:86740a56073b 4967 #define FMC_TAGVDW0S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW0S_tag_SHIFT)) & FMC_TAGVDW0S_tag_MASK)
AnnaBridge 143:86740a56073b 4968
AnnaBridge 143:86740a56073b 4969 /* The count of FMC_TAGVDW0S */
AnnaBridge 143:86740a56073b 4970 #define FMC_TAGVDW0S_COUNT (4U)
AnnaBridge 143:86740a56073b 4971
AnnaBridge 143:86740a56073b 4972 /*! @name TAGVDW1S - Cache Tag Storage */
AnnaBridge 143:86740a56073b 4973 #define FMC_TAGVDW1S_valid_MASK (0x1U)
AnnaBridge 143:86740a56073b 4974 #define FMC_TAGVDW1S_valid_SHIFT (0U)
AnnaBridge 143:86740a56073b 4975 #define FMC_TAGVDW1S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_valid_SHIFT)) & FMC_TAGVDW1S_valid_MASK)
AnnaBridge 143:86740a56073b 4976 #define FMC_TAGVDW1S_tag_MASK (0x7FFE0U)
AnnaBridge 143:86740a56073b 4977 #define FMC_TAGVDW1S_tag_SHIFT (5U)
AnnaBridge 143:86740a56073b 4978 #define FMC_TAGVDW1S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW1S_tag_SHIFT)) & FMC_TAGVDW1S_tag_MASK)
AnnaBridge 143:86740a56073b 4979
AnnaBridge 143:86740a56073b 4980 /* The count of FMC_TAGVDW1S */
AnnaBridge 143:86740a56073b 4981 #define FMC_TAGVDW1S_COUNT (4U)
AnnaBridge 143:86740a56073b 4982
AnnaBridge 143:86740a56073b 4983 /*! @name TAGVDW2S - Cache Tag Storage */
AnnaBridge 143:86740a56073b 4984 #define FMC_TAGVDW2S_valid_MASK (0x1U)
AnnaBridge 143:86740a56073b 4985 #define FMC_TAGVDW2S_valid_SHIFT (0U)
AnnaBridge 143:86740a56073b 4986 #define FMC_TAGVDW2S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_valid_SHIFT)) & FMC_TAGVDW2S_valid_MASK)
AnnaBridge 143:86740a56073b 4987 #define FMC_TAGVDW2S_tag_MASK (0x7FFE0U)
AnnaBridge 143:86740a56073b 4988 #define FMC_TAGVDW2S_tag_SHIFT (5U)
AnnaBridge 143:86740a56073b 4989 #define FMC_TAGVDW2S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW2S_tag_SHIFT)) & FMC_TAGVDW2S_tag_MASK)
AnnaBridge 143:86740a56073b 4990
AnnaBridge 143:86740a56073b 4991 /* The count of FMC_TAGVDW2S */
AnnaBridge 143:86740a56073b 4992 #define FMC_TAGVDW2S_COUNT (4U)
AnnaBridge 143:86740a56073b 4993
AnnaBridge 143:86740a56073b 4994 /*! @name TAGVDW3S - Cache Tag Storage */
AnnaBridge 143:86740a56073b 4995 #define FMC_TAGVDW3S_valid_MASK (0x1U)
AnnaBridge 143:86740a56073b 4996 #define FMC_TAGVDW3S_valid_SHIFT (0U)
AnnaBridge 143:86740a56073b 4997 #define FMC_TAGVDW3S_valid(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_valid_SHIFT)) & FMC_TAGVDW3S_valid_MASK)
AnnaBridge 143:86740a56073b 4998 #define FMC_TAGVDW3S_tag_MASK (0x7FFE0U)
AnnaBridge 143:86740a56073b 4999 #define FMC_TAGVDW3S_tag_SHIFT (5U)
AnnaBridge 143:86740a56073b 5000 #define FMC_TAGVDW3S_tag(x) (((uint32_t)(((uint32_t)(x)) << FMC_TAGVDW3S_tag_SHIFT)) & FMC_TAGVDW3S_tag_MASK)
AnnaBridge 143:86740a56073b 5001
AnnaBridge 143:86740a56073b 5002 /* The count of FMC_TAGVDW3S */
AnnaBridge 143:86740a56073b 5003 #define FMC_TAGVDW3S_COUNT (4U)
AnnaBridge 143:86740a56073b 5004
AnnaBridge 143:86740a56073b 5005 /*! @name DATA_U - Cache Data Storage (upper word) */
AnnaBridge 143:86740a56073b 5006 #define FMC_DATA_U_data_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5007 #define FMC_DATA_U_data_SHIFT (0U)
AnnaBridge 143:86740a56073b 5008 #define FMC_DATA_U_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_U_data_SHIFT)) & FMC_DATA_U_data_MASK)
AnnaBridge 143:86740a56073b 5009
AnnaBridge 143:86740a56073b 5010 /* The count of FMC_DATA_U */
AnnaBridge 143:86740a56073b 5011 #define FMC_DATA_U_COUNT (4U)
AnnaBridge 143:86740a56073b 5012
AnnaBridge 143:86740a56073b 5013 /* The count of FMC_DATA_U */
AnnaBridge 143:86740a56073b 5014 #define FMC_DATA_U_COUNT2 (4U)
AnnaBridge 143:86740a56073b 5015
AnnaBridge 143:86740a56073b 5016 /*! @name DATA_L - Cache Data Storage (lower word) */
AnnaBridge 143:86740a56073b 5017 #define FMC_DATA_L_data_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5018 #define FMC_DATA_L_data_SHIFT (0U)
AnnaBridge 143:86740a56073b 5019 #define FMC_DATA_L_data(x) (((uint32_t)(((uint32_t)(x)) << FMC_DATA_L_data_SHIFT)) & FMC_DATA_L_data_MASK)
AnnaBridge 143:86740a56073b 5020
AnnaBridge 143:86740a56073b 5021 /* The count of FMC_DATA_L */
AnnaBridge 143:86740a56073b 5022 #define FMC_DATA_L_COUNT (4U)
AnnaBridge 143:86740a56073b 5023
AnnaBridge 143:86740a56073b 5024 /* The count of FMC_DATA_L */
AnnaBridge 143:86740a56073b 5025 #define FMC_DATA_L_COUNT2 (4U)
AnnaBridge 143:86740a56073b 5026
AnnaBridge 143:86740a56073b 5027
AnnaBridge 143:86740a56073b 5028 /*!
AnnaBridge 143:86740a56073b 5029 * @}
AnnaBridge 143:86740a56073b 5030 */ /* end of group FMC_Register_Masks */
AnnaBridge 143:86740a56073b 5031
AnnaBridge 143:86740a56073b 5032
AnnaBridge 143:86740a56073b 5033 /* FMC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 5034 /** Peripheral FMC base address */
AnnaBridge 143:86740a56073b 5035 #define FMC_BASE (0x4001F000u)
AnnaBridge 143:86740a56073b 5036 /** Peripheral FMC base pointer */
AnnaBridge 143:86740a56073b 5037 #define FMC ((FMC_Type *)FMC_BASE)
AnnaBridge 143:86740a56073b 5038 /** Array initializer of FMC peripheral base addresses */
AnnaBridge 143:86740a56073b 5039 #define FMC_BASE_ADDRS { FMC_BASE }
AnnaBridge 143:86740a56073b 5040 /** Array initializer of FMC peripheral base pointers */
AnnaBridge 143:86740a56073b 5041 #define FMC_BASE_PTRS { FMC }
AnnaBridge 143:86740a56073b 5042
AnnaBridge 143:86740a56073b 5043 /*!
AnnaBridge 143:86740a56073b 5044 * @}
AnnaBridge 143:86740a56073b 5045 */ /* end of group FMC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 5046
AnnaBridge 143:86740a56073b 5047
AnnaBridge 143:86740a56073b 5048 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 5049 -- FTFE Peripheral Access Layer
AnnaBridge 143:86740a56073b 5050 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 5051
AnnaBridge 143:86740a56073b 5052 /*!
AnnaBridge 143:86740a56073b 5053 * @addtogroup FTFE_Peripheral_Access_Layer FTFE Peripheral Access Layer
AnnaBridge 143:86740a56073b 5054 * @{
AnnaBridge 143:86740a56073b 5055 */
AnnaBridge 143:86740a56073b 5056
AnnaBridge 143:86740a56073b 5057 /** FTFE - Register Layout Typedef */
AnnaBridge 143:86740a56073b 5058 typedef struct {
AnnaBridge 143:86740a56073b 5059 __IO uint8_t FSTAT; /**< Flash Status Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 5060 __IO uint8_t FCNFG; /**< Flash Configuration Register, offset: 0x1 */
AnnaBridge 143:86740a56073b 5061 __I uint8_t FSEC; /**< Flash Security Register, offset: 0x2 */
AnnaBridge 143:86740a56073b 5062 __I uint8_t FOPT; /**< Flash Option Register, offset: 0x3 */
AnnaBridge 143:86740a56073b 5063 __IO uint8_t FCCOB3; /**< Flash Common Command Object Registers, offset: 0x4 */
AnnaBridge 143:86740a56073b 5064 __IO uint8_t FCCOB2; /**< Flash Common Command Object Registers, offset: 0x5 */
AnnaBridge 143:86740a56073b 5065 __IO uint8_t FCCOB1; /**< Flash Common Command Object Registers, offset: 0x6 */
AnnaBridge 143:86740a56073b 5066 __IO uint8_t FCCOB0; /**< Flash Common Command Object Registers, offset: 0x7 */
AnnaBridge 143:86740a56073b 5067 __IO uint8_t FCCOB7; /**< Flash Common Command Object Registers, offset: 0x8 */
AnnaBridge 143:86740a56073b 5068 __IO uint8_t FCCOB6; /**< Flash Common Command Object Registers, offset: 0x9 */
AnnaBridge 143:86740a56073b 5069 __IO uint8_t FCCOB5; /**< Flash Common Command Object Registers, offset: 0xA */
AnnaBridge 143:86740a56073b 5070 __IO uint8_t FCCOB4; /**< Flash Common Command Object Registers, offset: 0xB */
AnnaBridge 143:86740a56073b 5071 __IO uint8_t FCCOBB; /**< Flash Common Command Object Registers, offset: 0xC */
AnnaBridge 143:86740a56073b 5072 __IO uint8_t FCCOBA; /**< Flash Common Command Object Registers, offset: 0xD */
AnnaBridge 143:86740a56073b 5073 __IO uint8_t FCCOB9; /**< Flash Common Command Object Registers, offset: 0xE */
AnnaBridge 143:86740a56073b 5074 __IO uint8_t FCCOB8; /**< Flash Common Command Object Registers, offset: 0xF */
AnnaBridge 143:86740a56073b 5075 __IO uint8_t FPROT3; /**< Program Flash Protection Registers, offset: 0x10 */
AnnaBridge 143:86740a56073b 5076 __IO uint8_t FPROT2; /**< Program Flash Protection Registers, offset: 0x11 */
AnnaBridge 143:86740a56073b 5077 __IO uint8_t FPROT1; /**< Program Flash Protection Registers, offset: 0x12 */
AnnaBridge 143:86740a56073b 5078 __IO uint8_t FPROT0; /**< Program Flash Protection Registers, offset: 0x13 */
AnnaBridge 143:86740a56073b 5079 } FTFE_Type;
AnnaBridge 143:86740a56073b 5080
AnnaBridge 143:86740a56073b 5081 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 5082 -- FTFE Register Masks
AnnaBridge 143:86740a56073b 5083 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 5084
AnnaBridge 143:86740a56073b 5085 /*!
AnnaBridge 143:86740a56073b 5086 * @addtogroup FTFE_Register_Masks FTFE Register Masks
AnnaBridge 143:86740a56073b 5087 * @{
AnnaBridge 143:86740a56073b 5088 */
AnnaBridge 143:86740a56073b 5089
AnnaBridge 143:86740a56073b 5090 /*! @name FSTAT - Flash Status Register */
AnnaBridge 143:86740a56073b 5091 #define FTFE_FSTAT_MGSTAT0_MASK (0x1U)
AnnaBridge 143:86740a56073b 5092 #define FTFE_FSTAT_MGSTAT0_SHIFT (0U)
AnnaBridge 143:86740a56073b 5093 #define FTFE_FSTAT_MGSTAT0(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_MGSTAT0_SHIFT)) & FTFE_FSTAT_MGSTAT0_MASK)
AnnaBridge 143:86740a56073b 5094 #define FTFE_FSTAT_FPVIOL_MASK (0x10U)
AnnaBridge 143:86740a56073b 5095 #define FTFE_FSTAT_FPVIOL_SHIFT (4U)
AnnaBridge 143:86740a56073b 5096 #define FTFE_FSTAT_FPVIOL(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_FPVIOL_SHIFT)) & FTFE_FSTAT_FPVIOL_MASK)
AnnaBridge 143:86740a56073b 5097 #define FTFE_FSTAT_ACCERR_MASK (0x20U)
AnnaBridge 143:86740a56073b 5098 #define FTFE_FSTAT_ACCERR_SHIFT (5U)
AnnaBridge 143:86740a56073b 5099 #define FTFE_FSTAT_ACCERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_ACCERR_SHIFT)) & FTFE_FSTAT_ACCERR_MASK)
AnnaBridge 143:86740a56073b 5100 #define FTFE_FSTAT_RDCOLERR_MASK (0x40U)
AnnaBridge 143:86740a56073b 5101 #define FTFE_FSTAT_RDCOLERR_SHIFT (6U)
AnnaBridge 143:86740a56073b 5102 #define FTFE_FSTAT_RDCOLERR(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_RDCOLERR_SHIFT)) & FTFE_FSTAT_RDCOLERR_MASK)
AnnaBridge 143:86740a56073b 5103 #define FTFE_FSTAT_CCIF_MASK (0x80U)
AnnaBridge 143:86740a56073b 5104 #define FTFE_FSTAT_CCIF_SHIFT (7U)
AnnaBridge 143:86740a56073b 5105 #define FTFE_FSTAT_CCIF(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSTAT_CCIF_SHIFT)) & FTFE_FSTAT_CCIF_MASK)
AnnaBridge 143:86740a56073b 5106
AnnaBridge 143:86740a56073b 5107 /*! @name FCNFG - Flash Configuration Register */
AnnaBridge 143:86740a56073b 5108 #define FTFE_FCNFG_EEERDY_MASK (0x1U)
AnnaBridge 143:86740a56073b 5109 #define FTFE_FCNFG_EEERDY_SHIFT (0U)
AnnaBridge 143:86740a56073b 5110 #define FTFE_FCNFG_EEERDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_EEERDY_SHIFT)) & FTFE_FCNFG_EEERDY_MASK)
AnnaBridge 143:86740a56073b 5111 #define FTFE_FCNFG_RAMRDY_MASK (0x2U)
AnnaBridge 143:86740a56073b 5112 #define FTFE_FCNFG_RAMRDY_SHIFT (1U)
AnnaBridge 143:86740a56073b 5113 #define FTFE_FCNFG_RAMRDY(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RAMRDY_SHIFT)) & FTFE_FCNFG_RAMRDY_MASK)
AnnaBridge 143:86740a56073b 5114 #define FTFE_FCNFG_PFLSH_MASK (0x4U)
AnnaBridge 143:86740a56073b 5115 #define FTFE_FCNFG_PFLSH_SHIFT (2U)
AnnaBridge 143:86740a56073b 5116 #define FTFE_FCNFG_PFLSH(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_PFLSH_SHIFT)) & FTFE_FCNFG_PFLSH_MASK)
AnnaBridge 143:86740a56073b 5117 #define FTFE_FCNFG_SWAP_MASK (0x8U)
AnnaBridge 143:86740a56073b 5118 #define FTFE_FCNFG_SWAP_SHIFT (3U)
AnnaBridge 143:86740a56073b 5119 #define FTFE_FCNFG_SWAP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_SWAP_SHIFT)) & FTFE_FCNFG_SWAP_MASK)
AnnaBridge 143:86740a56073b 5120 #define FTFE_FCNFG_ERSSUSP_MASK (0x10U)
AnnaBridge 143:86740a56073b 5121 #define FTFE_FCNFG_ERSSUSP_SHIFT (4U)
AnnaBridge 143:86740a56073b 5122 #define FTFE_FCNFG_ERSSUSP(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSSUSP_SHIFT)) & FTFE_FCNFG_ERSSUSP_MASK)
AnnaBridge 143:86740a56073b 5123 #define FTFE_FCNFG_ERSAREQ_MASK (0x20U)
AnnaBridge 143:86740a56073b 5124 #define FTFE_FCNFG_ERSAREQ_SHIFT (5U)
AnnaBridge 143:86740a56073b 5125 #define FTFE_FCNFG_ERSAREQ(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_ERSAREQ_SHIFT)) & FTFE_FCNFG_ERSAREQ_MASK)
AnnaBridge 143:86740a56073b 5126 #define FTFE_FCNFG_RDCOLLIE_MASK (0x40U)
AnnaBridge 143:86740a56073b 5127 #define FTFE_FCNFG_RDCOLLIE_SHIFT (6U)
AnnaBridge 143:86740a56073b 5128 #define FTFE_FCNFG_RDCOLLIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_RDCOLLIE_SHIFT)) & FTFE_FCNFG_RDCOLLIE_MASK)
AnnaBridge 143:86740a56073b 5129 #define FTFE_FCNFG_CCIE_MASK (0x80U)
AnnaBridge 143:86740a56073b 5130 #define FTFE_FCNFG_CCIE_SHIFT (7U)
AnnaBridge 143:86740a56073b 5131 #define FTFE_FCNFG_CCIE(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCNFG_CCIE_SHIFT)) & FTFE_FCNFG_CCIE_MASK)
AnnaBridge 143:86740a56073b 5132
AnnaBridge 143:86740a56073b 5133 /*! @name FSEC - Flash Security Register */
AnnaBridge 143:86740a56073b 5134 #define FTFE_FSEC_SEC_MASK (0x3U)
AnnaBridge 143:86740a56073b 5135 #define FTFE_FSEC_SEC_SHIFT (0U)
AnnaBridge 143:86740a56073b 5136 #define FTFE_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_SEC_SHIFT)) & FTFE_FSEC_SEC_MASK)
AnnaBridge 143:86740a56073b 5137 #define FTFE_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 143:86740a56073b 5138 #define FTFE_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 143:86740a56073b 5139 #define FTFE_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_FSLACC_SHIFT)) & FTFE_FSEC_FSLACC_MASK)
AnnaBridge 143:86740a56073b 5140 #define FTFE_FSEC_MEEN_MASK (0x30U)
AnnaBridge 143:86740a56073b 5141 #define FTFE_FSEC_MEEN_SHIFT (4U)
AnnaBridge 143:86740a56073b 5142 #define FTFE_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_MEEN_SHIFT)) & FTFE_FSEC_MEEN_MASK)
AnnaBridge 143:86740a56073b 5143 #define FTFE_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 143:86740a56073b 5144 #define FTFE_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 5145 #define FTFE_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FSEC_KEYEN_SHIFT)) & FTFE_FSEC_KEYEN_MASK)
AnnaBridge 143:86740a56073b 5146
AnnaBridge 143:86740a56073b 5147 /*! @name FOPT - Flash Option Register */
AnnaBridge 143:86740a56073b 5148 #define FTFE_FOPT_OPT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5149 #define FTFE_FOPT_OPT_SHIFT (0U)
AnnaBridge 143:86740a56073b 5150 #define FTFE_FOPT_OPT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FOPT_OPT_SHIFT)) & FTFE_FOPT_OPT_MASK)
AnnaBridge 143:86740a56073b 5151
AnnaBridge 143:86740a56073b 5152 /*! @name FCCOB3 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5153 #define FTFE_FCCOB3_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5154 #define FTFE_FCCOB3_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5155 #define FTFE_FCCOB3_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB3_CCOBn_SHIFT)) & FTFE_FCCOB3_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5156
AnnaBridge 143:86740a56073b 5157 /*! @name FCCOB2 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5158 #define FTFE_FCCOB2_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5159 #define FTFE_FCCOB2_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5160 #define FTFE_FCCOB2_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB2_CCOBn_SHIFT)) & FTFE_FCCOB2_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5161
AnnaBridge 143:86740a56073b 5162 /*! @name FCCOB1 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5163 #define FTFE_FCCOB1_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5164 #define FTFE_FCCOB1_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5165 #define FTFE_FCCOB1_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB1_CCOBn_SHIFT)) & FTFE_FCCOB1_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5166
AnnaBridge 143:86740a56073b 5167 /*! @name FCCOB0 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5168 #define FTFE_FCCOB0_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5169 #define FTFE_FCCOB0_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5170 #define FTFE_FCCOB0_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB0_CCOBn_SHIFT)) & FTFE_FCCOB0_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5171
AnnaBridge 143:86740a56073b 5172 /*! @name FCCOB7 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5173 #define FTFE_FCCOB7_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5174 #define FTFE_FCCOB7_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5175 #define FTFE_FCCOB7_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB7_CCOBn_SHIFT)) & FTFE_FCCOB7_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5176
AnnaBridge 143:86740a56073b 5177 /*! @name FCCOB6 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5178 #define FTFE_FCCOB6_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5179 #define FTFE_FCCOB6_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5180 #define FTFE_FCCOB6_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB6_CCOBn_SHIFT)) & FTFE_FCCOB6_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5181
AnnaBridge 143:86740a56073b 5182 /*! @name FCCOB5 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5183 #define FTFE_FCCOB5_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5184 #define FTFE_FCCOB5_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5185 #define FTFE_FCCOB5_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB5_CCOBn_SHIFT)) & FTFE_FCCOB5_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5186
AnnaBridge 143:86740a56073b 5187 /*! @name FCCOB4 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5188 #define FTFE_FCCOB4_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5189 #define FTFE_FCCOB4_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5190 #define FTFE_FCCOB4_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB4_CCOBn_SHIFT)) & FTFE_FCCOB4_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5191
AnnaBridge 143:86740a56073b 5192 /*! @name FCCOBB - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5193 #define FTFE_FCCOBB_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5194 #define FTFE_FCCOBB_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5195 #define FTFE_FCCOBB_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBB_CCOBn_SHIFT)) & FTFE_FCCOBB_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5196
AnnaBridge 143:86740a56073b 5197 /*! @name FCCOBA - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5198 #define FTFE_FCCOBA_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5199 #define FTFE_FCCOBA_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5200 #define FTFE_FCCOBA_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOBA_CCOBn_SHIFT)) & FTFE_FCCOBA_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5201
AnnaBridge 143:86740a56073b 5202 /*! @name FCCOB9 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5203 #define FTFE_FCCOB9_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5204 #define FTFE_FCCOB9_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5205 #define FTFE_FCCOB9_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB9_CCOBn_SHIFT)) & FTFE_FCCOB9_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5206
AnnaBridge 143:86740a56073b 5207 /*! @name FCCOB8 - Flash Common Command Object Registers */
AnnaBridge 143:86740a56073b 5208 #define FTFE_FCCOB8_CCOBn_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5209 #define FTFE_FCCOB8_CCOBn_SHIFT (0U)
AnnaBridge 143:86740a56073b 5210 #define FTFE_FCCOB8_CCOBn(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FCCOB8_CCOBn_SHIFT)) & FTFE_FCCOB8_CCOBn_MASK)
AnnaBridge 143:86740a56073b 5211
AnnaBridge 143:86740a56073b 5212 /*! @name FPROT3 - Program Flash Protection Registers */
AnnaBridge 143:86740a56073b 5213 #define FTFE_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5214 #define FTFE_FPROT3_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 5215 #define FTFE_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT3_PROT_SHIFT)) & FTFE_FPROT3_PROT_MASK)
AnnaBridge 143:86740a56073b 5216
AnnaBridge 143:86740a56073b 5217 /*! @name FPROT2 - Program Flash Protection Registers */
AnnaBridge 143:86740a56073b 5218 #define FTFE_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5219 #define FTFE_FPROT2_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 5220 #define FTFE_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT2_PROT_SHIFT)) & FTFE_FPROT2_PROT_MASK)
AnnaBridge 143:86740a56073b 5221
AnnaBridge 143:86740a56073b 5222 /*! @name FPROT1 - Program Flash Protection Registers */
AnnaBridge 143:86740a56073b 5223 #define FTFE_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5224 #define FTFE_FPROT1_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 5225 #define FTFE_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT1_PROT_SHIFT)) & FTFE_FPROT1_PROT_MASK)
AnnaBridge 143:86740a56073b 5226
AnnaBridge 143:86740a56073b 5227 /*! @name FPROT0 - Program Flash Protection Registers */
AnnaBridge 143:86740a56073b 5228 #define FTFE_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 5229 #define FTFE_FPROT0_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 5230 #define FTFE_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << FTFE_FPROT0_PROT_SHIFT)) & FTFE_FPROT0_PROT_MASK)
AnnaBridge 143:86740a56073b 5231
AnnaBridge 143:86740a56073b 5232
AnnaBridge 143:86740a56073b 5233 /*!
AnnaBridge 143:86740a56073b 5234 * @}
AnnaBridge 143:86740a56073b 5235 */ /* end of group FTFE_Register_Masks */
AnnaBridge 143:86740a56073b 5236
AnnaBridge 143:86740a56073b 5237
AnnaBridge 143:86740a56073b 5238 /* FTFE - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 5239 /** Peripheral FTFE base address */
AnnaBridge 143:86740a56073b 5240 #define FTFE_BASE (0x40020000u)
AnnaBridge 143:86740a56073b 5241 /** Peripheral FTFE base pointer */
AnnaBridge 143:86740a56073b 5242 #define FTFE ((FTFE_Type *)FTFE_BASE)
AnnaBridge 143:86740a56073b 5243 /** Array initializer of FTFE peripheral base addresses */
AnnaBridge 143:86740a56073b 5244 #define FTFE_BASE_ADDRS { FTFE_BASE }
AnnaBridge 143:86740a56073b 5245 /** Array initializer of FTFE peripheral base pointers */
AnnaBridge 143:86740a56073b 5246 #define FTFE_BASE_PTRS { FTFE }
AnnaBridge 143:86740a56073b 5247 /** Interrupt vectors for the FTFE peripheral type */
AnnaBridge 143:86740a56073b 5248 #define FTFE_COMMAND_COMPLETE_IRQS { FTFE_IRQn }
AnnaBridge 143:86740a56073b 5249 #define FTFE_READ_COLLISION_IRQS { Read_Collision_IRQn }
AnnaBridge 143:86740a56073b 5250
AnnaBridge 143:86740a56073b 5251 /*!
AnnaBridge 143:86740a56073b 5252 * @}
AnnaBridge 143:86740a56073b 5253 */ /* end of group FTFE_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 5254
AnnaBridge 143:86740a56073b 5255
AnnaBridge 143:86740a56073b 5256 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 5257 -- FTM Peripheral Access Layer
AnnaBridge 143:86740a56073b 5258 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 5259
AnnaBridge 143:86740a56073b 5260 /*!
AnnaBridge 143:86740a56073b 5261 * @addtogroup FTM_Peripheral_Access_Layer FTM Peripheral Access Layer
AnnaBridge 143:86740a56073b 5262 * @{
AnnaBridge 143:86740a56073b 5263 */
AnnaBridge 143:86740a56073b 5264
AnnaBridge 143:86740a56073b 5265 /** FTM - Register Layout Typedef */
AnnaBridge 143:86740a56073b 5266 typedef struct {
AnnaBridge 143:86740a56073b 5267 __IO uint32_t SC; /**< Status And Control, offset: 0x0 */
AnnaBridge 143:86740a56073b 5268 __IO uint32_t CNT; /**< Counter, offset: 0x4 */
AnnaBridge 143:86740a56073b 5269 __IO uint32_t MOD; /**< Modulo, offset: 0x8 */
AnnaBridge 143:86740a56073b 5270 struct { /* offset: 0xC, array step: 0x8 */
AnnaBridge 143:86740a56073b 5271 __IO uint32_t CnSC; /**< Channel (n) Status And Control, array offset: 0xC, array step: 0x8 */
AnnaBridge 143:86740a56073b 5272 __IO uint32_t CnV; /**< Channel (n) Value, array offset: 0x10, array step: 0x8 */
AnnaBridge 143:86740a56073b 5273 } CONTROLS[8];
AnnaBridge 143:86740a56073b 5274 __IO uint32_t CNTIN; /**< Counter Initial Value, offset: 0x4C */
AnnaBridge 143:86740a56073b 5275 __IO uint32_t STATUS; /**< Capture And Compare Status, offset: 0x50 */
AnnaBridge 143:86740a56073b 5276 __IO uint32_t MODE; /**< Features Mode Selection, offset: 0x54 */
AnnaBridge 143:86740a56073b 5277 __IO uint32_t SYNC; /**< Synchronization, offset: 0x58 */
AnnaBridge 143:86740a56073b 5278 __IO uint32_t OUTINIT; /**< Initial State For Channels Output, offset: 0x5C */
AnnaBridge 143:86740a56073b 5279 __IO uint32_t OUTMASK; /**< Output Mask, offset: 0x60 */
AnnaBridge 143:86740a56073b 5280 __IO uint32_t COMBINE; /**< Function For Linked Channels, offset: 0x64 */
AnnaBridge 143:86740a56073b 5281 __IO uint32_t DEADTIME; /**< Deadtime Insertion Control, offset: 0x68 */
AnnaBridge 143:86740a56073b 5282 __IO uint32_t EXTTRIG; /**< FTM External Trigger, offset: 0x6C */
AnnaBridge 143:86740a56073b 5283 __IO uint32_t POL; /**< Channels Polarity, offset: 0x70 */
AnnaBridge 143:86740a56073b 5284 __IO uint32_t FMS; /**< Fault Mode Status, offset: 0x74 */
AnnaBridge 143:86740a56073b 5285 __IO uint32_t FILTER; /**< Input Capture Filter Control, offset: 0x78 */
AnnaBridge 143:86740a56073b 5286 __IO uint32_t FLTCTRL; /**< Fault Control, offset: 0x7C */
AnnaBridge 143:86740a56073b 5287 __IO uint32_t QDCTRL; /**< Quadrature Decoder Control And Status, offset: 0x80 */
AnnaBridge 143:86740a56073b 5288 __IO uint32_t CONF; /**< Configuration, offset: 0x84 */
AnnaBridge 143:86740a56073b 5289 __IO uint32_t FLTPOL; /**< FTM Fault Input Polarity, offset: 0x88 */
AnnaBridge 143:86740a56073b 5290 __IO uint32_t SYNCONF; /**< Synchronization Configuration, offset: 0x8C */
AnnaBridge 143:86740a56073b 5291 __IO uint32_t INVCTRL; /**< FTM Inverting Control, offset: 0x90 */
AnnaBridge 143:86740a56073b 5292 __IO uint32_t SWOCTRL; /**< FTM Software Output Control, offset: 0x94 */
AnnaBridge 143:86740a56073b 5293 __IO uint32_t PWMLOAD; /**< FTM PWM Load, offset: 0x98 */
AnnaBridge 143:86740a56073b 5294 } FTM_Type;
AnnaBridge 143:86740a56073b 5295
AnnaBridge 143:86740a56073b 5296 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 5297 -- FTM Register Masks
AnnaBridge 143:86740a56073b 5298 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 5299
AnnaBridge 143:86740a56073b 5300 /*!
AnnaBridge 143:86740a56073b 5301 * @addtogroup FTM_Register_Masks FTM Register Masks
AnnaBridge 143:86740a56073b 5302 * @{
AnnaBridge 143:86740a56073b 5303 */
AnnaBridge 143:86740a56073b 5304
AnnaBridge 143:86740a56073b 5305 /*! @name SC - Status And Control */
AnnaBridge 143:86740a56073b 5306 #define FTM_SC_PS_MASK (0x7U)
AnnaBridge 143:86740a56073b 5307 #define FTM_SC_PS_SHIFT (0U)
AnnaBridge 143:86740a56073b 5308 #define FTM_SC_PS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_PS_SHIFT)) & FTM_SC_PS_MASK)
AnnaBridge 143:86740a56073b 5309 #define FTM_SC_CLKS_MASK (0x18U)
AnnaBridge 143:86740a56073b 5310 #define FTM_SC_CLKS_SHIFT (3U)
AnnaBridge 143:86740a56073b 5311 #define FTM_SC_CLKS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CLKS_SHIFT)) & FTM_SC_CLKS_MASK)
AnnaBridge 143:86740a56073b 5312 #define FTM_SC_CPWMS_MASK (0x20U)
AnnaBridge 143:86740a56073b 5313 #define FTM_SC_CPWMS_SHIFT (5U)
AnnaBridge 143:86740a56073b 5314 #define FTM_SC_CPWMS(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_CPWMS_SHIFT)) & FTM_SC_CPWMS_MASK)
AnnaBridge 143:86740a56073b 5315 #define FTM_SC_TOIE_MASK (0x40U)
AnnaBridge 143:86740a56073b 5316 #define FTM_SC_TOIE_SHIFT (6U)
AnnaBridge 143:86740a56073b 5317 #define FTM_SC_TOIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOIE_SHIFT)) & FTM_SC_TOIE_MASK)
AnnaBridge 143:86740a56073b 5318 #define FTM_SC_TOF_MASK (0x80U)
AnnaBridge 143:86740a56073b 5319 #define FTM_SC_TOF_SHIFT (7U)
AnnaBridge 143:86740a56073b 5320 #define FTM_SC_TOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SC_TOF_SHIFT)) & FTM_SC_TOF_MASK)
AnnaBridge 143:86740a56073b 5321
AnnaBridge 143:86740a56073b 5322 /*! @name CNT - Counter */
AnnaBridge 143:86740a56073b 5323 #define FTM_CNT_COUNT_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 5324 #define FTM_CNT_COUNT_SHIFT (0U)
AnnaBridge 143:86740a56073b 5325 #define FTM_CNT_COUNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNT_COUNT_SHIFT)) & FTM_CNT_COUNT_MASK)
AnnaBridge 143:86740a56073b 5326
AnnaBridge 143:86740a56073b 5327 /*! @name MOD - Modulo */
AnnaBridge 143:86740a56073b 5328 #define FTM_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 5329 #define FTM_MOD_MOD_SHIFT (0U)
AnnaBridge 143:86740a56073b 5330 #define FTM_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << FTM_MOD_MOD_SHIFT)) & FTM_MOD_MOD_MASK)
AnnaBridge 143:86740a56073b 5331
AnnaBridge 143:86740a56073b 5332 /*! @name CnSC - Channel (n) Status And Control */
AnnaBridge 143:86740a56073b 5333 #define FTM_CnSC_DMA_MASK (0x1U)
AnnaBridge 143:86740a56073b 5334 #define FTM_CnSC_DMA_SHIFT (0U)
AnnaBridge 143:86740a56073b 5335 #define FTM_CnSC_DMA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_DMA_SHIFT)) & FTM_CnSC_DMA_MASK)
AnnaBridge 143:86740a56073b 5336 #define FTM_CnSC_ELSA_MASK (0x4U)
AnnaBridge 143:86740a56073b 5337 #define FTM_CnSC_ELSA_SHIFT (2U)
AnnaBridge 143:86740a56073b 5338 #define FTM_CnSC_ELSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSA_SHIFT)) & FTM_CnSC_ELSA_MASK)
AnnaBridge 143:86740a56073b 5339 #define FTM_CnSC_ELSB_MASK (0x8U)
AnnaBridge 143:86740a56073b 5340 #define FTM_CnSC_ELSB_SHIFT (3U)
AnnaBridge 143:86740a56073b 5341 #define FTM_CnSC_ELSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_ELSB_SHIFT)) & FTM_CnSC_ELSB_MASK)
AnnaBridge 143:86740a56073b 5342 #define FTM_CnSC_MSA_MASK (0x10U)
AnnaBridge 143:86740a56073b 5343 #define FTM_CnSC_MSA_SHIFT (4U)
AnnaBridge 143:86740a56073b 5344 #define FTM_CnSC_MSA(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSA_SHIFT)) & FTM_CnSC_MSA_MASK)
AnnaBridge 143:86740a56073b 5345 #define FTM_CnSC_MSB_MASK (0x20U)
AnnaBridge 143:86740a56073b 5346 #define FTM_CnSC_MSB_SHIFT (5U)
AnnaBridge 143:86740a56073b 5347 #define FTM_CnSC_MSB(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_MSB_SHIFT)) & FTM_CnSC_MSB_MASK)
AnnaBridge 143:86740a56073b 5348 #define FTM_CnSC_CHIE_MASK (0x40U)
AnnaBridge 143:86740a56073b 5349 #define FTM_CnSC_CHIE_SHIFT (6U)
AnnaBridge 143:86740a56073b 5350 #define FTM_CnSC_CHIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHIE_SHIFT)) & FTM_CnSC_CHIE_MASK)
AnnaBridge 143:86740a56073b 5351 #define FTM_CnSC_CHF_MASK (0x80U)
AnnaBridge 143:86740a56073b 5352 #define FTM_CnSC_CHF_SHIFT (7U)
AnnaBridge 143:86740a56073b 5353 #define FTM_CnSC_CHF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnSC_CHF_SHIFT)) & FTM_CnSC_CHF_MASK)
AnnaBridge 143:86740a56073b 5354
AnnaBridge 143:86740a56073b 5355 /* The count of FTM_CnSC */
AnnaBridge 143:86740a56073b 5356 #define FTM_CnSC_COUNT (8U)
AnnaBridge 143:86740a56073b 5357
AnnaBridge 143:86740a56073b 5358 /*! @name CnV - Channel (n) Value */
AnnaBridge 143:86740a56073b 5359 #define FTM_CnV_VAL_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 5360 #define FTM_CnV_VAL_SHIFT (0U)
AnnaBridge 143:86740a56073b 5361 #define FTM_CnV_VAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_CnV_VAL_SHIFT)) & FTM_CnV_VAL_MASK)
AnnaBridge 143:86740a56073b 5362
AnnaBridge 143:86740a56073b 5363 /* The count of FTM_CnV */
AnnaBridge 143:86740a56073b 5364 #define FTM_CnV_COUNT (8U)
AnnaBridge 143:86740a56073b 5365
AnnaBridge 143:86740a56073b 5366 /*! @name CNTIN - Counter Initial Value */
AnnaBridge 143:86740a56073b 5367 #define FTM_CNTIN_INIT_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 5368 #define FTM_CNTIN_INIT_SHIFT (0U)
AnnaBridge 143:86740a56073b 5369 #define FTM_CNTIN_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CNTIN_INIT_SHIFT)) & FTM_CNTIN_INIT_MASK)
AnnaBridge 143:86740a56073b 5370
AnnaBridge 143:86740a56073b 5371 /*! @name STATUS - Capture And Compare Status */
AnnaBridge 143:86740a56073b 5372 #define FTM_STATUS_CH0F_MASK (0x1U)
AnnaBridge 143:86740a56073b 5373 #define FTM_STATUS_CH0F_SHIFT (0U)
AnnaBridge 143:86740a56073b 5374 #define FTM_STATUS_CH0F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH0F_SHIFT)) & FTM_STATUS_CH0F_MASK)
AnnaBridge 143:86740a56073b 5375 #define FTM_STATUS_CH1F_MASK (0x2U)
AnnaBridge 143:86740a56073b 5376 #define FTM_STATUS_CH1F_SHIFT (1U)
AnnaBridge 143:86740a56073b 5377 #define FTM_STATUS_CH1F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH1F_SHIFT)) & FTM_STATUS_CH1F_MASK)
AnnaBridge 143:86740a56073b 5378 #define FTM_STATUS_CH2F_MASK (0x4U)
AnnaBridge 143:86740a56073b 5379 #define FTM_STATUS_CH2F_SHIFT (2U)
AnnaBridge 143:86740a56073b 5380 #define FTM_STATUS_CH2F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH2F_SHIFT)) & FTM_STATUS_CH2F_MASK)
AnnaBridge 143:86740a56073b 5381 #define FTM_STATUS_CH3F_MASK (0x8U)
AnnaBridge 143:86740a56073b 5382 #define FTM_STATUS_CH3F_SHIFT (3U)
AnnaBridge 143:86740a56073b 5383 #define FTM_STATUS_CH3F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH3F_SHIFT)) & FTM_STATUS_CH3F_MASK)
AnnaBridge 143:86740a56073b 5384 #define FTM_STATUS_CH4F_MASK (0x10U)
AnnaBridge 143:86740a56073b 5385 #define FTM_STATUS_CH4F_SHIFT (4U)
AnnaBridge 143:86740a56073b 5386 #define FTM_STATUS_CH4F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH4F_SHIFT)) & FTM_STATUS_CH4F_MASK)
AnnaBridge 143:86740a56073b 5387 #define FTM_STATUS_CH5F_MASK (0x20U)
AnnaBridge 143:86740a56073b 5388 #define FTM_STATUS_CH5F_SHIFT (5U)
AnnaBridge 143:86740a56073b 5389 #define FTM_STATUS_CH5F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH5F_SHIFT)) & FTM_STATUS_CH5F_MASK)
AnnaBridge 143:86740a56073b 5390 #define FTM_STATUS_CH6F_MASK (0x40U)
AnnaBridge 143:86740a56073b 5391 #define FTM_STATUS_CH6F_SHIFT (6U)
AnnaBridge 143:86740a56073b 5392 #define FTM_STATUS_CH6F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH6F_SHIFT)) & FTM_STATUS_CH6F_MASK)
AnnaBridge 143:86740a56073b 5393 #define FTM_STATUS_CH7F_MASK (0x80U)
AnnaBridge 143:86740a56073b 5394 #define FTM_STATUS_CH7F_SHIFT (7U)
AnnaBridge 143:86740a56073b 5395 #define FTM_STATUS_CH7F(x) (((uint32_t)(((uint32_t)(x)) << FTM_STATUS_CH7F_SHIFT)) & FTM_STATUS_CH7F_MASK)
AnnaBridge 143:86740a56073b 5396
AnnaBridge 143:86740a56073b 5397 /*! @name MODE - Features Mode Selection */
AnnaBridge 143:86740a56073b 5398 #define FTM_MODE_FTMEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 5399 #define FTM_MODE_FTMEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 5400 #define FTM_MODE_FTMEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FTMEN_SHIFT)) & FTM_MODE_FTMEN_MASK)
AnnaBridge 143:86740a56073b 5401 #define FTM_MODE_INIT_MASK (0x2U)
AnnaBridge 143:86740a56073b 5402 #define FTM_MODE_INIT_SHIFT (1U)
AnnaBridge 143:86740a56073b 5403 #define FTM_MODE_INIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_INIT_SHIFT)) & FTM_MODE_INIT_MASK)
AnnaBridge 143:86740a56073b 5404 #define FTM_MODE_WPDIS_MASK (0x4U)
AnnaBridge 143:86740a56073b 5405 #define FTM_MODE_WPDIS_SHIFT (2U)
AnnaBridge 143:86740a56073b 5406 #define FTM_MODE_WPDIS(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_WPDIS_SHIFT)) & FTM_MODE_WPDIS_MASK)
AnnaBridge 143:86740a56073b 5407 #define FTM_MODE_PWMSYNC_MASK (0x8U)
AnnaBridge 143:86740a56073b 5408 #define FTM_MODE_PWMSYNC_SHIFT (3U)
AnnaBridge 143:86740a56073b 5409 #define FTM_MODE_PWMSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_PWMSYNC_SHIFT)) & FTM_MODE_PWMSYNC_MASK)
AnnaBridge 143:86740a56073b 5410 #define FTM_MODE_CAPTEST_MASK (0x10U)
AnnaBridge 143:86740a56073b 5411 #define FTM_MODE_CAPTEST_SHIFT (4U)
AnnaBridge 143:86740a56073b 5412 #define FTM_MODE_CAPTEST(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_CAPTEST_SHIFT)) & FTM_MODE_CAPTEST_MASK)
AnnaBridge 143:86740a56073b 5413 #define FTM_MODE_FAULTM_MASK (0x60U)
AnnaBridge 143:86740a56073b 5414 #define FTM_MODE_FAULTM_SHIFT (5U)
AnnaBridge 143:86740a56073b 5415 #define FTM_MODE_FAULTM(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTM_SHIFT)) & FTM_MODE_FAULTM_MASK)
AnnaBridge 143:86740a56073b 5416 #define FTM_MODE_FAULTIE_MASK (0x80U)
AnnaBridge 143:86740a56073b 5417 #define FTM_MODE_FAULTIE_SHIFT (7U)
AnnaBridge 143:86740a56073b 5418 #define FTM_MODE_FAULTIE(x) (((uint32_t)(((uint32_t)(x)) << FTM_MODE_FAULTIE_SHIFT)) & FTM_MODE_FAULTIE_MASK)
AnnaBridge 143:86740a56073b 5419
AnnaBridge 143:86740a56073b 5420 /*! @name SYNC - Synchronization */
AnnaBridge 143:86740a56073b 5421 #define FTM_SYNC_CNTMIN_MASK (0x1U)
AnnaBridge 143:86740a56073b 5422 #define FTM_SYNC_CNTMIN_SHIFT (0U)
AnnaBridge 143:86740a56073b 5423 #define FTM_SYNC_CNTMIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMIN_SHIFT)) & FTM_SYNC_CNTMIN_MASK)
AnnaBridge 143:86740a56073b 5424 #define FTM_SYNC_CNTMAX_MASK (0x2U)
AnnaBridge 143:86740a56073b 5425 #define FTM_SYNC_CNTMAX_SHIFT (1U)
AnnaBridge 143:86740a56073b 5426 #define FTM_SYNC_CNTMAX(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_CNTMAX_SHIFT)) & FTM_SYNC_CNTMAX_MASK)
AnnaBridge 143:86740a56073b 5427 #define FTM_SYNC_REINIT_MASK (0x4U)
AnnaBridge 143:86740a56073b 5428 #define FTM_SYNC_REINIT_SHIFT (2U)
AnnaBridge 143:86740a56073b 5429 #define FTM_SYNC_REINIT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_REINIT_SHIFT)) & FTM_SYNC_REINIT_MASK)
AnnaBridge 143:86740a56073b 5430 #define FTM_SYNC_SYNCHOM_MASK (0x8U)
AnnaBridge 143:86740a56073b 5431 #define FTM_SYNC_SYNCHOM_SHIFT (3U)
AnnaBridge 143:86740a56073b 5432 #define FTM_SYNC_SYNCHOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SYNCHOM_SHIFT)) & FTM_SYNC_SYNCHOM_MASK)
AnnaBridge 143:86740a56073b 5433 #define FTM_SYNC_TRIG0_MASK (0x10U)
AnnaBridge 143:86740a56073b 5434 #define FTM_SYNC_TRIG0_SHIFT (4U)
AnnaBridge 143:86740a56073b 5435 #define FTM_SYNC_TRIG0(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG0_SHIFT)) & FTM_SYNC_TRIG0_MASK)
AnnaBridge 143:86740a56073b 5436 #define FTM_SYNC_TRIG1_MASK (0x20U)
AnnaBridge 143:86740a56073b 5437 #define FTM_SYNC_TRIG1_SHIFT (5U)
AnnaBridge 143:86740a56073b 5438 #define FTM_SYNC_TRIG1(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG1_SHIFT)) & FTM_SYNC_TRIG1_MASK)
AnnaBridge 143:86740a56073b 5439 #define FTM_SYNC_TRIG2_MASK (0x40U)
AnnaBridge 143:86740a56073b 5440 #define FTM_SYNC_TRIG2_SHIFT (6U)
AnnaBridge 143:86740a56073b 5441 #define FTM_SYNC_TRIG2(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_TRIG2_SHIFT)) & FTM_SYNC_TRIG2_MASK)
AnnaBridge 143:86740a56073b 5442 #define FTM_SYNC_SWSYNC_MASK (0x80U)
AnnaBridge 143:86740a56073b 5443 #define FTM_SYNC_SWSYNC_SHIFT (7U)
AnnaBridge 143:86740a56073b 5444 #define FTM_SYNC_SWSYNC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNC_SWSYNC_SHIFT)) & FTM_SYNC_SWSYNC_MASK)
AnnaBridge 143:86740a56073b 5445
AnnaBridge 143:86740a56073b 5446 /*! @name OUTINIT - Initial State For Channels Output */
AnnaBridge 143:86740a56073b 5447 #define FTM_OUTINIT_CH0OI_MASK (0x1U)
AnnaBridge 143:86740a56073b 5448 #define FTM_OUTINIT_CH0OI_SHIFT (0U)
AnnaBridge 143:86740a56073b 5449 #define FTM_OUTINIT_CH0OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH0OI_SHIFT)) & FTM_OUTINIT_CH0OI_MASK)
AnnaBridge 143:86740a56073b 5450 #define FTM_OUTINIT_CH1OI_MASK (0x2U)
AnnaBridge 143:86740a56073b 5451 #define FTM_OUTINIT_CH1OI_SHIFT (1U)
AnnaBridge 143:86740a56073b 5452 #define FTM_OUTINIT_CH1OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH1OI_SHIFT)) & FTM_OUTINIT_CH1OI_MASK)
AnnaBridge 143:86740a56073b 5453 #define FTM_OUTINIT_CH2OI_MASK (0x4U)
AnnaBridge 143:86740a56073b 5454 #define FTM_OUTINIT_CH2OI_SHIFT (2U)
AnnaBridge 143:86740a56073b 5455 #define FTM_OUTINIT_CH2OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH2OI_SHIFT)) & FTM_OUTINIT_CH2OI_MASK)
AnnaBridge 143:86740a56073b 5456 #define FTM_OUTINIT_CH3OI_MASK (0x8U)
AnnaBridge 143:86740a56073b 5457 #define FTM_OUTINIT_CH3OI_SHIFT (3U)
AnnaBridge 143:86740a56073b 5458 #define FTM_OUTINIT_CH3OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH3OI_SHIFT)) & FTM_OUTINIT_CH3OI_MASK)
AnnaBridge 143:86740a56073b 5459 #define FTM_OUTINIT_CH4OI_MASK (0x10U)
AnnaBridge 143:86740a56073b 5460 #define FTM_OUTINIT_CH4OI_SHIFT (4U)
AnnaBridge 143:86740a56073b 5461 #define FTM_OUTINIT_CH4OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH4OI_SHIFT)) & FTM_OUTINIT_CH4OI_MASK)
AnnaBridge 143:86740a56073b 5462 #define FTM_OUTINIT_CH5OI_MASK (0x20U)
AnnaBridge 143:86740a56073b 5463 #define FTM_OUTINIT_CH5OI_SHIFT (5U)
AnnaBridge 143:86740a56073b 5464 #define FTM_OUTINIT_CH5OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH5OI_SHIFT)) & FTM_OUTINIT_CH5OI_MASK)
AnnaBridge 143:86740a56073b 5465 #define FTM_OUTINIT_CH6OI_MASK (0x40U)
AnnaBridge 143:86740a56073b 5466 #define FTM_OUTINIT_CH6OI_SHIFT (6U)
AnnaBridge 143:86740a56073b 5467 #define FTM_OUTINIT_CH6OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH6OI_SHIFT)) & FTM_OUTINIT_CH6OI_MASK)
AnnaBridge 143:86740a56073b 5468 #define FTM_OUTINIT_CH7OI_MASK (0x80U)
AnnaBridge 143:86740a56073b 5469 #define FTM_OUTINIT_CH7OI_SHIFT (7U)
AnnaBridge 143:86740a56073b 5470 #define FTM_OUTINIT_CH7OI(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTINIT_CH7OI_SHIFT)) & FTM_OUTINIT_CH7OI_MASK)
AnnaBridge 143:86740a56073b 5471
AnnaBridge 143:86740a56073b 5472 /*! @name OUTMASK - Output Mask */
AnnaBridge 143:86740a56073b 5473 #define FTM_OUTMASK_CH0OM_MASK (0x1U)
AnnaBridge 143:86740a56073b 5474 #define FTM_OUTMASK_CH0OM_SHIFT (0U)
AnnaBridge 143:86740a56073b 5475 #define FTM_OUTMASK_CH0OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH0OM_SHIFT)) & FTM_OUTMASK_CH0OM_MASK)
AnnaBridge 143:86740a56073b 5476 #define FTM_OUTMASK_CH1OM_MASK (0x2U)
AnnaBridge 143:86740a56073b 5477 #define FTM_OUTMASK_CH1OM_SHIFT (1U)
AnnaBridge 143:86740a56073b 5478 #define FTM_OUTMASK_CH1OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH1OM_SHIFT)) & FTM_OUTMASK_CH1OM_MASK)
AnnaBridge 143:86740a56073b 5479 #define FTM_OUTMASK_CH2OM_MASK (0x4U)
AnnaBridge 143:86740a56073b 5480 #define FTM_OUTMASK_CH2OM_SHIFT (2U)
AnnaBridge 143:86740a56073b 5481 #define FTM_OUTMASK_CH2OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH2OM_SHIFT)) & FTM_OUTMASK_CH2OM_MASK)
AnnaBridge 143:86740a56073b 5482 #define FTM_OUTMASK_CH3OM_MASK (0x8U)
AnnaBridge 143:86740a56073b 5483 #define FTM_OUTMASK_CH3OM_SHIFT (3U)
AnnaBridge 143:86740a56073b 5484 #define FTM_OUTMASK_CH3OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH3OM_SHIFT)) & FTM_OUTMASK_CH3OM_MASK)
AnnaBridge 143:86740a56073b 5485 #define FTM_OUTMASK_CH4OM_MASK (0x10U)
AnnaBridge 143:86740a56073b 5486 #define FTM_OUTMASK_CH4OM_SHIFT (4U)
AnnaBridge 143:86740a56073b 5487 #define FTM_OUTMASK_CH4OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH4OM_SHIFT)) & FTM_OUTMASK_CH4OM_MASK)
AnnaBridge 143:86740a56073b 5488 #define FTM_OUTMASK_CH5OM_MASK (0x20U)
AnnaBridge 143:86740a56073b 5489 #define FTM_OUTMASK_CH5OM_SHIFT (5U)
AnnaBridge 143:86740a56073b 5490 #define FTM_OUTMASK_CH5OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH5OM_SHIFT)) & FTM_OUTMASK_CH5OM_MASK)
AnnaBridge 143:86740a56073b 5491 #define FTM_OUTMASK_CH6OM_MASK (0x40U)
AnnaBridge 143:86740a56073b 5492 #define FTM_OUTMASK_CH6OM_SHIFT (6U)
AnnaBridge 143:86740a56073b 5493 #define FTM_OUTMASK_CH6OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH6OM_SHIFT)) & FTM_OUTMASK_CH6OM_MASK)
AnnaBridge 143:86740a56073b 5494 #define FTM_OUTMASK_CH7OM_MASK (0x80U)
AnnaBridge 143:86740a56073b 5495 #define FTM_OUTMASK_CH7OM_SHIFT (7U)
AnnaBridge 143:86740a56073b 5496 #define FTM_OUTMASK_CH7OM(x) (((uint32_t)(((uint32_t)(x)) << FTM_OUTMASK_CH7OM_SHIFT)) & FTM_OUTMASK_CH7OM_MASK)
AnnaBridge 143:86740a56073b 5497
AnnaBridge 143:86740a56073b 5498 /*! @name COMBINE - Function For Linked Channels */
AnnaBridge 143:86740a56073b 5499 #define FTM_COMBINE_COMBINE0_MASK (0x1U)
AnnaBridge 143:86740a56073b 5500 #define FTM_COMBINE_COMBINE0_SHIFT (0U)
AnnaBridge 143:86740a56073b 5501 #define FTM_COMBINE_COMBINE0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE0_SHIFT)) & FTM_COMBINE_COMBINE0_MASK)
AnnaBridge 143:86740a56073b 5502 #define FTM_COMBINE_COMP0_MASK (0x2U)
AnnaBridge 143:86740a56073b 5503 #define FTM_COMBINE_COMP0_SHIFT (1U)
AnnaBridge 143:86740a56073b 5504 #define FTM_COMBINE_COMP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP0_SHIFT)) & FTM_COMBINE_COMP0_MASK)
AnnaBridge 143:86740a56073b 5505 #define FTM_COMBINE_DECAPEN0_MASK (0x4U)
AnnaBridge 143:86740a56073b 5506 #define FTM_COMBINE_DECAPEN0_SHIFT (2U)
AnnaBridge 143:86740a56073b 5507 #define FTM_COMBINE_DECAPEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN0_SHIFT)) & FTM_COMBINE_DECAPEN0_MASK)
AnnaBridge 143:86740a56073b 5508 #define FTM_COMBINE_DECAP0_MASK (0x8U)
AnnaBridge 143:86740a56073b 5509 #define FTM_COMBINE_DECAP0_SHIFT (3U)
AnnaBridge 143:86740a56073b 5510 #define FTM_COMBINE_DECAP0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP0_SHIFT)) & FTM_COMBINE_DECAP0_MASK)
AnnaBridge 143:86740a56073b 5511 #define FTM_COMBINE_DTEN0_MASK (0x10U)
AnnaBridge 143:86740a56073b 5512 #define FTM_COMBINE_DTEN0_SHIFT (4U)
AnnaBridge 143:86740a56073b 5513 #define FTM_COMBINE_DTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN0_SHIFT)) & FTM_COMBINE_DTEN0_MASK)
AnnaBridge 143:86740a56073b 5514 #define FTM_COMBINE_SYNCEN0_MASK (0x20U)
AnnaBridge 143:86740a56073b 5515 #define FTM_COMBINE_SYNCEN0_SHIFT (5U)
AnnaBridge 143:86740a56073b 5516 #define FTM_COMBINE_SYNCEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN0_SHIFT)) & FTM_COMBINE_SYNCEN0_MASK)
AnnaBridge 143:86740a56073b 5517 #define FTM_COMBINE_FAULTEN0_MASK (0x40U)
AnnaBridge 143:86740a56073b 5518 #define FTM_COMBINE_FAULTEN0_SHIFT (6U)
AnnaBridge 143:86740a56073b 5519 #define FTM_COMBINE_FAULTEN0(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN0_SHIFT)) & FTM_COMBINE_FAULTEN0_MASK)
AnnaBridge 143:86740a56073b 5520 #define FTM_COMBINE_COMBINE1_MASK (0x100U)
AnnaBridge 143:86740a56073b 5521 #define FTM_COMBINE_COMBINE1_SHIFT (8U)
AnnaBridge 143:86740a56073b 5522 #define FTM_COMBINE_COMBINE1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE1_SHIFT)) & FTM_COMBINE_COMBINE1_MASK)
AnnaBridge 143:86740a56073b 5523 #define FTM_COMBINE_COMP1_MASK (0x200U)
AnnaBridge 143:86740a56073b 5524 #define FTM_COMBINE_COMP1_SHIFT (9U)
AnnaBridge 143:86740a56073b 5525 #define FTM_COMBINE_COMP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP1_SHIFT)) & FTM_COMBINE_COMP1_MASK)
AnnaBridge 143:86740a56073b 5526 #define FTM_COMBINE_DECAPEN1_MASK (0x400U)
AnnaBridge 143:86740a56073b 5527 #define FTM_COMBINE_DECAPEN1_SHIFT (10U)
AnnaBridge 143:86740a56073b 5528 #define FTM_COMBINE_DECAPEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN1_SHIFT)) & FTM_COMBINE_DECAPEN1_MASK)
AnnaBridge 143:86740a56073b 5529 #define FTM_COMBINE_DECAP1_MASK (0x800U)
AnnaBridge 143:86740a56073b 5530 #define FTM_COMBINE_DECAP1_SHIFT (11U)
AnnaBridge 143:86740a56073b 5531 #define FTM_COMBINE_DECAP1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP1_SHIFT)) & FTM_COMBINE_DECAP1_MASK)
AnnaBridge 143:86740a56073b 5532 #define FTM_COMBINE_DTEN1_MASK (0x1000U)
AnnaBridge 143:86740a56073b 5533 #define FTM_COMBINE_DTEN1_SHIFT (12U)
AnnaBridge 143:86740a56073b 5534 #define FTM_COMBINE_DTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN1_SHIFT)) & FTM_COMBINE_DTEN1_MASK)
AnnaBridge 143:86740a56073b 5535 #define FTM_COMBINE_SYNCEN1_MASK (0x2000U)
AnnaBridge 143:86740a56073b 5536 #define FTM_COMBINE_SYNCEN1_SHIFT (13U)
AnnaBridge 143:86740a56073b 5537 #define FTM_COMBINE_SYNCEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN1_SHIFT)) & FTM_COMBINE_SYNCEN1_MASK)
AnnaBridge 143:86740a56073b 5538 #define FTM_COMBINE_FAULTEN1_MASK (0x4000U)
AnnaBridge 143:86740a56073b 5539 #define FTM_COMBINE_FAULTEN1_SHIFT (14U)
AnnaBridge 143:86740a56073b 5540 #define FTM_COMBINE_FAULTEN1(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN1_SHIFT)) & FTM_COMBINE_FAULTEN1_MASK)
AnnaBridge 143:86740a56073b 5541 #define FTM_COMBINE_COMBINE2_MASK (0x10000U)
AnnaBridge 143:86740a56073b 5542 #define FTM_COMBINE_COMBINE2_SHIFT (16U)
AnnaBridge 143:86740a56073b 5543 #define FTM_COMBINE_COMBINE2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE2_SHIFT)) & FTM_COMBINE_COMBINE2_MASK)
AnnaBridge 143:86740a56073b 5544 #define FTM_COMBINE_COMP2_MASK (0x20000U)
AnnaBridge 143:86740a56073b 5545 #define FTM_COMBINE_COMP2_SHIFT (17U)
AnnaBridge 143:86740a56073b 5546 #define FTM_COMBINE_COMP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP2_SHIFT)) & FTM_COMBINE_COMP2_MASK)
AnnaBridge 143:86740a56073b 5547 #define FTM_COMBINE_DECAPEN2_MASK (0x40000U)
AnnaBridge 143:86740a56073b 5548 #define FTM_COMBINE_DECAPEN2_SHIFT (18U)
AnnaBridge 143:86740a56073b 5549 #define FTM_COMBINE_DECAPEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN2_SHIFT)) & FTM_COMBINE_DECAPEN2_MASK)
AnnaBridge 143:86740a56073b 5550 #define FTM_COMBINE_DECAP2_MASK (0x80000U)
AnnaBridge 143:86740a56073b 5551 #define FTM_COMBINE_DECAP2_SHIFT (19U)
AnnaBridge 143:86740a56073b 5552 #define FTM_COMBINE_DECAP2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP2_SHIFT)) & FTM_COMBINE_DECAP2_MASK)
AnnaBridge 143:86740a56073b 5553 #define FTM_COMBINE_DTEN2_MASK (0x100000U)
AnnaBridge 143:86740a56073b 5554 #define FTM_COMBINE_DTEN2_SHIFT (20U)
AnnaBridge 143:86740a56073b 5555 #define FTM_COMBINE_DTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN2_SHIFT)) & FTM_COMBINE_DTEN2_MASK)
AnnaBridge 143:86740a56073b 5556 #define FTM_COMBINE_SYNCEN2_MASK (0x200000U)
AnnaBridge 143:86740a56073b 5557 #define FTM_COMBINE_SYNCEN2_SHIFT (21U)
AnnaBridge 143:86740a56073b 5558 #define FTM_COMBINE_SYNCEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN2_SHIFT)) & FTM_COMBINE_SYNCEN2_MASK)
AnnaBridge 143:86740a56073b 5559 #define FTM_COMBINE_FAULTEN2_MASK (0x400000U)
AnnaBridge 143:86740a56073b 5560 #define FTM_COMBINE_FAULTEN2_SHIFT (22U)
AnnaBridge 143:86740a56073b 5561 #define FTM_COMBINE_FAULTEN2(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN2_SHIFT)) & FTM_COMBINE_FAULTEN2_MASK)
AnnaBridge 143:86740a56073b 5562 #define FTM_COMBINE_COMBINE3_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 5563 #define FTM_COMBINE_COMBINE3_SHIFT (24U)
AnnaBridge 143:86740a56073b 5564 #define FTM_COMBINE_COMBINE3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMBINE3_SHIFT)) & FTM_COMBINE_COMBINE3_MASK)
AnnaBridge 143:86740a56073b 5565 #define FTM_COMBINE_COMP3_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 5566 #define FTM_COMBINE_COMP3_SHIFT (25U)
AnnaBridge 143:86740a56073b 5567 #define FTM_COMBINE_COMP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_COMP3_SHIFT)) & FTM_COMBINE_COMP3_MASK)
AnnaBridge 143:86740a56073b 5568 #define FTM_COMBINE_DECAPEN3_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 5569 #define FTM_COMBINE_DECAPEN3_SHIFT (26U)
AnnaBridge 143:86740a56073b 5570 #define FTM_COMBINE_DECAPEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAPEN3_SHIFT)) & FTM_COMBINE_DECAPEN3_MASK)
AnnaBridge 143:86740a56073b 5571 #define FTM_COMBINE_DECAP3_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 5572 #define FTM_COMBINE_DECAP3_SHIFT (27U)
AnnaBridge 143:86740a56073b 5573 #define FTM_COMBINE_DECAP3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DECAP3_SHIFT)) & FTM_COMBINE_DECAP3_MASK)
AnnaBridge 143:86740a56073b 5574 #define FTM_COMBINE_DTEN3_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 5575 #define FTM_COMBINE_DTEN3_SHIFT (28U)
AnnaBridge 143:86740a56073b 5576 #define FTM_COMBINE_DTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_DTEN3_SHIFT)) & FTM_COMBINE_DTEN3_MASK)
AnnaBridge 143:86740a56073b 5577 #define FTM_COMBINE_SYNCEN3_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 5578 #define FTM_COMBINE_SYNCEN3_SHIFT (29U)
AnnaBridge 143:86740a56073b 5579 #define FTM_COMBINE_SYNCEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_SYNCEN3_SHIFT)) & FTM_COMBINE_SYNCEN3_MASK)
AnnaBridge 143:86740a56073b 5580 #define FTM_COMBINE_FAULTEN3_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 5581 #define FTM_COMBINE_FAULTEN3_SHIFT (30U)
AnnaBridge 143:86740a56073b 5582 #define FTM_COMBINE_FAULTEN3(x) (((uint32_t)(((uint32_t)(x)) << FTM_COMBINE_FAULTEN3_SHIFT)) & FTM_COMBINE_FAULTEN3_MASK)
AnnaBridge 143:86740a56073b 5583
AnnaBridge 143:86740a56073b 5584 /*! @name DEADTIME - Deadtime Insertion Control */
AnnaBridge 143:86740a56073b 5585 #define FTM_DEADTIME_DTVAL_MASK (0x3FU)
AnnaBridge 143:86740a56073b 5586 #define FTM_DEADTIME_DTVAL_SHIFT (0U)
AnnaBridge 143:86740a56073b 5587 #define FTM_DEADTIME_DTVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTVAL_SHIFT)) & FTM_DEADTIME_DTVAL_MASK)
AnnaBridge 143:86740a56073b 5588 #define FTM_DEADTIME_DTPS_MASK (0xC0U)
AnnaBridge 143:86740a56073b 5589 #define FTM_DEADTIME_DTPS_SHIFT (6U)
AnnaBridge 143:86740a56073b 5590 #define FTM_DEADTIME_DTPS(x) (((uint32_t)(((uint32_t)(x)) << FTM_DEADTIME_DTPS_SHIFT)) & FTM_DEADTIME_DTPS_MASK)
AnnaBridge 143:86740a56073b 5591
AnnaBridge 143:86740a56073b 5592 /*! @name EXTTRIG - FTM External Trigger */
AnnaBridge 143:86740a56073b 5593 #define FTM_EXTTRIG_CH2TRIG_MASK (0x1U)
AnnaBridge 143:86740a56073b 5594 #define FTM_EXTTRIG_CH2TRIG_SHIFT (0U)
AnnaBridge 143:86740a56073b 5595 #define FTM_EXTTRIG_CH2TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH2TRIG_SHIFT)) & FTM_EXTTRIG_CH2TRIG_MASK)
AnnaBridge 143:86740a56073b 5596 #define FTM_EXTTRIG_CH3TRIG_MASK (0x2U)
AnnaBridge 143:86740a56073b 5597 #define FTM_EXTTRIG_CH3TRIG_SHIFT (1U)
AnnaBridge 143:86740a56073b 5598 #define FTM_EXTTRIG_CH3TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH3TRIG_SHIFT)) & FTM_EXTTRIG_CH3TRIG_MASK)
AnnaBridge 143:86740a56073b 5599 #define FTM_EXTTRIG_CH4TRIG_MASK (0x4U)
AnnaBridge 143:86740a56073b 5600 #define FTM_EXTTRIG_CH4TRIG_SHIFT (2U)
AnnaBridge 143:86740a56073b 5601 #define FTM_EXTTRIG_CH4TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH4TRIG_SHIFT)) & FTM_EXTTRIG_CH4TRIG_MASK)
AnnaBridge 143:86740a56073b 5602 #define FTM_EXTTRIG_CH5TRIG_MASK (0x8U)
AnnaBridge 143:86740a56073b 5603 #define FTM_EXTTRIG_CH5TRIG_SHIFT (3U)
AnnaBridge 143:86740a56073b 5604 #define FTM_EXTTRIG_CH5TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH5TRIG_SHIFT)) & FTM_EXTTRIG_CH5TRIG_MASK)
AnnaBridge 143:86740a56073b 5605 #define FTM_EXTTRIG_CH0TRIG_MASK (0x10U)
AnnaBridge 143:86740a56073b 5606 #define FTM_EXTTRIG_CH0TRIG_SHIFT (4U)
AnnaBridge 143:86740a56073b 5607 #define FTM_EXTTRIG_CH0TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH0TRIG_SHIFT)) & FTM_EXTTRIG_CH0TRIG_MASK)
AnnaBridge 143:86740a56073b 5608 #define FTM_EXTTRIG_CH1TRIG_MASK (0x20U)
AnnaBridge 143:86740a56073b 5609 #define FTM_EXTTRIG_CH1TRIG_SHIFT (5U)
AnnaBridge 143:86740a56073b 5610 #define FTM_EXTTRIG_CH1TRIG(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_CH1TRIG_SHIFT)) & FTM_EXTTRIG_CH1TRIG_MASK)
AnnaBridge 143:86740a56073b 5611 #define FTM_EXTTRIG_INITTRIGEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 5612 #define FTM_EXTTRIG_INITTRIGEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 5613 #define FTM_EXTTRIG_INITTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_INITTRIGEN_SHIFT)) & FTM_EXTTRIG_INITTRIGEN_MASK)
AnnaBridge 143:86740a56073b 5614 #define FTM_EXTTRIG_TRIGF_MASK (0x80U)
AnnaBridge 143:86740a56073b 5615 #define FTM_EXTTRIG_TRIGF_SHIFT (7U)
AnnaBridge 143:86740a56073b 5616 #define FTM_EXTTRIG_TRIGF(x) (((uint32_t)(((uint32_t)(x)) << FTM_EXTTRIG_TRIGF_SHIFT)) & FTM_EXTTRIG_TRIGF_MASK)
AnnaBridge 143:86740a56073b 5617
AnnaBridge 143:86740a56073b 5618 /*! @name POL - Channels Polarity */
AnnaBridge 143:86740a56073b 5619 #define FTM_POL_POL0_MASK (0x1U)
AnnaBridge 143:86740a56073b 5620 #define FTM_POL_POL0_SHIFT (0U)
AnnaBridge 143:86740a56073b 5621 #define FTM_POL_POL0(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL0_SHIFT)) & FTM_POL_POL0_MASK)
AnnaBridge 143:86740a56073b 5622 #define FTM_POL_POL1_MASK (0x2U)
AnnaBridge 143:86740a56073b 5623 #define FTM_POL_POL1_SHIFT (1U)
AnnaBridge 143:86740a56073b 5624 #define FTM_POL_POL1(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL1_SHIFT)) & FTM_POL_POL1_MASK)
AnnaBridge 143:86740a56073b 5625 #define FTM_POL_POL2_MASK (0x4U)
AnnaBridge 143:86740a56073b 5626 #define FTM_POL_POL2_SHIFT (2U)
AnnaBridge 143:86740a56073b 5627 #define FTM_POL_POL2(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL2_SHIFT)) & FTM_POL_POL2_MASK)
AnnaBridge 143:86740a56073b 5628 #define FTM_POL_POL3_MASK (0x8U)
AnnaBridge 143:86740a56073b 5629 #define FTM_POL_POL3_SHIFT (3U)
AnnaBridge 143:86740a56073b 5630 #define FTM_POL_POL3(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL3_SHIFT)) & FTM_POL_POL3_MASK)
AnnaBridge 143:86740a56073b 5631 #define FTM_POL_POL4_MASK (0x10U)
AnnaBridge 143:86740a56073b 5632 #define FTM_POL_POL4_SHIFT (4U)
AnnaBridge 143:86740a56073b 5633 #define FTM_POL_POL4(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL4_SHIFT)) & FTM_POL_POL4_MASK)
AnnaBridge 143:86740a56073b 5634 #define FTM_POL_POL5_MASK (0x20U)
AnnaBridge 143:86740a56073b 5635 #define FTM_POL_POL5_SHIFT (5U)
AnnaBridge 143:86740a56073b 5636 #define FTM_POL_POL5(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL5_SHIFT)) & FTM_POL_POL5_MASK)
AnnaBridge 143:86740a56073b 5637 #define FTM_POL_POL6_MASK (0x40U)
AnnaBridge 143:86740a56073b 5638 #define FTM_POL_POL6_SHIFT (6U)
AnnaBridge 143:86740a56073b 5639 #define FTM_POL_POL6(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL6_SHIFT)) & FTM_POL_POL6_MASK)
AnnaBridge 143:86740a56073b 5640 #define FTM_POL_POL7_MASK (0x80U)
AnnaBridge 143:86740a56073b 5641 #define FTM_POL_POL7_SHIFT (7U)
AnnaBridge 143:86740a56073b 5642 #define FTM_POL_POL7(x) (((uint32_t)(((uint32_t)(x)) << FTM_POL_POL7_SHIFT)) & FTM_POL_POL7_MASK)
AnnaBridge 143:86740a56073b 5643
AnnaBridge 143:86740a56073b 5644 /*! @name FMS - Fault Mode Status */
AnnaBridge 143:86740a56073b 5645 #define FTM_FMS_FAULTF0_MASK (0x1U)
AnnaBridge 143:86740a56073b 5646 #define FTM_FMS_FAULTF0_SHIFT (0U)
AnnaBridge 143:86740a56073b 5647 #define FTM_FMS_FAULTF0(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF0_SHIFT)) & FTM_FMS_FAULTF0_MASK)
AnnaBridge 143:86740a56073b 5648 #define FTM_FMS_FAULTF1_MASK (0x2U)
AnnaBridge 143:86740a56073b 5649 #define FTM_FMS_FAULTF1_SHIFT (1U)
AnnaBridge 143:86740a56073b 5650 #define FTM_FMS_FAULTF1(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF1_SHIFT)) & FTM_FMS_FAULTF1_MASK)
AnnaBridge 143:86740a56073b 5651 #define FTM_FMS_FAULTF2_MASK (0x4U)
AnnaBridge 143:86740a56073b 5652 #define FTM_FMS_FAULTF2_SHIFT (2U)
AnnaBridge 143:86740a56073b 5653 #define FTM_FMS_FAULTF2(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF2_SHIFT)) & FTM_FMS_FAULTF2_MASK)
AnnaBridge 143:86740a56073b 5654 #define FTM_FMS_FAULTF3_MASK (0x8U)
AnnaBridge 143:86740a56073b 5655 #define FTM_FMS_FAULTF3_SHIFT (3U)
AnnaBridge 143:86740a56073b 5656 #define FTM_FMS_FAULTF3(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF3_SHIFT)) & FTM_FMS_FAULTF3_MASK)
AnnaBridge 143:86740a56073b 5657 #define FTM_FMS_FAULTIN_MASK (0x20U)
AnnaBridge 143:86740a56073b 5658 #define FTM_FMS_FAULTIN_SHIFT (5U)
AnnaBridge 143:86740a56073b 5659 #define FTM_FMS_FAULTIN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTIN_SHIFT)) & FTM_FMS_FAULTIN_MASK)
AnnaBridge 143:86740a56073b 5660 #define FTM_FMS_WPEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 5661 #define FTM_FMS_WPEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 5662 #define FTM_FMS_WPEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_WPEN_SHIFT)) & FTM_FMS_WPEN_MASK)
AnnaBridge 143:86740a56073b 5663 #define FTM_FMS_FAULTF_MASK (0x80U)
AnnaBridge 143:86740a56073b 5664 #define FTM_FMS_FAULTF_SHIFT (7U)
AnnaBridge 143:86740a56073b 5665 #define FTM_FMS_FAULTF(x) (((uint32_t)(((uint32_t)(x)) << FTM_FMS_FAULTF_SHIFT)) & FTM_FMS_FAULTF_MASK)
AnnaBridge 143:86740a56073b 5666
AnnaBridge 143:86740a56073b 5667 /*! @name FILTER - Input Capture Filter Control */
AnnaBridge 143:86740a56073b 5668 #define FTM_FILTER_CH0FVAL_MASK (0xFU)
AnnaBridge 143:86740a56073b 5669 #define FTM_FILTER_CH0FVAL_SHIFT (0U)
AnnaBridge 143:86740a56073b 5670 #define FTM_FILTER_CH0FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH0FVAL_SHIFT)) & FTM_FILTER_CH0FVAL_MASK)
AnnaBridge 143:86740a56073b 5671 #define FTM_FILTER_CH1FVAL_MASK (0xF0U)
AnnaBridge 143:86740a56073b 5672 #define FTM_FILTER_CH1FVAL_SHIFT (4U)
AnnaBridge 143:86740a56073b 5673 #define FTM_FILTER_CH1FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH1FVAL_SHIFT)) & FTM_FILTER_CH1FVAL_MASK)
AnnaBridge 143:86740a56073b 5674 #define FTM_FILTER_CH2FVAL_MASK (0xF00U)
AnnaBridge 143:86740a56073b 5675 #define FTM_FILTER_CH2FVAL_SHIFT (8U)
AnnaBridge 143:86740a56073b 5676 #define FTM_FILTER_CH2FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH2FVAL_SHIFT)) & FTM_FILTER_CH2FVAL_MASK)
AnnaBridge 143:86740a56073b 5677 #define FTM_FILTER_CH3FVAL_MASK (0xF000U)
AnnaBridge 143:86740a56073b 5678 #define FTM_FILTER_CH3FVAL_SHIFT (12U)
AnnaBridge 143:86740a56073b 5679 #define FTM_FILTER_CH3FVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FILTER_CH3FVAL_SHIFT)) & FTM_FILTER_CH3FVAL_MASK)
AnnaBridge 143:86740a56073b 5680
AnnaBridge 143:86740a56073b 5681 /*! @name FLTCTRL - Fault Control */
AnnaBridge 143:86740a56073b 5682 #define FTM_FLTCTRL_FAULT0EN_MASK (0x1U)
AnnaBridge 143:86740a56073b 5683 #define FTM_FLTCTRL_FAULT0EN_SHIFT (0U)
AnnaBridge 143:86740a56073b 5684 #define FTM_FLTCTRL_FAULT0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT0EN_SHIFT)) & FTM_FLTCTRL_FAULT0EN_MASK)
AnnaBridge 143:86740a56073b 5685 #define FTM_FLTCTRL_FAULT1EN_MASK (0x2U)
AnnaBridge 143:86740a56073b 5686 #define FTM_FLTCTRL_FAULT1EN_SHIFT (1U)
AnnaBridge 143:86740a56073b 5687 #define FTM_FLTCTRL_FAULT1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT1EN_SHIFT)) & FTM_FLTCTRL_FAULT1EN_MASK)
AnnaBridge 143:86740a56073b 5688 #define FTM_FLTCTRL_FAULT2EN_MASK (0x4U)
AnnaBridge 143:86740a56073b 5689 #define FTM_FLTCTRL_FAULT2EN_SHIFT (2U)
AnnaBridge 143:86740a56073b 5690 #define FTM_FLTCTRL_FAULT2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT2EN_SHIFT)) & FTM_FLTCTRL_FAULT2EN_MASK)
AnnaBridge 143:86740a56073b 5691 #define FTM_FLTCTRL_FAULT3EN_MASK (0x8U)
AnnaBridge 143:86740a56073b 5692 #define FTM_FLTCTRL_FAULT3EN_SHIFT (3U)
AnnaBridge 143:86740a56073b 5693 #define FTM_FLTCTRL_FAULT3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FAULT3EN_SHIFT)) & FTM_FLTCTRL_FAULT3EN_MASK)
AnnaBridge 143:86740a56073b 5694 #define FTM_FLTCTRL_FFLTR0EN_MASK (0x10U)
AnnaBridge 143:86740a56073b 5695 #define FTM_FLTCTRL_FFLTR0EN_SHIFT (4U)
AnnaBridge 143:86740a56073b 5696 #define FTM_FLTCTRL_FFLTR0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR0EN_SHIFT)) & FTM_FLTCTRL_FFLTR0EN_MASK)
AnnaBridge 143:86740a56073b 5697 #define FTM_FLTCTRL_FFLTR1EN_MASK (0x20U)
AnnaBridge 143:86740a56073b 5698 #define FTM_FLTCTRL_FFLTR1EN_SHIFT (5U)
AnnaBridge 143:86740a56073b 5699 #define FTM_FLTCTRL_FFLTR1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR1EN_SHIFT)) & FTM_FLTCTRL_FFLTR1EN_MASK)
AnnaBridge 143:86740a56073b 5700 #define FTM_FLTCTRL_FFLTR2EN_MASK (0x40U)
AnnaBridge 143:86740a56073b 5701 #define FTM_FLTCTRL_FFLTR2EN_SHIFT (6U)
AnnaBridge 143:86740a56073b 5702 #define FTM_FLTCTRL_FFLTR2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR2EN_SHIFT)) & FTM_FLTCTRL_FFLTR2EN_MASK)
AnnaBridge 143:86740a56073b 5703 #define FTM_FLTCTRL_FFLTR3EN_MASK (0x80U)
AnnaBridge 143:86740a56073b 5704 #define FTM_FLTCTRL_FFLTR3EN_SHIFT (7U)
AnnaBridge 143:86740a56073b 5705 #define FTM_FLTCTRL_FFLTR3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFLTR3EN_SHIFT)) & FTM_FLTCTRL_FFLTR3EN_MASK)
AnnaBridge 143:86740a56073b 5706 #define FTM_FLTCTRL_FFVAL_MASK (0xF00U)
AnnaBridge 143:86740a56073b 5707 #define FTM_FLTCTRL_FFVAL_SHIFT (8U)
AnnaBridge 143:86740a56073b 5708 #define FTM_FLTCTRL_FFVAL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTCTRL_FFVAL_SHIFT)) & FTM_FLTCTRL_FFVAL_MASK)
AnnaBridge 143:86740a56073b 5709
AnnaBridge 143:86740a56073b 5710 /*! @name QDCTRL - Quadrature Decoder Control And Status */
AnnaBridge 143:86740a56073b 5711 #define FTM_QDCTRL_QUADEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 5712 #define FTM_QDCTRL_QUADEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 5713 #define FTM_QDCTRL_QUADEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADEN_SHIFT)) & FTM_QDCTRL_QUADEN_MASK)
AnnaBridge 143:86740a56073b 5714 #define FTM_QDCTRL_TOFDIR_MASK (0x2U)
AnnaBridge 143:86740a56073b 5715 #define FTM_QDCTRL_TOFDIR_SHIFT (1U)
AnnaBridge 143:86740a56073b 5716 #define FTM_QDCTRL_TOFDIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_TOFDIR_SHIFT)) & FTM_QDCTRL_TOFDIR_MASK)
AnnaBridge 143:86740a56073b 5717 #define FTM_QDCTRL_QUADIR_MASK (0x4U)
AnnaBridge 143:86740a56073b 5718 #define FTM_QDCTRL_QUADIR_SHIFT (2U)
AnnaBridge 143:86740a56073b 5719 #define FTM_QDCTRL_QUADIR(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADIR_SHIFT)) & FTM_QDCTRL_QUADIR_MASK)
AnnaBridge 143:86740a56073b 5720 #define FTM_QDCTRL_QUADMODE_MASK (0x8U)
AnnaBridge 143:86740a56073b 5721 #define FTM_QDCTRL_QUADMODE_SHIFT (3U)
AnnaBridge 143:86740a56073b 5722 #define FTM_QDCTRL_QUADMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_QUADMODE_SHIFT)) & FTM_QDCTRL_QUADMODE_MASK)
AnnaBridge 143:86740a56073b 5723 #define FTM_QDCTRL_PHBPOL_MASK (0x10U)
AnnaBridge 143:86740a56073b 5724 #define FTM_QDCTRL_PHBPOL_SHIFT (4U)
AnnaBridge 143:86740a56073b 5725 #define FTM_QDCTRL_PHBPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBPOL_SHIFT)) & FTM_QDCTRL_PHBPOL_MASK)
AnnaBridge 143:86740a56073b 5726 #define FTM_QDCTRL_PHAPOL_MASK (0x20U)
AnnaBridge 143:86740a56073b 5727 #define FTM_QDCTRL_PHAPOL_SHIFT (5U)
AnnaBridge 143:86740a56073b 5728 #define FTM_QDCTRL_PHAPOL(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAPOL_SHIFT)) & FTM_QDCTRL_PHAPOL_MASK)
AnnaBridge 143:86740a56073b 5729 #define FTM_QDCTRL_PHBFLTREN_MASK (0x40U)
AnnaBridge 143:86740a56073b 5730 #define FTM_QDCTRL_PHBFLTREN_SHIFT (6U)
AnnaBridge 143:86740a56073b 5731 #define FTM_QDCTRL_PHBFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHBFLTREN_SHIFT)) & FTM_QDCTRL_PHBFLTREN_MASK)
AnnaBridge 143:86740a56073b 5732 #define FTM_QDCTRL_PHAFLTREN_MASK (0x80U)
AnnaBridge 143:86740a56073b 5733 #define FTM_QDCTRL_PHAFLTREN_SHIFT (7U)
AnnaBridge 143:86740a56073b 5734 #define FTM_QDCTRL_PHAFLTREN(x) (((uint32_t)(((uint32_t)(x)) << FTM_QDCTRL_PHAFLTREN_SHIFT)) & FTM_QDCTRL_PHAFLTREN_MASK)
AnnaBridge 143:86740a56073b 5735
AnnaBridge 143:86740a56073b 5736 /*! @name CONF - Configuration */
AnnaBridge 143:86740a56073b 5737 #define FTM_CONF_NUMTOF_MASK (0x1FU)
AnnaBridge 143:86740a56073b 5738 #define FTM_CONF_NUMTOF_SHIFT (0U)
AnnaBridge 143:86740a56073b 5739 #define FTM_CONF_NUMTOF(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_NUMTOF_SHIFT)) & FTM_CONF_NUMTOF_MASK)
AnnaBridge 143:86740a56073b 5740 #define FTM_CONF_BDMMODE_MASK (0xC0U)
AnnaBridge 143:86740a56073b 5741 #define FTM_CONF_BDMMODE_SHIFT (6U)
AnnaBridge 143:86740a56073b 5742 #define FTM_CONF_BDMMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_BDMMODE_SHIFT)) & FTM_CONF_BDMMODE_MASK)
AnnaBridge 143:86740a56073b 5743 #define FTM_CONF_GTBEEN_MASK (0x200U)
AnnaBridge 143:86740a56073b 5744 #define FTM_CONF_GTBEEN_SHIFT (9U)
AnnaBridge 143:86740a56073b 5745 #define FTM_CONF_GTBEEN(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEEN_SHIFT)) & FTM_CONF_GTBEEN_MASK)
AnnaBridge 143:86740a56073b 5746 #define FTM_CONF_GTBEOUT_MASK (0x400U)
AnnaBridge 143:86740a56073b 5747 #define FTM_CONF_GTBEOUT_SHIFT (10U)
AnnaBridge 143:86740a56073b 5748 #define FTM_CONF_GTBEOUT(x) (((uint32_t)(((uint32_t)(x)) << FTM_CONF_GTBEOUT_SHIFT)) & FTM_CONF_GTBEOUT_MASK)
AnnaBridge 143:86740a56073b 5749
AnnaBridge 143:86740a56073b 5750 /*! @name FLTPOL - FTM Fault Input Polarity */
AnnaBridge 143:86740a56073b 5751 #define FTM_FLTPOL_FLT0POL_MASK (0x1U)
AnnaBridge 143:86740a56073b 5752 #define FTM_FLTPOL_FLT0POL_SHIFT (0U)
AnnaBridge 143:86740a56073b 5753 #define FTM_FLTPOL_FLT0POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT0POL_SHIFT)) & FTM_FLTPOL_FLT0POL_MASK)
AnnaBridge 143:86740a56073b 5754 #define FTM_FLTPOL_FLT1POL_MASK (0x2U)
AnnaBridge 143:86740a56073b 5755 #define FTM_FLTPOL_FLT1POL_SHIFT (1U)
AnnaBridge 143:86740a56073b 5756 #define FTM_FLTPOL_FLT1POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT1POL_SHIFT)) & FTM_FLTPOL_FLT1POL_MASK)
AnnaBridge 143:86740a56073b 5757 #define FTM_FLTPOL_FLT2POL_MASK (0x4U)
AnnaBridge 143:86740a56073b 5758 #define FTM_FLTPOL_FLT2POL_SHIFT (2U)
AnnaBridge 143:86740a56073b 5759 #define FTM_FLTPOL_FLT2POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT2POL_SHIFT)) & FTM_FLTPOL_FLT2POL_MASK)
AnnaBridge 143:86740a56073b 5760 #define FTM_FLTPOL_FLT3POL_MASK (0x8U)
AnnaBridge 143:86740a56073b 5761 #define FTM_FLTPOL_FLT3POL_SHIFT (3U)
AnnaBridge 143:86740a56073b 5762 #define FTM_FLTPOL_FLT3POL(x) (((uint32_t)(((uint32_t)(x)) << FTM_FLTPOL_FLT3POL_SHIFT)) & FTM_FLTPOL_FLT3POL_MASK)
AnnaBridge 143:86740a56073b 5763
AnnaBridge 143:86740a56073b 5764 /*! @name SYNCONF - Synchronization Configuration */
AnnaBridge 143:86740a56073b 5765 #define FTM_SYNCONF_HWTRIGMODE_MASK (0x1U)
AnnaBridge 143:86740a56073b 5766 #define FTM_SYNCONF_HWTRIGMODE_SHIFT (0U)
AnnaBridge 143:86740a56073b 5767 #define FTM_SYNCONF_HWTRIGMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWTRIGMODE_SHIFT)) & FTM_SYNCONF_HWTRIGMODE_MASK)
AnnaBridge 143:86740a56073b 5768 #define FTM_SYNCONF_CNTINC_MASK (0x4U)
AnnaBridge 143:86740a56073b 5769 #define FTM_SYNCONF_CNTINC_SHIFT (2U)
AnnaBridge 143:86740a56073b 5770 #define FTM_SYNCONF_CNTINC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_CNTINC_SHIFT)) & FTM_SYNCONF_CNTINC_MASK)
AnnaBridge 143:86740a56073b 5771 #define FTM_SYNCONF_INVC_MASK (0x10U)
AnnaBridge 143:86740a56073b 5772 #define FTM_SYNCONF_INVC_SHIFT (4U)
AnnaBridge 143:86740a56073b 5773 #define FTM_SYNCONF_INVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_INVC_SHIFT)) & FTM_SYNCONF_INVC_MASK)
AnnaBridge 143:86740a56073b 5774 #define FTM_SYNCONF_SWOC_MASK (0x20U)
AnnaBridge 143:86740a56073b 5775 #define FTM_SYNCONF_SWOC_SHIFT (5U)
AnnaBridge 143:86740a56073b 5776 #define FTM_SYNCONF_SWOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOC_SHIFT)) & FTM_SYNCONF_SWOC_MASK)
AnnaBridge 143:86740a56073b 5777 #define FTM_SYNCONF_SYNCMODE_MASK (0x80U)
AnnaBridge 143:86740a56073b 5778 #define FTM_SYNCONF_SYNCMODE_SHIFT (7U)
AnnaBridge 143:86740a56073b 5779 #define FTM_SYNCONF_SYNCMODE(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SYNCMODE_SHIFT)) & FTM_SYNCONF_SYNCMODE_MASK)
AnnaBridge 143:86740a56073b 5780 #define FTM_SYNCONF_SWRSTCNT_MASK (0x100U)
AnnaBridge 143:86740a56073b 5781 #define FTM_SYNCONF_SWRSTCNT_SHIFT (8U)
AnnaBridge 143:86740a56073b 5782 #define FTM_SYNCONF_SWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWRSTCNT_SHIFT)) & FTM_SYNCONF_SWRSTCNT_MASK)
AnnaBridge 143:86740a56073b 5783 #define FTM_SYNCONF_SWWRBUF_MASK (0x200U)
AnnaBridge 143:86740a56073b 5784 #define FTM_SYNCONF_SWWRBUF_SHIFT (9U)
AnnaBridge 143:86740a56073b 5785 #define FTM_SYNCONF_SWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWWRBUF_SHIFT)) & FTM_SYNCONF_SWWRBUF_MASK)
AnnaBridge 143:86740a56073b 5786 #define FTM_SYNCONF_SWOM_MASK (0x400U)
AnnaBridge 143:86740a56073b 5787 #define FTM_SYNCONF_SWOM_SHIFT (10U)
AnnaBridge 143:86740a56073b 5788 #define FTM_SYNCONF_SWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWOM_SHIFT)) & FTM_SYNCONF_SWOM_MASK)
AnnaBridge 143:86740a56073b 5789 #define FTM_SYNCONF_SWINVC_MASK (0x800U)
AnnaBridge 143:86740a56073b 5790 #define FTM_SYNCONF_SWINVC_SHIFT (11U)
AnnaBridge 143:86740a56073b 5791 #define FTM_SYNCONF_SWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWINVC_SHIFT)) & FTM_SYNCONF_SWINVC_MASK)
AnnaBridge 143:86740a56073b 5792 #define FTM_SYNCONF_SWSOC_MASK (0x1000U)
AnnaBridge 143:86740a56073b 5793 #define FTM_SYNCONF_SWSOC_SHIFT (12U)
AnnaBridge 143:86740a56073b 5794 #define FTM_SYNCONF_SWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_SWSOC_SHIFT)) & FTM_SYNCONF_SWSOC_MASK)
AnnaBridge 143:86740a56073b 5795 #define FTM_SYNCONF_HWRSTCNT_MASK (0x10000U)
AnnaBridge 143:86740a56073b 5796 #define FTM_SYNCONF_HWRSTCNT_SHIFT (16U)
AnnaBridge 143:86740a56073b 5797 #define FTM_SYNCONF_HWRSTCNT(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWRSTCNT_SHIFT)) & FTM_SYNCONF_HWRSTCNT_MASK)
AnnaBridge 143:86740a56073b 5798 #define FTM_SYNCONF_HWWRBUF_MASK (0x20000U)
AnnaBridge 143:86740a56073b 5799 #define FTM_SYNCONF_HWWRBUF_SHIFT (17U)
AnnaBridge 143:86740a56073b 5800 #define FTM_SYNCONF_HWWRBUF(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWWRBUF_SHIFT)) & FTM_SYNCONF_HWWRBUF_MASK)
AnnaBridge 143:86740a56073b 5801 #define FTM_SYNCONF_HWOM_MASK (0x40000U)
AnnaBridge 143:86740a56073b 5802 #define FTM_SYNCONF_HWOM_SHIFT (18U)
AnnaBridge 143:86740a56073b 5803 #define FTM_SYNCONF_HWOM(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWOM_SHIFT)) & FTM_SYNCONF_HWOM_MASK)
AnnaBridge 143:86740a56073b 5804 #define FTM_SYNCONF_HWINVC_MASK (0x80000U)
AnnaBridge 143:86740a56073b 5805 #define FTM_SYNCONF_HWINVC_SHIFT (19U)
AnnaBridge 143:86740a56073b 5806 #define FTM_SYNCONF_HWINVC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWINVC_SHIFT)) & FTM_SYNCONF_HWINVC_MASK)
AnnaBridge 143:86740a56073b 5807 #define FTM_SYNCONF_HWSOC_MASK (0x100000U)
AnnaBridge 143:86740a56073b 5808 #define FTM_SYNCONF_HWSOC_SHIFT (20U)
AnnaBridge 143:86740a56073b 5809 #define FTM_SYNCONF_HWSOC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SYNCONF_HWSOC_SHIFT)) & FTM_SYNCONF_HWSOC_MASK)
AnnaBridge 143:86740a56073b 5810
AnnaBridge 143:86740a56073b 5811 /*! @name INVCTRL - FTM Inverting Control */
AnnaBridge 143:86740a56073b 5812 #define FTM_INVCTRL_INV0EN_MASK (0x1U)
AnnaBridge 143:86740a56073b 5813 #define FTM_INVCTRL_INV0EN_SHIFT (0U)
AnnaBridge 143:86740a56073b 5814 #define FTM_INVCTRL_INV0EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV0EN_SHIFT)) & FTM_INVCTRL_INV0EN_MASK)
AnnaBridge 143:86740a56073b 5815 #define FTM_INVCTRL_INV1EN_MASK (0x2U)
AnnaBridge 143:86740a56073b 5816 #define FTM_INVCTRL_INV1EN_SHIFT (1U)
AnnaBridge 143:86740a56073b 5817 #define FTM_INVCTRL_INV1EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV1EN_SHIFT)) & FTM_INVCTRL_INV1EN_MASK)
AnnaBridge 143:86740a56073b 5818 #define FTM_INVCTRL_INV2EN_MASK (0x4U)
AnnaBridge 143:86740a56073b 5819 #define FTM_INVCTRL_INV2EN_SHIFT (2U)
AnnaBridge 143:86740a56073b 5820 #define FTM_INVCTRL_INV2EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV2EN_SHIFT)) & FTM_INVCTRL_INV2EN_MASK)
AnnaBridge 143:86740a56073b 5821 #define FTM_INVCTRL_INV3EN_MASK (0x8U)
AnnaBridge 143:86740a56073b 5822 #define FTM_INVCTRL_INV3EN_SHIFT (3U)
AnnaBridge 143:86740a56073b 5823 #define FTM_INVCTRL_INV3EN(x) (((uint32_t)(((uint32_t)(x)) << FTM_INVCTRL_INV3EN_SHIFT)) & FTM_INVCTRL_INV3EN_MASK)
AnnaBridge 143:86740a56073b 5824
AnnaBridge 143:86740a56073b 5825 /*! @name SWOCTRL - FTM Software Output Control */
AnnaBridge 143:86740a56073b 5826 #define FTM_SWOCTRL_CH0OC_MASK (0x1U)
AnnaBridge 143:86740a56073b 5827 #define FTM_SWOCTRL_CH0OC_SHIFT (0U)
AnnaBridge 143:86740a56073b 5828 #define FTM_SWOCTRL_CH0OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OC_SHIFT)) & FTM_SWOCTRL_CH0OC_MASK)
AnnaBridge 143:86740a56073b 5829 #define FTM_SWOCTRL_CH1OC_MASK (0x2U)
AnnaBridge 143:86740a56073b 5830 #define FTM_SWOCTRL_CH1OC_SHIFT (1U)
AnnaBridge 143:86740a56073b 5831 #define FTM_SWOCTRL_CH1OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OC_SHIFT)) & FTM_SWOCTRL_CH1OC_MASK)
AnnaBridge 143:86740a56073b 5832 #define FTM_SWOCTRL_CH2OC_MASK (0x4U)
AnnaBridge 143:86740a56073b 5833 #define FTM_SWOCTRL_CH2OC_SHIFT (2U)
AnnaBridge 143:86740a56073b 5834 #define FTM_SWOCTRL_CH2OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OC_SHIFT)) & FTM_SWOCTRL_CH2OC_MASK)
AnnaBridge 143:86740a56073b 5835 #define FTM_SWOCTRL_CH3OC_MASK (0x8U)
AnnaBridge 143:86740a56073b 5836 #define FTM_SWOCTRL_CH3OC_SHIFT (3U)
AnnaBridge 143:86740a56073b 5837 #define FTM_SWOCTRL_CH3OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OC_SHIFT)) & FTM_SWOCTRL_CH3OC_MASK)
AnnaBridge 143:86740a56073b 5838 #define FTM_SWOCTRL_CH4OC_MASK (0x10U)
AnnaBridge 143:86740a56073b 5839 #define FTM_SWOCTRL_CH4OC_SHIFT (4U)
AnnaBridge 143:86740a56073b 5840 #define FTM_SWOCTRL_CH4OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OC_SHIFT)) & FTM_SWOCTRL_CH4OC_MASK)
AnnaBridge 143:86740a56073b 5841 #define FTM_SWOCTRL_CH5OC_MASK (0x20U)
AnnaBridge 143:86740a56073b 5842 #define FTM_SWOCTRL_CH5OC_SHIFT (5U)
AnnaBridge 143:86740a56073b 5843 #define FTM_SWOCTRL_CH5OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OC_SHIFT)) & FTM_SWOCTRL_CH5OC_MASK)
AnnaBridge 143:86740a56073b 5844 #define FTM_SWOCTRL_CH6OC_MASK (0x40U)
AnnaBridge 143:86740a56073b 5845 #define FTM_SWOCTRL_CH6OC_SHIFT (6U)
AnnaBridge 143:86740a56073b 5846 #define FTM_SWOCTRL_CH6OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OC_SHIFT)) & FTM_SWOCTRL_CH6OC_MASK)
AnnaBridge 143:86740a56073b 5847 #define FTM_SWOCTRL_CH7OC_MASK (0x80U)
AnnaBridge 143:86740a56073b 5848 #define FTM_SWOCTRL_CH7OC_SHIFT (7U)
AnnaBridge 143:86740a56073b 5849 #define FTM_SWOCTRL_CH7OC(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OC_SHIFT)) & FTM_SWOCTRL_CH7OC_MASK)
AnnaBridge 143:86740a56073b 5850 #define FTM_SWOCTRL_CH0OCV_MASK (0x100U)
AnnaBridge 143:86740a56073b 5851 #define FTM_SWOCTRL_CH0OCV_SHIFT (8U)
AnnaBridge 143:86740a56073b 5852 #define FTM_SWOCTRL_CH0OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH0OCV_SHIFT)) & FTM_SWOCTRL_CH0OCV_MASK)
AnnaBridge 143:86740a56073b 5853 #define FTM_SWOCTRL_CH1OCV_MASK (0x200U)
AnnaBridge 143:86740a56073b 5854 #define FTM_SWOCTRL_CH1OCV_SHIFT (9U)
AnnaBridge 143:86740a56073b 5855 #define FTM_SWOCTRL_CH1OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH1OCV_SHIFT)) & FTM_SWOCTRL_CH1OCV_MASK)
AnnaBridge 143:86740a56073b 5856 #define FTM_SWOCTRL_CH2OCV_MASK (0x400U)
AnnaBridge 143:86740a56073b 5857 #define FTM_SWOCTRL_CH2OCV_SHIFT (10U)
AnnaBridge 143:86740a56073b 5858 #define FTM_SWOCTRL_CH2OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH2OCV_SHIFT)) & FTM_SWOCTRL_CH2OCV_MASK)
AnnaBridge 143:86740a56073b 5859 #define FTM_SWOCTRL_CH3OCV_MASK (0x800U)
AnnaBridge 143:86740a56073b 5860 #define FTM_SWOCTRL_CH3OCV_SHIFT (11U)
AnnaBridge 143:86740a56073b 5861 #define FTM_SWOCTRL_CH3OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH3OCV_SHIFT)) & FTM_SWOCTRL_CH3OCV_MASK)
AnnaBridge 143:86740a56073b 5862 #define FTM_SWOCTRL_CH4OCV_MASK (0x1000U)
AnnaBridge 143:86740a56073b 5863 #define FTM_SWOCTRL_CH4OCV_SHIFT (12U)
AnnaBridge 143:86740a56073b 5864 #define FTM_SWOCTRL_CH4OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH4OCV_SHIFT)) & FTM_SWOCTRL_CH4OCV_MASK)
AnnaBridge 143:86740a56073b 5865 #define FTM_SWOCTRL_CH5OCV_MASK (0x2000U)
AnnaBridge 143:86740a56073b 5866 #define FTM_SWOCTRL_CH5OCV_SHIFT (13U)
AnnaBridge 143:86740a56073b 5867 #define FTM_SWOCTRL_CH5OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH5OCV_SHIFT)) & FTM_SWOCTRL_CH5OCV_MASK)
AnnaBridge 143:86740a56073b 5868 #define FTM_SWOCTRL_CH6OCV_MASK (0x4000U)
AnnaBridge 143:86740a56073b 5869 #define FTM_SWOCTRL_CH6OCV_SHIFT (14U)
AnnaBridge 143:86740a56073b 5870 #define FTM_SWOCTRL_CH6OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH6OCV_SHIFT)) & FTM_SWOCTRL_CH6OCV_MASK)
AnnaBridge 143:86740a56073b 5871 #define FTM_SWOCTRL_CH7OCV_MASK (0x8000U)
AnnaBridge 143:86740a56073b 5872 #define FTM_SWOCTRL_CH7OCV_SHIFT (15U)
AnnaBridge 143:86740a56073b 5873 #define FTM_SWOCTRL_CH7OCV(x) (((uint32_t)(((uint32_t)(x)) << FTM_SWOCTRL_CH7OCV_SHIFT)) & FTM_SWOCTRL_CH7OCV_MASK)
AnnaBridge 143:86740a56073b 5874
AnnaBridge 143:86740a56073b 5875 /*! @name PWMLOAD - FTM PWM Load */
AnnaBridge 143:86740a56073b 5876 #define FTM_PWMLOAD_CH0SEL_MASK (0x1U)
AnnaBridge 143:86740a56073b 5877 #define FTM_PWMLOAD_CH0SEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 5878 #define FTM_PWMLOAD_CH0SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH0SEL_SHIFT)) & FTM_PWMLOAD_CH0SEL_MASK)
AnnaBridge 143:86740a56073b 5879 #define FTM_PWMLOAD_CH1SEL_MASK (0x2U)
AnnaBridge 143:86740a56073b 5880 #define FTM_PWMLOAD_CH1SEL_SHIFT (1U)
AnnaBridge 143:86740a56073b 5881 #define FTM_PWMLOAD_CH1SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH1SEL_SHIFT)) & FTM_PWMLOAD_CH1SEL_MASK)
AnnaBridge 143:86740a56073b 5882 #define FTM_PWMLOAD_CH2SEL_MASK (0x4U)
AnnaBridge 143:86740a56073b 5883 #define FTM_PWMLOAD_CH2SEL_SHIFT (2U)
AnnaBridge 143:86740a56073b 5884 #define FTM_PWMLOAD_CH2SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH2SEL_SHIFT)) & FTM_PWMLOAD_CH2SEL_MASK)
AnnaBridge 143:86740a56073b 5885 #define FTM_PWMLOAD_CH3SEL_MASK (0x8U)
AnnaBridge 143:86740a56073b 5886 #define FTM_PWMLOAD_CH3SEL_SHIFT (3U)
AnnaBridge 143:86740a56073b 5887 #define FTM_PWMLOAD_CH3SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH3SEL_SHIFT)) & FTM_PWMLOAD_CH3SEL_MASK)
AnnaBridge 143:86740a56073b 5888 #define FTM_PWMLOAD_CH4SEL_MASK (0x10U)
AnnaBridge 143:86740a56073b 5889 #define FTM_PWMLOAD_CH4SEL_SHIFT (4U)
AnnaBridge 143:86740a56073b 5890 #define FTM_PWMLOAD_CH4SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH4SEL_SHIFT)) & FTM_PWMLOAD_CH4SEL_MASK)
AnnaBridge 143:86740a56073b 5891 #define FTM_PWMLOAD_CH5SEL_MASK (0x20U)
AnnaBridge 143:86740a56073b 5892 #define FTM_PWMLOAD_CH5SEL_SHIFT (5U)
AnnaBridge 143:86740a56073b 5893 #define FTM_PWMLOAD_CH5SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH5SEL_SHIFT)) & FTM_PWMLOAD_CH5SEL_MASK)
AnnaBridge 143:86740a56073b 5894 #define FTM_PWMLOAD_CH6SEL_MASK (0x40U)
AnnaBridge 143:86740a56073b 5895 #define FTM_PWMLOAD_CH6SEL_SHIFT (6U)
AnnaBridge 143:86740a56073b 5896 #define FTM_PWMLOAD_CH6SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH6SEL_SHIFT)) & FTM_PWMLOAD_CH6SEL_MASK)
AnnaBridge 143:86740a56073b 5897 #define FTM_PWMLOAD_CH7SEL_MASK (0x80U)
AnnaBridge 143:86740a56073b 5898 #define FTM_PWMLOAD_CH7SEL_SHIFT (7U)
AnnaBridge 143:86740a56073b 5899 #define FTM_PWMLOAD_CH7SEL(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_CH7SEL_SHIFT)) & FTM_PWMLOAD_CH7SEL_MASK)
AnnaBridge 143:86740a56073b 5900 #define FTM_PWMLOAD_LDOK_MASK (0x200U)
AnnaBridge 143:86740a56073b 5901 #define FTM_PWMLOAD_LDOK_SHIFT (9U)
AnnaBridge 143:86740a56073b 5902 #define FTM_PWMLOAD_LDOK(x) (((uint32_t)(((uint32_t)(x)) << FTM_PWMLOAD_LDOK_SHIFT)) & FTM_PWMLOAD_LDOK_MASK)
AnnaBridge 143:86740a56073b 5903
AnnaBridge 143:86740a56073b 5904
AnnaBridge 143:86740a56073b 5905 /*!
AnnaBridge 143:86740a56073b 5906 * @}
AnnaBridge 143:86740a56073b 5907 */ /* end of group FTM_Register_Masks */
AnnaBridge 143:86740a56073b 5908
AnnaBridge 143:86740a56073b 5909
AnnaBridge 143:86740a56073b 5910 /* FTM - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 5911 /** Peripheral FTM0 base address */
AnnaBridge 143:86740a56073b 5912 #define FTM0_BASE (0x40038000u)
AnnaBridge 143:86740a56073b 5913 /** Peripheral FTM0 base pointer */
AnnaBridge 143:86740a56073b 5914 #define FTM0 ((FTM_Type *)FTM0_BASE)
AnnaBridge 143:86740a56073b 5915 /** Peripheral FTM1 base address */
AnnaBridge 143:86740a56073b 5916 #define FTM1_BASE (0x40039000u)
AnnaBridge 143:86740a56073b 5917 /** Peripheral FTM1 base pointer */
AnnaBridge 143:86740a56073b 5918 #define FTM1 ((FTM_Type *)FTM1_BASE)
AnnaBridge 143:86740a56073b 5919 /** Peripheral FTM2 base address */
AnnaBridge 143:86740a56073b 5920 #define FTM2_BASE (0x4003A000u)
AnnaBridge 143:86740a56073b 5921 /** Peripheral FTM2 base pointer */
AnnaBridge 143:86740a56073b 5922 #define FTM2 ((FTM_Type *)FTM2_BASE)
AnnaBridge 143:86740a56073b 5923 /** Peripheral FTM3 base address */
AnnaBridge 143:86740a56073b 5924 #define FTM3_BASE (0x400B9000u)
AnnaBridge 143:86740a56073b 5925 /** Peripheral FTM3 base pointer */
AnnaBridge 143:86740a56073b 5926 #define FTM3 ((FTM_Type *)FTM3_BASE)
AnnaBridge 143:86740a56073b 5927 /** Array initializer of FTM peripheral base addresses */
AnnaBridge 143:86740a56073b 5928 #define FTM_BASE_ADDRS { FTM0_BASE, FTM1_BASE, FTM2_BASE, FTM3_BASE }
AnnaBridge 143:86740a56073b 5929 /** Array initializer of FTM peripheral base pointers */
AnnaBridge 143:86740a56073b 5930 #define FTM_BASE_PTRS { FTM0, FTM1, FTM2, FTM3 }
AnnaBridge 143:86740a56073b 5931 /** Interrupt vectors for the FTM peripheral type */
AnnaBridge 143:86740a56073b 5932 #define FTM_IRQS { FTM0_IRQn, FTM1_IRQn, FTM2_IRQn, FTM3_IRQn }
AnnaBridge 143:86740a56073b 5933
AnnaBridge 143:86740a56073b 5934 /*!
AnnaBridge 143:86740a56073b 5935 * @}
AnnaBridge 143:86740a56073b 5936 */ /* end of group FTM_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 5937
AnnaBridge 143:86740a56073b 5938
AnnaBridge 143:86740a56073b 5939 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 5940 -- GPIO Peripheral Access Layer
AnnaBridge 143:86740a56073b 5941 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 5942
AnnaBridge 143:86740a56073b 5943 /*!
AnnaBridge 143:86740a56073b 5944 * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
AnnaBridge 143:86740a56073b 5945 * @{
AnnaBridge 143:86740a56073b 5946 */
AnnaBridge 143:86740a56073b 5947
AnnaBridge 143:86740a56073b 5948 /** GPIO - Register Layout Typedef */
AnnaBridge 143:86740a56073b 5949 typedef struct {
AnnaBridge 143:86740a56073b 5950 __IO uint32_t PDOR; /**< Port Data Output Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 5951 __O uint32_t PSOR; /**< Port Set Output Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 5952 __O uint32_t PCOR; /**< Port Clear Output Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 5953 __O uint32_t PTOR; /**< Port Toggle Output Register, offset: 0xC */
AnnaBridge 143:86740a56073b 5954 __I uint32_t PDIR; /**< Port Data Input Register, offset: 0x10 */
AnnaBridge 143:86740a56073b 5955 __IO uint32_t PDDR; /**< Port Data Direction Register, offset: 0x14 */
AnnaBridge 143:86740a56073b 5956 } GPIO_Type;
AnnaBridge 143:86740a56073b 5957
AnnaBridge 143:86740a56073b 5958 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 5959 -- GPIO Register Masks
AnnaBridge 143:86740a56073b 5960 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 5961
AnnaBridge 143:86740a56073b 5962 /*!
AnnaBridge 143:86740a56073b 5963 * @addtogroup GPIO_Register_Masks GPIO Register Masks
AnnaBridge 143:86740a56073b 5964 * @{
AnnaBridge 143:86740a56073b 5965 */
AnnaBridge 143:86740a56073b 5966
AnnaBridge 143:86740a56073b 5967 /*! @name PDOR - Port Data Output Register */
AnnaBridge 143:86740a56073b 5968 #define GPIO_PDOR_PDO_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5969 #define GPIO_PDOR_PDO_SHIFT (0U)
AnnaBridge 143:86740a56073b 5970 #define GPIO_PDOR_PDO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDOR_PDO_SHIFT)) & GPIO_PDOR_PDO_MASK)
AnnaBridge 143:86740a56073b 5971
AnnaBridge 143:86740a56073b 5972 /*! @name PSOR - Port Set Output Register */
AnnaBridge 143:86740a56073b 5973 #define GPIO_PSOR_PTSO_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5974 #define GPIO_PSOR_PTSO_SHIFT (0U)
AnnaBridge 143:86740a56073b 5975 #define GPIO_PSOR_PTSO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PSOR_PTSO_SHIFT)) & GPIO_PSOR_PTSO_MASK)
AnnaBridge 143:86740a56073b 5976
AnnaBridge 143:86740a56073b 5977 /*! @name PCOR - Port Clear Output Register */
AnnaBridge 143:86740a56073b 5978 #define GPIO_PCOR_PTCO_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5979 #define GPIO_PCOR_PTCO_SHIFT (0U)
AnnaBridge 143:86740a56073b 5980 #define GPIO_PCOR_PTCO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PCOR_PTCO_SHIFT)) & GPIO_PCOR_PTCO_MASK)
AnnaBridge 143:86740a56073b 5981
AnnaBridge 143:86740a56073b 5982 /*! @name PTOR - Port Toggle Output Register */
AnnaBridge 143:86740a56073b 5983 #define GPIO_PTOR_PTTO_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5984 #define GPIO_PTOR_PTTO_SHIFT (0U)
AnnaBridge 143:86740a56073b 5985 #define GPIO_PTOR_PTTO(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PTOR_PTTO_SHIFT)) & GPIO_PTOR_PTTO_MASK)
AnnaBridge 143:86740a56073b 5986
AnnaBridge 143:86740a56073b 5987 /*! @name PDIR - Port Data Input Register */
AnnaBridge 143:86740a56073b 5988 #define GPIO_PDIR_PDI_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5989 #define GPIO_PDIR_PDI_SHIFT (0U)
AnnaBridge 143:86740a56073b 5990 #define GPIO_PDIR_PDI(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDIR_PDI_SHIFT)) & GPIO_PDIR_PDI_MASK)
AnnaBridge 143:86740a56073b 5991
AnnaBridge 143:86740a56073b 5992 /*! @name PDDR - Port Data Direction Register */
AnnaBridge 143:86740a56073b 5993 #define GPIO_PDDR_PDD_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 5994 #define GPIO_PDDR_PDD_SHIFT (0U)
AnnaBridge 143:86740a56073b 5995 #define GPIO_PDDR_PDD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PDDR_PDD_SHIFT)) & GPIO_PDDR_PDD_MASK)
AnnaBridge 143:86740a56073b 5996
AnnaBridge 143:86740a56073b 5997
AnnaBridge 143:86740a56073b 5998 /*!
AnnaBridge 143:86740a56073b 5999 * @}
AnnaBridge 143:86740a56073b 6000 */ /* end of group GPIO_Register_Masks */
AnnaBridge 143:86740a56073b 6001
AnnaBridge 143:86740a56073b 6002
AnnaBridge 143:86740a56073b 6003 /* GPIO - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 6004 /** Peripheral GPIOA base address */
AnnaBridge 143:86740a56073b 6005 #define GPIOA_BASE (0x400FF000u)
AnnaBridge 143:86740a56073b 6006 /** Peripheral GPIOA base pointer */
AnnaBridge 143:86740a56073b 6007 #define GPIOA ((GPIO_Type *)GPIOA_BASE)
AnnaBridge 143:86740a56073b 6008 /** Peripheral GPIOB base address */
AnnaBridge 143:86740a56073b 6009 #define GPIOB_BASE (0x400FF040u)
AnnaBridge 143:86740a56073b 6010 /** Peripheral GPIOB base pointer */
AnnaBridge 143:86740a56073b 6011 #define GPIOB ((GPIO_Type *)GPIOB_BASE)
AnnaBridge 143:86740a56073b 6012 /** Peripheral GPIOC base address */
AnnaBridge 143:86740a56073b 6013 #define GPIOC_BASE (0x400FF080u)
AnnaBridge 143:86740a56073b 6014 /** Peripheral GPIOC base pointer */
AnnaBridge 143:86740a56073b 6015 #define GPIOC ((GPIO_Type *)GPIOC_BASE)
AnnaBridge 143:86740a56073b 6016 /** Peripheral GPIOD base address */
AnnaBridge 143:86740a56073b 6017 #define GPIOD_BASE (0x400FF0C0u)
AnnaBridge 143:86740a56073b 6018 /** Peripheral GPIOD base pointer */
AnnaBridge 143:86740a56073b 6019 #define GPIOD ((GPIO_Type *)GPIOD_BASE)
AnnaBridge 143:86740a56073b 6020 /** Peripheral GPIOE base address */
AnnaBridge 143:86740a56073b 6021 #define GPIOE_BASE (0x400FF100u)
AnnaBridge 143:86740a56073b 6022 /** Peripheral GPIOE base pointer */
AnnaBridge 143:86740a56073b 6023 #define GPIOE ((GPIO_Type *)GPIOE_BASE)
AnnaBridge 143:86740a56073b 6024 /** Array initializer of GPIO peripheral base addresses */
AnnaBridge 143:86740a56073b 6025 #define GPIO_BASE_ADDRS { GPIOA_BASE, GPIOB_BASE, GPIOC_BASE, GPIOD_BASE, GPIOE_BASE }
AnnaBridge 143:86740a56073b 6026 /** Array initializer of GPIO peripheral base pointers */
AnnaBridge 143:86740a56073b 6027 #define GPIO_BASE_PTRS { GPIOA, GPIOB, GPIOC, GPIOD, GPIOE }
AnnaBridge 143:86740a56073b 6028
AnnaBridge 143:86740a56073b 6029 /*!
AnnaBridge 143:86740a56073b 6030 * @}
AnnaBridge 143:86740a56073b 6031 */ /* end of group GPIO_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 6032
AnnaBridge 143:86740a56073b 6033
AnnaBridge 143:86740a56073b 6034 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6035 -- I2C Peripheral Access Layer
AnnaBridge 143:86740a56073b 6036 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6037
AnnaBridge 143:86740a56073b 6038 /*!
AnnaBridge 143:86740a56073b 6039 * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
AnnaBridge 143:86740a56073b 6040 * @{
AnnaBridge 143:86740a56073b 6041 */
AnnaBridge 143:86740a56073b 6042
AnnaBridge 143:86740a56073b 6043 /** I2C - Register Layout Typedef */
AnnaBridge 143:86740a56073b 6044 typedef struct {
AnnaBridge 143:86740a56073b 6045 __IO uint8_t A1; /**< I2C Address Register 1, offset: 0x0 */
AnnaBridge 143:86740a56073b 6046 __IO uint8_t F; /**< I2C Frequency Divider register, offset: 0x1 */
AnnaBridge 143:86740a56073b 6047 __IO uint8_t C1; /**< I2C Control Register 1, offset: 0x2 */
AnnaBridge 143:86740a56073b 6048 __IO uint8_t S; /**< I2C Status register, offset: 0x3 */
AnnaBridge 143:86740a56073b 6049 __IO uint8_t D; /**< I2C Data I/O register, offset: 0x4 */
AnnaBridge 143:86740a56073b 6050 __IO uint8_t C2; /**< I2C Control Register 2, offset: 0x5 */
AnnaBridge 143:86740a56073b 6051 __IO uint8_t FLT; /**< I2C Programmable Input Glitch Filter register, offset: 0x6 */
AnnaBridge 143:86740a56073b 6052 __IO uint8_t RA; /**< I2C Range Address register, offset: 0x7 */
AnnaBridge 143:86740a56073b 6053 __IO uint8_t SMB; /**< I2C SMBus Control and Status register, offset: 0x8 */
AnnaBridge 143:86740a56073b 6054 __IO uint8_t A2; /**< I2C Address Register 2, offset: 0x9 */
AnnaBridge 143:86740a56073b 6055 __IO uint8_t SLTH; /**< I2C SCL Low Timeout Register High, offset: 0xA */
AnnaBridge 143:86740a56073b 6056 __IO uint8_t SLTL; /**< I2C SCL Low Timeout Register Low, offset: 0xB */
AnnaBridge 143:86740a56073b 6057 } I2C_Type;
AnnaBridge 143:86740a56073b 6058
AnnaBridge 143:86740a56073b 6059 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6060 -- I2C Register Masks
AnnaBridge 143:86740a56073b 6061 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6062
AnnaBridge 143:86740a56073b 6063 /*!
AnnaBridge 143:86740a56073b 6064 * @addtogroup I2C_Register_Masks I2C Register Masks
AnnaBridge 143:86740a56073b 6065 * @{
AnnaBridge 143:86740a56073b 6066 */
AnnaBridge 143:86740a56073b 6067
AnnaBridge 143:86740a56073b 6068 /*! @name A1 - I2C Address Register 1 */
AnnaBridge 143:86740a56073b 6069 #define I2C_A1_AD_MASK (0xFEU)
AnnaBridge 143:86740a56073b 6070 #define I2C_A1_AD_SHIFT (1U)
AnnaBridge 143:86740a56073b 6071 #define I2C_A1_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A1_AD_SHIFT)) & I2C_A1_AD_MASK)
AnnaBridge 143:86740a56073b 6072
AnnaBridge 143:86740a56073b 6073 /*! @name F - I2C Frequency Divider register */
AnnaBridge 143:86740a56073b 6074 #define I2C_F_ICR_MASK (0x3FU)
AnnaBridge 143:86740a56073b 6075 #define I2C_F_ICR_SHIFT (0U)
AnnaBridge 143:86740a56073b 6076 #define I2C_F_ICR(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_ICR_SHIFT)) & I2C_F_ICR_MASK)
AnnaBridge 143:86740a56073b 6077 #define I2C_F_MULT_MASK (0xC0U)
AnnaBridge 143:86740a56073b 6078 #define I2C_F_MULT_SHIFT (6U)
AnnaBridge 143:86740a56073b 6079 #define I2C_F_MULT(x) (((uint8_t)(((uint8_t)(x)) << I2C_F_MULT_SHIFT)) & I2C_F_MULT_MASK)
AnnaBridge 143:86740a56073b 6080
AnnaBridge 143:86740a56073b 6081 /*! @name C1 - I2C Control Register 1 */
AnnaBridge 143:86740a56073b 6082 #define I2C_C1_DMAEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 6083 #define I2C_C1_DMAEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 6084 #define I2C_C1_DMAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_DMAEN_SHIFT)) & I2C_C1_DMAEN_MASK)
AnnaBridge 143:86740a56073b 6085 #define I2C_C1_WUEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 6086 #define I2C_C1_WUEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 6087 #define I2C_C1_WUEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_WUEN_SHIFT)) & I2C_C1_WUEN_MASK)
AnnaBridge 143:86740a56073b 6088 #define I2C_C1_RSTA_MASK (0x4U)
AnnaBridge 143:86740a56073b 6089 #define I2C_C1_RSTA_SHIFT (2U)
AnnaBridge 143:86740a56073b 6090 #define I2C_C1_RSTA(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_RSTA_SHIFT)) & I2C_C1_RSTA_MASK)
AnnaBridge 143:86740a56073b 6091 #define I2C_C1_TXAK_MASK (0x8U)
AnnaBridge 143:86740a56073b 6092 #define I2C_C1_TXAK_SHIFT (3U)
AnnaBridge 143:86740a56073b 6093 #define I2C_C1_TXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TXAK_SHIFT)) & I2C_C1_TXAK_MASK)
AnnaBridge 143:86740a56073b 6094 #define I2C_C1_TX_MASK (0x10U)
AnnaBridge 143:86740a56073b 6095 #define I2C_C1_TX_SHIFT (4U)
AnnaBridge 143:86740a56073b 6096 #define I2C_C1_TX(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_TX_SHIFT)) & I2C_C1_TX_MASK)
AnnaBridge 143:86740a56073b 6097 #define I2C_C1_MST_MASK (0x20U)
AnnaBridge 143:86740a56073b 6098 #define I2C_C1_MST_SHIFT (5U)
AnnaBridge 143:86740a56073b 6099 #define I2C_C1_MST(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_MST_SHIFT)) & I2C_C1_MST_MASK)
AnnaBridge 143:86740a56073b 6100 #define I2C_C1_IICIE_MASK (0x40U)
AnnaBridge 143:86740a56073b 6101 #define I2C_C1_IICIE_SHIFT (6U)
AnnaBridge 143:86740a56073b 6102 #define I2C_C1_IICIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICIE_SHIFT)) & I2C_C1_IICIE_MASK)
AnnaBridge 143:86740a56073b 6103 #define I2C_C1_IICEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 6104 #define I2C_C1_IICEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 6105 #define I2C_C1_IICEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C1_IICEN_SHIFT)) & I2C_C1_IICEN_MASK)
AnnaBridge 143:86740a56073b 6106
AnnaBridge 143:86740a56073b 6107 /*! @name S - I2C Status register */
AnnaBridge 143:86740a56073b 6108 #define I2C_S_RXAK_MASK (0x1U)
AnnaBridge 143:86740a56073b 6109 #define I2C_S_RXAK_SHIFT (0U)
AnnaBridge 143:86740a56073b 6110 #define I2C_S_RXAK(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RXAK_SHIFT)) & I2C_S_RXAK_MASK)
AnnaBridge 143:86740a56073b 6111 #define I2C_S_IICIF_MASK (0x2U)
AnnaBridge 143:86740a56073b 6112 #define I2C_S_IICIF_SHIFT (1U)
AnnaBridge 143:86740a56073b 6113 #define I2C_S_IICIF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IICIF_SHIFT)) & I2C_S_IICIF_MASK)
AnnaBridge 143:86740a56073b 6114 #define I2C_S_SRW_MASK (0x4U)
AnnaBridge 143:86740a56073b 6115 #define I2C_S_SRW_SHIFT (2U)
AnnaBridge 143:86740a56073b 6116 #define I2C_S_SRW(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_SRW_SHIFT)) & I2C_S_SRW_MASK)
AnnaBridge 143:86740a56073b 6117 #define I2C_S_RAM_MASK (0x8U)
AnnaBridge 143:86740a56073b 6118 #define I2C_S_RAM_SHIFT (3U)
AnnaBridge 143:86740a56073b 6119 #define I2C_S_RAM(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_RAM_SHIFT)) & I2C_S_RAM_MASK)
AnnaBridge 143:86740a56073b 6120 #define I2C_S_ARBL_MASK (0x10U)
AnnaBridge 143:86740a56073b 6121 #define I2C_S_ARBL_SHIFT (4U)
AnnaBridge 143:86740a56073b 6122 #define I2C_S_ARBL(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_ARBL_SHIFT)) & I2C_S_ARBL_MASK)
AnnaBridge 143:86740a56073b 6123 #define I2C_S_BUSY_MASK (0x20U)
AnnaBridge 143:86740a56073b 6124 #define I2C_S_BUSY_SHIFT (5U)
AnnaBridge 143:86740a56073b 6125 #define I2C_S_BUSY(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_BUSY_SHIFT)) & I2C_S_BUSY_MASK)
AnnaBridge 143:86740a56073b 6126 #define I2C_S_IAAS_MASK (0x40U)
AnnaBridge 143:86740a56073b 6127 #define I2C_S_IAAS_SHIFT (6U)
AnnaBridge 143:86740a56073b 6128 #define I2C_S_IAAS(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_IAAS_SHIFT)) & I2C_S_IAAS_MASK)
AnnaBridge 143:86740a56073b 6129 #define I2C_S_TCF_MASK (0x80U)
AnnaBridge 143:86740a56073b 6130 #define I2C_S_TCF_SHIFT (7U)
AnnaBridge 143:86740a56073b 6131 #define I2C_S_TCF(x) (((uint8_t)(((uint8_t)(x)) << I2C_S_TCF_SHIFT)) & I2C_S_TCF_MASK)
AnnaBridge 143:86740a56073b 6132
AnnaBridge 143:86740a56073b 6133 /*! @name D - I2C Data I/O register */
AnnaBridge 143:86740a56073b 6134 #define I2C_D_DATA_MASK (0xFFU)
AnnaBridge 143:86740a56073b 6135 #define I2C_D_DATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 6136 #define I2C_D_DATA(x) (((uint8_t)(((uint8_t)(x)) << I2C_D_DATA_SHIFT)) & I2C_D_DATA_MASK)
AnnaBridge 143:86740a56073b 6137
AnnaBridge 143:86740a56073b 6138 /*! @name C2 - I2C Control Register 2 */
AnnaBridge 143:86740a56073b 6139 #define I2C_C2_AD_MASK (0x7U)
AnnaBridge 143:86740a56073b 6140 #define I2C_C2_AD_SHIFT (0U)
AnnaBridge 143:86740a56073b 6141 #define I2C_C2_AD(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_AD_SHIFT)) & I2C_C2_AD_MASK)
AnnaBridge 143:86740a56073b 6142 #define I2C_C2_RMEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 6143 #define I2C_C2_RMEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 6144 #define I2C_C2_RMEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_RMEN_SHIFT)) & I2C_C2_RMEN_MASK)
AnnaBridge 143:86740a56073b 6145 #define I2C_C2_SBRC_MASK (0x10U)
AnnaBridge 143:86740a56073b 6146 #define I2C_C2_SBRC_SHIFT (4U)
AnnaBridge 143:86740a56073b 6147 #define I2C_C2_SBRC(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_SBRC_SHIFT)) & I2C_C2_SBRC_MASK)
AnnaBridge 143:86740a56073b 6148 #define I2C_C2_HDRS_MASK (0x20U)
AnnaBridge 143:86740a56073b 6149 #define I2C_C2_HDRS_SHIFT (5U)
AnnaBridge 143:86740a56073b 6150 #define I2C_C2_HDRS(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_HDRS_SHIFT)) & I2C_C2_HDRS_MASK)
AnnaBridge 143:86740a56073b 6151 #define I2C_C2_ADEXT_MASK (0x40U)
AnnaBridge 143:86740a56073b 6152 #define I2C_C2_ADEXT_SHIFT (6U)
AnnaBridge 143:86740a56073b 6153 #define I2C_C2_ADEXT(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_ADEXT_SHIFT)) & I2C_C2_ADEXT_MASK)
AnnaBridge 143:86740a56073b 6154 #define I2C_C2_GCAEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 6155 #define I2C_C2_GCAEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 6156 #define I2C_C2_GCAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_C2_GCAEN_SHIFT)) & I2C_C2_GCAEN_MASK)
AnnaBridge 143:86740a56073b 6157
AnnaBridge 143:86740a56073b 6158 /*! @name FLT - I2C Programmable Input Glitch Filter register */
AnnaBridge 143:86740a56073b 6159 #define I2C_FLT_FLT_MASK (0xFU)
AnnaBridge 143:86740a56073b 6160 #define I2C_FLT_FLT_SHIFT (0U)
AnnaBridge 143:86740a56073b 6161 #define I2C_FLT_FLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_FLT_SHIFT)) & I2C_FLT_FLT_MASK)
AnnaBridge 143:86740a56073b 6162 #define I2C_FLT_STARTF_MASK (0x10U)
AnnaBridge 143:86740a56073b 6163 #define I2C_FLT_STARTF_SHIFT (4U)
AnnaBridge 143:86740a56073b 6164 #define I2C_FLT_STARTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STARTF_SHIFT)) & I2C_FLT_STARTF_MASK)
AnnaBridge 143:86740a56073b 6165 #define I2C_FLT_SSIE_MASK (0x20U)
AnnaBridge 143:86740a56073b 6166 #define I2C_FLT_SSIE_SHIFT (5U)
AnnaBridge 143:86740a56073b 6167 #define I2C_FLT_SSIE(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SSIE_SHIFT)) & I2C_FLT_SSIE_MASK)
AnnaBridge 143:86740a56073b 6168 #define I2C_FLT_STOPF_MASK (0x40U)
AnnaBridge 143:86740a56073b 6169 #define I2C_FLT_STOPF_SHIFT (6U)
AnnaBridge 143:86740a56073b 6170 #define I2C_FLT_STOPF(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_STOPF_SHIFT)) & I2C_FLT_STOPF_MASK)
AnnaBridge 143:86740a56073b 6171 #define I2C_FLT_SHEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 6172 #define I2C_FLT_SHEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 6173 #define I2C_FLT_SHEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_FLT_SHEN_SHIFT)) & I2C_FLT_SHEN_MASK)
AnnaBridge 143:86740a56073b 6174
AnnaBridge 143:86740a56073b 6175 /*! @name RA - I2C Range Address register */
AnnaBridge 143:86740a56073b 6176 #define I2C_RA_RAD_MASK (0xFEU)
AnnaBridge 143:86740a56073b 6177 #define I2C_RA_RAD_SHIFT (1U)
AnnaBridge 143:86740a56073b 6178 #define I2C_RA_RAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_RA_RAD_SHIFT)) & I2C_RA_RAD_MASK)
AnnaBridge 143:86740a56073b 6179
AnnaBridge 143:86740a56073b 6180 /*! @name SMB - I2C SMBus Control and Status register */
AnnaBridge 143:86740a56073b 6181 #define I2C_SMB_SHTF2IE_MASK (0x1U)
AnnaBridge 143:86740a56073b 6182 #define I2C_SMB_SHTF2IE_SHIFT (0U)
AnnaBridge 143:86740a56073b 6183 #define I2C_SMB_SHTF2IE(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2IE_SHIFT)) & I2C_SMB_SHTF2IE_MASK)
AnnaBridge 143:86740a56073b 6184 #define I2C_SMB_SHTF2_MASK (0x2U)
AnnaBridge 143:86740a56073b 6185 #define I2C_SMB_SHTF2_SHIFT (1U)
AnnaBridge 143:86740a56073b 6186 #define I2C_SMB_SHTF2(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF2_SHIFT)) & I2C_SMB_SHTF2_MASK)
AnnaBridge 143:86740a56073b 6187 #define I2C_SMB_SHTF1_MASK (0x4U)
AnnaBridge 143:86740a56073b 6188 #define I2C_SMB_SHTF1_SHIFT (2U)
AnnaBridge 143:86740a56073b 6189 #define I2C_SMB_SHTF1(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SHTF1_SHIFT)) & I2C_SMB_SHTF1_MASK)
AnnaBridge 143:86740a56073b 6190 #define I2C_SMB_SLTF_MASK (0x8U)
AnnaBridge 143:86740a56073b 6191 #define I2C_SMB_SLTF_SHIFT (3U)
AnnaBridge 143:86740a56073b 6192 #define I2C_SMB_SLTF(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SLTF_SHIFT)) & I2C_SMB_SLTF_MASK)
AnnaBridge 143:86740a56073b 6193 #define I2C_SMB_TCKSEL_MASK (0x10U)
AnnaBridge 143:86740a56073b 6194 #define I2C_SMB_TCKSEL_SHIFT (4U)
AnnaBridge 143:86740a56073b 6195 #define I2C_SMB_TCKSEL(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_TCKSEL_SHIFT)) & I2C_SMB_TCKSEL_MASK)
AnnaBridge 143:86740a56073b 6196 #define I2C_SMB_SIICAEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 6197 #define I2C_SMB_SIICAEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 6198 #define I2C_SMB_SIICAEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_SIICAEN_SHIFT)) & I2C_SMB_SIICAEN_MASK)
AnnaBridge 143:86740a56073b 6199 #define I2C_SMB_ALERTEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 6200 #define I2C_SMB_ALERTEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 6201 #define I2C_SMB_ALERTEN(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_ALERTEN_SHIFT)) & I2C_SMB_ALERTEN_MASK)
AnnaBridge 143:86740a56073b 6202 #define I2C_SMB_FACK_MASK (0x80U)
AnnaBridge 143:86740a56073b 6203 #define I2C_SMB_FACK_SHIFT (7U)
AnnaBridge 143:86740a56073b 6204 #define I2C_SMB_FACK(x) (((uint8_t)(((uint8_t)(x)) << I2C_SMB_FACK_SHIFT)) & I2C_SMB_FACK_MASK)
AnnaBridge 143:86740a56073b 6205
AnnaBridge 143:86740a56073b 6206 /*! @name A2 - I2C Address Register 2 */
AnnaBridge 143:86740a56073b 6207 #define I2C_A2_SAD_MASK (0xFEU)
AnnaBridge 143:86740a56073b 6208 #define I2C_A2_SAD_SHIFT (1U)
AnnaBridge 143:86740a56073b 6209 #define I2C_A2_SAD(x) (((uint8_t)(((uint8_t)(x)) << I2C_A2_SAD_SHIFT)) & I2C_A2_SAD_MASK)
AnnaBridge 143:86740a56073b 6210
AnnaBridge 143:86740a56073b 6211 /*! @name SLTH - I2C SCL Low Timeout Register High */
AnnaBridge 143:86740a56073b 6212 #define I2C_SLTH_SSLT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 6213 #define I2C_SLTH_SSLT_SHIFT (0U)
AnnaBridge 143:86740a56073b 6214 #define I2C_SLTH_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTH_SSLT_SHIFT)) & I2C_SLTH_SSLT_MASK)
AnnaBridge 143:86740a56073b 6215
AnnaBridge 143:86740a56073b 6216 /*! @name SLTL - I2C SCL Low Timeout Register Low */
AnnaBridge 143:86740a56073b 6217 #define I2C_SLTL_SSLT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 6218 #define I2C_SLTL_SSLT_SHIFT (0U)
AnnaBridge 143:86740a56073b 6219 #define I2C_SLTL_SSLT(x) (((uint8_t)(((uint8_t)(x)) << I2C_SLTL_SSLT_SHIFT)) & I2C_SLTL_SSLT_MASK)
AnnaBridge 143:86740a56073b 6220
AnnaBridge 143:86740a56073b 6221
AnnaBridge 143:86740a56073b 6222 /*!
AnnaBridge 143:86740a56073b 6223 * @}
AnnaBridge 143:86740a56073b 6224 */ /* end of group I2C_Register_Masks */
AnnaBridge 143:86740a56073b 6225
AnnaBridge 143:86740a56073b 6226
AnnaBridge 143:86740a56073b 6227 /* I2C - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 6228 /** Peripheral I2C0 base address */
AnnaBridge 143:86740a56073b 6229 #define I2C0_BASE (0x40066000u)
AnnaBridge 143:86740a56073b 6230 /** Peripheral I2C0 base pointer */
AnnaBridge 143:86740a56073b 6231 #define I2C0 ((I2C_Type *)I2C0_BASE)
AnnaBridge 143:86740a56073b 6232 /** Peripheral I2C1 base address */
AnnaBridge 143:86740a56073b 6233 #define I2C1_BASE (0x40067000u)
AnnaBridge 143:86740a56073b 6234 /** Peripheral I2C1 base pointer */
AnnaBridge 143:86740a56073b 6235 #define I2C1 ((I2C_Type *)I2C1_BASE)
AnnaBridge 143:86740a56073b 6236 /** Peripheral I2C2 base address */
AnnaBridge 143:86740a56073b 6237 #define I2C2_BASE (0x400E6000u)
AnnaBridge 143:86740a56073b 6238 /** Peripheral I2C2 base pointer */
AnnaBridge 143:86740a56073b 6239 #define I2C2 ((I2C_Type *)I2C2_BASE)
AnnaBridge 143:86740a56073b 6240 /** Array initializer of I2C peripheral base addresses */
AnnaBridge 143:86740a56073b 6241 #define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE }
AnnaBridge 143:86740a56073b 6242 /** Array initializer of I2C peripheral base pointers */
AnnaBridge 143:86740a56073b 6243 #define I2C_BASE_PTRS { I2C0, I2C1, I2C2 }
AnnaBridge 143:86740a56073b 6244 /** Interrupt vectors for the I2C peripheral type */
AnnaBridge 143:86740a56073b 6245 #define I2C_IRQS { I2C0_IRQn, I2C1_IRQn, I2C2_IRQn }
AnnaBridge 143:86740a56073b 6246
AnnaBridge 143:86740a56073b 6247 /*!
AnnaBridge 143:86740a56073b 6248 * @}
AnnaBridge 143:86740a56073b 6249 */ /* end of group I2C_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 6250
AnnaBridge 143:86740a56073b 6251
AnnaBridge 143:86740a56073b 6252 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6253 -- I2S Peripheral Access Layer
AnnaBridge 143:86740a56073b 6254 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6255
AnnaBridge 143:86740a56073b 6256 /*!
AnnaBridge 143:86740a56073b 6257 * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
AnnaBridge 143:86740a56073b 6258 * @{
AnnaBridge 143:86740a56073b 6259 */
AnnaBridge 143:86740a56073b 6260
AnnaBridge 143:86740a56073b 6261 /** I2S - Register Layout Typedef */
AnnaBridge 143:86740a56073b 6262 typedef struct {
AnnaBridge 143:86740a56073b 6263 __IO uint32_t TCSR; /**< SAI Transmit Control Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 6264 __IO uint32_t TCR1; /**< SAI Transmit Configuration 1 Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 6265 __IO uint32_t TCR2; /**< SAI Transmit Configuration 2 Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 6266 __IO uint32_t TCR3; /**< SAI Transmit Configuration 3 Register, offset: 0xC */
AnnaBridge 143:86740a56073b 6267 __IO uint32_t TCR4; /**< SAI Transmit Configuration 4 Register, offset: 0x10 */
AnnaBridge 143:86740a56073b 6268 __IO uint32_t TCR5; /**< SAI Transmit Configuration 5 Register, offset: 0x14 */
AnnaBridge 143:86740a56073b 6269 uint8_t RESERVED_0[8];
AnnaBridge 143:86740a56073b 6270 __O uint32_t TDR[2]; /**< SAI Transmit Data Register, array offset: 0x20, array step: 0x4 */
AnnaBridge 143:86740a56073b 6271 uint8_t RESERVED_1[24];
AnnaBridge 143:86740a56073b 6272 __I uint32_t TFR[2]; /**< SAI Transmit FIFO Register, array offset: 0x40, array step: 0x4 */
AnnaBridge 143:86740a56073b 6273 uint8_t RESERVED_2[24];
AnnaBridge 143:86740a56073b 6274 __IO uint32_t TMR; /**< SAI Transmit Mask Register, offset: 0x60 */
AnnaBridge 143:86740a56073b 6275 uint8_t RESERVED_3[28];
AnnaBridge 143:86740a56073b 6276 __IO uint32_t RCSR; /**< SAI Receive Control Register, offset: 0x80 */
AnnaBridge 143:86740a56073b 6277 __IO uint32_t RCR1; /**< SAI Receive Configuration 1 Register, offset: 0x84 */
AnnaBridge 143:86740a56073b 6278 __IO uint32_t RCR2; /**< SAI Receive Configuration 2 Register, offset: 0x88 */
AnnaBridge 143:86740a56073b 6279 __IO uint32_t RCR3; /**< SAI Receive Configuration 3 Register, offset: 0x8C */
AnnaBridge 143:86740a56073b 6280 __IO uint32_t RCR4; /**< SAI Receive Configuration 4 Register, offset: 0x90 */
AnnaBridge 143:86740a56073b 6281 __IO uint32_t RCR5; /**< SAI Receive Configuration 5 Register, offset: 0x94 */
AnnaBridge 143:86740a56073b 6282 uint8_t RESERVED_4[8];
AnnaBridge 143:86740a56073b 6283 __I uint32_t RDR[2]; /**< SAI Receive Data Register, array offset: 0xA0, array step: 0x4 */
AnnaBridge 143:86740a56073b 6284 uint8_t RESERVED_5[24];
AnnaBridge 143:86740a56073b 6285 __I uint32_t RFR[2]; /**< SAI Receive FIFO Register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 143:86740a56073b 6286 uint8_t RESERVED_6[24];
AnnaBridge 143:86740a56073b 6287 __IO uint32_t RMR; /**< SAI Receive Mask Register, offset: 0xE0 */
AnnaBridge 143:86740a56073b 6288 uint8_t RESERVED_7[28];
AnnaBridge 143:86740a56073b 6289 __IO uint32_t MCR; /**< SAI MCLK Control Register, offset: 0x100 */
AnnaBridge 143:86740a56073b 6290 __IO uint32_t MDR; /**< SAI MCLK Divide Register, offset: 0x104 */
AnnaBridge 143:86740a56073b 6291 } I2S_Type;
AnnaBridge 143:86740a56073b 6292
AnnaBridge 143:86740a56073b 6293 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6294 -- I2S Register Masks
AnnaBridge 143:86740a56073b 6295 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6296
AnnaBridge 143:86740a56073b 6297 /*!
AnnaBridge 143:86740a56073b 6298 * @addtogroup I2S_Register_Masks I2S Register Masks
AnnaBridge 143:86740a56073b 6299 * @{
AnnaBridge 143:86740a56073b 6300 */
AnnaBridge 143:86740a56073b 6301
AnnaBridge 143:86740a56073b 6302 /*! @name TCSR - SAI Transmit Control Register */
AnnaBridge 143:86740a56073b 6303 #define I2S_TCSR_FRDE_MASK (0x1U)
AnnaBridge 143:86740a56073b 6304 #define I2S_TCSR_FRDE_SHIFT (0U)
AnnaBridge 143:86740a56073b 6305 #define I2S_TCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRDE_SHIFT)) & I2S_TCSR_FRDE_MASK)
AnnaBridge 143:86740a56073b 6306 #define I2S_TCSR_FWDE_MASK (0x2U)
AnnaBridge 143:86740a56073b 6307 #define I2S_TCSR_FWDE_SHIFT (1U)
AnnaBridge 143:86740a56073b 6308 #define I2S_TCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWDE_SHIFT)) & I2S_TCSR_FWDE_MASK)
AnnaBridge 143:86740a56073b 6309 #define I2S_TCSR_FRIE_MASK (0x100U)
AnnaBridge 143:86740a56073b 6310 #define I2S_TCSR_FRIE_SHIFT (8U)
AnnaBridge 143:86740a56073b 6311 #define I2S_TCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRIE_SHIFT)) & I2S_TCSR_FRIE_MASK)
AnnaBridge 143:86740a56073b 6312 #define I2S_TCSR_FWIE_MASK (0x200U)
AnnaBridge 143:86740a56073b 6313 #define I2S_TCSR_FWIE_SHIFT (9U)
AnnaBridge 143:86740a56073b 6314 #define I2S_TCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWIE_SHIFT)) & I2S_TCSR_FWIE_MASK)
AnnaBridge 143:86740a56073b 6315 #define I2S_TCSR_FEIE_MASK (0x400U)
AnnaBridge 143:86740a56073b 6316 #define I2S_TCSR_FEIE_SHIFT (10U)
AnnaBridge 143:86740a56073b 6317 #define I2S_TCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEIE_SHIFT)) & I2S_TCSR_FEIE_MASK)
AnnaBridge 143:86740a56073b 6318 #define I2S_TCSR_SEIE_MASK (0x800U)
AnnaBridge 143:86740a56073b 6319 #define I2S_TCSR_SEIE_SHIFT (11U)
AnnaBridge 143:86740a56073b 6320 #define I2S_TCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEIE_SHIFT)) & I2S_TCSR_SEIE_MASK)
AnnaBridge 143:86740a56073b 6321 #define I2S_TCSR_WSIE_MASK (0x1000U)
AnnaBridge 143:86740a56073b 6322 #define I2S_TCSR_WSIE_SHIFT (12U)
AnnaBridge 143:86740a56073b 6323 #define I2S_TCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSIE_SHIFT)) & I2S_TCSR_WSIE_MASK)
AnnaBridge 143:86740a56073b 6324 #define I2S_TCSR_FRF_MASK (0x10000U)
AnnaBridge 143:86740a56073b 6325 #define I2S_TCSR_FRF_SHIFT (16U)
AnnaBridge 143:86740a56073b 6326 #define I2S_TCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FRF_SHIFT)) & I2S_TCSR_FRF_MASK)
AnnaBridge 143:86740a56073b 6327 #define I2S_TCSR_FWF_MASK (0x20000U)
AnnaBridge 143:86740a56073b 6328 #define I2S_TCSR_FWF_SHIFT (17U)
AnnaBridge 143:86740a56073b 6329 #define I2S_TCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FWF_SHIFT)) & I2S_TCSR_FWF_MASK)
AnnaBridge 143:86740a56073b 6330 #define I2S_TCSR_FEF_MASK (0x40000U)
AnnaBridge 143:86740a56073b 6331 #define I2S_TCSR_FEF_SHIFT (18U)
AnnaBridge 143:86740a56073b 6332 #define I2S_TCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FEF_SHIFT)) & I2S_TCSR_FEF_MASK)
AnnaBridge 143:86740a56073b 6333 #define I2S_TCSR_SEF_MASK (0x80000U)
AnnaBridge 143:86740a56073b 6334 #define I2S_TCSR_SEF_SHIFT (19U)
AnnaBridge 143:86740a56073b 6335 #define I2S_TCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SEF_SHIFT)) & I2S_TCSR_SEF_MASK)
AnnaBridge 143:86740a56073b 6336 #define I2S_TCSR_WSF_MASK (0x100000U)
AnnaBridge 143:86740a56073b 6337 #define I2S_TCSR_WSF_SHIFT (20U)
AnnaBridge 143:86740a56073b 6338 #define I2S_TCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_WSF_SHIFT)) & I2S_TCSR_WSF_MASK)
AnnaBridge 143:86740a56073b 6339 #define I2S_TCSR_SR_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 6340 #define I2S_TCSR_SR_SHIFT (24U)
AnnaBridge 143:86740a56073b 6341 #define I2S_TCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_SR_SHIFT)) & I2S_TCSR_SR_MASK)
AnnaBridge 143:86740a56073b 6342 #define I2S_TCSR_FR_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 6343 #define I2S_TCSR_FR_SHIFT (25U)
AnnaBridge 143:86740a56073b 6344 #define I2S_TCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_FR_SHIFT)) & I2S_TCSR_FR_MASK)
AnnaBridge 143:86740a56073b 6345 #define I2S_TCSR_BCE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 6346 #define I2S_TCSR_BCE_SHIFT (28U)
AnnaBridge 143:86740a56073b 6347 #define I2S_TCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_BCE_SHIFT)) & I2S_TCSR_BCE_MASK)
AnnaBridge 143:86740a56073b 6348 #define I2S_TCSR_DBGE_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 6349 #define I2S_TCSR_DBGE_SHIFT (29U)
AnnaBridge 143:86740a56073b 6350 #define I2S_TCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_DBGE_SHIFT)) & I2S_TCSR_DBGE_MASK)
AnnaBridge 143:86740a56073b 6351 #define I2S_TCSR_STOPE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 6352 #define I2S_TCSR_STOPE_SHIFT (30U)
AnnaBridge 143:86740a56073b 6353 #define I2S_TCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_STOPE_SHIFT)) & I2S_TCSR_STOPE_MASK)
AnnaBridge 143:86740a56073b 6354 #define I2S_TCSR_TE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 6355 #define I2S_TCSR_TE_SHIFT (31U)
AnnaBridge 143:86740a56073b 6356 #define I2S_TCSR_TE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCSR_TE_SHIFT)) & I2S_TCSR_TE_MASK)
AnnaBridge 143:86740a56073b 6357
AnnaBridge 143:86740a56073b 6358 /*! @name TCR1 - SAI Transmit Configuration 1 Register */
AnnaBridge 143:86740a56073b 6359 #define I2S_TCR1_TFW_MASK (0x7U)
AnnaBridge 143:86740a56073b 6360 #define I2S_TCR1_TFW_SHIFT (0U)
AnnaBridge 143:86740a56073b 6361 #define I2S_TCR1_TFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR1_TFW_SHIFT)) & I2S_TCR1_TFW_MASK)
AnnaBridge 143:86740a56073b 6362
AnnaBridge 143:86740a56073b 6363 /*! @name TCR2 - SAI Transmit Configuration 2 Register */
AnnaBridge 143:86740a56073b 6364 #define I2S_TCR2_DIV_MASK (0xFFU)
AnnaBridge 143:86740a56073b 6365 #define I2S_TCR2_DIV_SHIFT (0U)
AnnaBridge 143:86740a56073b 6366 #define I2S_TCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_DIV_SHIFT)) & I2S_TCR2_DIV_MASK)
AnnaBridge 143:86740a56073b 6367 #define I2S_TCR2_BCD_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 6368 #define I2S_TCR2_BCD_SHIFT (24U)
AnnaBridge 143:86740a56073b 6369 #define I2S_TCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCD_SHIFT)) & I2S_TCR2_BCD_MASK)
AnnaBridge 143:86740a56073b 6370 #define I2S_TCR2_BCP_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 6371 #define I2S_TCR2_BCP_SHIFT (25U)
AnnaBridge 143:86740a56073b 6372 #define I2S_TCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCP_SHIFT)) & I2S_TCR2_BCP_MASK)
AnnaBridge 143:86740a56073b 6373 #define I2S_TCR2_MSEL_MASK (0xC000000U)
AnnaBridge 143:86740a56073b 6374 #define I2S_TCR2_MSEL_SHIFT (26U)
AnnaBridge 143:86740a56073b 6375 #define I2S_TCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_MSEL_SHIFT)) & I2S_TCR2_MSEL_MASK)
AnnaBridge 143:86740a56073b 6376 #define I2S_TCR2_BCI_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 6377 #define I2S_TCR2_BCI_SHIFT (28U)
AnnaBridge 143:86740a56073b 6378 #define I2S_TCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCI_SHIFT)) & I2S_TCR2_BCI_MASK)
AnnaBridge 143:86740a56073b 6379 #define I2S_TCR2_BCS_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 6380 #define I2S_TCR2_BCS_SHIFT (29U)
AnnaBridge 143:86740a56073b 6381 #define I2S_TCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_BCS_SHIFT)) & I2S_TCR2_BCS_MASK)
AnnaBridge 143:86740a56073b 6382 #define I2S_TCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 143:86740a56073b 6383 #define I2S_TCR2_SYNC_SHIFT (30U)
AnnaBridge 143:86740a56073b 6384 #define I2S_TCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR2_SYNC_SHIFT)) & I2S_TCR2_SYNC_MASK)
AnnaBridge 143:86740a56073b 6385
AnnaBridge 143:86740a56073b 6386 /*! @name TCR3 - SAI Transmit Configuration 3 Register */
AnnaBridge 143:86740a56073b 6387 #define I2S_TCR3_WDFL_MASK (0x1FU)
AnnaBridge 143:86740a56073b 6388 #define I2S_TCR3_WDFL_SHIFT (0U)
AnnaBridge 143:86740a56073b 6389 #define I2S_TCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_WDFL_SHIFT)) & I2S_TCR3_WDFL_MASK)
AnnaBridge 143:86740a56073b 6390 #define I2S_TCR3_TCE_MASK (0x30000U)
AnnaBridge 143:86740a56073b 6391 #define I2S_TCR3_TCE_SHIFT (16U)
AnnaBridge 143:86740a56073b 6392 #define I2S_TCR3_TCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR3_TCE_SHIFT)) & I2S_TCR3_TCE_MASK)
AnnaBridge 143:86740a56073b 6393
AnnaBridge 143:86740a56073b 6394 /*! @name TCR4 - SAI Transmit Configuration 4 Register */
AnnaBridge 143:86740a56073b 6395 #define I2S_TCR4_FSD_MASK (0x1U)
AnnaBridge 143:86740a56073b 6396 #define I2S_TCR4_FSD_SHIFT (0U)
AnnaBridge 143:86740a56073b 6397 #define I2S_TCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSD_SHIFT)) & I2S_TCR4_FSD_MASK)
AnnaBridge 143:86740a56073b 6398 #define I2S_TCR4_FSP_MASK (0x2U)
AnnaBridge 143:86740a56073b 6399 #define I2S_TCR4_FSP_SHIFT (1U)
AnnaBridge 143:86740a56073b 6400 #define I2S_TCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSP_SHIFT)) & I2S_TCR4_FSP_MASK)
AnnaBridge 143:86740a56073b 6401 #define I2S_TCR4_FSE_MASK (0x8U)
AnnaBridge 143:86740a56073b 6402 #define I2S_TCR4_FSE_SHIFT (3U)
AnnaBridge 143:86740a56073b 6403 #define I2S_TCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FSE_SHIFT)) & I2S_TCR4_FSE_MASK)
AnnaBridge 143:86740a56073b 6404 #define I2S_TCR4_MF_MASK (0x10U)
AnnaBridge 143:86740a56073b 6405 #define I2S_TCR4_MF_SHIFT (4U)
AnnaBridge 143:86740a56073b 6406 #define I2S_TCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_MF_SHIFT)) & I2S_TCR4_MF_MASK)
AnnaBridge 143:86740a56073b 6407 #define I2S_TCR4_SYWD_MASK (0x1F00U)
AnnaBridge 143:86740a56073b 6408 #define I2S_TCR4_SYWD_SHIFT (8U)
AnnaBridge 143:86740a56073b 6409 #define I2S_TCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_SYWD_SHIFT)) & I2S_TCR4_SYWD_MASK)
AnnaBridge 143:86740a56073b 6410 #define I2S_TCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 143:86740a56073b 6411 #define I2S_TCR4_FRSZ_SHIFT (16U)
AnnaBridge 143:86740a56073b 6412 #define I2S_TCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR4_FRSZ_SHIFT)) & I2S_TCR4_FRSZ_MASK)
AnnaBridge 143:86740a56073b 6413
AnnaBridge 143:86740a56073b 6414 /*! @name TCR5 - SAI Transmit Configuration 5 Register */
AnnaBridge 143:86740a56073b 6415 #define I2S_TCR5_FBT_MASK (0x1F00U)
AnnaBridge 143:86740a56073b 6416 #define I2S_TCR5_FBT_SHIFT (8U)
AnnaBridge 143:86740a56073b 6417 #define I2S_TCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_FBT_SHIFT)) & I2S_TCR5_FBT_MASK)
AnnaBridge 143:86740a56073b 6418 #define I2S_TCR5_W0W_MASK (0x1F0000U)
AnnaBridge 143:86740a56073b 6419 #define I2S_TCR5_W0W_SHIFT (16U)
AnnaBridge 143:86740a56073b 6420 #define I2S_TCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_W0W_SHIFT)) & I2S_TCR5_W0W_MASK)
AnnaBridge 143:86740a56073b 6421 #define I2S_TCR5_WNW_MASK (0x1F000000U)
AnnaBridge 143:86740a56073b 6422 #define I2S_TCR5_WNW_SHIFT (24U)
AnnaBridge 143:86740a56073b 6423 #define I2S_TCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_TCR5_WNW_SHIFT)) & I2S_TCR5_WNW_MASK)
AnnaBridge 143:86740a56073b 6424
AnnaBridge 143:86740a56073b 6425 /*! @name TDR - SAI Transmit Data Register */
AnnaBridge 143:86740a56073b 6426 #define I2S_TDR_TDR_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 6427 #define I2S_TDR_TDR_SHIFT (0U)
AnnaBridge 143:86740a56073b 6428 #define I2S_TDR_TDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_TDR_TDR_SHIFT)) & I2S_TDR_TDR_MASK)
AnnaBridge 143:86740a56073b 6429
AnnaBridge 143:86740a56073b 6430 /* The count of I2S_TDR */
AnnaBridge 143:86740a56073b 6431 #define I2S_TDR_COUNT (2U)
AnnaBridge 143:86740a56073b 6432
AnnaBridge 143:86740a56073b 6433 /*! @name TFR - SAI Transmit FIFO Register */
AnnaBridge 143:86740a56073b 6434 #define I2S_TFR_RFP_MASK (0xFU)
AnnaBridge 143:86740a56073b 6435 #define I2S_TFR_RFP_SHIFT (0U)
AnnaBridge 143:86740a56073b 6436 #define I2S_TFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_RFP_SHIFT)) & I2S_TFR_RFP_MASK)
AnnaBridge 143:86740a56073b 6437 #define I2S_TFR_WFP_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 6438 #define I2S_TFR_WFP_SHIFT (16U)
AnnaBridge 143:86740a56073b 6439 #define I2S_TFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_TFR_WFP_SHIFT)) & I2S_TFR_WFP_MASK)
AnnaBridge 143:86740a56073b 6440
AnnaBridge 143:86740a56073b 6441 /* The count of I2S_TFR */
AnnaBridge 143:86740a56073b 6442 #define I2S_TFR_COUNT (2U)
AnnaBridge 143:86740a56073b 6443
AnnaBridge 143:86740a56073b 6444 /*! @name TMR - SAI Transmit Mask Register */
AnnaBridge 143:86740a56073b 6445 #define I2S_TMR_TWM_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 6446 #define I2S_TMR_TWM_SHIFT (0U)
AnnaBridge 143:86740a56073b 6447 #define I2S_TMR_TWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_TMR_TWM_SHIFT)) & I2S_TMR_TWM_MASK)
AnnaBridge 143:86740a56073b 6448
AnnaBridge 143:86740a56073b 6449 /*! @name RCSR - SAI Receive Control Register */
AnnaBridge 143:86740a56073b 6450 #define I2S_RCSR_FRDE_MASK (0x1U)
AnnaBridge 143:86740a56073b 6451 #define I2S_RCSR_FRDE_SHIFT (0U)
AnnaBridge 143:86740a56073b 6452 #define I2S_RCSR_FRDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRDE_SHIFT)) & I2S_RCSR_FRDE_MASK)
AnnaBridge 143:86740a56073b 6453 #define I2S_RCSR_FWDE_MASK (0x2U)
AnnaBridge 143:86740a56073b 6454 #define I2S_RCSR_FWDE_SHIFT (1U)
AnnaBridge 143:86740a56073b 6455 #define I2S_RCSR_FWDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWDE_SHIFT)) & I2S_RCSR_FWDE_MASK)
AnnaBridge 143:86740a56073b 6456 #define I2S_RCSR_FRIE_MASK (0x100U)
AnnaBridge 143:86740a56073b 6457 #define I2S_RCSR_FRIE_SHIFT (8U)
AnnaBridge 143:86740a56073b 6458 #define I2S_RCSR_FRIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRIE_SHIFT)) & I2S_RCSR_FRIE_MASK)
AnnaBridge 143:86740a56073b 6459 #define I2S_RCSR_FWIE_MASK (0x200U)
AnnaBridge 143:86740a56073b 6460 #define I2S_RCSR_FWIE_SHIFT (9U)
AnnaBridge 143:86740a56073b 6461 #define I2S_RCSR_FWIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWIE_SHIFT)) & I2S_RCSR_FWIE_MASK)
AnnaBridge 143:86740a56073b 6462 #define I2S_RCSR_FEIE_MASK (0x400U)
AnnaBridge 143:86740a56073b 6463 #define I2S_RCSR_FEIE_SHIFT (10U)
AnnaBridge 143:86740a56073b 6464 #define I2S_RCSR_FEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEIE_SHIFT)) & I2S_RCSR_FEIE_MASK)
AnnaBridge 143:86740a56073b 6465 #define I2S_RCSR_SEIE_MASK (0x800U)
AnnaBridge 143:86740a56073b 6466 #define I2S_RCSR_SEIE_SHIFT (11U)
AnnaBridge 143:86740a56073b 6467 #define I2S_RCSR_SEIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEIE_SHIFT)) & I2S_RCSR_SEIE_MASK)
AnnaBridge 143:86740a56073b 6468 #define I2S_RCSR_WSIE_MASK (0x1000U)
AnnaBridge 143:86740a56073b 6469 #define I2S_RCSR_WSIE_SHIFT (12U)
AnnaBridge 143:86740a56073b 6470 #define I2S_RCSR_WSIE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSIE_SHIFT)) & I2S_RCSR_WSIE_MASK)
AnnaBridge 143:86740a56073b 6471 #define I2S_RCSR_FRF_MASK (0x10000U)
AnnaBridge 143:86740a56073b 6472 #define I2S_RCSR_FRF_SHIFT (16U)
AnnaBridge 143:86740a56073b 6473 #define I2S_RCSR_FRF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FRF_SHIFT)) & I2S_RCSR_FRF_MASK)
AnnaBridge 143:86740a56073b 6474 #define I2S_RCSR_FWF_MASK (0x20000U)
AnnaBridge 143:86740a56073b 6475 #define I2S_RCSR_FWF_SHIFT (17U)
AnnaBridge 143:86740a56073b 6476 #define I2S_RCSR_FWF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FWF_SHIFT)) & I2S_RCSR_FWF_MASK)
AnnaBridge 143:86740a56073b 6477 #define I2S_RCSR_FEF_MASK (0x40000U)
AnnaBridge 143:86740a56073b 6478 #define I2S_RCSR_FEF_SHIFT (18U)
AnnaBridge 143:86740a56073b 6479 #define I2S_RCSR_FEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FEF_SHIFT)) & I2S_RCSR_FEF_MASK)
AnnaBridge 143:86740a56073b 6480 #define I2S_RCSR_SEF_MASK (0x80000U)
AnnaBridge 143:86740a56073b 6481 #define I2S_RCSR_SEF_SHIFT (19U)
AnnaBridge 143:86740a56073b 6482 #define I2S_RCSR_SEF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SEF_SHIFT)) & I2S_RCSR_SEF_MASK)
AnnaBridge 143:86740a56073b 6483 #define I2S_RCSR_WSF_MASK (0x100000U)
AnnaBridge 143:86740a56073b 6484 #define I2S_RCSR_WSF_SHIFT (20U)
AnnaBridge 143:86740a56073b 6485 #define I2S_RCSR_WSF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_WSF_SHIFT)) & I2S_RCSR_WSF_MASK)
AnnaBridge 143:86740a56073b 6486 #define I2S_RCSR_SR_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 6487 #define I2S_RCSR_SR_SHIFT (24U)
AnnaBridge 143:86740a56073b 6488 #define I2S_RCSR_SR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_SR_SHIFT)) & I2S_RCSR_SR_MASK)
AnnaBridge 143:86740a56073b 6489 #define I2S_RCSR_FR_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 6490 #define I2S_RCSR_FR_SHIFT (25U)
AnnaBridge 143:86740a56073b 6491 #define I2S_RCSR_FR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_FR_SHIFT)) & I2S_RCSR_FR_MASK)
AnnaBridge 143:86740a56073b 6492 #define I2S_RCSR_BCE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 6493 #define I2S_RCSR_BCE_SHIFT (28U)
AnnaBridge 143:86740a56073b 6494 #define I2S_RCSR_BCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_BCE_SHIFT)) & I2S_RCSR_BCE_MASK)
AnnaBridge 143:86740a56073b 6495 #define I2S_RCSR_DBGE_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 6496 #define I2S_RCSR_DBGE_SHIFT (29U)
AnnaBridge 143:86740a56073b 6497 #define I2S_RCSR_DBGE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_DBGE_SHIFT)) & I2S_RCSR_DBGE_MASK)
AnnaBridge 143:86740a56073b 6498 #define I2S_RCSR_STOPE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 6499 #define I2S_RCSR_STOPE_SHIFT (30U)
AnnaBridge 143:86740a56073b 6500 #define I2S_RCSR_STOPE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_STOPE_SHIFT)) & I2S_RCSR_STOPE_MASK)
AnnaBridge 143:86740a56073b 6501 #define I2S_RCSR_RE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 6502 #define I2S_RCSR_RE_SHIFT (31U)
AnnaBridge 143:86740a56073b 6503 #define I2S_RCSR_RE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCSR_RE_SHIFT)) & I2S_RCSR_RE_MASK)
AnnaBridge 143:86740a56073b 6504
AnnaBridge 143:86740a56073b 6505 /*! @name RCR1 - SAI Receive Configuration 1 Register */
AnnaBridge 143:86740a56073b 6506 #define I2S_RCR1_RFW_MASK (0x7U)
AnnaBridge 143:86740a56073b 6507 #define I2S_RCR1_RFW_SHIFT (0U)
AnnaBridge 143:86740a56073b 6508 #define I2S_RCR1_RFW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR1_RFW_SHIFT)) & I2S_RCR1_RFW_MASK)
AnnaBridge 143:86740a56073b 6509
AnnaBridge 143:86740a56073b 6510 /*! @name RCR2 - SAI Receive Configuration 2 Register */
AnnaBridge 143:86740a56073b 6511 #define I2S_RCR2_DIV_MASK (0xFFU)
AnnaBridge 143:86740a56073b 6512 #define I2S_RCR2_DIV_SHIFT (0U)
AnnaBridge 143:86740a56073b 6513 #define I2S_RCR2_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_DIV_SHIFT)) & I2S_RCR2_DIV_MASK)
AnnaBridge 143:86740a56073b 6514 #define I2S_RCR2_BCD_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 6515 #define I2S_RCR2_BCD_SHIFT (24U)
AnnaBridge 143:86740a56073b 6516 #define I2S_RCR2_BCD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCD_SHIFT)) & I2S_RCR2_BCD_MASK)
AnnaBridge 143:86740a56073b 6517 #define I2S_RCR2_BCP_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 6518 #define I2S_RCR2_BCP_SHIFT (25U)
AnnaBridge 143:86740a56073b 6519 #define I2S_RCR2_BCP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCP_SHIFT)) & I2S_RCR2_BCP_MASK)
AnnaBridge 143:86740a56073b 6520 #define I2S_RCR2_MSEL_MASK (0xC000000U)
AnnaBridge 143:86740a56073b 6521 #define I2S_RCR2_MSEL_SHIFT (26U)
AnnaBridge 143:86740a56073b 6522 #define I2S_RCR2_MSEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_MSEL_SHIFT)) & I2S_RCR2_MSEL_MASK)
AnnaBridge 143:86740a56073b 6523 #define I2S_RCR2_BCI_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 6524 #define I2S_RCR2_BCI_SHIFT (28U)
AnnaBridge 143:86740a56073b 6525 #define I2S_RCR2_BCI(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCI_SHIFT)) & I2S_RCR2_BCI_MASK)
AnnaBridge 143:86740a56073b 6526 #define I2S_RCR2_BCS_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 6527 #define I2S_RCR2_BCS_SHIFT (29U)
AnnaBridge 143:86740a56073b 6528 #define I2S_RCR2_BCS(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_BCS_SHIFT)) & I2S_RCR2_BCS_MASK)
AnnaBridge 143:86740a56073b 6529 #define I2S_RCR2_SYNC_MASK (0xC0000000U)
AnnaBridge 143:86740a56073b 6530 #define I2S_RCR2_SYNC_SHIFT (30U)
AnnaBridge 143:86740a56073b 6531 #define I2S_RCR2_SYNC(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR2_SYNC_SHIFT)) & I2S_RCR2_SYNC_MASK)
AnnaBridge 143:86740a56073b 6532
AnnaBridge 143:86740a56073b 6533 /*! @name RCR3 - SAI Receive Configuration 3 Register */
AnnaBridge 143:86740a56073b 6534 #define I2S_RCR3_WDFL_MASK (0x1FU)
AnnaBridge 143:86740a56073b 6535 #define I2S_RCR3_WDFL_SHIFT (0U)
AnnaBridge 143:86740a56073b 6536 #define I2S_RCR3_WDFL(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_WDFL_SHIFT)) & I2S_RCR3_WDFL_MASK)
AnnaBridge 143:86740a56073b 6537 #define I2S_RCR3_RCE_MASK (0x30000U)
AnnaBridge 143:86740a56073b 6538 #define I2S_RCR3_RCE_SHIFT (16U)
AnnaBridge 143:86740a56073b 6539 #define I2S_RCR3_RCE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR3_RCE_SHIFT)) & I2S_RCR3_RCE_MASK)
AnnaBridge 143:86740a56073b 6540
AnnaBridge 143:86740a56073b 6541 /*! @name RCR4 - SAI Receive Configuration 4 Register */
AnnaBridge 143:86740a56073b 6542 #define I2S_RCR4_FSD_MASK (0x1U)
AnnaBridge 143:86740a56073b 6543 #define I2S_RCR4_FSD_SHIFT (0U)
AnnaBridge 143:86740a56073b 6544 #define I2S_RCR4_FSD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSD_SHIFT)) & I2S_RCR4_FSD_MASK)
AnnaBridge 143:86740a56073b 6545 #define I2S_RCR4_FSP_MASK (0x2U)
AnnaBridge 143:86740a56073b 6546 #define I2S_RCR4_FSP_SHIFT (1U)
AnnaBridge 143:86740a56073b 6547 #define I2S_RCR4_FSP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSP_SHIFT)) & I2S_RCR4_FSP_MASK)
AnnaBridge 143:86740a56073b 6548 #define I2S_RCR4_FSE_MASK (0x8U)
AnnaBridge 143:86740a56073b 6549 #define I2S_RCR4_FSE_SHIFT (3U)
AnnaBridge 143:86740a56073b 6550 #define I2S_RCR4_FSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FSE_SHIFT)) & I2S_RCR4_FSE_MASK)
AnnaBridge 143:86740a56073b 6551 #define I2S_RCR4_MF_MASK (0x10U)
AnnaBridge 143:86740a56073b 6552 #define I2S_RCR4_MF_SHIFT (4U)
AnnaBridge 143:86740a56073b 6553 #define I2S_RCR4_MF(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_MF_SHIFT)) & I2S_RCR4_MF_MASK)
AnnaBridge 143:86740a56073b 6554 #define I2S_RCR4_SYWD_MASK (0x1F00U)
AnnaBridge 143:86740a56073b 6555 #define I2S_RCR4_SYWD_SHIFT (8U)
AnnaBridge 143:86740a56073b 6556 #define I2S_RCR4_SYWD(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_SYWD_SHIFT)) & I2S_RCR4_SYWD_MASK)
AnnaBridge 143:86740a56073b 6557 #define I2S_RCR4_FRSZ_MASK (0x1F0000U)
AnnaBridge 143:86740a56073b 6558 #define I2S_RCR4_FRSZ_SHIFT (16U)
AnnaBridge 143:86740a56073b 6559 #define I2S_RCR4_FRSZ(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR4_FRSZ_SHIFT)) & I2S_RCR4_FRSZ_MASK)
AnnaBridge 143:86740a56073b 6560
AnnaBridge 143:86740a56073b 6561 /*! @name RCR5 - SAI Receive Configuration 5 Register */
AnnaBridge 143:86740a56073b 6562 #define I2S_RCR5_FBT_MASK (0x1F00U)
AnnaBridge 143:86740a56073b 6563 #define I2S_RCR5_FBT_SHIFT (8U)
AnnaBridge 143:86740a56073b 6564 #define I2S_RCR5_FBT(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_FBT_SHIFT)) & I2S_RCR5_FBT_MASK)
AnnaBridge 143:86740a56073b 6565 #define I2S_RCR5_W0W_MASK (0x1F0000U)
AnnaBridge 143:86740a56073b 6566 #define I2S_RCR5_W0W_SHIFT (16U)
AnnaBridge 143:86740a56073b 6567 #define I2S_RCR5_W0W(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_W0W_SHIFT)) & I2S_RCR5_W0W_MASK)
AnnaBridge 143:86740a56073b 6568 #define I2S_RCR5_WNW_MASK (0x1F000000U)
AnnaBridge 143:86740a56073b 6569 #define I2S_RCR5_WNW_SHIFT (24U)
AnnaBridge 143:86740a56073b 6570 #define I2S_RCR5_WNW(x) (((uint32_t)(((uint32_t)(x)) << I2S_RCR5_WNW_SHIFT)) & I2S_RCR5_WNW_MASK)
AnnaBridge 143:86740a56073b 6571
AnnaBridge 143:86740a56073b 6572 /*! @name RDR - SAI Receive Data Register */
AnnaBridge 143:86740a56073b 6573 #define I2S_RDR_RDR_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 6574 #define I2S_RDR_RDR_SHIFT (0U)
AnnaBridge 143:86740a56073b 6575 #define I2S_RDR_RDR(x) (((uint32_t)(((uint32_t)(x)) << I2S_RDR_RDR_SHIFT)) & I2S_RDR_RDR_MASK)
AnnaBridge 143:86740a56073b 6576
AnnaBridge 143:86740a56073b 6577 /* The count of I2S_RDR */
AnnaBridge 143:86740a56073b 6578 #define I2S_RDR_COUNT (2U)
AnnaBridge 143:86740a56073b 6579
AnnaBridge 143:86740a56073b 6580 /*! @name RFR - SAI Receive FIFO Register */
AnnaBridge 143:86740a56073b 6581 #define I2S_RFR_RFP_MASK (0xFU)
AnnaBridge 143:86740a56073b 6582 #define I2S_RFR_RFP_SHIFT (0U)
AnnaBridge 143:86740a56073b 6583 #define I2S_RFR_RFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_RFP_SHIFT)) & I2S_RFR_RFP_MASK)
AnnaBridge 143:86740a56073b 6584 #define I2S_RFR_WFP_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 6585 #define I2S_RFR_WFP_SHIFT (16U)
AnnaBridge 143:86740a56073b 6586 #define I2S_RFR_WFP(x) (((uint32_t)(((uint32_t)(x)) << I2S_RFR_WFP_SHIFT)) & I2S_RFR_WFP_MASK)
AnnaBridge 143:86740a56073b 6587
AnnaBridge 143:86740a56073b 6588 /* The count of I2S_RFR */
AnnaBridge 143:86740a56073b 6589 #define I2S_RFR_COUNT (2U)
AnnaBridge 143:86740a56073b 6590
AnnaBridge 143:86740a56073b 6591 /*! @name RMR - SAI Receive Mask Register */
AnnaBridge 143:86740a56073b 6592 #define I2S_RMR_RWM_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 6593 #define I2S_RMR_RWM_SHIFT (0U)
AnnaBridge 143:86740a56073b 6594 #define I2S_RMR_RWM(x) (((uint32_t)(((uint32_t)(x)) << I2S_RMR_RWM_SHIFT)) & I2S_RMR_RWM_MASK)
AnnaBridge 143:86740a56073b 6595
AnnaBridge 143:86740a56073b 6596 /*! @name MCR - SAI MCLK Control Register */
AnnaBridge 143:86740a56073b 6597 #define I2S_MCR_MICS_MASK (0x3000000U)
AnnaBridge 143:86740a56073b 6598 #define I2S_MCR_MICS_SHIFT (24U)
AnnaBridge 143:86740a56073b 6599 #define I2S_MCR_MICS(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MICS_SHIFT)) & I2S_MCR_MICS_MASK)
AnnaBridge 143:86740a56073b 6600 #define I2S_MCR_MOE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 6601 #define I2S_MCR_MOE_SHIFT (30U)
AnnaBridge 143:86740a56073b 6602 #define I2S_MCR_MOE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_MOE_SHIFT)) & I2S_MCR_MOE_MASK)
AnnaBridge 143:86740a56073b 6603 #define I2S_MCR_DUF_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 6604 #define I2S_MCR_DUF_SHIFT (31U)
AnnaBridge 143:86740a56073b 6605 #define I2S_MCR_DUF(x) (((uint32_t)(((uint32_t)(x)) << I2S_MCR_DUF_SHIFT)) & I2S_MCR_DUF_MASK)
AnnaBridge 143:86740a56073b 6606
AnnaBridge 143:86740a56073b 6607 /*! @name MDR - SAI MCLK Divide Register */
AnnaBridge 143:86740a56073b 6608 #define I2S_MDR_DIVIDE_MASK (0xFFFU)
AnnaBridge 143:86740a56073b 6609 #define I2S_MDR_DIVIDE_SHIFT (0U)
AnnaBridge 143:86740a56073b 6610 #define I2S_MDR_DIVIDE(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_DIVIDE_SHIFT)) & I2S_MDR_DIVIDE_MASK)
AnnaBridge 143:86740a56073b 6611 #define I2S_MDR_FRACT_MASK (0xFF000U)
AnnaBridge 143:86740a56073b 6612 #define I2S_MDR_FRACT_SHIFT (12U)
AnnaBridge 143:86740a56073b 6613 #define I2S_MDR_FRACT(x) (((uint32_t)(((uint32_t)(x)) << I2S_MDR_FRACT_SHIFT)) & I2S_MDR_FRACT_MASK)
AnnaBridge 143:86740a56073b 6614
AnnaBridge 143:86740a56073b 6615
AnnaBridge 143:86740a56073b 6616 /*!
AnnaBridge 143:86740a56073b 6617 * @}
AnnaBridge 143:86740a56073b 6618 */ /* end of group I2S_Register_Masks */
AnnaBridge 143:86740a56073b 6619
AnnaBridge 143:86740a56073b 6620
AnnaBridge 143:86740a56073b 6621 /* I2S - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 6622 /** Peripheral I2S0 base address */
AnnaBridge 143:86740a56073b 6623 #define I2S0_BASE (0x4002F000u)
AnnaBridge 143:86740a56073b 6624 /** Peripheral I2S0 base pointer */
AnnaBridge 143:86740a56073b 6625 #define I2S0 ((I2S_Type *)I2S0_BASE)
AnnaBridge 143:86740a56073b 6626 /** Array initializer of I2S peripheral base addresses */
AnnaBridge 143:86740a56073b 6627 #define I2S_BASE_ADDRS { I2S0_BASE }
AnnaBridge 143:86740a56073b 6628 /** Array initializer of I2S peripheral base pointers */
AnnaBridge 143:86740a56073b 6629 #define I2S_BASE_PTRS { I2S0 }
AnnaBridge 143:86740a56073b 6630 /** Interrupt vectors for the I2S peripheral type */
AnnaBridge 143:86740a56073b 6631 #define I2S_RX_IRQS { I2S0_Rx_IRQn }
AnnaBridge 143:86740a56073b 6632 #define I2S_TX_IRQS { I2S0_Tx_IRQn }
AnnaBridge 143:86740a56073b 6633
AnnaBridge 143:86740a56073b 6634 /*!
AnnaBridge 143:86740a56073b 6635 * @}
AnnaBridge 143:86740a56073b 6636 */ /* end of group I2S_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 6637
AnnaBridge 143:86740a56073b 6638
AnnaBridge 143:86740a56073b 6639 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6640 -- LLWU Peripheral Access Layer
AnnaBridge 143:86740a56073b 6641 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6642
AnnaBridge 143:86740a56073b 6643 /*!
AnnaBridge 143:86740a56073b 6644 * @addtogroup LLWU_Peripheral_Access_Layer LLWU Peripheral Access Layer
AnnaBridge 143:86740a56073b 6645 * @{
AnnaBridge 143:86740a56073b 6646 */
AnnaBridge 143:86740a56073b 6647
AnnaBridge 143:86740a56073b 6648 /** LLWU - Register Layout Typedef */
AnnaBridge 143:86740a56073b 6649 typedef struct {
AnnaBridge 143:86740a56073b 6650 __IO uint8_t PE1; /**< LLWU Pin Enable 1 register, offset: 0x0 */
AnnaBridge 143:86740a56073b 6651 __IO uint8_t PE2; /**< LLWU Pin Enable 2 register, offset: 0x1 */
AnnaBridge 143:86740a56073b 6652 __IO uint8_t PE3; /**< LLWU Pin Enable 3 register, offset: 0x2 */
AnnaBridge 143:86740a56073b 6653 __IO uint8_t PE4; /**< LLWU Pin Enable 4 register, offset: 0x3 */
AnnaBridge 143:86740a56073b 6654 __IO uint8_t ME; /**< LLWU Module Enable register, offset: 0x4 */
AnnaBridge 143:86740a56073b 6655 __IO uint8_t F1; /**< LLWU Flag 1 register, offset: 0x5 */
AnnaBridge 143:86740a56073b 6656 __IO uint8_t F2; /**< LLWU Flag 2 register, offset: 0x6 */
AnnaBridge 143:86740a56073b 6657 __I uint8_t F3; /**< LLWU Flag 3 register, offset: 0x7 */
AnnaBridge 143:86740a56073b 6658 __IO uint8_t FILT1; /**< LLWU Pin Filter 1 register, offset: 0x8 */
AnnaBridge 143:86740a56073b 6659 __IO uint8_t FILT2; /**< LLWU Pin Filter 2 register, offset: 0x9 */
AnnaBridge 143:86740a56073b 6660 __IO uint8_t RST; /**< LLWU Reset Enable register, offset: 0xA */
AnnaBridge 143:86740a56073b 6661 } LLWU_Type;
AnnaBridge 143:86740a56073b 6662
AnnaBridge 143:86740a56073b 6663 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6664 -- LLWU Register Masks
AnnaBridge 143:86740a56073b 6665 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6666
AnnaBridge 143:86740a56073b 6667 /*!
AnnaBridge 143:86740a56073b 6668 * @addtogroup LLWU_Register_Masks LLWU Register Masks
AnnaBridge 143:86740a56073b 6669 * @{
AnnaBridge 143:86740a56073b 6670 */
AnnaBridge 143:86740a56073b 6671
AnnaBridge 143:86740a56073b 6672 /*! @name PE1 - LLWU Pin Enable 1 register */
AnnaBridge 143:86740a56073b 6673 #define LLWU_PE1_WUPE0_MASK (0x3U)
AnnaBridge 143:86740a56073b 6674 #define LLWU_PE1_WUPE0_SHIFT (0U)
AnnaBridge 143:86740a56073b 6675 #define LLWU_PE1_WUPE0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE0_SHIFT)) & LLWU_PE1_WUPE0_MASK)
AnnaBridge 143:86740a56073b 6676 #define LLWU_PE1_WUPE1_MASK (0xCU)
AnnaBridge 143:86740a56073b 6677 #define LLWU_PE1_WUPE1_SHIFT (2U)
AnnaBridge 143:86740a56073b 6678 #define LLWU_PE1_WUPE1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE1_SHIFT)) & LLWU_PE1_WUPE1_MASK)
AnnaBridge 143:86740a56073b 6679 #define LLWU_PE1_WUPE2_MASK (0x30U)
AnnaBridge 143:86740a56073b 6680 #define LLWU_PE1_WUPE2_SHIFT (4U)
AnnaBridge 143:86740a56073b 6681 #define LLWU_PE1_WUPE2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE2_SHIFT)) & LLWU_PE1_WUPE2_MASK)
AnnaBridge 143:86740a56073b 6682 #define LLWU_PE1_WUPE3_MASK (0xC0U)
AnnaBridge 143:86740a56073b 6683 #define LLWU_PE1_WUPE3_SHIFT (6U)
AnnaBridge 143:86740a56073b 6684 #define LLWU_PE1_WUPE3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE1_WUPE3_SHIFT)) & LLWU_PE1_WUPE3_MASK)
AnnaBridge 143:86740a56073b 6685
AnnaBridge 143:86740a56073b 6686 /*! @name PE2 - LLWU Pin Enable 2 register */
AnnaBridge 143:86740a56073b 6687 #define LLWU_PE2_WUPE4_MASK (0x3U)
AnnaBridge 143:86740a56073b 6688 #define LLWU_PE2_WUPE4_SHIFT (0U)
AnnaBridge 143:86740a56073b 6689 #define LLWU_PE2_WUPE4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE4_SHIFT)) & LLWU_PE2_WUPE4_MASK)
AnnaBridge 143:86740a56073b 6690 #define LLWU_PE2_WUPE5_MASK (0xCU)
AnnaBridge 143:86740a56073b 6691 #define LLWU_PE2_WUPE5_SHIFT (2U)
AnnaBridge 143:86740a56073b 6692 #define LLWU_PE2_WUPE5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE5_SHIFT)) & LLWU_PE2_WUPE5_MASK)
AnnaBridge 143:86740a56073b 6693 #define LLWU_PE2_WUPE6_MASK (0x30U)
AnnaBridge 143:86740a56073b 6694 #define LLWU_PE2_WUPE6_SHIFT (4U)
AnnaBridge 143:86740a56073b 6695 #define LLWU_PE2_WUPE6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE6_SHIFT)) & LLWU_PE2_WUPE6_MASK)
AnnaBridge 143:86740a56073b 6696 #define LLWU_PE2_WUPE7_MASK (0xC0U)
AnnaBridge 143:86740a56073b 6697 #define LLWU_PE2_WUPE7_SHIFT (6U)
AnnaBridge 143:86740a56073b 6698 #define LLWU_PE2_WUPE7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE2_WUPE7_SHIFT)) & LLWU_PE2_WUPE7_MASK)
AnnaBridge 143:86740a56073b 6699
AnnaBridge 143:86740a56073b 6700 /*! @name PE3 - LLWU Pin Enable 3 register */
AnnaBridge 143:86740a56073b 6701 #define LLWU_PE3_WUPE8_MASK (0x3U)
AnnaBridge 143:86740a56073b 6702 #define LLWU_PE3_WUPE8_SHIFT (0U)
AnnaBridge 143:86740a56073b 6703 #define LLWU_PE3_WUPE8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE8_SHIFT)) & LLWU_PE3_WUPE8_MASK)
AnnaBridge 143:86740a56073b 6704 #define LLWU_PE3_WUPE9_MASK (0xCU)
AnnaBridge 143:86740a56073b 6705 #define LLWU_PE3_WUPE9_SHIFT (2U)
AnnaBridge 143:86740a56073b 6706 #define LLWU_PE3_WUPE9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE9_SHIFT)) & LLWU_PE3_WUPE9_MASK)
AnnaBridge 143:86740a56073b 6707 #define LLWU_PE3_WUPE10_MASK (0x30U)
AnnaBridge 143:86740a56073b 6708 #define LLWU_PE3_WUPE10_SHIFT (4U)
AnnaBridge 143:86740a56073b 6709 #define LLWU_PE3_WUPE10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE10_SHIFT)) & LLWU_PE3_WUPE10_MASK)
AnnaBridge 143:86740a56073b 6710 #define LLWU_PE3_WUPE11_MASK (0xC0U)
AnnaBridge 143:86740a56073b 6711 #define LLWU_PE3_WUPE11_SHIFT (6U)
AnnaBridge 143:86740a56073b 6712 #define LLWU_PE3_WUPE11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE3_WUPE11_SHIFT)) & LLWU_PE3_WUPE11_MASK)
AnnaBridge 143:86740a56073b 6713
AnnaBridge 143:86740a56073b 6714 /*! @name PE4 - LLWU Pin Enable 4 register */
AnnaBridge 143:86740a56073b 6715 #define LLWU_PE4_WUPE12_MASK (0x3U)
AnnaBridge 143:86740a56073b 6716 #define LLWU_PE4_WUPE12_SHIFT (0U)
AnnaBridge 143:86740a56073b 6717 #define LLWU_PE4_WUPE12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE12_SHIFT)) & LLWU_PE4_WUPE12_MASK)
AnnaBridge 143:86740a56073b 6718 #define LLWU_PE4_WUPE13_MASK (0xCU)
AnnaBridge 143:86740a56073b 6719 #define LLWU_PE4_WUPE13_SHIFT (2U)
AnnaBridge 143:86740a56073b 6720 #define LLWU_PE4_WUPE13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE13_SHIFT)) & LLWU_PE4_WUPE13_MASK)
AnnaBridge 143:86740a56073b 6721 #define LLWU_PE4_WUPE14_MASK (0x30U)
AnnaBridge 143:86740a56073b 6722 #define LLWU_PE4_WUPE14_SHIFT (4U)
AnnaBridge 143:86740a56073b 6723 #define LLWU_PE4_WUPE14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE14_SHIFT)) & LLWU_PE4_WUPE14_MASK)
AnnaBridge 143:86740a56073b 6724 #define LLWU_PE4_WUPE15_MASK (0xC0U)
AnnaBridge 143:86740a56073b 6725 #define LLWU_PE4_WUPE15_SHIFT (6U)
AnnaBridge 143:86740a56073b 6726 #define LLWU_PE4_WUPE15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_PE4_WUPE15_SHIFT)) & LLWU_PE4_WUPE15_MASK)
AnnaBridge 143:86740a56073b 6727
AnnaBridge 143:86740a56073b 6728 /*! @name ME - LLWU Module Enable register */
AnnaBridge 143:86740a56073b 6729 #define LLWU_ME_WUME0_MASK (0x1U)
AnnaBridge 143:86740a56073b 6730 #define LLWU_ME_WUME0_SHIFT (0U)
AnnaBridge 143:86740a56073b 6731 #define LLWU_ME_WUME0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME0_SHIFT)) & LLWU_ME_WUME0_MASK)
AnnaBridge 143:86740a56073b 6732 #define LLWU_ME_WUME1_MASK (0x2U)
AnnaBridge 143:86740a56073b 6733 #define LLWU_ME_WUME1_SHIFT (1U)
AnnaBridge 143:86740a56073b 6734 #define LLWU_ME_WUME1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME1_SHIFT)) & LLWU_ME_WUME1_MASK)
AnnaBridge 143:86740a56073b 6735 #define LLWU_ME_WUME2_MASK (0x4U)
AnnaBridge 143:86740a56073b 6736 #define LLWU_ME_WUME2_SHIFT (2U)
AnnaBridge 143:86740a56073b 6737 #define LLWU_ME_WUME2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME2_SHIFT)) & LLWU_ME_WUME2_MASK)
AnnaBridge 143:86740a56073b 6738 #define LLWU_ME_WUME3_MASK (0x8U)
AnnaBridge 143:86740a56073b 6739 #define LLWU_ME_WUME3_SHIFT (3U)
AnnaBridge 143:86740a56073b 6740 #define LLWU_ME_WUME3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME3_SHIFT)) & LLWU_ME_WUME3_MASK)
AnnaBridge 143:86740a56073b 6741 #define LLWU_ME_WUME4_MASK (0x10U)
AnnaBridge 143:86740a56073b 6742 #define LLWU_ME_WUME4_SHIFT (4U)
AnnaBridge 143:86740a56073b 6743 #define LLWU_ME_WUME4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME4_SHIFT)) & LLWU_ME_WUME4_MASK)
AnnaBridge 143:86740a56073b 6744 #define LLWU_ME_WUME5_MASK (0x20U)
AnnaBridge 143:86740a56073b 6745 #define LLWU_ME_WUME5_SHIFT (5U)
AnnaBridge 143:86740a56073b 6746 #define LLWU_ME_WUME5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME5_SHIFT)) & LLWU_ME_WUME5_MASK)
AnnaBridge 143:86740a56073b 6747 #define LLWU_ME_WUME6_MASK (0x40U)
AnnaBridge 143:86740a56073b 6748 #define LLWU_ME_WUME6_SHIFT (6U)
AnnaBridge 143:86740a56073b 6749 #define LLWU_ME_WUME6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME6_SHIFT)) & LLWU_ME_WUME6_MASK)
AnnaBridge 143:86740a56073b 6750 #define LLWU_ME_WUME7_MASK (0x80U)
AnnaBridge 143:86740a56073b 6751 #define LLWU_ME_WUME7_SHIFT (7U)
AnnaBridge 143:86740a56073b 6752 #define LLWU_ME_WUME7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_ME_WUME7_SHIFT)) & LLWU_ME_WUME7_MASK)
AnnaBridge 143:86740a56073b 6753
AnnaBridge 143:86740a56073b 6754 /*! @name F1 - LLWU Flag 1 register */
AnnaBridge 143:86740a56073b 6755 #define LLWU_F1_WUF0_MASK (0x1U)
AnnaBridge 143:86740a56073b 6756 #define LLWU_F1_WUF0_SHIFT (0U)
AnnaBridge 143:86740a56073b 6757 #define LLWU_F1_WUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF0_SHIFT)) & LLWU_F1_WUF0_MASK)
AnnaBridge 143:86740a56073b 6758 #define LLWU_F1_WUF1_MASK (0x2U)
AnnaBridge 143:86740a56073b 6759 #define LLWU_F1_WUF1_SHIFT (1U)
AnnaBridge 143:86740a56073b 6760 #define LLWU_F1_WUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF1_SHIFT)) & LLWU_F1_WUF1_MASK)
AnnaBridge 143:86740a56073b 6761 #define LLWU_F1_WUF2_MASK (0x4U)
AnnaBridge 143:86740a56073b 6762 #define LLWU_F1_WUF2_SHIFT (2U)
AnnaBridge 143:86740a56073b 6763 #define LLWU_F1_WUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF2_SHIFT)) & LLWU_F1_WUF2_MASK)
AnnaBridge 143:86740a56073b 6764 #define LLWU_F1_WUF3_MASK (0x8U)
AnnaBridge 143:86740a56073b 6765 #define LLWU_F1_WUF3_SHIFT (3U)
AnnaBridge 143:86740a56073b 6766 #define LLWU_F1_WUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF3_SHIFT)) & LLWU_F1_WUF3_MASK)
AnnaBridge 143:86740a56073b 6767 #define LLWU_F1_WUF4_MASK (0x10U)
AnnaBridge 143:86740a56073b 6768 #define LLWU_F1_WUF4_SHIFT (4U)
AnnaBridge 143:86740a56073b 6769 #define LLWU_F1_WUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF4_SHIFT)) & LLWU_F1_WUF4_MASK)
AnnaBridge 143:86740a56073b 6770 #define LLWU_F1_WUF5_MASK (0x20U)
AnnaBridge 143:86740a56073b 6771 #define LLWU_F1_WUF5_SHIFT (5U)
AnnaBridge 143:86740a56073b 6772 #define LLWU_F1_WUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF5_SHIFT)) & LLWU_F1_WUF5_MASK)
AnnaBridge 143:86740a56073b 6773 #define LLWU_F1_WUF6_MASK (0x40U)
AnnaBridge 143:86740a56073b 6774 #define LLWU_F1_WUF6_SHIFT (6U)
AnnaBridge 143:86740a56073b 6775 #define LLWU_F1_WUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF6_SHIFT)) & LLWU_F1_WUF6_MASK)
AnnaBridge 143:86740a56073b 6776 #define LLWU_F1_WUF7_MASK (0x80U)
AnnaBridge 143:86740a56073b 6777 #define LLWU_F1_WUF7_SHIFT (7U)
AnnaBridge 143:86740a56073b 6778 #define LLWU_F1_WUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F1_WUF7_SHIFT)) & LLWU_F1_WUF7_MASK)
AnnaBridge 143:86740a56073b 6779
AnnaBridge 143:86740a56073b 6780 /*! @name F2 - LLWU Flag 2 register */
AnnaBridge 143:86740a56073b 6781 #define LLWU_F2_WUF8_MASK (0x1U)
AnnaBridge 143:86740a56073b 6782 #define LLWU_F2_WUF8_SHIFT (0U)
AnnaBridge 143:86740a56073b 6783 #define LLWU_F2_WUF8(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF8_SHIFT)) & LLWU_F2_WUF8_MASK)
AnnaBridge 143:86740a56073b 6784 #define LLWU_F2_WUF9_MASK (0x2U)
AnnaBridge 143:86740a56073b 6785 #define LLWU_F2_WUF9_SHIFT (1U)
AnnaBridge 143:86740a56073b 6786 #define LLWU_F2_WUF9(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF9_SHIFT)) & LLWU_F2_WUF9_MASK)
AnnaBridge 143:86740a56073b 6787 #define LLWU_F2_WUF10_MASK (0x4U)
AnnaBridge 143:86740a56073b 6788 #define LLWU_F2_WUF10_SHIFT (2U)
AnnaBridge 143:86740a56073b 6789 #define LLWU_F2_WUF10(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF10_SHIFT)) & LLWU_F2_WUF10_MASK)
AnnaBridge 143:86740a56073b 6790 #define LLWU_F2_WUF11_MASK (0x8U)
AnnaBridge 143:86740a56073b 6791 #define LLWU_F2_WUF11_SHIFT (3U)
AnnaBridge 143:86740a56073b 6792 #define LLWU_F2_WUF11(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF11_SHIFT)) & LLWU_F2_WUF11_MASK)
AnnaBridge 143:86740a56073b 6793 #define LLWU_F2_WUF12_MASK (0x10U)
AnnaBridge 143:86740a56073b 6794 #define LLWU_F2_WUF12_SHIFT (4U)
AnnaBridge 143:86740a56073b 6795 #define LLWU_F2_WUF12(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF12_SHIFT)) & LLWU_F2_WUF12_MASK)
AnnaBridge 143:86740a56073b 6796 #define LLWU_F2_WUF13_MASK (0x20U)
AnnaBridge 143:86740a56073b 6797 #define LLWU_F2_WUF13_SHIFT (5U)
AnnaBridge 143:86740a56073b 6798 #define LLWU_F2_WUF13(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF13_SHIFT)) & LLWU_F2_WUF13_MASK)
AnnaBridge 143:86740a56073b 6799 #define LLWU_F2_WUF14_MASK (0x40U)
AnnaBridge 143:86740a56073b 6800 #define LLWU_F2_WUF14_SHIFT (6U)
AnnaBridge 143:86740a56073b 6801 #define LLWU_F2_WUF14(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF14_SHIFT)) & LLWU_F2_WUF14_MASK)
AnnaBridge 143:86740a56073b 6802 #define LLWU_F2_WUF15_MASK (0x80U)
AnnaBridge 143:86740a56073b 6803 #define LLWU_F2_WUF15_SHIFT (7U)
AnnaBridge 143:86740a56073b 6804 #define LLWU_F2_WUF15(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F2_WUF15_SHIFT)) & LLWU_F2_WUF15_MASK)
AnnaBridge 143:86740a56073b 6805
AnnaBridge 143:86740a56073b 6806 /*! @name F3 - LLWU Flag 3 register */
AnnaBridge 143:86740a56073b 6807 #define LLWU_F3_MWUF0_MASK (0x1U)
AnnaBridge 143:86740a56073b 6808 #define LLWU_F3_MWUF0_SHIFT (0U)
AnnaBridge 143:86740a56073b 6809 #define LLWU_F3_MWUF0(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF0_SHIFT)) & LLWU_F3_MWUF0_MASK)
AnnaBridge 143:86740a56073b 6810 #define LLWU_F3_MWUF1_MASK (0x2U)
AnnaBridge 143:86740a56073b 6811 #define LLWU_F3_MWUF1_SHIFT (1U)
AnnaBridge 143:86740a56073b 6812 #define LLWU_F3_MWUF1(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF1_SHIFT)) & LLWU_F3_MWUF1_MASK)
AnnaBridge 143:86740a56073b 6813 #define LLWU_F3_MWUF2_MASK (0x4U)
AnnaBridge 143:86740a56073b 6814 #define LLWU_F3_MWUF2_SHIFT (2U)
AnnaBridge 143:86740a56073b 6815 #define LLWU_F3_MWUF2(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF2_SHIFT)) & LLWU_F3_MWUF2_MASK)
AnnaBridge 143:86740a56073b 6816 #define LLWU_F3_MWUF3_MASK (0x8U)
AnnaBridge 143:86740a56073b 6817 #define LLWU_F3_MWUF3_SHIFT (3U)
AnnaBridge 143:86740a56073b 6818 #define LLWU_F3_MWUF3(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF3_SHIFT)) & LLWU_F3_MWUF3_MASK)
AnnaBridge 143:86740a56073b 6819 #define LLWU_F3_MWUF4_MASK (0x10U)
AnnaBridge 143:86740a56073b 6820 #define LLWU_F3_MWUF4_SHIFT (4U)
AnnaBridge 143:86740a56073b 6821 #define LLWU_F3_MWUF4(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF4_SHIFT)) & LLWU_F3_MWUF4_MASK)
AnnaBridge 143:86740a56073b 6822 #define LLWU_F3_MWUF5_MASK (0x20U)
AnnaBridge 143:86740a56073b 6823 #define LLWU_F3_MWUF5_SHIFT (5U)
AnnaBridge 143:86740a56073b 6824 #define LLWU_F3_MWUF5(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF5_SHIFT)) & LLWU_F3_MWUF5_MASK)
AnnaBridge 143:86740a56073b 6825 #define LLWU_F3_MWUF6_MASK (0x40U)
AnnaBridge 143:86740a56073b 6826 #define LLWU_F3_MWUF6_SHIFT (6U)
AnnaBridge 143:86740a56073b 6827 #define LLWU_F3_MWUF6(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF6_SHIFT)) & LLWU_F3_MWUF6_MASK)
AnnaBridge 143:86740a56073b 6828 #define LLWU_F3_MWUF7_MASK (0x80U)
AnnaBridge 143:86740a56073b 6829 #define LLWU_F3_MWUF7_SHIFT (7U)
AnnaBridge 143:86740a56073b 6830 #define LLWU_F3_MWUF7(x) (((uint8_t)(((uint8_t)(x)) << LLWU_F3_MWUF7_SHIFT)) & LLWU_F3_MWUF7_MASK)
AnnaBridge 143:86740a56073b 6831
AnnaBridge 143:86740a56073b 6832 /*! @name FILT1 - LLWU Pin Filter 1 register */
AnnaBridge 143:86740a56073b 6833 #define LLWU_FILT1_FILTSEL_MASK (0xFU)
AnnaBridge 143:86740a56073b 6834 #define LLWU_FILT1_FILTSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 6835 #define LLWU_FILT1_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTSEL_SHIFT)) & LLWU_FILT1_FILTSEL_MASK)
AnnaBridge 143:86740a56073b 6836 #define LLWU_FILT1_FILTE_MASK (0x60U)
AnnaBridge 143:86740a56073b 6837 #define LLWU_FILT1_FILTE_SHIFT (5U)
AnnaBridge 143:86740a56073b 6838 #define LLWU_FILT1_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTE_SHIFT)) & LLWU_FILT1_FILTE_MASK)
AnnaBridge 143:86740a56073b 6839 #define LLWU_FILT1_FILTF_MASK (0x80U)
AnnaBridge 143:86740a56073b 6840 #define LLWU_FILT1_FILTF_SHIFT (7U)
AnnaBridge 143:86740a56073b 6841 #define LLWU_FILT1_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT1_FILTF_SHIFT)) & LLWU_FILT1_FILTF_MASK)
AnnaBridge 143:86740a56073b 6842
AnnaBridge 143:86740a56073b 6843 /*! @name FILT2 - LLWU Pin Filter 2 register */
AnnaBridge 143:86740a56073b 6844 #define LLWU_FILT2_FILTSEL_MASK (0xFU)
AnnaBridge 143:86740a56073b 6845 #define LLWU_FILT2_FILTSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 6846 #define LLWU_FILT2_FILTSEL(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTSEL_SHIFT)) & LLWU_FILT2_FILTSEL_MASK)
AnnaBridge 143:86740a56073b 6847 #define LLWU_FILT2_FILTE_MASK (0x60U)
AnnaBridge 143:86740a56073b 6848 #define LLWU_FILT2_FILTE_SHIFT (5U)
AnnaBridge 143:86740a56073b 6849 #define LLWU_FILT2_FILTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTE_SHIFT)) & LLWU_FILT2_FILTE_MASK)
AnnaBridge 143:86740a56073b 6850 #define LLWU_FILT2_FILTF_MASK (0x80U)
AnnaBridge 143:86740a56073b 6851 #define LLWU_FILT2_FILTF_SHIFT (7U)
AnnaBridge 143:86740a56073b 6852 #define LLWU_FILT2_FILTF(x) (((uint8_t)(((uint8_t)(x)) << LLWU_FILT2_FILTF_SHIFT)) & LLWU_FILT2_FILTF_MASK)
AnnaBridge 143:86740a56073b 6853
AnnaBridge 143:86740a56073b 6854 /*! @name RST - LLWU Reset Enable register */
AnnaBridge 143:86740a56073b 6855 #define LLWU_RST_RSTFILT_MASK (0x1U)
AnnaBridge 143:86740a56073b 6856 #define LLWU_RST_RSTFILT_SHIFT (0U)
AnnaBridge 143:86740a56073b 6857 #define LLWU_RST_RSTFILT(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_RSTFILT_SHIFT)) & LLWU_RST_RSTFILT_MASK)
AnnaBridge 143:86740a56073b 6858 #define LLWU_RST_LLRSTE_MASK (0x2U)
AnnaBridge 143:86740a56073b 6859 #define LLWU_RST_LLRSTE_SHIFT (1U)
AnnaBridge 143:86740a56073b 6860 #define LLWU_RST_LLRSTE(x) (((uint8_t)(((uint8_t)(x)) << LLWU_RST_LLRSTE_SHIFT)) & LLWU_RST_LLRSTE_MASK)
AnnaBridge 143:86740a56073b 6861
AnnaBridge 143:86740a56073b 6862
AnnaBridge 143:86740a56073b 6863 /*!
AnnaBridge 143:86740a56073b 6864 * @}
AnnaBridge 143:86740a56073b 6865 */ /* end of group LLWU_Register_Masks */
AnnaBridge 143:86740a56073b 6866
AnnaBridge 143:86740a56073b 6867
AnnaBridge 143:86740a56073b 6868 /* LLWU - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 6869 /** Peripheral LLWU base address */
AnnaBridge 143:86740a56073b 6870 #define LLWU_BASE (0x4007C000u)
AnnaBridge 143:86740a56073b 6871 /** Peripheral LLWU base pointer */
AnnaBridge 143:86740a56073b 6872 #define LLWU ((LLWU_Type *)LLWU_BASE)
AnnaBridge 143:86740a56073b 6873 /** Array initializer of LLWU peripheral base addresses */
AnnaBridge 143:86740a56073b 6874 #define LLWU_BASE_ADDRS { LLWU_BASE }
AnnaBridge 143:86740a56073b 6875 /** Array initializer of LLWU peripheral base pointers */
AnnaBridge 143:86740a56073b 6876 #define LLWU_BASE_PTRS { LLWU }
AnnaBridge 143:86740a56073b 6877 /** Interrupt vectors for the LLWU peripheral type */
AnnaBridge 143:86740a56073b 6878 #define LLWU_IRQS { LLWU_IRQn }
AnnaBridge 143:86740a56073b 6879
AnnaBridge 143:86740a56073b 6880 /*!
AnnaBridge 143:86740a56073b 6881 * @}
AnnaBridge 143:86740a56073b 6882 */ /* end of group LLWU_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 6883
AnnaBridge 143:86740a56073b 6884
AnnaBridge 143:86740a56073b 6885 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6886 -- LPTMR Peripheral Access Layer
AnnaBridge 143:86740a56073b 6887 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6888
AnnaBridge 143:86740a56073b 6889 /*!
AnnaBridge 143:86740a56073b 6890 * @addtogroup LPTMR_Peripheral_Access_Layer LPTMR Peripheral Access Layer
AnnaBridge 143:86740a56073b 6891 * @{
AnnaBridge 143:86740a56073b 6892 */
AnnaBridge 143:86740a56073b 6893
AnnaBridge 143:86740a56073b 6894 /** LPTMR - Register Layout Typedef */
AnnaBridge 143:86740a56073b 6895 typedef struct {
AnnaBridge 143:86740a56073b 6896 __IO uint32_t CSR; /**< Low Power Timer Control Status Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 6897 __IO uint32_t PSR; /**< Low Power Timer Prescale Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 6898 __IO uint32_t CMR; /**< Low Power Timer Compare Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 6899 __IO uint32_t CNR; /**< Low Power Timer Counter Register, offset: 0xC */
AnnaBridge 143:86740a56073b 6900 } LPTMR_Type;
AnnaBridge 143:86740a56073b 6901
AnnaBridge 143:86740a56073b 6902 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6903 -- LPTMR Register Masks
AnnaBridge 143:86740a56073b 6904 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6905
AnnaBridge 143:86740a56073b 6906 /*!
AnnaBridge 143:86740a56073b 6907 * @addtogroup LPTMR_Register_Masks LPTMR Register Masks
AnnaBridge 143:86740a56073b 6908 * @{
AnnaBridge 143:86740a56073b 6909 */
AnnaBridge 143:86740a56073b 6910
AnnaBridge 143:86740a56073b 6911 /*! @name CSR - Low Power Timer Control Status Register */
AnnaBridge 143:86740a56073b 6912 #define LPTMR_CSR_TEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 6913 #define LPTMR_CSR_TEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 6914 #define LPTMR_CSR_TEN(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TEN_SHIFT)) & LPTMR_CSR_TEN_MASK)
AnnaBridge 143:86740a56073b 6915 #define LPTMR_CSR_TMS_MASK (0x2U)
AnnaBridge 143:86740a56073b 6916 #define LPTMR_CSR_TMS_SHIFT (1U)
AnnaBridge 143:86740a56073b 6917 #define LPTMR_CSR_TMS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TMS_SHIFT)) & LPTMR_CSR_TMS_MASK)
AnnaBridge 143:86740a56073b 6918 #define LPTMR_CSR_TFC_MASK (0x4U)
AnnaBridge 143:86740a56073b 6919 #define LPTMR_CSR_TFC_SHIFT (2U)
AnnaBridge 143:86740a56073b 6920 #define LPTMR_CSR_TFC(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TFC_SHIFT)) & LPTMR_CSR_TFC_MASK)
AnnaBridge 143:86740a56073b 6921 #define LPTMR_CSR_TPP_MASK (0x8U)
AnnaBridge 143:86740a56073b 6922 #define LPTMR_CSR_TPP_SHIFT (3U)
AnnaBridge 143:86740a56073b 6923 #define LPTMR_CSR_TPP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPP_SHIFT)) & LPTMR_CSR_TPP_MASK)
AnnaBridge 143:86740a56073b 6924 #define LPTMR_CSR_TPS_MASK (0x30U)
AnnaBridge 143:86740a56073b 6925 #define LPTMR_CSR_TPS_SHIFT (4U)
AnnaBridge 143:86740a56073b 6926 #define LPTMR_CSR_TPS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TPS_SHIFT)) & LPTMR_CSR_TPS_MASK)
AnnaBridge 143:86740a56073b 6927 #define LPTMR_CSR_TIE_MASK (0x40U)
AnnaBridge 143:86740a56073b 6928 #define LPTMR_CSR_TIE_SHIFT (6U)
AnnaBridge 143:86740a56073b 6929 #define LPTMR_CSR_TIE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TIE_SHIFT)) & LPTMR_CSR_TIE_MASK)
AnnaBridge 143:86740a56073b 6930 #define LPTMR_CSR_TCF_MASK (0x80U)
AnnaBridge 143:86740a56073b 6931 #define LPTMR_CSR_TCF_SHIFT (7U)
AnnaBridge 143:86740a56073b 6932 #define LPTMR_CSR_TCF(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CSR_TCF_SHIFT)) & LPTMR_CSR_TCF_MASK)
AnnaBridge 143:86740a56073b 6933
AnnaBridge 143:86740a56073b 6934 /*! @name PSR - Low Power Timer Prescale Register */
AnnaBridge 143:86740a56073b 6935 #define LPTMR_PSR_PCS_MASK (0x3U)
AnnaBridge 143:86740a56073b 6936 #define LPTMR_PSR_PCS_SHIFT (0U)
AnnaBridge 143:86740a56073b 6937 #define LPTMR_PSR_PCS(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PCS_SHIFT)) & LPTMR_PSR_PCS_MASK)
AnnaBridge 143:86740a56073b 6938 #define LPTMR_PSR_PBYP_MASK (0x4U)
AnnaBridge 143:86740a56073b 6939 #define LPTMR_PSR_PBYP_SHIFT (2U)
AnnaBridge 143:86740a56073b 6940 #define LPTMR_PSR_PBYP(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PBYP_SHIFT)) & LPTMR_PSR_PBYP_MASK)
AnnaBridge 143:86740a56073b 6941 #define LPTMR_PSR_PRESCALE_MASK (0x78U)
AnnaBridge 143:86740a56073b 6942 #define LPTMR_PSR_PRESCALE_SHIFT (3U)
AnnaBridge 143:86740a56073b 6943 #define LPTMR_PSR_PRESCALE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_PSR_PRESCALE_SHIFT)) & LPTMR_PSR_PRESCALE_MASK)
AnnaBridge 143:86740a56073b 6944
AnnaBridge 143:86740a56073b 6945 /*! @name CMR - Low Power Timer Compare Register */
AnnaBridge 143:86740a56073b 6946 #define LPTMR_CMR_COMPARE_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 6947 #define LPTMR_CMR_COMPARE_SHIFT (0U)
AnnaBridge 143:86740a56073b 6948 #define LPTMR_CMR_COMPARE(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CMR_COMPARE_SHIFT)) & LPTMR_CMR_COMPARE_MASK)
AnnaBridge 143:86740a56073b 6949
AnnaBridge 143:86740a56073b 6950 /*! @name CNR - Low Power Timer Counter Register */
AnnaBridge 143:86740a56073b 6951 #define LPTMR_CNR_COUNTER_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 6952 #define LPTMR_CNR_COUNTER_SHIFT (0U)
AnnaBridge 143:86740a56073b 6953 #define LPTMR_CNR_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << LPTMR_CNR_COUNTER_SHIFT)) & LPTMR_CNR_COUNTER_MASK)
AnnaBridge 143:86740a56073b 6954
AnnaBridge 143:86740a56073b 6955
AnnaBridge 143:86740a56073b 6956 /*!
AnnaBridge 143:86740a56073b 6957 * @}
AnnaBridge 143:86740a56073b 6958 */ /* end of group LPTMR_Register_Masks */
AnnaBridge 143:86740a56073b 6959
AnnaBridge 143:86740a56073b 6960
AnnaBridge 143:86740a56073b 6961 /* LPTMR - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 6962 /** Peripheral LPTMR0 base address */
AnnaBridge 143:86740a56073b 6963 #define LPTMR0_BASE (0x40040000u)
AnnaBridge 143:86740a56073b 6964 /** Peripheral LPTMR0 base pointer */
AnnaBridge 143:86740a56073b 6965 #define LPTMR0 ((LPTMR_Type *)LPTMR0_BASE)
AnnaBridge 143:86740a56073b 6966 /** Array initializer of LPTMR peripheral base addresses */
AnnaBridge 143:86740a56073b 6967 #define LPTMR_BASE_ADDRS { LPTMR0_BASE }
AnnaBridge 143:86740a56073b 6968 /** Array initializer of LPTMR peripheral base pointers */
AnnaBridge 143:86740a56073b 6969 #define LPTMR_BASE_PTRS { LPTMR0 }
AnnaBridge 143:86740a56073b 6970 /** Interrupt vectors for the LPTMR peripheral type */
AnnaBridge 143:86740a56073b 6971 #define LPTMR_IRQS { LPTMR0_IRQn }
AnnaBridge 143:86740a56073b 6972
AnnaBridge 143:86740a56073b 6973 /*!
AnnaBridge 143:86740a56073b 6974 * @}
AnnaBridge 143:86740a56073b 6975 */ /* end of group LPTMR_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 6976
AnnaBridge 143:86740a56073b 6977
AnnaBridge 143:86740a56073b 6978 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 6979 -- MCG Peripheral Access Layer
AnnaBridge 143:86740a56073b 6980 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 6981
AnnaBridge 143:86740a56073b 6982 /*!
AnnaBridge 143:86740a56073b 6983 * @addtogroup MCG_Peripheral_Access_Layer MCG Peripheral Access Layer
AnnaBridge 143:86740a56073b 6984 * @{
AnnaBridge 143:86740a56073b 6985 */
AnnaBridge 143:86740a56073b 6986
AnnaBridge 143:86740a56073b 6987 /** MCG - Register Layout Typedef */
AnnaBridge 143:86740a56073b 6988 typedef struct {
AnnaBridge 143:86740a56073b 6989 __IO uint8_t C1; /**< MCG Control 1 Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 6990 __IO uint8_t C2; /**< MCG Control 2 Register, offset: 0x1 */
AnnaBridge 143:86740a56073b 6991 __IO uint8_t C3; /**< MCG Control 3 Register, offset: 0x2 */
AnnaBridge 143:86740a56073b 6992 __IO uint8_t C4; /**< MCG Control 4 Register, offset: 0x3 */
AnnaBridge 143:86740a56073b 6993 __IO uint8_t C5; /**< MCG Control 5 Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 6994 __IO uint8_t C6; /**< MCG Control 6 Register, offset: 0x5 */
AnnaBridge 143:86740a56073b 6995 __IO uint8_t S; /**< MCG Status Register, offset: 0x6 */
AnnaBridge 143:86740a56073b 6996 uint8_t RESERVED_0[1];
AnnaBridge 143:86740a56073b 6997 __IO uint8_t SC; /**< MCG Status and Control Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 6998 uint8_t RESERVED_1[1];
AnnaBridge 143:86740a56073b 6999 __IO uint8_t ATCVH; /**< MCG Auto Trim Compare Value High Register, offset: 0xA */
AnnaBridge 143:86740a56073b 7000 __IO uint8_t ATCVL; /**< MCG Auto Trim Compare Value Low Register, offset: 0xB */
AnnaBridge 143:86740a56073b 7001 __IO uint8_t C7; /**< MCG Control 7 Register, offset: 0xC */
AnnaBridge 143:86740a56073b 7002 __IO uint8_t C8; /**< MCG Control 8 Register, offset: 0xD */
AnnaBridge 143:86740a56073b 7003 } MCG_Type;
AnnaBridge 143:86740a56073b 7004
AnnaBridge 143:86740a56073b 7005 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7006 -- MCG Register Masks
AnnaBridge 143:86740a56073b 7007 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7008
AnnaBridge 143:86740a56073b 7009 /*!
AnnaBridge 143:86740a56073b 7010 * @addtogroup MCG_Register_Masks MCG Register Masks
AnnaBridge 143:86740a56073b 7011 * @{
AnnaBridge 143:86740a56073b 7012 */
AnnaBridge 143:86740a56073b 7013
AnnaBridge 143:86740a56073b 7014 /*! @name C1 - MCG Control 1 Register */
AnnaBridge 143:86740a56073b 7015 #define MCG_C1_IREFSTEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 7016 #define MCG_C1_IREFSTEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 7017 #define MCG_C1_IREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFSTEN_SHIFT)) & MCG_C1_IREFSTEN_MASK)
AnnaBridge 143:86740a56073b 7018 #define MCG_C1_IRCLKEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 7019 #define MCG_C1_IRCLKEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 7020 #define MCG_C1_IRCLKEN(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IRCLKEN_SHIFT)) & MCG_C1_IRCLKEN_MASK)
AnnaBridge 143:86740a56073b 7021 #define MCG_C1_IREFS_MASK (0x4U)
AnnaBridge 143:86740a56073b 7022 #define MCG_C1_IREFS_SHIFT (2U)
AnnaBridge 143:86740a56073b 7023 #define MCG_C1_IREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_IREFS_SHIFT)) & MCG_C1_IREFS_MASK)
AnnaBridge 143:86740a56073b 7024 #define MCG_C1_FRDIV_MASK (0x38U)
AnnaBridge 143:86740a56073b 7025 #define MCG_C1_FRDIV_SHIFT (3U)
AnnaBridge 143:86740a56073b 7026 #define MCG_C1_FRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_FRDIV_SHIFT)) & MCG_C1_FRDIV_MASK)
AnnaBridge 143:86740a56073b 7027 #define MCG_C1_CLKS_MASK (0xC0U)
AnnaBridge 143:86740a56073b 7028 #define MCG_C1_CLKS_SHIFT (6U)
AnnaBridge 143:86740a56073b 7029 #define MCG_C1_CLKS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C1_CLKS_SHIFT)) & MCG_C1_CLKS_MASK)
AnnaBridge 143:86740a56073b 7030
AnnaBridge 143:86740a56073b 7031 /*! @name C2 - MCG Control 2 Register */
AnnaBridge 143:86740a56073b 7032 #define MCG_C2_IRCS_MASK (0x1U)
AnnaBridge 143:86740a56073b 7033 #define MCG_C2_IRCS_SHIFT (0U)
AnnaBridge 143:86740a56073b 7034 #define MCG_C2_IRCS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_IRCS_SHIFT)) & MCG_C2_IRCS_MASK)
AnnaBridge 143:86740a56073b 7035 #define MCG_C2_LP_MASK (0x2U)
AnnaBridge 143:86740a56073b 7036 #define MCG_C2_LP_SHIFT (1U)
AnnaBridge 143:86740a56073b 7037 #define MCG_C2_LP(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LP_SHIFT)) & MCG_C2_LP_MASK)
AnnaBridge 143:86740a56073b 7038 #define MCG_C2_EREFS_MASK (0x4U)
AnnaBridge 143:86740a56073b 7039 #define MCG_C2_EREFS_SHIFT (2U)
AnnaBridge 143:86740a56073b 7040 #define MCG_C2_EREFS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_EREFS_SHIFT)) & MCG_C2_EREFS_MASK)
AnnaBridge 143:86740a56073b 7041 #define MCG_C2_HGO_MASK (0x8U)
AnnaBridge 143:86740a56073b 7042 #define MCG_C2_HGO_SHIFT (3U)
AnnaBridge 143:86740a56073b 7043 #define MCG_C2_HGO(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_HGO_SHIFT)) & MCG_C2_HGO_MASK)
AnnaBridge 143:86740a56073b 7044 #define MCG_C2_RANGE_MASK (0x30U)
AnnaBridge 143:86740a56073b 7045 #define MCG_C2_RANGE_SHIFT (4U)
AnnaBridge 143:86740a56073b 7046 #define MCG_C2_RANGE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_RANGE_SHIFT)) & MCG_C2_RANGE_MASK)
AnnaBridge 143:86740a56073b 7047 #define MCG_C2_FCFTRIM_MASK (0x40U)
AnnaBridge 143:86740a56073b 7048 #define MCG_C2_FCFTRIM_SHIFT (6U)
AnnaBridge 143:86740a56073b 7049 #define MCG_C2_FCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_FCFTRIM_SHIFT)) & MCG_C2_FCFTRIM_MASK)
AnnaBridge 143:86740a56073b 7050 #define MCG_C2_LOCRE0_MASK (0x80U)
AnnaBridge 143:86740a56073b 7051 #define MCG_C2_LOCRE0_SHIFT (7U)
AnnaBridge 143:86740a56073b 7052 #define MCG_C2_LOCRE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C2_LOCRE0_SHIFT)) & MCG_C2_LOCRE0_MASK)
AnnaBridge 143:86740a56073b 7053
AnnaBridge 143:86740a56073b 7054 /*! @name C3 - MCG Control 3 Register */
AnnaBridge 143:86740a56073b 7055 #define MCG_C3_SCTRIM_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7056 #define MCG_C3_SCTRIM_SHIFT (0U)
AnnaBridge 143:86740a56073b 7057 #define MCG_C3_SCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C3_SCTRIM_SHIFT)) & MCG_C3_SCTRIM_MASK)
AnnaBridge 143:86740a56073b 7058
AnnaBridge 143:86740a56073b 7059 /*! @name C4 - MCG Control 4 Register */
AnnaBridge 143:86740a56073b 7060 #define MCG_C4_SCFTRIM_MASK (0x1U)
AnnaBridge 143:86740a56073b 7061 #define MCG_C4_SCFTRIM_SHIFT (0U)
AnnaBridge 143:86740a56073b 7062 #define MCG_C4_SCFTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_SCFTRIM_SHIFT)) & MCG_C4_SCFTRIM_MASK)
AnnaBridge 143:86740a56073b 7063 #define MCG_C4_FCTRIM_MASK (0x1EU)
AnnaBridge 143:86740a56073b 7064 #define MCG_C4_FCTRIM_SHIFT (1U)
AnnaBridge 143:86740a56073b 7065 #define MCG_C4_FCTRIM(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_FCTRIM_SHIFT)) & MCG_C4_FCTRIM_MASK)
AnnaBridge 143:86740a56073b 7066 #define MCG_C4_DRST_DRS_MASK (0x60U)
AnnaBridge 143:86740a56073b 7067 #define MCG_C4_DRST_DRS_SHIFT (5U)
AnnaBridge 143:86740a56073b 7068 #define MCG_C4_DRST_DRS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DRST_DRS_SHIFT)) & MCG_C4_DRST_DRS_MASK)
AnnaBridge 143:86740a56073b 7069 #define MCG_C4_DMX32_MASK (0x80U)
AnnaBridge 143:86740a56073b 7070 #define MCG_C4_DMX32_SHIFT (7U)
AnnaBridge 143:86740a56073b 7071 #define MCG_C4_DMX32(x) (((uint8_t)(((uint8_t)(x)) << MCG_C4_DMX32_SHIFT)) & MCG_C4_DMX32_MASK)
AnnaBridge 143:86740a56073b 7072
AnnaBridge 143:86740a56073b 7073 /*! @name C5 - MCG Control 5 Register */
AnnaBridge 143:86740a56073b 7074 #define MCG_C5_PRDIV0_MASK (0x1FU)
AnnaBridge 143:86740a56073b 7075 #define MCG_C5_PRDIV0_SHIFT (0U)
AnnaBridge 143:86740a56073b 7076 #define MCG_C5_PRDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PRDIV0_SHIFT)) & MCG_C5_PRDIV0_MASK)
AnnaBridge 143:86740a56073b 7077 #define MCG_C5_PLLSTEN0_MASK (0x20U)
AnnaBridge 143:86740a56073b 7078 #define MCG_C5_PLLSTEN0_SHIFT (5U)
AnnaBridge 143:86740a56073b 7079 #define MCG_C5_PLLSTEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLSTEN0_SHIFT)) & MCG_C5_PLLSTEN0_MASK)
AnnaBridge 143:86740a56073b 7080 #define MCG_C5_PLLCLKEN0_MASK (0x40U)
AnnaBridge 143:86740a56073b 7081 #define MCG_C5_PLLCLKEN0_SHIFT (6U)
AnnaBridge 143:86740a56073b 7082 #define MCG_C5_PLLCLKEN0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C5_PLLCLKEN0_SHIFT)) & MCG_C5_PLLCLKEN0_MASK)
AnnaBridge 143:86740a56073b 7083
AnnaBridge 143:86740a56073b 7084 /*! @name C6 - MCG Control 6 Register */
AnnaBridge 143:86740a56073b 7085 #define MCG_C6_VDIV0_MASK (0x1FU)
AnnaBridge 143:86740a56073b 7086 #define MCG_C6_VDIV0_SHIFT (0U)
AnnaBridge 143:86740a56073b 7087 #define MCG_C6_VDIV0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_VDIV0_SHIFT)) & MCG_C6_VDIV0_MASK)
AnnaBridge 143:86740a56073b 7088 #define MCG_C6_CME0_MASK (0x20U)
AnnaBridge 143:86740a56073b 7089 #define MCG_C6_CME0_SHIFT (5U)
AnnaBridge 143:86740a56073b 7090 #define MCG_C6_CME0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_CME0_SHIFT)) & MCG_C6_CME0_MASK)
AnnaBridge 143:86740a56073b 7091 #define MCG_C6_PLLS_MASK (0x40U)
AnnaBridge 143:86740a56073b 7092 #define MCG_C6_PLLS_SHIFT (6U)
AnnaBridge 143:86740a56073b 7093 #define MCG_C6_PLLS(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_PLLS_SHIFT)) & MCG_C6_PLLS_MASK)
AnnaBridge 143:86740a56073b 7094 #define MCG_C6_LOLIE0_MASK (0x80U)
AnnaBridge 143:86740a56073b 7095 #define MCG_C6_LOLIE0_SHIFT (7U)
AnnaBridge 143:86740a56073b 7096 #define MCG_C6_LOLIE0(x) (((uint8_t)(((uint8_t)(x)) << MCG_C6_LOLIE0_SHIFT)) & MCG_C6_LOLIE0_MASK)
AnnaBridge 143:86740a56073b 7097
AnnaBridge 143:86740a56073b 7098 /*! @name S - MCG Status Register */
AnnaBridge 143:86740a56073b 7099 #define MCG_S_IRCST_MASK (0x1U)
AnnaBridge 143:86740a56073b 7100 #define MCG_S_IRCST_SHIFT (0U)
AnnaBridge 143:86740a56073b 7101 #define MCG_S_IRCST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IRCST_SHIFT)) & MCG_S_IRCST_MASK)
AnnaBridge 143:86740a56073b 7102 #define MCG_S_OSCINIT0_MASK (0x2U)
AnnaBridge 143:86740a56073b 7103 #define MCG_S_OSCINIT0_SHIFT (1U)
AnnaBridge 143:86740a56073b 7104 #define MCG_S_OSCINIT0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_OSCINIT0_SHIFT)) & MCG_S_OSCINIT0_MASK)
AnnaBridge 143:86740a56073b 7105 #define MCG_S_CLKST_MASK (0xCU)
AnnaBridge 143:86740a56073b 7106 #define MCG_S_CLKST_SHIFT (2U)
AnnaBridge 143:86740a56073b 7107 #define MCG_S_CLKST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_CLKST_SHIFT)) & MCG_S_CLKST_MASK)
AnnaBridge 143:86740a56073b 7108 #define MCG_S_IREFST_MASK (0x10U)
AnnaBridge 143:86740a56073b 7109 #define MCG_S_IREFST_SHIFT (4U)
AnnaBridge 143:86740a56073b 7110 #define MCG_S_IREFST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_IREFST_SHIFT)) & MCG_S_IREFST_MASK)
AnnaBridge 143:86740a56073b 7111 #define MCG_S_PLLST_MASK (0x20U)
AnnaBridge 143:86740a56073b 7112 #define MCG_S_PLLST_SHIFT (5U)
AnnaBridge 143:86740a56073b 7113 #define MCG_S_PLLST(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_PLLST_SHIFT)) & MCG_S_PLLST_MASK)
AnnaBridge 143:86740a56073b 7114 #define MCG_S_LOCK0_MASK (0x40U)
AnnaBridge 143:86740a56073b 7115 #define MCG_S_LOCK0_SHIFT (6U)
AnnaBridge 143:86740a56073b 7116 #define MCG_S_LOCK0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOCK0_SHIFT)) & MCG_S_LOCK0_MASK)
AnnaBridge 143:86740a56073b 7117 #define MCG_S_LOLS0_MASK (0x80U)
AnnaBridge 143:86740a56073b 7118 #define MCG_S_LOLS0_SHIFT (7U)
AnnaBridge 143:86740a56073b 7119 #define MCG_S_LOLS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_S_LOLS0_SHIFT)) & MCG_S_LOLS0_MASK)
AnnaBridge 143:86740a56073b 7120
AnnaBridge 143:86740a56073b 7121 /*! @name SC - MCG Status and Control Register */
AnnaBridge 143:86740a56073b 7122 #define MCG_SC_LOCS0_MASK (0x1U)
AnnaBridge 143:86740a56073b 7123 #define MCG_SC_LOCS0_SHIFT (0U)
AnnaBridge 143:86740a56073b 7124 #define MCG_SC_LOCS0(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_LOCS0_SHIFT)) & MCG_SC_LOCS0_MASK)
AnnaBridge 143:86740a56073b 7125 #define MCG_SC_FCRDIV_MASK (0xEU)
AnnaBridge 143:86740a56073b 7126 #define MCG_SC_FCRDIV_SHIFT (1U)
AnnaBridge 143:86740a56073b 7127 #define MCG_SC_FCRDIV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FCRDIV_SHIFT)) & MCG_SC_FCRDIV_MASK)
AnnaBridge 143:86740a56073b 7128 #define MCG_SC_FLTPRSRV_MASK (0x10U)
AnnaBridge 143:86740a56073b 7129 #define MCG_SC_FLTPRSRV_SHIFT (4U)
AnnaBridge 143:86740a56073b 7130 #define MCG_SC_FLTPRSRV(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_FLTPRSRV_SHIFT)) & MCG_SC_FLTPRSRV_MASK)
AnnaBridge 143:86740a56073b 7131 #define MCG_SC_ATMF_MASK (0x20U)
AnnaBridge 143:86740a56073b 7132 #define MCG_SC_ATMF_SHIFT (5U)
AnnaBridge 143:86740a56073b 7133 #define MCG_SC_ATMF(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMF_SHIFT)) & MCG_SC_ATMF_MASK)
AnnaBridge 143:86740a56073b 7134 #define MCG_SC_ATMS_MASK (0x40U)
AnnaBridge 143:86740a56073b 7135 #define MCG_SC_ATMS_SHIFT (6U)
AnnaBridge 143:86740a56073b 7136 #define MCG_SC_ATMS(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATMS_SHIFT)) & MCG_SC_ATMS_MASK)
AnnaBridge 143:86740a56073b 7137 #define MCG_SC_ATME_MASK (0x80U)
AnnaBridge 143:86740a56073b 7138 #define MCG_SC_ATME_SHIFT (7U)
AnnaBridge 143:86740a56073b 7139 #define MCG_SC_ATME(x) (((uint8_t)(((uint8_t)(x)) << MCG_SC_ATME_SHIFT)) & MCG_SC_ATME_MASK)
AnnaBridge 143:86740a56073b 7140
AnnaBridge 143:86740a56073b 7141 /*! @name ATCVH - MCG Auto Trim Compare Value High Register */
AnnaBridge 143:86740a56073b 7142 #define MCG_ATCVH_ATCVH_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7143 #define MCG_ATCVH_ATCVH_SHIFT (0U)
AnnaBridge 143:86740a56073b 7144 #define MCG_ATCVH_ATCVH(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVH_ATCVH_SHIFT)) & MCG_ATCVH_ATCVH_MASK)
AnnaBridge 143:86740a56073b 7145
AnnaBridge 143:86740a56073b 7146 /*! @name ATCVL - MCG Auto Trim Compare Value Low Register */
AnnaBridge 143:86740a56073b 7147 #define MCG_ATCVL_ATCVL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7148 #define MCG_ATCVL_ATCVL_SHIFT (0U)
AnnaBridge 143:86740a56073b 7149 #define MCG_ATCVL_ATCVL(x) (((uint8_t)(((uint8_t)(x)) << MCG_ATCVL_ATCVL_SHIFT)) & MCG_ATCVL_ATCVL_MASK)
AnnaBridge 143:86740a56073b 7150
AnnaBridge 143:86740a56073b 7151 /*! @name C7 - MCG Control 7 Register */
AnnaBridge 143:86740a56073b 7152 #define MCG_C7_OSCSEL_MASK (0x3U)
AnnaBridge 143:86740a56073b 7153 #define MCG_C7_OSCSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 7154 #define MCG_C7_OSCSEL(x) (((uint8_t)(((uint8_t)(x)) << MCG_C7_OSCSEL_SHIFT)) & MCG_C7_OSCSEL_MASK)
AnnaBridge 143:86740a56073b 7155
AnnaBridge 143:86740a56073b 7156 /*! @name C8 - MCG Control 8 Register */
AnnaBridge 143:86740a56073b 7157 #define MCG_C8_LOCS1_MASK (0x1U)
AnnaBridge 143:86740a56073b 7158 #define MCG_C8_LOCS1_SHIFT (0U)
AnnaBridge 143:86740a56073b 7159 #define MCG_C8_LOCS1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCS1_SHIFT)) & MCG_C8_LOCS1_MASK)
AnnaBridge 143:86740a56073b 7160 #define MCG_C8_CME1_MASK (0x20U)
AnnaBridge 143:86740a56073b 7161 #define MCG_C8_CME1_SHIFT (5U)
AnnaBridge 143:86740a56073b 7162 #define MCG_C8_CME1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_CME1_SHIFT)) & MCG_C8_CME1_MASK)
AnnaBridge 143:86740a56073b 7163 #define MCG_C8_LOLRE_MASK (0x40U)
AnnaBridge 143:86740a56073b 7164 #define MCG_C8_LOLRE_SHIFT (6U)
AnnaBridge 143:86740a56073b 7165 #define MCG_C8_LOLRE(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOLRE_SHIFT)) & MCG_C8_LOLRE_MASK)
AnnaBridge 143:86740a56073b 7166 #define MCG_C8_LOCRE1_MASK (0x80U)
AnnaBridge 143:86740a56073b 7167 #define MCG_C8_LOCRE1_SHIFT (7U)
AnnaBridge 143:86740a56073b 7168 #define MCG_C8_LOCRE1(x) (((uint8_t)(((uint8_t)(x)) << MCG_C8_LOCRE1_SHIFT)) & MCG_C8_LOCRE1_MASK)
AnnaBridge 143:86740a56073b 7169
AnnaBridge 143:86740a56073b 7170
AnnaBridge 143:86740a56073b 7171 /*!
AnnaBridge 143:86740a56073b 7172 * @}
AnnaBridge 143:86740a56073b 7173 */ /* end of group MCG_Register_Masks */
AnnaBridge 143:86740a56073b 7174
AnnaBridge 143:86740a56073b 7175
AnnaBridge 143:86740a56073b 7176 /* MCG - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 7177 /** Peripheral MCG base address */
AnnaBridge 143:86740a56073b 7178 #define MCG_BASE (0x40064000u)
AnnaBridge 143:86740a56073b 7179 /** Peripheral MCG base pointer */
AnnaBridge 143:86740a56073b 7180 #define MCG ((MCG_Type *)MCG_BASE)
AnnaBridge 143:86740a56073b 7181 /** Array initializer of MCG peripheral base addresses */
AnnaBridge 143:86740a56073b 7182 #define MCG_BASE_ADDRS { MCG_BASE }
AnnaBridge 143:86740a56073b 7183 /** Array initializer of MCG peripheral base pointers */
AnnaBridge 143:86740a56073b 7184 #define MCG_BASE_PTRS { MCG }
AnnaBridge 143:86740a56073b 7185
AnnaBridge 143:86740a56073b 7186 /*!
AnnaBridge 143:86740a56073b 7187 * @}
AnnaBridge 143:86740a56073b 7188 */ /* end of group MCG_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 7189
AnnaBridge 143:86740a56073b 7190
AnnaBridge 143:86740a56073b 7191 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7192 -- MCM Peripheral Access Layer
AnnaBridge 143:86740a56073b 7193 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7194
AnnaBridge 143:86740a56073b 7195 /*!
AnnaBridge 143:86740a56073b 7196 * @addtogroup MCM_Peripheral_Access_Layer MCM Peripheral Access Layer
AnnaBridge 143:86740a56073b 7197 * @{
AnnaBridge 143:86740a56073b 7198 */
AnnaBridge 143:86740a56073b 7199
AnnaBridge 143:86740a56073b 7200 /** MCM - Register Layout Typedef */
AnnaBridge 143:86740a56073b 7201 typedef struct {
AnnaBridge 143:86740a56073b 7202 uint8_t RESERVED_0[8];
AnnaBridge 143:86740a56073b 7203 __I uint16_t PLASC; /**< Crossbar Switch (AXBS) Slave Configuration, offset: 0x8 */
AnnaBridge 143:86740a56073b 7204 __I uint16_t PLAMC; /**< Crossbar Switch (AXBS) Master Configuration, offset: 0xA */
AnnaBridge 143:86740a56073b 7205 __IO uint32_t CR; /**< Control Register, offset: 0xC */
AnnaBridge 143:86740a56073b 7206 __IO uint32_t ISCR; /**< Interrupt Status Register, offset: 0x10 */
AnnaBridge 143:86740a56073b 7207 __IO uint32_t ETBCC; /**< ETB Counter Control register, offset: 0x14 */
AnnaBridge 143:86740a56073b 7208 __IO uint32_t ETBRL; /**< ETB Reload register, offset: 0x18 */
AnnaBridge 143:86740a56073b 7209 __I uint32_t ETBCNT; /**< ETB Counter Value register, offset: 0x1C */
AnnaBridge 143:86740a56073b 7210 uint8_t RESERVED_1[16];
AnnaBridge 143:86740a56073b 7211 __IO uint32_t PID; /**< Process ID register, offset: 0x30 */
AnnaBridge 143:86740a56073b 7212 } MCM_Type;
AnnaBridge 143:86740a56073b 7213
AnnaBridge 143:86740a56073b 7214 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7215 -- MCM Register Masks
AnnaBridge 143:86740a56073b 7216 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7217
AnnaBridge 143:86740a56073b 7218 /*!
AnnaBridge 143:86740a56073b 7219 * @addtogroup MCM_Register_Masks MCM Register Masks
AnnaBridge 143:86740a56073b 7220 * @{
AnnaBridge 143:86740a56073b 7221 */
AnnaBridge 143:86740a56073b 7222
AnnaBridge 143:86740a56073b 7223 /*! @name PLASC - Crossbar Switch (AXBS) Slave Configuration */
AnnaBridge 143:86740a56073b 7224 #define MCM_PLASC_ASC_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7225 #define MCM_PLASC_ASC_SHIFT (0U)
AnnaBridge 143:86740a56073b 7226 #define MCM_PLASC_ASC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLASC_ASC_SHIFT)) & MCM_PLASC_ASC_MASK)
AnnaBridge 143:86740a56073b 7227
AnnaBridge 143:86740a56073b 7228 /*! @name PLAMC - Crossbar Switch (AXBS) Master Configuration */
AnnaBridge 143:86740a56073b 7229 #define MCM_PLAMC_AMC_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7230 #define MCM_PLAMC_AMC_SHIFT (0U)
AnnaBridge 143:86740a56073b 7231 #define MCM_PLAMC_AMC(x) (((uint16_t)(((uint16_t)(x)) << MCM_PLAMC_AMC_SHIFT)) & MCM_PLAMC_AMC_MASK)
AnnaBridge 143:86740a56073b 7232
AnnaBridge 143:86740a56073b 7233 /*! @name CR - Control Register */
AnnaBridge 143:86740a56073b 7234 #define MCM_CR_SRAMUAP_MASK (0x3000000U)
AnnaBridge 143:86740a56073b 7235 #define MCM_CR_SRAMUAP_SHIFT (24U)
AnnaBridge 143:86740a56073b 7236 #define MCM_CR_SRAMUAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUAP_SHIFT)) & MCM_CR_SRAMUAP_MASK)
AnnaBridge 143:86740a56073b 7237 #define MCM_CR_SRAMUWP_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 7238 #define MCM_CR_SRAMUWP_SHIFT (26U)
AnnaBridge 143:86740a56073b 7239 #define MCM_CR_SRAMUWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMUWP_SHIFT)) & MCM_CR_SRAMUWP_MASK)
AnnaBridge 143:86740a56073b 7240 #define MCM_CR_SRAMLAP_MASK (0x30000000U)
AnnaBridge 143:86740a56073b 7241 #define MCM_CR_SRAMLAP_SHIFT (28U)
AnnaBridge 143:86740a56073b 7242 #define MCM_CR_SRAMLAP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLAP_SHIFT)) & MCM_CR_SRAMLAP_MASK)
AnnaBridge 143:86740a56073b 7243 #define MCM_CR_SRAMLWP_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 7244 #define MCM_CR_SRAMLWP_SHIFT (30U)
AnnaBridge 143:86740a56073b 7245 #define MCM_CR_SRAMLWP(x) (((uint32_t)(((uint32_t)(x)) << MCM_CR_SRAMLWP_SHIFT)) & MCM_CR_SRAMLWP_MASK)
AnnaBridge 143:86740a56073b 7246
AnnaBridge 143:86740a56073b 7247 /*! @name ISCR - Interrupt Status Register */
AnnaBridge 143:86740a56073b 7248 #define MCM_ISCR_IRQ_MASK (0x2U)
AnnaBridge 143:86740a56073b 7249 #define MCM_ISCR_IRQ_SHIFT (1U)
AnnaBridge 143:86740a56073b 7250 #define MCM_ISCR_IRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_IRQ_SHIFT)) & MCM_ISCR_IRQ_MASK)
AnnaBridge 143:86740a56073b 7251 #define MCM_ISCR_NMI_MASK (0x4U)
AnnaBridge 143:86740a56073b 7252 #define MCM_ISCR_NMI_SHIFT (2U)
AnnaBridge 143:86740a56073b 7253 #define MCM_ISCR_NMI(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_NMI_SHIFT)) & MCM_ISCR_NMI_MASK)
AnnaBridge 143:86740a56073b 7254 #define MCM_ISCR_DHREQ_MASK (0x8U)
AnnaBridge 143:86740a56073b 7255 #define MCM_ISCR_DHREQ_SHIFT (3U)
AnnaBridge 143:86740a56073b 7256 #define MCM_ISCR_DHREQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_DHREQ_SHIFT)) & MCM_ISCR_DHREQ_MASK)
AnnaBridge 143:86740a56073b 7257 #define MCM_ISCR_FIOC_MASK (0x100U)
AnnaBridge 143:86740a56073b 7258 #define MCM_ISCR_FIOC_SHIFT (8U)
AnnaBridge 143:86740a56073b 7259 #define MCM_ISCR_FIOC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOC_SHIFT)) & MCM_ISCR_FIOC_MASK)
AnnaBridge 143:86740a56073b 7260 #define MCM_ISCR_FDZC_MASK (0x200U)
AnnaBridge 143:86740a56073b 7261 #define MCM_ISCR_FDZC_SHIFT (9U)
AnnaBridge 143:86740a56073b 7262 #define MCM_ISCR_FDZC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZC_SHIFT)) & MCM_ISCR_FDZC_MASK)
AnnaBridge 143:86740a56073b 7263 #define MCM_ISCR_FOFC_MASK (0x400U)
AnnaBridge 143:86740a56073b 7264 #define MCM_ISCR_FOFC_SHIFT (10U)
AnnaBridge 143:86740a56073b 7265 #define MCM_ISCR_FOFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFC_SHIFT)) & MCM_ISCR_FOFC_MASK)
AnnaBridge 143:86740a56073b 7266 #define MCM_ISCR_FUFC_MASK (0x800U)
AnnaBridge 143:86740a56073b 7267 #define MCM_ISCR_FUFC_SHIFT (11U)
AnnaBridge 143:86740a56073b 7268 #define MCM_ISCR_FUFC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFC_SHIFT)) & MCM_ISCR_FUFC_MASK)
AnnaBridge 143:86740a56073b 7269 #define MCM_ISCR_FIXC_MASK (0x1000U)
AnnaBridge 143:86740a56073b 7270 #define MCM_ISCR_FIXC_SHIFT (12U)
AnnaBridge 143:86740a56073b 7271 #define MCM_ISCR_FIXC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXC_SHIFT)) & MCM_ISCR_FIXC_MASK)
AnnaBridge 143:86740a56073b 7272 #define MCM_ISCR_FIDC_MASK (0x8000U)
AnnaBridge 143:86740a56073b 7273 #define MCM_ISCR_FIDC_SHIFT (15U)
AnnaBridge 143:86740a56073b 7274 #define MCM_ISCR_FIDC(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDC_SHIFT)) & MCM_ISCR_FIDC_MASK)
AnnaBridge 143:86740a56073b 7275 #define MCM_ISCR_FIOCE_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 7276 #define MCM_ISCR_FIOCE_SHIFT (24U)
AnnaBridge 143:86740a56073b 7277 #define MCM_ISCR_FIOCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIOCE_SHIFT)) & MCM_ISCR_FIOCE_MASK)
AnnaBridge 143:86740a56073b 7278 #define MCM_ISCR_FDZCE_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 7279 #define MCM_ISCR_FDZCE_SHIFT (25U)
AnnaBridge 143:86740a56073b 7280 #define MCM_ISCR_FDZCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FDZCE_SHIFT)) & MCM_ISCR_FDZCE_MASK)
AnnaBridge 143:86740a56073b 7281 #define MCM_ISCR_FOFCE_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 7282 #define MCM_ISCR_FOFCE_SHIFT (26U)
AnnaBridge 143:86740a56073b 7283 #define MCM_ISCR_FOFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FOFCE_SHIFT)) & MCM_ISCR_FOFCE_MASK)
AnnaBridge 143:86740a56073b 7284 #define MCM_ISCR_FUFCE_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 7285 #define MCM_ISCR_FUFCE_SHIFT (27U)
AnnaBridge 143:86740a56073b 7286 #define MCM_ISCR_FUFCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FUFCE_SHIFT)) & MCM_ISCR_FUFCE_MASK)
AnnaBridge 143:86740a56073b 7287 #define MCM_ISCR_FIXCE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 7288 #define MCM_ISCR_FIXCE_SHIFT (28U)
AnnaBridge 143:86740a56073b 7289 #define MCM_ISCR_FIXCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIXCE_SHIFT)) & MCM_ISCR_FIXCE_MASK)
AnnaBridge 143:86740a56073b 7290 #define MCM_ISCR_FIDCE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 7291 #define MCM_ISCR_FIDCE_SHIFT (31U)
AnnaBridge 143:86740a56073b 7292 #define MCM_ISCR_FIDCE(x) (((uint32_t)(((uint32_t)(x)) << MCM_ISCR_FIDCE_SHIFT)) & MCM_ISCR_FIDCE_MASK)
AnnaBridge 143:86740a56073b 7293
AnnaBridge 143:86740a56073b 7294 /*! @name ETBCC - ETB Counter Control register */
AnnaBridge 143:86740a56073b 7295 #define MCM_ETBCC_CNTEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 7296 #define MCM_ETBCC_CNTEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 7297 #define MCM_ETBCC_CNTEN(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_CNTEN_SHIFT)) & MCM_ETBCC_CNTEN_MASK)
AnnaBridge 143:86740a56073b 7298 #define MCM_ETBCC_RSPT_MASK (0x6U)
AnnaBridge 143:86740a56073b 7299 #define MCM_ETBCC_RSPT_SHIFT (1U)
AnnaBridge 143:86740a56073b 7300 #define MCM_ETBCC_RSPT(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RSPT_SHIFT)) & MCM_ETBCC_RSPT_MASK)
AnnaBridge 143:86740a56073b 7301 #define MCM_ETBCC_RLRQ_MASK (0x8U)
AnnaBridge 143:86740a56073b 7302 #define MCM_ETBCC_RLRQ_SHIFT (3U)
AnnaBridge 143:86740a56073b 7303 #define MCM_ETBCC_RLRQ(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_RLRQ_SHIFT)) & MCM_ETBCC_RLRQ_MASK)
AnnaBridge 143:86740a56073b 7304 #define MCM_ETBCC_ETDIS_MASK (0x10U)
AnnaBridge 143:86740a56073b 7305 #define MCM_ETBCC_ETDIS_SHIFT (4U)
AnnaBridge 143:86740a56073b 7306 #define MCM_ETBCC_ETDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ETDIS_SHIFT)) & MCM_ETBCC_ETDIS_MASK)
AnnaBridge 143:86740a56073b 7307 #define MCM_ETBCC_ITDIS_MASK (0x20U)
AnnaBridge 143:86740a56073b 7308 #define MCM_ETBCC_ITDIS_SHIFT (5U)
AnnaBridge 143:86740a56073b 7309 #define MCM_ETBCC_ITDIS(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCC_ITDIS_SHIFT)) & MCM_ETBCC_ITDIS_MASK)
AnnaBridge 143:86740a56073b 7310
AnnaBridge 143:86740a56073b 7311 /*! @name ETBRL - ETB Reload register */
AnnaBridge 143:86740a56073b 7312 #define MCM_ETBRL_RELOAD_MASK (0x7FFU)
AnnaBridge 143:86740a56073b 7313 #define MCM_ETBRL_RELOAD_SHIFT (0U)
AnnaBridge 143:86740a56073b 7314 #define MCM_ETBRL_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBRL_RELOAD_SHIFT)) & MCM_ETBRL_RELOAD_MASK)
AnnaBridge 143:86740a56073b 7315
AnnaBridge 143:86740a56073b 7316 /*! @name ETBCNT - ETB Counter Value register */
AnnaBridge 143:86740a56073b 7317 #define MCM_ETBCNT_COUNTER_MASK (0x7FFU)
AnnaBridge 143:86740a56073b 7318 #define MCM_ETBCNT_COUNTER_SHIFT (0U)
AnnaBridge 143:86740a56073b 7319 #define MCM_ETBCNT_COUNTER(x) (((uint32_t)(((uint32_t)(x)) << MCM_ETBCNT_COUNTER_SHIFT)) & MCM_ETBCNT_COUNTER_MASK)
AnnaBridge 143:86740a56073b 7320
AnnaBridge 143:86740a56073b 7321 /*! @name PID - Process ID register */
AnnaBridge 143:86740a56073b 7322 #define MCM_PID_PID_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7323 #define MCM_PID_PID_SHIFT (0U)
AnnaBridge 143:86740a56073b 7324 #define MCM_PID_PID(x) (((uint32_t)(((uint32_t)(x)) << MCM_PID_PID_SHIFT)) & MCM_PID_PID_MASK)
AnnaBridge 143:86740a56073b 7325
AnnaBridge 143:86740a56073b 7326
AnnaBridge 143:86740a56073b 7327 /*!
AnnaBridge 143:86740a56073b 7328 * @}
AnnaBridge 143:86740a56073b 7329 */ /* end of group MCM_Register_Masks */
AnnaBridge 143:86740a56073b 7330
AnnaBridge 143:86740a56073b 7331
AnnaBridge 143:86740a56073b 7332 /* MCM - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 7333 /** Peripheral MCM base address */
AnnaBridge 143:86740a56073b 7334 #define MCM_BASE (0xE0080000u)
AnnaBridge 143:86740a56073b 7335 /** Peripheral MCM base pointer */
AnnaBridge 143:86740a56073b 7336 #define MCM ((MCM_Type *)MCM_BASE)
AnnaBridge 143:86740a56073b 7337 /** Array initializer of MCM peripheral base addresses */
AnnaBridge 143:86740a56073b 7338 #define MCM_BASE_ADDRS { MCM_BASE }
AnnaBridge 143:86740a56073b 7339 /** Array initializer of MCM peripheral base pointers */
AnnaBridge 143:86740a56073b 7340 #define MCM_BASE_PTRS { MCM }
AnnaBridge 143:86740a56073b 7341 /** Interrupt vectors for the MCM peripheral type */
AnnaBridge 143:86740a56073b 7342 #define MCM_IRQS { MCM_IRQn }
AnnaBridge 143:86740a56073b 7343
AnnaBridge 143:86740a56073b 7344 /*!
AnnaBridge 143:86740a56073b 7345 * @}
AnnaBridge 143:86740a56073b 7346 */ /* end of group MCM_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 7347
AnnaBridge 143:86740a56073b 7348
AnnaBridge 143:86740a56073b 7349 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7350 -- NV Peripheral Access Layer
AnnaBridge 143:86740a56073b 7351 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7352
AnnaBridge 143:86740a56073b 7353 /*!
AnnaBridge 143:86740a56073b 7354 * @addtogroup NV_Peripheral_Access_Layer NV Peripheral Access Layer
AnnaBridge 143:86740a56073b 7355 * @{
AnnaBridge 143:86740a56073b 7356 */
AnnaBridge 143:86740a56073b 7357
AnnaBridge 143:86740a56073b 7358 /** NV - Register Layout Typedef */
AnnaBridge 143:86740a56073b 7359 typedef struct {
AnnaBridge 143:86740a56073b 7360 __I uint8_t BACKKEY3; /**< Backdoor Comparison Key 3., offset: 0x0 */
AnnaBridge 143:86740a56073b 7361 __I uint8_t BACKKEY2; /**< Backdoor Comparison Key 2., offset: 0x1 */
AnnaBridge 143:86740a56073b 7362 __I uint8_t BACKKEY1; /**< Backdoor Comparison Key 1., offset: 0x2 */
AnnaBridge 143:86740a56073b 7363 __I uint8_t BACKKEY0; /**< Backdoor Comparison Key 0., offset: 0x3 */
AnnaBridge 143:86740a56073b 7364 __I uint8_t BACKKEY7; /**< Backdoor Comparison Key 7., offset: 0x4 */
AnnaBridge 143:86740a56073b 7365 __I uint8_t BACKKEY6; /**< Backdoor Comparison Key 6., offset: 0x5 */
AnnaBridge 143:86740a56073b 7366 __I uint8_t BACKKEY5; /**< Backdoor Comparison Key 5., offset: 0x6 */
AnnaBridge 143:86740a56073b 7367 __I uint8_t BACKKEY4; /**< Backdoor Comparison Key 4., offset: 0x7 */
AnnaBridge 143:86740a56073b 7368 __I uint8_t FPROT3; /**< Non-volatile P-Flash Protection 1 - Low Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 7369 __I uint8_t FPROT2; /**< Non-volatile P-Flash Protection 1 - High Register, offset: 0x9 */
AnnaBridge 143:86740a56073b 7370 __I uint8_t FPROT1; /**< Non-volatile P-Flash Protection 0 - Low Register, offset: 0xA */
AnnaBridge 143:86740a56073b 7371 __I uint8_t FPROT0; /**< Non-volatile P-Flash Protection 0 - High Register, offset: 0xB */
AnnaBridge 143:86740a56073b 7372 __I uint8_t FSEC; /**< Non-volatile Flash Security Register, offset: 0xC */
AnnaBridge 143:86740a56073b 7373 __I uint8_t FOPT; /**< Non-volatile Flash Option Register, offset: 0xD */
AnnaBridge 143:86740a56073b 7374 __I uint8_t FEPROT; /**< Non-volatile EERAM Protection Register, offset: 0xE */
AnnaBridge 143:86740a56073b 7375 __I uint8_t FDPROT; /**< Non-volatile D-Flash Protection Register, offset: 0xF */
AnnaBridge 143:86740a56073b 7376 } NV_Type;
AnnaBridge 143:86740a56073b 7377
AnnaBridge 143:86740a56073b 7378 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7379 -- NV Register Masks
AnnaBridge 143:86740a56073b 7380 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7381
AnnaBridge 143:86740a56073b 7382 /*!
AnnaBridge 143:86740a56073b 7383 * @addtogroup NV_Register_Masks NV Register Masks
AnnaBridge 143:86740a56073b 7384 * @{
AnnaBridge 143:86740a56073b 7385 */
AnnaBridge 143:86740a56073b 7386
AnnaBridge 143:86740a56073b 7387 /*! @name BACKKEY3 - Backdoor Comparison Key 3. */
AnnaBridge 143:86740a56073b 7388 #define NV_BACKKEY3_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7389 #define NV_BACKKEY3_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7390 #define NV_BACKKEY3_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY3_KEY_SHIFT)) & NV_BACKKEY3_KEY_MASK)
AnnaBridge 143:86740a56073b 7391
AnnaBridge 143:86740a56073b 7392 /*! @name BACKKEY2 - Backdoor Comparison Key 2. */
AnnaBridge 143:86740a56073b 7393 #define NV_BACKKEY2_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7394 #define NV_BACKKEY2_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7395 #define NV_BACKKEY2_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY2_KEY_SHIFT)) & NV_BACKKEY2_KEY_MASK)
AnnaBridge 143:86740a56073b 7396
AnnaBridge 143:86740a56073b 7397 /*! @name BACKKEY1 - Backdoor Comparison Key 1. */
AnnaBridge 143:86740a56073b 7398 #define NV_BACKKEY1_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7399 #define NV_BACKKEY1_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7400 #define NV_BACKKEY1_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY1_KEY_SHIFT)) & NV_BACKKEY1_KEY_MASK)
AnnaBridge 143:86740a56073b 7401
AnnaBridge 143:86740a56073b 7402 /*! @name BACKKEY0 - Backdoor Comparison Key 0. */
AnnaBridge 143:86740a56073b 7403 #define NV_BACKKEY0_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7404 #define NV_BACKKEY0_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7405 #define NV_BACKKEY0_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY0_KEY_SHIFT)) & NV_BACKKEY0_KEY_MASK)
AnnaBridge 143:86740a56073b 7406
AnnaBridge 143:86740a56073b 7407 /*! @name BACKKEY7 - Backdoor Comparison Key 7. */
AnnaBridge 143:86740a56073b 7408 #define NV_BACKKEY7_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7409 #define NV_BACKKEY7_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7410 #define NV_BACKKEY7_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY7_KEY_SHIFT)) & NV_BACKKEY7_KEY_MASK)
AnnaBridge 143:86740a56073b 7411
AnnaBridge 143:86740a56073b 7412 /*! @name BACKKEY6 - Backdoor Comparison Key 6. */
AnnaBridge 143:86740a56073b 7413 #define NV_BACKKEY6_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7414 #define NV_BACKKEY6_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7415 #define NV_BACKKEY6_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY6_KEY_SHIFT)) & NV_BACKKEY6_KEY_MASK)
AnnaBridge 143:86740a56073b 7416
AnnaBridge 143:86740a56073b 7417 /*! @name BACKKEY5 - Backdoor Comparison Key 5. */
AnnaBridge 143:86740a56073b 7418 #define NV_BACKKEY5_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7419 #define NV_BACKKEY5_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7420 #define NV_BACKKEY5_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY5_KEY_SHIFT)) & NV_BACKKEY5_KEY_MASK)
AnnaBridge 143:86740a56073b 7421
AnnaBridge 143:86740a56073b 7422 /*! @name BACKKEY4 - Backdoor Comparison Key 4. */
AnnaBridge 143:86740a56073b 7423 #define NV_BACKKEY4_KEY_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7424 #define NV_BACKKEY4_KEY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7425 #define NV_BACKKEY4_KEY(x) (((uint8_t)(((uint8_t)(x)) << NV_BACKKEY4_KEY_SHIFT)) & NV_BACKKEY4_KEY_MASK)
AnnaBridge 143:86740a56073b 7426
AnnaBridge 143:86740a56073b 7427 /*! @name FPROT3 - Non-volatile P-Flash Protection 1 - Low Register */
AnnaBridge 143:86740a56073b 7428 #define NV_FPROT3_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7429 #define NV_FPROT3_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7430 #define NV_FPROT3_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT3_PROT_SHIFT)) & NV_FPROT3_PROT_MASK)
AnnaBridge 143:86740a56073b 7431
AnnaBridge 143:86740a56073b 7432 /*! @name FPROT2 - Non-volatile P-Flash Protection 1 - High Register */
AnnaBridge 143:86740a56073b 7433 #define NV_FPROT2_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7434 #define NV_FPROT2_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7435 #define NV_FPROT2_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT2_PROT_SHIFT)) & NV_FPROT2_PROT_MASK)
AnnaBridge 143:86740a56073b 7436
AnnaBridge 143:86740a56073b 7437 /*! @name FPROT1 - Non-volatile P-Flash Protection 0 - Low Register */
AnnaBridge 143:86740a56073b 7438 #define NV_FPROT1_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7439 #define NV_FPROT1_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7440 #define NV_FPROT1_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT1_PROT_SHIFT)) & NV_FPROT1_PROT_MASK)
AnnaBridge 143:86740a56073b 7441
AnnaBridge 143:86740a56073b 7442 /*! @name FPROT0 - Non-volatile P-Flash Protection 0 - High Register */
AnnaBridge 143:86740a56073b 7443 #define NV_FPROT0_PROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7444 #define NV_FPROT0_PROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7445 #define NV_FPROT0_PROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FPROT0_PROT_SHIFT)) & NV_FPROT0_PROT_MASK)
AnnaBridge 143:86740a56073b 7446
AnnaBridge 143:86740a56073b 7447 /*! @name FSEC - Non-volatile Flash Security Register */
AnnaBridge 143:86740a56073b 7448 #define NV_FSEC_SEC_MASK (0x3U)
AnnaBridge 143:86740a56073b 7449 #define NV_FSEC_SEC_SHIFT (0U)
AnnaBridge 143:86740a56073b 7450 #define NV_FSEC_SEC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_SEC_SHIFT)) & NV_FSEC_SEC_MASK)
AnnaBridge 143:86740a56073b 7451 #define NV_FSEC_FSLACC_MASK (0xCU)
AnnaBridge 143:86740a56073b 7452 #define NV_FSEC_FSLACC_SHIFT (2U)
AnnaBridge 143:86740a56073b 7453 #define NV_FSEC_FSLACC(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_FSLACC_SHIFT)) & NV_FSEC_FSLACC_MASK)
AnnaBridge 143:86740a56073b 7454 #define NV_FSEC_MEEN_MASK (0x30U)
AnnaBridge 143:86740a56073b 7455 #define NV_FSEC_MEEN_SHIFT (4U)
AnnaBridge 143:86740a56073b 7456 #define NV_FSEC_MEEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_MEEN_SHIFT)) & NV_FSEC_MEEN_MASK)
AnnaBridge 143:86740a56073b 7457 #define NV_FSEC_KEYEN_MASK (0xC0U)
AnnaBridge 143:86740a56073b 7458 #define NV_FSEC_KEYEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 7459 #define NV_FSEC_KEYEN(x) (((uint8_t)(((uint8_t)(x)) << NV_FSEC_KEYEN_SHIFT)) & NV_FSEC_KEYEN_MASK)
AnnaBridge 143:86740a56073b 7460
AnnaBridge 143:86740a56073b 7461 /*! @name FOPT - Non-volatile Flash Option Register */
AnnaBridge 143:86740a56073b 7462 #define NV_FOPT_LPBOOT_MASK (0x1U)
AnnaBridge 143:86740a56073b 7463 #define NV_FOPT_LPBOOT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7464 #define NV_FOPT_LPBOOT(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_LPBOOT_SHIFT)) & NV_FOPT_LPBOOT_MASK)
AnnaBridge 143:86740a56073b 7465 #define NV_FOPT_EZPORT_DIS_MASK (0x2U)
AnnaBridge 143:86740a56073b 7466 #define NV_FOPT_EZPORT_DIS_SHIFT (1U)
AnnaBridge 143:86740a56073b 7467 #define NV_FOPT_EZPORT_DIS(x) (((uint8_t)(((uint8_t)(x)) << NV_FOPT_EZPORT_DIS_SHIFT)) & NV_FOPT_EZPORT_DIS_MASK)
AnnaBridge 143:86740a56073b 7468
AnnaBridge 143:86740a56073b 7469 /*! @name FEPROT - Non-volatile EERAM Protection Register */
AnnaBridge 143:86740a56073b 7470 #define NV_FEPROT_EPROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7471 #define NV_FEPROT_EPROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7472 #define NV_FEPROT_EPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FEPROT_EPROT_SHIFT)) & NV_FEPROT_EPROT_MASK)
AnnaBridge 143:86740a56073b 7473
AnnaBridge 143:86740a56073b 7474 /*! @name FDPROT - Non-volatile D-Flash Protection Register */
AnnaBridge 143:86740a56073b 7475 #define NV_FDPROT_DPROT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7476 #define NV_FDPROT_DPROT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7477 #define NV_FDPROT_DPROT(x) (((uint8_t)(((uint8_t)(x)) << NV_FDPROT_DPROT_SHIFT)) & NV_FDPROT_DPROT_MASK)
AnnaBridge 143:86740a56073b 7478
AnnaBridge 143:86740a56073b 7479
AnnaBridge 143:86740a56073b 7480 /*!
AnnaBridge 143:86740a56073b 7481 * @}
AnnaBridge 143:86740a56073b 7482 */ /* end of group NV_Register_Masks */
AnnaBridge 143:86740a56073b 7483
AnnaBridge 143:86740a56073b 7484
AnnaBridge 143:86740a56073b 7485 /* NV - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 7486 /** Peripheral FTFE_FlashConfig base address */
AnnaBridge 143:86740a56073b 7487 #define FTFE_FlashConfig_BASE (0x400u)
AnnaBridge 143:86740a56073b 7488 /** Peripheral FTFE_FlashConfig base pointer */
AnnaBridge 143:86740a56073b 7489 #define FTFE_FlashConfig ((NV_Type *)FTFE_FlashConfig_BASE)
AnnaBridge 143:86740a56073b 7490 /** Array initializer of NV peripheral base addresses */
AnnaBridge 143:86740a56073b 7491 #define NV_BASE_ADDRS { FTFE_FlashConfig_BASE }
AnnaBridge 143:86740a56073b 7492 /** Array initializer of NV peripheral base pointers */
AnnaBridge 143:86740a56073b 7493 #define NV_BASE_PTRS { FTFE_FlashConfig }
AnnaBridge 143:86740a56073b 7494
AnnaBridge 143:86740a56073b 7495 /*!
AnnaBridge 143:86740a56073b 7496 * @}
AnnaBridge 143:86740a56073b 7497 */ /* end of group NV_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 7498
AnnaBridge 143:86740a56073b 7499
AnnaBridge 143:86740a56073b 7500 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7501 -- OSC Peripheral Access Layer
AnnaBridge 143:86740a56073b 7502 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7503
AnnaBridge 143:86740a56073b 7504 /*!
AnnaBridge 143:86740a56073b 7505 * @addtogroup OSC_Peripheral_Access_Layer OSC Peripheral Access Layer
AnnaBridge 143:86740a56073b 7506 * @{
AnnaBridge 143:86740a56073b 7507 */
AnnaBridge 143:86740a56073b 7508
AnnaBridge 143:86740a56073b 7509 /** OSC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 7510 typedef struct {
AnnaBridge 143:86740a56073b 7511 __IO uint8_t CR; /**< OSC Control Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 7512 } OSC_Type;
AnnaBridge 143:86740a56073b 7513
AnnaBridge 143:86740a56073b 7514 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7515 -- OSC Register Masks
AnnaBridge 143:86740a56073b 7516 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7517
AnnaBridge 143:86740a56073b 7518 /*!
AnnaBridge 143:86740a56073b 7519 * @addtogroup OSC_Register_Masks OSC Register Masks
AnnaBridge 143:86740a56073b 7520 * @{
AnnaBridge 143:86740a56073b 7521 */
AnnaBridge 143:86740a56073b 7522
AnnaBridge 143:86740a56073b 7523 /*! @name CR - OSC Control Register */
AnnaBridge 143:86740a56073b 7524 #define OSC_CR_SC16P_MASK (0x1U)
AnnaBridge 143:86740a56073b 7525 #define OSC_CR_SC16P_SHIFT (0U)
AnnaBridge 143:86740a56073b 7526 #define OSC_CR_SC16P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC16P_SHIFT)) & OSC_CR_SC16P_MASK)
AnnaBridge 143:86740a56073b 7527 #define OSC_CR_SC8P_MASK (0x2U)
AnnaBridge 143:86740a56073b 7528 #define OSC_CR_SC8P_SHIFT (1U)
AnnaBridge 143:86740a56073b 7529 #define OSC_CR_SC8P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC8P_SHIFT)) & OSC_CR_SC8P_MASK)
AnnaBridge 143:86740a56073b 7530 #define OSC_CR_SC4P_MASK (0x4U)
AnnaBridge 143:86740a56073b 7531 #define OSC_CR_SC4P_SHIFT (2U)
AnnaBridge 143:86740a56073b 7532 #define OSC_CR_SC4P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC4P_SHIFT)) & OSC_CR_SC4P_MASK)
AnnaBridge 143:86740a56073b 7533 #define OSC_CR_SC2P_MASK (0x8U)
AnnaBridge 143:86740a56073b 7534 #define OSC_CR_SC2P_SHIFT (3U)
AnnaBridge 143:86740a56073b 7535 #define OSC_CR_SC2P(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_SC2P_SHIFT)) & OSC_CR_SC2P_MASK)
AnnaBridge 143:86740a56073b 7536 #define OSC_CR_EREFSTEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 7537 #define OSC_CR_EREFSTEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 7538 #define OSC_CR_EREFSTEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_EREFSTEN_SHIFT)) & OSC_CR_EREFSTEN_MASK)
AnnaBridge 143:86740a56073b 7539 #define OSC_CR_ERCLKEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 7540 #define OSC_CR_ERCLKEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 7541 #define OSC_CR_ERCLKEN(x) (((uint8_t)(((uint8_t)(x)) << OSC_CR_ERCLKEN_SHIFT)) & OSC_CR_ERCLKEN_MASK)
AnnaBridge 143:86740a56073b 7542
AnnaBridge 143:86740a56073b 7543
AnnaBridge 143:86740a56073b 7544 /*!
AnnaBridge 143:86740a56073b 7545 * @}
AnnaBridge 143:86740a56073b 7546 */ /* end of group OSC_Register_Masks */
AnnaBridge 143:86740a56073b 7547
AnnaBridge 143:86740a56073b 7548
AnnaBridge 143:86740a56073b 7549 /* OSC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 7550 /** Peripheral OSC base address */
AnnaBridge 143:86740a56073b 7551 #define OSC_BASE (0x40065000u)
AnnaBridge 143:86740a56073b 7552 /** Peripheral OSC base pointer */
AnnaBridge 143:86740a56073b 7553 #define OSC ((OSC_Type *)OSC_BASE)
AnnaBridge 143:86740a56073b 7554 /** Array initializer of OSC peripheral base addresses */
AnnaBridge 143:86740a56073b 7555 #define OSC_BASE_ADDRS { OSC_BASE }
AnnaBridge 143:86740a56073b 7556 /** Array initializer of OSC peripheral base pointers */
AnnaBridge 143:86740a56073b 7557 #define OSC_BASE_PTRS { OSC }
AnnaBridge 143:86740a56073b 7558
AnnaBridge 143:86740a56073b 7559 /*!
AnnaBridge 143:86740a56073b 7560 * @}
AnnaBridge 143:86740a56073b 7561 */ /* end of group OSC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 7562
AnnaBridge 143:86740a56073b 7563
AnnaBridge 143:86740a56073b 7564 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7565 -- PDB Peripheral Access Layer
AnnaBridge 143:86740a56073b 7566 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7567
AnnaBridge 143:86740a56073b 7568 /*!
AnnaBridge 143:86740a56073b 7569 * @addtogroup PDB_Peripheral_Access_Layer PDB Peripheral Access Layer
AnnaBridge 143:86740a56073b 7570 * @{
AnnaBridge 143:86740a56073b 7571 */
AnnaBridge 143:86740a56073b 7572
AnnaBridge 143:86740a56073b 7573 /** PDB - Register Layout Typedef */
AnnaBridge 143:86740a56073b 7574 typedef struct {
AnnaBridge 143:86740a56073b 7575 __IO uint32_t SC; /**< Status and Control register, offset: 0x0 */
AnnaBridge 143:86740a56073b 7576 __IO uint32_t MOD; /**< Modulus register, offset: 0x4 */
AnnaBridge 143:86740a56073b 7577 __I uint32_t CNT; /**< Counter register, offset: 0x8 */
AnnaBridge 143:86740a56073b 7578 __IO uint32_t IDLY; /**< Interrupt Delay register, offset: 0xC */
AnnaBridge 143:86740a56073b 7579 struct { /* offset: 0x10, array step: 0x28 */
AnnaBridge 143:86740a56073b 7580 __IO uint32_t C1; /**< Channel n Control register 1, array offset: 0x10, array step: 0x28 */
AnnaBridge 143:86740a56073b 7581 __IO uint32_t S; /**< Channel n Status register, array offset: 0x14, array step: 0x28 */
AnnaBridge 143:86740a56073b 7582 __IO uint32_t DLY[2]; /**< Channel n Delay 0 register..Channel n Delay 1 register, array offset: 0x18, array step: index*0x28, index2*0x4 */
AnnaBridge 143:86740a56073b 7583 uint8_t RESERVED_0[24];
AnnaBridge 143:86740a56073b 7584 } CH[2];
AnnaBridge 143:86740a56073b 7585 uint8_t RESERVED_0[240];
AnnaBridge 143:86740a56073b 7586 struct { /* offset: 0x150, array step: 0x8 */
AnnaBridge 143:86740a56073b 7587 __IO uint32_t INTC; /**< DAC Interval Trigger n Control register, array offset: 0x150, array step: 0x8 */
AnnaBridge 143:86740a56073b 7588 __IO uint32_t INT; /**< DAC Interval n register, array offset: 0x154, array step: 0x8 */
AnnaBridge 143:86740a56073b 7589 } DAC[2];
AnnaBridge 143:86740a56073b 7590 uint8_t RESERVED_1[48];
AnnaBridge 143:86740a56073b 7591 __IO uint32_t POEN; /**< Pulse-Out n Enable register, offset: 0x190 */
AnnaBridge 143:86740a56073b 7592 __IO uint32_t PODLY[3]; /**< Pulse-Out n Delay register, array offset: 0x194, array step: 0x4 */
AnnaBridge 143:86740a56073b 7593 } PDB_Type;
AnnaBridge 143:86740a56073b 7594
AnnaBridge 143:86740a56073b 7595 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7596 -- PDB Register Masks
AnnaBridge 143:86740a56073b 7597 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7598
AnnaBridge 143:86740a56073b 7599 /*!
AnnaBridge 143:86740a56073b 7600 * @addtogroup PDB_Register_Masks PDB Register Masks
AnnaBridge 143:86740a56073b 7601 * @{
AnnaBridge 143:86740a56073b 7602 */
AnnaBridge 143:86740a56073b 7603
AnnaBridge 143:86740a56073b 7604 /*! @name SC - Status and Control register */
AnnaBridge 143:86740a56073b 7605 #define PDB_SC_LDOK_MASK (0x1U)
AnnaBridge 143:86740a56073b 7606 #define PDB_SC_LDOK_SHIFT (0U)
AnnaBridge 143:86740a56073b 7607 #define PDB_SC_LDOK(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDOK_SHIFT)) & PDB_SC_LDOK_MASK)
AnnaBridge 143:86740a56073b 7608 #define PDB_SC_CONT_MASK (0x2U)
AnnaBridge 143:86740a56073b 7609 #define PDB_SC_CONT_SHIFT (1U)
AnnaBridge 143:86740a56073b 7610 #define PDB_SC_CONT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_CONT_SHIFT)) & PDB_SC_CONT_MASK)
AnnaBridge 143:86740a56073b 7611 #define PDB_SC_MULT_MASK (0xCU)
AnnaBridge 143:86740a56073b 7612 #define PDB_SC_MULT_SHIFT (2U)
AnnaBridge 143:86740a56073b 7613 #define PDB_SC_MULT(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_MULT_SHIFT)) & PDB_SC_MULT_MASK)
AnnaBridge 143:86740a56073b 7614 #define PDB_SC_PDBIE_MASK (0x20U)
AnnaBridge 143:86740a56073b 7615 #define PDB_SC_PDBIE_SHIFT (5U)
AnnaBridge 143:86740a56073b 7616 #define PDB_SC_PDBIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIE_SHIFT)) & PDB_SC_PDBIE_MASK)
AnnaBridge 143:86740a56073b 7617 #define PDB_SC_PDBIF_MASK (0x40U)
AnnaBridge 143:86740a56073b 7618 #define PDB_SC_PDBIF_SHIFT (6U)
AnnaBridge 143:86740a56073b 7619 #define PDB_SC_PDBIF(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBIF_SHIFT)) & PDB_SC_PDBIF_MASK)
AnnaBridge 143:86740a56073b 7620 #define PDB_SC_PDBEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 7621 #define PDB_SC_PDBEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 7622 #define PDB_SC_PDBEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEN_SHIFT)) & PDB_SC_PDBEN_MASK)
AnnaBridge 143:86740a56073b 7623 #define PDB_SC_TRGSEL_MASK (0xF00U)
AnnaBridge 143:86740a56073b 7624 #define PDB_SC_TRGSEL_SHIFT (8U)
AnnaBridge 143:86740a56073b 7625 #define PDB_SC_TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_TRGSEL_SHIFT)) & PDB_SC_TRGSEL_MASK)
AnnaBridge 143:86740a56073b 7626 #define PDB_SC_PRESCALER_MASK (0x7000U)
AnnaBridge 143:86740a56073b 7627 #define PDB_SC_PRESCALER_SHIFT (12U)
AnnaBridge 143:86740a56073b 7628 #define PDB_SC_PRESCALER(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PRESCALER_SHIFT)) & PDB_SC_PRESCALER_MASK)
AnnaBridge 143:86740a56073b 7629 #define PDB_SC_DMAEN_MASK (0x8000U)
AnnaBridge 143:86740a56073b 7630 #define PDB_SC_DMAEN_SHIFT (15U)
AnnaBridge 143:86740a56073b 7631 #define PDB_SC_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_DMAEN_SHIFT)) & PDB_SC_DMAEN_MASK)
AnnaBridge 143:86740a56073b 7632 #define PDB_SC_SWTRIG_MASK (0x10000U)
AnnaBridge 143:86740a56073b 7633 #define PDB_SC_SWTRIG_SHIFT (16U)
AnnaBridge 143:86740a56073b 7634 #define PDB_SC_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_SWTRIG_SHIFT)) & PDB_SC_SWTRIG_MASK)
AnnaBridge 143:86740a56073b 7635 #define PDB_SC_PDBEIE_MASK (0x20000U)
AnnaBridge 143:86740a56073b 7636 #define PDB_SC_PDBEIE_SHIFT (17U)
AnnaBridge 143:86740a56073b 7637 #define PDB_SC_PDBEIE(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_PDBEIE_SHIFT)) & PDB_SC_PDBEIE_MASK)
AnnaBridge 143:86740a56073b 7638 #define PDB_SC_LDMOD_MASK (0xC0000U)
AnnaBridge 143:86740a56073b 7639 #define PDB_SC_LDMOD_SHIFT (18U)
AnnaBridge 143:86740a56073b 7640 #define PDB_SC_LDMOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_SC_LDMOD_SHIFT)) & PDB_SC_LDMOD_MASK)
AnnaBridge 143:86740a56073b 7641
AnnaBridge 143:86740a56073b 7642 /*! @name MOD - Modulus register */
AnnaBridge 143:86740a56073b 7643 #define PDB_MOD_MOD_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 7644 #define PDB_MOD_MOD_SHIFT (0U)
AnnaBridge 143:86740a56073b 7645 #define PDB_MOD_MOD(x) (((uint32_t)(((uint32_t)(x)) << PDB_MOD_MOD_SHIFT)) & PDB_MOD_MOD_MASK)
AnnaBridge 143:86740a56073b 7646
AnnaBridge 143:86740a56073b 7647 /*! @name CNT - Counter register */
AnnaBridge 143:86740a56073b 7648 #define PDB_CNT_CNT_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 7649 #define PDB_CNT_CNT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7650 #define PDB_CNT_CNT(x) (((uint32_t)(((uint32_t)(x)) << PDB_CNT_CNT_SHIFT)) & PDB_CNT_CNT_MASK)
AnnaBridge 143:86740a56073b 7651
AnnaBridge 143:86740a56073b 7652 /*! @name IDLY - Interrupt Delay register */
AnnaBridge 143:86740a56073b 7653 #define PDB_IDLY_IDLY_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 7654 #define PDB_IDLY_IDLY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7655 #define PDB_IDLY_IDLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_IDLY_IDLY_SHIFT)) & PDB_IDLY_IDLY_MASK)
AnnaBridge 143:86740a56073b 7656
AnnaBridge 143:86740a56073b 7657 /*! @name C1 - Channel n Control register 1 */
AnnaBridge 143:86740a56073b 7658 #define PDB_C1_EN_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7659 #define PDB_C1_EN_SHIFT (0U)
AnnaBridge 143:86740a56073b 7660 #define PDB_C1_EN(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_EN_SHIFT)) & PDB_C1_EN_MASK)
AnnaBridge 143:86740a56073b 7661 #define PDB_C1_TOS_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 7662 #define PDB_C1_TOS_SHIFT (8U)
AnnaBridge 143:86740a56073b 7663 #define PDB_C1_TOS(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_TOS_SHIFT)) & PDB_C1_TOS_MASK)
AnnaBridge 143:86740a56073b 7664 #define PDB_C1_BB_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 7665 #define PDB_C1_BB_SHIFT (16U)
AnnaBridge 143:86740a56073b 7666 #define PDB_C1_BB(x) (((uint32_t)(((uint32_t)(x)) << PDB_C1_BB_SHIFT)) & PDB_C1_BB_MASK)
AnnaBridge 143:86740a56073b 7667
AnnaBridge 143:86740a56073b 7668 /* The count of PDB_C1 */
AnnaBridge 143:86740a56073b 7669 #define PDB_C1_COUNT (2U)
AnnaBridge 143:86740a56073b 7670
AnnaBridge 143:86740a56073b 7671 /*! @name S - Channel n Status register */
AnnaBridge 143:86740a56073b 7672 #define PDB_S_ERR_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7673 #define PDB_S_ERR_SHIFT (0U)
AnnaBridge 143:86740a56073b 7674 #define PDB_S_ERR(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_ERR_SHIFT)) & PDB_S_ERR_MASK)
AnnaBridge 143:86740a56073b 7675 #define PDB_S_CF_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 7676 #define PDB_S_CF_SHIFT (16U)
AnnaBridge 143:86740a56073b 7677 #define PDB_S_CF(x) (((uint32_t)(((uint32_t)(x)) << PDB_S_CF_SHIFT)) & PDB_S_CF_MASK)
AnnaBridge 143:86740a56073b 7678
AnnaBridge 143:86740a56073b 7679 /* The count of PDB_S */
AnnaBridge 143:86740a56073b 7680 #define PDB_S_COUNT (2U)
AnnaBridge 143:86740a56073b 7681
AnnaBridge 143:86740a56073b 7682 /*! @name DLY - Channel n Delay 0 register..Channel n Delay 1 register */
AnnaBridge 143:86740a56073b 7683 #define PDB_DLY_DLY_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 7684 #define PDB_DLY_DLY_SHIFT (0U)
AnnaBridge 143:86740a56073b 7685 #define PDB_DLY_DLY(x) (((uint32_t)(((uint32_t)(x)) << PDB_DLY_DLY_SHIFT)) & PDB_DLY_DLY_MASK)
AnnaBridge 143:86740a56073b 7686
AnnaBridge 143:86740a56073b 7687 /* The count of PDB_DLY */
AnnaBridge 143:86740a56073b 7688 #define PDB_DLY_COUNT (2U)
AnnaBridge 143:86740a56073b 7689
AnnaBridge 143:86740a56073b 7690 /* The count of PDB_DLY */
AnnaBridge 143:86740a56073b 7691 #define PDB_DLY_COUNT2 (2U)
AnnaBridge 143:86740a56073b 7692
AnnaBridge 143:86740a56073b 7693 /*! @name INTC - DAC Interval Trigger n Control register */
AnnaBridge 143:86740a56073b 7694 #define PDB_INTC_TOE_MASK (0x1U)
AnnaBridge 143:86740a56073b 7695 #define PDB_INTC_TOE_SHIFT (0U)
AnnaBridge 143:86740a56073b 7696 #define PDB_INTC_TOE(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_TOE_SHIFT)) & PDB_INTC_TOE_MASK)
AnnaBridge 143:86740a56073b 7697 #define PDB_INTC_EXT_MASK (0x2U)
AnnaBridge 143:86740a56073b 7698 #define PDB_INTC_EXT_SHIFT (1U)
AnnaBridge 143:86740a56073b 7699 #define PDB_INTC_EXT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INTC_EXT_SHIFT)) & PDB_INTC_EXT_MASK)
AnnaBridge 143:86740a56073b 7700
AnnaBridge 143:86740a56073b 7701 /* The count of PDB_INTC */
AnnaBridge 143:86740a56073b 7702 #define PDB_INTC_COUNT (2U)
AnnaBridge 143:86740a56073b 7703
AnnaBridge 143:86740a56073b 7704 /*! @name INT - DAC Interval n register */
AnnaBridge 143:86740a56073b 7705 #define PDB_INT_INT_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 7706 #define PDB_INT_INT_SHIFT (0U)
AnnaBridge 143:86740a56073b 7707 #define PDB_INT_INT(x) (((uint32_t)(((uint32_t)(x)) << PDB_INT_INT_SHIFT)) & PDB_INT_INT_MASK)
AnnaBridge 143:86740a56073b 7708
AnnaBridge 143:86740a56073b 7709 /* The count of PDB_INT */
AnnaBridge 143:86740a56073b 7710 #define PDB_INT_COUNT (2U)
AnnaBridge 143:86740a56073b 7711
AnnaBridge 143:86740a56073b 7712 /*! @name POEN - Pulse-Out n Enable register */
AnnaBridge 143:86740a56073b 7713 #define PDB_POEN_POEN_MASK (0xFFU)
AnnaBridge 143:86740a56073b 7714 #define PDB_POEN_POEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 7715 #define PDB_POEN_POEN(x) (((uint32_t)(((uint32_t)(x)) << PDB_POEN_POEN_SHIFT)) & PDB_POEN_POEN_MASK)
AnnaBridge 143:86740a56073b 7716
AnnaBridge 143:86740a56073b 7717 /*! @name PODLY - Pulse-Out n Delay register */
AnnaBridge 143:86740a56073b 7718 #define PDB_PODLY_DLY2_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 7719 #define PDB_PODLY_DLY2_SHIFT (0U)
AnnaBridge 143:86740a56073b 7720 #define PDB_PODLY_DLY2(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY2_SHIFT)) & PDB_PODLY_DLY2_MASK)
AnnaBridge 143:86740a56073b 7721 #define PDB_PODLY_DLY1_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 7722 #define PDB_PODLY_DLY1_SHIFT (16U)
AnnaBridge 143:86740a56073b 7723 #define PDB_PODLY_DLY1(x) (((uint32_t)(((uint32_t)(x)) << PDB_PODLY_DLY1_SHIFT)) & PDB_PODLY_DLY1_MASK)
AnnaBridge 143:86740a56073b 7724
AnnaBridge 143:86740a56073b 7725 /* The count of PDB_PODLY */
AnnaBridge 143:86740a56073b 7726 #define PDB_PODLY_COUNT (3U)
AnnaBridge 143:86740a56073b 7727
AnnaBridge 143:86740a56073b 7728
AnnaBridge 143:86740a56073b 7729 /*!
AnnaBridge 143:86740a56073b 7730 * @}
AnnaBridge 143:86740a56073b 7731 */ /* end of group PDB_Register_Masks */
AnnaBridge 143:86740a56073b 7732
AnnaBridge 143:86740a56073b 7733
AnnaBridge 143:86740a56073b 7734 /* PDB - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 7735 /** Peripheral PDB0 base address */
AnnaBridge 143:86740a56073b 7736 #define PDB0_BASE (0x40036000u)
AnnaBridge 143:86740a56073b 7737 /** Peripheral PDB0 base pointer */
AnnaBridge 143:86740a56073b 7738 #define PDB0 ((PDB_Type *)PDB0_BASE)
AnnaBridge 143:86740a56073b 7739 /** Array initializer of PDB peripheral base addresses */
AnnaBridge 143:86740a56073b 7740 #define PDB_BASE_ADDRS { PDB0_BASE }
AnnaBridge 143:86740a56073b 7741 /** Array initializer of PDB peripheral base pointers */
AnnaBridge 143:86740a56073b 7742 #define PDB_BASE_PTRS { PDB0 }
AnnaBridge 143:86740a56073b 7743 /** Interrupt vectors for the PDB peripheral type */
AnnaBridge 143:86740a56073b 7744 #define PDB_IRQS { PDB0_IRQn }
AnnaBridge 143:86740a56073b 7745
AnnaBridge 143:86740a56073b 7746 /*!
AnnaBridge 143:86740a56073b 7747 * @}
AnnaBridge 143:86740a56073b 7748 */ /* end of group PDB_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 7749
AnnaBridge 143:86740a56073b 7750
AnnaBridge 143:86740a56073b 7751 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7752 -- PIT Peripheral Access Layer
AnnaBridge 143:86740a56073b 7753 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7754
AnnaBridge 143:86740a56073b 7755 /*!
AnnaBridge 143:86740a56073b 7756 * @addtogroup PIT_Peripheral_Access_Layer PIT Peripheral Access Layer
AnnaBridge 143:86740a56073b 7757 * @{
AnnaBridge 143:86740a56073b 7758 */
AnnaBridge 143:86740a56073b 7759
AnnaBridge 143:86740a56073b 7760 /** PIT - Register Layout Typedef */
AnnaBridge 143:86740a56073b 7761 typedef struct {
AnnaBridge 143:86740a56073b 7762 __IO uint32_t MCR; /**< PIT Module Control Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 7763 uint8_t RESERVED_0[252];
AnnaBridge 143:86740a56073b 7764 struct { /* offset: 0x100, array step: 0x10 */
AnnaBridge 143:86740a56073b 7765 __IO uint32_t LDVAL; /**< Timer Load Value Register, array offset: 0x100, array step: 0x10 */
AnnaBridge 143:86740a56073b 7766 __I uint32_t CVAL; /**< Current Timer Value Register, array offset: 0x104, array step: 0x10 */
AnnaBridge 143:86740a56073b 7767 __IO uint32_t TCTRL; /**< Timer Control Register, array offset: 0x108, array step: 0x10 */
AnnaBridge 143:86740a56073b 7768 __IO uint32_t TFLG; /**< Timer Flag Register, array offset: 0x10C, array step: 0x10 */
AnnaBridge 143:86740a56073b 7769 } CHANNEL[4];
AnnaBridge 143:86740a56073b 7770 } PIT_Type;
AnnaBridge 143:86740a56073b 7771
AnnaBridge 143:86740a56073b 7772 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7773 -- PIT Register Masks
AnnaBridge 143:86740a56073b 7774 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7775
AnnaBridge 143:86740a56073b 7776 /*!
AnnaBridge 143:86740a56073b 7777 * @addtogroup PIT_Register_Masks PIT Register Masks
AnnaBridge 143:86740a56073b 7778 * @{
AnnaBridge 143:86740a56073b 7779 */
AnnaBridge 143:86740a56073b 7780
AnnaBridge 143:86740a56073b 7781 /*! @name MCR - PIT Module Control Register */
AnnaBridge 143:86740a56073b 7782 #define PIT_MCR_FRZ_MASK (0x1U)
AnnaBridge 143:86740a56073b 7783 #define PIT_MCR_FRZ_SHIFT (0U)
AnnaBridge 143:86740a56073b 7784 #define PIT_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_FRZ_SHIFT)) & PIT_MCR_FRZ_MASK)
AnnaBridge 143:86740a56073b 7785 #define PIT_MCR_MDIS_MASK (0x2U)
AnnaBridge 143:86740a56073b 7786 #define PIT_MCR_MDIS_SHIFT (1U)
AnnaBridge 143:86740a56073b 7787 #define PIT_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << PIT_MCR_MDIS_SHIFT)) & PIT_MCR_MDIS_MASK)
AnnaBridge 143:86740a56073b 7788
AnnaBridge 143:86740a56073b 7789 /*! @name LDVAL - Timer Load Value Register */
AnnaBridge 143:86740a56073b 7790 #define PIT_LDVAL_TSV_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 7791 #define PIT_LDVAL_TSV_SHIFT (0U)
AnnaBridge 143:86740a56073b 7792 #define PIT_LDVAL_TSV(x) (((uint32_t)(((uint32_t)(x)) << PIT_LDVAL_TSV_SHIFT)) & PIT_LDVAL_TSV_MASK)
AnnaBridge 143:86740a56073b 7793
AnnaBridge 143:86740a56073b 7794 /* The count of PIT_LDVAL */
AnnaBridge 143:86740a56073b 7795 #define PIT_LDVAL_COUNT (4U)
AnnaBridge 143:86740a56073b 7796
AnnaBridge 143:86740a56073b 7797 /*! @name CVAL - Current Timer Value Register */
AnnaBridge 143:86740a56073b 7798 #define PIT_CVAL_TVL_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 7799 #define PIT_CVAL_TVL_SHIFT (0U)
AnnaBridge 143:86740a56073b 7800 #define PIT_CVAL_TVL(x) (((uint32_t)(((uint32_t)(x)) << PIT_CVAL_TVL_SHIFT)) & PIT_CVAL_TVL_MASK)
AnnaBridge 143:86740a56073b 7801
AnnaBridge 143:86740a56073b 7802 /* The count of PIT_CVAL */
AnnaBridge 143:86740a56073b 7803 #define PIT_CVAL_COUNT (4U)
AnnaBridge 143:86740a56073b 7804
AnnaBridge 143:86740a56073b 7805 /*! @name TCTRL - Timer Control Register */
AnnaBridge 143:86740a56073b 7806 #define PIT_TCTRL_TEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 7807 #define PIT_TCTRL_TEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 7808 #define PIT_TCTRL_TEN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TEN_SHIFT)) & PIT_TCTRL_TEN_MASK)
AnnaBridge 143:86740a56073b 7809 #define PIT_TCTRL_TIE_MASK (0x2U)
AnnaBridge 143:86740a56073b 7810 #define PIT_TCTRL_TIE_SHIFT (1U)
AnnaBridge 143:86740a56073b 7811 #define PIT_TCTRL_TIE(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_TIE_SHIFT)) & PIT_TCTRL_TIE_MASK)
AnnaBridge 143:86740a56073b 7812 #define PIT_TCTRL_CHN_MASK (0x4U)
AnnaBridge 143:86740a56073b 7813 #define PIT_TCTRL_CHN_SHIFT (2U)
AnnaBridge 143:86740a56073b 7814 #define PIT_TCTRL_CHN(x) (((uint32_t)(((uint32_t)(x)) << PIT_TCTRL_CHN_SHIFT)) & PIT_TCTRL_CHN_MASK)
AnnaBridge 143:86740a56073b 7815
AnnaBridge 143:86740a56073b 7816 /* The count of PIT_TCTRL */
AnnaBridge 143:86740a56073b 7817 #define PIT_TCTRL_COUNT (4U)
AnnaBridge 143:86740a56073b 7818
AnnaBridge 143:86740a56073b 7819 /*! @name TFLG - Timer Flag Register */
AnnaBridge 143:86740a56073b 7820 #define PIT_TFLG_TIF_MASK (0x1U)
AnnaBridge 143:86740a56073b 7821 #define PIT_TFLG_TIF_SHIFT (0U)
AnnaBridge 143:86740a56073b 7822 #define PIT_TFLG_TIF(x) (((uint32_t)(((uint32_t)(x)) << PIT_TFLG_TIF_SHIFT)) & PIT_TFLG_TIF_MASK)
AnnaBridge 143:86740a56073b 7823
AnnaBridge 143:86740a56073b 7824 /* The count of PIT_TFLG */
AnnaBridge 143:86740a56073b 7825 #define PIT_TFLG_COUNT (4U)
AnnaBridge 143:86740a56073b 7826
AnnaBridge 143:86740a56073b 7827
AnnaBridge 143:86740a56073b 7828 /*!
AnnaBridge 143:86740a56073b 7829 * @}
AnnaBridge 143:86740a56073b 7830 */ /* end of group PIT_Register_Masks */
AnnaBridge 143:86740a56073b 7831
AnnaBridge 143:86740a56073b 7832
AnnaBridge 143:86740a56073b 7833 /* PIT - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 7834 /** Peripheral PIT base address */
AnnaBridge 143:86740a56073b 7835 #define PIT_BASE (0x40037000u)
AnnaBridge 143:86740a56073b 7836 /** Peripheral PIT base pointer */
AnnaBridge 143:86740a56073b 7837 #define PIT ((PIT_Type *)PIT_BASE)
AnnaBridge 143:86740a56073b 7838 /** Array initializer of PIT peripheral base addresses */
AnnaBridge 143:86740a56073b 7839 #define PIT_BASE_ADDRS { PIT_BASE }
AnnaBridge 143:86740a56073b 7840 /** Array initializer of PIT peripheral base pointers */
AnnaBridge 143:86740a56073b 7841 #define PIT_BASE_PTRS { PIT }
AnnaBridge 143:86740a56073b 7842 /** Interrupt vectors for the PIT peripheral type */
AnnaBridge 143:86740a56073b 7843 #define PIT_IRQS { { PIT0_IRQn, PIT1_IRQn, PIT2_IRQn, PIT3_IRQn } }
AnnaBridge 143:86740a56073b 7844
AnnaBridge 143:86740a56073b 7845 /*!
AnnaBridge 143:86740a56073b 7846 * @}
AnnaBridge 143:86740a56073b 7847 */ /* end of group PIT_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 7848
AnnaBridge 143:86740a56073b 7849
AnnaBridge 143:86740a56073b 7850 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7851 -- PMC Peripheral Access Layer
AnnaBridge 143:86740a56073b 7852 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7853
AnnaBridge 143:86740a56073b 7854 /*!
AnnaBridge 143:86740a56073b 7855 * @addtogroup PMC_Peripheral_Access_Layer PMC Peripheral Access Layer
AnnaBridge 143:86740a56073b 7856 * @{
AnnaBridge 143:86740a56073b 7857 */
AnnaBridge 143:86740a56073b 7858
AnnaBridge 143:86740a56073b 7859 /** PMC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 7860 typedef struct {
AnnaBridge 143:86740a56073b 7861 __IO uint8_t LVDSC1; /**< Low Voltage Detect Status And Control 1 register, offset: 0x0 */
AnnaBridge 143:86740a56073b 7862 __IO uint8_t LVDSC2; /**< Low Voltage Detect Status And Control 2 register, offset: 0x1 */
AnnaBridge 143:86740a56073b 7863 __IO uint8_t REGSC; /**< Regulator Status And Control register, offset: 0x2 */
AnnaBridge 143:86740a56073b 7864 } PMC_Type;
AnnaBridge 143:86740a56073b 7865
AnnaBridge 143:86740a56073b 7866 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7867 -- PMC Register Masks
AnnaBridge 143:86740a56073b 7868 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7869
AnnaBridge 143:86740a56073b 7870 /*!
AnnaBridge 143:86740a56073b 7871 * @addtogroup PMC_Register_Masks PMC Register Masks
AnnaBridge 143:86740a56073b 7872 * @{
AnnaBridge 143:86740a56073b 7873 */
AnnaBridge 143:86740a56073b 7874
AnnaBridge 143:86740a56073b 7875 /*! @name LVDSC1 - Low Voltage Detect Status And Control 1 register */
AnnaBridge 143:86740a56073b 7876 #define PMC_LVDSC1_LVDV_MASK (0x3U)
AnnaBridge 143:86740a56073b 7877 #define PMC_LVDSC1_LVDV_SHIFT (0U)
AnnaBridge 143:86740a56073b 7878 #define PMC_LVDSC1_LVDV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDV_SHIFT)) & PMC_LVDSC1_LVDV_MASK)
AnnaBridge 143:86740a56073b 7879 #define PMC_LVDSC1_LVDRE_MASK (0x10U)
AnnaBridge 143:86740a56073b 7880 #define PMC_LVDSC1_LVDRE_SHIFT (4U)
AnnaBridge 143:86740a56073b 7881 #define PMC_LVDSC1_LVDRE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDRE_SHIFT)) & PMC_LVDSC1_LVDRE_MASK)
AnnaBridge 143:86740a56073b 7882 #define PMC_LVDSC1_LVDIE_MASK (0x20U)
AnnaBridge 143:86740a56073b 7883 #define PMC_LVDSC1_LVDIE_SHIFT (5U)
AnnaBridge 143:86740a56073b 7884 #define PMC_LVDSC1_LVDIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDIE_SHIFT)) & PMC_LVDSC1_LVDIE_MASK)
AnnaBridge 143:86740a56073b 7885 #define PMC_LVDSC1_LVDACK_MASK (0x40U)
AnnaBridge 143:86740a56073b 7886 #define PMC_LVDSC1_LVDACK_SHIFT (6U)
AnnaBridge 143:86740a56073b 7887 #define PMC_LVDSC1_LVDACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDACK_SHIFT)) & PMC_LVDSC1_LVDACK_MASK)
AnnaBridge 143:86740a56073b 7888 #define PMC_LVDSC1_LVDF_MASK (0x80U)
AnnaBridge 143:86740a56073b 7889 #define PMC_LVDSC1_LVDF_SHIFT (7U)
AnnaBridge 143:86740a56073b 7890 #define PMC_LVDSC1_LVDF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC1_LVDF_SHIFT)) & PMC_LVDSC1_LVDF_MASK)
AnnaBridge 143:86740a56073b 7891
AnnaBridge 143:86740a56073b 7892 /*! @name LVDSC2 - Low Voltage Detect Status And Control 2 register */
AnnaBridge 143:86740a56073b 7893 #define PMC_LVDSC2_LVWV_MASK (0x3U)
AnnaBridge 143:86740a56073b 7894 #define PMC_LVDSC2_LVWV_SHIFT (0U)
AnnaBridge 143:86740a56073b 7895 #define PMC_LVDSC2_LVWV(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWV_SHIFT)) & PMC_LVDSC2_LVWV_MASK)
AnnaBridge 143:86740a56073b 7896 #define PMC_LVDSC2_LVWIE_MASK (0x20U)
AnnaBridge 143:86740a56073b 7897 #define PMC_LVDSC2_LVWIE_SHIFT (5U)
AnnaBridge 143:86740a56073b 7898 #define PMC_LVDSC2_LVWIE(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWIE_SHIFT)) & PMC_LVDSC2_LVWIE_MASK)
AnnaBridge 143:86740a56073b 7899 #define PMC_LVDSC2_LVWACK_MASK (0x40U)
AnnaBridge 143:86740a56073b 7900 #define PMC_LVDSC2_LVWACK_SHIFT (6U)
AnnaBridge 143:86740a56073b 7901 #define PMC_LVDSC2_LVWACK(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWACK_SHIFT)) & PMC_LVDSC2_LVWACK_MASK)
AnnaBridge 143:86740a56073b 7902 #define PMC_LVDSC2_LVWF_MASK (0x80U)
AnnaBridge 143:86740a56073b 7903 #define PMC_LVDSC2_LVWF_SHIFT (7U)
AnnaBridge 143:86740a56073b 7904 #define PMC_LVDSC2_LVWF(x) (((uint8_t)(((uint8_t)(x)) << PMC_LVDSC2_LVWF_SHIFT)) & PMC_LVDSC2_LVWF_MASK)
AnnaBridge 143:86740a56073b 7905
AnnaBridge 143:86740a56073b 7906 /*! @name REGSC - Regulator Status And Control register */
AnnaBridge 143:86740a56073b 7907 #define PMC_REGSC_BGBE_MASK (0x1U)
AnnaBridge 143:86740a56073b 7908 #define PMC_REGSC_BGBE_SHIFT (0U)
AnnaBridge 143:86740a56073b 7909 #define PMC_REGSC_BGBE(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGBE_SHIFT)) & PMC_REGSC_BGBE_MASK)
AnnaBridge 143:86740a56073b 7910 #define PMC_REGSC_REGONS_MASK (0x4U)
AnnaBridge 143:86740a56073b 7911 #define PMC_REGSC_REGONS_SHIFT (2U)
AnnaBridge 143:86740a56073b 7912 #define PMC_REGSC_REGONS(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_REGONS_SHIFT)) & PMC_REGSC_REGONS_MASK)
AnnaBridge 143:86740a56073b 7913 #define PMC_REGSC_ACKISO_MASK (0x8U)
AnnaBridge 143:86740a56073b 7914 #define PMC_REGSC_ACKISO_SHIFT (3U)
AnnaBridge 143:86740a56073b 7915 #define PMC_REGSC_ACKISO(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_ACKISO_SHIFT)) & PMC_REGSC_ACKISO_MASK)
AnnaBridge 143:86740a56073b 7916 #define PMC_REGSC_BGEN_MASK (0x10U)
AnnaBridge 143:86740a56073b 7917 #define PMC_REGSC_BGEN_SHIFT (4U)
AnnaBridge 143:86740a56073b 7918 #define PMC_REGSC_BGEN(x) (((uint8_t)(((uint8_t)(x)) << PMC_REGSC_BGEN_SHIFT)) & PMC_REGSC_BGEN_MASK)
AnnaBridge 143:86740a56073b 7919
AnnaBridge 143:86740a56073b 7920
AnnaBridge 143:86740a56073b 7921 /*!
AnnaBridge 143:86740a56073b 7922 * @}
AnnaBridge 143:86740a56073b 7923 */ /* end of group PMC_Register_Masks */
AnnaBridge 143:86740a56073b 7924
AnnaBridge 143:86740a56073b 7925
AnnaBridge 143:86740a56073b 7926 /* PMC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 7927 /** Peripheral PMC base address */
AnnaBridge 143:86740a56073b 7928 #define PMC_BASE (0x4007D000u)
AnnaBridge 143:86740a56073b 7929 /** Peripheral PMC base pointer */
AnnaBridge 143:86740a56073b 7930 #define PMC ((PMC_Type *)PMC_BASE)
AnnaBridge 143:86740a56073b 7931 /** Array initializer of PMC peripheral base addresses */
AnnaBridge 143:86740a56073b 7932 #define PMC_BASE_ADDRS { PMC_BASE }
AnnaBridge 143:86740a56073b 7933 /** Array initializer of PMC peripheral base pointers */
AnnaBridge 143:86740a56073b 7934 #define PMC_BASE_PTRS { PMC }
AnnaBridge 143:86740a56073b 7935 /** Interrupt vectors for the PMC peripheral type */
AnnaBridge 143:86740a56073b 7936 #define PMC_IRQS { LVD_LVW_IRQn }
AnnaBridge 143:86740a56073b 7937
AnnaBridge 143:86740a56073b 7938 /*!
AnnaBridge 143:86740a56073b 7939 * @}
AnnaBridge 143:86740a56073b 7940 */ /* end of group PMC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 7941
AnnaBridge 143:86740a56073b 7942
AnnaBridge 143:86740a56073b 7943 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7944 -- PORT Peripheral Access Layer
AnnaBridge 143:86740a56073b 7945 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7946
AnnaBridge 143:86740a56073b 7947 /*!
AnnaBridge 143:86740a56073b 7948 * @addtogroup PORT_Peripheral_Access_Layer PORT Peripheral Access Layer
AnnaBridge 143:86740a56073b 7949 * @{
AnnaBridge 143:86740a56073b 7950 */
AnnaBridge 143:86740a56073b 7951
AnnaBridge 143:86740a56073b 7952 /** PORT - Register Layout Typedef */
AnnaBridge 143:86740a56073b 7953 typedef struct {
AnnaBridge 143:86740a56073b 7954 __IO uint32_t PCR[32]; /**< Pin Control Register n, array offset: 0x0, array step: 0x4 */
AnnaBridge 143:86740a56073b 7955 __O uint32_t GPCLR; /**< Global Pin Control Low Register, offset: 0x80 */
AnnaBridge 143:86740a56073b 7956 __O uint32_t GPCHR; /**< Global Pin Control High Register, offset: 0x84 */
AnnaBridge 143:86740a56073b 7957 uint8_t RESERVED_0[24];
AnnaBridge 143:86740a56073b 7958 __IO uint32_t ISFR; /**< Interrupt Status Flag Register, offset: 0xA0 */
AnnaBridge 143:86740a56073b 7959 uint8_t RESERVED_1[28];
AnnaBridge 143:86740a56073b 7960 __IO uint32_t DFER; /**< Digital Filter Enable Register, offset: 0xC0 */
AnnaBridge 143:86740a56073b 7961 __IO uint32_t DFCR; /**< Digital Filter Clock Register, offset: 0xC4 */
AnnaBridge 143:86740a56073b 7962 __IO uint32_t DFWR; /**< Digital Filter Width Register, offset: 0xC8 */
AnnaBridge 143:86740a56073b 7963 } PORT_Type;
AnnaBridge 143:86740a56073b 7964
AnnaBridge 143:86740a56073b 7965 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 7966 -- PORT Register Masks
AnnaBridge 143:86740a56073b 7967 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 7968
AnnaBridge 143:86740a56073b 7969 /*!
AnnaBridge 143:86740a56073b 7970 * @addtogroup PORT_Register_Masks PORT Register Masks
AnnaBridge 143:86740a56073b 7971 * @{
AnnaBridge 143:86740a56073b 7972 */
AnnaBridge 143:86740a56073b 7973
AnnaBridge 143:86740a56073b 7974 /*! @name PCR - Pin Control Register n */
AnnaBridge 143:86740a56073b 7975 #define PORT_PCR_PS_MASK (0x1U)
AnnaBridge 143:86740a56073b 7976 #define PORT_PCR_PS_SHIFT (0U)
AnnaBridge 143:86740a56073b 7977 #define PORT_PCR_PS(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PS_SHIFT)) & PORT_PCR_PS_MASK)
AnnaBridge 143:86740a56073b 7978 #define PORT_PCR_PE_MASK (0x2U)
AnnaBridge 143:86740a56073b 7979 #define PORT_PCR_PE_SHIFT (1U)
AnnaBridge 143:86740a56073b 7980 #define PORT_PCR_PE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PE_SHIFT)) & PORT_PCR_PE_MASK)
AnnaBridge 143:86740a56073b 7981 #define PORT_PCR_SRE_MASK (0x4U)
AnnaBridge 143:86740a56073b 7982 #define PORT_PCR_SRE_SHIFT (2U)
AnnaBridge 143:86740a56073b 7983 #define PORT_PCR_SRE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_SRE_SHIFT)) & PORT_PCR_SRE_MASK)
AnnaBridge 143:86740a56073b 7984 #define PORT_PCR_PFE_MASK (0x10U)
AnnaBridge 143:86740a56073b 7985 #define PORT_PCR_PFE_SHIFT (4U)
AnnaBridge 143:86740a56073b 7986 #define PORT_PCR_PFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_PFE_SHIFT)) & PORT_PCR_PFE_MASK)
AnnaBridge 143:86740a56073b 7987 #define PORT_PCR_ODE_MASK (0x20U)
AnnaBridge 143:86740a56073b 7988 #define PORT_PCR_ODE_SHIFT (5U)
AnnaBridge 143:86740a56073b 7989 #define PORT_PCR_ODE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ODE_SHIFT)) & PORT_PCR_ODE_MASK)
AnnaBridge 143:86740a56073b 7990 #define PORT_PCR_DSE_MASK (0x40U)
AnnaBridge 143:86740a56073b 7991 #define PORT_PCR_DSE_SHIFT (6U)
AnnaBridge 143:86740a56073b 7992 #define PORT_PCR_DSE(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_DSE_SHIFT)) & PORT_PCR_DSE_MASK)
AnnaBridge 143:86740a56073b 7993 #define PORT_PCR_MUX_MASK (0x700U)
AnnaBridge 143:86740a56073b 7994 #define PORT_PCR_MUX_SHIFT (8U)
AnnaBridge 143:86740a56073b 7995 #define PORT_PCR_MUX(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_MUX_SHIFT)) & PORT_PCR_MUX_MASK)
AnnaBridge 143:86740a56073b 7996 #define PORT_PCR_LK_MASK (0x8000U)
AnnaBridge 143:86740a56073b 7997 #define PORT_PCR_LK_SHIFT (15U)
AnnaBridge 143:86740a56073b 7998 #define PORT_PCR_LK(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_LK_SHIFT)) & PORT_PCR_LK_MASK)
AnnaBridge 143:86740a56073b 7999 #define PORT_PCR_IRQC_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 8000 #define PORT_PCR_IRQC_SHIFT (16U)
AnnaBridge 143:86740a56073b 8001 #define PORT_PCR_IRQC(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_IRQC_SHIFT)) & PORT_PCR_IRQC_MASK)
AnnaBridge 143:86740a56073b 8002 #define PORT_PCR_ISF_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 8003 #define PORT_PCR_ISF_SHIFT (24U)
AnnaBridge 143:86740a56073b 8004 #define PORT_PCR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_PCR_ISF_SHIFT)) & PORT_PCR_ISF_MASK)
AnnaBridge 143:86740a56073b 8005
AnnaBridge 143:86740a56073b 8006 /* The count of PORT_PCR */
AnnaBridge 143:86740a56073b 8007 #define PORT_PCR_COUNT (32U)
AnnaBridge 143:86740a56073b 8008
AnnaBridge 143:86740a56073b 8009 /*! @name GPCLR - Global Pin Control Low Register */
AnnaBridge 143:86740a56073b 8010 #define PORT_GPCLR_GPWD_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 8011 #define PORT_GPCLR_GPWD_SHIFT (0U)
AnnaBridge 143:86740a56073b 8012 #define PORT_GPCLR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWD_SHIFT)) & PORT_GPCLR_GPWD_MASK)
AnnaBridge 143:86740a56073b 8013 #define PORT_GPCLR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 8014 #define PORT_GPCLR_GPWE_SHIFT (16U)
AnnaBridge 143:86740a56073b 8015 #define PORT_GPCLR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCLR_GPWE_SHIFT)) & PORT_GPCLR_GPWE_MASK)
AnnaBridge 143:86740a56073b 8016
AnnaBridge 143:86740a56073b 8017 /*! @name GPCHR - Global Pin Control High Register */
AnnaBridge 143:86740a56073b 8018 #define PORT_GPCHR_GPWD_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 8019 #define PORT_GPCHR_GPWD_SHIFT (0U)
AnnaBridge 143:86740a56073b 8020 #define PORT_GPCHR_GPWD(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWD_SHIFT)) & PORT_GPCHR_GPWD_MASK)
AnnaBridge 143:86740a56073b 8021 #define PORT_GPCHR_GPWE_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 8022 #define PORT_GPCHR_GPWE_SHIFT (16U)
AnnaBridge 143:86740a56073b 8023 #define PORT_GPCHR_GPWE(x) (((uint32_t)(((uint32_t)(x)) << PORT_GPCHR_GPWE_SHIFT)) & PORT_GPCHR_GPWE_MASK)
AnnaBridge 143:86740a56073b 8024
AnnaBridge 143:86740a56073b 8025 /*! @name ISFR - Interrupt Status Flag Register */
AnnaBridge 143:86740a56073b 8026 #define PORT_ISFR_ISF_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8027 #define PORT_ISFR_ISF_SHIFT (0U)
AnnaBridge 143:86740a56073b 8028 #define PORT_ISFR_ISF(x) (((uint32_t)(((uint32_t)(x)) << PORT_ISFR_ISF_SHIFT)) & PORT_ISFR_ISF_MASK)
AnnaBridge 143:86740a56073b 8029
AnnaBridge 143:86740a56073b 8030 /*! @name DFER - Digital Filter Enable Register */
AnnaBridge 143:86740a56073b 8031 #define PORT_DFER_DFE_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8032 #define PORT_DFER_DFE_SHIFT (0U)
AnnaBridge 143:86740a56073b 8033 #define PORT_DFER_DFE(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFER_DFE_SHIFT)) & PORT_DFER_DFE_MASK)
AnnaBridge 143:86740a56073b 8034
AnnaBridge 143:86740a56073b 8035 /*! @name DFCR - Digital Filter Clock Register */
AnnaBridge 143:86740a56073b 8036 #define PORT_DFCR_CS_MASK (0x1U)
AnnaBridge 143:86740a56073b 8037 #define PORT_DFCR_CS_SHIFT (0U)
AnnaBridge 143:86740a56073b 8038 #define PORT_DFCR_CS(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFCR_CS_SHIFT)) & PORT_DFCR_CS_MASK)
AnnaBridge 143:86740a56073b 8039
AnnaBridge 143:86740a56073b 8040 /*! @name DFWR - Digital Filter Width Register */
AnnaBridge 143:86740a56073b 8041 #define PORT_DFWR_FILT_MASK (0x1FU)
AnnaBridge 143:86740a56073b 8042 #define PORT_DFWR_FILT_SHIFT (0U)
AnnaBridge 143:86740a56073b 8043 #define PORT_DFWR_FILT(x) (((uint32_t)(((uint32_t)(x)) << PORT_DFWR_FILT_SHIFT)) & PORT_DFWR_FILT_MASK)
AnnaBridge 143:86740a56073b 8044
AnnaBridge 143:86740a56073b 8045
AnnaBridge 143:86740a56073b 8046 /*!
AnnaBridge 143:86740a56073b 8047 * @}
AnnaBridge 143:86740a56073b 8048 */ /* end of group PORT_Register_Masks */
AnnaBridge 143:86740a56073b 8049
AnnaBridge 143:86740a56073b 8050
AnnaBridge 143:86740a56073b 8051 /* PORT - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 8052 /** Peripheral PORTA base address */
AnnaBridge 143:86740a56073b 8053 #define PORTA_BASE (0x40049000u)
AnnaBridge 143:86740a56073b 8054 /** Peripheral PORTA base pointer */
AnnaBridge 143:86740a56073b 8055 #define PORTA ((PORT_Type *)PORTA_BASE)
AnnaBridge 143:86740a56073b 8056 /** Peripheral PORTB base address */
AnnaBridge 143:86740a56073b 8057 #define PORTB_BASE (0x4004A000u)
AnnaBridge 143:86740a56073b 8058 /** Peripheral PORTB base pointer */
AnnaBridge 143:86740a56073b 8059 #define PORTB ((PORT_Type *)PORTB_BASE)
AnnaBridge 143:86740a56073b 8060 /** Peripheral PORTC base address */
AnnaBridge 143:86740a56073b 8061 #define PORTC_BASE (0x4004B000u)
AnnaBridge 143:86740a56073b 8062 /** Peripheral PORTC base pointer */
AnnaBridge 143:86740a56073b 8063 #define PORTC ((PORT_Type *)PORTC_BASE)
AnnaBridge 143:86740a56073b 8064 /** Peripheral PORTD base address */
AnnaBridge 143:86740a56073b 8065 #define PORTD_BASE (0x4004C000u)
AnnaBridge 143:86740a56073b 8066 /** Peripheral PORTD base pointer */
AnnaBridge 143:86740a56073b 8067 #define PORTD ((PORT_Type *)PORTD_BASE)
AnnaBridge 143:86740a56073b 8068 /** Peripheral PORTE base address */
AnnaBridge 143:86740a56073b 8069 #define PORTE_BASE (0x4004D000u)
AnnaBridge 143:86740a56073b 8070 /** Peripheral PORTE base pointer */
AnnaBridge 143:86740a56073b 8071 #define PORTE ((PORT_Type *)PORTE_BASE)
AnnaBridge 143:86740a56073b 8072 /** Array initializer of PORT peripheral base addresses */
AnnaBridge 143:86740a56073b 8073 #define PORT_BASE_ADDRS { PORTA_BASE, PORTB_BASE, PORTC_BASE, PORTD_BASE, PORTE_BASE }
AnnaBridge 143:86740a56073b 8074 /** Array initializer of PORT peripheral base pointers */
AnnaBridge 143:86740a56073b 8075 #define PORT_BASE_PTRS { PORTA, PORTB, PORTC, PORTD, PORTE }
AnnaBridge 143:86740a56073b 8076 /** Interrupt vectors for the PORT peripheral type */
AnnaBridge 143:86740a56073b 8077 #define PORT_IRQS { PORTA_IRQn, PORTB_IRQn, PORTC_IRQn, PORTD_IRQn, PORTE_IRQn }
AnnaBridge 143:86740a56073b 8078
AnnaBridge 143:86740a56073b 8079 /*!
AnnaBridge 143:86740a56073b 8080 * @}
AnnaBridge 143:86740a56073b 8081 */ /* end of group PORT_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 8082
AnnaBridge 143:86740a56073b 8083
AnnaBridge 143:86740a56073b 8084 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8085 -- RCM Peripheral Access Layer
AnnaBridge 143:86740a56073b 8086 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8087
AnnaBridge 143:86740a56073b 8088 /*!
AnnaBridge 143:86740a56073b 8089 * @addtogroup RCM_Peripheral_Access_Layer RCM Peripheral Access Layer
AnnaBridge 143:86740a56073b 8090 * @{
AnnaBridge 143:86740a56073b 8091 */
AnnaBridge 143:86740a56073b 8092
AnnaBridge 143:86740a56073b 8093 /** RCM - Register Layout Typedef */
AnnaBridge 143:86740a56073b 8094 typedef struct {
AnnaBridge 143:86740a56073b 8095 __I uint8_t SRS0; /**< System Reset Status Register 0, offset: 0x0 */
AnnaBridge 143:86740a56073b 8096 __I uint8_t SRS1; /**< System Reset Status Register 1, offset: 0x1 */
AnnaBridge 143:86740a56073b 8097 uint8_t RESERVED_0[2];
AnnaBridge 143:86740a56073b 8098 __IO uint8_t RPFC; /**< Reset Pin Filter Control register, offset: 0x4 */
AnnaBridge 143:86740a56073b 8099 __IO uint8_t RPFW; /**< Reset Pin Filter Width register, offset: 0x5 */
AnnaBridge 143:86740a56073b 8100 uint8_t RESERVED_1[1];
AnnaBridge 143:86740a56073b 8101 __I uint8_t MR; /**< Mode Register, offset: 0x7 */
AnnaBridge 143:86740a56073b 8102 } RCM_Type;
AnnaBridge 143:86740a56073b 8103
AnnaBridge 143:86740a56073b 8104 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8105 -- RCM Register Masks
AnnaBridge 143:86740a56073b 8106 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8107
AnnaBridge 143:86740a56073b 8108 /*!
AnnaBridge 143:86740a56073b 8109 * @addtogroup RCM_Register_Masks RCM Register Masks
AnnaBridge 143:86740a56073b 8110 * @{
AnnaBridge 143:86740a56073b 8111 */
AnnaBridge 143:86740a56073b 8112
AnnaBridge 143:86740a56073b 8113 /*! @name SRS0 - System Reset Status Register 0 */
AnnaBridge 143:86740a56073b 8114 #define RCM_SRS0_WAKEUP_MASK (0x1U)
AnnaBridge 143:86740a56073b 8115 #define RCM_SRS0_WAKEUP_SHIFT (0U)
AnnaBridge 143:86740a56073b 8116 #define RCM_SRS0_WAKEUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WAKEUP_SHIFT)) & RCM_SRS0_WAKEUP_MASK)
AnnaBridge 143:86740a56073b 8117 #define RCM_SRS0_LVD_MASK (0x2U)
AnnaBridge 143:86740a56073b 8118 #define RCM_SRS0_LVD_SHIFT (1U)
AnnaBridge 143:86740a56073b 8119 #define RCM_SRS0_LVD(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LVD_SHIFT)) & RCM_SRS0_LVD_MASK)
AnnaBridge 143:86740a56073b 8120 #define RCM_SRS0_LOC_MASK (0x4U)
AnnaBridge 143:86740a56073b 8121 #define RCM_SRS0_LOC_SHIFT (2U)
AnnaBridge 143:86740a56073b 8122 #define RCM_SRS0_LOC(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOC_SHIFT)) & RCM_SRS0_LOC_MASK)
AnnaBridge 143:86740a56073b 8123 #define RCM_SRS0_LOL_MASK (0x8U)
AnnaBridge 143:86740a56073b 8124 #define RCM_SRS0_LOL_SHIFT (3U)
AnnaBridge 143:86740a56073b 8125 #define RCM_SRS0_LOL(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_LOL_SHIFT)) & RCM_SRS0_LOL_MASK)
AnnaBridge 143:86740a56073b 8126 #define RCM_SRS0_WDOG_MASK (0x20U)
AnnaBridge 143:86740a56073b 8127 #define RCM_SRS0_WDOG_SHIFT (5U)
AnnaBridge 143:86740a56073b 8128 #define RCM_SRS0_WDOG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_WDOG_SHIFT)) & RCM_SRS0_WDOG_MASK)
AnnaBridge 143:86740a56073b 8129 #define RCM_SRS0_PIN_MASK (0x40U)
AnnaBridge 143:86740a56073b 8130 #define RCM_SRS0_PIN_SHIFT (6U)
AnnaBridge 143:86740a56073b 8131 #define RCM_SRS0_PIN(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_PIN_SHIFT)) & RCM_SRS0_PIN_MASK)
AnnaBridge 143:86740a56073b 8132 #define RCM_SRS0_POR_MASK (0x80U)
AnnaBridge 143:86740a56073b 8133 #define RCM_SRS0_POR_SHIFT (7U)
AnnaBridge 143:86740a56073b 8134 #define RCM_SRS0_POR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS0_POR_SHIFT)) & RCM_SRS0_POR_MASK)
AnnaBridge 143:86740a56073b 8135
AnnaBridge 143:86740a56073b 8136 /*! @name SRS1 - System Reset Status Register 1 */
AnnaBridge 143:86740a56073b 8137 #define RCM_SRS1_JTAG_MASK (0x1U)
AnnaBridge 143:86740a56073b 8138 #define RCM_SRS1_JTAG_SHIFT (0U)
AnnaBridge 143:86740a56073b 8139 #define RCM_SRS1_JTAG(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_JTAG_SHIFT)) & RCM_SRS1_JTAG_MASK)
AnnaBridge 143:86740a56073b 8140 #define RCM_SRS1_LOCKUP_MASK (0x2U)
AnnaBridge 143:86740a56073b 8141 #define RCM_SRS1_LOCKUP_SHIFT (1U)
AnnaBridge 143:86740a56073b 8142 #define RCM_SRS1_LOCKUP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_LOCKUP_SHIFT)) & RCM_SRS1_LOCKUP_MASK)
AnnaBridge 143:86740a56073b 8143 #define RCM_SRS1_SW_MASK (0x4U)
AnnaBridge 143:86740a56073b 8144 #define RCM_SRS1_SW_SHIFT (2U)
AnnaBridge 143:86740a56073b 8145 #define RCM_SRS1_SW(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SW_SHIFT)) & RCM_SRS1_SW_MASK)
AnnaBridge 143:86740a56073b 8146 #define RCM_SRS1_MDM_AP_MASK (0x8U)
AnnaBridge 143:86740a56073b 8147 #define RCM_SRS1_MDM_AP_SHIFT (3U)
AnnaBridge 143:86740a56073b 8148 #define RCM_SRS1_MDM_AP(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_MDM_AP_SHIFT)) & RCM_SRS1_MDM_AP_MASK)
AnnaBridge 143:86740a56073b 8149 #define RCM_SRS1_EZPT_MASK (0x10U)
AnnaBridge 143:86740a56073b 8150 #define RCM_SRS1_EZPT_SHIFT (4U)
AnnaBridge 143:86740a56073b 8151 #define RCM_SRS1_EZPT(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_EZPT_SHIFT)) & RCM_SRS1_EZPT_MASK)
AnnaBridge 143:86740a56073b 8152 #define RCM_SRS1_SACKERR_MASK (0x20U)
AnnaBridge 143:86740a56073b 8153 #define RCM_SRS1_SACKERR_SHIFT (5U)
AnnaBridge 143:86740a56073b 8154 #define RCM_SRS1_SACKERR(x) (((uint8_t)(((uint8_t)(x)) << RCM_SRS1_SACKERR_SHIFT)) & RCM_SRS1_SACKERR_MASK)
AnnaBridge 143:86740a56073b 8155
AnnaBridge 143:86740a56073b 8156 /*! @name RPFC - Reset Pin Filter Control register */
AnnaBridge 143:86740a56073b 8157 #define RCM_RPFC_RSTFLTSRW_MASK (0x3U)
AnnaBridge 143:86740a56073b 8158 #define RCM_RPFC_RSTFLTSRW_SHIFT (0U)
AnnaBridge 143:86740a56073b 8159 #define RCM_RPFC_RSTFLTSRW(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSRW_SHIFT)) & RCM_RPFC_RSTFLTSRW_MASK)
AnnaBridge 143:86740a56073b 8160 #define RCM_RPFC_RSTFLTSS_MASK (0x4U)
AnnaBridge 143:86740a56073b 8161 #define RCM_RPFC_RSTFLTSS_SHIFT (2U)
AnnaBridge 143:86740a56073b 8162 #define RCM_RPFC_RSTFLTSS(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFC_RSTFLTSS_SHIFT)) & RCM_RPFC_RSTFLTSS_MASK)
AnnaBridge 143:86740a56073b 8163
AnnaBridge 143:86740a56073b 8164 /*! @name RPFW - Reset Pin Filter Width register */
AnnaBridge 143:86740a56073b 8165 #define RCM_RPFW_RSTFLTSEL_MASK (0x1FU)
AnnaBridge 143:86740a56073b 8166 #define RCM_RPFW_RSTFLTSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 8167 #define RCM_RPFW_RSTFLTSEL(x) (((uint8_t)(((uint8_t)(x)) << RCM_RPFW_RSTFLTSEL_SHIFT)) & RCM_RPFW_RSTFLTSEL_MASK)
AnnaBridge 143:86740a56073b 8168
AnnaBridge 143:86740a56073b 8169 /*! @name MR - Mode Register */
AnnaBridge 143:86740a56073b 8170 #define RCM_MR_EZP_MS_MASK (0x2U)
AnnaBridge 143:86740a56073b 8171 #define RCM_MR_EZP_MS_SHIFT (1U)
AnnaBridge 143:86740a56073b 8172 #define RCM_MR_EZP_MS(x) (((uint8_t)(((uint8_t)(x)) << RCM_MR_EZP_MS_SHIFT)) & RCM_MR_EZP_MS_MASK)
AnnaBridge 143:86740a56073b 8173
AnnaBridge 143:86740a56073b 8174
AnnaBridge 143:86740a56073b 8175 /*!
AnnaBridge 143:86740a56073b 8176 * @}
AnnaBridge 143:86740a56073b 8177 */ /* end of group RCM_Register_Masks */
AnnaBridge 143:86740a56073b 8178
AnnaBridge 143:86740a56073b 8179
AnnaBridge 143:86740a56073b 8180 /* RCM - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 8181 /** Peripheral RCM base address */
AnnaBridge 143:86740a56073b 8182 #define RCM_BASE (0x4007F000u)
AnnaBridge 143:86740a56073b 8183 /** Peripheral RCM base pointer */
AnnaBridge 143:86740a56073b 8184 #define RCM ((RCM_Type *)RCM_BASE)
AnnaBridge 143:86740a56073b 8185 /** Array initializer of RCM peripheral base addresses */
AnnaBridge 143:86740a56073b 8186 #define RCM_BASE_ADDRS { RCM_BASE }
AnnaBridge 143:86740a56073b 8187 /** Array initializer of RCM peripheral base pointers */
AnnaBridge 143:86740a56073b 8188 #define RCM_BASE_PTRS { RCM }
AnnaBridge 143:86740a56073b 8189
AnnaBridge 143:86740a56073b 8190 /*!
AnnaBridge 143:86740a56073b 8191 * @}
AnnaBridge 143:86740a56073b 8192 */ /* end of group RCM_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 8193
AnnaBridge 143:86740a56073b 8194
AnnaBridge 143:86740a56073b 8195 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8196 -- RFSYS Peripheral Access Layer
AnnaBridge 143:86740a56073b 8197 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8198
AnnaBridge 143:86740a56073b 8199 /*!
AnnaBridge 143:86740a56073b 8200 * @addtogroup RFSYS_Peripheral_Access_Layer RFSYS Peripheral Access Layer
AnnaBridge 143:86740a56073b 8201 * @{
AnnaBridge 143:86740a56073b 8202 */
AnnaBridge 143:86740a56073b 8203
AnnaBridge 143:86740a56073b 8204 /** RFSYS - Register Layout Typedef */
AnnaBridge 143:86740a56073b 8205 typedef struct {
AnnaBridge 143:86740a56073b 8206 __IO uint32_t REG[8]; /**< Register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 143:86740a56073b 8207 } RFSYS_Type;
AnnaBridge 143:86740a56073b 8208
AnnaBridge 143:86740a56073b 8209 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8210 -- RFSYS Register Masks
AnnaBridge 143:86740a56073b 8211 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8212
AnnaBridge 143:86740a56073b 8213 /*!
AnnaBridge 143:86740a56073b 8214 * @addtogroup RFSYS_Register_Masks RFSYS Register Masks
AnnaBridge 143:86740a56073b 8215 * @{
AnnaBridge 143:86740a56073b 8216 */
AnnaBridge 143:86740a56073b 8217
AnnaBridge 143:86740a56073b 8218 /*! @name REG - Register file register */
AnnaBridge 143:86740a56073b 8219 #define RFSYS_REG_LL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 8220 #define RFSYS_REG_LL_SHIFT (0U)
AnnaBridge 143:86740a56073b 8221 #define RFSYS_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LL_SHIFT)) & RFSYS_REG_LL_MASK)
AnnaBridge 143:86740a56073b 8222 #define RFSYS_REG_LH_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 8223 #define RFSYS_REG_LH_SHIFT (8U)
AnnaBridge 143:86740a56073b 8224 #define RFSYS_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_LH_SHIFT)) & RFSYS_REG_LH_MASK)
AnnaBridge 143:86740a56073b 8225 #define RFSYS_REG_HL_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 8226 #define RFSYS_REG_HL_SHIFT (16U)
AnnaBridge 143:86740a56073b 8227 #define RFSYS_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HL_SHIFT)) & RFSYS_REG_HL_MASK)
AnnaBridge 143:86740a56073b 8228 #define RFSYS_REG_HH_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 8229 #define RFSYS_REG_HH_SHIFT (24U)
AnnaBridge 143:86740a56073b 8230 #define RFSYS_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFSYS_REG_HH_SHIFT)) & RFSYS_REG_HH_MASK)
AnnaBridge 143:86740a56073b 8231
AnnaBridge 143:86740a56073b 8232 /* The count of RFSYS_REG */
AnnaBridge 143:86740a56073b 8233 #define RFSYS_REG_COUNT (8U)
AnnaBridge 143:86740a56073b 8234
AnnaBridge 143:86740a56073b 8235
AnnaBridge 143:86740a56073b 8236 /*!
AnnaBridge 143:86740a56073b 8237 * @}
AnnaBridge 143:86740a56073b 8238 */ /* end of group RFSYS_Register_Masks */
AnnaBridge 143:86740a56073b 8239
AnnaBridge 143:86740a56073b 8240
AnnaBridge 143:86740a56073b 8241 /* RFSYS - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 8242 /** Peripheral RFSYS base address */
AnnaBridge 143:86740a56073b 8243 #define RFSYS_BASE (0x40041000u)
AnnaBridge 143:86740a56073b 8244 /** Peripheral RFSYS base pointer */
AnnaBridge 143:86740a56073b 8245 #define RFSYS ((RFSYS_Type *)RFSYS_BASE)
AnnaBridge 143:86740a56073b 8246 /** Array initializer of RFSYS peripheral base addresses */
AnnaBridge 143:86740a56073b 8247 #define RFSYS_BASE_ADDRS { RFSYS_BASE }
AnnaBridge 143:86740a56073b 8248 /** Array initializer of RFSYS peripheral base pointers */
AnnaBridge 143:86740a56073b 8249 #define RFSYS_BASE_PTRS { RFSYS }
AnnaBridge 143:86740a56073b 8250
AnnaBridge 143:86740a56073b 8251 /*!
AnnaBridge 143:86740a56073b 8252 * @}
AnnaBridge 143:86740a56073b 8253 */ /* end of group RFSYS_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 8254
AnnaBridge 143:86740a56073b 8255
AnnaBridge 143:86740a56073b 8256 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8257 -- RFVBAT Peripheral Access Layer
AnnaBridge 143:86740a56073b 8258 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8259
AnnaBridge 143:86740a56073b 8260 /*!
AnnaBridge 143:86740a56073b 8261 * @addtogroup RFVBAT_Peripheral_Access_Layer RFVBAT Peripheral Access Layer
AnnaBridge 143:86740a56073b 8262 * @{
AnnaBridge 143:86740a56073b 8263 */
AnnaBridge 143:86740a56073b 8264
AnnaBridge 143:86740a56073b 8265 /** RFVBAT - Register Layout Typedef */
AnnaBridge 143:86740a56073b 8266 typedef struct {
AnnaBridge 143:86740a56073b 8267 __IO uint32_t REG[8]; /**< VBAT register file register, array offset: 0x0, array step: 0x4 */
AnnaBridge 143:86740a56073b 8268 } RFVBAT_Type;
AnnaBridge 143:86740a56073b 8269
AnnaBridge 143:86740a56073b 8270 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8271 -- RFVBAT Register Masks
AnnaBridge 143:86740a56073b 8272 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8273
AnnaBridge 143:86740a56073b 8274 /*!
AnnaBridge 143:86740a56073b 8275 * @addtogroup RFVBAT_Register_Masks RFVBAT Register Masks
AnnaBridge 143:86740a56073b 8276 * @{
AnnaBridge 143:86740a56073b 8277 */
AnnaBridge 143:86740a56073b 8278
AnnaBridge 143:86740a56073b 8279 /*! @name REG - VBAT register file register */
AnnaBridge 143:86740a56073b 8280 #define RFVBAT_REG_LL_MASK (0xFFU)
AnnaBridge 143:86740a56073b 8281 #define RFVBAT_REG_LL_SHIFT (0U)
AnnaBridge 143:86740a56073b 8282 #define RFVBAT_REG_LL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LL_SHIFT)) & RFVBAT_REG_LL_MASK)
AnnaBridge 143:86740a56073b 8283 #define RFVBAT_REG_LH_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 8284 #define RFVBAT_REG_LH_SHIFT (8U)
AnnaBridge 143:86740a56073b 8285 #define RFVBAT_REG_LH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_LH_SHIFT)) & RFVBAT_REG_LH_MASK)
AnnaBridge 143:86740a56073b 8286 #define RFVBAT_REG_HL_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 8287 #define RFVBAT_REG_HL_SHIFT (16U)
AnnaBridge 143:86740a56073b 8288 #define RFVBAT_REG_HL(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HL_SHIFT)) & RFVBAT_REG_HL_MASK)
AnnaBridge 143:86740a56073b 8289 #define RFVBAT_REG_HH_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 8290 #define RFVBAT_REG_HH_SHIFT (24U)
AnnaBridge 143:86740a56073b 8291 #define RFVBAT_REG_HH(x) (((uint32_t)(((uint32_t)(x)) << RFVBAT_REG_HH_SHIFT)) & RFVBAT_REG_HH_MASK)
AnnaBridge 143:86740a56073b 8292
AnnaBridge 143:86740a56073b 8293 /* The count of RFVBAT_REG */
AnnaBridge 143:86740a56073b 8294 #define RFVBAT_REG_COUNT (8U)
AnnaBridge 143:86740a56073b 8295
AnnaBridge 143:86740a56073b 8296
AnnaBridge 143:86740a56073b 8297 /*!
AnnaBridge 143:86740a56073b 8298 * @}
AnnaBridge 143:86740a56073b 8299 */ /* end of group RFVBAT_Register_Masks */
AnnaBridge 143:86740a56073b 8300
AnnaBridge 143:86740a56073b 8301
AnnaBridge 143:86740a56073b 8302 /* RFVBAT - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 8303 /** Peripheral RFVBAT base address */
AnnaBridge 143:86740a56073b 8304 #define RFVBAT_BASE (0x4003E000u)
AnnaBridge 143:86740a56073b 8305 /** Peripheral RFVBAT base pointer */
AnnaBridge 143:86740a56073b 8306 #define RFVBAT ((RFVBAT_Type *)RFVBAT_BASE)
AnnaBridge 143:86740a56073b 8307 /** Array initializer of RFVBAT peripheral base addresses */
AnnaBridge 143:86740a56073b 8308 #define RFVBAT_BASE_ADDRS { RFVBAT_BASE }
AnnaBridge 143:86740a56073b 8309 /** Array initializer of RFVBAT peripheral base pointers */
AnnaBridge 143:86740a56073b 8310 #define RFVBAT_BASE_PTRS { RFVBAT }
AnnaBridge 143:86740a56073b 8311
AnnaBridge 143:86740a56073b 8312 /*!
AnnaBridge 143:86740a56073b 8313 * @}
AnnaBridge 143:86740a56073b 8314 */ /* end of group RFVBAT_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 8315
AnnaBridge 143:86740a56073b 8316
AnnaBridge 143:86740a56073b 8317 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8318 -- RNG Peripheral Access Layer
AnnaBridge 143:86740a56073b 8319 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8320
AnnaBridge 143:86740a56073b 8321 /*!
AnnaBridge 143:86740a56073b 8322 * @addtogroup RNG_Peripheral_Access_Layer RNG Peripheral Access Layer
AnnaBridge 143:86740a56073b 8323 * @{
AnnaBridge 143:86740a56073b 8324 */
AnnaBridge 143:86740a56073b 8325
AnnaBridge 143:86740a56073b 8326 /** RNG - Register Layout Typedef */
AnnaBridge 143:86740a56073b 8327 typedef struct {
AnnaBridge 143:86740a56073b 8328 __IO uint32_t CR; /**< RNGA Control Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 8329 __I uint32_t SR; /**< RNGA Status Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 8330 __O uint32_t ER; /**< RNGA Entropy Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 8331 __I uint32_t OR; /**< RNGA Output Register, offset: 0xC */
AnnaBridge 143:86740a56073b 8332 } RNG_Type;
AnnaBridge 143:86740a56073b 8333
AnnaBridge 143:86740a56073b 8334 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8335 -- RNG Register Masks
AnnaBridge 143:86740a56073b 8336 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8337
AnnaBridge 143:86740a56073b 8338 /*!
AnnaBridge 143:86740a56073b 8339 * @addtogroup RNG_Register_Masks RNG Register Masks
AnnaBridge 143:86740a56073b 8340 * @{
AnnaBridge 143:86740a56073b 8341 */
AnnaBridge 143:86740a56073b 8342
AnnaBridge 143:86740a56073b 8343 /*! @name CR - RNGA Control Register */
AnnaBridge 143:86740a56073b 8344 #define RNG_CR_GO_MASK (0x1U)
AnnaBridge 143:86740a56073b 8345 #define RNG_CR_GO_SHIFT (0U)
AnnaBridge 143:86740a56073b 8346 #define RNG_CR_GO(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_GO_SHIFT)) & RNG_CR_GO_MASK)
AnnaBridge 143:86740a56073b 8347 #define RNG_CR_HA_MASK (0x2U)
AnnaBridge 143:86740a56073b 8348 #define RNG_CR_HA_SHIFT (1U)
AnnaBridge 143:86740a56073b 8349 #define RNG_CR_HA(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_HA_SHIFT)) & RNG_CR_HA_MASK)
AnnaBridge 143:86740a56073b 8350 #define RNG_CR_INTM_MASK (0x4U)
AnnaBridge 143:86740a56073b 8351 #define RNG_CR_INTM_SHIFT (2U)
AnnaBridge 143:86740a56073b 8352 #define RNG_CR_INTM(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_INTM_SHIFT)) & RNG_CR_INTM_MASK)
AnnaBridge 143:86740a56073b 8353 #define RNG_CR_CLRI_MASK (0x8U)
AnnaBridge 143:86740a56073b 8354 #define RNG_CR_CLRI_SHIFT (3U)
AnnaBridge 143:86740a56073b 8355 #define RNG_CR_CLRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_CLRI_SHIFT)) & RNG_CR_CLRI_MASK)
AnnaBridge 143:86740a56073b 8356 #define RNG_CR_SLP_MASK (0x10U)
AnnaBridge 143:86740a56073b 8357 #define RNG_CR_SLP_SHIFT (4U)
AnnaBridge 143:86740a56073b 8358 #define RNG_CR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_CR_SLP_SHIFT)) & RNG_CR_SLP_MASK)
AnnaBridge 143:86740a56073b 8359
AnnaBridge 143:86740a56073b 8360 /*! @name SR - RNGA Status Register */
AnnaBridge 143:86740a56073b 8361 #define RNG_SR_SECV_MASK (0x1U)
AnnaBridge 143:86740a56073b 8362 #define RNG_SR_SECV_SHIFT (0U)
AnnaBridge 143:86740a56073b 8363 #define RNG_SR_SECV(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SECV_SHIFT)) & RNG_SR_SECV_MASK)
AnnaBridge 143:86740a56073b 8364 #define RNG_SR_LRS_MASK (0x2U)
AnnaBridge 143:86740a56073b 8365 #define RNG_SR_LRS_SHIFT (1U)
AnnaBridge 143:86740a56073b 8366 #define RNG_SR_LRS(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_LRS_SHIFT)) & RNG_SR_LRS_MASK)
AnnaBridge 143:86740a56073b 8367 #define RNG_SR_ORU_MASK (0x4U)
AnnaBridge 143:86740a56073b 8368 #define RNG_SR_ORU_SHIFT (2U)
AnnaBridge 143:86740a56073b 8369 #define RNG_SR_ORU(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ORU_SHIFT)) & RNG_SR_ORU_MASK)
AnnaBridge 143:86740a56073b 8370 #define RNG_SR_ERRI_MASK (0x8U)
AnnaBridge 143:86740a56073b 8371 #define RNG_SR_ERRI_SHIFT (3U)
AnnaBridge 143:86740a56073b 8372 #define RNG_SR_ERRI(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_ERRI_SHIFT)) & RNG_SR_ERRI_MASK)
AnnaBridge 143:86740a56073b 8373 #define RNG_SR_SLP_MASK (0x10U)
AnnaBridge 143:86740a56073b 8374 #define RNG_SR_SLP_SHIFT (4U)
AnnaBridge 143:86740a56073b 8375 #define RNG_SR_SLP(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_SLP_SHIFT)) & RNG_SR_SLP_MASK)
AnnaBridge 143:86740a56073b 8376 #define RNG_SR_OREG_LVL_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 8377 #define RNG_SR_OREG_LVL_SHIFT (8U)
AnnaBridge 143:86740a56073b 8378 #define RNG_SR_OREG_LVL(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_LVL_SHIFT)) & RNG_SR_OREG_LVL_MASK)
AnnaBridge 143:86740a56073b 8379 #define RNG_SR_OREG_SIZE_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 8380 #define RNG_SR_OREG_SIZE_SHIFT (16U)
AnnaBridge 143:86740a56073b 8381 #define RNG_SR_OREG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << RNG_SR_OREG_SIZE_SHIFT)) & RNG_SR_OREG_SIZE_MASK)
AnnaBridge 143:86740a56073b 8382
AnnaBridge 143:86740a56073b 8383 /*! @name ER - RNGA Entropy Register */
AnnaBridge 143:86740a56073b 8384 #define RNG_ER_EXT_ENT_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8385 #define RNG_ER_EXT_ENT_SHIFT (0U)
AnnaBridge 143:86740a56073b 8386 #define RNG_ER_EXT_ENT(x) (((uint32_t)(((uint32_t)(x)) << RNG_ER_EXT_ENT_SHIFT)) & RNG_ER_EXT_ENT_MASK)
AnnaBridge 143:86740a56073b 8387
AnnaBridge 143:86740a56073b 8388 /*! @name OR - RNGA Output Register */
AnnaBridge 143:86740a56073b 8389 #define RNG_OR_RANDOUT_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8390 #define RNG_OR_RANDOUT_SHIFT (0U)
AnnaBridge 143:86740a56073b 8391 #define RNG_OR_RANDOUT(x) (((uint32_t)(((uint32_t)(x)) << RNG_OR_RANDOUT_SHIFT)) & RNG_OR_RANDOUT_MASK)
AnnaBridge 143:86740a56073b 8392
AnnaBridge 143:86740a56073b 8393
AnnaBridge 143:86740a56073b 8394 /*!
AnnaBridge 143:86740a56073b 8395 * @}
AnnaBridge 143:86740a56073b 8396 */ /* end of group RNG_Register_Masks */
AnnaBridge 143:86740a56073b 8397
AnnaBridge 143:86740a56073b 8398
AnnaBridge 143:86740a56073b 8399 /* RNG - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 8400 /** Peripheral RNG base address */
AnnaBridge 143:86740a56073b 8401 #define RNG_BASE (0x40029000u)
AnnaBridge 143:86740a56073b 8402 /** Peripheral RNG base pointer */
AnnaBridge 143:86740a56073b 8403 #define RNG ((RNG_Type *)RNG_BASE)
AnnaBridge 143:86740a56073b 8404 /** Array initializer of RNG peripheral base addresses */
AnnaBridge 143:86740a56073b 8405 #define RNG_BASE_ADDRS { RNG_BASE }
AnnaBridge 143:86740a56073b 8406 /** Array initializer of RNG peripheral base pointers */
AnnaBridge 143:86740a56073b 8407 #define RNG_BASE_PTRS { RNG }
AnnaBridge 143:86740a56073b 8408 /** Interrupt vectors for the RNG peripheral type */
AnnaBridge 143:86740a56073b 8409 #define RNG_IRQS { RNG_IRQn }
AnnaBridge 143:86740a56073b 8410
AnnaBridge 143:86740a56073b 8411 /*!
AnnaBridge 143:86740a56073b 8412 * @}
AnnaBridge 143:86740a56073b 8413 */ /* end of group RNG_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 8414
AnnaBridge 143:86740a56073b 8415
AnnaBridge 143:86740a56073b 8416 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8417 -- RTC Peripheral Access Layer
AnnaBridge 143:86740a56073b 8418 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8419
AnnaBridge 143:86740a56073b 8420 /*!
AnnaBridge 143:86740a56073b 8421 * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
AnnaBridge 143:86740a56073b 8422 * @{
AnnaBridge 143:86740a56073b 8423 */
AnnaBridge 143:86740a56073b 8424
AnnaBridge 143:86740a56073b 8425 /** RTC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 8426 typedef struct {
AnnaBridge 143:86740a56073b 8427 __IO uint32_t TSR; /**< RTC Time Seconds Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 8428 __IO uint32_t TPR; /**< RTC Time Prescaler Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 8429 __IO uint32_t TAR; /**< RTC Time Alarm Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 8430 __IO uint32_t TCR; /**< RTC Time Compensation Register, offset: 0xC */
AnnaBridge 143:86740a56073b 8431 __IO uint32_t CR; /**< RTC Control Register, offset: 0x10 */
AnnaBridge 143:86740a56073b 8432 __IO uint32_t SR; /**< RTC Status Register, offset: 0x14 */
AnnaBridge 143:86740a56073b 8433 __IO uint32_t LR; /**< RTC Lock Register, offset: 0x18 */
AnnaBridge 143:86740a56073b 8434 __IO uint32_t IER; /**< RTC Interrupt Enable Register, offset: 0x1C */
AnnaBridge 143:86740a56073b 8435 uint8_t RESERVED_0[2016];
AnnaBridge 143:86740a56073b 8436 __IO uint32_t WAR; /**< RTC Write Access Register, offset: 0x800 */
AnnaBridge 143:86740a56073b 8437 __IO uint32_t RAR; /**< RTC Read Access Register, offset: 0x804 */
AnnaBridge 143:86740a56073b 8438 } RTC_Type;
AnnaBridge 143:86740a56073b 8439
AnnaBridge 143:86740a56073b 8440 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8441 -- RTC Register Masks
AnnaBridge 143:86740a56073b 8442 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8443
AnnaBridge 143:86740a56073b 8444 /*!
AnnaBridge 143:86740a56073b 8445 * @addtogroup RTC_Register_Masks RTC Register Masks
AnnaBridge 143:86740a56073b 8446 * @{
AnnaBridge 143:86740a56073b 8447 */
AnnaBridge 143:86740a56073b 8448
AnnaBridge 143:86740a56073b 8449 /*! @name TSR - RTC Time Seconds Register */
AnnaBridge 143:86740a56073b 8450 #define RTC_TSR_TSR_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8451 #define RTC_TSR_TSR_SHIFT (0U)
AnnaBridge 143:86740a56073b 8452 #define RTC_TSR_TSR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TSR_TSR_SHIFT)) & RTC_TSR_TSR_MASK)
AnnaBridge 143:86740a56073b 8453
AnnaBridge 143:86740a56073b 8454 /*! @name TPR - RTC Time Prescaler Register */
AnnaBridge 143:86740a56073b 8455 #define RTC_TPR_TPR_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 8456 #define RTC_TPR_TPR_SHIFT (0U)
AnnaBridge 143:86740a56073b 8457 #define RTC_TPR_TPR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TPR_TPR_SHIFT)) & RTC_TPR_TPR_MASK)
AnnaBridge 143:86740a56073b 8458
AnnaBridge 143:86740a56073b 8459 /*! @name TAR - RTC Time Alarm Register */
AnnaBridge 143:86740a56073b 8460 #define RTC_TAR_TAR_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8461 #define RTC_TAR_TAR_SHIFT (0U)
AnnaBridge 143:86740a56073b 8462 #define RTC_TAR_TAR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TAR_TAR_SHIFT)) & RTC_TAR_TAR_MASK)
AnnaBridge 143:86740a56073b 8463
AnnaBridge 143:86740a56073b 8464 /*! @name TCR - RTC Time Compensation Register */
AnnaBridge 143:86740a56073b 8465 #define RTC_TCR_TCR_MASK (0xFFU)
AnnaBridge 143:86740a56073b 8466 #define RTC_TCR_TCR_SHIFT (0U)
AnnaBridge 143:86740a56073b 8467 #define RTC_TCR_TCR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCR_SHIFT)) & RTC_TCR_TCR_MASK)
AnnaBridge 143:86740a56073b 8468 #define RTC_TCR_CIR_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 8469 #define RTC_TCR_CIR_SHIFT (8U)
AnnaBridge 143:86740a56073b 8470 #define RTC_TCR_CIR(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIR_SHIFT)) & RTC_TCR_CIR_MASK)
AnnaBridge 143:86740a56073b 8471 #define RTC_TCR_TCV_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 8472 #define RTC_TCR_TCV_SHIFT (16U)
AnnaBridge 143:86740a56073b 8473 #define RTC_TCR_TCV(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_TCV_SHIFT)) & RTC_TCR_TCV_MASK)
AnnaBridge 143:86740a56073b 8474 #define RTC_TCR_CIC_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 8475 #define RTC_TCR_CIC_SHIFT (24U)
AnnaBridge 143:86740a56073b 8476 #define RTC_TCR_CIC(x) (((uint32_t)(((uint32_t)(x)) << RTC_TCR_CIC_SHIFT)) & RTC_TCR_CIC_MASK)
AnnaBridge 143:86740a56073b 8477
AnnaBridge 143:86740a56073b 8478 /*! @name CR - RTC Control Register */
AnnaBridge 143:86740a56073b 8479 #define RTC_CR_SWR_MASK (0x1U)
AnnaBridge 143:86740a56073b 8480 #define RTC_CR_SWR_SHIFT (0U)
AnnaBridge 143:86740a56073b 8481 #define RTC_CR_SWR(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SWR_SHIFT)) & RTC_CR_SWR_MASK)
AnnaBridge 143:86740a56073b 8482 #define RTC_CR_WPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 8483 #define RTC_CR_WPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 8484 #define RTC_CR_WPE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPE_SHIFT)) & RTC_CR_WPE_MASK)
AnnaBridge 143:86740a56073b 8485 #define RTC_CR_SUP_MASK (0x4U)
AnnaBridge 143:86740a56073b 8486 #define RTC_CR_SUP_SHIFT (2U)
AnnaBridge 143:86740a56073b 8487 #define RTC_CR_SUP(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SUP_SHIFT)) & RTC_CR_SUP_MASK)
AnnaBridge 143:86740a56073b 8488 #define RTC_CR_UM_MASK (0x8U)
AnnaBridge 143:86740a56073b 8489 #define RTC_CR_UM_SHIFT (3U)
AnnaBridge 143:86740a56073b 8490 #define RTC_CR_UM(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_UM_SHIFT)) & RTC_CR_UM_MASK)
AnnaBridge 143:86740a56073b 8491 #define RTC_CR_WPS_MASK (0x10U)
AnnaBridge 143:86740a56073b 8492 #define RTC_CR_WPS_SHIFT (4U)
AnnaBridge 143:86740a56073b 8493 #define RTC_CR_WPS(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_WPS_SHIFT)) & RTC_CR_WPS_MASK)
AnnaBridge 143:86740a56073b 8494 #define RTC_CR_OSCE_MASK (0x100U)
AnnaBridge 143:86740a56073b 8495 #define RTC_CR_OSCE_SHIFT (8U)
AnnaBridge 143:86740a56073b 8496 #define RTC_CR_OSCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_OSCE_SHIFT)) & RTC_CR_OSCE_MASK)
AnnaBridge 143:86740a56073b 8497 #define RTC_CR_CLKO_MASK (0x200U)
AnnaBridge 143:86740a56073b 8498 #define RTC_CR_CLKO_SHIFT (9U)
AnnaBridge 143:86740a56073b 8499 #define RTC_CR_CLKO(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_CLKO_SHIFT)) & RTC_CR_CLKO_MASK)
AnnaBridge 143:86740a56073b 8500 #define RTC_CR_SC16P_MASK (0x400U)
AnnaBridge 143:86740a56073b 8501 #define RTC_CR_SC16P_SHIFT (10U)
AnnaBridge 143:86740a56073b 8502 #define RTC_CR_SC16P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC16P_SHIFT)) & RTC_CR_SC16P_MASK)
AnnaBridge 143:86740a56073b 8503 #define RTC_CR_SC8P_MASK (0x800U)
AnnaBridge 143:86740a56073b 8504 #define RTC_CR_SC8P_SHIFT (11U)
AnnaBridge 143:86740a56073b 8505 #define RTC_CR_SC8P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC8P_SHIFT)) & RTC_CR_SC8P_MASK)
AnnaBridge 143:86740a56073b 8506 #define RTC_CR_SC4P_MASK (0x1000U)
AnnaBridge 143:86740a56073b 8507 #define RTC_CR_SC4P_SHIFT (12U)
AnnaBridge 143:86740a56073b 8508 #define RTC_CR_SC4P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC4P_SHIFT)) & RTC_CR_SC4P_MASK)
AnnaBridge 143:86740a56073b 8509 #define RTC_CR_SC2P_MASK (0x2000U)
AnnaBridge 143:86740a56073b 8510 #define RTC_CR_SC2P_SHIFT (13U)
AnnaBridge 143:86740a56073b 8511 #define RTC_CR_SC2P(x) (((uint32_t)(((uint32_t)(x)) << RTC_CR_SC2P_SHIFT)) & RTC_CR_SC2P_MASK)
AnnaBridge 143:86740a56073b 8512
AnnaBridge 143:86740a56073b 8513 /*! @name SR - RTC Status Register */
AnnaBridge 143:86740a56073b 8514 #define RTC_SR_TIF_MASK (0x1U)
AnnaBridge 143:86740a56073b 8515 #define RTC_SR_TIF_SHIFT (0U)
AnnaBridge 143:86740a56073b 8516 #define RTC_SR_TIF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TIF_SHIFT)) & RTC_SR_TIF_MASK)
AnnaBridge 143:86740a56073b 8517 #define RTC_SR_TOF_MASK (0x2U)
AnnaBridge 143:86740a56073b 8518 #define RTC_SR_TOF_SHIFT (1U)
AnnaBridge 143:86740a56073b 8519 #define RTC_SR_TOF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TOF_SHIFT)) & RTC_SR_TOF_MASK)
AnnaBridge 143:86740a56073b 8520 #define RTC_SR_TAF_MASK (0x4U)
AnnaBridge 143:86740a56073b 8521 #define RTC_SR_TAF_SHIFT (2U)
AnnaBridge 143:86740a56073b 8522 #define RTC_SR_TAF(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TAF_SHIFT)) & RTC_SR_TAF_MASK)
AnnaBridge 143:86740a56073b 8523 #define RTC_SR_TCE_MASK (0x10U)
AnnaBridge 143:86740a56073b 8524 #define RTC_SR_TCE_SHIFT (4U)
AnnaBridge 143:86740a56073b 8525 #define RTC_SR_TCE(x) (((uint32_t)(((uint32_t)(x)) << RTC_SR_TCE_SHIFT)) & RTC_SR_TCE_MASK)
AnnaBridge 143:86740a56073b 8526
AnnaBridge 143:86740a56073b 8527 /*! @name LR - RTC Lock Register */
AnnaBridge 143:86740a56073b 8528 #define RTC_LR_TCL_MASK (0x8U)
AnnaBridge 143:86740a56073b 8529 #define RTC_LR_TCL_SHIFT (3U)
AnnaBridge 143:86740a56073b 8530 #define RTC_LR_TCL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_TCL_SHIFT)) & RTC_LR_TCL_MASK)
AnnaBridge 143:86740a56073b 8531 #define RTC_LR_CRL_MASK (0x10U)
AnnaBridge 143:86740a56073b 8532 #define RTC_LR_CRL_SHIFT (4U)
AnnaBridge 143:86740a56073b 8533 #define RTC_LR_CRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_CRL_SHIFT)) & RTC_LR_CRL_MASK)
AnnaBridge 143:86740a56073b 8534 #define RTC_LR_SRL_MASK (0x20U)
AnnaBridge 143:86740a56073b 8535 #define RTC_LR_SRL_SHIFT (5U)
AnnaBridge 143:86740a56073b 8536 #define RTC_LR_SRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_SRL_SHIFT)) & RTC_LR_SRL_MASK)
AnnaBridge 143:86740a56073b 8537 #define RTC_LR_LRL_MASK (0x40U)
AnnaBridge 143:86740a56073b 8538 #define RTC_LR_LRL_SHIFT (6U)
AnnaBridge 143:86740a56073b 8539 #define RTC_LR_LRL(x) (((uint32_t)(((uint32_t)(x)) << RTC_LR_LRL_SHIFT)) & RTC_LR_LRL_MASK)
AnnaBridge 143:86740a56073b 8540
AnnaBridge 143:86740a56073b 8541 /*! @name IER - RTC Interrupt Enable Register */
AnnaBridge 143:86740a56073b 8542 #define RTC_IER_TIIE_MASK (0x1U)
AnnaBridge 143:86740a56073b 8543 #define RTC_IER_TIIE_SHIFT (0U)
AnnaBridge 143:86740a56073b 8544 #define RTC_IER_TIIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TIIE_SHIFT)) & RTC_IER_TIIE_MASK)
AnnaBridge 143:86740a56073b 8545 #define RTC_IER_TOIE_MASK (0x2U)
AnnaBridge 143:86740a56073b 8546 #define RTC_IER_TOIE_SHIFT (1U)
AnnaBridge 143:86740a56073b 8547 #define RTC_IER_TOIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TOIE_SHIFT)) & RTC_IER_TOIE_MASK)
AnnaBridge 143:86740a56073b 8548 #define RTC_IER_TAIE_MASK (0x4U)
AnnaBridge 143:86740a56073b 8549 #define RTC_IER_TAIE_SHIFT (2U)
AnnaBridge 143:86740a56073b 8550 #define RTC_IER_TAIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TAIE_SHIFT)) & RTC_IER_TAIE_MASK)
AnnaBridge 143:86740a56073b 8551 #define RTC_IER_TSIE_MASK (0x10U)
AnnaBridge 143:86740a56073b 8552 #define RTC_IER_TSIE_SHIFT (4U)
AnnaBridge 143:86740a56073b 8553 #define RTC_IER_TSIE(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_TSIE_SHIFT)) & RTC_IER_TSIE_MASK)
AnnaBridge 143:86740a56073b 8554 #define RTC_IER_WPON_MASK (0x80U)
AnnaBridge 143:86740a56073b 8555 #define RTC_IER_WPON_SHIFT (7U)
AnnaBridge 143:86740a56073b 8556 #define RTC_IER_WPON(x) (((uint32_t)(((uint32_t)(x)) << RTC_IER_WPON_SHIFT)) & RTC_IER_WPON_MASK)
AnnaBridge 143:86740a56073b 8557
AnnaBridge 143:86740a56073b 8558 /*! @name WAR - RTC Write Access Register */
AnnaBridge 143:86740a56073b 8559 #define RTC_WAR_TSRW_MASK (0x1U)
AnnaBridge 143:86740a56073b 8560 #define RTC_WAR_TSRW_SHIFT (0U)
AnnaBridge 143:86740a56073b 8561 #define RTC_WAR_TSRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TSRW_SHIFT)) & RTC_WAR_TSRW_MASK)
AnnaBridge 143:86740a56073b 8562 #define RTC_WAR_TPRW_MASK (0x2U)
AnnaBridge 143:86740a56073b 8563 #define RTC_WAR_TPRW_SHIFT (1U)
AnnaBridge 143:86740a56073b 8564 #define RTC_WAR_TPRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TPRW_SHIFT)) & RTC_WAR_TPRW_MASK)
AnnaBridge 143:86740a56073b 8565 #define RTC_WAR_TARW_MASK (0x4U)
AnnaBridge 143:86740a56073b 8566 #define RTC_WAR_TARW_SHIFT (2U)
AnnaBridge 143:86740a56073b 8567 #define RTC_WAR_TARW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TARW_SHIFT)) & RTC_WAR_TARW_MASK)
AnnaBridge 143:86740a56073b 8568 #define RTC_WAR_TCRW_MASK (0x8U)
AnnaBridge 143:86740a56073b 8569 #define RTC_WAR_TCRW_SHIFT (3U)
AnnaBridge 143:86740a56073b 8570 #define RTC_WAR_TCRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_TCRW_SHIFT)) & RTC_WAR_TCRW_MASK)
AnnaBridge 143:86740a56073b 8571 #define RTC_WAR_CRW_MASK (0x10U)
AnnaBridge 143:86740a56073b 8572 #define RTC_WAR_CRW_SHIFT (4U)
AnnaBridge 143:86740a56073b 8573 #define RTC_WAR_CRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_CRW_SHIFT)) & RTC_WAR_CRW_MASK)
AnnaBridge 143:86740a56073b 8574 #define RTC_WAR_SRW_MASK (0x20U)
AnnaBridge 143:86740a56073b 8575 #define RTC_WAR_SRW_SHIFT (5U)
AnnaBridge 143:86740a56073b 8576 #define RTC_WAR_SRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_SRW_SHIFT)) & RTC_WAR_SRW_MASK)
AnnaBridge 143:86740a56073b 8577 #define RTC_WAR_LRW_MASK (0x40U)
AnnaBridge 143:86740a56073b 8578 #define RTC_WAR_LRW_SHIFT (6U)
AnnaBridge 143:86740a56073b 8579 #define RTC_WAR_LRW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_LRW_SHIFT)) & RTC_WAR_LRW_MASK)
AnnaBridge 143:86740a56073b 8580 #define RTC_WAR_IERW_MASK (0x80U)
AnnaBridge 143:86740a56073b 8581 #define RTC_WAR_IERW_SHIFT (7U)
AnnaBridge 143:86740a56073b 8582 #define RTC_WAR_IERW(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAR_IERW_SHIFT)) & RTC_WAR_IERW_MASK)
AnnaBridge 143:86740a56073b 8583
AnnaBridge 143:86740a56073b 8584 /*! @name RAR - RTC Read Access Register */
AnnaBridge 143:86740a56073b 8585 #define RTC_RAR_TSRR_MASK (0x1U)
AnnaBridge 143:86740a56073b 8586 #define RTC_RAR_TSRR_SHIFT (0U)
AnnaBridge 143:86740a56073b 8587 #define RTC_RAR_TSRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TSRR_SHIFT)) & RTC_RAR_TSRR_MASK)
AnnaBridge 143:86740a56073b 8588 #define RTC_RAR_TPRR_MASK (0x2U)
AnnaBridge 143:86740a56073b 8589 #define RTC_RAR_TPRR_SHIFT (1U)
AnnaBridge 143:86740a56073b 8590 #define RTC_RAR_TPRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TPRR_SHIFT)) & RTC_RAR_TPRR_MASK)
AnnaBridge 143:86740a56073b 8591 #define RTC_RAR_TARR_MASK (0x4U)
AnnaBridge 143:86740a56073b 8592 #define RTC_RAR_TARR_SHIFT (2U)
AnnaBridge 143:86740a56073b 8593 #define RTC_RAR_TARR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TARR_SHIFT)) & RTC_RAR_TARR_MASK)
AnnaBridge 143:86740a56073b 8594 #define RTC_RAR_TCRR_MASK (0x8U)
AnnaBridge 143:86740a56073b 8595 #define RTC_RAR_TCRR_SHIFT (3U)
AnnaBridge 143:86740a56073b 8596 #define RTC_RAR_TCRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_TCRR_SHIFT)) & RTC_RAR_TCRR_MASK)
AnnaBridge 143:86740a56073b 8597 #define RTC_RAR_CRR_MASK (0x10U)
AnnaBridge 143:86740a56073b 8598 #define RTC_RAR_CRR_SHIFT (4U)
AnnaBridge 143:86740a56073b 8599 #define RTC_RAR_CRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_CRR_SHIFT)) & RTC_RAR_CRR_MASK)
AnnaBridge 143:86740a56073b 8600 #define RTC_RAR_SRR_MASK (0x20U)
AnnaBridge 143:86740a56073b 8601 #define RTC_RAR_SRR_SHIFT (5U)
AnnaBridge 143:86740a56073b 8602 #define RTC_RAR_SRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_SRR_SHIFT)) & RTC_RAR_SRR_MASK)
AnnaBridge 143:86740a56073b 8603 #define RTC_RAR_LRR_MASK (0x40U)
AnnaBridge 143:86740a56073b 8604 #define RTC_RAR_LRR_SHIFT (6U)
AnnaBridge 143:86740a56073b 8605 #define RTC_RAR_LRR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_LRR_SHIFT)) & RTC_RAR_LRR_MASK)
AnnaBridge 143:86740a56073b 8606 #define RTC_RAR_IERR_MASK (0x80U)
AnnaBridge 143:86740a56073b 8607 #define RTC_RAR_IERR_SHIFT (7U)
AnnaBridge 143:86740a56073b 8608 #define RTC_RAR_IERR(x) (((uint32_t)(((uint32_t)(x)) << RTC_RAR_IERR_SHIFT)) & RTC_RAR_IERR_MASK)
AnnaBridge 143:86740a56073b 8609
AnnaBridge 143:86740a56073b 8610
AnnaBridge 143:86740a56073b 8611 /*!
AnnaBridge 143:86740a56073b 8612 * @}
AnnaBridge 143:86740a56073b 8613 */ /* end of group RTC_Register_Masks */
AnnaBridge 143:86740a56073b 8614
AnnaBridge 143:86740a56073b 8615
AnnaBridge 143:86740a56073b 8616 /* RTC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 8617 /** Peripheral RTC base address */
AnnaBridge 143:86740a56073b 8618 #define RTC_BASE (0x4003D000u)
AnnaBridge 143:86740a56073b 8619 /** Peripheral RTC base pointer */
AnnaBridge 143:86740a56073b 8620 #define RTC ((RTC_Type *)RTC_BASE)
AnnaBridge 143:86740a56073b 8621 /** Array initializer of RTC peripheral base addresses */
AnnaBridge 143:86740a56073b 8622 #define RTC_BASE_ADDRS { RTC_BASE }
AnnaBridge 143:86740a56073b 8623 /** Array initializer of RTC peripheral base pointers */
AnnaBridge 143:86740a56073b 8624 #define RTC_BASE_PTRS { RTC }
AnnaBridge 143:86740a56073b 8625 /** Interrupt vectors for the RTC peripheral type */
AnnaBridge 143:86740a56073b 8626 #define RTC_IRQS { RTC_IRQn }
AnnaBridge 143:86740a56073b 8627 #define RTC_SECONDS_IRQS { RTC_Seconds_IRQn }
AnnaBridge 143:86740a56073b 8628
AnnaBridge 143:86740a56073b 8629 /*!
AnnaBridge 143:86740a56073b 8630 * @}
AnnaBridge 143:86740a56073b 8631 */ /* end of group RTC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 8632
AnnaBridge 143:86740a56073b 8633
AnnaBridge 143:86740a56073b 8634 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8635 -- SDHC Peripheral Access Layer
AnnaBridge 143:86740a56073b 8636 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8637
AnnaBridge 143:86740a56073b 8638 /*!
AnnaBridge 143:86740a56073b 8639 * @addtogroup SDHC_Peripheral_Access_Layer SDHC Peripheral Access Layer
AnnaBridge 143:86740a56073b 8640 * @{
AnnaBridge 143:86740a56073b 8641 */
AnnaBridge 143:86740a56073b 8642
AnnaBridge 143:86740a56073b 8643 /** SDHC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 8644 typedef struct {
AnnaBridge 143:86740a56073b 8645 __IO uint32_t DSADDR; /**< DMA System Address register, offset: 0x0 */
AnnaBridge 143:86740a56073b 8646 __IO uint32_t BLKATTR; /**< Block Attributes register, offset: 0x4 */
AnnaBridge 143:86740a56073b 8647 __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x8 */
AnnaBridge 143:86740a56073b 8648 __IO uint32_t XFERTYP; /**< Transfer Type register, offset: 0xC */
AnnaBridge 143:86740a56073b 8649 __I uint32_t CMDRSP[4]; /**< Command Response 0..Command Response 3, array offset: 0x10, array step: 0x4 */
AnnaBridge 143:86740a56073b 8650 __IO uint32_t DATPORT; /**< Buffer Data Port register, offset: 0x20 */
AnnaBridge 143:86740a56073b 8651 __I uint32_t PRSSTAT; /**< Present State register, offset: 0x24 */
AnnaBridge 143:86740a56073b 8652 __IO uint32_t PROCTL; /**< Protocol Control register, offset: 0x28 */
AnnaBridge 143:86740a56073b 8653 __IO uint32_t SYSCTL; /**< System Control register, offset: 0x2C */
AnnaBridge 143:86740a56073b 8654 __IO uint32_t IRQSTAT; /**< Interrupt Status register, offset: 0x30 */
AnnaBridge 143:86740a56073b 8655 __IO uint32_t IRQSTATEN; /**< Interrupt Status Enable register, offset: 0x34 */
AnnaBridge 143:86740a56073b 8656 __IO uint32_t IRQSIGEN; /**< Interrupt Signal Enable register, offset: 0x38 */
AnnaBridge 143:86740a56073b 8657 __I uint32_t AC12ERR; /**< Auto CMD12 Error Status Register, offset: 0x3C */
AnnaBridge 143:86740a56073b 8658 __I uint32_t HTCAPBLT; /**< Host Controller Capabilities, offset: 0x40 */
AnnaBridge 143:86740a56073b 8659 __IO uint32_t WML; /**< Watermark Level Register, offset: 0x44 */
AnnaBridge 143:86740a56073b 8660 uint8_t RESERVED_0[8];
AnnaBridge 143:86740a56073b 8661 __O uint32_t FEVT; /**< Force Event register, offset: 0x50 */
AnnaBridge 143:86740a56073b 8662 __I uint32_t ADMAES; /**< ADMA Error Status register, offset: 0x54 */
AnnaBridge 143:86740a56073b 8663 __IO uint32_t ADSADDR; /**< ADMA System Addressregister, offset: 0x58 */
AnnaBridge 143:86740a56073b 8664 uint8_t RESERVED_1[100];
AnnaBridge 143:86740a56073b 8665 __IO uint32_t VENDOR; /**< Vendor Specific register, offset: 0xC0 */
AnnaBridge 143:86740a56073b 8666 __IO uint32_t MMCBOOT; /**< MMC Boot register, offset: 0xC4 */
AnnaBridge 143:86740a56073b 8667 uint8_t RESERVED_2[52];
AnnaBridge 143:86740a56073b 8668 __I uint32_t HOSTVER; /**< Host Controller Version, offset: 0xFC */
AnnaBridge 143:86740a56073b 8669 } SDHC_Type;
AnnaBridge 143:86740a56073b 8670
AnnaBridge 143:86740a56073b 8671 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 8672 -- SDHC Register Masks
AnnaBridge 143:86740a56073b 8673 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 8674
AnnaBridge 143:86740a56073b 8675 /*!
AnnaBridge 143:86740a56073b 8676 * @addtogroup SDHC_Register_Masks SDHC Register Masks
AnnaBridge 143:86740a56073b 8677 * @{
AnnaBridge 143:86740a56073b 8678 */
AnnaBridge 143:86740a56073b 8679
AnnaBridge 143:86740a56073b 8680 /*! @name DSADDR - DMA System Address register */
AnnaBridge 143:86740a56073b 8681 #define SDHC_DSADDR_DSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 143:86740a56073b 8682 #define SDHC_DSADDR_DSADDR_SHIFT (2U)
AnnaBridge 143:86740a56073b 8683 #define SDHC_DSADDR_DSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DSADDR_DSADDR_SHIFT)) & SDHC_DSADDR_DSADDR_MASK)
AnnaBridge 143:86740a56073b 8684
AnnaBridge 143:86740a56073b 8685 /*! @name BLKATTR - Block Attributes register */
AnnaBridge 143:86740a56073b 8686 #define SDHC_BLKATTR_BLKSIZE_MASK (0x1FFFU)
AnnaBridge 143:86740a56073b 8687 #define SDHC_BLKATTR_BLKSIZE_SHIFT (0U)
AnnaBridge 143:86740a56073b 8688 #define SDHC_BLKATTR_BLKSIZE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKSIZE_SHIFT)) & SDHC_BLKATTR_BLKSIZE_MASK)
AnnaBridge 143:86740a56073b 8689 #define SDHC_BLKATTR_BLKCNT_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 8690 #define SDHC_BLKATTR_BLKCNT_SHIFT (16U)
AnnaBridge 143:86740a56073b 8691 #define SDHC_BLKATTR_BLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_BLKATTR_BLKCNT_SHIFT)) & SDHC_BLKATTR_BLKCNT_MASK)
AnnaBridge 143:86740a56073b 8692
AnnaBridge 143:86740a56073b 8693 /*! @name CMDARG - Command Argument register */
AnnaBridge 143:86740a56073b 8694 #define SDHC_CMDARG_CMDARG_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8695 #define SDHC_CMDARG_CMDARG_SHIFT (0U)
AnnaBridge 143:86740a56073b 8696 #define SDHC_CMDARG_CMDARG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDARG_CMDARG_SHIFT)) & SDHC_CMDARG_CMDARG_MASK)
AnnaBridge 143:86740a56073b 8697
AnnaBridge 143:86740a56073b 8698 /*! @name XFERTYP - Transfer Type register */
AnnaBridge 143:86740a56073b 8699 #define SDHC_XFERTYP_DMAEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 8700 #define SDHC_XFERTYP_DMAEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 8701 #define SDHC_XFERTYP_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DMAEN_SHIFT)) & SDHC_XFERTYP_DMAEN_MASK)
AnnaBridge 143:86740a56073b 8702 #define SDHC_XFERTYP_BCEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 8703 #define SDHC_XFERTYP_BCEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 8704 #define SDHC_XFERTYP_BCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_BCEN_SHIFT)) & SDHC_XFERTYP_BCEN_MASK)
AnnaBridge 143:86740a56073b 8705 #define SDHC_XFERTYP_AC12EN_MASK (0x4U)
AnnaBridge 143:86740a56073b 8706 #define SDHC_XFERTYP_AC12EN_SHIFT (2U)
AnnaBridge 143:86740a56073b 8707 #define SDHC_XFERTYP_AC12EN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_AC12EN_SHIFT)) & SDHC_XFERTYP_AC12EN_MASK)
AnnaBridge 143:86740a56073b 8708 #define SDHC_XFERTYP_DTDSEL_MASK (0x10U)
AnnaBridge 143:86740a56073b 8709 #define SDHC_XFERTYP_DTDSEL_SHIFT (4U)
AnnaBridge 143:86740a56073b 8710 #define SDHC_XFERTYP_DTDSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DTDSEL_SHIFT)) & SDHC_XFERTYP_DTDSEL_MASK)
AnnaBridge 143:86740a56073b 8711 #define SDHC_XFERTYP_MSBSEL_MASK (0x20U)
AnnaBridge 143:86740a56073b 8712 #define SDHC_XFERTYP_MSBSEL_SHIFT (5U)
AnnaBridge 143:86740a56073b 8713 #define SDHC_XFERTYP_MSBSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_MSBSEL_SHIFT)) & SDHC_XFERTYP_MSBSEL_MASK)
AnnaBridge 143:86740a56073b 8714 #define SDHC_XFERTYP_RSPTYP_MASK (0x30000U)
AnnaBridge 143:86740a56073b 8715 #define SDHC_XFERTYP_RSPTYP_SHIFT (16U)
AnnaBridge 143:86740a56073b 8716 #define SDHC_XFERTYP_RSPTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_RSPTYP_SHIFT)) & SDHC_XFERTYP_RSPTYP_MASK)
AnnaBridge 143:86740a56073b 8717 #define SDHC_XFERTYP_CCCEN_MASK (0x80000U)
AnnaBridge 143:86740a56073b 8718 #define SDHC_XFERTYP_CCCEN_SHIFT (19U)
AnnaBridge 143:86740a56073b 8719 #define SDHC_XFERTYP_CCCEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CCCEN_SHIFT)) & SDHC_XFERTYP_CCCEN_MASK)
AnnaBridge 143:86740a56073b 8720 #define SDHC_XFERTYP_CICEN_MASK (0x100000U)
AnnaBridge 143:86740a56073b 8721 #define SDHC_XFERTYP_CICEN_SHIFT (20U)
AnnaBridge 143:86740a56073b 8722 #define SDHC_XFERTYP_CICEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CICEN_SHIFT)) & SDHC_XFERTYP_CICEN_MASK)
AnnaBridge 143:86740a56073b 8723 #define SDHC_XFERTYP_DPSEL_MASK (0x200000U)
AnnaBridge 143:86740a56073b 8724 #define SDHC_XFERTYP_DPSEL_SHIFT (21U)
AnnaBridge 143:86740a56073b 8725 #define SDHC_XFERTYP_DPSEL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_DPSEL_SHIFT)) & SDHC_XFERTYP_DPSEL_MASK)
AnnaBridge 143:86740a56073b 8726 #define SDHC_XFERTYP_CMDTYP_MASK (0xC00000U)
AnnaBridge 143:86740a56073b 8727 #define SDHC_XFERTYP_CMDTYP_SHIFT (22U)
AnnaBridge 143:86740a56073b 8728 #define SDHC_XFERTYP_CMDTYP(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDTYP_SHIFT)) & SDHC_XFERTYP_CMDTYP_MASK)
AnnaBridge 143:86740a56073b 8729 #define SDHC_XFERTYP_CMDINX_MASK (0x3F000000U)
AnnaBridge 143:86740a56073b 8730 #define SDHC_XFERTYP_CMDINX_SHIFT (24U)
AnnaBridge 143:86740a56073b 8731 #define SDHC_XFERTYP_CMDINX(x) (((uint32_t)(((uint32_t)(x)) << SDHC_XFERTYP_CMDINX_SHIFT)) & SDHC_XFERTYP_CMDINX_MASK)
AnnaBridge 143:86740a56073b 8732
AnnaBridge 143:86740a56073b 8733 /*! @name CMDRSP - Command Response 0..Command Response 3 */
AnnaBridge 143:86740a56073b 8734 #define SDHC_CMDRSP_CMDRSP0_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8735 #define SDHC_CMDRSP_CMDRSP0_SHIFT (0U)
AnnaBridge 143:86740a56073b 8736 #define SDHC_CMDRSP_CMDRSP0(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP0_SHIFT)) & SDHC_CMDRSP_CMDRSP0_MASK)
AnnaBridge 143:86740a56073b 8737 #define SDHC_CMDRSP_CMDRSP1_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8738 #define SDHC_CMDRSP_CMDRSP1_SHIFT (0U)
AnnaBridge 143:86740a56073b 8739 #define SDHC_CMDRSP_CMDRSP1(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP1_SHIFT)) & SDHC_CMDRSP_CMDRSP1_MASK)
AnnaBridge 143:86740a56073b 8740 #define SDHC_CMDRSP_CMDRSP2_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8741 #define SDHC_CMDRSP_CMDRSP2_SHIFT (0U)
AnnaBridge 143:86740a56073b 8742 #define SDHC_CMDRSP_CMDRSP2(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP2_SHIFT)) & SDHC_CMDRSP_CMDRSP2_MASK)
AnnaBridge 143:86740a56073b 8743 #define SDHC_CMDRSP_CMDRSP3_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8744 #define SDHC_CMDRSP_CMDRSP3_SHIFT (0U)
AnnaBridge 143:86740a56073b 8745 #define SDHC_CMDRSP_CMDRSP3(x) (((uint32_t)(((uint32_t)(x)) << SDHC_CMDRSP_CMDRSP3_SHIFT)) & SDHC_CMDRSP_CMDRSP3_MASK)
AnnaBridge 143:86740a56073b 8746
AnnaBridge 143:86740a56073b 8747 /* The count of SDHC_CMDRSP */
AnnaBridge 143:86740a56073b 8748 #define SDHC_CMDRSP_COUNT (4U)
AnnaBridge 143:86740a56073b 8749
AnnaBridge 143:86740a56073b 8750 /*! @name DATPORT - Buffer Data Port register */
AnnaBridge 143:86740a56073b 8751 #define SDHC_DATPORT_DATCONT_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 8752 #define SDHC_DATPORT_DATCONT_SHIFT (0U)
AnnaBridge 143:86740a56073b 8753 #define SDHC_DATPORT_DATCONT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_DATPORT_DATCONT_SHIFT)) & SDHC_DATPORT_DATCONT_MASK)
AnnaBridge 143:86740a56073b 8754
AnnaBridge 143:86740a56073b 8755 /*! @name PRSSTAT - Present State register */
AnnaBridge 143:86740a56073b 8756 #define SDHC_PRSSTAT_CIHB_MASK (0x1U)
AnnaBridge 143:86740a56073b 8757 #define SDHC_PRSSTAT_CIHB_SHIFT (0U)
AnnaBridge 143:86740a56073b 8758 #define SDHC_PRSSTAT_CIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CIHB_SHIFT)) & SDHC_PRSSTAT_CIHB_MASK)
AnnaBridge 143:86740a56073b 8759 #define SDHC_PRSSTAT_CDIHB_MASK (0x2U)
AnnaBridge 143:86740a56073b 8760 #define SDHC_PRSSTAT_CDIHB_SHIFT (1U)
AnnaBridge 143:86740a56073b 8761 #define SDHC_PRSSTAT_CDIHB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CDIHB_SHIFT)) & SDHC_PRSSTAT_CDIHB_MASK)
AnnaBridge 143:86740a56073b 8762 #define SDHC_PRSSTAT_DLA_MASK (0x4U)
AnnaBridge 143:86740a56073b 8763 #define SDHC_PRSSTAT_DLA_SHIFT (2U)
AnnaBridge 143:86740a56073b 8764 #define SDHC_PRSSTAT_DLA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLA_SHIFT)) & SDHC_PRSSTAT_DLA_MASK)
AnnaBridge 143:86740a56073b 8765 #define SDHC_PRSSTAT_SDSTB_MASK (0x8U)
AnnaBridge 143:86740a56073b 8766 #define SDHC_PRSSTAT_SDSTB_SHIFT (3U)
AnnaBridge 143:86740a56073b 8767 #define SDHC_PRSSTAT_SDSTB(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDSTB_SHIFT)) & SDHC_PRSSTAT_SDSTB_MASK)
AnnaBridge 143:86740a56073b 8768 #define SDHC_PRSSTAT_IPGOFF_MASK (0x10U)
AnnaBridge 143:86740a56073b 8769 #define SDHC_PRSSTAT_IPGOFF_SHIFT (4U)
AnnaBridge 143:86740a56073b 8770 #define SDHC_PRSSTAT_IPGOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_IPGOFF_SHIFT)) & SDHC_PRSSTAT_IPGOFF_MASK)
AnnaBridge 143:86740a56073b 8771 #define SDHC_PRSSTAT_HCKOFF_MASK (0x20U)
AnnaBridge 143:86740a56073b 8772 #define SDHC_PRSSTAT_HCKOFF_SHIFT (5U)
AnnaBridge 143:86740a56073b 8773 #define SDHC_PRSSTAT_HCKOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_HCKOFF_SHIFT)) & SDHC_PRSSTAT_HCKOFF_MASK)
AnnaBridge 143:86740a56073b 8774 #define SDHC_PRSSTAT_PEROFF_MASK (0x40U)
AnnaBridge 143:86740a56073b 8775 #define SDHC_PRSSTAT_PEROFF_SHIFT (6U)
AnnaBridge 143:86740a56073b 8776 #define SDHC_PRSSTAT_PEROFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_PEROFF_SHIFT)) & SDHC_PRSSTAT_PEROFF_MASK)
AnnaBridge 143:86740a56073b 8777 #define SDHC_PRSSTAT_SDOFF_MASK (0x80U)
AnnaBridge 143:86740a56073b 8778 #define SDHC_PRSSTAT_SDOFF_SHIFT (7U)
AnnaBridge 143:86740a56073b 8779 #define SDHC_PRSSTAT_SDOFF(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_SDOFF_SHIFT)) & SDHC_PRSSTAT_SDOFF_MASK)
AnnaBridge 143:86740a56073b 8780 #define SDHC_PRSSTAT_WTA_MASK (0x100U)
AnnaBridge 143:86740a56073b 8781 #define SDHC_PRSSTAT_WTA_SHIFT (8U)
AnnaBridge 143:86740a56073b 8782 #define SDHC_PRSSTAT_WTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_WTA_SHIFT)) & SDHC_PRSSTAT_WTA_MASK)
AnnaBridge 143:86740a56073b 8783 #define SDHC_PRSSTAT_RTA_MASK (0x200U)
AnnaBridge 143:86740a56073b 8784 #define SDHC_PRSSTAT_RTA_SHIFT (9U)
AnnaBridge 143:86740a56073b 8785 #define SDHC_PRSSTAT_RTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_RTA_SHIFT)) & SDHC_PRSSTAT_RTA_MASK)
AnnaBridge 143:86740a56073b 8786 #define SDHC_PRSSTAT_BWEN_MASK (0x400U)
AnnaBridge 143:86740a56073b 8787 #define SDHC_PRSSTAT_BWEN_SHIFT (10U)
AnnaBridge 143:86740a56073b 8788 #define SDHC_PRSSTAT_BWEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BWEN_SHIFT)) & SDHC_PRSSTAT_BWEN_MASK)
AnnaBridge 143:86740a56073b 8789 #define SDHC_PRSSTAT_BREN_MASK (0x800U)
AnnaBridge 143:86740a56073b 8790 #define SDHC_PRSSTAT_BREN_SHIFT (11U)
AnnaBridge 143:86740a56073b 8791 #define SDHC_PRSSTAT_BREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_BREN_SHIFT)) & SDHC_PRSSTAT_BREN_MASK)
AnnaBridge 143:86740a56073b 8792 #define SDHC_PRSSTAT_CINS_MASK (0x10000U)
AnnaBridge 143:86740a56073b 8793 #define SDHC_PRSSTAT_CINS_SHIFT (16U)
AnnaBridge 143:86740a56073b 8794 #define SDHC_PRSSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CINS_SHIFT)) & SDHC_PRSSTAT_CINS_MASK)
AnnaBridge 143:86740a56073b 8795 #define SDHC_PRSSTAT_CLSL_MASK (0x800000U)
AnnaBridge 143:86740a56073b 8796 #define SDHC_PRSSTAT_CLSL_SHIFT (23U)
AnnaBridge 143:86740a56073b 8797 #define SDHC_PRSSTAT_CLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_CLSL_SHIFT)) & SDHC_PRSSTAT_CLSL_MASK)
AnnaBridge 143:86740a56073b 8798 #define SDHC_PRSSTAT_DLSL_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 8799 #define SDHC_PRSSTAT_DLSL_SHIFT (24U)
AnnaBridge 143:86740a56073b 8800 #define SDHC_PRSSTAT_DLSL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PRSSTAT_DLSL_SHIFT)) & SDHC_PRSSTAT_DLSL_MASK)
AnnaBridge 143:86740a56073b 8801
AnnaBridge 143:86740a56073b 8802 /*! @name PROCTL - Protocol Control register */
AnnaBridge 143:86740a56073b 8803 #define SDHC_PROCTL_LCTL_MASK (0x1U)
AnnaBridge 143:86740a56073b 8804 #define SDHC_PROCTL_LCTL_SHIFT (0U)
AnnaBridge 143:86740a56073b 8805 #define SDHC_PROCTL_LCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_LCTL_SHIFT)) & SDHC_PROCTL_LCTL_MASK)
AnnaBridge 143:86740a56073b 8806 #define SDHC_PROCTL_DTW_MASK (0x6U)
AnnaBridge 143:86740a56073b 8807 #define SDHC_PROCTL_DTW_SHIFT (1U)
AnnaBridge 143:86740a56073b 8808 #define SDHC_PROCTL_DTW(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DTW_SHIFT)) & SDHC_PROCTL_DTW_MASK)
AnnaBridge 143:86740a56073b 8809 #define SDHC_PROCTL_D3CD_MASK (0x8U)
AnnaBridge 143:86740a56073b 8810 #define SDHC_PROCTL_D3CD_SHIFT (3U)
AnnaBridge 143:86740a56073b 8811 #define SDHC_PROCTL_D3CD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_D3CD_SHIFT)) & SDHC_PROCTL_D3CD_MASK)
AnnaBridge 143:86740a56073b 8812 #define SDHC_PROCTL_EMODE_MASK (0x30U)
AnnaBridge 143:86740a56073b 8813 #define SDHC_PROCTL_EMODE_SHIFT (4U)
AnnaBridge 143:86740a56073b 8814 #define SDHC_PROCTL_EMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_EMODE_SHIFT)) & SDHC_PROCTL_EMODE_MASK)
AnnaBridge 143:86740a56073b 8815 #define SDHC_PROCTL_CDTL_MASK (0x40U)
AnnaBridge 143:86740a56073b 8816 #define SDHC_PROCTL_CDTL_SHIFT (6U)
AnnaBridge 143:86740a56073b 8817 #define SDHC_PROCTL_CDTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDTL_SHIFT)) & SDHC_PROCTL_CDTL_MASK)
AnnaBridge 143:86740a56073b 8818 #define SDHC_PROCTL_CDSS_MASK (0x80U)
AnnaBridge 143:86740a56073b 8819 #define SDHC_PROCTL_CDSS_SHIFT (7U)
AnnaBridge 143:86740a56073b 8820 #define SDHC_PROCTL_CDSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CDSS_SHIFT)) & SDHC_PROCTL_CDSS_MASK)
AnnaBridge 143:86740a56073b 8821 #define SDHC_PROCTL_DMAS_MASK (0x300U)
AnnaBridge 143:86740a56073b 8822 #define SDHC_PROCTL_DMAS_SHIFT (8U)
AnnaBridge 143:86740a56073b 8823 #define SDHC_PROCTL_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_DMAS_SHIFT)) & SDHC_PROCTL_DMAS_MASK)
AnnaBridge 143:86740a56073b 8824 #define SDHC_PROCTL_SABGREQ_MASK (0x10000U)
AnnaBridge 143:86740a56073b 8825 #define SDHC_PROCTL_SABGREQ_SHIFT (16U)
AnnaBridge 143:86740a56073b 8826 #define SDHC_PROCTL_SABGREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_SABGREQ_SHIFT)) & SDHC_PROCTL_SABGREQ_MASK)
AnnaBridge 143:86740a56073b 8827 #define SDHC_PROCTL_CREQ_MASK (0x20000U)
AnnaBridge 143:86740a56073b 8828 #define SDHC_PROCTL_CREQ_SHIFT (17U)
AnnaBridge 143:86740a56073b 8829 #define SDHC_PROCTL_CREQ(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_CREQ_SHIFT)) & SDHC_PROCTL_CREQ_MASK)
AnnaBridge 143:86740a56073b 8830 #define SDHC_PROCTL_RWCTL_MASK (0x40000U)
AnnaBridge 143:86740a56073b 8831 #define SDHC_PROCTL_RWCTL_SHIFT (18U)
AnnaBridge 143:86740a56073b 8832 #define SDHC_PROCTL_RWCTL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_RWCTL_SHIFT)) & SDHC_PROCTL_RWCTL_MASK)
AnnaBridge 143:86740a56073b 8833 #define SDHC_PROCTL_IABG_MASK (0x80000U)
AnnaBridge 143:86740a56073b 8834 #define SDHC_PROCTL_IABG_SHIFT (19U)
AnnaBridge 143:86740a56073b 8835 #define SDHC_PROCTL_IABG(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_IABG_SHIFT)) & SDHC_PROCTL_IABG_MASK)
AnnaBridge 143:86740a56073b 8836 #define SDHC_PROCTL_WECINT_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 8837 #define SDHC_PROCTL_WECINT_SHIFT (24U)
AnnaBridge 143:86740a56073b 8838 #define SDHC_PROCTL_WECINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINT_SHIFT)) & SDHC_PROCTL_WECINT_MASK)
AnnaBridge 143:86740a56073b 8839 #define SDHC_PROCTL_WECINS_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 8840 #define SDHC_PROCTL_WECINS_SHIFT (25U)
AnnaBridge 143:86740a56073b 8841 #define SDHC_PROCTL_WECINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECINS_SHIFT)) & SDHC_PROCTL_WECINS_MASK)
AnnaBridge 143:86740a56073b 8842 #define SDHC_PROCTL_WECRM_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 8843 #define SDHC_PROCTL_WECRM_SHIFT (26U)
AnnaBridge 143:86740a56073b 8844 #define SDHC_PROCTL_WECRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_PROCTL_WECRM_SHIFT)) & SDHC_PROCTL_WECRM_MASK)
AnnaBridge 143:86740a56073b 8845
AnnaBridge 143:86740a56073b 8846 /*! @name SYSCTL - System Control register */
AnnaBridge 143:86740a56073b 8847 #define SDHC_SYSCTL_IPGEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 8848 #define SDHC_SYSCTL_IPGEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 8849 #define SDHC_SYSCTL_IPGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_IPGEN_SHIFT)) & SDHC_SYSCTL_IPGEN_MASK)
AnnaBridge 143:86740a56073b 8850 #define SDHC_SYSCTL_HCKEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 8851 #define SDHC_SYSCTL_HCKEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 8852 #define SDHC_SYSCTL_HCKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_HCKEN_SHIFT)) & SDHC_SYSCTL_HCKEN_MASK)
AnnaBridge 143:86740a56073b 8853 #define SDHC_SYSCTL_PEREN_MASK (0x4U)
AnnaBridge 143:86740a56073b 8854 #define SDHC_SYSCTL_PEREN_SHIFT (2U)
AnnaBridge 143:86740a56073b 8855 #define SDHC_SYSCTL_PEREN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_PEREN_SHIFT)) & SDHC_SYSCTL_PEREN_MASK)
AnnaBridge 143:86740a56073b 8856 #define SDHC_SYSCTL_SDCLKEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 8857 #define SDHC_SYSCTL_SDCLKEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 8858 #define SDHC_SYSCTL_SDCLKEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKEN_SHIFT)) & SDHC_SYSCTL_SDCLKEN_MASK)
AnnaBridge 143:86740a56073b 8859 #define SDHC_SYSCTL_DVS_MASK (0xF0U)
AnnaBridge 143:86740a56073b 8860 #define SDHC_SYSCTL_DVS_SHIFT (4U)
AnnaBridge 143:86740a56073b 8861 #define SDHC_SYSCTL_DVS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DVS_SHIFT)) & SDHC_SYSCTL_DVS_MASK)
AnnaBridge 143:86740a56073b 8862 #define SDHC_SYSCTL_SDCLKFS_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 8863 #define SDHC_SYSCTL_SDCLKFS_SHIFT (8U)
AnnaBridge 143:86740a56073b 8864 #define SDHC_SYSCTL_SDCLKFS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_SDCLKFS_SHIFT)) & SDHC_SYSCTL_SDCLKFS_MASK)
AnnaBridge 143:86740a56073b 8865 #define SDHC_SYSCTL_DTOCV_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 8866 #define SDHC_SYSCTL_DTOCV_SHIFT (16U)
AnnaBridge 143:86740a56073b 8867 #define SDHC_SYSCTL_DTOCV(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_DTOCV_SHIFT)) & SDHC_SYSCTL_DTOCV_MASK)
AnnaBridge 143:86740a56073b 8868 #define SDHC_SYSCTL_RSTA_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 8869 #define SDHC_SYSCTL_RSTA_SHIFT (24U)
AnnaBridge 143:86740a56073b 8870 #define SDHC_SYSCTL_RSTA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTA_SHIFT)) & SDHC_SYSCTL_RSTA_MASK)
AnnaBridge 143:86740a56073b 8871 #define SDHC_SYSCTL_RSTC_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 8872 #define SDHC_SYSCTL_RSTC_SHIFT (25U)
AnnaBridge 143:86740a56073b 8873 #define SDHC_SYSCTL_RSTC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTC_SHIFT)) & SDHC_SYSCTL_RSTC_MASK)
AnnaBridge 143:86740a56073b 8874 #define SDHC_SYSCTL_RSTD_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 8875 #define SDHC_SYSCTL_RSTD_SHIFT (26U)
AnnaBridge 143:86740a56073b 8876 #define SDHC_SYSCTL_RSTD(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_RSTD_SHIFT)) & SDHC_SYSCTL_RSTD_MASK)
AnnaBridge 143:86740a56073b 8877 #define SDHC_SYSCTL_INITA_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 8878 #define SDHC_SYSCTL_INITA_SHIFT (27U)
AnnaBridge 143:86740a56073b 8879 #define SDHC_SYSCTL_INITA(x) (((uint32_t)(((uint32_t)(x)) << SDHC_SYSCTL_INITA_SHIFT)) & SDHC_SYSCTL_INITA_MASK)
AnnaBridge 143:86740a56073b 8880
AnnaBridge 143:86740a56073b 8881 /*! @name IRQSTAT - Interrupt Status register */
AnnaBridge 143:86740a56073b 8882 #define SDHC_IRQSTAT_CC_MASK (0x1U)
AnnaBridge 143:86740a56073b 8883 #define SDHC_IRQSTAT_CC_SHIFT (0U)
AnnaBridge 143:86740a56073b 8884 #define SDHC_IRQSTAT_CC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CC_SHIFT)) & SDHC_IRQSTAT_CC_MASK)
AnnaBridge 143:86740a56073b 8885 #define SDHC_IRQSTAT_TC_MASK (0x2U)
AnnaBridge 143:86740a56073b 8886 #define SDHC_IRQSTAT_TC_SHIFT (1U)
AnnaBridge 143:86740a56073b 8887 #define SDHC_IRQSTAT_TC(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_TC_SHIFT)) & SDHC_IRQSTAT_TC_MASK)
AnnaBridge 143:86740a56073b 8888 #define SDHC_IRQSTAT_BGE_MASK (0x4U)
AnnaBridge 143:86740a56073b 8889 #define SDHC_IRQSTAT_BGE_SHIFT (2U)
AnnaBridge 143:86740a56073b 8890 #define SDHC_IRQSTAT_BGE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BGE_SHIFT)) & SDHC_IRQSTAT_BGE_MASK)
AnnaBridge 143:86740a56073b 8891 #define SDHC_IRQSTAT_DINT_MASK (0x8U)
AnnaBridge 143:86740a56073b 8892 #define SDHC_IRQSTAT_DINT_SHIFT (3U)
AnnaBridge 143:86740a56073b 8893 #define SDHC_IRQSTAT_DINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DINT_SHIFT)) & SDHC_IRQSTAT_DINT_MASK)
AnnaBridge 143:86740a56073b 8894 #define SDHC_IRQSTAT_BWR_MASK (0x10U)
AnnaBridge 143:86740a56073b 8895 #define SDHC_IRQSTAT_BWR_SHIFT (4U)
AnnaBridge 143:86740a56073b 8896 #define SDHC_IRQSTAT_BWR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BWR_SHIFT)) & SDHC_IRQSTAT_BWR_MASK)
AnnaBridge 143:86740a56073b 8897 #define SDHC_IRQSTAT_BRR_MASK (0x20U)
AnnaBridge 143:86740a56073b 8898 #define SDHC_IRQSTAT_BRR_SHIFT (5U)
AnnaBridge 143:86740a56073b 8899 #define SDHC_IRQSTAT_BRR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_BRR_SHIFT)) & SDHC_IRQSTAT_BRR_MASK)
AnnaBridge 143:86740a56073b 8900 #define SDHC_IRQSTAT_CINS_MASK (0x40U)
AnnaBridge 143:86740a56073b 8901 #define SDHC_IRQSTAT_CINS_SHIFT (6U)
AnnaBridge 143:86740a56073b 8902 #define SDHC_IRQSTAT_CINS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINS_SHIFT)) & SDHC_IRQSTAT_CINS_MASK)
AnnaBridge 143:86740a56073b 8903 #define SDHC_IRQSTAT_CRM_MASK (0x80U)
AnnaBridge 143:86740a56073b 8904 #define SDHC_IRQSTAT_CRM_SHIFT (7U)
AnnaBridge 143:86740a56073b 8905 #define SDHC_IRQSTAT_CRM(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CRM_SHIFT)) & SDHC_IRQSTAT_CRM_MASK)
AnnaBridge 143:86740a56073b 8906 #define SDHC_IRQSTAT_CINT_MASK (0x100U)
AnnaBridge 143:86740a56073b 8907 #define SDHC_IRQSTAT_CINT_SHIFT (8U)
AnnaBridge 143:86740a56073b 8908 #define SDHC_IRQSTAT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CINT_SHIFT)) & SDHC_IRQSTAT_CINT_MASK)
AnnaBridge 143:86740a56073b 8909 #define SDHC_IRQSTAT_CTOE_MASK (0x10000U)
AnnaBridge 143:86740a56073b 8910 #define SDHC_IRQSTAT_CTOE_SHIFT (16U)
AnnaBridge 143:86740a56073b 8911 #define SDHC_IRQSTAT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CTOE_SHIFT)) & SDHC_IRQSTAT_CTOE_MASK)
AnnaBridge 143:86740a56073b 8912 #define SDHC_IRQSTAT_CCE_MASK (0x20000U)
AnnaBridge 143:86740a56073b 8913 #define SDHC_IRQSTAT_CCE_SHIFT (17U)
AnnaBridge 143:86740a56073b 8914 #define SDHC_IRQSTAT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CCE_SHIFT)) & SDHC_IRQSTAT_CCE_MASK)
AnnaBridge 143:86740a56073b 8915 #define SDHC_IRQSTAT_CEBE_MASK (0x40000U)
AnnaBridge 143:86740a56073b 8916 #define SDHC_IRQSTAT_CEBE_SHIFT (18U)
AnnaBridge 143:86740a56073b 8917 #define SDHC_IRQSTAT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CEBE_SHIFT)) & SDHC_IRQSTAT_CEBE_MASK)
AnnaBridge 143:86740a56073b 8918 #define SDHC_IRQSTAT_CIE_MASK (0x80000U)
AnnaBridge 143:86740a56073b 8919 #define SDHC_IRQSTAT_CIE_SHIFT (19U)
AnnaBridge 143:86740a56073b 8920 #define SDHC_IRQSTAT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_CIE_SHIFT)) & SDHC_IRQSTAT_CIE_MASK)
AnnaBridge 143:86740a56073b 8921 #define SDHC_IRQSTAT_DTOE_MASK (0x100000U)
AnnaBridge 143:86740a56073b 8922 #define SDHC_IRQSTAT_DTOE_SHIFT (20U)
AnnaBridge 143:86740a56073b 8923 #define SDHC_IRQSTAT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DTOE_SHIFT)) & SDHC_IRQSTAT_DTOE_MASK)
AnnaBridge 143:86740a56073b 8924 #define SDHC_IRQSTAT_DCE_MASK (0x200000U)
AnnaBridge 143:86740a56073b 8925 #define SDHC_IRQSTAT_DCE_SHIFT (21U)
AnnaBridge 143:86740a56073b 8926 #define SDHC_IRQSTAT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DCE_SHIFT)) & SDHC_IRQSTAT_DCE_MASK)
AnnaBridge 143:86740a56073b 8927 #define SDHC_IRQSTAT_DEBE_MASK (0x400000U)
AnnaBridge 143:86740a56073b 8928 #define SDHC_IRQSTAT_DEBE_SHIFT (22U)
AnnaBridge 143:86740a56073b 8929 #define SDHC_IRQSTAT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DEBE_SHIFT)) & SDHC_IRQSTAT_DEBE_MASK)
AnnaBridge 143:86740a56073b 8930 #define SDHC_IRQSTAT_AC12E_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 8931 #define SDHC_IRQSTAT_AC12E_SHIFT (24U)
AnnaBridge 143:86740a56073b 8932 #define SDHC_IRQSTAT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_AC12E_SHIFT)) & SDHC_IRQSTAT_AC12E_MASK)
AnnaBridge 143:86740a56073b 8933 #define SDHC_IRQSTAT_DMAE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 8934 #define SDHC_IRQSTAT_DMAE_SHIFT (28U)
AnnaBridge 143:86740a56073b 8935 #define SDHC_IRQSTAT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTAT_DMAE_SHIFT)) & SDHC_IRQSTAT_DMAE_MASK)
AnnaBridge 143:86740a56073b 8936
AnnaBridge 143:86740a56073b 8937 /*! @name IRQSTATEN - Interrupt Status Enable register */
AnnaBridge 143:86740a56073b 8938 #define SDHC_IRQSTATEN_CCSEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 8939 #define SDHC_IRQSTATEN_CCSEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 8940 #define SDHC_IRQSTATEN_CCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCSEN_SHIFT)) & SDHC_IRQSTATEN_CCSEN_MASK)
AnnaBridge 143:86740a56073b 8941 #define SDHC_IRQSTATEN_TCSEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 8942 #define SDHC_IRQSTATEN_TCSEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 8943 #define SDHC_IRQSTATEN_TCSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_TCSEN_SHIFT)) & SDHC_IRQSTATEN_TCSEN_MASK)
AnnaBridge 143:86740a56073b 8944 #define SDHC_IRQSTATEN_BGESEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 8945 #define SDHC_IRQSTATEN_BGESEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 8946 #define SDHC_IRQSTATEN_BGESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BGESEN_SHIFT)) & SDHC_IRQSTATEN_BGESEN_MASK)
AnnaBridge 143:86740a56073b 8947 #define SDHC_IRQSTATEN_DINTSEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 8948 #define SDHC_IRQSTATEN_DINTSEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 8949 #define SDHC_IRQSTATEN_DINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DINTSEN_SHIFT)) & SDHC_IRQSTATEN_DINTSEN_MASK)
AnnaBridge 143:86740a56073b 8950 #define SDHC_IRQSTATEN_BWRSEN_MASK (0x10U)
AnnaBridge 143:86740a56073b 8951 #define SDHC_IRQSTATEN_BWRSEN_SHIFT (4U)
AnnaBridge 143:86740a56073b 8952 #define SDHC_IRQSTATEN_BWRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BWRSEN_SHIFT)) & SDHC_IRQSTATEN_BWRSEN_MASK)
AnnaBridge 143:86740a56073b 8953 #define SDHC_IRQSTATEN_BRRSEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 8954 #define SDHC_IRQSTATEN_BRRSEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 8955 #define SDHC_IRQSTATEN_BRRSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_BRRSEN_SHIFT)) & SDHC_IRQSTATEN_BRRSEN_MASK)
AnnaBridge 143:86740a56073b 8956 #define SDHC_IRQSTATEN_CINSEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 8957 #define SDHC_IRQSTATEN_CINSEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 8958 #define SDHC_IRQSTATEN_CINSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINSEN_SHIFT)) & SDHC_IRQSTATEN_CINSEN_MASK)
AnnaBridge 143:86740a56073b 8959 #define SDHC_IRQSTATEN_CRMSEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 8960 #define SDHC_IRQSTATEN_CRMSEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 8961 #define SDHC_IRQSTATEN_CRMSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CRMSEN_SHIFT)) & SDHC_IRQSTATEN_CRMSEN_MASK)
AnnaBridge 143:86740a56073b 8962 #define SDHC_IRQSTATEN_CINTSEN_MASK (0x100U)
AnnaBridge 143:86740a56073b 8963 #define SDHC_IRQSTATEN_CINTSEN_SHIFT (8U)
AnnaBridge 143:86740a56073b 8964 #define SDHC_IRQSTATEN_CINTSEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CINTSEN_SHIFT)) & SDHC_IRQSTATEN_CINTSEN_MASK)
AnnaBridge 143:86740a56073b 8965 #define SDHC_IRQSTATEN_CTOESEN_MASK (0x10000U)
AnnaBridge 143:86740a56073b 8966 #define SDHC_IRQSTATEN_CTOESEN_SHIFT (16U)
AnnaBridge 143:86740a56073b 8967 #define SDHC_IRQSTATEN_CTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CTOESEN_SHIFT)) & SDHC_IRQSTATEN_CTOESEN_MASK)
AnnaBridge 143:86740a56073b 8968 #define SDHC_IRQSTATEN_CCESEN_MASK (0x20000U)
AnnaBridge 143:86740a56073b 8969 #define SDHC_IRQSTATEN_CCESEN_SHIFT (17U)
AnnaBridge 143:86740a56073b 8970 #define SDHC_IRQSTATEN_CCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CCESEN_SHIFT)) & SDHC_IRQSTATEN_CCESEN_MASK)
AnnaBridge 143:86740a56073b 8971 #define SDHC_IRQSTATEN_CEBESEN_MASK (0x40000U)
AnnaBridge 143:86740a56073b 8972 #define SDHC_IRQSTATEN_CEBESEN_SHIFT (18U)
AnnaBridge 143:86740a56073b 8973 #define SDHC_IRQSTATEN_CEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CEBESEN_SHIFT)) & SDHC_IRQSTATEN_CEBESEN_MASK)
AnnaBridge 143:86740a56073b 8974 #define SDHC_IRQSTATEN_CIESEN_MASK (0x80000U)
AnnaBridge 143:86740a56073b 8975 #define SDHC_IRQSTATEN_CIESEN_SHIFT (19U)
AnnaBridge 143:86740a56073b 8976 #define SDHC_IRQSTATEN_CIESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_CIESEN_SHIFT)) & SDHC_IRQSTATEN_CIESEN_MASK)
AnnaBridge 143:86740a56073b 8977 #define SDHC_IRQSTATEN_DTOESEN_MASK (0x100000U)
AnnaBridge 143:86740a56073b 8978 #define SDHC_IRQSTATEN_DTOESEN_SHIFT (20U)
AnnaBridge 143:86740a56073b 8979 #define SDHC_IRQSTATEN_DTOESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DTOESEN_SHIFT)) & SDHC_IRQSTATEN_DTOESEN_MASK)
AnnaBridge 143:86740a56073b 8980 #define SDHC_IRQSTATEN_DCESEN_MASK (0x200000U)
AnnaBridge 143:86740a56073b 8981 #define SDHC_IRQSTATEN_DCESEN_SHIFT (21U)
AnnaBridge 143:86740a56073b 8982 #define SDHC_IRQSTATEN_DCESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DCESEN_SHIFT)) & SDHC_IRQSTATEN_DCESEN_MASK)
AnnaBridge 143:86740a56073b 8983 #define SDHC_IRQSTATEN_DEBESEN_MASK (0x400000U)
AnnaBridge 143:86740a56073b 8984 #define SDHC_IRQSTATEN_DEBESEN_SHIFT (22U)
AnnaBridge 143:86740a56073b 8985 #define SDHC_IRQSTATEN_DEBESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DEBESEN_SHIFT)) & SDHC_IRQSTATEN_DEBESEN_MASK)
AnnaBridge 143:86740a56073b 8986 #define SDHC_IRQSTATEN_AC12ESEN_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 8987 #define SDHC_IRQSTATEN_AC12ESEN_SHIFT (24U)
AnnaBridge 143:86740a56073b 8988 #define SDHC_IRQSTATEN_AC12ESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_AC12ESEN_SHIFT)) & SDHC_IRQSTATEN_AC12ESEN_MASK)
AnnaBridge 143:86740a56073b 8989 #define SDHC_IRQSTATEN_DMAESEN_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 8990 #define SDHC_IRQSTATEN_DMAESEN_SHIFT (28U)
AnnaBridge 143:86740a56073b 8991 #define SDHC_IRQSTATEN_DMAESEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSTATEN_DMAESEN_SHIFT)) & SDHC_IRQSTATEN_DMAESEN_MASK)
AnnaBridge 143:86740a56073b 8992
AnnaBridge 143:86740a56073b 8993 /*! @name IRQSIGEN - Interrupt Signal Enable register */
AnnaBridge 143:86740a56073b 8994 #define SDHC_IRQSIGEN_CCIEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 8995 #define SDHC_IRQSIGEN_CCIEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 8996 #define SDHC_IRQSIGEN_CCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCIEN_SHIFT)) & SDHC_IRQSIGEN_CCIEN_MASK)
AnnaBridge 143:86740a56073b 8997 #define SDHC_IRQSIGEN_TCIEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 8998 #define SDHC_IRQSIGEN_TCIEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 8999 #define SDHC_IRQSIGEN_TCIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_TCIEN_SHIFT)) & SDHC_IRQSIGEN_TCIEN_MASK)
AnnaBridge 143:86740a56073b 9000 #define SDHC_IRQSIGEN_BGEIEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 9001 #define SDHC_IRQSIGEN_BGEIEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 9002 #define SDHC_IRQSIGEN_BGEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BGEIEN_SHIFT)) & SDHC_IRQSIGEN_BGEIEN_MASK)
AnnaBridge 143:86740a56073b 9003 #define SDHC_IRQSIGEN_DINTIEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 9004 #define SDHC_IRQSIGEN_DINTIEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 9005 #define SDHC_IRQSIGEN_DINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DINTIEN_SHIFT)) & SDHC_IRQSIGEN_DINTIEN_MASK)
AnnaBridge 143:86740a56073b 9006 #define SDHC_IRQSIGEN_BWRIEN_MASK (0x10U)
AnnaBridge 143:86740a56073b 9007 #define SDHC_IRQSIGEN_BWRIEN_SHIFT (4U)
AnnaBridge 143:86740a56073b 9008 #define SDHC_IRQSIGEN_BWRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BWRIEN_SHIFT)) & SDHC_IRQSIGEN_BWRIEN_MASK)
AnnaBridge 143:86740a56073b 9009 #define SDHC_IRQSIGEN_BRRIEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 9010 #define SDHC_IRQSIGEN_BRRIEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 9011 #define SDHC_IRQSIGEN_BRRIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_BRRIEN_SHIFT)) & SDHC_IRQSIGEN_BRRIEN_MASK)
AnnaBridge 143:86740a56073b 9012 #define SDHC_IRQSIGEN_CINSIEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 9013 #define SDHC_IRQSIGEN_CINSIEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 9014 #define SDHC_IRQSIGEN_CINSIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINSIEN_SHIFT)) & SDHC_IRQSIGEN_CINSIEN_MASK)
AnnaBridge 143:86740a56073b 9015 #define SDHC_IRQSIGEN_CRMIEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 9016 #define SDHC_IRQSIGEN_CRMIEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 9017 #define SDHC_IRQSIGEN_CRMIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CRMIEN_SHIFT)) & SDHC_IRQSIGEN_CRMIEN_MASK)
AnnaBridge 143:86740a56073b 9018 #define SDHC_IRQSIGEN_CINTIEN_MASK (0x100U)
AnnaBridge 143:86740a56073b 9019 #define SDHC_IRQSIGEN_CINTIEN_SHIFT (8U)
AnnaBridge 143:86740a56073b 9020 #define SDHC_IRQSIGEN_CINTIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CINTIEN_SHIFT)) & SDHC_IRQSIGEN_CINTIEN_MASK)
AnnaBridge 143:86740a56073b 9021 #define SDHC_IRQSIGEN_CTOEIEN_MASK (0x10000U)
AnnaBridge 143:86740a56073b 9022 #define SDHC_IRQSIGEN_CTOEIEN_SHIFT (16U)
AnnaBridge 143:86740a56073b 9023 #define SDHC_IRQSIGEN_CTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CTOEIEN_SHIFT)) & SDHC_IRQSIGEN_CTOEIEN_MASK)
AnnaBridge 143:86740a56073b 9024 #define SDHC_IRQSIGEN_CCEIEN_MASK (0x20000U)
AnnaBridge 143:86740a56073b 9025 #define SDHC_IRQSIGEN_CCEIEN_SHIFT (17U)
AnnaBridge 143:86740a56073b 9026 #define SDHC_IRQSIGEN_CCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CCEIEN_SHIFT)) & SDHC_IRQSIGEN_CCEIEN_MASK)
AnnaBridge 143:86740a56073b 9027 #define SDHC_IRQSIGEN_CEBEIEN_MASK (0x40000U)
AnnaBridge 143:86740a56073b 9028 #define SDHC_IRQSIGEN_CEBEIEN_SHIFT (18U)
AnnaBridge 143:86740a56073b 9029 #define SDHC_IRQSIGEN_CEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CEBEIEN_SHIFT)) & SDHC_IRQSIGEN_CEBEIEN_MASK)
AnnaBridge 143:86740a56073b 9030 #define SDHC_IRQSIGEN_CIEIEN_MASK (0x80000U)
AnnaBridge 143:86740a56073b 9031 #define SDHC_IRQSIGEN_CIEIEN_SHIFT (19U)
AnnaBridge 143:86740a56073b 9032 #define SDHC_IRQSIGEN_CIEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_CIEIEN_SHIFT)) & SDHC_IRQSIGEN_CIEIEN_MASK)
AnnaBridge 143:86740a56073b 9033 #define SDHC_IRQSIGEN_DTOEIEN_MASK (0x100000U)
AnnaBridge 143:86740a56073b 9034 #define SDHC_IRQSIGEN_DTOEIEN_SHIFT (20U)
AnnaBridge 143:86740a56073b 9035 #define SDHC_IRQSIGEN_DTOEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DTOEIEN_SHIFT)) & SDHC_IRQSIGEN_DTOEIEN_MASK)
AnnaBridge 143:86740a56073b 9036 #define SDHC_IRQSIGEN_DCEIEN_MASK (0x200000U)
AnnaBridge 143:86740a56073b 9037 #define SDHC_IRQSIGEN_DCEIEN_SHIFT (21U)
AnnaBridge 143:86740a56073b 9038 #define SDHC_IRQSIGEN_DCEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DCEIEN_SHIFT)) & SDHC_IRQSIGEN_DCEIEN_MASK)
AnnaBridge 143:86740a56073b 9039 #define SDHC_IRQSIGEN_DEBEIEN_MASK (0x400000U)
AnnaBridge 143:86740a56073b 9040 #define SDHC_IRQSIGEN_DEBEIEN_SHIFT (22U)
AnnaBridge 143:86740a56073b 9041 #define SDHC_IRQSIGEN_DEBEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DEBEIEN_SHIFT)) & SDHC_IRQSIGEN_DEBEIEN_MASK)
AnnaBridge 143:86740a56073b 9042 #define SDHC_IRQSIGEN_AC12EIEN_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9043 #define SDHC_IRQSIGEN_AC12EIEN_SHIFT (24U)
AnnaBridge 143:86740a56073b 9044 #define SDHC_IRQSIGEN_AC12EIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_AC12EIEN_SHIFT)) & SDHC_IRQSIGEN_AC12EIEN_MASK)
AnnaBridge 143:86740a56073b 9045 #define SDHC_IRQSIGEN_DMAEIEN_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 9046 #define SDHC_IRQSIGEN_DMAEIEN_SHIFT (28U)
AnnaBridge 143:86740a56073b 9047 #define SDHC_IRQSIGEN_DMAEIEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_IRQSIGEN_DMAEIEN_SHIFT)) & SDHC_IRQSIGEN_DMAEIEN_MASK)
AnnaBridge 143:86740a56073b 9048
AnnaBridge 143:86740a56073b 9049 /*! @name AC12ERR - Auto CMD12 Error Status Register */
AnnaBridge 143:86740a56073b 9050 #define SDHC_AC12ERR_AC12NE_MASK (0x1U)
AnnaBridge 143:86740a56073b 9051 #define SDHC_AC12ERR_AC12NE_SHIFT (0U)
AnnaBridge 143:86740a56073b 9052 #define SDHC_AC12ERR_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12NE_SHIFT)) & SDHC_AC12ERR_AC12NE_MASK)
AnnaBridge 143:86740a56073b 9053 #define SDHC_AC12ERR_AC12TOE_MASK (0x2U)
AnnaBridge 143:86740a56073b 9054 #define SDHC_AC12ERR_AC12TOE_SHIFT (1U)
AnnaBridge 143:86740a56073b 9055 #define SDHC_AC12ERR_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12TOE_SHIFT)) & SDHC_AC12ERR_AC12TOE_MASK)
AnnaBridge 143:86740a56073b 9056 #define SDHC_AC12ERR_AC12EBE_MASK (0x4U)
AnnaBridge 143:86740a56073b 9057 #define SDHC_AC12ERR_AC12EBE_SHIFT (2U)
AnnaBridge 143:86740a56073b 9058 #define SDHC_AC12ERR_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12EBE_SHIFT)) & SDHC_AC12ERR_AC12EBE_MASK)
AnnaBridge 143:86740a56073b 9059 #define SDHC_AC12ERR_AC12CE_MASK (0x8U)
AnnaBridge 143:86740a56073b 9060 #define SDHC_AC12ERR_AC12CE_SHIFT (3U)
AnnaBridge 143:86740a56073b 9061 #define SDHC_AC12ERR_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12CE_SHIFT)) & SDHC_AC12ERR_AC12CE_MASK)
AnnaBridge 143:86740a56073b 9062 #define SDHC_AC12ERR_AC12IE_MASK (0x10U)
AnnaBridge 143:86740a56073b 9063 #define SDHC_AC12ERR_AC12IE_SHIFT (4U)
AnnaBridge 143:86740a56073b 9064 #define SDHC_AC12ERR_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_AC12IE_SHIFT)) & SDHC_AC12ERR_AC12IE_MASK)
AnnaBridge 143:86740a56073b 9065 #define SDHC_AC12ERR_CNIBAC12E_MASK (0x80U)
AnnaBridge 143:86740a56073b 9066 #define SDHC_AC12ERR_CNIBAC12E_SHIFT (7U)
AnnaBridge 143:86740a56073b 9067 #define SDHC_AC12ERR_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_AC12ERR_CNIBAC12E_SHIFT)) & SDHC_AC12ERR_CNIBAC12E_MASK)
AnnaBridge 143:86740a56073b 9068
AnnaBridge 143:86740a56073b 9069 /*! @name HTCAPBLT - Host Controller Capabilities */
AnnaBridge 143:86740a56073b 9070 #define SDHC_HTCAPBLT_MBL_MASK (0x70000U)
AnnaBridge 143:86740a56073b 9071 #define SDHC_HTCAPBLT_MBL_SHIFT (16U)
AnnaBridge 143:86740a56073b 9072 #define SDHC_HTCAPBLT_MBL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_MBL_SHIFT)) & SDHC_HTCAPBLT_MBL_MASK)
AnnaBridge 143:86740a56073b 9073 #define SDHC_HTCAPBLT_ADMAS_MASK (0x100000U)
AnnaBridge 143:86740a56073b 9074 #define SDHC_HTCAPBLT_ADMAS_SHIFT (20U)
AnnaBridge 143:86740a56073b 9075 #define SDHC_HTCAPBLT_ADMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_ADMAS_SHIFT)) & SDHC_HTCAPBLT_ADMAS_MASK)
AnnaBridge 143:86740a56073b 9076 #define SDHC_HTCAPBLT_HSS_MASK (0x200000U)
AnnaBridge 143:86740a56073b 9077 #define SDHC_HTCAPBLT_HSS_SHIFT (21U)
AnnaBridge 143:86740a56073b 9078 #define SDHC_HTCAPBLT_HSS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_HSS_SHIFT)) & SDHC_HTCAPBLT_HSS_MASK)
AnnaBridge 143:86740a56073b 9079 #define SDHC_HTCAPBLT_DMAS_MASK (0x400000U)
AnnaBridge 143:86740a56073b 9080 #define SDHC_HTCAPBLT_DMAS_SHIFT (22U)
AnnaBridge 143:86740a56073b 9081 #define SDHC_HTCAPBLT_DMAS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_DMAS_SHIFT)) & SDHC_HTCAPBLT_DMAS_MASK)
AnnaBridge 143:86740a56073b 9082 #define SDHC_HTCAPBLT_SRS_MASK (0x800000U)
AnnaBridge 143:86740a56073b 9083 #define SDHC_HTCAPBLT_SRS_SHIFT (23U)
AnnaBridge 143:86740a56073b 9084 #define SDHC_HTCAPBLT_SRS(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_SRS_SHIFT)) & SDHC_HTCAPBLT_SRS_MASK)
AnnaBridge 143:86740a56073b 9085 #define SDHC_HTCAPBLT_VS33_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9086 #define SDHC_HTCAPBLT_VS33_SHIFT (24U)
AnnaBridge 143:86740a56073b 9087 #define SDHC_HTCAPBLT_VS33(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HTCAPBLT_VS33_SHIFT)) & SDHC_HTCAPBLT_VS33_MASK)
AnnaBridge 143:86740a56073b 9088
AnnaBridge 143:86740a56073b 9089 /*! @name WML - Watermark Level Register */
AnnaBridge 143:86740a56073b 9090 #define SDHC_WML_RDWML_MASK (0xFFU)
AnnaBridge 143:86740a56073b 9091 #define SDHC_WML_RDWML_SHIFT (0U)
AnnaBridge 143:86740a56073b 9092 #define SDHC_WML_RDWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_RDWML_SHIFT)) & SDHC_WML_RDWML_MASK)
AnnaBridge 143:86740a56073b 9093 #define SDHC_WML_WRWML_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 9094 #define SDHC_WML_WRWML_SHIFT (16U)
AnnaBridge 143:86740a56073b 9095 #define SDHC_WML_WRWML(x) (((uint32_t)(((uint32_t)(x)) << SDHC_WML_WRWML_SHIFT)) & SDHC_WML_WRWML_MASK)
AnnaBridge 143:86740a56073b 9096
AnnaBridge 143:86740a56073b 9097 /*! @name FEVT - Force Event register */
AnnaBridge 143:86740a56073b 9098 #define SDHC_FEVT_AC12NE_MASK (0x1U)
AnnaBridge 143:86740a56073b 9099 #define SDHC_FEVT_AC12NE_SHIFT (0U)
AnnaBridge 143:86740a56073b 9100 #define SDHC_FEVT_AC12NE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12NE_SHIFT)) & SDHC_FEVT_AC12NE_MASK)
AnnaBridge 143:86740a56073b 9101 #define SDHC_FEVT_AC12TOE_MASK (0x2U)
AnnaBridge 143:86740a56073b 9102 #define SDHC_FEVT_AC12TOE_SHIFT (1U)
AnnaBridge 143:86740a56073b 9103 #define SDHC_FEVT_AC12TOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12TOE_SHIFT)) & SDHC_FEVT_AC12TOE_MASK)
AnnaBridge 143:86740a56073b 9104 #define SDHC_FEVT_AC12CE_MASK (0x4U)
AnnaBridge 143:86740a56073b 9105 #define SDHC_FEVT_AC12CE_SHIFT (2U)
AnnaBridge 143:86740a56073b 9106 #define SDHC_FEVT_AC12CE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12CE_SHIFT)) & SDHC_FEVT_AC12CE_MASK)
AnnaBridge 143:86740a56073b 9107 #define SDHC_FEVT_AC12EBE_MASK (0x8U)
AnnaBridge 143:86740a56073b 9108 #define SDHC_FEVT_AC12EBE_SHIFT (3U)
AnnaBridge 143:86740a56073b 9109 #define SDHC_FEVT_AC12EBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12EBE_SHIFT)) & SDHC_FEVT_AC12EBE_MASK)
AnnaBridge 143:86740a56073b 9110 #define SDHC_FEVT_AC12IE_MASK (0x10U)
AnnaBridge 143:86740a56073b 9111 #define SDHC_FEVT_AC12IE_SHIFT (4U)
AnnaBridge 143:86740a56073b 9112 #define SDHC_FEVT_AC12IE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12IE_SHIFT)) & SDHC_FEVT_AC12IE_MASK)
AnnaBridge 143:86740a56073b 9113 #define SDHC_FEVT_CNIBAC12E_MASK (0x80U)
AnnaBridge 143:86740a56073b 9114 #define SDHC_FEVT_CNIBAC12E_SHIFT (7U)
AnnaBridge 143:86740a56073b 9115 #define SDHC_FEVT_CNIBAC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CNIBAC12E_SHIFT)) & SDHC_FEVT_CNIBAC12E_MASK)
AnnaBridge 143:86740a56073b 9116 #define SDHC_FEVT_CTOE_MASK (0x10000U)
AnnaBridge 143:86740a56073b 9117 #define SDHC_FEVT_CTOE_SHIFT (16U)
AnnaBridge 143:86740a56073b 9118 #define SDHC_FEVT_CTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CTOE_SHIFT)) & SDHC_FEVT_CTOE_MASK)
AnnaBridge 143:86740a56073b 9119 #define SDHC_FEVT_CCE_MASK (0x20000U)
AnnaBridge 143:86740a56073b 9120 #define SDHC_FEVT_CCE_SHIFT (17U)
AnnaBridge 143:86740a56073b 9121 #define SDHC_FEVT_CCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CCE_SHIFT)) & SDHC_FEVT_CCE_MASK)
AnnaBridge 143:86740a56073b 9122 #define SDHC_FEVT_CEBE_MASK (0x40000U)
AnnaBridge 143:86740a56073b 9123 #define SDHC_FEVT_CEBE_SHIFT (18U)
AnnaBridge 143:86740a56073b 9124 #define SDHC_FEVT_CEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CEBE_SHIFT)) & SDHC_FEVT_CEBE_MASK)
AnnaBridge 143:86740a56073b 9125 #define SDHC_FEVT_CIE_MASK (0x80000U)
AnnaBridge 143:86740a56073b 9126 #define SDHC_FEVT_CIE_SHIFT (19U)
AnnaBridge 143:86740a56073b 9127 #define SDHC_FEVT_CIE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CIE_SHIFT)) & SDHC_FEVT_CIE_MASK)
AnnaBridge 143:86740a56073b 9128 #define SDHC_FEVT_DTOE_MASK (0x100000U)
AnnaBridge 143:86740a56073b 9129 #define SDHC_FEVT_DTOE_SHIFT (20U)
AnnaBridge 143:86740a56073b 9130 #define SDHC_FEVT_DTOE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DTOE_SHIFT)) & SDHC_FEVT_DTOE_MASK)
AnnaBridge 143:86740a56073b 9131 #define SDHC_FEVT_DCE_MASK (0x200000U)
AnnaBridge 143:86740a56073b 9132 #define SDHC_FEVT_DCE_SHIFT (21U)
AnnaBridge 143:86740a56073b 9133 #define SDHC_FEVT_DCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DCE_SHIFT)) & SDHC_FEVT_DCE_MASK)
AnnaBridge 143:86740a56073b 9134 #define SDHC_FEVT_DEBE_MASK (0x400000U)
AnnaBridge 143:86740a56073b 9135 #define SDHC_FEVT_DEBE_SHIFT (22U)
AnnaBridge 143:86740a56073b 9136 #define SDHC_FEVT_DEBE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DEBE_SHIFT)) & SDHC_FEVT_DEBE_MASK)
AnnaBridge 143:86740a56073b 9137 #define SDHC_FEVT_AC12E_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9138 #define SDHC_FEVT_AC12E_SHIFT (24U)
AnnaBridge 143:86740a56073b 9139 #define SDHC_FEVT_AC12E(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_AC12E_SHIFT)) & SDHC_FEVT_AC12E_MASK)
AnnaBridge 143:86740a56073b 9140 #define SDHC_FEVT_DMAE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 9141 #define SDHC_FEVT_DMAE_SHIFT (28U)
AnnaBridge 143:86740a56073b 9142 #define SDHC_FEVT_DMAE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_DMAE_SHIFT)) & SDHC_FEVT_DMAE_MASK)
AnnaBridge 143:86740a56073b 9143 #define SDHC_FEVT_CINT_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9144 #define SDHC_FEVT_CINT_SHIFT (31U)
AnnaBridge 143:86740a56073b 9145 #define SDHC_FEVT_CINT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_FEVT_CINT_SHIFT)) & SDHC_FEVT_CINT_MASK)
AnnaBridge 143:86740a56073b 9146
AnnaBridge 143:86740a56073b 9147 /*! @name ADMAES - ADMA Error Status register */
AnnaBridge 143:86740a56073b 9148 #define SDHC_ADMAES_ADMAES_MASK (0x3U)
AnnaBridge 143:86740a56073b 9149 #define SDHC_ADMAES_ADMAES_SHIFT (0U)
AnnaBridge 143:86740a56073b 9150 #define SDHC_ADMAES_ADMAES(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMAES_SHIFT)) & SDHC_ADMAES_ADMAES_MASK)
AnnaBridge 143:86740a56073b 9151 #define SDHC_ADMAES_ADMALME_MASK (0x4U)
AnnaBridge 143:86740a56073b 9152 #define SDHC_ADMAES_ADMALME_SHIFT (2U)
AnnaBridge 143:86740a56073b 9153 #define SDHC_ADMAES_ADMALME(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMALME_SHIFT)) & SDHC_ADMAES_ADMALME_MASK)
AnnaBridge 143:86740a56073b 9154 #define SDHC_ADMAES_ADMADCE_MASK (0x8U)
AnnaBridge 143:86740a56073b 9155 #define SDHC_ADMAES_ADMADCE_SHIFT (3U)
AnnaBridge 143:86740a56073b 9156 #define SDHC_ADMAES_ADMADCE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADMAES_ADMADCE_SHIFT)) & SDHC_ADMAES_ADMADCE_MASK)
AnnaBridge 143:86740a56073b 9157
AnnaBridge 143:86740a56073b 9158 /*! @name ADSADDR - ADMA System Addressregister */
AnnaBridge 143:86740a56073b 9159 #define SDHC_ADSADDR_ADSADDR_MASK (0xFFFFFFFCU)
AnnaBridge 143:86740a56073b 9160 #define SDHC_ADSADDR_ADSADDR_SHIFT (2U)
AnnaBridge 143:86740a56073b 9161 #define SDHC_ADSADDR_ADSADDR(x) (((uint32_t)(((uint32_t)(x)) << SDHC_ADSADDR_ADSADDR_SHIFT)) & SDHC_ADSADDR_ADSADDR_MASK)
AnnaBridge 143:86740a56073b 9162
AnnaBridge 143:86740a56073b 9163 /*! @name VENDOR - Vendor Specific register */
AnnaBridge 143:86740a56073b 9164 #define SDHC_VENDOR_EXTDMAEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 9165 #define SDHC_VENDOR_EXTDMAEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 9166 #define SDHC_VENDOR_EXTDMAEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXTDMAEN_SHIFT)) & SDHC_VENDOR_EXTDMAEN_MASK)
AnnaBridge 143:86740a56073b 9167 #define SDHC_VENDOR_EXBLKNU_MASK (0x2U)
AnnaBridge 143:86740a56073b 9168 #define SDHC_VENDOR_EXBLKNU_SHIFT (1U)
AnnaBridge 143:86740a56073b 9169 #define SDHC_VENDOR_EXBLKNU(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_EXBLKNU_SHIFT)) & SDHC_VENDOR_EXBLKNU_MASK)
AnnaBridge 143:86740a56073b 9170 #define SDHC_VENDOR_INTSTVAL_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 9171 #define SDHC_VENDOR_INTSTVAL_SHIFT (16U)
AnnaBridge 143:86740a56073b 9172 #define SDHC_VENDOR_INTSTVAL(x) (((uint32_t)(((uint32_t)(x)) << SDHC_VENDOR_INTSTVAL_SHIFT)) & SDHC_VENDOR_INTSTVAL_MASK)
AnnaBridge 143:86740a56073b 9173
AnnaBridge 143:86740a56073b 9174 /*! @name MMCBOOT - MMC Boot register */
AnnaBridge 143:86740a56073b 9175 #define SDHC_MMCBOOT_DTOCVACK_MASK (0xFU)
AnnaBridge 143:86740a56073b 9176 #define SDHC_MMCBOOT_DTOCVACK_SHIFT (0U)
AnnaBridge 143:86740a56073b 9177 #define SDHC_MMCBOOT_DTOCVACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_DTOCVACK_SHIFT)) & SDHC_MMCBOOT_DTOCVACK_MASK)
AnnaBridge 143:86740a56073b 9178 #define SDHC_MMCBOOT_BOOTACK_MASK (0x10U)
AnnaBridge 143:86740a56073b 9179 #define SDHC_MMCBOOT_BOOTACK_SHIFT (4U)
AnnaBridge 143:86740a56073b 9180 #define SDHC_MMCBOOT_BOOTACK(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTACK_SHIFT)) & SDHC_MMCBOOT_BOOTACK_MASK)
AnnaBridge 143:86740a56073b 9181 #define SDHC_MMCBOOT_BOOTMODE_MASK (0x20U)
AnnaBridge 143:86740a56073b 9182 #define SDHC_MMCBOOT_BOOTMODE_SHIFT (5U)
AnnaBridge 143:86740a56073b 9183 #define SDHC_MMCBOOT_BOOTMODE(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTMODE_SHIFT)) & SDHC_MMCBOOT_BOOTMODE_MASK)
AnnaBridge 143:86740a56073b 9184 #define SDHC_MMCBOOT_BOOTEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 9185 #define SDHC_MMCBOOT_BOOTEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 9186 #define SDHC_MMCBOOT_BOOTEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTEN_SHIFT)) & SDHC_MMCBOOT_BOOTEN_MASK)
AnnaBridge 143:86740a56073b 9187 #define SDHC_MMCBOOT_AUTOSABGEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 9188 #define SDHC_MMCBOOT_AUTOSABGEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 9189 #define SDHC_MMCBOOT_AUTOSABGEN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_AUTOSABGEN_SHIFT)) & SDHC_MMCBOOT_AUTOSABGEN_MASK)
AnnaBridge 143:86740a56073b 9190 #define SDHC_MMCBOOT_BOOTBLKCNT_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 9191 #define SDHC_MMCBOOT_BOOTBLKCNT_SHIFT (16U)
AnnaBridge 143:86740a56073b 9192 #define SDHC_MMCBOOT_BOOTBLKCNT(x) (((uint32_t)(((uint32_t)(x)) << SDHC_MMCBOOT_BOOTBLKCNT_SHIFT)) & SDHC_MMCBOOT_BOOTBLKCNT_MASK)
AnnaBridge 143:86740a56073b 9193
AnnaBridge 143:86740a56073b 9194 /*! @name HOSTVER - Host Controller Version */
AnnaBridge 143:86740a56073b 9195 #define SDHC_HOSTVER_SVN_MASK (0xFFU)
AnnaBridge 143:86740a56073b 9196 #define SDHC_HOSTVER_SVN_SHIFT (0U)
AnnaBridge 143:86740a56073b 9197 #define SDHC_HOSTVER_SVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_SVN_SHIFT)) & SDHC_HOSTVER_SVN_MASK)
AnnaBridge 143:86740a56073b 9198 #define SDHC_HOSTVER_VVN_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 9199 #define SDHC_HOSTVER_VVN_SHIFT (8U)
AnnaBridge 143:86740a56073b 9200 #define SDHC_HOSTVER_VVN(x) (((uint32_t)(((uint32_t)(x)) << SDHC_HOSTVER_VVN_SHIFT)) & SDHC_HOSTVER_VVN_MASK)
AnnaBridge 143:86740a56073b 9201
AnnaBridge 143:86740a56073b 9202
AnnaBridge 143:86740a56073b 9203 /*!
AnnaBridge 143:86740a56073b 9204 * @}
AnnaBridge 143:86740a56073b 9205 */ /* end of group SDHC_Register_Masks */
AnnaBridge 143:86740a56073b 9206
AnnaBridge 143:86740a56073b 9207
AnnaBridge 143:86740a56073b 9208 /* SDHC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 9209 /** Peripheral SDHC base address */
AnnaBridge 143:86740a56073b 9210 #define SDHC_BASE (0x400B1000u)
AnnaBridge 143:86740a56073b 9211 /** Peripheral SDHC base pointer */
AnnaBridge 143:86740a56073b 9212 #define SDHC ((SDHC_Type *)SDHC_BASE)
AnnaBridge 143:86740a56073b 9213 /** Array initializer of SDHC peripheral base addresses */
AnnaBridge 143:86740a56073b 9214 #define SDHC_BASE_ADDRS { SDHC_BASE }
AnnaBridge 143:86740a56073b 9215 /** Array initializer of SDHC peripheral base pointers */
AnnaBridge 143:86740a56073b 9216 #define SDHC_BASE_PTRS { SDHC }
AnnaBridge 143:86740a56073b 9217 /** Interrupt vectors for the SDHC peripheral type */
AnnaBridge 143:86740a56073b 9218 #define SDHC_IRQS { SDHC_IRQn }
AnnaBridge 143:86740a56073b 9219
AnnaBridge 143:86740a56073b 9220 /*!
AnnaBridge 143:86740a56073b 9221 * @}
AnnaBridge 143:86740a56073b 9222 */ /* end of group SDHC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 9223
AnnaBridge 143:86740a56073b 9224
AnnaBridge 143:86740a56073b 9225 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 9226 -- SIM Peripheral Access Layer
AnnaBridge 143:86740a56073b 9227 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 9228
AnnaBridge 143:86740a56073b 9229 /*!
AnnaBridge 143:86740a56073b 9230 * @addtogroup SIM_Peripheral_Access_Layer SIM Peripheral Access Layer
AnnaBridge 143:86740a56073b 9231 * @{
AnnaBridge 143:86740a56073b 9232 */
AnnaBridge 143:86740a56073b 9233
AnnaBridge 143:86740a56073b 9234 /** SIM - Register Layout Typedef */
AnnaBridge 143:86740a56073b 9235 typedef struct {
AnnaBridge 143:86740a56073b 9236 __IO uint32_t SOPT1; /**< System Options Register 1, offset: 0x0 */
AnnaBridge 143:86740a56073b 9237 __IO uint32_t SOPT1CFG; /**< SOPT1 Configuration Register, offset: 0x4 */
AnnaBridge 143:86740a56073b 9238 uint8_t RESERVED_0[4092];
AnnaBridge 143:86740a56073b 9239 __IO uint32_t SOPT2; /**< System Options Register 2, offset: 0x1004 */
AnnaBridge 143:86740a56073b 9240 uint8_t RESERVED_1[4];
AnnaBridge 143:86740a56073b 9241 __IO uint32_t SOPT4; /**< System Options Register 4, offset: 0x100C */
AnnaBridge 143:86740a56073b 9242 __IO uint32_t SOPT5; /**< System Options Register 5, offset: 0x1010 */
AnnaBridge 143:86740a56073b 9243 uint8_t RESERVED_2[4];
AnnaBridge 143:86740a56073b 9244 __IO uint32_t SOPT7; /**< System Options Register 7, offset: 0x1018 */
AnnaBridge 143:86740a56073b 9245 uint8_t RESERVED_3[8];
AnnaBridge 143:86740a56073b 9246 __I uint32_t SDID; /**< System Device Identification Register, offset: 0x1024 */
AnnaBridge 143:86740a56073b 9247 __IO uint32_t SCGC1; /**< System Clock Gating Control Register 1, offset: 0x1028 */
AnnaBridge 143:86740a56073b 9248 __IO uint32_t SCGC2; /**< System Clock Gating Control Register 2, offset: 0x102C */
AnnaBridge 143:86740a56073b 9249 __IO uint32_t SCGC3; /**< System Clock Gating Control Register 3, offset: 0x1030 */
AnnaBridge 143:86740a56073b 9250 __IO uint32_t SCGC4; /**< System Clock Gating Control Register 4, offset: 0x1034 */
AnnaBridge 143:86740a56073b 9251 __IO uint32_t SCGC5; /**< System Clock Gating Control Register 5, offset: 0x1038 */
AnnaBridge 143:86740a56073b 9252 __IO uint32_t SCGC6; /**< System Clock Gating Control Register 6, offset: 0x103C */
AnnaBridge 143:86740a56073b 9253 __IO uint32_t SCGC7; /**< System Clock Gating Control Register 7, offset: 0x1040 */
AnnaBridge 143:86740a56073b 9254 __IO uint32_t CLKDIV1; /**< System Clock Divider Register 1, offset: 0x1044 */
AnnaBridge 143:86740a56073b 9255 __IO uint32_t CLKDIV2; /**< System Clock Divider Register 2, offset: 0x1048 */
AnnaBridge 143:86740a56073b 9256 __IO uint32_t FCFG1; /**< Flash Configuration Register 1, offset: 0x104C */
AnnaBridge 143:86740a56073b 9257 __I uint32_t FCFG2; /**< Flash Configuration Register 2, offset: 0x1050 */
AnnaBridge 143:86740a56073b 9258 __I uint32_t UIDH; /**< Unique Identification Register High, offset: 0x1054 */
AnnaBridge 143:86740a56073b 9259 __I uint32_t UIDMH; /**< Unique Identification Register Mid-High, offset: 0x1058 */
AnnaBridge 143:86740a56073b 9260 __I uint32_t UIDML; /**< Unique Identification Register Mid Low, offset: 0x105C */
AnnaBridge 143:86740a56073b 9261 __I uint32_t UIDL; /**< Unique Identification Register Low, offset: 0x1060 */
AnnaBridge 143:86740a56073b 9262 } SIM_Type;
AnnaBridge 143:86740a56073b 9263
AnnaBridge 143:86740a56073b 9264 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 9265 -- SIM Register Masks
AnnaBridge 143:86740a56073b 9266 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 9267
AnnaBridge 143:86740a56073b 9268 /*!
AnnaBridge 143:86740a56073b 9269 * @addtogroup SIM_Register_Masks SIM Register Masks
AnnaBridge 143:86740a56073b 9270 * @{
AnnaBridge 143:86740a56073b 9271 */
AnnaBridge 143:86740a56073b 9272
AnnaBridge 143:86740a56073b 9273 /*! @name SOPT1 - System Options Register 1 */
AnnaBridge 143:86740a56073b 9274 #define SIM_SOPT1_RAMSIZE_MASK (0xF000U)
AnnaBridge 143:86740a56073b 9275 #define SIM_SOPT1_RAMSIZE_SHIFT (12U)
AnnaBridge 143:86740a56073b 9276 #define SIM_SOPT1_RAMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_RAMSIZE_SHIFT)) & SIM_SOPT1_RAMSIZE_MASK)
AnnaBridge 143:86740a56073b 9277 #define SIM_SOPT1_OSC32KSEL_MASK (0xC0000U)
AnnaBridge 143:86740a56073b 9278 #define SIM_SOPT1_OSC32KSEL_SHIFT (18U)
AnnaBridge 143:86740a56073b 9279 #define SIM_SOPT1_OSC32KSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_OSC32KSEL_SHIFT)) & SIM_SOPT1_OSC32KSEL_MASK)
AnnaBridge 143:86740a56073b 9280 #define SIM_SOPT1_USBVSTBY_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 9281 #define SIM_SOPT1_USBVSTBY_SHIFT (29U)
AnnaBridge 143:86740a56073b 9282 #define SIM_SOPT1_USBVSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBVSTBY_SHIFT)) & SIM_SOPT1_USBVSTBY_MASK)
AnnaBridge 143:86740a56073b 9283 #define SIM_SOPT1_USBSSTBY_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 9284 #define SIM_SOPT1_USBSSTBY_SHIFT (30U)
AnnaBridge 143:86740a56073b 9285 #define SIM_SOPT1_USBSSTBY(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBSSTBY_SHIFT)) & SIM_SOPT1_USBSSTBY_MASK)
AnnaBridge 143:86740a56073b 9286 #define SIM_SOPT1_USBREGEN_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9287 #define SIM_SOPT1_USBREGEN_SHIFT (31U)
AnnaBridge 143:86740a56073b 9288 #define SIM_SOPT1_USBREGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1_USBREGEN_SHIFT)) & SIM_SOPT1_USBREGEN_MASK)
AnnaBridge 143:86740a56073b 9289
AnnaBridge 143:86740a56073b 9290 /*! @name SOPT1CFG - SOPT1 Configuration Register */
AnnaBridge 143:86740a56073b 9291 #define SIM_SOPT1CFG_URWE_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9292 #define SIM_SOPT1CFG_URWE_SHIFT (24U)
AnnaBridge 143:86740a56073b 9293 #define SIM_SOPT1CFG_URWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_URWE_SHIFT)) & SIM_SOPT1CFG_URWE_MASK)
AnnaBridge 143:86740a56073b 9294 #define SIM_SOPT1CFG_UVSWE_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9295 #define SIM_SOPT1CFG_UVSWE_SHIFT (25U)
AnnaBridge 143:86740a56073b 9296 #define SIM_SOPT1CFG_UVSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_UVSWE_SHIFT)) & SIM_SOPT1CFG_UVSWE_MASK)
AnnaBridge 143:86740a56073b 9297 #define SIM_SOPT1CFG_USSWE_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 9298 #define SIM_SOPT1CFG_USSWE_SHIFT (26U)
AnnaBridge 143:86740a56073b 9299 #define SIM_SOPT1CFG_USSWE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT1CFG_USSWE_SHIFT)) & SIM_SOPT1CFG_USSWE_MASK)
AnnaBridge 143:86740a56073b 9300
AnnaBridge 143:86740a56073b 9301 /*! @name SOPT2 - System Options Register 2 */
AnnaBridge 143:86740a56073b 9302 #define SIM_SOPT2_RTCCLKOUTSEL_MASK (0x10U)
AnnaBridge 143:86740a56073b 9303 #define SIM_SOPT2_RTCCLKOUTSEL_SHIFT (4U)
AnnaBridge 143:86740a56073b 9304 #define SIM_SOPT2_RTCCLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_RTCCLKOUTSEL_SHIFT)) & SIM_SOPT2_RTCCLKOUTSEL_MASK)
AnnaBridge 143:86740a56073b 9305 #define SIM_SOPT2_CLKOUTSEL_MASK (0xE0U)
AnnaBridge 143:86740a56073b 9306 #define SIM_SOPT2_CLKOUTSEL_SHIFT (5U)
AnnaBridge 143:86740a56073b 9307 #define SIM_SOPT2_CLKOUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_CLKOUTSEL_SHIFT)) & SIM_SOPT2_CLKOUTSEL_MASK)
AnnaBridge 143:86740a56073b 9308 #define SIM_SOPT2_FBSL_MASK (0x300U)
AnnaBridge 143:86740a56073b 9309 #define SIM_SOPT2_FBSL_SHIFT (8U)
AnnaBridge 143:86740a56073b 9310 #define SIM_SOPT2_FBSL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_FBSL_SHIFT)) & SIM_SOPT2_FBSL_MASK)
AnnaBridge 143:86740a56073b 9311 #define SIM_SOPT2_PTD7PAD_MASK (0x800U)
AnnaBridge 143:86740a56073b 9312 #define SIM_SOPT2_PTD7PAD_SHIFT (11U)
AnnaBridge 143:86740a56073b 9313 #define SIM_SOPT2_PTD7PAD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PTD7PAD_SHIFT)) & SIM_SOPT2_PTD7PAD_MASK)
AnnaBridge 143:86740a56073b 9314 #define SIM_SOPT2_TRACECLKSEL_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9315 #define SIM_SOPT2_TRACECLKSEL_SHIFT (12U)
AnnaBridge 143:86740a56073b 9316 #define SIM_SOPT2_TRACECLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_TRACECLKSEL_SHIFT)) & SIM_SOPT2_TRACECLKSEL_MASK)
AnnaBridge 143:86740a56073b 9317 #define SIM_SOPT2_PLLFLLSEL_MASK (0x30000U)
AnnaBridge 143:86740a56073b 9318 #define SIM_SOPT2_PLLFLLSEL_SHIFT (16U)
AnnaBridge 143:86740a56073b 9319 #define SIM_SOPT2_PLLFLLSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_PLLFLLSEL_SHIFT)) & SIM_SOPT2_PLLFLLSEL_MASK)
AnnaBridge 143:86740a56073b 9320 #define SIM_SOPT2_USBSRC_MASK (0x40000U)
AnnaBridge 143:86740a56073b 9321 #define SIM_SOPT2_USBSRC_SHIFT (18U)
AnnaBridge 143:86740a56073b 9322 #define SIM_SOPT2_USBSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_USBSRC_SHIFT)) & SIM_SOPT2_USBSRC_MASK)
AnnaBridge 143:86740a56073b 9323 #define SIM_SOPT2_SDHCSRC_MASK (0x30000000U)
AnnaBridge 143:86740a56073b 9324 #define SIM_SOPT2_SDHCSRC_SHIFT (28U)
AnnaBridge 143:86740a56073b 9325 #define SIM_SOPT2_SDHCSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT2_SDHCSRC_SHIFT)) & SIM_SOPT2_SDHCSRC_MASK)
AnnaBridge 143:86740a56073b 9326
AnnaBridge 143:86740a56073b 9327 /*! @name SOPT4 - System Options Register 4 */
AnnaBridge 143:86740a56073b 9328 #define SIM_SOPT4_FTM0FLT0_MASK (0x1U)
AnnaBridge 143:86740a56073b 9329 #define SIM_SOPT4_FTM0FLT0_SHIFT (0U)
AnnaBridge 143:86740a56073b 9330 #define SIM_SOPT4_FTM0FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT0_SHIFT)) & SIM_SOPT4_FTM0FLT0_MASK)
AnnaBridge 143:86740a56073b 9331 #define SIM_SOPT4_FTM0FLT1_MASK (0x2U)
AnnaBridge 143:86740a56073b 9332 #define SIM_SOPT4_FTM0FLT1_SHIFT (1U)
AnnaBridge 143:86740a56073b 9333 #define SIM_SOPT4_FTM0FLT1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT1_SHIFT)) & SIM_SOPT4_FTM0FLT1_MASK)
AnnaBridge 143:86740a56073b 9334 #define SIM_SOPT4_FTM0FLT2_MASK (0x4U)
AnnaBridge 143:86740a56073b 9335 #define SIM_SOPT4_FTM0FLT2_SHIFT (2U)
AnnaBridge 143:86740a56073b 9336 #define SIM_SOPT4_FTM0FLT2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0FLT2_SHIFT)) & SIM_SOPT4_FTM0FLT2_MASK)
AnnaBridge 143:86740a56073b 9337 #define SIM_SOPT4_FTM1FLT0_MASK (0x10U)
AnnaBridge 143:86740a56073b 9338 #define SIM_SOPT4_FTM1FLT0_SHIFT (4U)
AnnaBridge 143:86740a56073b 9339 #define SIM_SOPT4_FTM1FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1FLT0_SHIFT)) & SIM_SOPT4_FTM1FLT0_MASK)
AnnaBridge 143:86740a56073b 9340 #define SIM_SOPT4_FTM2FLT0_MASK (0x100U)
AnnaBridge 143:86740a56073b 9341 #define SIM_SOPT4_FTM2FLT0_SHIFT (8U)
AnnaBridge 143:86740a56073b 9342 #define SIM_SOPT4_FTM2FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2FLT0_SHIFT)) & SIM_SOPT4_FTM2FLT0_MASK)
AnnaBridge 143:86740a56073b 9343 #define SIM_SOPT4_FTM3FLT0_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9344 #define SIM_SOPT4_FTM3FLT0_SHIFT (12U)
AnnaBridge 143:86740a56073b 9345 #define SIM_SOPT4_FTM3FLT0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3FLT0_SHIFT)) & SIM_SOPT4_FTM3FLT0_MASK)
AnnaBridge 143:86740a56073b 9346 #define SIM_SOPT4_FTM1CH0SRC_MASK (0xC0000U)
AnnaBridge 143:86740a56073b 9347 #define SIM_SOPT4_FTM1CH0SRC_SHIFT (18U)
AnnaBridge 143:86740a56073b 9348 #define SIM_SOPT4_FTM1CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CH0SRC_SHIFT)) & SIM_SOPT4_FTM1CH0SRC_MASK)
AnnaBridge 143:86740a56073b 9349 #define SIM_SOPT4_FTM2CH0SRC_MASK (0x300000U)
AnnaBridge 143:86740a56073b 9350 #define SIM_SOPT4_FTM2CH0SRC_SHIFT (20U)
AnnaBridge 143:86740a56073b 9351 #define SIM_SOPT4_FTM2CH0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CH0SRC_SHIFT)) & SIM_SOPT4_FTM2CH0SRC_MASK)
AnnaBridge 143:86740a56073b 9352 #define SIM_SOPT4_FTM0CLKSEL_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9353 #define SIM_SOPT4_FTM0CLKSEL_SHIFT (24U)
AnnaBridge 143:86740a56073b 9354 #define SIM_SOPT4_FTM0CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0CLKSEL_SHIFT)) & SIM_SOPT4_FTM0CLKSEL_MASK)
AnnaBridge 143:86740a56073b 9355 #define SIM_SOPT4_FTM1CLKSEL_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9356 #define SIM_SOPT4_FTM1CLKSEL_SHIFT (25U)
AnnaBridge 143:86740a56073b 9357 #define SIM_SOPT4_FTM1CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM1CLKSEL_SHIFT)) & SIM_SOPT4_FTM1CLKSEL_MASK)
AnnaBridge 143:86740a56073b 9358 #define SIM_SOPT4_FTM2CLKSEL_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 9359 #define SIM_SOPT4_FTM2CLKSEL_SHIFT (26U)
AnnaBridge 143:86740a56073b 9360 #define SIM_SOPT4_FTM2CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM2CLKSEL_SHIFT)) & SIM_SOPT4_FTM2CLKSEL_MASK)
AnnaBridge 143:86740a56073b 9361 #define SIM_SOPT4_FTM3CLKSEL_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 9362 #define SIM_SOPT4_FTM3CLKSEL_SHIFT (27U)
AnnaBridge 143:86740a56073b 9363 #define SIM_SOPT4_FTM3CLKSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3CLKSEL_SHIFT)) & SIM_SOPT4_FTM3CLKSEL_MASK)
AnnaBridge 143:86740a56073b 9364 #define SIM_SOPT4_FTM0TRG0SRC_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 9365 #define SIM_SOPT4_FTM0TRG0SRC_SHIFT (28U)
AnnaBridge 143:86740a56073b 9366 #define SIM_SOPT4_FTM0TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG0SRC_SHIFT)) & SIM_SOPT4_FTM0TRG0SRC_MASK)
AnnaBridge 143:86740a56073b 9367 #define SIM_SOPT4_FTM0TRG1SRC_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 9368 #define SIM_SOPT4_FTM0TRG1SRC_SHIFT (29U)
AnnaBridge 143:86740a56073b 9369 #define SIM_SOPT4_FTM0TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM0TRG1SRC_SHIFT)) & SIM_SOPT4_FTM0TRG1SRC_MASK)
AnnaBridge 143:86740a56073b 9370 #define SIM_SOPT4_FTM3TRG0SRC_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 9371 #define SIM_SOPT4_FTM3TRG0SRC_SHIFT (30U)
AnnaBridge 143:86740a56073b 9372 #define SIM_SOPT4_FTM3TRG0SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG0SRC_SHIFT)) & SIM_SOPT4_FTM3TRG0SRC_MASK)
AnnaBridge 143:86740a56073b 9373 #define SIM_SOPT4_FTM3TRG1SRC_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9374 #define SIM_SOPT4_FTM3TRG1SRC_SHIFT (31U)
AnnaBridge 143:86740a56073b 9375 #define SIM_SOPT4_FTM3TRG1SRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT4_FTM3TRG1SRC_SHIFT)) & SIM_SOPT4_FTM3TRG1SRC_MASK)
AnnaBridge 143:86740a56073b 9376
AnnaBridge 143:86740a56073b 9377 /*! @name SOPT5 - System Options Register 5 */
AnnaBridge 143:86740a56073b 9378 #define SIM_SOPT5_UART0TXSRC_MASK (0x3U)
AnnaBridge 143:86740a56073b 9379 #define SIM_SOPT5_UART0TXSRC_SHIFT (0U)
AnnaBridge 143:86740a56073b 9380 #define SIM_SOPT5_UART0TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0TXSRC_SHIFT)) & SIM_SOPT5_UART0TXSRC_MASK)
AnnaBridge 143:86740a56073b 9381 #define SIM_SOPT5_UART0RXSRC_MASK (0xCU)
AnnaBridge 143:86740a56073b 9382 #define SIM_SOPT5_UART0RXSRC_SHIFT (2U)
AnnaBridge 143:86740a56073b 9383 #define SIM_SOPT5_UART0RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART0RXSRC_SHIFT)) & SIM_SOPT5_UART0RXSRC_MASK)
AnnaBridge 143:86740a56073b 9384 #define SIM_SOPT5_UART1TXSRC_MASK (0x30U)
AnnaBridge 143:86740a56073b 9385 #define SIM_SOPT5_UART1TXSRC_SHIFT (4U)
AnnaBridge 143:86740a56073b 9386 #define SIM_SOPT5_UART1TXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1TXSRC_SHIFT)) & SIM_SOPT5_UART1TXSRC_MASK)
AnnaBridge 143:86740a56073b 9387 #define SIM_SOPT5_UART1RXSRC_MASK (0xC0U)
AnnaBridge 143:86740a56073b 9388 #define SIM_SOPT5_UART1RXSRC_SHIFT (6U)
AnnaBridge 143:86740a56073b 9389 #define SIM_SOPT5_UART1RXSRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT5_UART1RXSRC_SHIFT)) & SIM_SOPT5_UART1RXSRC_MASK)
AnnaBridge 143:86740a56073b 9390
AnnaBridge 143:86740a56073b 9391 /*! @name SOPT7 - System Options Register 7 */
AnnaBridge 143:86740a56073b 9392 #define SIM_SOPT7_ADC0TRGSEL_MASK (0xFU)
AnnaBridge 143:86740a56073b 9393 #define SIM_SOPT7_ADC0TRGSEL_SHIFT (0U)
AnnaBridge 143:86740a56073b 9394 #define SIM_SOPT7_ADC0TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0TRGSEL_SHIFT)) & SIM_SOPT7_ADC0TRGSEL_MASK)
AnnaBridge 143:86740a56073b 9395 #define SIM_SOPT7_ADC0PRETRGSEL_MASK (0x10U)
AnnaBridge 143:86740a56073b 9396 #define SIM_SOPT7_ADC0PRETRGSEL_SHIFT (4U)
AnnaBridge 143:86740a56073b 9397 #define SIM_SOPT7_ADC0PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC0PRETRGSEL_MASK)
AnnaBridge 143:86740a56073b 9398 #define SIM_SOPT7_ADC0ALTTRGEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 9399 #define SIM_SOPT7_ADC0ALTTRGEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 9400 #define SIM_SOPT7_ADC0ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC0ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC0ALTTRGEN_MASK)
AnnaBridge 143:86740a56073b 9401 #define SIM_SOPT7_ADC1TRGSEL_MASK (0xF00U)
AnnaBridge 143:86740a56073b 9402 #define SIM_SOPT7_ADC1TRGSEL_SHIFT (8U)
AnnaBridge 143:86740a56073b 9403 #define SIM_SOPT7_ADC1TRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1TRGSEL_SHIFT)) & SIM_SOPT7_ADC1TRGSEL_MASK)
AnnaBridge 143:86740a56073b 9404 #define SIM_SOPT7_ADC1PRETRGSEL_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9405 #define SIM_SOPT7_ADC1PRETRGSEL_SHIFT (12U)
AnnaBridge 143:86740a56073b 9406 #define SIM_SOPT7_ADC1PRETRGSEL(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1PRETRGSEL_SHIFT)) & SIM_SOPT7_ADC1PRETRGSEL_MASK)
AnnaBridge 143:86740a56073b 9407 #define SIM_SOPT7_ADC1ALTTRGEN_MASK (0x8000U)
AnnaBridge 143:86740a56073b 9408 #define SIM_SOPT7_ADC1ALTTRGEN_SHIFT (15U)
AnnaBridge 143:86740a56073b 9409 #define SIM_SOPT7_ADC1ALTTRGEN(x) (((uint32_t)(((uint32_t)(x)) << SIM_SOPT7_ADC1ALTTRGEN_SHIFT)) & SIM_SOPT7_ADC1ALTTRGEN_MASK)
AnnaBridge 143:86740a56073b 9410
AnnaBridge 143:86740a56073b 9411 /*! @name SDID - System Device Identification Register */
AnnaBridge 143:86740a56073b 9412 #define SIM_SDID_PINID_MASK (0xFU)
AnnaBridge 143:86740a56073b 9413 #define SIM_SDID_PINID_SHIFT (0U)
AnnaBridge 143:86740a56073b 9414 #define SIM_SDID_PINID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_PINID_SHIFT)) & SIM_SDID_PINID_MASK)
AnnaBridge 143:86740a56073b 9415 #define SIM_SDID_FAMID_MASK (0x70U)
AnnaBridge 143:86740a56073b 9416 #define SIM_SDID_FAMID_SHIFT (4U)
AnnaBridge 143:86740a56073b 9417 #define SIM_SDID_FAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMID_SHIFT)) & SIM_SDID_FAMID_MASK)
AnnaBridge 143:86740a56073b 9418 #define SIM_SDID_DIEID_MASK (0xF80U)
AnnaBridge 143:86740a56073b 9419 #define SIM_SDID_DIEID_SHIFT (7U)
AnnaBridge 143:86740a56073b 9420 #define SIM_SDID_DIEID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_DIEID_SHIFT)) & SIM_SDID_DIEID_MASK)
AnnaBridge 143:86740a56073b 9421 #define SIM_SDID_REVID_MASK (0xF000U)
AnnaBridge 143:86740a56073b 9422 #define SIM_SDID_REVID_SHIFT (12U)
AnnaBridge 143:86740a56073b 9423 #define SIM_SDID_REVID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_REVID_SHIFT)) & SIM_SDID_REVID_MASK)
AnnaBridge 143:86740a56073b 9424 #define SIM_SDID_SERIESID_MASK (0xF00000U)
AnnaBridge 143:86740a56073b 9425 #define SIM_SDID_SERIESID_SHIFT (20U)
AnnaBridge 143:86740a56073b 9426 #define SIM_SDID_SERIESID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SERIESID_SHIFT)) & SIM_SDID_SERIESID_MASK)
AnnaBridge 143:86740a56073b 9427 #define SIM_SDID_SUBFAMID_MASK (0xF000000U)
AnnaBridge 143:86740a56073b 9428 #define SIM_SDID_SUBFAMID_SHIFT (24U)
AnnaBridge 143:86740a56073b 9429 #define SIM_SDID_SUBFAMID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_SUBFAMID_SHIFT)) & SIM_SDID_SUBFAMID_MASK)
AnnaBridge 143:86740a56073b 9430 #define SIM_SDID_FAMILYID_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 9431 #define SIM_SDID_FAMILYID_SHIFT (28U)
AnnaBridge 143:86740a56073b 9432 #define SIM_SDID_FAMILYID(x) (((uint32_t)(((uint32_t)(x)) << SIM_SDID_FAMILYID_SHIFT)) & SIM_SDID_FAMILYID_MASK)
AnnaBridge 143:86740a56073b 9433
AnnaBridge 143:86740a56073b 9434 /*! @name SCGC1 - System Clock Gating Control Register 1 */
AnnaBridge 143:86740a56073b 9435 #define SIM_SCGC1_I2C2_MASK (0x40U)
AnnaBridge 143:86740a56073b 9436 #define SIM_SCGC1_I2C2_SHIFT (6U)
AnnaBridge 143:86740a56073b 9437 #define SIM_SCGC1_I2C2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_I2C2_SHIFT)) & SIM_SCGC1_I2C2_MASK)
AnnaBridge 143:86740a56073b 9438 #define SIM_SCGC1_UART4_MASK (0x400U)
AnnaBridge 143:86740a56073b 9439 #define SIM_SCGC1_UART4_SHIFT (10U)
AnnaBridge 143:86740a56073b 9440 #define SIM_SCGC1_UART4(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART4_SHIFT)) & SIM_SCGC1_UART4_MASK)
AnnaBridge 143:86740a56073b 9441 #define SIM_SCGC1_UART5_MASK (0x800U)
AnnaBridge 143:86740a56073b 9442 #define SIM_SCGC1_UART5_SHIFT (11U)
AnnaBridge 143:86740a56073b 9443 #define SIM_SCGC1_UART5(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC1_UART5_SHIFT)) & SIM_SCGC1_UART5_MASK)
AnnaBridge 143:86740a56073b 9444
AnnaBridge 143:86740a56073b 9445 /*! @name SCGC2 - System Clock Gating Control Register 2 */
AnnaBridge 143:86740a56073b 9446 #define SIM_SCGC2_DAC0_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9447 #define SIM_SCGC2_DAC0_SHIFT (12U)
AnnaBridge 143:86740a56073b 9448 #define SIM_SCGC2_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC0_SHIFT)) & SIM_SCGC2_DAC0_MASK)
AnnaBridge 143:86740a56073b 9449 #define SIM_SCGC2_DAC1_MASK (0x2000U)
AnnaBridge 143:86740a56073b 9450 #define SIM_SCGC2_DAC1_SHIFT (13U)
AnnaBridge 143:86740a56073b 9451 #define SIM_SCGC2_DAC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC2_DAC1_SHIFT)) & SIM_SCGC2_DAC1_MASK)
AnnaBridge 143:86740a56073b 9452
AnnaBridge 143:86740a56073b 9453 /*! @name SCGC3 - System Clock Gating Control Register 3 */
AnnaBridge 143:86740a56073b 9454 #define SIM_SCGC3_RNGA_MASK (0x1U)
AnnaBridge 143:86740a56073b 9455 #define SIM_SCGC3_RNGA_SHIFT (0U)
AnnaBridge 143:86740a56073b 9456 #define SIM_SCGC3_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_RNGA_SHIFT)) & SIM_SCGC3_RNGA_MASK)
AnnaBridge 143:86740a56073b 9457 #define SIM_SCGC3_SPI2_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9458 #define SIM_SCGC3_SPI2_SHIFT (12U)
AnnaBridge 143:86740a56073b 9459 #define SIM_SCGC3_SPI2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SPI2_SHIFT)) & SIM_SCGC3_SPI2_MASK)
AnnaBridge 143:86740a56073b 9460 #define SIM_SCGC3_SDHC_MASK (0x20000U)
AnnaBridge 143:86740a56073b 9461 #define SIM_SCGC3_SDHC_SHIFT (17U)
AnnaBridge 143:86740a56073b 9462 #define SIM_SCGC3_SDHC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_SDHC_SHIFT)) & SIM_SCGC3_SDHC_MASK)
AnnaBridge 143:86740a56073b 9463 #define SIM_SCGC3_FTM2_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9464 #define SIM_SCGC3_FTM2_SHIFT (24U)
AnnaBridge 143:86740a56073b 9465 #define SIM_SCGC3_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM2_SHIFT)) & SIM_SCGC3_FTM2_MASK)
AnnaBridge 143:86740a56073b 9466 #define SIM_SCGC3_FTM3_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9467 #define SIM_SCGC3_FTM3_SHIFT (25U)
AnnaBridge 143:86740a56073b 9468 #define SIM_SCGC3_FTM3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_FTM3_SHIFT)) & SIM_SCGC3_FTM3_MASK)
AnnaBridge 143:86740a56073b 9469 #define SIM_SCGC3_ADC1_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 9470 #define SIM_SCGC3_ADC1_SHIFT (27U)
AnnaBridge 143:86740a56073b 9471 #define SIM_SCGC3_ADC1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC3_ADC1_SHIFT)) & SIM_SCGC3_ADC1_MASK)
AnnaBridge 143:86740a56073b 9472
AnnaBridge 143:86740a56073b 9473 /*! @name SCGC4 - System Clock Gating Control Register 4 */
AnnaBridge 143:86740a56073b 9474 #define SIM_SCGC4_EWM_MASK (0x2U)
AnnaBridge 143:86740a56073b 9475 #define SIM_SCGC4_EWM_SHIFT (1U)
AnnaBridge 143:86740a56073b 9476 #define SIM_SCGC4_EWM(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_EWM_SHIFT)) & SIM_SCGC4_EWM_MASK)
AnnaBridge 143:86740a56073b 9477 #define SIM_SCGC4_CMT_MASK (0x4U)
AnnaBridge 143:86740a56073b 9478 #define SIM_SCGC4_CMT_SHIFT (2U)
AnnaBridge 143:86740a56073b 9479 #define SIM_SCGC4_CMT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMT_SHIFT)) & SIM_SCGC4_CMT_MASK)
AnnaBridge 143:86740a56073b 9480 #define SIM_SCGC4_I2C0_MASK (0x40U)
AnnaBridge 143:86740a56073b 9481 #define SIM_SCGC4_I2C0_SHIFT (6U)
AnnaBridge 143:86740a56073b 9482 #define SIM_SCGC4_I2C0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C0_SHIFT)) & SIM_SCGC4_I2C0_MASK)
AnnaBridge 143:86740a56073b 9483 #define SIM_SCGC4_I2C1_MASK (0x80U)
AnnaBridge 143:86740a56073b 9484 #define SIM_SCGC4_I2C1_SHIFT (7U)
AnnaBridge 143:86740a56073b 9485 #define SIM_SCGC4_I2C1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_I2C1_SHIFT)) & SIM_SCGC4_I2C1_MASK)
AnnaBridge 143:86740a56073b 9486 #define SIM_SCGC4_UART0_MASK (0x400U)
AnnaBridge 143:86740a56073b 9487 #define SIM_SCGC4_UART0_SHIFT (10U)
AnnaBridge 143:86740a56073b 9488 #define SIM_SCGC4_UART0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART0_SHIFT)) & SIM_SCGC4_UART0_MASK)
AnnaBridge 143:86740a56073b 9489 #define SIM_SCGC4_UART1_MASK (0x800U)
AnnaBridge 143:86740a56073b 9490 #define SIM_SCGC4_UART1_SHIFT (11U)
AnnaBridge 143:86740a56073b 9491 #define SIM_SCGC4_UART1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART1_SHIFT)) & SIM_SCGC4_UART1_MASK)
AnnaBridge 143:86740a56073b 9492 #define SIM_SCGC4_UART2_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9493 #define SIM_SCGC4_UART2_SHIFT (12U)
AnnaBridge 143:86740a56073b 9494 #define SIM_SCGC4_UART2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART2_SHIFT)) & SIM_SCGC4_UART2_MASK)
AnnaBridge 143:86740a56073b 9495 #define SIM_SCGC4_UART3_MASK (0x2000U)
AnnaBridge 143:86740a56073b 9496 #define SIM_SCGC4_UART3_SHIFT (13U)
AnnaBridge 143:86740a56073b 9497 #define SIM_SCGC4_UART3(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_UART3_SHIFT)) & SIM_SCGC4_UART3_MASK)
AnnaBridge 143:86740a56073b 9498 #define SIM_SCGC4_USBOTG_MASK (0x40000U)
AnnaBridge 143:86740a56073b 9499 #define SIM_SCGC4_USBOTG_SHIFT (18U)
AnnaBridge 143:86740a56073b 9500 #define SIM_SCGC4_USBOTG(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_USBOTG_SHIFT)) & SIM_SCGC4_USBOTG_MASK)
AnnaBridge 143:86740a56073b 9501 #define SIM_SCGC4_CMP_MASK (0x80000U)
AnnaBridge 143:86740a56073b 9502 #define SIM_SCGC4_CMP_SHIFT (19U)
AnnaBridge 143:86740a56073b 9503 #define SIM_SCGC4_CMP(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_CMP_SHIFT)) & SIM_SCGC4_CMP_MASK)
AnnaBridge 143:86740a56073b 9504 #define SIM_SCGC4_VREF_MASK (0x100000U)
AnnaBridge 143:86740a56073b 9505 #define SIM_SCGC4_VREF_SHIFT (20U)
AnnaBridge 143:86740a56073b 9506 #define SIM_SCGC4_VREF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC4_VREF_SHIFT)) & SIM_SCGC4_VREF_MASK)
AnnaBridge 143:86740a56073b 9507
AnnaBridge 143:86740a56073b 9508 /*! @name SCGC5 - System Clock Gating Control Register 5 */
AnnaBridge 143:86740a56073b 9509 #define SIM_SCGC5_LPTMR_MASK (0x1U)
AnnaBridge 143:86740a56073b 9510 #define SIM_SCGC5_LPTMR_SHIFT (0U)
AnnaBridge 143:86740a56073b 9511 #define SIM_SCGC5_LPTMR(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_LPTMR_SHIFT)) & SIM_SCGC5_LPTMR_MASK)
AnnaBridge 143:86740a56073b 9512 #define SIM_SCGC5_PORTA_MASK (0x200U)
AnnaBridge 143:86740a56073b 9513 #define SIM_SCGC5_PORTA_SHIFT (9U)
AnnaBridge 143:86740a56073b 9514 #define SIM_SCGC5_PORTA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTA_SHIFT)) & SIM_SCGC5_PORTA_MASK)
AnnaBridge 143:86740a56073b 9515 #define SIM_SCGC5_PORTB_MASK (0x400U)
AnnaBridge 143:86740a56073b 9516 #define SIM_SCGC5_PORTB_SHIFT (10U)
AnnaBridge 143:86740a56073b 9517 #define SIM_SCGC5_PORTB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTB_SHIFT)) & SIM_SCGC5_PORTB_MASK)
AnnaBridge 143:86740a56073b 9518 #define SIM_SCGC5_PORTC_MASK (0x800U)
AnnaBridge 143:86740a56073b 9519 #define SIM_SCGC5_PORTC_SHIFT (11U)
AnnaBridge 143:86740a56073b 9520 #define SIM_SCGC5_PORTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTC_SHIFT)) & SIM_SCGC5_PORTC_MASK)
AnnaBridge 143:86740a56073b 9521 #define SIM_SCGC5_PORTD_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9522 #define SIM_SCGC5_PORTD_SHIFT (12U)
AnnaBridge 143:86740a56073b 9523 #define SIM_SCGC5_PORTD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTD_SHIFT)) & SIM_SCGC5_PORTD_MASK)
AnnaBridge 143:86740a56073b 9524 #define SIM_SCGC5_PORTE_MASK (0x2000U)
AnnaBridge 143:86740a56073b 9525 #define SIM_SCGC5_PORTE_SHIFT (13U)
AnnaBridge 143:86740a56073b 9526 #define SIM_SCGC5_PORTE(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC5_PORTE_SHIFT)) & SIM_SCGC5_PORTE_MASK)
AnnaBridge 143:86740a56073b 9527
AnnaBridge 143:86740a56073b 9528 /*! @name SCGC6 - System Clock Gating Control Register 6 */
AnnaBridge 143:86740a56073b 9529 #define SIM_SCGC6_FTF_MASK (0x1U)
AnnaBridge 143:86740a56073b 9530 #define SIM_SCGC6_FTF_SHIFT (0U)
AnnaBridge 143:86740a56073b 9531 #define SIM_SCGC6_FTF(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTF_SHIFT)) & SIM_SCGC6_FTF_MASK)
AnnaBridge 143:86740a56073b 9532 #define SIM_SCGC6_DMAMUX_MASK (0x2U)
AnnaBridge 143:86740a56073b 9533 #define SIM_SCGC6_DMAMUX_SHIFT (1U)
AnnaBridge 143:86740a56073b 9534 #define SIM_SCGC6_DMAMUX(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DMAMUX_SHIFT)) & SIM_SCGC6_DMAMUX_MASK)
AnnaBridge 143:86740a56073b 9535 #define SIM_SCGC6_FLEXCAN0_MASK (0x10U)
AnnaBridge 143:86740a56073b 9536 #define SIM_SCGC6_FLEXCAN0_SHIFT (4U)
AnnaBridge 143:86740a56073b 9537 #define SIM_SCGC6_FLEXCAN0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FLEXCAN0_SHIFT)) & SIM_SCGC6_FLEXCAN0_MASK)
AnnaBridge 143:86740a56073b 9538 #define SIM_SCGC6_RNGA_MASK (0x200U)
AnnaBridge 143:86740a56073b 9539 #define SIM_SCGC6_RNGA_SHIFT (9U)
AnnaBridge 143:86740a56073b 9540 #define SIM_SCGC6_RNGA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RNGA_SHIFT)) & SIM_SCGC6_RNGA_MASK)
AnnaBridge 143:86740a56073b 9541 #define SIM_SCGC6_SPI0_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9542 #define SIM_SCGC6_SPI0_SHIFT (12U)
AnnaBridge 143:86740a56073b 9543 #define SIM_SCGC6_SPI0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI0_SHIFT)) & SIM_SCGC6_SPI0_MASK)
AnnaBridge 143:86740a56073b 9544 #define SIM_SCGC6_SPI1_MASK (0x2000U)
AnnaBridge 143:86740a56073b 9545 #define SIM_SCGC6_SPI1_SHIFT (13U)
AnnaBridge 143:86740a56073b 9546 #define SIM_SCGC6_SPI1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_SPI1_SHIFT)) & SIM_SCGC6_SPI1_MASK)
AnnaBridge 143:86740a56073b 9547 #define SIM_SCGC6_I2S_MASK (0x8000U)
AnnaBridge 143:86740a56073b 9548 #define SIM_SCGC6_I2S_SHIFT (15U)
AnnaBridge 143:86740a56073b 9549 #define SIM_SCGC6_I2S(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_I2S_SHIFT)) & SIM_SCGC6_I2S_MASK)
AnnaBridge 143:86740a56073b 9550 #define SIM_SCGC6_CRC_MASK (0x40000U)
AnnaBridge 143:86740a56073b 9551 #define SIM_SCGC6_CRC_SHIFT (18U)
AnnaBridge 143:86740a56073b 9552 #define SIM_SCGC6_CRC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_CRC_SHIFT)) & SIM_SCGC6_CRC_MASK)
AnnaBridge 143:86740a56073b 9553 #define SIM_SCGC6_USBDCD_MASK (0x200000U)
AnnaBridge 143:86740a56073b 9554 #define SIM_SCGC6_USBDCD_SHIFT (21U)
AnnaBridge 143:86740a56073b 9555 #define SIM_SCGC6_USBDCD(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_USBDCD_SHIFT)) & SIM_SCGC6_USBDCD_MASK)
AnnaBridge 143:86740a56073b 9556 #define SIM_SCGC6_PDB_MASK (0x400000U)
AnnaBridge 143:86740a56073b 9557 #define SIM_SCGC6_PDB_SHIFT (22U)
AnnaBridge 143:86740a56073b 9558 #define SIM_SCGC6_PDB(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PDB_SHIFT)) & SIM_SCGC6_PDB_MASK)
AnnaBridge 143:86740a56073b 9559 #define SIM_SCGC6_PIT_MASK (0x800000U)
AnnaBridge 143:86740a56073b 9560 #define SIM_SCGC6_PIT_SHIFT (23U)
AnnaBridge 143:86740a56073b 9561 #define SIM_SCGC6_PIT(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_PIT_SHIFT)) & SIM_SCGC6_PIT_MASK)
AnnaBridge 143:86740a56073b 9562 #define SIM_SCGC6_FTM0_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9563 #define SIM_SCGC6_FTM0_SHIFT (24U)
AnnaBridge 143:86740a56073b 9564 #define SIM_SCGC6_FTM0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM0_SHIFT)) & SIM_SCGC6_FTM0_MASK)
AnnaBridge 143:86740a56073b 9565 #define SIM_SCGC6_FTM1_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9566 #define SIM_SCGC6_FTM1_SHIFT (25U)
AnnaBridge 143:86740a56073b 9567 #define SIM_SCGC6_FTM1(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM1_SHIFT)) & SIM_SCGC6_FTM1_MASK)
AnnaBridge 143:86740a56073b 9568 #define SIM_SCGC6_FTM2_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 9569 #define SIM_SCGC6_FTM2_SHIFT (26U)
AnnaBridge 143:86740a56073b 9570 #define SIM_SCGC6_FTM2(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_FTM2_SHIFT)) & SIM_SCGC6_FTM2_MASK)
AnnaBridge 143:86740a56073b 9571 #define SIM_SCGC6_ADC0_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 9572 #define SIM_SCGC6_ADC0_SHIFT (27U)
AnnaBridge 143:86740a56073b 9573 #define SIM_SCGC6_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_ADC0_SHIFT)) & SIM_SCGC6_ADC0_MASK)
AnnaBridge 143:86740a56073b 9574 #define SIM_SCGC6_RTC_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 9575 #define SIM_SCGC6_RTC_SHIFT (29U)
AnnaBridge 143:86740a56073b 9576 #define SIM_SCGC6_RTC(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_RTC_SHIFT)) & SIM_SCGC6_RTC_MASK)
AnnaBridge 143:86740a56073b 9577 #define SIM_SCGC6_DAC0_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9578 #define SIM_SCGC6_DAC0_SHIFT (31U)
AnnaBridge 143:86740a56073b 9579 #define SIM_SCGC6_DAC0(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC6_DAC0_SHIFT)) & SIM_SCGC6_DAC0_MASK)
AnnaBridge 143:86740a56073b 9580
AnnaBridge 143:86740a56073b 9581 /*! @name SCGC7 - System Clock Gating Control Register 7 */
AnnaBridge 143:86740a56073b 9582 #define SIM_SCGC7_FLEXBUS_MASK (0x1U)
AnnaBridge 143:86740a56073b 9583 #define SIM_SCGC7_FLEXBUS_SHIFT (0U)
AnnaBridge 143:86740a56073b 9584 #define SIM_SCGC7_FLEXBUS(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_FLEXBUS_SHIFT)) & SIM_SCGC7_FLEXBUS_MASK)
AnnaBridge 143:86740a56073b 9585 #define SIM_SCGC7_DMA_MASK (0x2U)
AnnaBridge 143:86740a56073b 9586 #define SIM_SCGC7_DMA_SHIFT (1U)
AnnaBridge 143:86740a56073b 9587 #define SIM_SCGC7_DMA(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_DMA_SHIFT)) & SIM_SCGC7_DMA_MASK)
AnnaBridge 143:86740a56073b 9588 #define SIM_SCGC7_MPU_MASK (0x4U)
AnnaBridge 143:86740a56073b 9589 #define SIM_SCGC7_MPU_SHIFT (2U)
AnnaBridge 143:86740a56073b 9590 #define SIM_SCGC7_MPU(x) (((uint32_t)(((uint32_t)(x)) << SIM_SCGC7_MPU_SHIFT)) & SIM_SCGC7_MPU_MASK)
AnnaBridge 143:86740a56073b 9591
AnnaBridge 143:86740a56073b 9592 /*! @name CLKDIV1 - System Clock Divider Register 1 */
AnnaBridge 143:86740a56073b 9593 #define SIM_CLKDIV1_OUTDIV4_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 9594 #define SIM_CLKDIV1_OUTDIV4_SHIFT (16U)
AnnaBridge 143:86740a56073b 9595 #define SIM_CLKDIV1_OUTDIV4(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV4_SHIFT)) & SIM_CLKDIV1_OUTDIV4_MASK)
AnnaBridge 143:86740a56073b 9596 #define SIM_CLKDIV1_OUTDIV3_MASK (0xF00000U)
AnnaBridge 143:86740a56073b 9597 #define SIM_CLKDIV1_OUTDIV3_SHIFT (20U)
AnnaBridge 143:86740a56073b 9598 #define SIM_CLKDIV1_OUTDIV3(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV3_SHIFT)) & SIM_CLKDIV1_OUTDIV3_MASK)
AnnaBridge 143:86740a56073b 9599 #define SIM_CLKDIV1_OUTDIV2_MASK (0xF000000U)
AnnaBridge 143:86740a56073b 9600 #define SIM_CLKDIV1_OUTDIV2_SHIFT (24U)
AnnaBridge 143:86740a56073b 9601 #define SIM_CLKDIV1_OUTDIV2(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV2_SHIFT)) & SIM_CLKDIV1_OUTDIV2_MASK)
AnnaBridge 143:86740a56073b 9602 #define SIM_CLKDIV1_OUTDIV1_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 9603 #define SIM_CLKDIV1_OUTDIV1_SHIFT (28U)
AnnaBridge 143:86740a56073b 9604 #define SIM_CLKDIV1_OUTDIV1(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV1_OUTDIV1_SHIFT)) & SIM_CLKDIV1_OUTDIV1_MASK)
AnnaBridge 143:86740a56073b 9605
AnnaBridge 143:86740a56073b 9606 /*! @name CLKDIV2 - System Clock Divider Register 2 */
AnnaBridge 143:86740a56073b 9607 #define SIM_CLKDIV2_USBFRAC_MASK (0x1U)
AnnaBridge 143:86740a56073b 9608 #define SIM_CLKDIV2_USBFRAC_SHIFT (0U)
AnnaBridge 143:86740a56073b 9609 #define SIM_CLKDIV2_USBFRAC(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBFRAC_SHIFT)) & SIM_CLKDIV2_USBFRAC_MASK)
AnnaBridge 143:86740a56073b 9610 #define SIM_CLKDIV2_USBDIV_MASK (0xEU)
AnnaBridge 143:86740a56073b 9611 #define SIM_CLKDIV2_USBDIV_SHIFT (1U)
AnnaBridge 143:86740a56073b 9612 #define SIM_CLKDIV2_USBDIV(x) (((uint32_t)(((uint32_t)(x)) << SIM_CLKDIV2_USBDIV_SHIFT)) & SIM_CLKDIV2_USBDIV_MASK)
AnnaBridge 143:86740a56073b 9613
AnnaBridge 143:86740a56073b 9614 /*! @name FCFG1 - Flash Configuration Register 1 */
AnnaBridge 143:86740a56073b 9615 #define SIM_FCFG1_FLASHDIS_MASK (0x1U)
AnnaBridge 143:86740a56073b 9616 #define SIM_FCFG1_FLASHDIS_SHIFT (0U)
AnnaBridge 143:86740a56073b 9617 #define SIM_FCFG1_FLASHDIS(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDIS_SHIFT)) & SIM_FCFG1_FLASHDIS_MASK)
AnnaBridge 143:86740a56073b 9618 #define SIM_FCFG1_FLASHDOZE_MASK (0x2U)
AnnaBridge 143:86740a56073b 9619 #define SIM_FCFG1_FLASHDOZE_SHIFT (1U)
AnnaBridge 143:86740a56073b 9620 #define SIM_FCFG1_FLASHDOZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_FLASHDOZE_SHIFT)) & SIM_FCFG1_FLASHDOZE_MASK)
AnnaBridge 143:86740a56073b 9621 #define SIM_FCFG1_DEPART_MASK (0xF00U)
AnnaBridge 143:86740a56073b 9622 #define SIM_FCFG1_DEPART_SHIFT (8U)
AnnaBridge 143:86740a56073b 9623 #define SIM_FCFG1_DEPART(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_DEPART_SHIFT)) & SIM_FCFG1_DEPART_MASK)
AnnaBridge 143:86740a56073b 9624 #define SIM_FCFG1_EESIZE_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 9625 #define SIM_FCFG1_EESIZE_SHIFT (16U)
AnnaBridge 143:86740a56073b 9626 #define SIM_FCFG1_EESIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_EESIZE_SHIFT)) & SIM_FCFG1_EESIZE_MASK)
AnnaBridge 143:86740a56073b 9627 #define SIM_FCFG1_PFSIZE_MASK (0xF000000U)
AnnaBridge 143:86740a56073b 9628 #define SIM_FCFG1_PFSIZE_SHIFT (24U)
AnnaBridge 143:86740a56073b 9629 #define SIM_FCFG1_PFSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_PFSIZE_SHIFT)) & SIM_FCFG1_PFSIZE_MASK)
AnnaBridge 143:86740a56073b 9630 #define SIM_FCFG1_NVMSIZE_MASK (0xF0000000U)
AnnaBridge 143:86740a56073b 9631 #define SIM_FCFG1_NVMSIZE_SHIFT (28U)
AnnaBridge 143:86740a56073b 9632 #define SIM_FCFG1_NVMSIZE(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG1_NVMSIZE_SHIFT)) & SIM_FCFG1_NVMSIZE_MASK)
AnnaBridge 143:86740a56073b 9633
AnnaBridge 143:86740a56073b 9634 /*! @name FCFG2 - Flash Configuration Register 2 */
AnnaBridge 143:86740a56073b 9635 #define SIM_FCFG2_MAXADDR1_MASK (0x7F0000U)
AnnaBridge 143:86740a56073b 9636 #define SIM_FCFG2_MAXADDR1_SHIFT (16U)
AnnaBridge 143:86740a56073b 9637 #define SIM_FCFG2_MAXADDR1(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR1_SHIFT)) & SIM_FCFG2_MAXADDR1_MASK)
AnnaBridge 143:86740a56073b 9638 #define SIM_FCFG2_PFLSH_MASK (0x800000U)
AnnaBridge 143:86740a56073b 9639 #define SIM_FCFG2_PFLSH_SHIFT (23U)
AnnaBridge 143:86740a56073b 9640 #define SIM_FCFG2_PFLSH(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_PFLSH_SHIFT)) & SIM_FCFG2_PFLSH_MASK)
AnnaBridge 143:86740a56073b 9641 #define SIM_FCFG2_MAXADDR0_MASK (0x7F000000U)
AnnaBridge 143:86740a56073b 9642 #define SIM_FCFG2_MAXADDR0_SHIFT (24U)
AnnaBridge 143:86740a56073b 9643 #define SIM_FCFG2_MAXADDR0(x) (((uint32_t)(((uint32_t)(x)) << SIM_FCFG2_MAXADDR0_SHIFT)) & SIM_FCFG2_MAXADDR0_MASK)
AnnaBridge 143:86740a56073b 9644
AnnaBridge 143:86740a56073b 9645 /*! @name UIDH - Unique Identification Register High */
AnnaBridge 143:86740a56073b 9646 #define SIM_UIDH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 9647 #define SIM_UIDH_UID_SHIFT (0U)
AnnaBridge 143:86740a56073b 9648 #define SIM_UIDH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDH_UID_SHIFT)) & SIM_UIDH_UID_MASK)
AnnaBridge 143:86740a56073b 9649
AnnaBridge 143:86740a56073b 9650 /*! @name UIDMH - Unique Identification Register Mid-High */
AnnaBridge 143:86740a56073b 9651 #define SIM_UIDMH_UID_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 9652 #define SIM_UIDMH_UID_SHIFT (0U)
AnnaBridge 143:86740a56073b 9653 #define SIM_UIDMH_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDMH_UID_SHIFT)) & SIM_UIDMH_UID_MASK)
AnnaBridge 143:86740a56073b 9654
AnnaBridge 143:86740a56073b 9655 /*! @name UIDML - Unique Identification Register Mid Low */
AnnaBridge 143:86740a56073b 9656 #define SIM_UIDML_UID_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 9657 #define SIM_UIDML_UID_SHIFT (0U)
AnnaBridge 143:86740a56073b 9658 #define SIM_UIDML_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDML_UID_SHIFT)) & SIM_UIDML_UID_MASK)
AnnaBridge 143:86740a56073b 9659
AnnaBridge 143:86740a56073b 9660 /*! @name UIDL - Unique Identification Register Low */
AnnaBridge 143:86740a56073b 9661 #define SIM_UIDL_UID_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 9662 #define SIM_UIDL_UID_SHIFT (0U)
AnnaBridge 143:86740a56073b 9663 #define SIM_UIDL_UID(x) (((uint32_t)(((uint32_t)(x)) << SIM_UIDL_UID_SHIFT)) & SIM_UIDL_UID_MASK)
AnnaBridge 143:86740a56073b 9664
AnnaBridge 143:86740a56073b 9665
AnnaBridge 143:86740a56073b 9666 /*!
AnnaBridge 143:86740a56073b 9667 * @}
AnnaBridge 143:86740a56073b 9668 */ /* end of group SIM_Register_Masks */
AnnaBridge 143:86740a56073b 9669
AnnaBridge 143:86740a56073b 9670
AnnaBridge 143:86740a56073b 9671 /* SIM - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 9672 /** Peripheral SIM base address */
AnnaBridge 143:86740a56073b 9673 #define SIM_BASE (0x40047000u)
AnnaBridge 143:86740a56073b 9674 /** Peripheral SIM base pointer */
AnnaBridge 143:86740a56073b 9675 #define SIM ((SIM_Type *)SIM_BASE)
AnnaBridge 143:86740a56073b 9676 /** Array initializer of SIM peripheral base addresses */
AnnaBridge 143:86740a56073b 9677 #define SIM_BASE_ADDRS { SIM_BASE }
AnnaBridge 143:86740a56073b 9678 /** Array initializer of SIM peripheral base pointers */
AnnaBridge 143:86740a56073b 9679 #define SIM_BASE_PTRS { SIM }
AnnaBridge 143:86740a56073b 9680
AnnaBridge 143:86740a56073b 9681 /*!
AnnaBridge 143:86740a56073b 9682 * @}
AnnaBridge 143:86740a56073b 9683 */ /* end of group SIM_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 9684
AnnaBridge 143:86740a56073b 9685
AnnaBridge 143:86740a56073b 9686 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 9687 -- SMC Peripheral Access Layer
AnnaBridge 143:86740a56073b 9688 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 9689
AnnaBridge 143:86740a56073b 9690 /*!
AnnaBridge 143:86740a56073b 9691 * @addtogroup SMC_Peripheral_Access_Layer SMC Peripheral Access Layer
AnnaBridge 143:86740a56073b 9692 * @{
AnnaBridge 143:86740a56073b 9693 */
AnnaBridge 143:86740a56073b 9694
AnnaBridge 143:86740a56073b 9695 /** SMC - Register Layout Typedef */
AnnaBridge 143:86740a56073b 9696 typedef struct {
AnnaBridge 143:86740a56073b 9697 __IO uint8_t PMPROT; /**< Power Mode Protection register, offset: 0x0 */
AnnaBridge 143:86740a56073b 9698 __IO uint8_t PMCTRL; /**< Power Mode Control register, offset: 0x1 */
AnnaBridge 143:86740a56073b 9699 __IO uint8_t VLLSCTRL; /**< VLLS Control register, offset: 0x2 */
AnnaBridge 143:86740a56073b 9700 __I uint8_t PMSTAT; /**< Power Mode Status register, offset: 0x3 */
AnnaBridge 143:86740a56073b 9701 } SMC_Type;
AnnaBridge 143:86740a56073b 9702
AnnaBridge 143:86740a56073b 9703 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 9704 -- SMC Register Masks
AnnaBridge 143:86740a56073b 9705 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 9706
AnnaBridge 143:86740a56073b 9707 /*!
AnnaBridge 143:86740a56073b 9708 * @addtogroup SMC_Register_Masks SMC Register Masks
AnnaBridge 143:86740a56073b 9709 * @{
AnnaBridge 143:86740a56073b 9710 */
AnnaBridge 143:86740a56073b 9711
AnnaBridge 143:86740a56073b 9712 /*! @name PMPROT - Power Mode Protection register */
AnnaBridge 143:86740a56073b 9713 #define SMC_PMPROT_AVLLS_MASK (0x2U)
AnnaBridge 143:86740a56073b 9714 #define SMC_PMPROT_AVLLS_SHIFT (1U)
AnnaBridge 143:86740a56073b 9715 #define SMC_PMPROT_AVLLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLLS_SHIFT)) & SMC_PMPROT_AVLLS_MASK)
AnnaBridge 143:86740a56073b 9716 #define SMC_PMPROT_ALLS_MASK (0x8U)
AnnaBridge 143:86740a56073b 9717 #define SMC_PMPROT_ALLS_SHIFT (3U)
AnnaBridge 143:86740a56073b 9718 #define SMC_PMPROT_ALLS(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_ALLS_SHIFT)) & SMC_PMPROT_ALLS_MASK)
AnnaBridge 143:86740a56073b 9719 #define SMC_PMPROT_AVLP_MASK (0x20U)
AnnaBridge 143:86740a56073b 9720 #define SMC_PMPROT_AVLP_SHIFT (5U)
AnnaBridge 143:86740a56073b 9721 #define SMC_PMPROT_AVLP(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMPROT_AVLP_SHIFT)) & SMC_PMPROT_AVLP_MASK)
AnnaBridge 143:86740a56073b 9722
AnnaBridge 143:86740a56073b 9723 /*! @name PMCTRL - Power Mode Control register */
AnnaBridge 143:86740a56073b 9724 #define SMC_PMCTRL_STOPM_MASK (0x7U)
AnnaBridge 143:86740a56073b 9725 #define SMC_PMCTRL_STOPM_SHIFT (0U)
AnnaBridge 143:86740a56073b 9726 #define SMC_PMCTRL_STOPM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPM_SHIFT)) & SMC_PMCTRL_STOPM_MASK)
AnnaBridge 143:86740a56073b 9727 #define SMC_PMCTRL_STOPA_MASK (0x8U)
AnnaBridge 143:86740a56073b 9728 #define SMC_PMCTRL_STOPA_SHIFT (3U)
AnnaBridge 143:86740a56073b 9729 #define SMC_PMCTRL_STOPA(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_STOPA_SHIFT)) & SMC_PMCTRL_STOPA_MASK)
AnnaBridge 143:86740a56073b 9730 #define SMC_PMCTRL_RUNM_MASK (0x60U)
AnnaBridge 143:86740a56073b 9731 #define SMC_PMCTRL_RUNM_SHIFT (5U)
AnnaBridge 143:86740a56073b 9732 #define SMC_PMCTRL_RUNM(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_RUNM_SHIFT)) & SMC_PMCTRL_RUNM_MASK)
AnnaBridge 143:86740a56073b 9733 #define SMC_PMCTRL_LPWUI_MASK (0x80U)
AnnaBridge 143:86740a56073b 9734 #define SMC_PMCTRL_LPWUI_SHIFT (7U)
AnnaBridge 143:86740a56073b 9735 #define SMC_PMCTRL_LPWUI(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMCTRL_LPWUI_SHIFT)) & SMC_PMCTRL_LPWUI_MASK)
AnnaBridge 143:86740a56073b 9736
AnnaBridge 143:86740a56073b 9737 /*! @name VLLSCTRL - VLLS Control register */
AnnaBridge 143:86740a56073b 9738 #define SMC_VLLSCTRL_VLLSM_MASK (0x7U)
AnnaBridge 143:86740a56073b 9739 #define SMC_VLLSCTRL_VLLSM_SHIFT (0U)
AnnaBridge 143:86740a56073b 9740 #define SMC_VLLSCTRL_VLLSM(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_VLLSM_SHIFT)) & SMC_VLLSCTRL_VLLSM_MASK)
AnnaBridge 143:86740a56073b 9741 #define SMC_VLLSCTRL_PORPO_MASK (0x20U)
AnnaBridge 143:86740a56073b 9742 #define SMC_VLLSCTRL_PORPO_SHIFT (5U)
AnnaBridge 143:86740a56073b 9743 #define SMC_VLLSCTRL_PORPO(x) (((uint8_t)(((uint8_t)(x)) << SMC_VLLSCTRL_PORPO_SHIFT)) & SMC_VLLSCTRL_PORPO_MASK)
AnnaBridge 143:86740a56073b 9744
AnnaBridge 143:86740a56073b 9745 /*! @name PMSTAT - Power Mode Status register */
AnnaBridge 143:86740a56073b 9746 #define SMC_PMSTAT_PMSTAT_MASK (0x7FU)
AnnaBridge 143:86740a56073b 9747 #define SMC_PMSTAT_PMSTAT_SHIFT (0U)
AnnaBridge 143:86740a56073b 9748 #define SMC_PMSTAT_PMSTAT(x) (((uint8_t)(((uint8_t)(x)) << SMC_PMSTAT_PMSTAT_SHIFT)) & SMC_PMSTAT_PMSTAT_MASK)
AnnaBridge 143:86740a56073b 9749
AnnaBridge 143:86740a56073b 9750
AnnaBridge 143:86740a56073b 9751 /*!
AnnaBridge 143:86740a56073b 9752 * @}
AnnaBridge 143:86740a56073b 9753 */ /* end of group SMC_Register_Masks */
AnnaBridge 143:86740a56073b 9754
AnnaBridge 143:86740a56073b 9755
AnnaBridge 143:86740a56073b 9756 /* SMC - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 9757 /** Peripheral SMC base address */
AnnaBridge 143:86740a56073b 9758 #define SMC_BASE (0x4007E000u)
AnnaBridge 143:86740a56073b 9759 /** Peripheral SMC base pointer */
AnnaBridge 143:86740a56073b 9760 #define SMC ((SMC_Type *)SMC_BASE)
AnnaBridge 143:86740a56073b 9761 /** Array initializer of SMC peripheral base addresses */
AnnaBridge 143:86740a56073b 9762 #define SMC_BASE_ADDRS { SMC_BASE }
AnnaBridge 143:86740a56073b 9763 /** Array initializer of SMC peripheral base pointers */
AnnaBridge 143:86740a56073b 9764 #define SMC_BASE_PTRS { SMC }
AnnaBridge 143:86740a56073b 9765
AnnaBridge 143:86740a56073b 9766 /*!
AnnaBridge 143:86740a56073b 9767 * @}
AnnaBridge 143:86740a56073b 9768 */ /* end of group SMC_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 9769
AnnaBridge 143:86740a56073b 9770
AnnaBridge 143:86740a56073b 9771 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 9772 -- SPI Peripheral Access Layer
AnnaBridge 143:86740a56073b 9773 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 9774
AnnaBridge 143:86740a56073b 9775 /*!
AnnaBridge 143:86740a56073b 9776 * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
AnnaBridge 143:86740a56073b 9777 * @{
AnnaBridge 143:86740a56073b 9778 */
AnnaBridge 143:86740a56073b 9779
AnnaBridge 143:86740a56073b 9780 /** SPI - Register Layout Typedef */
AnnaBridge 143:86740a56073b 9781 typedef struct {
AnnaBridge 143:86740a56073b 9782 __IO uint32_t MCR; /**< Module Configuration Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 9783 uint8_t RESERVED_0[4];
AnnaBridge 143:86740a56073b 9784 __IO uint32_t TCR; /**< Transfer Count Register, offset: 0x8 */
AnnaBridge 143:86740a56073b 9785 union { /* offset: 0xC */
AnnaBridge 143:86740a56073b 9786 __IO uint32_t CTAR[2]; /**< Clock and Transfer Attributes Register (In Master Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 143:86740a56073b 9787 __IO uint32_t CTAR_SLAVE[1]; /**< Clock and Transfer Attributes Register (In Slave Mode), array offset: 0xC, array step: 0x4 */
AnnaBridge 143:86740a56073b 9788 };
AnnaBridge 143:86740a56073b 9789 uint8_t RESERVED_1[24];
AnnaBridge 143:86740a56073b 9790 __IO uint32_t SR; /**< Status Register, offset: 0x2C */
AnnaBridge 143:86740a56073b 9791 __IO uint32_t RSER; /**< DMA/Interrupt Request Select and Enable Register, offset: 0x30 */
AnnaBridge 143:86740a56073b 9792 union { /* offset: 0x34 */
AnnaBridge 143:86740a56073b 9793 __IO uint32_t PUSHR; /**< PUSH TX FIFO Register In Master Mode, offset: 0x34 */
AnnaBridge 143:86740a56073b 9794 __IO uint32_t PUSHR_SLAVE; /**< PUSH TX FIFO Register In Slave Mode, offset: 0x34 */
AnnaBridge 143:86740a56073b 9795 };
AnnaBridge 143:86740a56073b 9796 __I uint32_t POPR; /**< POP RX FIFO Register, offset: 0x38 */
AnnaBridge 143:86740a56073b 9797 __I uint32_t TXFR0; /**< Transmit FIFO Registers, offset: 0x3C */
AnnaBridge 143:86740a56073b 9798 __I uint32_t TXFR1; /**< Transmit FIFO Registers, offset: 0x40 */
AnnaBridge 143:86740a56073b 9799 __I uint32_t TXFR2; /**< Transmit FIFO Registers, offset: 0x44 */
AnnaBridge 143:86740a56073b 9800 __I uint32_t TXFR3; /**< Transmit FIFO Registers, offset: 0x48 */
AnnaBridge 143:86740a56073b 9801 uint8_t RESERVED_2[48];
AnnaBridge 143:86740a56073b 9802 __I uint32_t RXFR0; /**< Receive FIFO Registers, offset: 0x7C */
AnnaBridge 143:86740a56073b 9803 __I uint32_t RXFR1; /**< Receive FIFO Registers, offset: 0x80 */
AnnaBridge 143:86740a56073b 9804 __I uint32_t RXFR2; /**< Receive FIFO Registers, offset: 0x84 */
AnnaBridge 143:86740a56073b 9805 __I uint32_t RXFR3; /**< Receive FIFO Registers, offset: 0x88 */
AnnaBridge 143:86740a56073b 9806 } SPI_Type;
AnnaBridge 143:86740a56073b 9807
AnnaBridge 143:86740a56073b 9808 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 9809 -- SPI Register Masks
AnnaBridge 143:86740a56073b 9810 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 9811
AnnaBridge 143:86740a56073b 9812 /*!
AnnaBridge 143:86740a56073b 9813 * @addtogroup SPI_Register_Masks SPI Register Masks
AnnaBridge 143:86740a56073b 9814 * @{
AnnaBridge 143:86740a56073b 9815 */
AnnaBridge 143:86740a56073b 9816
AnnaBridge 143:86740a56073b 9817 /*! @name MCR - Module Configuration Register */
AnnaBridge 143:86740a56073b 9818 #define SPI_MCR_HALT_MASK (0x1U)
AnnaBridge 143:86740a56073b 9819 #define SPI_MCR_HALT_SHIFT (0U)
AnnaBridge 143:86740a56073b 9820 #define SPI_MCR_HALT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_HALT_SHIFT)) & SPI_MCR_HALT_MASK)
AnnaBridge 143:86740a56073b 9821 #define SPI_MCR_SMPL_PT_MASK (0x300U)
AnnaBridge 143:86740a56073b 9822 #define SPI_MCR_SMPL_PT_SHIFT (8U)
AnnaBridge 143:86740a56073b 9823 #define SPI_MCR_SMPL_PT(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_SMPL_PT_SHIFT)) & SPI_MCR_SMPL_PT_MASK)
AnnaBridge 143:86740a56073b 9824 #define SPI_MCR_CLR_RXF_MASK (0x400U)
AnnaBridge 143:86740a56073b 9825 #define SPI_MCR_CLR_RXF_SHIFT (10U)
AnnaBridge 143:86740a56073b 9826 #define SPI_MCR_CLR_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_RXF_SHIFT)) & SPI_MCR_CLR_RXF_MASK)
AnnaBridge 143:86740a56073b 9827 #define SPI_MCR_CLR_TXF_MASK (0x800U)
AnnaBridge 143:86740a56073b 9828 #define SPI_MCR_CLR_TXF_SHIFT (11U)
AnnaBridge 143:86740a56073b 9829 #define SPI_MCR_CLR_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CLR_TXF_SHIFT)) & SPI_MCR_CLR_TXF_MASK)
AnnaBridge 143:86740a56073b 9830 #define SPI_MCR_DIS_RXF_MASK (0x1000U)
AnnaBridge 143:86740a56073b 9831 #define SPI_MCR_DIS_RXF_SHIFT (12U)
AnnaBridge 143:86740a56073b 9832 #define SPI_MCR_DIS_RXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_RXF_SHIFT)) & SPI_MCR_DIS_RXF_MASK)
AnnaBridge 143:86740a56073b 9833 #define SPI_MCR_DIS_TXF_MASK (0x2000U)
AnnaBridge 143:86740a56073b 9834 #define SPI_MCR_DIS_TXF_SHIFT (13U)
AnnaBridge 143:86740a56073b 9835 #define SPI_MCR_DIS_TXF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DIS_TXF_SHIFT)) & SPI_MCR_DIS_TXF_MASK)
AnnaBridge 143:86740a56073b 9836 #define SPI_MCR_MDIS_MASK (0x4000U)
AnnaBridge 143:86740a56073b 9837 #define SPI_MCR_MDIS_SHIFT (14U)
AnnaBridge 143:86740a56073b 9838 #define SPI_MCR_MDIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MDIS_SHIFT)) & SPI_MCR_MDIS_MASK)
AnnaBridge 143:86740a56073b 9839 #define SPI_MCR_DOZE_MASK (0x8000U)
AnnaBridge 143:86740a56073b 9840 #define SPI_MCR_DOZE_SHIFT (15U)
AnnaBridge 143:86740a56073b 9841 #define SPI_MCR_DOZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DOZE_SHIFT)) & SPI_MCR_DOZE_MASK)
AnnaBridge 143:86740a56073b 9842 #define SPI_MCR_PCSIS_MASK (0x3F0000U)
AnnaBridge 143:86740a56073b 9843 #define SPI_MCR_PCSIS_SHIFT (16U)
AnnaBridge 143:86740a56073b 9844 #define SPI_MCR_PCSIS(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSIS_SHIFT)) & SPI_MCR_PCSIS_MASK)
AnnaBridge 143:86740a56073b 9845 #define SPI_MCR_ROOE_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9846 #define SPI_MCR_ROOE_SHIFT (24U)
AnnaBridge 143:86740a56073b 9847 #define SPI_MCR_ROOE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_ROOE_SHIFT)) & SPI_MCR_ROOE_MASK)
AnnaBridge 143:86740a56073b 9848 #define SPI_MCR_PCSSE_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9849 #define SPI_MCR_PCSSE_SHIFT (25U)
AnnaBridge 143:86740a56073b 9850 #define SPI_MCR_PCSSE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_PCSSE_SHIFT)) & SPI_MCR_PCSSE_MASK)
AnnaBridge 143:86740a56073b 9851 #define SPI_MCR_MTFE_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 9852 #define SPI_MCR_MTFE_SHIFT (26U)
AnnaBridge 143:86740a56073b 9853 #define SPI_MCR_MTFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MTFE_SHIFT)) & SPI_MCR_MTFE_MASK)
AnnaBridge 143:86740a56073b 9854 #define SPI_MCR_FRZ_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 9855 #define SPI_MCR_FRZ_SHIFT (27U)
AnnaBridge 143:86740a56073b 9856 #define SPI_MCR_FRZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_FRZ_SHIFT)) & SPI_MCR_FRZ_MASK)
AnnaBridge 143:86740a56073b 9857 #define SPI_MCR_DCONF_MASK (0x30000000U)
AnnaBridge 143:86740a56073b 9858 #define SPI_MCR_DCONF_SHIFT (28U)
AnnaBridge 143:86740a56073b 9859 #define SPI_MCR_DCONF(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_DCONF_SHIFT)) & SPI_MCR_DCONF_MASK)
AnnaBridge 143:86740a56073b 9860 #define SPI_MCR_CONT_SCKE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 9861 #define SPI_MCR_CONT_SCKE_SHIFT (30U)
AnnaBridge 143:86740a56073b 9862 #define SPI_MCR_CONT_SCKE(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_CONT_SCKE_SHIFT)) & SPI_MCR_CONT_SCKE_MASK)
AnnaBridge 143:86740a56073b 9863 #define SPI_MCR_MSTR_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9864 #define SPI_MCR_MSTR_SHIFT (31U)
AnnaBridge 143:86740a56073b 9865 #define SPI_MCR_MSTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_MCR_MSTR_SHIFT)) & SPI_MCR_MSTR_MASK)
AnnaBridge 143:86740a56073b 9866
AnnaBridge 143:86740a56073b 9867 /*! @name TCR - Transfer Count Register */
AnnaBridge 143:86740a56073b 9868 #define SPI_TCR_SPI_TCNT_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 9869 #define SPI_TCR_SPI_TCNT_SHIFT (16U)
AnnaBridge 143:86740a56073b 9870 #define SPI_TCR_SPI_TCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_TCR_SPI_TCNT_SHIFT)) & SPI_TCR_SPI_TCNT_MASK)
AnnaBridge 143:86740a56073b 9871
AnnaBridge 143:86740a56073b 9872 /*! @name CTAR - Clock and Transfer Attributes Register (In Master Mode) */
AnnaBridge 143:86740a56073b 9873 #define SPI_CTAR_BR_MASK (0xFU)
AnnaBridge 143:86740a56073b 9874 #define SPI_CTAR_BR_SHIFT (0U)
AnnaBridge 143:86740a56073b 9875 #define SPI_CTAR_BR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_BR_SHIFT)) & SPI_CTAR_BR_MASK)
AnnaBridge 143:86740a56073b 9876 #define SPI_CTAR_DT_MASK (0xF0U)
AnnaBridge 143:86740a56073b 9877 #define SPI_CTAR_DT_SHIFT (4U)
AnnaBridge 143:86740a56073b 9878 #define SPI_CTAR_DT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DT_SHIFT)) & SPI_CTAR_DT_MASK)
AnnaBridge 143:86740a56073b 9879 #define SPI_CTAR_ASC_MASK (0xF00U)
AnnaBridge 143:86740a56073b 9880 #define SPI_CTAR_ASC_SHIFT (8U)
AnnaBridge 143:86740a56073b 9881 #define SPI_CTAR_ASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_ASC_SHIFT)) & SPI_CTAR_ASC_MASK)
AnnaBridge 143:86740a56073b 9882 #define SPI_CTAR_CSSCK_MASK (0xF000U)
AnnaBridge 143:86740a56073b 9883 #define SPI_CTAR_CSSCK_SHIFT (12U)
AnnaBridge 143:86740a56073b 9884 #define SPI_CTAR_CSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CSSCK_SHIFT)) & SPI_CTAR_CSSCK_MASK)
AnnaBridge 143:86740a56073b 9885 #define SPI_CTAR_PBR_MASK (0x30000U)
AnnaBridge 143:86740a56073b 9886 #define SPI_CTAR_PBR_SHIFT (16U)
AnnaBridge 143:86740a56073b 9887 #define SPI_CTAR_PBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PBR_SHIFT)) & SPI_CTAR_PBR_MASK)
AnnaBridge 143:86740a56073b 9888 #define SPI_CTAR_PDT_MASK (0xC0000U)
AnnaBridge 143:86740a56073b 9889 #define SPI_CTAR_PDT_SHIFT (18U)
AnnaBridge 143:86740a56073b 9890 #define SPI_CTAR_PDT(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PDT_SHIFT)) & SPI_CTAR_PDT_MASK)
AnnaBridge 143:86740a56073b 9891 #define SPI_CTAR_PASC_MASK (0x300000U)
AnnaBridge 143:86740a56073b 9892 #define SPI_CTAR_PASC_SHIFT (20U)
AnnaBridge 143:86740a56073b 9893 #define SPI_CTAR_PASC(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PASC_SHIFT)) & SPI_CTAR_PASC_MASK)
AnnaBridge 143:86740a56073b 9894 #define SPI_CTAR_PCSSCK_MASK (0xC00000U)
AnnaBridge 143:86740a56073b 9895 #define SPI_CTAR_PCSSCK_SHIFT (22U)
AnnaBridge 143:86740a56073b 9896 #define SPI_CTAR_PCSSCK(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_PCSSCK_SHIFT)) & SPI_CTAR_PCSSCK_MASK)
AnnaBridge 143:86740a56073b 9897 #define SPI_CTAR_LSBFE_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9898 #define SPI_CTAR_LSBFE_SHIFT (24U)
AnnaBridge 143:86740a56073b 9899 #define SPI_CTAR_LSBFE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_LSBFE_SHIFT)) & SPI_CTAR_LSBFE_MASK)
AnnaBridge 143:86740a56073b 9900 #define SPI_CTAR_CPHA_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9901 #define SPI_CTAR_CPHA_SHIFT (25U)
AnnaBridge 143:86740a56073b 9902 #define SPI_CTAR_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPHA_SHIFT)) & SPI_CTAR_CPHA_MASK)
AnnaBridge 143:86740a56073b 9903 #define SPI_CTAR_CPOL_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 9904 #define SPI_CTAR_CPOL_SHIFT (26U)
AnnaBridge 143:86740a56073b 9905 #define SPI_CTAR_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_CPOL_SHIFT)) & SPI_CTAR_CPOL_MASK)
AnnaBridge 143:86740a56073b 9906 #define SPI_CTAR_FMSZ_MASK (0x78000000U)
AnnaBridge 143:86740a56073b 9907 #define SPI_CTAR_FMSZ_SHIFT (27U)
AnnaBridge 143:86740a56073b 9908 #define SPI_CTAR_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_FMSZ_SHIFT)) & SPI_CTAR_FMSZ_MASK)
AnnaBridge 143:86740a56073b 9909 #define SPI_CTAR_DBR_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9910 #define SPI_CTAR_DBR_SHIFT (31U)
AnnaBridge 143:86740a56073b 9911 #define SPI_CTAR_DBR(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_DBR_SHIFT)) & SPI_CTAR_DBR_MASK)
AnnaBridge 143:86740a56073b 9912
AnnaBridge 143:86740a56073b 9913 /* The count of SPI_CTAR */
AnnaBridge 143:86740a56073b 9914 #define SPI_CTAR_COUNT (2U)
AnnaBridge 143:86740a56073b 9915
AnnaBridge 143:86740a56073b 9916 /*! @name CTAR_SLAVE - Clock and Transfer Attributes Register (In Slave Mode) */
AnnaBridge 143:86740a56073b 9917 #define SPI_CTAR_SLAVE_CPHA_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9918 #define SPI_CTAR_SLAVE_CPHA_SHIFT (25U)
AnnaBridge 143:86740a56073b 9919 #define SPI_CTAR_SLAVE_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPHA_SHIFT)) & SPI_CTAR_SLAVE_CPHA_MASK)
AnnaBridge 143:86740a56073b 9920 #define SPI_CTAR_SLAVE_CPOL_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 9921 #define SPI_CTAR_SLAVE_CPOL_SHIFT (26U)
AnnaBridge 143:86740a56073b 9922 #define SPI_CTAR_SLAVE_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_CPOL_SHIFT)) & SPI_CTAR_SLAVE_CPOL_MASK)
AnnaBridge 143:86740a56073b 9923 #define SPI_CTAR_SLAVE_FMSZ_MASK (0xF8000000U)
AnnaBridge 143:86740a56073b 9924 #define SPI_CTAR_SLAVE_FMSZ_SHIFT (27U)
AnnaBridge 143:86740a56073b 9925 #define SPI_CTAR_SLAVE_FMSZ(x) (((uint32_t)(((uint32_t)(x)) << SPI_CTAR_SLAVE_FMSZ_SHIFT)) & SPI_CTAR_SLAVE_FMSZ_MASK)
AnnaBridge 143:86740a56073b 9926
AnnaBridge 143:86740a56073b 9927 /* The count of SPI_CTAR_SLAVE */
AnnaBridge 143:86740a56073b 9928 #define SPI_CTAR_SLAVE_COUNT (1U)
AnnaBridge 143:86740a56073b 9929
AnnaBridge 143:86740a56073b 9930 /*! @name SR - Status Register */
AnnaBridge 143:86740a56073b 9931 #define SPI_SR_POPNXTPTR_MASK (0xFU)
AnnaBridge 143:86740a56073b 9932 #define SPI_SR_POPNXTPTR_SHIFT (0U)
AnnaBridge 143:86740a56073b 9933 #define SPI_SR_POPNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_POPNXTPTR_SHIFT)) & SPI_SR_POPNXTPTR_MASK)
AnnaBridge 143:86740a56073b 9934 #define SPI_SR_RXCTR_MASK (0xF0U)
AnnaBridge 143:86740a56073b 9935 #define SPI_SR_RXCTR_SHIFT (4U)
AnnaBridge 143:86740a56073b 9936 #define SPI_SR_RXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RXCTR_SHIFT)) & SPI_SR_RXCTR_MASK)
AnnaBridge 143:86740a56073b 9937 #define SPI_SR_TXNXTPTR_MASK (0xF00U)
AnnaBridge 143:86740a56073b 9938 #define SPI_SR_TXNXTPTR_SHIFT (8U)
AnnaBridge 143:86740a56073b 9939 #define SPI_SR_TXNXTPTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXNXTPTR_SHIFT)) & SPI_SR_TXNXTPTR_MASK)
AnnaBridge 143:86740a56073b 9940 #define SPI_SR_TXCTR_MASK (0xF000U)
AnnaBridge 143:86740a56073b 9941 #define SPI_SR_TXCTR_SHIFT (12U)
AnnaBridge 143:86740a56073b 9942 #define SPI_SR_TXCTR(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXCTR_SHIFT)) & SPI_SR_TXCTR_MASK)
AnnaBridge 143:86740a56073b 9943 #define SPI_SR_RFDF_MASK (0x20000U)
AnnaBridge 143:86740a56073b 9944 #define SPI_SR_RFDF_SHIFT (17U)
AnnaBridge 143:86740a56073b 9945 #define SPI_SR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFDF_SHIFT)) & SPI_SR_RFDF_MASK)
AnnaBridge 143:86740a56073b 9946 #define SPI_SR_RFOF_MASK (0x80000U)
AnnaBridge 143:86740a56073b 9947 #define SPI_SR_RFOF_SHIFT (19U)
AnnaBridge 143:86740a56073b 9948 #define SPI_SR_RFOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_RFOF_SHIFT)) & SPI_SR_RFOF_MASK)
AnnaBridge 143:86740a56073b 9949 #define SPI_SR_TFFF_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9950 #define SPI_SR_TFFF_SHIFT (25U)
AnnaBridge 143:86740a56073b 9951 #define SPI_SR_TFFF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFFF_SHIFT)) & SPI_SR_TFFF_MASK)
AnnaBridge 143:86740a56073b 9952 #define SPI_SR_TFUF_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 9953 #define SPI_SR_TFUF_SHIFT (27U)
AnnaBridge 143:86740a56073b 9954 #define SPI_SR_TFUF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TFUF_SHIFT)) & SPI_SR_TFUF_MASK)
AnnaBridge 143:86740a56073b 9955 #define SPI_SR_EOQF_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 9956 #define SPI_SR_EOQF_SHIFT (28U)
AnnaBridge 143:86740a56073b 9957 #define SPI_SR_EOQF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_EOQF_SHIFT)) & SPI_SR_EOQF_MASK)
AnnaBridge 143:86740a56073b 9958 #define SPI_SR_TXRXS_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 9959 #define SPI_SR_TXRXS_SHIFT (30U)
AnnaBridge 143:86740a56073b 9960 #define SPI_SR_TXRXS(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TXRXS_SHIFT)) & SPI_SR_TXRXS_MASK)
AnnaBridge 143:86740a56073b 9961 #define SPI_SR_TCF_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9962 #define SPI_SR_TCF_SHIFT (31U)
AnnaBridge 143:86740a56073b 9963 #define SPI_SR_TCF(x) (((uint32_t)(((uint32_t)(x)) << SPI_SR_TCF_SHIFT)) & SPI_SR_TCF_MASK)
AnnaBridge 143:86740a56073b 9964
AnnaBridge 143:86740a56073b 9965 /*! @name RSER - DMA/Interrupt Request Select and Enable Register */
AnnaBridge 143:86740a56073b 9966 #define SPI_RSER_RFDF_DIRS_MASK (0x10000U)
AnnaBridge 143:86740a56073b 9967 #define SPI_RSER_RFDF_DIRS_SHIFT (16U)
AnnaBridge 143:86740a56073b 9968 #define SPI_RSER_RFDF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_DIRS_SHIFT)) & SPI_RSER_RFDF_DIRS_MASK)
AnnaBridge 143:86740a56073b 9969 #define SPI_RSER_RFDF_RE_MASK (0x20000U)
AnnaBridge 143:86740a56073b 9970 #define SPI_RSER_RFDF_RE_SHIFT (17U)
AnnaBridge 143:86740a56073b 9971 #define SPI_RSER_RFDF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFDF_RE_SHIFT)) & SPI_RSER_RFDF_RE_MASK)
AnnaBridge 143:86740a56073b 9972 #define SPI_RSER_RFOF_RE_MASK (0x80000U)
AnnaBridge 143:86740a56073b 9973 #define SPI_RSER_RFOF_RE_SHIFT (19U)
AnnaBridge 143:86740a56073b 9974 #define SPI_RSER_RFOF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_RFOF_RE_SHIFT)) & SPI_RSER_RFOF_RE_MASK)
AnnaBridge 143:86740a56073b 9975 #define SPI_RSER_TFFF_DIRS_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 9976 #define SPI_RSER_TFFF_DIRS_SHIFT (24U)
AnnaBridge 143:86740a56073b 9977 #define SPI_RSER_TFFF_DIRS(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_DIRS_SHIFT)) & SPI_RSER_TFFF_DIRS_MASK)
AnnaBridge 143:86740a56073b 9978 #define SPI_RSER_TFFF_RE_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 9979 #define SPI_RSER_TFFF_RE_SHIFT (25U)
AnnaBridge 143:86740a56073b 9980 #define SPI_RSER_TFFF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFFF_RE_SHIFT)) & SPI_RSER_TFFF_RE_MASK)
AnnaBridge 143:86740a56073b 9981 #define SPI_RSER_TFUF_RE_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 9982 #define SPI_RSER_TFUF_RE_SHIFT (27U)
AnnaBridge 143:86740a56073b 9983 #define SPI_RSER_TFUF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TFUF_RE_SHIFT)) & SPI_RSER_TFUF_RE_MASK)
AnnaBridge 143:86740a56073b 9984 #define SPI_RSER_EOQF_RE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 9985 #define SPI_RSER_EOQF_RE_SHIFT (28U)
AnnaBridge 143:86740a56073b 9986 #define SPI_RSER_EOQF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_EOQF_RE_SHIFT)) & SPI_RSER_EOQF_RE_MASK)
AnnaBridge 143:86740a56073b 9987 #define SPI_RSER_TCF_RE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 9988 #define SPI_RSER_TCF_RE_SHIFT (31U)
AnnaBridge 143:86740a56073b 9989 #define SPI_RSER_TCF_RE(x) (((uint32_t)(((uint32_t)(x)) << SPI_RSER_TCF_RE_SHIFT)) & SPI_RSER_TCF_RE_MASK)
AnnaBridge 143:86740a56073b 9990
AnnaBridge 143:86740a56073b 9991 /*! @name PUSHR - PUSH TX FIFO Register In Master Mode */
AnnaBridge 143:86740a56073b 9992 #define SPI_PUSHR_TXDATA_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 9993 #define SPI_PUSHR_TXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 9994 #define SPI_PUSHR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_TXDATA_SHIFT)) & SPI_PUSHR_TXDATA_MASK)
AnnaBridge 143:86740a56073b 9995 #define SPI_PUSHR_PCS_MASK (0x3F0000U)
AnnaBridge 143:86740a56073b 9996 #define SPI_PUSHR_PCS_SHIFT (16U)
AnnaBridge 143:86740a56073b 9997 #define SPI_PUSHR_PCS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_PCS_SHIFT)) & SPI_PUSHR_PCS_MASK)
AnnaBridge 143:86740a56073b 9998 #define SPI_PUSHR_CTCNT_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 9999 #define SPI_PUSHR_CTCNT_SHIFT (26U)
AnnaBridge 143:86740a56073b 10000 #define SPI_PUSHR_CTCNT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTCNT_SHIFT)) & SPI_PUSHR_CTCNT_MASK)
AnnaBridge 143:86740a56073b 10001 #define SPI_PUSHR_EOQ_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 10002 #define SPI_PUSHR_EOQ_SHIFT (27U)
AnnaBridge 143:86740a56073b 10003 #define SPI_PUSHR_EOQ(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_EOQ_SHIFT)) & SPI_PUSHR_EOQ_MASK)
AnnaBridge 143:86740a56073b 10004 #define SPI_PUSHR_CTAS_MASK (0x70000000U)
AnnaBridge 143:86740a56073b 10005 #define SPI_PUSHR_CTAS_SHIFT (28U)
AnnaBridge 143:86740a56073b 10006 #define SPI_PUSHR_CTAS(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CTAS_SHIFT)) & SPI_PUSHR_CTAS_MASK)
AnnaBridge 143:86740a56073b 10007 #define SPI_PUSHR_CONT_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 10008 #define SPI_PUSHR_CONT_SHIFT (31U)
AnnaBridge 143:86740a56073b 10009 #define SPI_PUSHR_CONT(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_CONT_SHIFT)) & SPI_PUSHR_CONT_MASK)
AnnaBridge 143:86740a56073b 10010
AnnaBridge 143:86740a56073b 10011 /*! @name PUSHR_SLAVE - PUSH TX FIFO Register In Slave Mode */
AnnaBridge 143:86740a56073b 10012 #define SPI_PUSHR_SLAVE_TXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 10013 #define SPI_PUSHR_SLAVE_TXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10014 #define SPI_PUSHR_SLAVE_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_PUSHR_SLAVE_TXDATA_SHIFT)) & SPI_PUSHR_SLAVE_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10015
AnnaBridge 143:86740a56073b 10016 /*! @name POPR - POP RX FIFO Register */
AnnaBridge 143:86740a56073b 10017 #define SPI_POPR_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 10018 #define SPI_POPR_RXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10019 #define SPI_POPR_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_POPR_RXDATA_SHIFT)) & SPI_POPR_RXDATA_MASK)
AnnaBridge 143:86740a56073b 10020
AnnaBridge 143:86740a56073b 10021 /*! @name TXFR0 - Transmit FIFO Registers */
AnnaBridge 143:86740a56073b 10022 #define SPI_TXFR0_TXDATA_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 10023 #define SPI_TXFR0_TXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10024 #define SPI_TXFR0_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXDATA_SHIFT)) & SPI_TXFR0_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10025 #define SPI_TXFR0_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 10026 #define SPI_TXFR0_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 143:86740a56073b 10027 #define SPI_TXFR0_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR0_TXCMD_TXDATA_SHIFT)) & SPI_TXFR0_TXCMD_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10028
AnnaBridge 143:86740a56073b 10029 /*! @name TXFR1 - Transmit FIFO Registers */
AnnaBridge 143:86740a56073b 10030 #define SPI_TXFR1_TXDATA_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 10031 #define SPI_TXFR1_TXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10032 #define SPI_TXFR1_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXDATA_SHIFT)) & SPI_TXFR1_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10033 #define SPI_TXFR1_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 10034 #define SPI_TXFR1_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 143:86740a56073b 10035 #define SPI_TXFR1_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR1_TXCMD_TXDATA_SHIFT)) & SPI_TXFR1_TXCMD_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10036
AnnaBridge 143:86740a56073b 10037 /*! @name TXFR2 - Transmit FIFO Registers */
AnnaBridge 143:86740a56073b 10038 #define SPI_TXFR2_TXDATA_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 10039 #define SPI_TXFR2_TXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10040 #define SPI_TXFR2_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXDATA_SHIFT)) & SPI_TXFR2_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10041 #define SPI_TXFR2_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 10042 #define SPI_TXFR2_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 143:86740a56073b 10043 #define SPI_TXFR2_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR2_TXCMD_TXDATA_SHIFT)) & SPI_TXFR2_TXCMD_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10044
AnnaBridge 143:86740a56073b 10045 /*! @name TXFR3 - Transmit FIFO Registers */
AnnaBridge 143:86740a56073b 10046 #define SPI_TXFR3_TXDATA_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 10047 #define SPI_TXFR3_TXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10048 #define SPI_TXFR3_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXDATA_SHIFT)) & SPI_TXFR3_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10049 #define SPI_TXFR3_TXCMD_TXDATA_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 10050 #define SPI_TXFR3_TXCMD_TXDATA_SHIFT (16U)
AnnaBridge 143:86740a56073b 10051 #define SPI_TXFR3_TXCMD_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_TXFR3_TXCMD_TXDATA_SHIFT)) & SPI_TXFR3_TXCMD_TXDATA_MASK)
AnnaBridge 143:86740a56073b 10052
AnnaBridge 143:86740a56073b 10053 /*! @name RXFR0 - Receive FIFO Registers */
AnnaBridge 143:86740a56073b 10054 #define SPI_RXFR0_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 10055 #define SPI_RXFR0_RXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10056 #define SPI_RXFR0_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR0_RXDATA_SHIFT)) & SPI_RXFR0_RXDATA_MASK)
AnnaBridge 143:86740a56073b 10057
AnnaBridge 143:86740a56073b 10058 /*! @name RXFR1 - Receive FIFO Registers */
AnnaBridge 143:86740a56073b 10059 #define SPI_RXFR1_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 10060 #define SPI_RXFR1_RXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10061 #define SPI_RXFR1_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR1_RXDATA_SHIFT)) & SPI_RXFR1_RXDATA_MASK)
AnnaBridge 143:86740a56073b 10062
AnnaBridge 143:86740a56073b 10063 /*! @name RXFR2 - Receive FIFO Registers */
AnnaBridge 143:86740a56073b 10064 #define SPI_RXFR2_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 10065 #define SPI_RXFR2_RXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10066 #define SPI_RXFR2_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR2_RXDATA_SHIFT)) & SPI_RXFR2_RXDATA_MASK)
AnnaBridge 143:86740a56073b 10067
AnnaBridge 143:86740a56073b 10068 /*! @name RXFR3 - Receive FIFO Registers */
AnnaBridge 143:86740a56073b 10069 #define SPI_RXFR3_RXDATA_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 10070 #define SPI_RXFR3_RXDATA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10071 #define SPI_RXFR3_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_RXFR3_RXDATA_SHIFT)) & SPI_RXFR3_RXDATA_MASK)
AnnaBridge 143:86740a56073b 10072
AnnaBridge 143:86740a56073b 10073
AnnaBridge 143:86740a56073b 10074 /*!
AnnaBridge 143:86740a56073b 10075 * @}
AnnaBridge 143:86740a56073b 10076 */ /* end of group SPI_Register_Masks */
AnnaBridge 143:86740a56073b 10077
AnnaBridge 143:86740a56073b 10078
AnnaBridge 143:86740a56073b 10079 /* SPI - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 10080 /** Peripheral SPI0 base address */
AnnaBridge 143:86740a56073b 10081 #define SPI0_BASE (0x4002C000u)
AnnaBridge 143:86740a56073b 10082 /** Peripheral SPI0 base pointer */
AnnaBridge 143:86740a56073b 10083 #define SPI0 ((SPI_Type *)SPI0_BASE)
AnnaBridge 143:86740a56073b 10084 /** Peripheral SPI1 base address */
AnnaBridge 143:86740a56073b 10085 #define SPI1_BASE (0x4002D000u)
AnnaBridge 143:86740a56073b 10086 /** Peripheral SPI1 base pointer */
AnnaBridge 143:86740a56073b 10087 #define SPI1 ((SPI_Type *)SPI1_BASE)
AnnaBridge 143:86740a56073b 10088 /** Peripheral SPI2 base address */
AnnaBridge 143:86740a56073b 10089 #define SPI2_BASE (0x400AC000u)
AnnaBridge 143:86740a56073b 10090 /** Peripheral SPI2 base pointer */
AnnaBridge 143:86740a56073b 10091 #define SPI2 ((SPI_Type *)SPI2_BASE)
AnnaBridge 143:86740a56073b 10092 /** Array initializer of SPI peripheral base addresses */
AnnaBridge 143:86740a56073b 10093 #define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE }
AnnaBridge 143:86740a56073b 10094 /** Array initializer of SPI peripheral base pointers */
AnnaBridge 143:86740a56073b 10095 #define SPI_BASE_PTRS { SPI0, SPI1, SPI2 }
AnnaBridge 143:86740a56073b 10096 /** Interrupt vectors for the SPI peripheral type */
AnnaBridge 143:86740a56073b 10097 #define SPI_IRQS { SPI0_IRQn, SPI1_IRQn, SPI2_IRQn }
AnnaBridge 143:86740a56073b 10098
AnnaBridge 143:86740a56073b 10099 /*!
AnnaBridge 143:86740a56073b 10100 * @}
AnnaBridge 143:86740a56073b 10101 */ /* end of group SPI_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 10102
AnnaBridge 143:86740a56073b 10103
AnnaBridge 143:86740a56073b 10104 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 10105 -- SYSMPU Peripheral Access Layer
AnnaBridge 143:86740a56073b 10106 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 10107
AnnaBridge 143:86740a56073b 10108 /*!
AnnaBridge 143:86740a56073b 10109 * @addtogroup SYSMPU_Peripheral_Access_Layer SYSMPU Peripheral Access Layer
AnnaBridge 143:86740a56073b 10110 * @{
AnnaBridge 143:86740a56073b 10111 */
AnnaBridge 143:86740a56073b 10112
AnnaBridge 143:86740a56073b 10113 /** SYSMPU - Register Layout Typedef */
AnnaBridge 143:86740a56073b 10114 typedef struct {
AnnaBridge 143:86740a56073b 10115 __IO uint32_t CESR; /**< Control/Error Status Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 10116 uint8_t RESERVED_0[12];
AnnaBridge 143:86740a56073b 10117 struct { /* offset: 0x10, array step: 0x8 */
AnnaBridge 143:86740a56073b 10118 __I uint32_t EAR; /**< Error Address Register, slave port n, array offset: 0x10, array step: 0x8 */
AnnaBridge 143:86740a56073b 10119 __I uint32_t EDR; /**< Error Detail Register, slave port n, array offset: 0x14, array step: 0x8 */
AnnaBridge 143:86740a56073b 10120 } SP[5];
AnnaBridge 143:86740a56073b 10121 uint8_t RESERVED_1[968];
AnnaBridge 143:86740a56073b 10122 __IO uint32_t WORD[12][4]; /**< Region Descriptor n, Word 0..Region Descriptor n, Word 3, array offset: 0x400, array step: index*0x10, index2*0x4 */
AnnaBridge 143:86740a56073b 10123 uint8_t RESERVED_2[832];
AnnaBridge 143:86740a56073b 10124 __IO uint32_t RGDAAC[12]; /**< Region Descriptor Alternate Access Control n, array offset: 0x800, array step: 0x4 */
AnnaBridge 143:86740a56073b 10125 } SYSMPU_Type;
AnnaBridge 143:86740a56073b 10126
AnnaBridge 143:86740a56073b 10127 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 10128 -- SYSMPU Register Masks
AnnaBridge 143:86740a56073b 10129 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 10130
AnnaBridge 143:86740a56073b 10131 /*!
AnnaBridge 143:86740a56073b 10132 * @addtogroup SYSMPU_Register_Masks SYSMPU Register Masks
AnnaBridge 143:86740a56073b 10133 * @{
AnnaBridge 143:86740a56073b 10134 */
AnnaBridge 143:86740a56073b 10135
AnnaBridge 143:86740a56073b 10136 /*! @name CESR - Control/Error Status Register */
AnnaBridge 143:86740a56073b 10137 #define SYSMPU_CESR_VLD_MASK (0x1U)
AnnaBridge 143:86740a56073b 10138 #define SYSMPU_CESR_VLD_SHIFT (0U)
AnnaBridge 143:86740a56073b 10139 #define SYSMPU_CESR_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_VLD_SHIFT)) & SYSMPU_CESR_VLD_MASK)
AnnaBridge 143:86740a56073b 10140 #define SYSMPU_CESR_NRGD_MASK (0xF00U)
AnnaBridge 143:86740a56073b 10141 #define SYSMPU_CESR_NRGD_SHIFT (8U)
AnnaBridge 143:86740a56073b 10142 #define SYSMPU_CESR_NRGD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NRGD_SHIFT)) & SYSMPU_CESR_NRGD_MASK)
AnnaBridge 143:86740a56073b 10143 #define SYSMPU_CESR_NSP_MASK (0xF000U)
AnnaBridge 143:86740a56073b 10144 #define SYSMPU_CESR_NSP_SHIFT (12U)
AnnaBridge 143:86740a56073b 10145 #define SYSMPU_CESR_NSP(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_NSP_SHIFT)) & SYSMPU_CESR_NSP_MASK)
AnnaBridge 143:86740a56073b 10146 #define SYSMPU_CESR_HRL_MASK (0xF0000U)
AnnaBridge 143:86740a56073b 10147 #define SYSMPU_CESR_HRL_SHIFT (16U)
AnnaBridge 143:86740a56073b 10148 #define SYSMPU_CESR_HRL(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_HRL_SHIFT)) & SYSMPU_CESR_HRL_MASK)
AnnaBridge 143:86740a56073b 10149 #define SYSMPU_CESR_SPERR_MASK (0xF8000000U)
AnnaBridge 143:86740a56073b 10150 #define SYSMPU_CESR_SPERR_SHIFT (27U)
AnnaBridge 143:86740a56073b 10151 #define SYSMPU_CESR_SPERR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_CESR_SPERR_SHIFT)) & SYSMPU_CESR_SPERR_MASK)
AnnaBridge 143:86740a56073b 10152
AnnaBridge 143:86740a56073b 10153 /*! @name EAR - Error Address Register, slave port n */
AnnaBridge 143:86740a56073b 10154 #define SYSMPU_EAR_EADDR_MASK (0xFFFFFFFFU)
AnnaBridge 143:86740a56073b 10155 #define SYSMPU_EAR_EADDR_SHIFT (0U)
AnnaBridge 143:86740a56073b 10156 #define SYSMPU_EAR_EADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EAR_EADDR_SHIFT)) & SYSMPU_EAR_EADDR_MASK)
AnnaBridge 143:86740a56073b 10157
AnnaBridge 143:86740a56073b 10158 /* The count of SYSMPU_EAR */
AnnaBridge 143:86740a56073b 10159 #define SYSMPU_EAR_COUNT (5U)
AnnaBridge 143:86740a56073b 10160
AnnaBridge 143:86740a56073b 10161 /*! @name EDR - Error Detail Register, slave port n */
AnnaBridge 143:86740a56073b 10162 #define SYSMPU_EDR_ERW_MASK (0x1U)
AnnaBridge 143:86740a56073b 10163 #define SYSMPU_EDR_ERW_SHIFT (0U)
AnnaBridge 143:86740a56073b 10164 #define SYSMPU_EDR_ERW(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_ERW_SHIFT)) & SYSMPU_EDR_ERW_MASK)
AnnaBridge 143:86740a56073b 10165 #define SYSMPU_EDR_EATTR_MASK (0xEU)
AnnaBridge 143:86740a56073b 10166 #define SYSMPU_EDR_EATTR_SHIFT (1U)
AnnaBridge 143:86740a56073b 10167 #define SYSMPU_EDR_EATTR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EATTR_SHIFT)) & SYSMPU_EDR_EATTR_MASK)
AnnaBridge 143:86740a56073b 10168 #define SYSMPU_EDR_EMN_MASK (0xF0U)
AnnaBridge 143:86740a56073b 10169 #define SYSMPU_EDR_EMN_SHIFT (4U)
AnnaBridge 143:86740a56073b 10170 #define SYSMPU_EDR_EMN(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EMN_SHIFT)) & SYSMPU_EDR_EMN_MASK)
AnnaBridge 143:86740a56073b 10171 #define SYSMPU_EDR_EPID_MASK (0xFF00U)
AnnaBridge 143:86740a56073b 10172 #define SYSMPU_EDR_EPID_SHIFT (8U)
AnnaBridge 143:86740a56073b 10173 #define SYSMPU_EDR_EPID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EPID_SHIFT)) & SYSMPU_EDR_EPID_MASK)
AnnaBridge 143:86740a56073b 10174 #define SYSMPU_EDR_EACD_MASK (0xFFFF0000U)
AnnaBridge 143:86740a56073b 10175 #define SYSMPU_EDR_EACD_SHIFT (16U)
AnnaBridge 143:86740a56073b 10176 #define SYSMPU_EDR_EACD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_EDR_EACD_SHIFT)) & SYSMPU_EDR_EACD_MASK)
AnnaBridge 143:86740a56073b 10177
AnnaBridge 143:86740a56073b 10178 /* The count of SYSMPU_EDR */
AnnaBridge 143:86740a56073b 10179 #define SYSMPU_EDR_COUNT (5U)
AnnaBridge 143:86740a56073b 10180
AnnaBridge 143:86740a56073b 10181 /*! @name WORD - Region Descriptor n, Word 0..Region Descriptor n, Word 3 */
AnnaBridge 143:86740a56073b 10182 #define SYSMPU_WORD_VLD_MASK (0x1U)
AnnaBridge 143:86740a56073b 10183 #define SYSMPU_WORD_VLD_SHIFT (0U)
AnnaBridge 143:86740a56073b 10184 #define SYSMPU_WORD_VLD(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_VLD_SHIFT)) & SYSMPU_WORD_VLD_MASK)
AnnaBridge 143:86740a56073b 10185 #define SYSMPU_WORD_M0UM_MASK (0x7U)
AnnaBridge 143:86740a56073b 10186 #define SYSMPU_WORD_M0UM_SHIFT (0U)
AnnaBridge 143:86740a56073b 10187 #define SYSMPU_WORD_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0UM_SHIFT)) & SYSMPU_WORD_M0UM_MASK)
AnnaBridge 143:86740a56073b 10188 #define SYSMPU_WORD_M0SM_MASK (0x18U)
AnnaBridge 143:86740a56073b 10189 #define SYSMPU_WORD_M0SM_SHIFT (3U)
AnnaBridge 143:86740a56073b 10190 #define SYSMPU_WORD_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0SM_SHIFT)) & SYSMPU_WORD_M0SM_MASK)
AnnaBridge 143:86740a56073b 10191 #define SYSMPU_WORD_M0PE_MASK (0x20U)
AnnaBridge 143:86740a56073b 10192 #define SYSMPU_WORD_M0PE_SHIFT (5U)
AnnaBridge 143:86740a56073b 10193 #define SYSMPU_WORD_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M0PE_SHIFT)) & SYSMPU_WORD_M0PE_MASK)
AnnaBridge 143:86740a56073b 10194 #define SYSMPU_WORD_ENDADDR_MASK (0xFFFFFFE0U)
AnnaBridge 143:86740a56073b 10195 #define SYSMPU_WORD_ENDADDR_SHIFT (5U)
AnnaBridge 143:86740a56073b 10196 #define SYSMPU_WORD_ENDADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_ENDADDR_SHIFT)) & SYSMPU_WORD_ENDADDR_MASK)
AnnaBridge 143:86740a56073b 10197 #define SYSMPU_WORD_SRTADDR_MASK (0xFFFFFFE0U)
AnnaBridge 143:86740a56073b 10198 #define SYSMPU_WORD_SRTADDR_SHIFT (5U)
AnnaBridge 143:86740a56073b 10199 #define SYSMPU_WORD_SRTADDR(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_SRTADDR_SHIFT)) & SYSMPU_WORD_SRTADDR_MASK)
AnnaBridge 143:86740a56073b 10200 #define SYSMPU_WORD_M1UM_MASK (0x1C0U)
AnnaBridge 143:86740a56073b 10201 #define SYSMPU_WORD_M1UM_SHIFT (6U)
AnnaBridge 143:86740a56073b 10202 #define SYSMPU_WORD_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1UM_SHIFT)) & SYSMPU_WORD_M1UM_MASK)
AnnaBridge 143:86740a56073b 10203 #define SYSMPU_WORD_M1SM_MASK (0x600U)
AnnaBridge 143:86740a56073b 10204 #define SYSMPU_WORD_M1SM_SHIFT (9U)
AnnaBridge 143:86740a56073b 10205 #define SYSMPU_WORD_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1SM_SHIFT)) & SYSMPU_WORD_M1SM_MASK)
AnnaBridge 143:86740a56073b 10206 #define SYSMPU_WORD_M1PE_MASK (0x800U)
AnnaBridge 143:86740a56073b 10207 #define SYSMPU_WORD_M1PE_SHIFT (11U)
AnnaBridge 143:86740a56073b 10208 #define SYSMPU_WORD_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M1PE_SHIFT)) & SYSMPU_WORD_M1PE_MASK)
AnnaBridge 143:86740a56073b 10209 #define SYSMPU_WORD_M2UM_MASK (0x7000U)
AnnaBridge 143:86740a56073b 10210 #define SYSMPU_WORD_M2UM_SHIFT (12U)
AnnaBridge 143:86740a56073b 10211 #define SYSMPU_WORD_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2UM_SHIFT)) & SYSMPU_WORD_M2UM_MASK)
AnnaBridge 143:86740a56073b 10212 #define SYSMPU_WORD_M2SM_MASK (0x18000U)
AnnaBridge 143:86740a56073b 10213 #define SYSMPU_WORD_M2SM_SHIFT (15U)
AnnaBridge 143:86740a56073b 10214 #define SYSMPU_WORD_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2SM_SHIFT)) & SYSMPU_WORD_M2SM_MASK)
AnnaBridge 143:86740a56073b 10215 #define SYSMPU_WORD_PIDMASK_MASK (0xFF0000U)
AnnaBridge 143:86740a56073b 10216 #define SYSMPU_WORD_PIDMASK_SHIFT (16U)
AnnaBridge 143:86740a56073b 10217 #define SYSMPU_WORD_PIDMASK(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PIDMASK_SHIFT)) & SYSMPU_WORD_PIDMASK_MASK)
AnnaBridge 143:86740a56073b 10218 #define SYSMPU_WORD_M2PE_MASK (0x20000U)
AnnaBridge 143:86740a56073b 10219 #define SYSMPU_WORD_M2PE_SHIFT (17U)
AnnaBridge 143:86740a56073b 10220 #define SYSMPU_WORD_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M2PE_SHIFT)) & SYSMPU_WORD_M2PE_MASK)
AnnaBridge 143:86740a56073b 10221 #define SYSMPU_WORD_M3UM_MASK (0x1C0000U)
AnnaBridge 143:86740a56073b 10222 #define SYSMPU_WORD_M3UM_SHIFT (18U)
AnnaBridge 143:86740a56073b 10223 #define SYSMPU_WORD_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3UM_SHIFT)) & SYSMPU_WORD_M3UM_MASK)
AnnaBridge 143:86740a56073b 10224 #define SYSMPU_WORD_M3SM_MASK (0x600000U)
AnnaBridge 143:86740a56073b 10225 #define SYSMPU_WORD_M3SM_SHIFT (21U)
AnnaBridge 143:86740a56073b 10226 #define SYSMPU_WORD_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3SM_SHIFT)) & SYSMPU_WORD_M3SM_MASK)
AnnaBridge 143:86740a56073b 10227 #define SYSMPU_WORD_M3PE_MASK (0x800000U)
AnnaBridge 143:86740a56073b 10228 #define SYSMPU_WORD_M3PE_SHIFT (23U)
AnnaBridge 143:86740a56073b 10229 #define SYSMPU_WORD_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M3PE_SHIFT)) & SYSMPU_WORD_M3PE_MASK)
AnnaBridge 143:86740a56073b 10230 #define SYSMPU_WORD_PID_MASK (0xFF000000U)
AnnaBridge 143:86740a56073b 10231 #define SYSMPU_WORD_PID_SHIFT (24U)
AnnaBridge 143:86740a56073b 10232 #define SYSMPU_WORD_PID(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_PID_SHIFT)) & SYSMPU_WORD_PID_MASK)
AnnaBridge 143:86740a56073b 10233 #define SYSMPU_WORD_M4WE_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 10234 #define SYSMPU_WORD_M4WE_SHIFT (24U)
AnnaBridge 143:86740a56073b 10235 #define SYSMPU_WORD_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4WE_SHIFT)) & SYSMPU_WORD_M4WE_MASK)
AnnaBridge 143:86740a56073b 10236 #define SYSMPU_WORD_M4RE_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 10237 #define SYSMPU_WORD_M4RE_SHIFT (25U)
AnnaBridge 143:86740a56073b 10238 #define SYSMPU_WORD_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M4RE_SHIFT)) & SYSMPU_WORD_M4RE_MASK)
AnnaBridge 143:86740a56073b 10239 #define SYSMPU_WORD_M5WE_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 10240 #define SYSMPU_WORD_M5WE_SHIFT (26U)
AnnaBridge 143:86740a56073b 10241 #define SYSMPU_WORD_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5WE_SHIFT)) & SYSMPU_WORD_M5WE_MASK)
AnnaBridge 143:86740a56073b 10242 #define SYSMPU_WORD_M5RE_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 10243 #define SYSMPU_WORD_M5RE_SHIFT (27U)
AnnaBridge 143:86740a56073b 10244 #define SYSMPU_WORD_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M5RE_SHIFT)) & SYSMPU_WORD_M5RE_MASK)
AnnaBridge 143:86740a56073b 10245 #define SYSMPU_WORD_M6WE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 10246 #define SYSMPU_WORD_M6WE_SHIFT (28U)
AnnaBridge 143:86740a56073b 10247 #define SYSMPU_WORD_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6WE_SHIFT)) & SYSMPU_WORD_M6WE_MASK)
AnnaBridge 143:86740a56073b 10248 #define SYSMPU_WORD_M6RE_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 10249 #define SYSMPU_WORD_M6RE_SHIFT (29U)
AnnaBridge 143:86740a56073b 10250 #define SYSMPU_WORD_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M6RE_SHIFT)) & SYSMPU_WORD_M6RE_MASK)
AnnaBridge 143:86740a56073b 10251 #define SYSMPU_WORD_M7WE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 10252 #define SYSMPU_WORD_M7WE_SHIFT (30U)
AnnaBridge 143:86740a56073b 10253 #define SYSMPU_WORD_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7WE_SHIFT)) & SYSMPU_WORD_M7WE_MASK)
AnnaBridge 143:86740a56073b 10254 #define SYSMPU_WORD_M7RE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 10255 #define SYSMPU_WORD_M7RE_SHIFT (31U)
AnnaBridge 143:86740a56073b 10256 #define SYSMPU_WORD_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_WORD_M7RE_SHIFT)) & SYSMPU_WORD_M7RE_MASK)
AnnaBridge 143:86740a56073b 10257
AnnaBridge 143:86740a56073b 10258 /* The count of SYSMPU_WORD */
AnnaBridge 143:86740a56073b 10259 #define SYSMPU_WORD_COUNT (12U)
AnnaBridge 143:86740a56073b 10260
AnnaBridge 143:86740a56073b 10261 /* The count of SYSMPU_WORD */
AnnaBridge 143:86740a56073b 10262 #define SYSMPU_WORD_COUNT2 (4U)
AnnaBridge 143:86740a56073b 10263
AnnaBridge 143:86740a56073b 10264 /*! @name RGDAAC - Region Descriptor Alternate Access Control n */
AnnaBridge 143:86740a56073b 10265 #define SYSMPU_RGDAAC_M0UM_MASK (0x7U)
AnnaBridge 143:86740a56073b 10266 #define SYSMPU_RGDAAC_M0UM_SHIFT (0U)
AnnaBridge 143:86740a56073b 10267 #define SYSMPU_RGDAAC_M0UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0UM_SHIFT)) & SYSMPU_RGDAAC_M0UM_MASK)
AnnaBridge 143:86740a56073b 10268 #define SYSMPU_RGDAAC_M0SM_MASK (0x18U)
AnnaBridge 143:86740a56073b 10269 #define SYSMPU_RGDAAC_M0SM_SHIFT (3U)
AnnaBridge 143:86740a56073b 10270 #define SYSMPU_RGDAAC_M0SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0SM_SHIFT)) & SYSMPU_RGDAAC_M0SM_MASK)
AnnaBridge 143:86740a56073b 10271 #define SYSMPU_RGDAAC_M0PE_MASK (0x20U)
AnnaBridge 143:86740a56073b 10272 #define SYSMPU_RGDAAC_M0PE_SHIFT (5U)
AnnaBridge 143:86740a56073b 10273 #define SYSMPU_RGDAAC_M0PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M0PE_SHIFT)) & SYSMPU_RGDAAC_M0PE_MASK)
AnnaBridge 143:86740a56073b 10274 #define SYSMPU_RGDAAC_M1UM_MASK (0x1C0U)
AnnaBridge 143:86740a56073b 10275 #define SYSMPU_RGDAAC_M1UM_SHIFT (6U)
AnnaBridge 143:86740a56073b 10276 #define SYSMPU_RGDAAC_M1UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1UM_SHIFT)) & SYSMPU_RGDAAC_M1UM_MASK)
AnnaBridge 143:86740a56073b 10277 #define SYSMPU_RGDAAC_M1SM_MASK (0x600U)
AnnaBridge 143:86740a56073b 10278 #define SYSMPU_RGDAAC_M1SM_SHIFT (9U)
AnnaBridge 143:86740a56073b 10279 #define SYSMPU_RGDAAC_M1SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1SM_SHIFT)) & SYSMPU_RGDAAC_M1SM_MASK)
AnnaBridge 143:86740a56073b 10280 #define SYSMPU_RGDAAC_M1PE_MASK (0x800U)
AnnaBridge 143:86740a56073b 10281 #define SYSMPU_RGDAAC_M1PE_SHIFT (11U)
AnnaBridge 143:86740a56073b 10282 #define SYSMPU_RGDAAC_M1PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M1PE_SHIFT)) & SYSMPU_RGDAAC_M1PE_MASK)
AnnaBridge 143:86740a56073b 10283 #define SYSMPU_RGDAAC_M2UM_MASK (0x7000U)
AnnaBridge 143:86740a56073b 10284 #define SYSMPU_RGDAAC_M2UM_SHIFT (12U)
AnnaBridge 143:86740a56073b 10285 #define SYSMPU_RGDAAC_M2UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2UM_SHIFT)) & SYSMPU_RGDAAC_M2UM_MASK)
AnnaBridge 143:86740a56073b 10286 #define SYSMPU_RGDAAC_M2SM_MASK (0x18000U)
AnnaBridge 143:86740a56073b 10287 #define SYSMPU_RGDAAC_M2SM_SHIFT (15U)
AnnaBridge 143:86740a56073b 10288 #define SYSMPU_RGDAAC_M2SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2SM_SHIFT)) & SYSMPU_RGDAAC_M2SM_MASK)
AnnaBridge 143:86740a56073b 10289 #define SYSMPU_RGDAAC_M2PE_MASK (0x20000U)
AnnaBridge 143:86740a56073b 10290 #define SYSMPU_RGDAAC_M2PE_SHIFT (17U)
AnnaBridge 143:86740a56073b 10291 #define SYSMPU_RGDAAC_M2PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M2PE_SHIFT)) & SYSMPU_RGDAAC_M2PE_MASK)
AnnaBridge 143:86740a56073b 10292 #define SYSMPU_RGDAAC_M3UM_MASK (0x1C0000U)
AnnaBridge 143:86740a56073b 10293 #define SYSMPU_RGDAAC_M3UM_SHIFT (18U)
AnnaBridge 143:86740a56073b 10294 #define SYSMPU_RGDAAC_M3UM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3UM_SHIFT)) & SYSMPU_RGDAAC_M3UM_MASK)
AnnaBridge 143:86740a56073b 10295 #define SYSMPU_RGDAAC_M3SM_MASK (0x600000U)
AnnaBridge 143:86740a56073b 10296 #define SYSMPU_RGDAAC_M3SM_SHIFT (21U)
AnnaBridge 143:86740a56073b 10297 #define SYSMPU_RGDAAC_M3SM(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3SM_SHIFT)) & SYSMPU_RGDAAC_M3SM_MASK)
AnnaBridge 143:86740a56073b 10298 #define SYSMPU_RGDAAC_M3PE_MASK (0x800000U)
AnnaBridge 143:86740a56073b 10299 #define SYSMPU_RGDAAC_M3PE_SHIFT (23U)
AnnaBridge 143:86740a56073b 10300 #define SYSMPU_RGDAAC_M3PE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M3PE_SHIFT)) & SYSMPU_RGDAAC_M3PE_MASK)
AnnaBridge 143:86740a56073b 10301 #define SYSMPU_RGDAAC_M4WE_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 10302 #define SYSMPU_RGDAAC_M4WE_SHIFT (24U)
AnnaBridge 143:86740a56073b 10303 #define SYSMPU_RGDAAC_M4WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4WE_SHIFT)) & SYSMPU_RGDAAC_M4WE_MASK)
AnnaBridge 143:86740a56073b 10304 #define SYSMPU_RGDAAC_M4RE_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 10305 #define SYSMPU_RGDAAC_M4RE_SHIFT (25U)
AnnaBridge 143:86740a56073b 10306 #define SYSMPU_RGDAAC_M4RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M4RE_SHIFT)) & SYSMPU_RGDAAC_M4RE_MASK)
AnnaBridge 143:86740a56073b 10307 #define SYSMPU_RGDAAC_M5WE_MASK (0x4000000U)
AnnaBridge 143:86740a56073b 10308 #define SYSMPU_RGDAAC_M5WE_SHIFT (26U)
AnnaBridge 143:86740a56073b 10309 #define SYSMPU_RGDAAC_M5WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5WE_SHIFT)) & SYSMPU_RGDAAC_M5WE_MASK)
AnnaBridge 143:86740a56073b 10310 #define SYSMPU_RGDAAC_M5RE_MASK (0x8000000U)
AnnaBridge 143:86740a56073b 10311 #define SYSMPU_RGDAAC_M5RE_SHIFT (27U)
AnnaBridge 143:86740a56073b 10312 #define SYSMPU_RGDAAC_M5RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M5RE_SHIFT)) & SYSMPU_RGDAAC_M5RE_MASK)
AnnaBridge 143:86740a56073b 10313 #define SYSMPU_RGDAAC_M6WE_MASK (0x10000000U)
AnnaBridge 143:86740a56073b 10314 #define SYSMPU_RGDAAC_M6WE_SHIFT (28U)
AnnaBridge 143:86740a56073b 10315 #define SYSMPU_RGDAAC_M6WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6WE_SHIFT)) & SYSMPU_RGDAAC_M6WE_MASK)
AnnaBridge 143:86740a56073b 10316 #define SYSMPU_RGDAAC_M6RE_MASK (0x20000000U)
AnnaBridge 143:86740a56073b 10317 #define SYSMPU_RGDAAC_M6RE_SHIFT (29U)
AnnaBridge 143:86740a56073b 10318 #define SYSMPU_RGDAAC_M6RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M6RE_SHIFT)) & SYSMPU_RGDAAC_M6RE_MASK)
AnnaBridge 143:86740a56073b 10319 #define SYSMPU_RGDAAC_M7WE_MASK (0x40000000U)
AnnaBridge 143:86740a56073b 10320 #define SYSMPU_RGDAAC_M7WE_SHIFT (30U)
AnnaBridge 143:86740a56073b 10321 #define SYSMPU_RGDAAC_M7WE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7WE_SHIFT)) & SYSMPU_RGDAAC_M7WE_MASK)
AnnaBridge 143:86740a56073b 10322 #define SYSMPU_RGDAAC_M7RE_MASK (0x80000000U)
AnnaBridge 143:86740a56073b 10323 #define SYSMPU_RGDAAC_M7RE_SHIFT (31U)
AnnaBridge 143:86740a56073b 10324 #define SYSMPU_RGDAAC_M7RE(x) (((uint32_t)(((uint32_t)(x)) << SYSMPU_RGDAAC_M7RE_SHIFT)) & SYSMPU_RGDAAC_M7RE_MASK)
AnnaBridge 143:86740a56073b 10325
AnnaBridge 143:86740a56073b 10326 /* The count of SYSMPU_RGDAAC */
AnnaBridge 143:86740a56073b 10327 #define SYSMPU_RGDAAC_COUNT (12U)
AnnaBridge 143:86740a56073b 10328
AnnaBridge 143:86740a56073b 10329
AnnaBridge 143:86740a56073b 10330 /*!
AnnaBridge 143:86740a56073b 10331 * @}
AnnaBridge 143:86740a56073b 10332 */ /* end of group SYSMPU_Register_Masks */
AnnaBridge 143:86740a56073b 10333
AnnaBridge 143:86740a56073b 10334
AnnaBridge 143:86740a56073b 10335 /* SYSMPU - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 10336 /** Peripheral SYSMPU base address */
AnnaBridge 143:86740a56073b 10337 #define SYSMPU_BASE (0x4000D000u)
AnnaBridge 143:86740a56073b 10338 /** Peripheral SYSMPU base pointer */
AnnaBridge 143:86740a56073b 10339 #define SYSMPU ((SYSMPU_Type *)SYSMPU_BASE)
AnnaBridge 143:86740a56073b 10340 /** Array initializer of SYSMPU peripheral base addresses */
AnnaBridge 143:86740a56073b 10341 #define SYSMPU_BASE_ADDRS { SYSMPU_BASE }
AnnaBridge 143:86740a56073b 10342 /** Array initializer of SYSMPU peripheral base pointers */
AnnaBridge 143:86740a56073b 10343 #define SYSMPU_BASE_PTRS { SYSMPU }
AnnaBridge 143:86740a56073b 10344
AnnaBridge 143:86740a56073b 10345 /*!
AnnaBridge 143:86740a56073b 10346 * @}
AnnaBridge 143:86740a56073b 10347 */ /* end of group SYSMPU_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 10348
AnnaBridge 143:86740a56073b 10349
AnnaBridge 143:86740a56073b 10350 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 10351 -- UART Peripheral Access Layer
AnnaBridge 143:86740a56073b 10352 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 10353
AnnaBridge 143:86740a56073b 10354 /*!
AnnaBridge 143:86740a56073b 10355 * @addtogroup UART_Peripheral_Access_Layer UART Peripheral Access Layer
AnnaBridge 143:86740a56073b 10356 * @{
AnnaBridge 143:86740a56073b 10357 */
AnnaBridge 143:86740a56073b 10358
AnnaBridge 143:86740a56073b 10359 /** UART - Register Layout Typedef */
AnnaBridge 143:86740a56073b 10360 typedef struct {
AnnaBridge 143:86740a56073b 10361 __IO uint8_t BDH; /**< UART Baud Rate Registers: High, offset: 0x0 */
AnnaBridge 143:86740a56073b 10362 __IO uint8_t BDL; /**< UART Baud Rate Registers: Low, offset: 0x1 */
AnnaBridge 143:86740a56073b 10363 __IO uint8_t C1; /**< UART Control Register 1, offset: 0x2 */
AnnaBridge 143:86740a56073b 10364 __IO uint8_t C2; /**< UART Control Register 2, offset: 0x3 */
AnnaBridge 143:86740a56073b 10365 __I uint8_t S1; /**< UART Status Register 1, offset: 0x4 */
AnnaBridge 143:86740a56073b 10366 __IO uint8_t S2; /**< UART Status Register 2, offset: 0x5 */
AnnaBridge 143:86740a56073b 10367 __IO uint8_t C3; /**< UART Control Register 3, offset: 0x6 */
AnnaBridge 143:86740a56073b 10368 __IO uint8_t D; /**< UART Data Register, offset: 0x7 */
AnnaBridge 143:86740a56073b 10369 __IO uint8_t MA1; /**< UART Match Address Registers 1, offset: 0x8 */
AnnaBridge 143:86740a56073b 10370 __IO uint8_t MA2; /**< UART Match Address Registers 2, offset: 0x9 */
AnnaBridge 143:86740a56073b 10371 __IO uint8_t C4; /**< UART Control Register 4, offset: 0xA */
AnnaBridge 143:86740a56073b 10372 __IO uint8_t C5; /**< UART Control Register 5, offset: 0xB */
AnnaBridge 143:86740a56073b 10373 __I uint8_t ED; /**< UART Extended Data Register, offset: 0xC */
AnnaBridge 143:86740a56073b 10374 __IO uint8_t MODEM; /**< UART Modem Register, offset: 0xD */
AnnaBridge 143:86740a56073b 10375 __IO uint8_t IR; /**< UART Infrared Register, offset: 0xE */
AnnaBridge 143:86740a56073b 10376 uint8_t RESERVED_0[1];
AnnaBridge 143:86740a56073b 10377 __IO uint8_t PFIFO; /**< UART FIFO Parameters, offset: 0x10 */
AnnaBridge 143:86740a56073b 10378 __IO uint8_t CFIFO; /**< UART FIFO Control Register, offset: 0x11 */
AnnaBridge 143:86740a56073b 10379 __IO uint8_t SFIFO; /**< UART FIFO Status Register, offset: 0x12 */
AnnaBridge 143:86740a56073b 10380 __IO uint8_t TWFIFO; /**< UART FIFO Transmit Watermark, offset: 0x13 */
AnnaBridge 143:86740a56073b 10381 __I uint8_t TCFIFO; /**< UART FIFO Transmit Count, offset: 0x14 */
AnnaBridge 143:86740a56073b 10382 __IO uint8_t RWFIFO; /**< UART FIFO Receive Watermark, offset: 0x15 */
AnnaBridge 143:86740a56073b 10383 __I uint8_t RCFIFO; /**< UART FIFO Receive Count, offset: 0x16 */
AnnaBridge 143:86740a56073b 10384 uint8_t RESERVED_1[1];
AnnaBridge 143:86740a56073b 10385 __IO uint8_t C7816; /**< UART 7816 Control Register, offset: 0x18 */
AnnaBridge 143:86740a56073b 10386 __IO uint8_t IE7816; /**< UART 7816 Interrupt Enable Register, offset: 0x19 */
AnnaBridge 143:86740a56073b 10387 __IO uint8_t IS7816; /**< UART 7816 Interrupt Status Register, offset: 0x1A */
AnnaBridge 143:86740a56073b 10388 union { /* offset: 0x1B */
AnnaBridge 143:86740a56073b 10389 __IO uint8_t WP7816T0; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 143:86740a56073b 10390 __IO uint8_t WP7816T1; /**< UART 7816 Wait Parameter Register, offset: 0x1B */
AnnaBridge 143:86740a56073b 10391 };
AnnaBridge 143:86740a56073b 10392 __IO uint8_t WN7816; /**< UART 7816 Wait N Register, offset: 0x1C */
AnnaBridge 143:86740a56073b 10393 __IO uint8_t WF7816; /**< UART 7816 Wait FD Register, offset: 0x1D */
AnnaBridge 143:86740a56073b 10394 __IO uint8_t ET7816; /**< UART 7816 Error Threshold Register, offset: 0x1E */
AnnaBridge 143:86740a56073b 10395 __IO uint8_t TL7816; /**< UART 7816 Transmit Length Register, offset: 0x1F */
AnnaBridge 143:86740a56073b 10396 } UART_Type;
AnnaBridge 143:86740a56073b 10397
AnnaBridge 143:86740a56073b 10398 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 10399 -- UART Register Masks
AnnaBridge 143:86740a56073b 10400 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 10401
AnnaBridge 143:86740a56073b 10402 /*!
AnnaBridge 143:86740a56073b 10403 * @addtogroup UART_Register_Masks UART Register Masks
AnnaBridge 143:86740a56073b 10404 * @{
AnnaBridge 143:86740a56073b 10405 */
AnnaBridge 143:86740a56073b 10406
AnnaBridge 143:86740a56073b 10407 /*! @name BDH - UART Baud Rate Registers: High */
AnnaBridge 143:86740a56073b 10408 #define UART_BDH_SBR_MASK (0x1FU)
AnnaBridge 143:86740a56073b 10409 #define UART_BDH_SBR_SHIFT (0U)
AnnaBridge 143:86740a56073b 10410 #define UART_BDH_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBR_SHIFT)) & UART_BDH_SBR_MASK)
AnnaBridge 143:86740a56073b 10411 #define UART_BDH_SBNS_MASK (0x20U)
AnnaBridge 143:86740a56073b 10412 #define UART_BDH_SBNS_SHIFT (5U)
AnnaBridge 143:86740a56073b 10413 #define UART_BDH_SBNS(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_SBNS_SHIFT)) & UART_BDH_SBNS_MASK)
AnnaBridge 143:86740a56073b 10414 #define UART_BDH_RXEDGIE_MASK (0x40U)
AnnaBridge 143:86740a56073b 10415 #define UART_BDH_RXEDGIE_SHIFT (6U)
AnnaBridge 143:86740a56073b 10416 #define UART_BDH_RXEDGIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_RXEDGIE_SHIFT)) & UART_BDH_RXEDGIE_MASK)
AnnaBridge 143:86740a56073b 10417 #define UART_BDH_LBKDIE_MASK (0x80U)
AnnaBridge 143:86740a56073b 10418 #define UART_BDH_LBKDIE_SHIFT (7U)
AnnaBridge 143:86740a56073b 10419 #define UART_BDH_LBKDIE(x) (((uint8_t)(((uint8_t)(x)) << UART_BDH_LBKDIE_SHIFT)) & UART_BDH_LBKDIE_MASK)
AnnaBridge 143:86740a56073b 10420
AnnaBridge 143:86740a56073b 10421 /*! @name BDL - UART Baud Rate Registers: Low */
AnnaBridge 143:86740a56073b 10422 #define UART_BDL_SBR_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10423 #define UART_BDL_SBR_SHIFT (0U)
AnnaBridge 143:86740a56073b 10424 #define UART_BDL_SBR(x) (((uint8_t)(((uint8_t)(x)) << UART_BDL_SBR_SHIFT)) & UART_BDL_SBR_MASK)
AnnaBridge 143:86740a56073b 10425
AnnaBridge 143:86740a56073b 10426 /*! @name C1 - UART Control Register 1 */
AnnaBridge 143:86740a56073b 10427 #define UART_C1_PT_MASK (0x1U)
AnnaBridge 143:86740a56073b 10428 #define UART_C1_PT_SHIFT (0U)
AnnaBridge 143:86740a56073b 10429 #define UART_C1_PT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PT_SHIFT)) & UART_C1_PT_MASK)
AnnaBridge 143:86740a56073b 10430 #define UART_C1_PE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10431 #define UART_C1_PE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10432 #define UART_C1_PE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_PE_SHIFT)) & UART_C1_PE_MASK)
AnnaBridge 143:86740a56073b 10433 #define UART_C1_ILT_MASK (0x4U)
AnnaBridge 143:86740a56073b 10434 #define UART_C1_ILT_SHIFT (2U)
AnnaBridge 143:86740a56073b 10435 #define UART_C1_ILT(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_ILT_SHIFT)) & UART_C1_ILT_MASK)
AnnaBridge 143:86740a56073b 10436 #define UART_C1_WAKE_MASK (0x8U)
AnnaBridge 143:86740a56073b 10437 #define UART_C1_WAKE_SHIFT (3U)
AnnaBridge 143:86740a56073b 10438 #define UART_C1_WAKE(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_WAKE_SHIFT)) & UART_C1_WAKE_MASK)
AnnaBridge 143:86740a56073b 10439 #define UART_C1_M_MASK (0x10U)
AnnaBridge 143:86740a56073b 10440 #define UART_C1_M_SHIFT (4U)
AnnaBridge 143:86740a56073b 10441 #define UART_C1_M(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_M_SHIFT)) & UART_C1_M_MASK)
AnnaBridge 143:86740a56073b 10442 #define UART_C1_RSRC_MASK (0x20U)
AnnaBridge 143:86740a56073b 10443 #define UART_C1_RSRC_SHIFT (5U)
AnnaBridge 143:86740a56073b 10444 #define UART_C1_RSRC(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_RSRC_SHIFT)) & UART_C1_RSRC_MASK)
AnnaBridge 143:86740a56073b 10445 #define UART_C1_UARTSWAI_MASK (0x40U)
AnnaBridge 143:86740a56073b 10446 #define UART_C1_UARTSWAI_SHIFT (6U)
AnnaBridge 143:86740a56073b 10447 #define UART_C1_UARTSWAI(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_UARTSWAI_SHIFT)) & UART_C1_UARTSWAI_MASK)
AnnaBridge 143:86740a56073b 10448 #define UART_C1_LOOPS_MASK (0x80U)
AnnaBridge 143:86740a56073b 10449 #define UART_C1_LOOPS_SHIFT (7U)
AnnaBridge 143:86740a56073b 10450 #define UART_C1_LOOPS(x) (((uint8_t)(((uint8_t)(x)) << UART_C1_LOOPS_SHIFT)) & UART_C1_LOOPS_MASK)
AnnaBridge 143:86740a56073b 10451
AnnaBridge 143:86740a56073b 10452 /*! @name C2 - UART Control Register 2 */
AnnaBridge 143:86740a56073b 10453 #define UART_C2_SBK_MASK (0x1U)
AnnaBridge 143:86740a56073b 10454 #define UART_C2_SBK_SHIFT (0U)
AnnaBridge 143:86740a56073b 10455 #define UART_C2_SBK(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_SBK_SHIFT)) & UART_C2_SBK_MASK)
AnnaBridge 143:86740a56073b 10456 #define UART_C2_RWU_MASK (0x2U)
AnnaBridge 143:86740a56073b 10457 #define UART_C2_RWU_SHIFT (1U)
AnnaBridge 143:86740a56073b 10458 #define UART_C2_RWU(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RWU_SHIFT)) & UART_C2_RWU_MASK)
AnnaBridge 143:86740a56073b 10459 #define UART_C2_RE_MASK (0x4U)
AnnaBridge 143:86740a56073b 10460 #define UART_C2_RE_SHIFT (2U)
AnnaBridge 143:86740a56073b 10461 #define UART_C2_RE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RE_SHIFT)) & UART_C2_RE_MASK)
AnnaBridge 143:86740a56073b 10462 #define UART_C2_TE_MASK (0x8U)
AnnaBridge 143:86740a56073b 10463 #define UART_C2_TE_SHIFT (3U)
AnnaBridge 143:86740a56073b 10464 #define UART_C2_TE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TE_SHIFT)) & UART_C2_TE_MASK)
AnnaBridge 143:86740a56073b 10465 #define UART_C2_ILIE_MASK (0x10U)
AnnaBridge 143:86740a56073b 10466 #define UART_C2_ILIE_SHIFT (4U)
AnnaBridge 143:86740a56073b 10467 #define UART_C2_ILIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_ILIE_SHIFT)) & UART_C2_ILIE_MASK)
AnnaBridge 143:86740a56073b 10468 #define UART_C2_RIE_MASK (0x20U)
AnnaBridge 143:86740a56073b 10469 #define UART_C2_RIE_SHIFT (5U)
AnnaBridge 143:86740a56073b 10470 #define UART_C2_RIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_RIE_SHIFT)) & UART_C2_RIE_MASK)
AnnaBridge 143:86740a56073b 10471 #define UART_C2_TCIE_MASK (0x40U)
AnnaBridge 143:86740a56073b 10472 #define UART_C2_TCIE_SHIFT (6U)
AnnaBridge 143:86740a56073b 10473 #define UART_C2_TCIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TCIE_SHIFT)) & UART_C2_TCIE_MASK)
AnnaBridge 143:86740a56073b 10474 #define UART_C2_TIE_MASK (0x80U)
AnnaBridge 143:86740a56073b 10475 #define UART_C2_TIE_SHIFT (7U)
AnnaBridge 143:86740a56073b 10476 #define UART_C2_TIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C2_TIE_SHIFT)) & UART_C2_TIE_MASK)
AnnaBridge 143:86740a56073b 10477
AnnaBridge 143:86740a56073b 10478 /*! @name S1 - UART Status Register 1 */
AnnaBridge 143:86740a56073b 10479 #define UART_S1_PF_MASK (0x1U)
AnnaBridge 143:86740a56073b 10480 #define UART_S1_PF_SHIFT (0U)
AnnaBridge 143:86740a56073b 10481 #define UART_S1_PF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_PF_SHIFT)) & UART_S1_PF_MASK)
AnnaBridge 143:86740a56073b 10482 #define UART_S1_FE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10483 #define UART_S1_FE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10484 #define UART_S1_FE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_FE_SHIFT)) & UART_S1_FE_MASK)
AnnaBridge 143:86740a56073b 10485 #define UART_S1_NF_MASK (0x4U)
AnnaBridge 143:86740a56073b 10486 #define UART_S1_NF_SHIFT (2U)
AnnaBridge 143:86740a56073b 10487 #define UART_S1_NF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_NF_SHIFT)) & UART_S1_NF_MASK)
AnnaBridge 143:86740a56073b 10488 #define UART_S1_OR_MASK (0x8U)
AnnaBridge 143:86740a56073b 10489 #define UART_S1_OR_SHIFT (3U)
AnnaBridge 143:86740a56073b 10490 #define UART_S1_OR(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_OR_SHIFT)) & UART_S1_OR_MASK)
AnnaBridge 143:86740a56073b 10491 #define UART_S1_IDLE_MASK (0x10U)
AnnaBridge 143:86740a56073b 10492 #define UART_S1_IDLE_SHIFT (4U)
AnnaBridge 143:86740a56073b 10493 #define UART_S1_IDLE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_IDLE_SHIFT)) & UART_S1_IDLE_MASK)
AnnaBridge 143:86740a56073b 10494 #define UART_S1_RDRF_MASK (0x20U)
AnnaBridge 143:86740a56073b 10495 #define UART_S1_RDRF_SHIFT (5U)
AnnaBridge 143:86740a56073b 10496 #define UART_S1_RDRF(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_RDRF_SHIFT)) & UART_S1_RDRF_MASK)
AnnaBridge 143:86740a56073b 10497 #define UART_S1_TC_MASK (0x40U)
AnnaBridge 143:86740a56073b 10498 #define UART_S1_TC_SHIFT (6U)
AnnaBridge 143:86740a56073b 10499 #define UART_S1_TC(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TC_SHIFT)) & UART_S1_TC_MASK)
AnnaBridge 143:86740a56073b 10500 #define UART_S1_TDRE_MASK (0x80U)
AnnaBridge 143:86740a56073b 10501 #define UART_S1_TDRE_SHIFT (7U)
AnnaBridge 143:86740a56073b 10502 #define UART_S1_TDRE(x) (((uint8_t)(((uint8_t)(x)) << UART_S1_TDRE_SHIFT)) & UART_S1_TDRE_MASK)
AnnaBridge 143:86740a56073b 10503
AnnaBridge 143:86740a56073b 10504 /*! @name S2 - UART Status Register 2 */
AnnaBridge 143:86740a56073b 10505 #define UART_S2_RAF_MASK (0x1U)
AnnaBridge 143:86740a56073b 10506 #define UART_S2_RAF_SHIFT (0U)
AnnaBridge 143:86740a56073b 10507 #define UART_S2_RAF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RAF_SHIFT)) & UART_S2_RAF_MASK)
AnnaBridge 143:86740a56073b 10508 #define UART_S2_LBKDE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10509 #define UART_S2_LBKDE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10510 #define UART_S2_LBKDE(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDE_SHIFT)) & UART_S2_LBKDE_MASK)
AnnaBridge 143:86740a56073b 10511 #define UART_S2_BRK13_MASK (0x4U)
AnnaBridge 143:86740a56073b 10512 #define UART_S2_BRK13_SHIFT (2U)
AnnaBridge 143:86740a56073b 10513 #define UART_S2_BRK13(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_BRK13_SHIFT)) & UART_S2_BRK13_MASK)
AnnaBridge 143:86740a56073b 10514 #define UART_S2_RWUID_MASK (0x8U)
AnnaBridge 143:86740a56073b 10515 #define UART_S2_RWUID_SHIFT (3U)
AnnaBridge 143:86740a56073b 10516 #define UART_S2_RWUID(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RWUID_SHIFT)) & UART_S2_RWUID_MASK)
AnnaBridge 143:86740a56073b 10517 #define UART_S2_RXINV_MASK (0x10U)
AnnaBridge 143:86740a56073b 10518 #define UART_S2_RXINV_SHIFT (4U)
AnnaBridge 143:86740a56073b 10519 #define UART_S2_RXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXINV_SHIFT)) & UART_S2_RXINV_MASK)
AnnaBridge 143:86740a56073b 10520 #define UART_S2_MSBF_MASK (0x20U)
AnnaBridge 143:86740a56073b 10521 #define UART_S2_MSBF_SHIFT (5U)
AnnaBridge 143:86740a56073b 10522 #define UART_S2_MSBF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_MSBF_SHIFT)) & UART_S2_MSBF_MASK)
AnnaBridge 143:86740a56073b 10523 #define UART_S2_RXEDGIF_MASK (0x40U)
AnnaBridge 143:86740a56073b 10524 #define UART_S2_RXEDGIF_SHIFT (6U)
AnnaBridge 143:86740a56073b 10525 #define UART_S2_RXEDGIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_RXEDGIF_SHIFT)) & UART_S2_RXEDGIF_MASK)
AnnaBridge 143:86740a56073b 10526 #define UART_S2_LBKDIF_MASK (0x80U)
AnnaBridge 143:86740a56073b 10527 #define UART_S2_LBKDIF_SHIFT (7U)
AnnaBridge 143:86740a56073b 10528 #define UART_S2_LBKDIF(x) (((uint8_t)(((uint8_t)(x)) << UART_S2_LBKDIF_SHIFT)) & UART_S2_LBKDIF_MASK)
AnnaBridge 143:86740a56073b 10529
AnnaBridge 143:86740a56073b 10530 /*! @name C3 - UART Control Register 3 */
AnnaBridge 143:86740a56073b 10531 #define UART_C3_PEIE_MASK (0x1U)
AnnaBridge 143:86740a56073b 10532 #define UART_C3_PEIE_SHIFT (0U)
AnnaBridge 143:86740a56073b 10533 #define UART_C3_PEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_PEIE_SHIFT)) & UART_C3_PEIE_MASK)
AnnaBridge 143:86740a56073b 10534 #define UART_C3_FEIE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10535 #define UART_C3_FEIE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10536 #define UART_C3_FEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_FEIE_SHIFT)) & UART_C3_FEIE_MASK)
AnnaBridge 143:86740a56073b 10537 #define UART_C3_NEIE_MASK (0x4U)
AnnaBridge 143:86740a56073b 10538 #define UART_C3_NEIE_SHIFT (2U)
AnnaBridge 143:86740a56073b 10539 #define UART_C3_NEIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_NEIE_SHIFT)) & UART_C3_NEIE_MASK)
AnnaBridge 143:86740a56073b 10540 #define UART_C3_ORIE_MASK (0x8U)
AnnaBridge 143:86740a56073b 10541 #define UART_C3_ORIE_SHIFT (3U)
AnnaBridge 143:86740a56073b 10542 #define UART_C3_ORIE(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_ORIE_SHIFT)) & UART_C3_ORIE_MASK)
AnnaBridge 143:86740a56073b 10543 #define UART_C3_TXINV_MASK (0x10U)
AnnaBridge 143:86740a56073b 10544 #define UART_C3_TXINV_SHIFT (4U)
AnnaBridge 143:86740a56073b 10545 #define UART_C3_TXINV(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXINV_SHIFT)) & UART_C3_TXINV_MASK)
AnnaBridge 143:86740a56073b 10546 #define UART_C3_TXDIR_MASK (0x20U)
AnnaBridge 143:86740a56073b 10547 #define UART_C3_TXDIR_SHIFT (5U)
AnnaBridge 143:86740a56073b 10548 #define UART_C3_TXDIR(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_TXDIR_SHIFT)) & UART_C3_TXDIR_MASK)
AnnaBridge 143:86740a56073b 10549 #define UART_C3_T8_MASK (0x40U)
AnnaBridge 143:86740a56073b 10550 #define UART_C3_T8_SHIFT (6U)
AnnaBridge 143:86740a56073b 10551 #define UART_C3_T8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_T8_SHIFT)) & UART_C3_T8_MASK)
AnnaBridge 143:86740a56073b 10552 #define UART_C3_R8_MASK (0x80U)
AnnaBridge 143:86740a56073b 10553 #define UART_C3_R8_SHIFT (7U)
AnnaBridge 143:86740a56073b 10554 #define UART_C3_R8(x) (((uint8_t)(((uint8_t)(x)) << UART_C3_R8_SHIFT)) & UART_C3_R8_MASK)
AnnaBridge 143:86740a56073b 10555
AnnaBridge 143:86740a56073b 10556 /*! @name D - UART Data Register */
AnnaBridge 143:86740a56073b 10557 #define UART_D_RT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10558 #define UART_D_RT_SHIFT (0U)
AnnaBridge 143:86740a56073b 10559 #define UART_D_RT(x) (((uint8_t)(((uint8_t)(x)) << UART_D_RT_SHIFT)) & UART_D_RT_MASK)
AnnaBridge 143:86740a56073b 10560
AnnaBridge 143:86740a56073b 10561 /*! @name MA1 - UART Match Address Registers 1 */
AnnaBridge 143:86740a56073b 10562 #define UART_MA1_MA_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10563 #define UART_MA1_MA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10564 #define UART_MA1_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA1_MA_SHIFT)) & UART_MA1_MA_MASK)
AnnaBridge 143:86740a56073b 10565
AnnaBridge 143:86740a56073b 10566 /*! @name MA2 - UART Match Address Registers 2 */
AnnaBridge 143:86740a56073b 10567 #define UART_MA2_MA_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10568 #define UART_MA2_MA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10569 #define UART_MA2_MA(x) (((uint8_t)(((uint8_t)(x)) << UART_MA2_MA_SHIFT)) & UART_MA2_MA_MASK)
AnnaBridge 143:86740a56073b 10570
AnnaBridge 143:86740a56073b 10571 /*! @name C4 - UART Control Register 4 */
AnnaBridge 143:86740a56073b 10572 #define UART_C4_BRFA_MASK (0x1FU)
AnnaBridge 143:86740a56073b 10573 #define UART_C4_BRFA_SHIFT (0U)
AnnaBridge 143:86740a56073b 10574 #define UART_C4_BRFA(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_BRFA_SHIFT)) & UART_C4_BRFA_MASK)
AnnaBridge 143:86740a56073b 10575 #define UART_C4_M10_MASK (0x20U)
AnnaBridge 143:86740a56073b 10576 #define UART_C4_M10_SHIFT (5U)
AnnaBridge 143:86740a56073b 10577 #define UART_C4_M10(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_M10_SHIFT)) & UART_C4_M10_MASK)
AnnaBridge 143:86740a56073b 10578 #define UART_C4_MAEN2_MASK (0x40U)
AnnaBridge 143:86740a56073b 10579 #define UART_C4_MAEN2_SHIFT (6U)
AnnaBridge 143:86740a56073b 10580 #define UART_C4_MAEN2(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN2_SHIFT)) & UART_C4_MAEN2_MASK)
AnnaBridge 143:86740a56073b 10581 #define UART_C4_MAEN1_MASK (0x80U)
AnnaBridge 143:86740a56073b 10582 #define UART_C4_MAEN1_SHIFT (7U)
AnnaBridge 143:86740a56073b 10583 #define UART_C4_MAEN1(x) (((uint8_t)(((uint8_t)(x)) << UART_C4_MAEN1_SHIFT)) & UART_C4_MAEN1_MASK)
AnnaBridge 143:86740a56073b 10584
AnnaBridge 143:86740a56073b 10585 /*! @name C5 - UART Control Register 5 */
AnnaBridge 143:86740a56073b 10586 #define UART_C5_LBKDDMAS_MASK (0x8U)
AnnaBridge 143:86740a56073b 10587 #define UART_C5_LBKDDMAS_SHIFT (3U)
AnnaBridge 143:86740a56073b 10588 #define UART_C5_LBKDDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_LBKDDMAS_SHIFT)) & UART_C5_LBKDDMAS_MASK)
AnnaBridge 143:86740a56073b 10589 #define UART_C5_ILDMAS_MASK (0x10U)
AnnaBridge 143:86740a56073b 10590 #define UART_C5_ILDMAS_SHIFT (4U)
AnnaBridge 143:86740a56073b 10591 #define UART_C5_ILDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_ILDMAS_SHIFT)) & UART_C5_ILDMAS_MASK)
AnnaBridge 143:86740a56073b 10592 #define UART_C5_RDMAS_MASK (0x20U)
AnnaBridge 143:86740a56073b 10593 #define UART_C5_RDMAS_SHIFT (5U)
AnnaBridge 143:86740a56073b 10594 #define UART_C5_RDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_RDMAS_SHIFT)) & UART_C5_RDMAS_MASK)
AnnaBridge 143:86740a56073b 10595 #define UART_C5_TCDMAS_MASK (0x40U)
AnnaBridge 143:86740a56073b 10596 #define UART_C5_TCDMAS_SHIFT (6U)
AnnaBridge 143:86740a56073b 10597 #define UART_C5_TCDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TCDMAS_SHIFT)) & UART_C5_TCDMAS_MASK)
AnnaBridge 143:86740a56073b 10598 #define UART_C5_TDMAS_MASK (0x80U)
AnnaBridge 143:86740a56073b 10599 #define UART_C5_TDMAS_SHIFT (7U)
AnnaBridge 143:86740a56073b 10600 #define UART_C5_TDMAS(x) (((uint8_t)(((uint8_t)(x)) << UART_C5_TDMAS_SHIFT)) & UART_C5_TDMAS_MASK)
AnnaBridge 143:86740a56073b 10601
AnnaBridge 143:86740a56073b 10602 /*! @name ED - UART Extended Data Register */
AnnaBridge 143:86740a56073b 10603 #define UART_ED_PARITYE_MASK (0x40U)
AnnaBridge 143:86740a56073b 10604 #define UART_ED_PARITYE_SHIFT (6U)
AnnaBridge 143:86740a56073b 10605 #define UART_ED_PARITYE(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_PARITYE_SHIFT)) & UART_ED_PARITYE_MASK)
AnnaBridge 143:86740a56073b 10606 #define UART_ED_NOISY_MASK (0x80U)
AnnaBridge 143:86740a56073b 10607 #define UART_ED_NOISY_SHIFT (7U)
AnnaBridge 143:86740a56073b 10608 #define UART_ED_NOISY(x) (((uint8_t)(((uint8_t)(x)) << UART_ED_NOISY_SHIFT)) & UART_ED_NOISY_MASK)
AnnaBridge 143:86740a56073b 10609
AnnaBridge 143:86740a56073b 10610 /*! @name MODEM - UART Modem Register */
AnnaBridge 143:86740a56073b 10611 #define UART_MODEM_TXCTSE_MASK (0x1U)
AnnaBridge 143:86740a56073b 10612 #define UART_MODEM_TXCTSE_SHIFT (0U)
AnnaBridge 143:86740a56073b 10613 #define UART_MODEM_TXCTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXCTSE_SHIFT)) & UART_MODEM_TXCTSE_MASK)
AnnaBridge 143:86740a56073b 10614 #define UART_MODEM_TXRTSE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10615 #define UART_MODEM_TXRTSE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10616 #define UART_MODEM_TXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSE_SHIFT)) & UART_MODEM_TXRTSE_MASK)
AnnaBridge 143:86740a56073b 10617 #define UART_MODEM_TXRTSPOL_MASK (0x4U)
AnnaBridge 143:86740a56073b 10618 #define UART_MODEM_TXRTSPOL_SHIFT (2U)
AnnaBridge 143:86740a56073b 10619 #define UART_MODEM_TXRTSPOL(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_TXRTSPOL_SHIFT)) & UART_MODEM_TXRTSPOL_MASK)
AnnaBridge 143:86740a56073b 10620 #define UART_MODEM_RXRTSE_MASK (0x8U)
AnnaBridge 143:86740a56073b 10621 #define UART_MODEM_RXRTSE_SHIFT (3U)
AnnaBridge 143:86740a56073b 10622 #define UART_MODEM_RXRTSE(x) (((uint8_t)(((uint8_t)(x)) << UART_MODEM_RXRTSE_SHIFT)) & UART_MODEM_RXRTSE_MASK)
AnnaBridge 143:86740a56073b 10623
AnnaBridge 143:86740a56073b 10624 /*! @name IR - UART Infrared Register */
AnnaBridge 143:86740a56073b 10625 #define UART_IR_TNP_MASK (0x3U)
AnnaBridge 143:86740a56073b 10626 #define UART_IR_TNP_SHIFT (0U)
AnnaBridge 143:86740a56073b 10627 #define UART_IR_TNP(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_TNP_SHIFT)) & UART_IR_TNP_MASK)
AnnaBridge 143:86740a56073b 10628 #define UART_IR_IREN_MASK (0x4U)
AnnaBridge 143:86740a56073b 10629 #define UART_IR_IREN_SHIFT (2U)
AnnaBridge 143:86740a56073b 10630 #define UART_IR_IREN(x) (((uint8_t)(((uint8_t)(x)) << UART_IR_IREN_SHIFT)) & UART_IR_IREN_MASK)
AnnaBridge 143:86740a56073b 10631
AnnaBridge 143:86740a56073b 10632 /*! @name PFIFO - UART FIFO Parameters */
AnnaBridge 143:86740a56073b 10633 #define UART_PFIFO_RXFIFOSIZE_MASK (0x7U)
AnnaBridge 143:86740a56073b 10634 #define UART_PFIFO_RXFIFOSIZE_SHIFT (0U)
AnnaBridge 143:86740a56073b 10635 #define UART_PFIFO_RXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFIFOSIZE_SHIFT)) & UART_PFIFO_RXFIFOSIZE_MASK)
AnnaBridge 143:86740a56073b 10636 #define UART_PFIFO_RXFE_MASK (0x8U)
AnnaBridge 143:86740a56073b 10637 #define UART_PFIFO_RXFE_SHIFT (3U)
AnnaBridge 143:86740a56073b 10638 #define UART_PFIFO_RXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_RXFE_SHIFT)) & UART_PFIFO_RXFE_MASK)
AnnaBridge 143:86740a56073b 10639 #define UART_PFIFO_TXFIFOSIZE_MASK (0x70U)
AnnaBridge 143:86740a56073b 10640 #define UART_PFIFO_TXFIFOSIZE_SHIFT (4U)
AnnaBridge 143:86740a56073b 10641 #define UART_PFIFO_TXFIFOSIZE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFIFOSIZE_SHIFT)) & UART_PFIFO_TXFIFOSIZE_MASK)
AnnaBridge 143:86740a56073b 10642 #define UART_PFIFO_TXFE_MASK (0x80U)
AnnaBridge 143:86740a56073b 10643 #define UART_PFIFO_TXFE_SHIFT (7U)
AnnaBridge 143:86740a56073b 10644 #define UART_PFIFO_TXFE(x) (((uint8_t)(((uint8_t)(x)) << UART_PFIFO_TXFE_SHIFT)) & UART_PFIFO_TXFE_MASK)
AnnaBridge 143:86740a56073b 10645
AnnaBridge 143:86740a56073b 10646 /*! @name CFIFO - UART FIFO Control Register */
AnnaBridge 143:86740a56073b 10647 #define UART_CFIFO_RXUFE_MASK (0x1U)
AnnaBridge 143:86740a56073b 10648 #define UART_CFIFO_RXUFE_SHIFT (0U)
AnnaBridge 143:86740a56073b 10649 #define UART_CFIFO_RXUFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXUFE_SHIFT)) & UART_CFIFO_RXUFE_MASK)
AnnaBridge 143:86740a56073b 10650 #define UART_CFIFO_TXOFE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10651 #define UART_CFIFO_TXOFE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10652 #define UART_CFIFO_TXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXOFE_SHIFT)) & UART_CFIFO_TXOFE_MASK)
AnnaBridge 143:86740a56073b 10653 #define UART_CFIFO_RXOFE_MASK (0x4U)
AnnaBridge 143:86740a56073b 10654 #define UART_CFIFO_RXOFE_SHIFT (2U)
AnnaBridge 143:86740a56073b 10655 #define UART_CFIFO_RXOFE(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXOFE_SHIFT)) & UART_CFIFO_RXOFE_MASK)
AnnaBridge 143:86740a56073b 10656 #define UART_CFIFO_RXFLUSH_MASK (0x40U)
AnnaBridge 143:86740a56073b 10657 #define UART_CFIFO_RXFLUSH_SHIFT (6U)
AnnaBridge 143:86740a56073b 10658 #define UART_CFIFO_RXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_RXFLUSH_SHIFT)) & UART_CFIFO_RXFLUSH_MASK)
AnnaBridge 143:86740a56073b 10659 #define UART_CFIFO_TXFLUSH_MASK (0x80U)
AnnaBridge 143:86740a56073b 10660 #define UART_CFIFO_TXFLUSH_SHIFT (7U)
AnnaBridge 143:86740a56073b 10661 #define UART_CFIFO_TXFLUSH(x) (((uint8_t)(((uint8_t)(x)) << UART_CFIFO_TXFLUSH_SHIFT)) & UART_CFIFO_TXFLUSH_MASK)
AnnaBridge 143:86740a56073b 10662
AnnaBridge 143:86740a56073b 10663 /*! @name SFIFO - UART FIFO Status Register */
AnnaBridge 143:86740a56073b 10664 #define UART_SFIFO_RXUF_MASK (0x1U)
AnnaBridge 143:86740a56073b 10665 #define UART_SFIFO_RXUF_SHIFT (0U)
AnnaBridge 143:86740a56073b 10666 #define UART_SFIFO_RXUF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXUF_SHIFT)) & UART_SFIFO_RXUF_MASK)
AnnaBridge 143:86740a56073b 10667 #define UART_SFIFO_TXOF_MASK (0x2U)
AnnaBridge 143:86740a56073b 10668 #define UART_SFIFO_TXOF_SHIFT (1U)
AnnaBridge 143:86740a56073b 10669 #define UART_SFIFO_TXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXOF_SHIFT)) & UART_SFIFO_TXOF_MASK)
AnnaBridge 143:86740a56073b 10670 #define UART_SFIFO_RXOF_MASK (0x4U)
AnnaBridge 143:86740a56073b 10671 #define UART_SFIFO_RXOF_SHIFT (2U)
AnnaBridge 143:86740a56073b 10672 #define UART_SFIFO_RXOF(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXOF_SHIFT)) & UART_SFIFO_RXOF_MASK)
AnnaBridge 143:86740a56073b 10673 #define UART_SFIFO_RXEMPT_MASK (0x40U)
AnnaBridge 143:86740a56073b 10674 #define UART_SFIFO_RXEMPT_SHIFT (6U)
AnnaBridge 143:86740a56073b 10675 #define UART_SFIFO_RXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_RXEMPT_SHIFT)) & UART_SFIFO_RXEMPT_MASK)
AnnaBridge 143:86740a56073b 10676 #define UART_SFIFO_TXEMPT_MASK (0x80U)
AnnaBridge 143:86740a56073b 10677 #define UART_SFIFO_TXEMPT_SHIFT (7U)
AnnaBridge 143:86740a56073b 10678 #define UART_SFIFO_TXEMPT(x) (((uint8_t)(((uint8_t)(x)) << UART_SFIFO_TXEMPT_SHIFT)) & UART_SFIFO_TXEMPT_MASK)
AnnaBridge 143:86740a56073b 10679
AnnaBridge 143:86740a56073b 10680 /*! @name TWFIFO - UART FIFO Transmit Watermark */
AnnaBridge 143:86740a56073b 10681 #define UART_TWFIFO_TXWATER_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10682 #define UART_TWFIFO_TXWATER_SHIFT (0U)
AnnaBridge 143:86740a56073b 10683 #define UART_TWFIFO_TXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_TWFIFO_TXWATER_SHIFT)) & UART_TWFIFO_TXWATER_MASK)
AnnaBridge 143:86740a56073b 10684
AnnaBridge 143:86740a56073b 10685 /*! @name TCFIFO - UART FIFO Transmit Count */
AnnaBridge 143:86740a56073b 10686 #define UART_TCFIFO_TXCOUNT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10687 #define UART_TCFIFO_TXCOUNT_SHIFT (0U)
AnnaBridge 143:86740a56073b 10688 #define UART_TCFIFO_TXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_TCFIFO_TXCOUNT_SHIFT)) & UART_TCFIFO_TXCOUNT_MASK)
AnnaBridge 143:86740a56073b 10689
AnnaBridge 143:86740a56073b 10690 /*! @name RWFIFO - UART FIFO Receive Watermark */
AnnaBridge 143:86740a56073b 10691 #define UART_RWFIFO_RXWATER_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10692 #define UART_RWFIFO_RXWATER_SHIFT (0U)
AnnaBridge 143:86740a56073b 10693 #define UART_RWFIFO_RXWATER(x) (((uint8_t)(((uint8_t)(x)) << UART_RWFIFO_RXWATER_SHIFT)) & UART_RWFIFO_RXWATER_MASK)
AnnaBridge 143:86740a56073b 10694
AnnaBridge 143:86740a56073b 10695 /*! @name RCFIFO - UART FIFO Receive Count */
AnnaBridge 143:86740a56073b 10696 #define UART_RCFIFO_RXCOUNT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10697 #define UART_RCFIFO_RXCOUNT_SHIFT (0U)
AnnaBridge 143:86740a56073b 10698 #define UART_RCFIFO_RXCOUNT(x) (((uint8_t)(((uint8_t)(x)) << UART_RCFIFO_RXCOUNT_SHIFT)) & UART_RCFIFO_RXCOUNT_MASK)
AnnaBridge 143:86740a56073b 10699
AnnaBridge 143:86740a56073b 10700 /*! @name C7816 - UART 7816 Control Register */
AnnaBridge 143:86740a56073b 10701 #define UART_C7816_ISO_7816E_MASK (0x1U)
AnnaBridge 143:86740a56073b 10702 #define UART_C7816_ISO_7816E_SHIFT (0U)
AnnaBridge 143:86740a56073b 10703 #define UART_C7816_ISO_7816E(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ISO_7816E_SHIFT)) & UART_C7816_ISO_7816E_MASK)
AnnaBridge 143:86740a56073b 10704 #define UART_C7816_TTYPE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10705 #define UART_C7816_TTYPE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10706 #define UART_C7816_TTYPE(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_TTYPE_SHIFT)) & UART_C7816_TTYPE_MASK)
AnnaBridge 143:86740a56073b 10707 #define UART_C7816_INIT_MASK (0x4U)
AnnaBridge 143:86740a56073b 10708 #define UART_C7816_INIT_SHIFT (2U)
AnnaBridge 143:86740a56073b 10709 #define UART_C7816_INIT(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_INIT_SHIFT)) & UART_C7816_INIT_MASK)
AnnaBridge 143:86740a56073b 10710 #define UART_C7816_ANACK_MASK (0x8U)
AnnaBridge 143:86740a56073b 10711 #define UART_C7816_ANACK_SHIFT (3U)
AnnaBridge 143:86740a56073b 10712 #define UART_C7816_ANACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ANACK_SHIFT)) & UART_C7816_ANACK_MASK)
AnnaBridge 143:86740a56073b 10713 #define UART_C7816_ONACK_MASK (0x10U)
AnnaBridge 143:86740a56073b 10714 #define UART_C7816_ONACK_SHIFT (4U)
AnnaBridge 143:86740a56073b 10715 #define UART_C7816_ONACK(x) (((uint8_t)(((uint8_t)(x)) << UART_C7816_ONACK_SHIFT)) & UART_C7816_ONACK_MASK)
AnnaBridge 143:86740a56073b 10716
AnnaBridge 143:86740a56073b 10717 /*! @name IE7816 - UART 7816 Interrupt Enable Register */
AnnaBridge 143:86740a56073b 10718 #define UART_IE7816_RXTE_MASK (0x1U)
AnnaBridge 143:86740a56073b 10719 #define UART_IE7816_RXTE_SHIFT (0U)
AnnaBridge 143:86740a56073b 10720 #define UART_IE7816_RXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_RXTE_SHIFT)) & UART_IE7816_RXTE_MASK)
AnnaBridge 143:86740a56073b 10721 #define UART_IE7816_TXTE_MASK (0x2U)
AnnaBridge 143:86740a56073b 10722 #define UART_IE7816_TXTE_SHIFT (1U)
AnnaBridge 143:86740a56073b 10723 #define UART_IE7816_TXTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_TXTE_SHIFT)) & UART_IE7816_TXTE_MASK)
AnnaBridge 143:86740a56073b 10724 #define UART_IE7816_GTVE_MASK (0x4U)
AnnaBridge 143:86740a56073b 10725 #define UART_IE7816_GTVE_SHIFT (2U)
AnnaBridge 143:86740a56073b 10726 #define UART_IE7816_GTVE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_GTVE_SHIFT)) & UART_IE7816_GTVE_MASK)
AnnaBridge 143:86740a56073b 10727 #define UART_IE7816_INITDE_MASK (0x10U)
AnnaBridge 143:86740a56073b 10728 #define UART_IE7816_INITDE_SHIFT (4U)
AnnaBridge 143:86740a56073b 10729 #define UART_IE7816_INITDE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_INITDE_SHIFT)) & UART_IE7816_INITDE_MASK)
AnnaBridge 143:86740a56073b 10730 #define UART_IE7816_BWTE_MASK (0x20U)
AnnaBridge 143:86740a56073b 10731 #define UART_IE7816_BWTE_SHIFT (5U)
AnnaBridge 143:86740a56073b 10732 #define UART_IE7816_BWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_BWTE_SHIFT)) & UART_IE7816_BWTE_MASK)
AnnaBridge 143:86740a56073b 10733 #define UART_IE7816_CWTE_MASK (0x40U)
AnnaBridge 143:86740a56073b 10734 #define UART_IE7816_CWTE_SHIFT (6U)
AnnaBridge 143:86740a56073b 10735 #define UART_IE7816_CWTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_CWTE_SHIFT)) & UART_IE7816_CWTE_MASK)
AnnaBridge 143:86740a56073b 10736 #define UART_IE7816_WTE_MASK (0x80U)
AnnaBridge 143:86740a56073b 10737 #define UART_IE7816_WTE_SHIFT (7U)
AnnaBridge 143:86740a56073b 10738 #define UART_IE7816_WTE(x) (((uint8_t)(((uint8_t)(x)) << UART_IE7816_WTE_SHIFT)) & UART_IE7816_WTE_MASK)
AnnaBridge 143:86740a56073b 10739
AnnaBridge 143:86740a56073b 10740 /*! @name IS7816 - UART 7816 Interrupt Status Register */
AnnaBridge 143:86740a56073b 10741 #define UART_IS7816_RXT_MASK (0x1U)
AnnaBridge 143:86740a56073b 10742 #define UART_IS7816_RXT_SHIFT (0U)
AnnaBridge 143:86740a56073b 10743 #define UART_IS7816_RXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_RXT_SHIFT)) & UART_IS7816_RXT_MASK)
AnnaBridge 143:86740a56073b 10744 #define UART_IS7816_TXT_MASK (0x2U)
AnnaBridge 143:86740a56073b 10745 #define UART_IS7816_TXT_SHIFT (1U)
AnnaBridge 143:86740a56073b 10746 #define UART_IS7816_TXT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_TXT_SHIFT)) & UART_IS7816_TXT_MASK)
AnnaBridge 143:86740a56073b 10747 #define UART_IS7816_GTV_MASK (0x4U)
AnnaBridge 143:86740a56073b 10748 #define UART_IS7816_GTV_SHIFT (2U)
AnnaBridge 143:86740a56073b 10749 #define UART_IS7816_GTV(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_GTV_SHIFT)) & UART_IS7816_GTV_MASK)
AnnaBridge 143:86740a56073b 10750 #define UART_IS7816_INITD_MASK (0x10U)
AnnaBridge 143:86740a56073b 10751 #define UART_IS7816_INITD_SHIFT (4U)
AnnaBridge 143:86740a56073b 10752 #define UART_IS7816_INITD(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_INITD_SHIFT)) & UART_IS7816_INITD_MASK)
AnnaBridge 143:86740a56073b 10753 #define UART_IS7816_BWT_MASK (0x20U)
AnnaBridge 143:86740a56073b 10754 #define UART_IS7816_BWT_SHIFT (5U)
AnnaBridge 143:86740a56073b 10755 #define UART_IS7816_BWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_BWT_SHIFT)) & UART_IS7816_BWT_MASK)
AnnaBridge 143:86740a56073b 10756 #define UART_IS7816_CWT_MASK (0x40U)
AnnaBridge 143:86740a56073b 10757 #define UART_IS7816_CWT_SHIFT (6U)
AnnaBridge 143:86740a56073b 10758 #define UART_IS7816_CWT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_CWT_SHIFT)) & UART_IS7816_CWT_MASK)
AnnaBridge 143:86740a56073b 10759 #define UART_IS7816_WT_MASK (0x80U)
AnnaBridge 143:86740a56073b 10760 #define UART_IS7816_WT_SHIFT (7U)
AnnaBridge 143:86740a56073b 10761 #define UART_IS7816_WT(x) (((uint8_t)(((uint8_t)(x)) << UART_IS7816_WT_SHIFT)) & UART_IS7816_WT_MASK)
AnnaBridge 143:86740a56073b 10762
AnnaBridge 143:86740a56073b 10763 /*! @name WP7816T0 - UART 7816 Wait Parameter Register */
AnnaBridge 143:86740a56073b 10764 #define UART_WP7816T0_WI_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10765 #define UART_WP7816T0_WI_SHIFT (0U)
AnnaBridge 143:86740a56073b 10766 #define UART_WP7816T0_WI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T0_WI_SHIFT)) & UART_WP7816T0_WI_MASK)
AnnaBridge 143:86740a56073b 10767
AnnaBridge 143:86740a56073b 10768 /*! @name WP7816T1 - UART 7816 Wait Parameter Register */
AnnaBridge 143:86740a56073b 10769 #define UART_WP7816T1_BWI_MASK (0xFU)
AnnaBridge 143:86740a56073b 10770 #define UART_WP7816T1_BWI_SHIFT (0U)
AnnaBridge 143:86740a56073b 10771 #define UART_WP7816T1_BWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_BWI_SHIFT)) & UART_WP7816T1_BWI_MASK)
AnnaBridge 143:86740a56073b 10772 #define UART_WP7816T1_CWI_MASK (0xF0U)
AnnaBridge 143:86740a56073b 10773 #define UART_WP7816T1_CWI_SHIFT (4U)
AnnaBridge 143:86740a56073b 10774 #define UART_WP7816T1_CWI(x) (((uint8_t)(((uint8_t)(x)) << UART_WP7816T1_CWI_SHIFT)) & UART_WP7816T1_CWI_MASK)
AnnaBridge 143:86740a56073b 10775
AnnaBridge 143:86740a56073b 10776 /*! @name WN7816 - UART 7816 Wait N Register */
AnnaBridge 143:86740a56073b 10777 #define UART_WN7816_GTN_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10778 #define UART_WN7816_GTN_SHIFT (0U)
AnnaBridge 143:86740a56073b 10779 #define UART_WN7816_GTN(x) (((uint8_t)(((uint8_t)(x)) << UART_WN7816_GTN_SHIFT)) & UART_WN7816_GTN_MASK)
AnnaBridge 143:86740a56073b 10780
AnnaBridge 143:86740a56073b 10781 /*! @name WF7816 - UART 7816 Wait FD Register */
AnnaBridge 143:86740a56073b 10782 #define UART_WF7816_GTFD_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10783 #define UART_WF7816_GTFD_SHIFT (0U)
AnnaBridge 143:86740a56073b 10784 #define UART_WF7816_GTFD(x) (((uint8_t)(((uint8_t)(x)) << UART_WF7816_GTFD_SHIFT)) & UART_WF7816_GTFD_MASK)
AnnaBridge 143:86740a56073b 10785
AnnaBridge 143:86740a56073b 10786 /*! @name ET7816 - UART 7816 Error Threshold Register */
AnnaBridge 143:86740a56073b 10787 #define UART_ET7816_RXTHRESHOLD_MASK (0xFU)
AnnaBridge 143:86740a56073b 10788 #define UART_ET7816_RXTHRESHOLD_SHIFT (0U)
AnnaBridge 143:86740a56073b 10789 #define UART_ET7816_RXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_RXTHRESHOLD_SHIFT)) & UART_ET7816_RXTHRESHOLD_MASK)
AnnaBridge 143:86740a56073b 10790 #define UART_ET7816_TXTHRESHOLD_MASK (0xF0U)
AnnaBridge 143:86740a56073b 10791 #define UART_ET7816_TXTHRESHOLD_SHIFT (4U)
AnnaBridge 143:86740a56073b 10792 #define UART_ET7816_TXTHRESHOLD(x) (((uint8_t)(((uint8_t)(x)) << UART_ET7816_TXTHRESHOLD_SHIFT)) & UART_ET7816_TXTHRESHOLD_MASK)
AnnaBridge 143:86740a56073b 10793
AnnaBridge 143:86740a56073b 10794 /*! @name TL7816 - UART 7816 Transmit Length Register */
AnnaBridge 143:86740a56073b 10795 #define UART_TL7816_TLEN_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10796 #define UART_TL7816_TLEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 10797 #define UART_TL7816_TLEN(x) (((uint8_t)(((uint8_t)(x)) << UART_TL7816_TLEN_SHIFT)) & UART_TL7816_TLEN_MASK)
AnnaBridge 143:86740a56073b 10798
AnnaBridge 143:86740a56073b 10799
AnnaBridge 143:86740a56073b 10800 /*!
AnnaBridge 143:86740a56073b 10801 * @}
AnnaBridge 143:86740a56073b 10802 */ /* end of group UART_Register_Masks */
AnnaBridge 143:86740a56073b 10803
AnnaBridge 143:86740a56073b 10804
AnnaBridge 143:86740a56073b 10805 /* UART - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 10806 /** Peripheral UART0 base address */
AnnaBridge 143:86740a56073b 10807 #define UART0_BASE (0x4006A000u)
AnnaBridge 143:86740a56073b 10808 /** Peripheral UART0 base pointer */
AnnaBridge 143:86740a56073b 10809 #define UART0 ((UART_Type *)UART0_BASE)
AnnaBridge 143:86740a56073b 10810 /** Peripheral UART1 base address */
AnnaBridge 143:86740a56073b 10811 #define UART1_BASE (0x4006B000u)
AnnaBridge 143:86740a56073b 10812 /** Peripheral UART1 base pointer */
AnnaBridge 143:86740a56073b 10813 #define UART1 ((UART_Type *)UART1_BASE)
AnnaBridge 143:86740a56073b 10814 /** Peripheral UART2 base address */
AnnaBridge 143:86740a56073b 10815 #define UART2_BASE (0x4006C000u)
AnnaBridge 143:86740a56073b 10816 /** Peripheral UART2 base pointer */
AnnaBridge 143:86740a56073b 10817 #define UART2 ((UART_Type *)UART2_BASE)
AnnaBridge 143:86740a56073b 10818 /** Peripheral UART3 base address */
AnnaBridge 143:86740a56073b 10819 #define UART3_BASE (0x4006D000u)
AnnaBridge 143:86740a56073b 10820 /** Peripheral UART3 base pointer */
AnnaBridge 143:86740a56073b 10821 #define UART3 ((UART_Type *)UART3_BASE)
AnnaBridge 143:86740a56073b 10822 /** Peripheral UART4 base address */
AnnaBridge 143:86740a56073b 10823 #define UART4_BASE (0x400EA000u)
AnnaBridge 143:86740a56073b 10824 /** Peripheral UART4 base pointer */
AnnaBridge 143:86740a56073b 10825 #define UART4 ((UART_Type *)UART4_BASE)
AnnaBridge 143:86740a56073b 10826 /** Peripheral UART5 base address */
AnnaBridge 143:86740a56073b 10827 #define UART5_BASE (0x400EB000u)
AnnaBridge 143:86740a56073b 10828 /** Peripheral UART5 base pointer */
AnnaBridge 143:86740a56073b 10829 #define UART5 ((UART_Type *)UART5_BASE)
AnnaBridge 143:86740a56073b 10830 /** Array initializer of UART peripheral base addresses */
AnnaBridge 143:86740a56073b 10831 #define UART_BASE_ADDRS { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE, UART4_BASE, UART5_BASE }
AnnaBridge 143:86740a56073b 10832 /** Array initializer of UART peripheral base pointers */
AnnaBridge 143:86740a56073b 10833 #define UART_BASE_PTRS { UART0, UART1, UART2, UART3, UART4, UART5 }
AnnaBridge 143:86740a56073b 10834 /** Interrupt vectors for the UART peripheral type */
AnnaBridge 143:86740a56073b 10835 #define UART_RX_TX_IRQS { UART0_RX_TX_IRQn, UART1_RX_TX_IRQn, UART2_RX_TX_IRQn, UART3_RX_TX_IRQn, UART4_RX_TX_IRQn, UART5_RX_TX_IRQn }
AnnaBridge 143:86740a56073b 10836 #define UART_ERR_IRQS { UART0_ERR_IRQn, UART1_ERR_IRQn, UART2_ERR_IRQn, UART3_ERR_IRQn, UART4_ERR_IRQn, UART5_ERR_IRQn }
AnnaBridge 143:86740a56073b 10837 #define UART_LON_IRQS { UART0_LON_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn, NotAvail_IRQn }
AnnaBridge 143:86740a56073b 10838
AnnaBridge 143:86740a56073b 10839 /*!
AnnaBridge 143:86740a56073b 10840 * @}
AnnaBridge 143:86740a56073b 10841 */ /* end of group UART_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 10842
AnnaBridge 143:86740a56073b 10843
AnnaBridge 143:86740a56073b 10844 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 10845 -- USB Peripheral Access Layer
AnnaBridge 143:86740a56073b 10846 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 10847
AnnaBridge 143:86740a56073b 10848 /*!
AnnaBridge 143:86740a56073b 10849 * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
AnnaBridge 143:86740a56073b 10850 * @{
AnnaBridge 143:86740a56073b 10851 */
AnnaBridge 143:86740a56073b 10852
AnnaBridge 143:86740a56073b 10853 /** USB - Register Layout Typedef */
AnnaBridge 143:86740a56073b 10854 typedef struct {
AnnaBridge 143:86740a56073b 10855 __I uint8_t PERID; /**< Peripheral ID register, offset: 0x0 */
AnnaBridge 143:86740a56073b 10856 uint8_t RESERVED_0[3];
AnnaBridge 143:86740a56073b 10857 __I uint8_t IDCOMP; /**< Peripheral ID Complement register, offset: 0x4 */
AnnaBridge 143:86740a56073b 10858 uint8_t RESERVED_1[3];
AnnaBridge 143:86740a56073b 10859 __I uint8_t REV; /**< Peripheral Revision register, offset: 0x8 */
AnnaBridge 143:86740a56073b 10860 uint8_t RESERVED_2[3];
AnnaBridge 143:86740a56073b 10861 __I uint8_t ADDINFO; /**< Peripheral Additional Info register, offset: 0xC */
AnnaBridge 143:86740a56073b 10862 uint8_t RESERVED_3[3];
AnnaBridge 143:86740a56073b 10863 __IO uint8_t OTGISTAT; /**< OTG Interrupt Status register, offset: 0x10 */
AnnaBridge 143:86740a56073b 10864 uint8_t RESERVED_4[3];
AnnaBridge 143:86740a56073b 10865 __IO uint8_t OTGICR; /**< OTG Interrupt Control register, offset: 0x14 */
AnnaBridge 143:86740a56073b 10866 uint8_t RESERVED_5[3];
AnnaBridge 143:86740a56073b 10867 __IO uint8_t OTGSTAT; /**< OTG Status register, offset: 0x18 */
AnnaBridge 143:86740a56073b 10868 uint8_t RESERVED_6[3];
AnnaBridge 143:86740a56073b 10869 __IO uint8_t OTGCTL; /**< OTG Control register, offset: 0x1C */
AnnaBridge 143:86740a56073b 10870 uint8_t RESERVED_7[99];
AnnaBridge 143:86740a56073b 10871 __IO uint8_t ISTAT; /**< Interrupt Status register, offset: 0x80 */
AnnaBridge 143:86740a56073b 10872 uint8_t RESERVED_8[3];
AnnaBridge 143:86740a56073b 10873 __IO uint8_t INTEN; /**< Interrupt Enable register, offset: 0x84 */
AnnaBridge 143:86740a56073b 10874 uint8_t RESERVED_9[3];
AnnaBridge 143:86740a56073b 10875 __IO uint8_t ERRSTAT; /**< Error Interrupt Status register, offset: 0x88 */
AnnaBridge 143:86740a56073b 10876 uint8_t RESERVED_10[3];
AnnaBridge 143:86740a56073b 10877 __IO uint8_t ERREN; /**< Error Interrupt Enable register, offset: 0x8C */
AnnaBridge 143:86740a56073b 10878 uint8_t RESERVED_11[3];
AnnaBridge 143:86740a56073b 10879 __I uint8_t STAT; /**< Status register, offset: 0x90 */
AnnaBridge 143:86740a56073b 10880 uint8_t RESERVED_12[3];
AnnaBridge 143:86740a56073b 10881 __IO uint8_t CTL; /**< Control register, offset: 0x94 */
AnnaBridge 143:86740a56073b 10882 uint8_t RESERVED_13[3];
AnnaBridge 143:86740a56073b 10883 __IO uint8_t ADDR; /**< Address register, offset: 0x98 */
AnnaBridge 143:86740a56073b 10884 uint8_t RESERVED_14[3];
AnnaBridge 143:86740a56073b 10885 __IO uint8_t BDTPAGE1; /**< BDT Page register 1, offset: 0x9C */
AnnaBridge 143:86740a56073b 10886 uint8_t RESERVED_15[3];
AnnaBridge 143:86740a56073b 10887 __IO uint8_t FRMNUML; /**< Frame Number register Low, offset: 0xA0 */
AnnaBridge 143:86740a56073b 10888 uint8_t RESERVED_16[3];
AnnaBridge 143:86740a56073b 10889 __IO uint8_t FRMNUMH; /**< Frame Number register High, offset: 0xA4 */
AnnaBridge 143:86740a56073b 10890 uint8_t RESERVED_17[3];
AnnaBridge 143:86740a56073b 10891 __IO uint8_t TOKEN; /**< Token register, offset: 0xA8 */
AnnaBridge 143:86740a56073b 10892 uint8_t RESERVED_18[3];
AnnaBridge 143:86740a56073b 10893 __IO uint8_t SOFTHLD; /**< SOF Threshold register, offset: 0xAC */
AnnaBridge 143:86740a56073b 10894 uint8_t RESERVED_19[3];
AnnaBridge 143:86740a56073b 10895 __IO uint8_t BDTPAGE2; /**< BDT Page Register 2, offset: 0xB0 */
AnnaBridge 143:86740a56073b 10896 uint8_t RESERVED_20[3];
AnnaBridge 143:86740a56073b 10897 __IO uint8_t BDTPAGE3; /**< BDT Page Register 3, offset: 0xB4 */
AnnaBridge 143:86740a56073b 10898 uint8_t RESERVED_21[11];
AnnaBridge 143:86740a56073b 10899 struct { /* offset: 0xC0, array step: 0x4 */
AnnaBridge 143:86740a56073b 10900 __IO uint8_t ENDPT; /**< Endpoint Control register, array offset: 0xC0, array step: 0x4 */
AnnaBridge 143:86740a56073b 10901 uint8_t RESERVED_0[3];
AnnaBridge 143:86740a56073b 10902 } ENDPOINT[16];
AnnaBridge 143:86740a56073b 10903 __IO uint8_t USBCTRL; /**< USB Control register, offset: 0x100 */
AnnaBridge 143:86740a56073b 10904 uint8_t RESERVED_22[3];
AnnaBridge 143:86740a56073b 10905 __I uint8_t OBSERVE; /**< USB OTG Observe register, offset: 0x104 */
AnnaBridge 143:86740a56073b 10906 uint8_t RESERVED_23[3];
AnnaBridge 143:86740a56073b 10907 __IO uint8_t CONTROL; /**< USB OTG Control register, offset: 0x108 */
AnnaBridge 143:86740a56073b 10908 uint8_t RESERVED_24[3];
AnnaBridge 143:86740a56073b 10909 __IO uint8_t USBTRC0; /**< USB Transceiver Control register 0, offset: 0x10C */
AnnaBridge 143:86740a56073b 10910 uint8_t RESERVED_25[7];
AnnaBridge 143:86740a56073b 10911 __IO uint8_t USBFRMADJUST; /**< Frame Adjust Register, offset: 0x114 */
AnnaBridge 143:86740a56073b 10912 uint8_t RESERVED_26[43];
AnnaBridge 143:86740a56073b 10913 __IO uint8_t CLK_RECOVER_CTRL; /**< USB Clock recovery control, offset: 0x140 */
AnnaBridge 143:86740a56073b 10914 uint8_t RESERVED_27[3];
AnnaBridge 143:86740a56073b 10915 __IO uint8_t CLK_RECOVER_IRC_EN; /**< IRC48M oscillator enable register, offset: 0x144 */
AnnaBridge 143:86740a56073b 10916 uint8_t RESERVED_28[23];
AnnaBridge 143:86740a56073b 10917 __IO uint8_t CLK_RECOVER_INT_STATUS; /**< Clock recovery separated interrupt status, offset: 0x15C */
AnnaBridge 143:86740a56073b 10918 } USB_Type;
AnnaBridge 143:86740a56073b 10919
AnnaBridge 143:86740a56073b 10920 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 10921 -- USB Register Masks
AnnaBridge 143:86740a56073b 10922 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 10923
AnnaBridge 143:86740a56073b 10924 /*!
AnnaBridge 143:86740a56073b 10925 * @addtogroup USB_Register_Masks USB Register Masks
AnnaBridge 143:86740a56073b 10926 * @{
AnnaBridge 143:86740a56073b 10927 */
AnnaBridge 143:86740a56073b 10928
AnnaBridge 143:86740a56073b 10929 /*! @name PERID - Peripheral ID register */
AnnaBridge 143:86740a56073b 10930 #define USB_PERID_ID_MASK (0x3FU)
AnnaBridge 143:86740a56073b 10931 #define USB_PERID_ID_SHIFT (0U)
AnnaBridge 143:86740a56073b 10932 #define USB_PERID_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_PERID_ID_SHIFT)) & USB_PERID_ID_MASK)
AnnaBridge 143:86740a56073b 10933
AnnaBridge 143:86740a56073b 10934 /*! @name IDCOMP - Peripheral ID Complement register */
AnnaBridge 143:86740a56073b 10935 #define USB_IDCOMP_NID_MASK (0x3FU)
AnnaBridge 143:86740a56073b 10936 #define USB_IDCOMP_NID_SHIFT (0U)
AnnaBridge 143:86740a56073b 10937 #define USB_IDCOMP_NID(x) (((uint8_t)(((uint8_t)(x)) << USB_IDCOMP_NID_SHIFT)) & USB_IDCOMP_NID_MASK)
AnnaBridge 143:86740a56073b 10938
AnnaBridge 143:86740a56073b 10939 /*! @name REV - Peripheral Revision register */
AnnaBridge 143:86740a56073b 10940 #define USB_REV_REV_MASK (0xFFU)
AnnaBridge 143:86740a56073b 10941 #define USB_REV_REV_SHIFT (0U)
AnnaBridge 143:86740a56073b 10942 #define USB_REV_REV(x) (((uint8_t)(((uint8_t)(x)) << USB_REV_REV_SHIFT)) & USB_REV_REV_MASK)
AnnaBridge 143:86740a56073b 10943
AnnaBridge 143:86740a56073b 10944 /*! @name ADDINFO - Peripheral Additional Info register */
AnnaBridge 143:86740a56073b 10945 #define USB_ADDINFO_IEHOST_MASK (0x1U)
AnnaBridge 143:86740a56073b 10946 #define USB_ADDINFO_IEHOST_SHIFT (0U)
AnnaBridge 143:86740a56073b 10947 #define USB_ADDINFO_IEHOST(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IEHOST_SHIFT)) & USB_ADDINFO_IEHOST_MASK)
AnnaBridge 143:86740a56073b 10948 #define USB_ADDINFO_IRQNUM_MASK (0xF8U)
AnnaBridge 143:86740a56073b 10949 #define USB_ADDINFO_IRQNUM_SHIFT (3U)
AnnaBridge 143:86740a56073b 10950 #define USB_ADDINFO_IRQNUM(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDINFO_IRQNUM_SHIFT)) & USB_ADDINFO_IRQNUM_MASK)
AnnaBridge 143:86740a56073b 10951
AnnaBridge 143:86740a56073b 10952 /*! @name OTGISTAT - OTG Interrupt Status register */
AnnaBridge 143:86740a56073b 10953 #define USB_OTGISTAT_AVBUSCHG_MASK (0x1U)
AnnaBridge 143:86740a56073b 10954 #define USB_OTGISTAT_AVBUSCHG_SHIFT (0U)
AnnaBridge 143:86740a56073b 10955 #define USB_OTGISTAT_AVBUSCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_AVBUSCHG_SHIFT)) & USB_OTGISTAT_AVBUSCHG_MASK)
AnnaBridge 143:86740a56073b 10956 #define USB_OTGISTAT_B_SESS_CHG_MASK (0x4U)
AnnaBridge 143:86740a56073b 10957 #define USB_OTGISTAT_B_SESS_CHG_SHIFT (2U)
AnnaBridge 143:86740a56073b 10958 #define USB_OTGISTAT_B_SESS_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_B_SESS_CHG_SHIFT)) & USB_OTGISTAT_B_SESS_CHG_MASK)
AnnaBridge 143:86740a56073b 10959 #define USB_OTGISTAT_SESSVLDCHG_MASK (0x8U)
AnnaBridge 143:86740a56073b 10960 #define USB_OTGISTAT_SESSVLDCHG_SHIFT (3U)
AnnaBridge 143:86740a56073b 10961 #define USB_OTGISTAT_SESSVLDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_SESSVLDCHG_SHIFT)) & USB_OTGISTAT_SESSVLDCHG_MASK)
AnnaBridge 143:86740a56073b 10962 #define USB_OTGISTAT_LINE_STATE_CHG_MASK (0x20U)
AnnaBridge 143:86740a56073b 10963 #define USB_OTGISTAT_LINE_STATE_CHG_SHIFT (5U)
AnnaBridge 143:86740a56073b 10964 #define USB_OTGISTAT_LINE_STATE_CHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_LINE_STATE_CHG_SHIFT)) & USB_OTGISTAT_LINE_STATE_CHG_MASK)
AnnaBridge 143:86740a56073b 10965 #define USB_OTGISTAT_ONEMSEC_MASK (0x40U)
AnnaBridge 143:86740a56073b 10966 #define USB_OTGISTAT_ONEMSEC_SHIFT (6U)
AnnaBridge 143:86740a56073b 10967 #define USB_OTGISTAT_ONEMSEC(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_ONEMSEC_SHIFT)) & USB_OTGISTAT_ONEMSEC_MASK)
AnnaBridge 143:86740a56073b 10968 #define USB_OTGISTAT_IDCHG_MASK (0x80U)
AnnaBridge 143:86740a56073b 10969 #define USB_OTGISTAT_IDCHG_SHIFT (7U)
AnnaBridge 143:86740a56073b 10970 #define USB_OTGISTAT_IDCHG(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGISTAT_IDCHG_SHIFT)) & USB_OTGISTAT_IDCHG_MASK)
AnnaBridge 143:86740a56073b 10971
AnnaBridge 143:86740a56073b 10972 /*! @name OTGICR - OTG Interrupt Control register */
AnnaBridge 143:86740a56073b 10973 #define USB_OTGICR_AVBUSEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 10974 #define USB_OTGICR_AVBUSEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 10975 #define USB_OTGICR_AVBUSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_AVBUSEN_SHIFT)) & USB_OTGICR_AVBUSEN_MASK)
AnnaBridge 143:86740a56073b 10976 #define USB_OTGICR_BSESSEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 10977 #define USB_OTGICR_BSESSEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 10978 #define USB_OTGICR_BSESSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_BSESSEN_SHIFT)) & USB_OTGICR_BSESSEN_MASK)
AnnaBridge 143:86740a56073b 10979 #define USB_OTGICR_SESSVLDEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 10980 #define USB_OTGICR_SESSVLDEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 10981 #define USB_OTGICR_SESSVLDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_SESSVLDEN_SHIFT)) & USB_OTGICR_SESSVLDEN_MASK)
AnnaBridge 143:86740a56073b 10982 #define USB_OTGICR_LINESTATEEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 10983 #define USB_OTGICR_LINESTATEEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 10984 #define USB_OTGICR_LINESTATEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_LINESTATEEN_SHIFT)) & USB_OTGICR_LINESTATEEN_MASK)
AnnaBridge 143:86740a56073b 10985 #define USB_OTGICR_ONEMSECEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 10986 #define USB_OTGICR_ONEMSECEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 10987 #define USB_OTGICR_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_ONEMSECEN_SHIFT)) & USB_OTGICR_ONEMSECEN_MASK)
AnnaBridge 143:86740a56073b 10988 #define USB_OTGICR_IDEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 10989 #define USB_OTGICR_IDEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 10990 #define USB_OTGICR_IDEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGICR_IDEN_SHIFT)) & USB_OTGICR_IDEN_MASK)
AnnaBridge 143:86740a56073b 10991
AnnaBridge 143:86740a56073b 10992 /*! @name OTGSTAT - OTG Status register */
AnnaBridge 143:86740a56073b 10993 #define USB_OTGSTAT_AVBUSVLD_MASK (0x1U)
AnnaBridge 143:86740a56073b 10994 #define USB_OTGSTAT_AVBUSVLD_SHIFT (0U)
AnnaBridge 143:86740a56073b 10995 #define USB_OTGSTAT_AVBUSVLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_AVBUSVLD_SHIFT)) & USB_OTGSTAT_AVBUSVLD_MASK)
AnnaBridge 143:86740a56073b 10996 #define USB_OTGSTAT_BSESSEND_MASK (0x4U)
AnnaBridge 143:86740a56073b 10997 #define USB_OTGSTAT_BSESSEND_SHIFT (2U)
AnnaBridge 143:86740a56073b 10998 #define USB_OTGSTAT_BSESSEND(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_BSESSEND_SHIFT)) & USB_OTGSTAT_BSESSEND_MASK)
AnnaBridge 143:86740a56073b 10999 #define USB_OTGSTAT_SESS_VLD_MASK (0x8U)
AnnaBridge 143:86740a56073b 11000 #define USB_OTGSTAT_SESS_VLD_SHIFT (3U)
AnnaBridge 143:86740a56073b 11001 #define USB_OTGSTAT_SESS_VLD(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_SESS_VLD_SHIFT)) & USB_OTGSTAT_SESS_VLD_MASK)
AnnaBridge 143:86740a56073b 11002 #define USB_OTGSTAT_LINESTATESTABLE_MASK (0x20U)
AnnaBridge 143:86740a56073b 11003 #define USB_OTGSTAT_LINESTATESTABLE_SHIFT (5U)
AnnaBridge 143:86740a56073b 11004 #define USB_OTGSTAT_LINESTATESTABLE(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_LINESTATESTABLE_SHIFT)) & USB_OTGSTAT_LINESTATESTABLE_MASK)
AnnaBridge 143:86740a56073b 11005 #define USB_OTGSTAT_ONEMSECEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 11006 #define USB_OTGSTAT_ONEMSECEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 11007 #define USB_OTGSTAT_ONEMSECEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ONEMSECEN_SHIFT)) & USB_OTGSTAT_ONEMSECEN_MASK)
AnnaBridge 143:86740a56073b 11008 #define USB_OTGSTAT_ID_MASK (0x80U)
AnnaBridge 143:86740a56073b 11009 #define USB_OTGSTAT_ID_SHIFT (7U)
AnnaBridge 143:86740a56073b 11010 #define USB_OTGSTAT_ID(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGSTAT_ID_SHIFT)) & USB_OTGSTAT_ID_MASK)
AnnaBridge 143:86740a56073b 11011
AnnaBridge 143:86740a56073b 11012 /*! @name OTGCTL - OTG Control register */
AnnaBridge 143:86740a56073b 11013 #define USB_OTGCTL_OTGEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 11014 #define USB_OTGCTL_OTGEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 11015 #define USB_OTGCTL_OTGEN(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_OTGEN_SHIFT)) & USB_OTGCTL_OTGEN_MASK)
AnnaBridge 143:86740a56073b 11016 #define USB_OTGCTL_DMLOW_MASK (0x10U)
AnnaBridge 143:86740a56073b 11017 #define USB_OTGCTL_DMLOW_SHIFT (4U)
AnnaBridge 143:86740a56073b 11018 #define USB_OTGCTL_DMLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DMLOW_SHIFT)) & USB_OTGCTL_DMLOW_MASK)
AnnaBridge 143:86740a56073b 11019 #define USB_OTGCTL_DPLOW_MASK (0x20U)
AnnaBridge 143:86740a56073b 11020 #define USB_OTGCTL_DPLOW_SHIFT (5U)
AnnaBridge 143:86740a56073b 11021 #define USB_OTGCTL_DPLOW(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPLOW_SHIFT)) & USB_OTGCTL_DPLOW_MASK)
AnnaBridge 143:86740a56073b 11022 #define USB_OTGCTL_DPHIGH_MASK (0x80U)
AnnaBridge 143:86740a56073b 11023 #define USB_OTGCTL_DPHIGH_SHIFT (7U)
AnnaBridge 143:86740a56073b 11024 #define USB_OTGCTL_DPHIGH(x) (((uint8_t)(((uint8_t)(x)) << USB_OTGCTL_DPHIGH_SHIFT)) & USB_OTGCTL_DPHIGH_MASK)
AnnaBridge 143:86740a56073b 11025
AnnaBridge 143:86740a56073b 11026 /*! @name ISTAT - Interrupt Status register */
AnnaBridge 143:86740a56073b 11027 #define USB_ISTAT_USBRST_MASK (0x1U)
AnnaBridge 143:86740a56073b 11028 #define USB_ISTAT_USBRST_SHIFT (0U)
AnnaBridge 143:86740a56073b 11029 #define USB_ISTAT_USBRST(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_USBRST_SHIFT)) & USB_ISTAT_USBRST_MASK)
AnnaBridge 143:86740a56073b 11030 #define USB_ISTAT_ERROR_MASK (0x2U)
AnnaBridge 143:86740a56073b 11031 #define USB_ISTAT_ERROR_SHIFT (1U)
AnnaBridge 143:86740a56073b 11032 #define USB_ISTAT_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ERROR_SHIFT)) & USB_ISTAT_ERROR_MASK)
AnnaBridge 143:86740a56073b 11033 #define USB_ISTAT_SOFTOK_MASK (0x4U)
AnnaBridge 143:86740a56073b 11034 #define USB_ISTAT_SOFTOK_SHIFT (2U)
AnnaBridge 143:86740a56073b 11035 #define USB_ISTAT_SOFTOK(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SOFTOK_SHIFT)) & USB_ISTAT_SOFTOK_MASK)
AnnaBridge 143:86740a56073b 11036 #define USB_ISTAT_TOKDNE_MASK (0x8U)
AnnaBridge 143:86740a56073b 11037 #define USB_ISTAT_TOKDNE_SHIFT (3U)
AnnaBridge 143:86740a56073b 11038 #define USB_ISTAT_TOKDNE(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_TOKDNE_SHIFT)) & USB_ISTAT_TOKDNE_MASK)
AnnaBridge 143:86740a56073b 11039 #define USB_ISTAT_SLEEP_MASK (0x10U)
AnnaBridge 143:86740a56073b 11040 #define USB_ISTAT_SLEEP_SHIFT (4U)
AnnaBridge 143:86740a56073b 11041 #define USB_ISTAT_SLEEP(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_SLEEP_SHIFT)) & USB_ISTAT_SLEEP_MASK)
AnnaBridge 143:86740a56073b 11042 #define USB_ISTAT_RESUME_MASK (0x20U)
AnnaBridge 143:86740a56073b 11043 #define USB_ISTAT_RESUME_SHIFT (5U)
AnnaBridge 143:86740a56073b 11044 #define USB_ISTAT_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_RESUME_SHIFT)) & USB_ISTAT_RESUME_MASK)
AnnaBridge 143:86740a56073b 11045 #define USB_ISTAT_ATTACH_MASK (0x40U)
AnnaBridge 143:86740a56073b 11046 #define USB_ISTAT_ATTACH_SHIFT (6U)
AnnaBridge 143:86740a56073b 11047 #define USB_ISTAT_ATTACH(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_ATTACH_SHIFT)) & USB_ISTAT_ATTACH_MASK)
AnnaBridge 143:86740a56073b 11048 #define USB_ISTAT_STALL_MASK (0x80U)
AnnaBridge 143:86740a56073b 11049 #define USB_ISTAT_STALL_SHIFT (7U)
AnnaBridge 143:86740a56073b 11050 #define USB_ISTAT_STALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ISTAT_STALL_SHIFT)) & USB_ISTAT_STALL_MASK)
AnnaBridge 143:86740a56073b 11051
AnnaBridge 143:86740a56073b 11052 /*! @name INTEN - Interrupt Enable register */
AnnaBridge 143:86740a56073b 11053 #define USB_INTEN_USBRSTEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 11054 #define USB_INTEN_USBRSTEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 11055 #define USB_INTEN_USBRSTEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_USBRSTEN_SHIFT)) & USB_INTEN_USBRSTEN_MASK)
AnnaBridge 143:86740a56073b 11056 #define USB_INTEN_ERROREN_MASK (0x2U)
AnnaBridge 143:86740a56073b 11057 #define USB_INTEN_ERROREN_SHIFT (1U)
AnnaBridge 143:86740a56073b 11058 #define USB_INTEN_ERROREN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ERROREN_SHIFT)) & USB_INTEN_ERROREN_MASK)
AnnaBridge 143:86740a56073b 11059 #define USB_INTEN_SOFTOKEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 11060 #define USB_INTEN_SOFTOKEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 11061 #define USB_INTEN_SOFTOKEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SOFTOKEN_SHIFT)) & USB_INTEN_SOFTOKEN_MASK)
AnnaBridge 143:86740a56073b 11062 #define USB_INTEN_TOKDNEEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 11063 #define USB_INTEN_TOKDNEEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 11064 #define USB_INTEN_TOKDNEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_TOKDNEEN_SHIFT)) & USB_INTEN_TOKDNEEN_MASK)
AnnaBridge 143:86740a56073b 11065 #define USB_INTEN_SLEEPEN_MASK (0x10U)
AnnaBridge 143:86740a56073b 11066 #define USB_INTEN_SLEEPEN_SHIFT (4U)
AnnaBridge 143:86740a56073b 11067 #define USB_INTEN_SLEEPEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_SLEEPEN_SHIFT)) & USB_INTEN_SLEEPEN_MASK)
AnnaBridge 143:86740a56073b 11068 #define USB_INTEN_RESUMEEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 11069 #define USB_INTEN_RESUMEEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 11070 #define USB_INTEN_RESUMEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_RESUMEEN_SHIFT)) & USB_INTEN_RESUMEEN_MASK)
AnnaBridge 143:86740a56073b 11071 #define USB_INTEN_ATTACHEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 11072 #define USB_INTEN_ATTACHEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 11073 #define USB_INTEN_ATTACHEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_ATTACHEN_SHIFT)) & USB_INTEN_ATTACHEN_MASK)
AnnaBridge 143:86740a56073b 11074 #define USB_INTEN_STALLEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 11075 #define USB_INTEN_STALLEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 11076 #define USB_INTEN_STALLEN(x) (((uint8_t)(((uint8_t)(x)) << USB_INTEN_STALLEN_SHIFT)) & USB_INTEN_STALLEN_MASK)
AnnaBridge 143:86740a56073b 11077
AnnaBridge 143:86740a56073b 11078 /*! @name ERRSTAT - Error Interrupt Status register */
AnnaBridge 143:86740a56073b 11079 #define USB_ERRSTAT_PIDERR_MASK (0x1U)
AnnaBridge 143:86740a56073b 11080 #define USB_ERRSTAT_PIDERR_SHIFT (0U)
AnnaBridge 143:86740a56073b 11081 #define USB_ERRSTAT_PIDERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_PIDERR_SHIFT)) & USB_ERRSTAT_PIDERR_MASK)
AnnaBridge 143:86740a56073b 11082 #define USB_ERRSTAT_CRC5EOF_MASK (0x2U)
AnnaBridge 143:86740a56073b 11083 #define USB_ERRSTAT_CRC5EOF_SHIFT (1U)
AnnaBridge 143:86740a56073b 11084 #define USB_ERRSTAT_CRC5EOF(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC5EOF_SHIFT)) & USB_ERRSTAT_CRC5EOF_MASK)
AnnaBridge 143:86740a56073b 11085 #define USB_ERRSTAT_CRC16_MASK (0x4U)
AnnaBridge 143:86740a56073b 11086 #define USB_ERRSTAT_CRC16_SHIFT (2U)
AnnaBridge 143:86740a56073b 11087 #define USB_ERRSTAT_CRC16(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_CRC16_SHIFT)) & USB_ERRSTAT_CRC16_MASK)
AnnaBridge 143:86740a56073b 11088 #define USB_ERRSTAT_DFN8_MASK (0x8U)
AnnaBridge 143:86740a56073b 11089 #define USB_ERRSTAT_DFN8_SHIFT (3U)
AnnaBridge 143:86740a56073b 11090 #define USB_ERRSTAT_DFN8(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DFN8_SHIFT)) & USB_ERRSTAT_DFN8_MASK)
AnnaBridge 143:86740a56073b 11091 #define USB_ERRSTAT_BTOERR_MASK (0x10U)
AnnaBridge 143:86740a56073b 11092 #define USB_ERRSTAT_BTOERR_SHIFT (4U)
AnnaBridge 143:86740a56073b 11093 #define USB_ERRSTAT_BTOERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTOERR_SHIFT)) & USB_ERRSTAT_BTOERR_MASK)
AnnaBridge 143:86740a56073b 11094 #define USB_ERRSTAT_DMAERR_MASK (0x20U)
AnnaBridge 143:86740a56073b 11095 #define USB_ERRSTAT_DMAERR_SHIFT (5U)
AnnaBridge 143:86740a56073b 11096 #define USB_ERRSTAT_DMAERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_DMAERR_SHIFT)) & USB_ERRSTAT_DMAERR_MASK)
AnnaBridge 143:86740a56073b 11097 #define USB_ERRSTAT_BTSERR_MASK (0x80U)
AnnaBridge 143:86740a56073b 11098 #define USB_ERRSTAT_BTSERR_SHIFT (7U)
AnnaBridge 143:86740a56073b 11099 #define USB_ERRSTAT_BTSERR(x) (((uint8_t)(((uint8_t)(x)) << USB_ERRSTAT_BTSERR_SHIFT)) & USB_ERRSTAT_BTSERR_MASK)
AnnaBridge 143:86740a56073b 11100
AnnaBridge 143:86740a56073b 11101 /*! @name ERREN - Error Interrupt Enable register */
AnnaBridge 143:86740a56073b 11102 #define USB_ERREN_PIDERREN_MASK (0x1U)
AnnaBridge 143:86740a56073b 11103 #define USB_ERREN_PIDERREN_SHIFT (0U)
AnnaBridge 143:86740a56073b 11104 #define USB_ERREN_PIDERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_PIDERREN_SHIFT)) & USB_ERREN_PIDERREN_MASK)
AnnaBridge 143:86740a56073b 11105 #define USB_ERREN_CRC5EOFEN_MASK (0x2U)
AnnaBridge 143:86740a56073b 11106 #define USB_ERREN_CRC5EOFEN_SHIFT (1U)
AnnaBridge 143:86740a56073b 11107 #define USB_ERREN_CRC5EOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC5EOFEN_SHIFT)) & USB_ERREN_CRC5EOFEN_MASK)
AnnaBridge 143:86740a56073b 11108 #define USB_ERREN_CRC16EN_MASK (0x4U)
AnnaBridge 143:86740a56073b 11109 #define USB_ERREN_CRC16EN_SHIFT (2U)
AnnaBridge 143:86740a56073b 11110 #define USB_ERREN_CRC16EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_CRC16EN_SHIFT)) & USB_ERREN_CRC16EN_MASK)
AnnaBridge 143:86740a56073b 11111 #define USB_ERREN_DFN8EN_MASK (0x8U)
AnnaBridge 143:86740a56073b 11112 #define USB_ERREN_DFN8EN_SHIFT (3U)
AnnaBridge 143:86740a56073b 11113 #define USB_ERREN_DFN8EN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DFN8EN_SHIFT)) & USB_ERREN_DFN8EN_MASK)
AnnaBridge 143:86740a56073b 11114 #define USB_ERREN_BTOERREN_MASK (0x10U)
AnnaBridge 143:86740a56073b 11115 #define USB_ERREN_BTOERREN_SHIFT (4U)
AnnaBridge 143:86740a56073b 11116 #define USB_ERREN_BTOERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTOERREN_SHIFT)) & USB_ERREN_BTOERREN_MASK)
AnnaBridge 143:86740a56073b 11117 #define USB_ERREN_DMAERREN_MASK (0x20U)
AnnaBridge 143:86740a56073b 11118 #define USB_ERREN_DMAERREN_SHIFT (5U)
AnnaBridge 143:86740a56073b 11119 #define USB_ERREN_DMAERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_DMAERREN_SHIFT)) & USB_ERREN_DMAERREN_MASK)
AnnaBridge 143:86740a56073b 11120 #define USB_ERREN_BTSERREN_MASK (0x80U)
AnnaBridge 143:86740a56073b 11121 #define USB_ERREN_BTSERREN_SHIFT (7U)
AnnaBridge 143:86740a56073b 11122 #define USB_ERREN_BTSERREN(x) (((uint8_t)(((uint8_t)(x)) << USB_ERREN_BTSERREN_SHIFT)) & USB_ERREN_BTSERREN_MASK)
AnnaBridge 143:86740a56073b 11123
AnnaBridge 143:86740a56073b 11124 /*! @name STAT - Status register */
AnnaBridge 143:86740a56073b 11125 #define USB_STAT_ODD_MASK (0x4U)
AnnaBridge 143:86740a56073b 11126 #define USB_STAT_ODD_SHIFT (2U)
AnnaBridge 143:86740a56073b 11127 #define USB_STAT_ODD(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ODD_SHIFT)) & USB_STAT_ODD_MASK)
AnnaBridge 143:86740a56073b 11128 #define USB_STAT_TX_MASK (0x8U)
AnnaBridge 143:86740a56073b 11129 #define USB_STAT_TX_SHIFT (3U)
AnnaBridge 143:86740a56073b 11130 #define USB_STAT_TX(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_TX_SHIFT)) & USB_STAT_TX_MASK)
AnnaBridge 143:86740a56073b 11131 #define USB_STAT_ENDP_MASK (0xF0U)
AnnaBridge 143:86740a56073b 11132 #define USB_STAT_ENDP_SHIFT (4U)
AnnaBridge 143:86740a56073b 11133 #define USB_STAT_ENDP(x) (((uint8_t)(((uint8_t)(x)) << USB_STAT_ENDP_SHIFT)) & USB_STAT_ENDP_MASK)
AnnaBridge 143:86740a56073b 11134
AnnaBridge 143:86740a56073b 11135 /*! @name CTL - Control register */
AnnaBridge 143:86740a56073b 11136 #define USB_CTL_USBENSOFEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 11137 #define USB_CTL_USBENSOFEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 11138 #define USB_CTL_USBENSOFEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_USBENSOFEN_SHIFT)) & USB_CTL_USBENSOFEN_MASK)
AnnaBridge 143:86740a56073b 11139 #define USB_CTL_ODDRST_MASK (0x2U)
AnnaBridge 143:86740a56073b 11140 #define USB_CTL_ODDRST_SHIFT (1U)
AnnaBridge 143:86740a56073b 11141 #define USB_CTL_ODDRST(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_ODDRST_SHIFT)) & USB_CTL_ODDRST_MASK)
AnnaBridge 143:86740a56073b 11142 #define USB_CTL_RESUME_MASK (0x4U)
AnnaBridge 143:86740a56073b 11143 #define USB_CTL_RESUME_SHIFT (2U)
AnnaBridge 143:86740a56073b 11144 #define USB_CTL_RESUME(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESUME_SHIFT)) & USB_CTL_RESUME_MASK)
AnnaBridge 143:86740a56073b 11145 #define USB_CTL_HOSTMODEEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 11146 #define USB_CTL_HOSTMODEEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 11147 #define USB_CTL_HOSTMODEEN(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_HOSTMODEEN_SHIFT)) & USB_CTL_HOSTMODEEN_MASK)
AnnaBridge 143:86740a56073b 11148 #define USB_CTL_RESET_MASK (0x10U)
AnnaBridge 143:86740a56073b 11149 #define USB_CTL_RESET_SHIFT (4U)
AnnaBridge 143:86740a56073b 11150 #define USB_CTL_RESET(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_RESET_SHIFT)) & USB_CTL_RESET_MASK)
AnnaBridge 143:86740a56073b 11151 #define USB_CTL_TXSUSPENDTOKENBUSY_MASK (0x20U)
AnnaBridge 143:86740a56073b 11152 #define USB_CTL_TXSUSPENDTOKENBUSY_SHIFT (5U)
AnnaBridge 143:86740a56073b 11153 #define USB_CTL_TXSUSPENDTOKENBUSY(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_TXSUSPENDTOKENBUSY_SHIFT)) & USB_CTL_TXSUSPENDTOKENBUSY_MASK)
AnnaBridge 143:86740a56073b 11154 #define USB_CTL_SE0_MASK (0x40U)
AnnaBridge 143:86740a56073b 11155 #define USB_CTL_SE0_SHIFT (6U)
AnnaBridge 143:86740a56073b 11156 #define USB_CTL_SE0(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_SE0_SHIFT)) & USB_CTL_SE0_MASK)
AnnaBridge 143:86740a56073b 11157 #define USB_CTL_JSTATE_MASK (0x80U)
AnnaBridge 143:86740a56073b 11158 #define USB_CTL_JSTATE_SHIFT (7U)
AnnaBridge 143:86740a56073b 11159 #define USB_CTL_JSTATE(x) (((uint8_t)(((uint8_t)(x)) << USB_CTL_JSTATE_SHIFT)) & USB_CTL_JSTATE_MASK)
AnnaBridge 143:86740a56073b 11160
AnnaBridge 143:86740a56073b 11161 /*! @name ADDR - Address register */
AnnaBridge 143:86740a56073b 11162 #define USB_ADDR_ADDR_MASK (0x7FU)
AnnaBridge 143:86740a56073b 11163 #define USB_ADDR_ADDR_SHIFT (0U)
AnnaBridge 143:86740a56073b 11164 #define USB_ADDR_ADDR(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_ADDR_SHIFT)) & USB_ADDR_ADDR_MASK)
AnnaBridge 143:86740a56073b 11165 #define USB_ADDR_LSEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 11166 #define USB_ADDR_LSEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 11167 #define USB_ADDR_LSEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ADDR_LSEN_SHIFT)) & USB_ADDR_LSEN_MASK)
AnnaBridge 143:86740a56073b 11168
AnnaBridge 143:86740a56073b 11169 /*! @name BDTPAGE1 - BDT Page register 1 */
AnnaBridge 143:86740a56073b 11170 #define USB_BDTPAGE1_BDTBA_MASK (0xFEU)
AnnaBridge 143:86740a56073b 11171 #define USB_BDTPAGE1_BDTBA_SHIFT (1U)
AnnaBridge 143:86740a56073b 11172 #define USB_BDTPAGE1_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE1_BDTBA_SHIFT)) & USB_BDTPAGE1_BDTBA_MASK)
AnnaBridge 143:86740a56073b 11173
AnnaBridge 143:86740a56073b 11174 /*! @name FRMNUML - Frame Number register Low */
AnnaBridge 143:86740a56073b 11175 #define USB_FRMNUML_FRM_MASK (0xFFU)
AnnaBridge 143:86740a56073b 11176 #define USB_FRMNUML_FRM_SHIFT (0U)
AnnaBridge 143:86740a56073b 11177 #define USB_FRMNUML_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUML_FRM_SHIFT)) & USB_FRMNUML_FRM_MASK)
AnnaBridge 143:86740a56073b 11178
AnnaBridge 143:86740a56073b 11179 /*! @name FRMNUMH - Frame Number register High */
AnnaBridge 143:86740a56073b 11180 #define USB_FRMNUMH_FRM_MASK (0x7U)
AnnaBridge 143:86740a56073b 11181 #define USB_FRMNUMH_FRM_SHIFT (0U)
AnnaBridge 143:86740a56073b 11182 #define USB_FRMNUMH_FRM(x) (((uint8_t)(((uint8_t)(x)) << USB_FRMNUMH_FRM_SHIFT)) & USB_FRMNUMH_FRM_MASK)
AnnaBridge 143:86740a56073b 11183
AnnaBridge 143:86740a56073b 11184 /*! @name TOKEN - Token register */
AnnaBridge 143:86740a56073b 11185 #define USB_TOKEN_TOKENENDPT_MASK (0xFU)
AnnaBridge 143:86740a56073b 11186 #define USB_TOKEN_TOKENENDPT_SHIFT (0U)
AnnaBridge 143:86740a56073b 11187 #define USB_TOKEN_TOKENENDPT(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENENDPT_SHIFT)) & USB_TOKEN_TOKENENDPT_MASK)
AnnaBridge 143:86740a56073b 11188 #define USB_TOKEN_TOKENPID_MASK (0xF0U)
AnnaBridge 143:86740a56073b 11189 #define USB_TOKEN_TOKENPID_SHIFT (4U)
AnnaBridge 143:86740a56073b 11190 #define USB_TOKEN_TOKENPID(x) (((uint8_t)(((uint8_t)(x)) << USB_TOKEN_TOKENPID_SHIFT)) & USB_TOKEN_TOKENPID_MASK)
AnnaBridge 143:86740a56073b 11191
AnnaBridge 143:86740a56073b 11192 /*! @name SOFTHLD - SOF Threshold register */
AnnaBridge 143:86740a56073b 11193 #define USB_SOFTHLD_CNT_MASK (0xFFU)
AnnaBridge 143:86740a56073b 11194 #define USB_SOFTHLD_CNT_SHIFT (0U)
AnnaBridge 143:86740a56073b 11195 #define USB_SOFTHLD_CNT(x) (((uint8_t)(((uint8_t)(x)) << USB_SOFTHLD_CNT_SHIFT)) & USB_SOFTHLD_CNT_MASK)
AnnaBridge 143:86740a56073b 11196
AnnaBridge 143:86740a56073b 11197 /*! @name BDTPAGE2 - BDT Page Register 2 */
AnnaBridge 143:86740a56073b 11198 #define USB_BDTPAGE2_BDTBA_MASK (0xFFU)
AnnaBridge 143:86740a56073b 11199 #define USB_BDTPAGE2_BDTBA_SHIFT (0U)
AnnaBridge 143:86740a56073b 11200 #define USB_BDTPAGE2_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE2_BDTBA_SHIFT)) & USB_BDTPAGE2_BDTBA_MASK)
AnnaBridge 143:86740a56073b 11201
AnnaBridge 143:86740a56073b 11202 /*! @name BDTPAGE3 - BDT Page Register 3 */
AnnaBridge 143:86740a56073b 11203 #define USB_BDTPAGE3_BDTBA_MASK (0xFFU)
AnnaBridge 143:86740a56073b 11204 #define USB_BDTPAGE3_BDTBA_SHIFT (0U)
AnnaBridge 143:86740a56073b 11205 #define USB_BDTPAGE3_BDTBA(x) (((uint8_t)(((uint8_t)(x)) << USB_BDTPAGE3_BDTBA_SHIFT)) & USB_BDTPAGE3_BDTBA_MASK)
AnnaBridge 143:86740a56073b 11206
AnnaBridge 143:86740a56073b 11207 /*! @name ENDPT - Endpoint Control register */
AnnaBridge 143:86740a56073b 11208 #define USB_ENDPT_EPHSHK_MASK (0x1U)
AnnaBridge 143:86740a56073b 11209 #define USB_ENDPT_EPHSHK_SHIFT (0U)
AnnaBridge 143:86740a56073b 11210 #define USB_ENDPT_EPHSHK(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPHSHK_SHIFT)) & USB_ENDPT_EPHSHK_MASK)
AnnaBridge 143:86740a56073b 11211 #define USB_ENDPT_EPSTALL_MASK (0x2U)
AnnaBridge 143:86740a56073b 11212 #define USB_ENDPT_EPSTALL_SHIFT (1U)
AnnaBridge 143:86740a56073b 11213 #define USB_ENDPT_EPSTALL(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPSTALL_SHIFT)) & USB_ENDPT_EPSTALL_MASK)
AnnaBridge 143:86740a56073b 11214 #define USB_ENDPT_EPTXEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 11215 #define USB_ENDPT_EPTXEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 11216 #define USB_ENDPT_EPTXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPTXEN_SHIFT)) & USB_ENDPT_EPTXEN_MASK)
AnnaBridge 143:86740a56073b 11217 #define USB_ENDPT_EPRXEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 11218 #define USB_ENDPT_EPRXEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 11219 #define USB_ENDPT_EPRXEN(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPRXEN_SHIFT)) & USB_ENDPT_EPRXEN_MASK)
AnnaBridge 143:86740a56073b 11220 #define USB_ENDPT_EPCTLDIS_MASK (0x10U)
AnnaBridge 143:86740a56073b 11221 #define USB_ENDPT_EPCTLDIS_SHIFT (4U)
AnnaBridge 143:86740a56073b 11222 #define USB_ENDPT_EPCTLDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_EPCTLDIS_SHIFT)) & USB_ENDPT_EPCTLDIS_MASK)
AnnaBridge 143:86740a56073b 11223 #define USB_ENDPT_RETRYDIS_MASK (0x40U)
AnnaBridge 143:86740a56073b 11224 #define USB_ENDPT_RETRYDIS_SHIFT (6U)
AnnaBridge 143:86740a56073b 11225 #define USB_ENDPT_RETRYDIS(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_RETRYDIS_SHIFT)) & USB_ENDPT_RETRYDIS_MASK)
AnnaBridge 143:86740a56073b 11226 #define USB_ENDPT_HOSTWOHUB_MASK (0x80U)
AnnaBridge 143:86740a56073b 11227 #define USB_ENDPT_HOSTWOHUB_SHIFT (7U)
AnnaBridge 143:86740a56073b 11228 #define USB_ENDPT_HOSTWOHUB(x) (((uint8_t)(((uint8_t)(x)) << USB_ENDPT_HOSTWOHUB_SHIFT)) & USB_ENDPT_HOSTWOHUB_MASK)
AnnaBridge 143:86740a56073b 11229
AnnaBridge 143:86740a56073b 11230 /* The count of USB_ENDPT */
AnnaBridge 143:86740a56073b 11231 #define USB_ENDPT_COUNT (16U)
AnnaBridge 143:86740a56073b 11232
AnnaBridge 143:86740a56073b 11233 /*! @name USBCTRL - USB Control register */
AnnaBridge 143:86740a56073b 11234 #define USB_USBCTRL_PDE_MASK (0x40U)
AnnaBridge 143:86740a56073b 11235 #define USB_USBCTRL_PDE_SHIFT (6U)
AnnaBridge 143:86740a56073b 11236 #define USB_USBCTRL_PDE(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_PDE_SHIFT)) & USB_USBCTRL_PDE_MASK)
AnnaBridge 143:86740a56073b 11237 #define USB_USBCTRL_SUSP_MASK (0x80U)
AnnaBridge 143:86740a56073b 11238 #define USB_USBCTRL_SUSP_SHIFT (7U)
AnnaBridge 143:86740a56073b 11239 #define USB_USBCTRL_SUSP(x) (((uint8_t)(((uint8_t)(x)) << USB_USBCTRL_SUSP_SHIFT)) & USB_USBCTRL_SUSP_MASK)
AnnaBridge 143:86740a56073b 11240
AnnaBridge 143:86740a56073b 11241 /*! @name OBSERVE - USB OTG Observe register */
AnnaBridge 143:86740a56073b 11242 #define USB_OBSERVE_DMPD_MASK (0x10U)
AnnaBridge 143:86740a56073b 11243 #define USB_OBSERVE_DMPD_SHIFT (4U)
AnnaBridge 143:86740a56073b 11244 #define USB_OBSERVE_DMPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DMPD_SHIFT)) & USB_OBSERVE_DMPD_MASK)
AnnaBridge 143:86740a56073b 11245 #define USB_OBSERVE_DPPD_MASK (0x40U)
AnnaBridge 143:86740a56073b 11246 #define USB_OBSERVE_DPPD_SHIFT (6U)
AnnaBridge 143:86740a56073b 11247 #define USB_OBSERVE_DPPD(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPD_SHIFT)) & USB_OBSERVE_DPPD_MASK)
AnnaBridge 143:86740a56073b 11248 #define USB_OBSERVE_DPPU_MASK (0x80U)
AnnaBridge 143:86740a56073b 11249 #define USB_OBSERVE_DPPU_SHIFT (7U)
AnnaBridge 143:86740a56073b 11250 #define USB_OBSERVE_DPPU(x) (((uint8_t)(((uint8_t)(x)) << USB_OBSERVE_DPPU_SHIFT)) & USB_OBSERVE_DPPU_MASK)
AnnaBridge 143:86740a56073b 11251
AnnaBridge 143:86740a56073b 11252 /*! @name CONTROL - USB OTG Control register */
AnnaBridge 143:86740a56073b 11253 #define USB_CONTROL_DPPULLUPNONOTG_MASK (0x10U)
AnnaBridge 143:86740a56073b 11254 #define USB_CONTROL_DPPULLUPNONOTG_SHIFT (4U)
AnnaBridge 143:86740a56073b 11255 #define USB_CONTROL_DPPULLUPNONOTG(x) (((uint8_t)(((uint8_t)(x)) << USB_CONTROL_DPPULLUPNONOTG_SHIFT)) & USB_CONTROL_DPPULLUPNONOTG_MASK)
AnnaBridge 143:86740a56073b 11256
AnnaBridge 143:86740a56073b 11257 /*! @name USBTRC0 - USB Transceiver Control register 0 */
AnnaBridge 143:86740a56073b 11258 #define USB_USBTRC0_USB_RESUME_INT_MASK (0x1U)
AnnaBridge 143:86740a56073b 11259 #define USB_USBTRC0_USB_RESUME_INT_SHIFT (0U)
AnnaBridge 143:86740a56073b 11260 #define USB_USBTRC0_USB_RESUME_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_RESUME_INT_SHIFT)) & USB_USBTRC0_USB_RESUME_INT_MASK)
AnnaBridge 143:86740a56073b 11261 #define USB_USBTRC0_SYNC_DET_MASK (0x2U)
AnnaBridge 143:86740a56073b 11262 #define USB_USBTRC0_SYNC_DET_SHIFT (1U)
AnnaBridge 143:86740a56073b 11263 #define USB_USBTRC0_SYNC_DET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_SYNC_DET_SHIFT)) & USB_USBTRC0_SYNC_DET_MASK)
AnnaBridge 143:86740a56073b 11264 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK (0x4U)
AnnaBridge 143:86740a56073b 11265 #define USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT (2U)
AnnaBridge 143:86740a56073b 11266 #define USB_USBTRC0_USB_CLK_RECOVERY_INT(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USB_CLK_RECOVERY_INT_SHIFT)) & USB_USBTRC0_USB_CLK_RECOVERY_INT_MASK)
AnnaBridge 143:86740a56073b 11267 #define USB_USBTRC0_USBRESMEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 11268 #define USB_USBTRC0_USBRESMEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 11269 #define USB_USBTRC0_USBRESMEN(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESMEN_SHIFT)) & USB_USBTRC0_USBRESMEN_MASK)
AnnaBridge 143:86740a56073b 11270 #define USB_USBTRC0_USBRESET_MASK (0x80U)
AnnaBridge 143:86740a56073b 11271 #define USB_USBTRC0_USBRESET_SHIFT (7U)
AnnaBridge 143:86740a56073b 11272 #define USB_USBTRC0_USBRESET(x) (((uint8_t)(((uint8_t)(x)) << USB_USBTRC0_USBRESET_SHIFT)) & USB_USBTRC0_USBRESET_MASK)
AnnaBridge 143:86740a56073b 11273
AnnaBridge 143:86740a56073b 11274 /*! @name USBFRMADJUST - Frame Adjust Register */
AnnaBridge 143:86740a56073b 11275 #define USB_USBFRMADJUST_ADJ_MASK (0xFFU)
AnnaBridge 143:86740a56073b 11276 #define USB_USBFRMADJUST_ADJ_SHIFT (0U)
AnnaBridge 143:86740a56073b 11277 #define USB_USBFRMADJUST_ADJ(x) (((uint8_t)(((uint8_t)(x)) << USB_USBFRMADJUST_ADJ_SHIFT)) & USB_USBFRMADJUST_ADJ_MASK)
AnnaBridge 143:86740a56073b 11278
AnnaBridge 143:86740a56073b 11279 /*! @name CLK_RECOVER_CTRL - USB Clock recovery control */
AnnaBridge 143:86740a56073b 11280 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK (0x20U)
AnnaBridge 143:86740a56073b 11281 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT (5U)
AnnaBridge 143:86740a56073b 11282 #define USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESTART_IFRTRIM_EN_MASK)
AnnaBridge 143:86740a56073b 11283 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK (0x40U)
AnnaBridge 143:86740a56073b 11284 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT (6U)
AnnaBridge 143:86740a56073b 11285 #define USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_RESET_RESUME_ROUGH_EN_MASK)
AnnaBridge 143:86740a56073b 11286 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK (0x80U)
AnnaBridge 143:86740a56073b 11287 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT (7U)
AnnaBridge 143:86740a56073b 11288 #define USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_SHIFT)) & USB_CLK_RECOVER_CTRL_CLOCK_RECOVER_EN_MASK)
AnnaBridge 143:86740a56073b 11289
AnnaBridge 143:86740a56073b 11290 /*! @name CLK_RECOVER_IRC_EN - IRC48M oscillator enable register */
AnnaBridge 143:86740a56073b 11291 #define USB_CLK_RECOVER_IRC_EN_REG_EN_MASK (0x1U)
AnnaBridge 143:86740a56073b 11292 #define USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT (0U)
AnnaBridge 143:86740a56073b 11293 #define USB_CLK_RECOVER_IRC_EN_REG_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_REG_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_REG_EN_MASK)
AnnaBridge 143:86740a56073b 11294 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK (0x2U)
AnnaBridge 143:86740a56073b 11295 #define USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT (1U)
AnnaBridge 143:86740a56073b 11296 #define USB_CLK_RECOVER_IRC_EN_IRC_EN(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_IRC_EN_IRC_EN_SHIFT)) & USB_CLK_RECOVER_IRC_EN_IRC_EN_MASK)
AnnaBridge 143:86740a56073b 11297
AnnaBridge 143:86740a56073b 11298 /*! @name CLK_RECOVER_INT_STATUS - Clock recovery separated interrupt status */
AnnaBridge 143:86740a56073b 11299 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK (0x10U)
AnnaBridge 143:86740a56073b 11300 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT (4U)
AnnaBridge 143:86740a56073b 11301 #define USB_CLK_RECOVER_INT_STATUS_OVF_ERROR(x) (((uint8_t)(((uint8_t)(x)) << USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_SHIFT)) & USB_CLK_RECOVER_INT_STATUS_OVF_ERROR_MASK)
AnnaBridge 143:86740a56073b 11302
AnnaBridge 143:86740a56073b 11303
AnnaBridge 143:86740a56073b 11304 /*!
AnnaBridge 143:86740a56073b 11305 * @}
AnnaBridge 143:86740a56073b 11306 */ /* end of group USB_Register_Masks */
AnnaBridge 143:86740a56073b 11307
AnnaBridge 143:86740a56073b 11308
AnnaBridge 143:86740a56073b 11309 /* USB - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 11310 /** Peripheral USB0 base address */
AnnaBridge 143:86740a56073b 11311 #define USB0_BASE (0x40072000u)
AnnaBridge 143:86740a56073b 11312 /** Peripheral USB0 base pointer */
AnnaBridge 143:86740a56073b 11313 #define USB0 ((USB_Type *)USB0_BASE)
AnnaBridge 143:86740a56073b 11314 /** Array initializer of USB peripheral base addresses */
AnnaBridge 143:86740a56073b 11315 #define USB_BASE_ADDRS { USB0_BASE }
AnnaBridge 143:86740a56073b 11316 /** Array initializer of USB peripheral base pointers */
AnnaBridge 143:86740a56073b 11317 #define USB_BASE_PTRS { USB0 }
AnnaBridge 143:86740a56073b 11318 /** Interrupt vectors for the USB peripheral type */
AnnaBridge 143:86740a56073b 11319 #define USB_IRQS { USB0_IRQn }
AnnaBridge 143:86740a56073b 11320
AnnaBridge 143:86740a56073b 11321 /*!
AnnaBridge 143:86740a56073b 11322 * @}
AnnaBridge 143:86740a56073b 11323 */ /* end of group USB_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 11324
AnnaBridge 143:86740a56073b 11325
AnnaBridge 143:86740a56073b 11326 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11327 -- USBDCD Peripheral Access Layer
AnnaBridge 143:86740a56073b 11328 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11329
AnnaBridge 143:86740a56073b 11330 /*!
AnnaBridge 143:86740a56073b 11331 * @addtogroup USBDCD_Peripheral_Access_Layer USBDCD Peripheral Access Layer
AnnaBridge 143:86740a56073b 11332 * @{
AnnaBridge 143:86740a56073b 11333 */
AnnaBridge 143:86740a56073b 11334
AnnaBridge 143:86740a56073b 11335 /** USBDCD - Register Layout Typedef */
AnnaBridge 143:86740a56073b 11336 typedef struct {
AnnaBridge 143:86740a56073b 11337 __IO uint32_t CONTROL; /**< Control register, offset: 0x0 */
AnnaBridge 143:86740a56073b 11338 __IO uint32_t CLOCK; /**< Clock register, offset: 0x4 */
AnnaBridge 143:86740a56073b 11339 __I uint32_t STATUS; /**< Status register, offset: 0x8 */
AnnaBridge 143:86740a56073b 11340 uint8_t RESERVED_0[4];
AnnaBridge 143:86740a56073b 11341 __IO uint32_t TIMER0; /**< TIMER0 register, offset: 0x10 */
AnnaBridge 143:86740a56073b 11342 __IO uint32_t TIMER1; /**< TIMER1 register, offset: 0x14 */
AnnaBridge 143:86740a56073b 11343 union { /* offset: 0x18 */
AnnaBridge 143:86740a56073b 11344 __IO uint32_t TIMER2_BC11; /**< TIMER2_BC11 register, offset: 0x18 */
AnnaBridge 143:86740a56073b 11345 __IO uint32_t TIMER2_BC12; /**< TIMER2_BC12 register, offset: 0x18 */
AnnaBridge 143:86740a56073b 11346 };
AnnaBridge 143:86740a56073b 11347 } USBDCD_Type;
AnnaBridge 143:86740a56073b 11348
AnnaBridge 143:86740a56073b 11349 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11350 -- USBDCD Register Masks
AnnaBridge 143:86740a56073b 11351 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11352
AnnaBridge 143:86740a56073b 11353 /*!
AnnaBridge 143:86740a56073b 11354 * @addtogroup USBDCD_Register_Masks USBDCD Register Masks
AnnaBridge 143:86740a56073b 11355 * @{
AnnaBridge 143:86740a56073b 11356 */
AnnaBridge 143:86740a56073b 11357
AnnaBridge 143:86740a56073b 11358 /*! @name CONTROL - Control register */
AnnaBridge 143:86740a56073b 11359 #define USBDCD_CONTROL_IACK_MASK (0x1U)
AnnaBridge 143:86740a56073b 11360 #define USBDCD_CONTROL_IACK_SHIFT (0U)
AnnaBridge 143:86740a56073b 11361 #define USBDCD_CONTROL_IACK(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IACK_SHIFT)) & USBDCD_CONTROL_IACK_MASK)
AnnaBridge 143:86740a56073b 11362 #define USBDCD_CONTROL_IF_MASK (0x100U)
AnnaBridge 143:86740a56073b 11363 #define USBDCD_CONTROL_IF_SHIFT (8U)
AnnaBridge 143:86740a56073b 11364 #define USBDCD_CONTROL_IF(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IF_SHIFT)) & USBDCD_CONTROL_IF_MASK)
AnnaBridge 143:86740a56073b 11365 #define USBDCD_CONTROL_IE_MASK (0x10000U)
AnnaBridge 143:86740a56073b 11366 #define USBDCD_CONTROL_IE_SHIFT (16U)
AnnaBridge 143:86740a56073b 11367 #define USBDCD_CONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_IE_SHIFT)) & USBDCD_CONTROL_IE_MASK)
AnnaBridge 143:86740a56073b 11368 #define USBDCD_CONTROL_BC12_MASK (0x20000U)
AnnaBridge 143:86740a56073b 11369 #define USBDCD_CONTROL_BC12_SHIFT (17U)
AnnaBridge 143:86740a56073b 11370 #define USBDCD_CONTROL_BC12(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_BC12_SHIFT)) & USBDCD_CONTROL_BC12_MASK)
AnnaBridge 143:86740a56073b 11371 #define USBDCD_CONTROL_START_MASK (0x1000000U)
AnnaBridge 143:86740a56073b 11372 #define USBDCD_CONTROL_START_SHIFT (24U)
AnnaBridge 143:86740a56073b 11373 #define USBDCD_CONTROL_START(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_START_SHIFT)) & USBDCD_CONTROL_START_MASK)
AnnaBridge 143:86740a56073b 11374 #define USBDCD_CONTROL_SR_MASK (0x2000000U)
AnnaBridge 143:86740a56073b 11375 #define USBDCD_CONTROL_SR_SHIFT (25U)
AnnaBridge 143:86740a56073b 11376 #define USBDCD_CONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CONTROL_SR_SHIFT)) & USBDCD_CONTROL_SR_MASK)
AnnaBridge 143:86740a56073b 11377
AnnaBridge 143:86740a56073b 11378 /*! @name CLOCK - Clock register */
AnnaBridge 143:86740a56073b 11379 #define USBDCD_CLOCK_CLOCK_UNIT_MASK (0x1U)
AnnaBridge 143:86740a56073b 11380 #define USBDCD_CLOCK_CLOCK_UNIT_SHIFT (0U)
AnnaBridge 143:86740a56073b 11381 #define USBDCD_CLOCK_CLOCK_UNIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_UNIT_SHIFT)) & USBDCD_CLOCK_CLOCK_UNIT_MASK)
AnnaBridge 143:86740a56073b 11382 #define USBDCD_CLOCK_CLOCK_SPEED_MASK (0xFFCU)
AnnaBridge 143:86740a56073b 11383 #define USBDCD_CLOCK_CLOCK_SPEED_SHIFT (2U)
AnnaBridge 143:86740a56073b 11384 #define USBDCD_CLOCK_CLOCK_SPEED(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_CLOCK_CLOCK_SPEED_SHIFT)) & USBDCD_CLOCK_CLOCK_SPEED_MASK)
AnnaBridge 143:86740a56073b 11385
AnnaBridge 143:86740a56073b 11386 /*! @name STATUS - Status register */
AnnaBridge 143:86740a56073b 11387 #define USBDCD_STATUS_SEQ_RES_MASK (0x30000U)
AnnaBridge 143:86740a56073b 11388 #define USBDCD_STATUS_SEQ_RES_SHIFT (16U)
AnnaBridge 143:86740a56073b 11389 #define USBDCD_STATUS_SEQ_RES(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_RES_SHIFT)) & USBDCD_STATUS_SEQ_RES_MASK)
AnnaBridge 143:86740a56073b 11390 #define USBDCD_STATUS_SEQ_STAT_MASK (0xC0000U)
AnnaBridge 143:86740a56073b 11391 #define USBDCD_STATUS_SEQ_STAT_SHIFT (18U)
AnnaBridge 143:86740a56073b 11392 #define USBDCD_STATUS_SEQ_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_SEQ_STAT_SHIFT)) & USBDCD_STATUS_SEQ_STAT_MASK)
AnnaBridge 143:86740a56073b 11393 #define USBDCD_STATUS_ERR_MASK (0x100000U)
AnnaBridge 143:86740a56073b 11394 #define USBDCD_STATUS_ERR_SHIFT (20U)
AnnaBridge 143:86740a56073b 11395 #define USBDCD_STATUS_ERR(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ERR_SHIFT)) & USBDCD_STATUS_ERR_MASK)
AnnaBridge 143:86740a56073b 11396 #define USBDCD_STATUS_TO_MASK (0x200000U)
AnnaBridge 143:86740a56073b 11397 #define USBDCD_STATUS_TO_SHIFT (21U)
AnnaBridge 143:86740a56073b 11398 #define USBDCD_STATUS_TO(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_TO_SHIFT)) & USBDCD_STATUS_TO_MASK)
AnnaBridge 143:86740a56073b 11399 #define USBDCD_STATUS_ACTIVE_MASK (0x400000U)
AnnaBridge 143:86740a56073b 11400 #define USBDCD_STATUS_ACTIVE_SHIFT (22U)
AnnaBridge 143:86740a56073b 11401 #define USBDCD_STATUS_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_STATUS_ACTIVE_SHIFT)) & USBDCD_STATUS_ACTIVE_MASK)
AnnaBridge 143:86740a56073b 11402
AnnaBridge 143:86740a56073b 11403 /*! @name TIMER0 - TIMER0 register */
AnnaBridge 143:86740a56073b 11404 #define USBDCD_TIMER0_TUNITCON_MASK (0xFFFU)
AnnaBridge 143:86740a56073b 11405 #define USBDCD_TIMER0_TUNITCON_SHIFT (0U)
AnnaBridge 143:86740a56073b 11406 #define USBDCD_TIMER0_TUNITCON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TUNITCON_SHIFT)) & USBDCD_TIMER0_TUNITCON_MASK)
AnnaBridge 143:86740a56073b 11407 #define USBDCD_TIMER0_TSEQ_INIT_MASK (0x3FF0000U)
AnnaBridge 143:86740a56073b 11408 #define USBDCD_TIMER0_TSEQ_INIT_SHIFT (16U)
AnnaBridge 143:86740a56073b 11409 #define USBDCD_TIMER0_TSEQ_INIT(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER0_TSEQ_INIT_SHIFT)) & USBDCD_TIMER0_TSEQ_INIT_MASK)
AnnaBridge 143:86740a56073b 11410
AnnaBridge 143:86740a56073b 11411 /*! @name TIMER1 - TIMER1 register */
AnnaBridge 143:86740a56073b 11412 #define USBDCD_TIMER1_TVDPSRC_ON_MASK (0x3FFU)
AnnaBridge 143:86740a56073b 11413 #define USBDCD_TIMER1_TVDPSRC_ON_SHIFT (0U)
AnnaBridge 143:86740a56073b 11414 #define USBDCD_TIMER1_TVDPSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TVDPSRC_ON_SHIFT)) & USBDCD_TIMER1_TVDPSRC_ON_MASK)
AnnaBridge 143:86740a56073b 11415 #define USBDCD_TIMER1_TDCD_DBNC_MASK (0x3FF0000U)
AnnaBridge 143:86740a56073b 11416 #define USBDCD_TIMER1_TDCD_DBNC_SHIFT (16U)
AnnaBridge 143:86740a56073b 11417 #define USBDCD_TIMER1_TDCD_DBNC(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER1_TDCD_DBNC_SHIFT)) & USBDCD_TIMER1_TDCD_DBNC_MASK)
AnnaBridge 143:86740a56073b 11418
AnnaBridge 143:86740a56073b 11419 /*! @name TIMER2_BC11 - TIMER2_BC11 register */
AnnaBridge 143:86740a56073b 11420 #define USBDCD_TIMER2_BC11_CHECK_DM_MASK (0xFU)
AnnaBridge 143:86740a56073b 11421 #define USBDCD_TIMER2_BC11_CHECK_DM_SHIFT (0U)
AnnaBridge 143:86740a56073b 11422 #define USBDCD_TIMER2_BC11_CHECK_DM(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_CHECK_DM_SHIFT)) & USBDCD_TIMER2_BC11_CHECK_DM_MASK)
AnnaBridge 143:86740a56073b 11423 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK (0x3FF0000U)
AnnaBridge 143:86740a56073b 11424 #define USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT (16U)
AnnaBridge 143:86740a56073b 11425 #define USBDCD_TIMER2_BC11_TVDPSRC_CON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC11_TVDPSRC_CON_SHIFT)) & USBDCD_TIMER2_BC11_TVDPSRC_CON_MASK)
AnnaBridge 143:86740a56073b 11426
AnnaBridge 143:86740a56073b 11427 /*! @name TIMER2_BC12 - TIMER2_BC12 register */
AnnaBridge 143:86740a56073b 11428 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK (0x3FFU)
AnnaBridge 143:86740a56073b 11429 #define USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT (0U)
AnnaBridge 143:86740a56073b 11430 #define USBDCD_TIMER2_BC12_TVDMSRC_ON(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TVDMSRC_ON_SHIFT)) & USBDCD_TIMER2_BC12_TVDMSRC_ON_MASK)
AnnaBridge 143:86740a56073b 11431 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK (0x3FF0000U)
AnnaBridge 143:86740a56073b 11432 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT (16U)
AnnaBridge 143:86740a56073b 11433 #define USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD(x) (((uint32_t)(((uint32_t)(x)) << USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_SHIFT)) & USBDCD_TIMER2_BC12_TWAIT_AFTER_PRD_MASK)
AnnaBridge 143:86740a56073b 11434
AnnaBridge 143:86740a56073b 11435
AnnaBridge 143:86740a56073b 11436 /*!
AnnaBridge 143:86740a56073b 11437 * @}
AnnaBridge 143:86740a56073b 11438 */ /* end of group USBDCD_Register_Masks */
AnnaBridge 143:86740a56073b 11439
AnnaBridge 143:86740a56073b 11440
AnnaBridge 143:86740a56073b 11441 /* USBDCD - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 11442 /** Peripheral USBDCD base address */
AnnaBridge 143:86740a56073b 11443 #define USBDCD_BASE (0x40035000u)
AnnaBridge 143:86740a56073b 11444 /** Peripheral USBDCD base pointer */
AnnaBridge 143:86740a56073b 11445 #define USBDCD ((USBDCD_Type *)USBDCD_BASE)
AnnaBridge 143:86740a56073b 11446 /** Array initializer of USBDCD peripheral base addresses */
AnnaBridge 143:86740a56073b 11447 #define USBDCD_BASE_ADDRS { USBDCD_BASE }
AnnaBridge 143:86740a56073b 11448 /** Array initializer of USBDCD peripheral base pointers */
AnnaBridge 143:86740a56073b 11449 #define USBDCD_BASE_PTRS { USBDCD }
AnnaBridge 143:86740a56073b 11450 /** Interrupt vectors for the USBDCD peripheral type */
AnnaBridge 143:86740a56073b 11451 #define USBDCD_IRQS { USBDCD_IRQn }
AnnaBridge 143:86740a56073b 11452
AnnaBridge 143:86740a56073b 11453 /*!
AnnaBridge 143:86740a56073b 11454 * @}
AnnaBridge 143:86740a56073b 11455 */ /* end of group USBDCD_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 11456
AnnaBridge 143:86740a56073b 11457
AnnaBridge 143:86740a56073b 11458 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11459 -- VREF Peripheral Access Layer
AnnaBridge 143:86740a56073b 11460 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11461
AnnaBridge 143:86740a56073b 11462 /*!
AnnaBridge 143:86740a56073b 11463 * @addtogroup VREF_Peripheral_Access_Layer VREF Peripheral Access Layer
AnnaBridge 143:86740a56073b 11464 * @{
AnnaBridge 143:86740a56073b 11465 */
AnnaBridge 143:86740a56073b 11466
AnnaBridge 143:86740a56073b 11467 /** VREF - Register Layout Typedef */
AnnaBridge 143:86740a56073b 11468 typedef struct {
AnnaBridge 143:86740a56073b 11469 __IO uint8_t TRM; /**< VREF Trim Register, offset: 0x0 */
AnnaBridge 143:86740a56073b 11470 __IO uint8_t SC; /**< VREF Status and Control Register, offset: 0x1 */
AnnaBridge 143:86740a56073b 11471 } VREF_Type;
AnnaBridge 143:86740a56073b 11472
AnnaBridge 143:86740a56073b 11473 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11474 -- VREF Register Masks
AnnaBridge 143:86740a56073b 11475 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11476
AnnaBridge 143:86740a56073b 11477 /*!
AnnaBridge 143:86740a56073b 11478 * @addtogroup VREF_Register_Masks VREF Register Masks
AnnaBridge 143:86740a56073b 11479 * @{
AnnaBridge 143:86740a56073b 11480 */
AnnaBridge 143:86740a56073b 11481
AnnaBridge 143:86740a56073b 11482 /*! @name TRM - VREF Trim Register */
AnnaBridge 143:86740a56073b 11483 #define VREF_TRM_TRIM_MASK (0x3FU)
AnnaBridge 143:86740a56073b 11484 #define VREF_TRM_TRIM_SHIFT (0U)
AnnaBridge 143:86740a56073b 11485 #define VREF_TRM_TRIM(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_TRIM_SHIFT)) & VREF_TRM_TRIM_MASK)
AnnaBridge 143:86740a56073b 11486 #define VREF_TRM_CHOPEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 11487 #define VREF_TRM_CHOPEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 11488 #define VREF_TRM_CHOPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_TRM_CHOPEN_SHIFT)) & VREF_TRM_CHOPEN_MASK)
AnnaBridge 143:86740a56073b 11489
AnnaBridge 143:86740a56073b 11490 /*! @name SC - VREF Status and Control Register */
AnnaBridge 143:86740a56073b 11491 #define VREF_SC_MODE_LV_MASK (0x3U)
AnnaBridge 143:86740a56073b 11492 #define VREF_SC_MODE_LV_SHIFT (0U)
AnnaBridge 143:86740a56073b 11493 #define VREF_SC_MODE_LV(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_MODE_LV_SHIFT)) & VREF_SC_MODE_LV_MASK)
AnnaBridge 143:86740a56073b 11494 #define VREF_SC_VREFST_MASK (0x4U)
AnnaBridge 143:86740a56073b 11495 #define VREF_SC_VREFST_SHIFT (2U)
AnnaBridge 143:86740a56073b 11496 #define VREF_SC_VREFST(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFST_SHIFT)) & VREF_SC_VREFST_MASK)
AnnaBridge 143:86740a56073b 11497 #define VREF_SC_ICOMPEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 11498 #define VREF_SC_ICOMPEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 11499 #define VREF_SC_ICOMPEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_ICOMPEN_SHIFT)) & VREF_SC_ICOMPEN_MASK)
AnnaBridge 143:86740a56073b 11500 #define VREF_SC_REGEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 11501 #define VREF_SC_REGEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 11502 #define VREF_SC_REGEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_REGEN_SHIFT)) & VREF_SC_REGEN_MASK)
AnnaBridge 143:86740a56073b 11503 #define VREF_SC_VREFEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 11504 #define VREF_SC_VREFEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 11505 #define VREF_SC_VREFEN(x) (((uint8_t)(((uint8_t)(x)) << VREF_SC_VREFEN_SHIFT)) & VREF_SC_VREFEN_MASK)
AnnaBridge 143:86740a56073b 11506
AnnaBridge 143:86740a56073b 11507
AnnaBridge 143:86740a56073b 11508 /*!
AnnaBridge 143:86740a56073b 11509 * @}
AnnaBridge 143:86740a56073b 11510 */ /* end of group VREF_Register_Masks */
AnnaBridge 143:86740a56073b 11511
AnnaBridge 143:86740a56073b 11512
AnnaBridge 143:86740a56073b 11513 /* VREF - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 11514 /** Peripheral VREF base address */
AnnaBridge 143:86740a56073b 11515 #define VREF_BASE (0x40074000u)
AnnaBridge 143:86740a56073b 11516 /** Peripheral VREF base pointer */
AnnaBridge 143:86740a56073b 11517 #define VREF ((VREF_Type *)VREF_BASE)
AnnaBridge 143:86740a56073b 11518 /** Array initializer of VREF peripheral base addresses */
AnnaBridge 143:86740a56073b 11519 #define VREF_BASE_ADDRS { VREF_BASE }
AnnaBridge 143:86740a56073b 11520 /** Array initializer of VREF peripheral base pointers */
AnnaBridge 143:86740a56073b 11521 #define VREF_BASE_PTRS { VREF }
AnnaBridge 143:86740a56073b 11522
AnnaBridge 143:86740a56073b 11523 /*!
AnnaBridge 143:86740a56073b 11524 * @}
AnnaBridge 143:86740a56073b 11525 */ /* end of group VREF_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 11526
AnnaBridge 143:86740a56073b 11527
AnnaBridge 143:86740a56073b 11528 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11529 -- WDOG Peripheral Access Layer
AnnaBridge 143:86740a56073b 11530 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11531
AnnaBridge 143:86740a56073b 11532 /*!
AnnaBridge 143:86740a56073b 11533 * @addtogroup WDOG_Peripheral_Access_Layer WDOG Peripheral Access Layer
AnnaBridge 143:86740a56073b 11534 * @{
AnnaBridge 143:86740a56073b 11535 */
AnnaBridge 143:86740a56073b 11536
AnnaBridge 143:86740a56073b 11537 /** WDOG - Register Layout Typedef */
AnnaBridge 143:86740a56073b 11538 typedef struct {
AnnaBridge 143:86740a56073b 11539 __IO uint16_t STCTRLH; /**< Watchdog Status and Control Register High, offset: 0x0 */
AnnaBridge 143:86740a56073b 11540 __IO uint16_t STCTRLL; /**< Watchdog Status and Control Register Low, offset: 0x2 */
AnnaBridge 143:86740a56073b 11541 __IO uint16_t TOVALH; /**< Watchdog Time-out Value Register High, offset: 0x4 */
AnnaBridge 143:86740a56073b 11542 __IO uint16_t TOVALL; /**< Watchdog Time-out Value Register Low, offset: 0x6 */
AnnaBridge 143:86740a56073b 11543 __IO uint16_t WINH; /**< Watchdog Window Register High, offset: 0x8 */
AnnaBridge 143:86740a56073b 11544 __IO uint16_t WINL; /**< Watchdog Window Register Low, offset: 0xA */
AnnaBridge 143:86740a56073b 11545 __IO uint16_t REFRESH; /**< Watchdog Refresh register, offset: 0xC */
AnnaBridge 143:86740a56073b 11546 __IO uint16_t UNLOCK; /**< Watchdog Unlock register, offset: 0xE */
AnnaBridge 143:86740a56073b 11547 __IO uint16_t TMROUTH; /**< Watchdog Timer Output Register High, offset: 0x10 */
AnnaBridge 143:86740a56073b 11548 __IO uint16_t TMROUTL; /**< Watchdog Timer Output Register Low, offset: 0x12 */
AnnaBridge 143:86740a56073b 11549 __IO uint16_t RSTCNT; /**< Watchdog Reset Count register, offset: 0x14 */
AnnaBridge 143:86740a56073b 11550 __IO uint16_t PRESC; /**< Watchdog Prescaler register, offset: 0x16 */
AnnaBridge 143:86740a56073b 11551 } WDOG_Type;
AnnaBridge 143:86740a56073b 11552
AnnaBridge 143:86740a56073b 11553 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11554 -- WDOG Register Masks
AnnaBridge 143:86740a56073b 11555 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11556
AnnaBridge 143:86740a56073b 11557 /*!
AnnaBridge 143:86740a56073b 11558 * @addtogroup WDOG_Register_Masks WDOG Register Masks
AnnaBridge 143:86740a56073b 11559 * @{
AnnaBridge 143:86740a56073b 11560 */
AnnaBridge 143:86740a56073b 11561
AnnaBridge 143:86740a56073b 11562 /*! @name STCTRLH - Watchdog Status and Control Register High */
AnnaBridge 143:86740a56073b 11563 #define WDOG_STCTRLH_WDOGEN_MASK (0x1U)
AnnaBridge 143:86740a56073b 11564 #define WDOG_STCTRLH_WDOGEN_SHIFT (0U)
AnnaBridge 143:86740a56073b 11565 #define WDOG_STCTRLH_WDOGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WDOGEN_SHIFT)) & WDOG_STCTRLH_WDOGEN_MASK)
AnnaBridge 143:86740a56073b 11566 #define WDOG_STCTRLH_CLKSRC_MASK (0x2U)
AnnaBridge 143:86740a56073b 11567 #define WDOG_STCTRLH_CLKSRC_SHIFT (1U)
AnnaBridge 143:86740a56073b 11568 #define WDOG_STCTRLH_CLKSRC(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_CLKSRC_SHIFT)) & WDOG_STCTRLH_CLKSRC_MASK)
AnnaBridge 143:86740a56073b 11569 #define WDOG_STCTRLH_IRQRSTEN_MASK (0x4U)
AnnaBridge 143:86740a56073b 11570 #define WDOG_STCTRLH_IRQRSTEN_SHIFT (2U)
AnnaBridge 143:86740a56073b 11571 #define WDOG_STCTRLH_IRQRSTEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_IRQRSTEN_SHIFT)) & WDOG_STCTRLH_IRQRSTEN_MASK)
AnnaBridge 143:86740a56073b 11572 #define WDOG_STCTRLH_WINEN_MASK (0x8U)
AnnaBridge 143:86740a56073b 11573 #define WDOG_STCTRLH_WINEN_SHIFT (3U)
AnnaBridge 143:86740a56073b 11574 #define WDOG_STCTRLH_WINEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WINEN_SHIFT)) & WDOG_STCTRLH_WINEN_MASK)
AnnaBridge 143:86740a56073b 11575 #define WDOG_STCTRLH_ALLOWUPDATE_MASK (0x10U)
AnnaBridge 143:86740a56073b 11576 #define WDOG_STCTRLH_ALLOWUPDATE_SHIFT (4U)
AnnaBridge 143:86740a56073b 11577 #define WDOG_STCTRLH_ALLOWUPDATE(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_ALLOWUPDATE_SHIFT)) & WDOG_STCTRLH_ALLOWUPDATE_MASK)
AnnaBridge 143:86740a56073b 11578 #define WDOG_STCTRLH_DBGEN_MASK (0x20U)
AnnaBridge 143:86740a56073b 11579 #define WDOG_STCTRLH_DBGEN_SHIFT (5U)
AnnaBridge 143:86740a56073b 11580 #define WDOG_STCTRLH_DBGEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DBGEN_SHIFT)) & WDOG_STCTRLH_DBGEN_MASK)
AnnaBridge 143:86740a56073b 11581 #define WDOG_STCTRLH_STOPEN_MASK (0x40U)
AnnaBridge 143:86740a56073b 11582 #define WDOG_STCTRLH_STOPEN_SHIFT (6U)
AnnaBridge 143:86740a56073b 11583 #define WDOG_STCTRLH_STOPEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_STOPEN_SHIFT)) & WDOG_STCTRLH_STOPEN_MASK)
AnnaBridge 143:86740a56073b 11584 #define WDOG_STCTRLH_WAITEN_MASK (0x80U)
AnnaBridge 143:86740a56073b 11585 #define WDOG_STCTRLH_WAITEN_SHIFT (7U)
AnnaBridge 143:86740a56073b 11586 #define WDOG_STCTRLH_WAITEN(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_WAITEN_SHIFT)) & WDOG_STCTRLH_WAITEN_MASK)
AnnaBridge 143:86740a56073b 11587 #define WDOG_STCTRLH_TESTWDOG_MASK (0x400U)
AnnaBridge 143:86740a56073b 11588 #define WDOG_STCTRLH_TESTWDOG_SHIFT (10U)
AnnaBridge 143:86740a56073b 11589 #define WDOG_STCTRLH_TESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTWDOG_SHIFT)) & WDOG_STCTRLH_TESTWDOG_MASK)
AnnaBridge 143:86740a56073b 11590 #define WDOG_STCTRLH_TESTSEL_MASK (0x800U)
AnnaBridge 143:86740a56073b 11591 #define WDOG_STCTRLH_TESTSEL_SHIFT (11U)
AnnaBridge 143:86740a56073b 11592 #define WDOG_STCTRLH_TESTSEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_TESTSEL_SHIFT)) & WDOG_STCTRLH_TESTSEL_MASK)
AnnaBridge 143:86740a56073b 11593 #define WDOG_STCTRLH_BYTESEL_MASK (0x3000U)
AnnaBridge 143:86740a56073b 11594 #define WDOG_STCTRLH_BYTESEL_SHIFT (12U)
AnnaBridge 143:86740a56073b 11595 #define WDOG_STCTRLH_BYTESEL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_BYTESEL_SHIFT)) & WDOG_STCTRLH_BYTESEL_MASK)
AnnaBridge 143:86740a56073b 11596 #define WDOG_STCTRLH_DISTESTWDOG_MASK (0x4000U)
AnnaBridge 143:86740a56073b 11597 #define WDOG_STCTRLH_DISTESTWDOG_SHIFT (14U)
AnnaBridge 143:86740a56073b 11598 #define WDOG_STCTRLH_DISTESTWDOG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLH_DISTESTWDOG_SHIFT)) & WDOG_STCTRLH_DISTESTWDOG_MASK)
AnnaBridge 143:86740a56073b 11599
AnnaBridge 143:86740a56073b 11600 /*! @name STCTRLL - Watchdog Status and Control Register Low */
AnnaBridge 143:86740a56073b 11601 #define WDOG_STCTRLL_INTFLG_MASK (0x8000U)
AnnaBridge 143:86740a56073b 11602 #define WDOG_STCTRLL_INTFLG_SHIFT (15U)
AnnaBridge 143:86740a56073b 11603 #define WDOG_STCTRLL_INTFLG(x) (((uint16_t)(((uint16_t)(x)) << WDOG_STCTRLL_INTFLG_SHIFT)) & WDOG_STCTRLL_INTFLG_MASK)
AnnaBridge 143:86740a56073b 11604
AnnaBridge 143:86740a56073b 11605 /*! @name TOVALH - Watchdog Time-out Value Register High */
AnnaBridge 143:86740a56073b 11606 #define WDOG_TOVALH_TOVALHIGH_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11607 #define WDOG_TOVALH_TOVALHIGH_SHIFT (0U)
AnnaBridge 143:86740a56073b 11608 #define WDOG_TOVALH_TOVALHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALH_TOVALHIGH_SHIFT)) & WDOG_TOVALH_TOVALHIGH_MASK)
AnnaBridge 143:86740a56073b 11609
AnnaBridge 143:86740a56073b 11610 /*! @name TOVALL - Watchdog Time-out Value Register Low */
AnnaBridge 143:86740a56073b 11611 #define WDOG_TOVALL_TOVALLOW_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11612 #define WDOG_TOVALL_TOVALLOW_SHIFT (0U)
AnnaBridge 143:86740a56073b 11613 #define WDOG_TOVALL_TOVALLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TOVALL_TOVALLOW_SHIFT)) & WDOG_TOVALL_TOVALLOW_MASK)
AnnaBridge 143:86740a56073b 11614
AnnaBridge 143:86740a56073b 11615 /*! @name WINH - Watchdog Window Register High */
AnnaBridge 143:86740a56073b 11616 #define WDOG_WINH_WINHIGH_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11617 #define WDOG_WINH_WINHIGH_SHIFT (0U)
AnnaBridge 143:86740a56073b 11618 #define WDOG_WINH_WINHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINH_WINHIGH_SHIFT)) & WDOG_WINH_WINHIGH_MASK)
AnnaBridge 143:86740a56073b 11619
AnnaBridge 143:86740a56073b 11620 /*! @name WINL - Watchdog Window Register Low */
AnnaBridge 143:86740a56073b 11621 #define WDOG_WINL_WINLOW_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11622 #define WDOG_WINL_WINLOW_SHIFT (0U)
AnnaBridge 143:86740a56073b 11623 #define WDOG_WINL_WINLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_WINL_WINLOW_SHIFT)) & WDOG_WINL_WINLOW_MASK)
AnnaBridge 143:86740a56073b 11624
AnnaBridge 143:86740a56073b 11625 /*! @name REFRESH - Watchdog Refresh register */
AnnaBridge 143:86740a56073b 11626 #define WDOG_REFRESH_WDOGREFRESH_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11627 #define WDOG_REFRESH_WDOGREFRESH_SHIFT (0U)
AnnaBridge 143:86740a56073b 11628 #define WDOG_REFRESH_WDOGREFRESH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_REFRESH_WDOGREFRESH_SHIFT)) & WDOG_REFRESH_WDOGREFRESH_MASK)
AnnaBridge 143:86740a56073b 11629
AnnaBridge 143:86740a56073b 11630 /*! @name UNLOCK - Watchdog Unlock register */
AnnaBridge 143:86740a56073b 11631 #define WDOG_UNLOCK_WDOGUNLOCK_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11632 #define WDOG_UNLOCK_WDOGUNLOCK_SHIFT (0U)
AnnaBridge 143:86740a56073b 11633 #define WDOG_UNLOCK_WDOGUNLOCK(x) (((uint16_t)(((uint16_t)(x)) << WDOG_UNLOCK_WDOGUNLOCK_SHIFT)) & WDOG_UNLOCK_WDOGUNLOCK_MASK)
AnnaBridge 143:86740a56073b 11634
AnnaBridge 143:86740a56073b 11635 /*! @name TMROUTH - Watchdog Timer Output Register High */
AnnaBridge 143:86740a56073b 11636 #define WDOG_TMROUTH_TIMEROUTHIGH_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11637 #define WDOG_TMROUTH_TIMEROUTHIGH_SHIFT (0U)
AnnaBridge 143:86740a56073b 11638 #define WDOG_TMROUTH_TIMEROUTHIGH(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTH_TIMEROUTHIGH_SHIFT)) & WDOG_TMROUTH_TIMEROUTHIGH_MASK)
AnnaBridge 143:86740a56073b 11639
AnnaBridge 143:86740a56073b 11640 /*! @name TMROUTL - Watchdog Timer Output Register Low */
AnnaBridge 143:86740a56073b 11641 #define WDOG_TMROUTL_TIMEROUTLOW_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11642 #define WDOG_TMROUTL_TIMEROUTLOW_SHIFT (0U)
AnnaBridge 143:86740a56073b 11643 #define WDOG_TMROUTL_TIMEROUTLOW(x) (((uint16_t)(((uint16_t)(x)) << WDOG_TMROUTL_TIMEROUTLOW_SHIFT)) & WDOG_TMROUTL_TIMEROUTLOW_MASK)
AnnaBridge 143:86740a56073b 11644
AnnaBridge 143:86740a56073b 11645 /*! @name RSTCNT - Watchdog Reset Count register */
AnnaBridge 143:86740a56073b 11646 #define WDOG_RSTCNT_RSTCNT_MASK (0xFFFFU)
AnnaBridge 143:86740a56073b 11647 #define WDOG_RSTCNT_RSTCNT_SHIFT (0U)
AnnaBridge 143:86740a56073b 11648 #define WDOG_RSTCNT_RSTCNT(x) (((uint16_t)(((uint16_t)(x)) << WDOG_RSTCNT_RSTCNT_SHIFT)) & WDOG_RSTCNT_RSTCNT_MASK)
AnnaBridge 143:86740a56073b 11649
AnnaBridge 143:86740a56073b 11650 /*! @name PRESC - Watchdog Prescaler register */
AnnaBridge 143:86740a56073b 11651 #define WDOG_PRESC_PRESCVAL_MASK (0x700U)
AnnaBridge 143:86740a56073b 11652 #define WDOG_PRESC_PRESCVAL_SHIFT (8U)
AnnaBridge 143:86740a56073b 11653 #define WDOG_PRESC_PRESCVAL(x) (((uint16_t)(((uint16_t)(x)) << WDOG_PRESC_PRESCVAL_SHIFT)) & WDOG_PRESC_PRESCVAL_MASK)
AnnaBridge 143:86740a56073b 11654
AnnaBridge 143:86740a56073b 11655
AnnaBridge 143:86740a56073b 11656 /*!
AnnaBridge 143:86740a56073b 11657 * @}
AnnaBridge 143:86740a56073b 11658 */ /* end of group WDOG_Register_Masks */
AnnaBridge 143:86740a56073b 11659
AnnaBridge 143:86740a56073b 11660
AnnaBridge 143:86740a56073b 11661 /* WDOG - Peripheral instance base addresses */
AnnaBridge 143:86740a56073b 11662 /** Peripheral WDOG base address */
AnnaBridge 143:86740a56073b 11663 #define WDOG_BASE (0x40052000u)
AnnaBridge 143:86740a56073b 11664 /** Peripheral WDOG base pointer */
AnnaBridge 143:86740a56073b 11665 #define WDOG ((WDOG_Type *)WDOG_BASE)
AnnaBridge 143:86740a56073b 11666 /** Array initializer of WDOG peripheral base addresses */
AnnaBridge 143:86740a56073b 11667 #define WDOG_BASE_ADDRS { WDOG_BASE }
AnnaBridge 143:86740a56073b 11668 /** Array initializer of WDOG peripheral base pointers */
AnnaBridge 143:86740a56073b 11669 #define WDOG_BASE_PTRS { WDOG }
AnnaBridge 143:86740a56073b 11670 /** Interrupt vectors for the WDOG peripheral type */
AnnaBridge 143:86740a56073b 11671 #define WDOG_IRQS { WDOG_EWM_IRQn }
AnnaBridge 143:86740a56073b 11672
AnnaBridge 143:86740a56073b 11673 /*!
AnnaBridge 143:86740a56073b 11674 * @}
AnnaBridge 143:86740a56073b 11675 */ /* end of group WDOG_Peripheral_Access_Layer */
AnnaBridge 143:86740a56073b 11676
AnnaBridge 143:86740a56073b 11677
AnnaBridge 143:86740a56073b 11678 /*
AnnaBridge 143:86740a56073b 11679 ** End of section using anonymous unions
AnnaBridge 143:86740a56073b 11680 */
AnnaBridge 143:86740a56073b 11681
AnnaBridge 143:86740a56073b 11682 #if defined(__ARMCC_VERSION)
AnnaBridge 143:86740a56073b 11683 #pragma pop
AnnaBridge 143:86740a56073b 11684 #elif defined(__CWCC__)
AnnaBridge 143:86740a56073b 11685 #pragma pop
AnnaBridge 143:86740a56073b 11686 #elif defined(__GNUC__)
AnnaBridge 143:86740a56073b 11687 /* leave anonymous unions enabled */
AnnaBridge 143:86740a56073b 11688 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 143:86740a56073b 11689 #pragma language=default
AnnaBridge 143:86740a56073b 11690 #else
AnnaBridge 143:86740a56073b 11691 #error Not supported compiler type
AnnaBridge 143:86740a56073b 11692 #endif
AnnaBridge 143:86740a56073b 11693
AnnaBridge 143:86740a56073b 11694 /*!
AnnaBridge 143:86740a56073b 11695 * @}
AnnaBridge 143:86740a56073b 11696 */ /* end of group Peripheral_access_layer */
AnnaBridge 143:86740a56073b 11697
AnnaBridge 143:86740a56073b 11698
AnnaBridge 143:86740a56073b 11699 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11700 -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
AnnaBridge 143:86740a56073b 11701 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11702
AnnaBridge 143:86740a56073b 11703 /*!
AnnaBridge 143:86740a56073b 11704 * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
AnnaBridge 143:86740a56073b 11705 * @{
AnnaBridge 143:86740a56073b 11706 */
AnnaBridge 143:86740a56073b 11707
AnnaBridge 143:86740a56073b 11708 #if defined(__ARMCC_VERSION)
AnnaBridge 143:86740a56073b 11709 #if (__ARMCC_VERSION >= 6010050)
AnnaBridge 143:86740a56073b 11710 #pragma clang system_header
AnnaBridge 143:86740a56073b 11711 #endif
AnnaBridge 143:86740a56073b 11712 #elif defined(__IAR_SYSTEMS_ICC__)
AnnaBridge 143:86740a56073b 11713 #pragma system_include
AnnaBridge 143:86740a56073b 11714 #endif
AnnaBridge 143:86740a56073b 11715
AnnaBridge 143:86740a56073b 11716 /**
AnnaBridge 143:86740a56073b 11717 * @brief Mask and left-shift a bit field value for use in a register bit range.
AnnaBridge 143:86740a56073b 11718 * @param field Name of the register bit field.
AnnaBridge 143:86740a56073b 11719 * @param value Value of the bit field.
AnnaBridge 143:86740a56073b 11720 * @return Masked and shifted value.
AnnaBridge 143:86740a56073b 11721 */
AnnaBridge 143:86740a56073b 11722 #define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
AnnaBridge 143:86740a56073b 11723 /**
AnnaBridge 143:86740a56073b 11724 * @brief Mask and right-shift a register value to extract a bit field value.
AnnaBridge 143:86740a56073b 11725 * @param field Name of the register bit field.
AnnaBridge 143:86740a56073b 11726 * @param value Value of the register.
AnnaBridge 143:86740a56073b 11727 * @return Masked and shifted bit field value.
AnnaBridge 143:86740a56073b 11728 */
AnnaBridge 143:86740a56073b 11729 #define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
AnnaBridge 143:86740a56073b 11730
AnnaBridge 143:86740a56073b 11731 /*!
AnnaBridge 143:86740a56073b 11732 * @}
AnnaBridge 143:86740a56073b 11733 */ /* end of group Bit_Field_Generic_Macros */
AnnaBridge 143:86740a56073b 11734
AnnaBridge 143:86740a56073b 11735
AnnaBridge 143:86740a56073b 11736 /* ----------------------------------------------------------------------------
AnnaBridge 143:86740a56073b 11737 -- SDK Compatibility
AnnaBridge 143:86740a56073b 11738 ---------------------------------------------------------------------------- */
AnnaBridge 143:86740a56073b 11739
AnnaBridge 143:86740a56073b 11740 /*!
AnnaBridge 143:86740a56073b 11741 * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
AnnaBridge 143:86740a56073b 11742 * @{
AnnaBridge 143:86740a56073b 11743 */
AnnaBridge 143:86740a56073b 11744
AnnaBridge 143:86740a56073b 11745 #define MCG_C2_EREFS0_MASK MCG_C2_EREFS_MASK
AnnaBridge 143:86740a56073b 11746 #define MCG_C2_EREFS0_SHIFT MCG_C2_EREFS_SHIFT
AnnaBridge 143:86740a56073b 11747 #define MCG_C2_HGO0_MASK MCG_C2_HGO_MASK
AnnaBridge 143:86740a56073b 11748 #define MCG_C2_HGO0_SHIFT MCG_C2_HGO_SHIFT
AnnaBridge 143:86740a56073b 11749 #define MCG_C2_RANGE0_MASK MCG_C2_RANGE_MASK
AnnaBridge 143:86740a56073b 11750 #define MCG_C2_RANGE0_SHIFT MCG_C2_RANGE_SHIFT
AnnaBridge 143:86740a56073b 11751 #define MCG_C2_RANGE0(x) MCG_C2_RANGE(x)
AnnaBridge 143:86740a56073b 11752 #define MCM_ISR_REG(base) MCM_ISCR_REG(base)
AnnaBridge 143:86740a56073b 11753 #define MCM_ISR_FIOC_MASK MCM_ISCR_FIOC_MASK
AnnaBridge 143:86740a56073b 11754 #define MCM_ISR_FIOC_SHIFT MCM_ISCR_FIOC_SHIFT
AnnaBridge 143:86740a56073b 11755 #define MCM_ISR_FDZC_MASK MCM_ISCR_FDZC_MASK
AnnaBridge 143:86740a56073b 11756 #define MCM_ISR_FDZC_SHIFT MCM_ISCR_FDZC_SHIFT
AnnaBridge 143:86740a56073b 11757 #define MCM_ISR_FOFC_MASK MCM_ISCR_FOFC_MASK
AnnaBridge 143:86740a56073b 11758 #define MCM_ISR_FOFC_SHIFT MCM_ISCR_FOFC_SHIFT
AnnaBridge 143:86740a56073b 11759 #define MCM_ISR_FUFC_MASK MCM_ISCR_FUFC_MASK
AnnaBridge 143:86740a56073b 11760 #define MCM_ISR_FUFC_SHIFT MCM_ISCR_FUFC_SHIFT
AnnaBridge 143:86740a56073b 11761 #define MCM_ISR_FIXC_MASK MCM_ISCR_FIXC_MASK
AnnaBridge 143:86740a56073b 11762 #define MCM_ISR_FIXC_SHIFT MCM_ISCR_FIXC_SHIFT
AnnaBridge 143:86740a56073b 11763 #define MCM_ISR_FIDC_MASK MCM_ISCR_FIDC_MASK
AnnaBridge 143:86740a56073b 11764 #define MCM_ISR_FIDC_SHIFT MCM_ISCR_FIDC_SHIFT
AnnaBridge 143:86740a56073b 11765 #define MCM_ISR_FIOCE_MASK MCM_ISCR_FIOCE_MASK
AnnaBridge 143:86740a56073b 11766 #define MCM_ISR_FIOCE_SHIFT MCM_ISCR_FIOCE_SHIFT
AnnaBridge 143:86740a56073b 11767 #define MCM_ISR_FDZCE_MASK MCM_ISCR_FDZCE_MASK
AnnaBridge 143:86740a56073b 11768 #define MCM_ISR_FDZCE_SHIFT MCM_ISCR_FDZCE_SHIFT
AnnaBridge 143:86740a56073b 11769 #define MCM_ISR_FOFCE_MASK MCM_ISCR_FOFCE_MASK
AnnaBridge 143:86740a56073b 11770 #define MCM_ISR_FOFCE_SHIFT MCM_ISCR_FOFCE_SHIFT
AnnaBridge 143:86740a56073b 11771 #define MCM_ISR_FUFCE_MASK MCM_ISCR_FUFCE_MASK
AnnaBridge 143:86740a56073b 11772 #define MCM_ISR_FUFCE_SHIFT MCM_ISCR_FUFCE_SHIFT
AnnaBridge 143:86740a56073b 11773 #define MCM_ISR_FIXCE_MASK MCM_ISCR_FIXCE_MASK
AnnaBridge 143:86740a56073b 11774 #define MCM_ISR_FIXCE_SHIFT MCM_ISCR_FIXCE_SHIFT
AnnaBridge 143:86740a56073b 11775 #define MCM_ISR_FIDCE_MASK MCM_ISCR_FIDCE_MASK
AnnaBridge 143:86740a56073b 11776 #define MCM_ISR_FIDCE_SHIFT MCM_ISCR_FIDCE_SHIFT
AnnaBridge 143:86740a56073b 11777 #define DSPI0 SPI0
AnnaBridge 143:86740a56073b 11778 #define DSPI1 SPI1
AnnaBridge 143:86740a56073b 11779 #define DSPI2 SPI2
AnnaBridge 143:86740a56073b 11780 #define FLEXCAN0 CAN0
AnnaBridge 143:86740a56073b 11781 #define PTA_BASE GPIOA_BASE
AnnaBridge 143:86740a56073b 11782 #define PTA GPIOA
AnnaBridge 143:86740a56073b 11783 #define PTB_BASE GPIOB_BASE
AnnaBridge 143:86740a56073b 11784 #define PTB GPIOB
AnnaBridge 143:86740a56073b 11785 #define PTC_BASE GPIOC_BASE
AnnaBridge 143:86740a56073b 11786 #define PTC GPIOC
AnnaBridge 143:86740a56073b 11787 #define PTD_BASE GPIOD_BASE
AnnaBridge 143:86740a56073b 11788 #define PTD GPIOD
AnnaBridge 143:86740a56073b 11789 #define PTE_BASE GPIOE_BASE
AnnaBridge 143:86740a56073b 11790 #define PTE GPIOE
AnnaBridge 143:86740a56073b 11791 #define UART_WP7816_T_TYPE0_REG(base) UART_WP7816T0_REG(base)
AnnaBridge 143:86740a56073b 11792 #define UART_WP7816_T_TYPE1_REG(base) UART_WP7816T1_REG(base)
AnnaBridge 143:86740a56073b 11793 #define UART_WP7816_T_TYPE0_WI_MASK UART_WP7816T0_WI_MASK
AnnaBridge 143:86740a56073b 11794 #define UART_WP7816_T_TYPE0_WI_SHIFT UART_WP7816T0_WI_SHIFT
AnnaBridge 143:86740a56073b 11795 #define UART_WP7816_T_TYPE0_WI(x) UART_WP7816T0_WI(x)
AnnaBridge 143:86740a56073b 11796 #define UART_WP7816_T_TYPE1_BWI_MASK UART_WP7816T1_BWI_MASK
AnnaBridge 143:86740a56073b 11797 #define UART_WP7816_T_TYPE1_BWI_SHIFT UART_WP7816T1_BWI_SHIFT
AnnaBridge 143:86740a56073b 11798 #define UART_WP7816_T_TYPE1_BWI(x) UART_WP7816T1_BWI(x)
AnnaBridge 143:86740a56073b 11799 #define UART_WP7816_T_TYPE1_CWI_MASK UART_WP7816T1_CWI_MASK
AnnaBridge 143:86740a56073b 11800 #define UART_WP7816_T_TYPE1_CWI_SHIFT UART_WP7816T1_CWI_SHIFT
AnnaBridge 143:86740a56073b 11801 #define UART_WP7816_T_TYPE1_CWI(x) UART_WP7816T1_CWI(x)
AnnaBridge 143:86740a56073b 11802 #define Watchdog_IRQn WDOG_EWM_IRQn
AnnaBridge 143:86740a56073b 11803 #define Watchdog_IRQHandler WDOG_EWM_IRQHandler
AnnaBridge 143:86740a56073b 11804 #define LPTimer_IRQn LPTMR0_IRQn
AnnaBridge 143:86740a56073b 11805 #define LPTimer_IRQHandler LPTMR0_IRQHandler
AnnaBridge 143:86740a56073b 11806 #define LLW_IRQn LLWU_IRQn
AnnaBridge 143:86740a56073b 11807 #define LLW_IRQHandler LLWU_IRQHandler
AnnaBridge 143:86740a56073b 11808 #define DMAMUX0 DMAMUX
AnnaBridge 143:86740a56073b 11809 #define WDOG0 WDOG
AnnaBridge 143:86740a56073b 11810 #define MCM0 MCM
AnnaBridge 143:86740a56073b 11811 #define RTC0 RTC
AnnaBridge 143:86740a56073b 11812
AnnaBridge 143:86740a56073b 11813 /*!
AnnaBridge 143:86740a56073b 11814 * @}
AnnaBridge 143:86740a56073b 11815 */ /* end of group SDK_Compatibility_Symbols */
AnnaBridge 143:86740a56073b 11816
AnnaBridge 143:86740a56073b 11817
AnnaBridge 143:86740a56073b 11818 #endif /* _MK24F12_H_ */
AnnaBridge 143:86740a56073b 11819