mbed official / mbed

The official Mbed 2 C/C++ SDK provides the software platform and libraries to build your applications.

Dependents:   hello SerialTestv11 SerialTestv12 Sierpinski ... more

mbed 2

This is the mbed 2 library. If you'd like to learn about Mbed OS please see the mbed-os docs.

TARGET_NRF51822/TOOLCHAIN_GCC_ARM/nrf51.h@172:65be27845400, 2019-02-20 (annotated)

Committer:
AnnaBridge
Date:
Wed Feb 20 20:53:29 2019 +0000
Revision:
172:65be27845400
Parent:
171:3a7713b1edbc 
mbed library release version 165

Who changed what in which revision?

UserRevisionLine numberNew contents of line
AnnaBridge 171:3a7713b1edbc 1 /*
AnnaBridge 171:3a7713b1edbc 2 * Copyright (c) Nordic Semiconductor ASA
AnnaBridge 171:3a7713b1edbc 3 * All rights reserved.
AnnaBridge 171:3a7713b1edbc 4 *
AnnaBridge 171:3a7713b1edbc 5 * Redistribution and use in source and binary forms, with or without modification,
AnnaBridge 171:3a7713b1edbc 6 * are permitted provided that the following conditions are met:
AnnaBridge 171:3a7713b1edbc 7 *
AnnaBridge 171:3a7713b1edbc 8 * 1. Redistributions of source code must retain the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 9 * list of conditions and the following disclaimer.
AnnaBridge 171:3a7713b1edbc 10 *
AnnaBridge 171:3a7713b1edbc 11 * 2. Redistributions in binary form must reproduce the above copyright notice, this
AnnaBridge 171:3a7713b1edbc 12 * list of conditions and the following disclaimer in the documentation and/or
AnnaBridge 171:3a7713b1edbc 13 * other materials provided with the distribution.
AnnaBridge 171:3a7713b1edbc 14 *
AnnaBridge 171:3a7713b1edbc 15 * 3. Neither the name of Nordic Semiconductor ASA nor the names of other
AnnaBridge 171:3a7713b1edbc 16 * contributors to this software may be used to endorse or promote products
AnnaBridge 171:3a7713b1edbc 17 * derived from this software without specific prior written permission.
AnnaBridge 171:3a7713b1edbc 18 *
AnnaBridge 171:3a7713b1edbc 19 *
AnnaBridge 171:3a7713b1edbc 20 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
AnnaBridge 171:3a7713b1edbc 21 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
AnnaBridge 171:3a7713b1edbc 22 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
AnnaBridge 171:3a7713b1edbc 23 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
AnnaBridge 171:3a7713b1edbc 24 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
AnnaBridge 171:3a7713b1edbc 25 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
AnnaBridge 171:3a7713b1edbc 26 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
AnnaBridge 171:3a7713b1edbc 27 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
AnnaBridge 171:3a7713b1edbc 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
AnnaBridge 171:3a7713b1edbc 29 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
AnnaBridge 171:3a7713b1edbc 30 *
AnnaBridge 171:3a7713b1edbc 31 */
AnnaBridge 171:3a7713b1edbc 32
AnnaBridge 171:3a7713b1edbc 33 #ifndef NRF51_H
AnnaBridge 171:3a7713b1edbc 34 #define NRF51_H
AnnaBridge 171:3a7713b1edbc 35
AnnaBridge 171:3a7713b1edbc 36 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 37 extern "C" {
AnnaBridge 171:3a7713b1edbc 38 #endif
AnnaBridge 171:3a7713b1edbc 39
AnnaBridge 171:3a7713b1edbc 40
AnnaBridge 171:3a7713b1edbc 41 /* ------------------------- Interrupt Number Definition ------------------------ */
AnnaBridge 171:3a7713b1edbc 42
AnnaBridge 171:3a7713b1edbc 43 typedef enum {
AnnaBridge 171:3a7713b1edbc 44 /* ------------------- Cortex-M0 Processor Exceptions Numbers ------------------- */
AnnaBridge 171:3a7713b1edbc 45 Reset_IRQn = -15, /*!< 1 Reset Vector, invoked on Power up and warm reset */
AnnaBridge 171:3a7713b1edbc 46 NonMaskableInt_IRQn = -14, /*!< 2 Non maskable Interrupt, cannot be stopped or preempted */
AnnaBridge 171:3a7713b1edbc 47 HardFault_IRQn = -13, /*!< 3 Hard Fault, all classes of Fault */
AnnaBridge 171:3a7713b1edbc 48 SVCall_IRQn = -5, /*!< 11 System Service Call via SVC instruction */
AnnaBridge 171:3a7713b1edbc 49 DebugMonitor_IRQn = -4, /*!< 12 Debug Monitor */
AnnaBridge 171:3a7713b1edbc 50 PendSV_IRQn = -2, /*!< 14 Pendable request for system service */
AnnaBridge 171:3a7713b1edbc 51 SysTick_IRQn = -1, /*!< 15 System Tick Timer */
AnnaBridge 171:3a7713b1edbc 52 /* ---------------------- nrf51 Specific Interrupt Numbers ---------------------- */
AnnaBridge 171:3a7713b1edbc 53 POWER_CLOCK_IRQn = 0, /*!< 0 POWER_CLOCK */
AnnaBridge 171:3a7713b1edbc 54 RADIO_IRQn = 1, /*!< 1 RADIO */
AnnaBridge 171:3a7713b1edbc 55 UART0_IRQn = 2, /*!< 2 UART0 */
AnnaBridge 171:3a7713b1edbc 56 SPI0_TWI0_IRQn = 3, /*!< 3 SPI0_TWI0 */
AnnaBridge 171:3a7713b1edbc 57 SPI1_TWI1_IRQn = 4, /*!< 4 SPI1_TWI1 */
AnnaBridge 171:3a7713b1edbc 58 GPIOTE_IRQn = 6, /*!< 6 GPIOTE */
AnnaBridge 171:3a7713b1edbc 59 ADC_IRQn = 7, /*!< 7 ADC */
AnnaBridge 171:3a7713b1edbc 60 TIMER0_IRQn = 8, /*!< 8 TIMER0 */
AnnaBridge 171:3a7713b1edbc 61 TIMER1_IRQn = 9, /*!< 9 TIMER1 */
AnnaBridge 171:3a7713b1edbc 62 TIMER2_IRQn = 10, /*!< 10 TIMER2 */
AnnaBridge 171:3a7713b1edbc 63 RTC0_IRQn = 11, /*!< 11 RTC0 */
AnnaBridge 171:3a7713b1edbc 64 TEMP_IRQn = 12, /*!< 12 TEMP */
AnnaBridge 171:3a7713b1edbc 65 RNG_IRQn = 13, /*!< 13 RNG */
AnnaBridge 171:3a7713b1edbc 66 ECB_IRQn = 14, /*!< 14 ECB */
AnnaBridge 171:3a7713b1edbc 67 CCM_AAR_IRQn = 15, /*!< 15 CCM_AAR */
AnnaBridge 171:3a7713b1edbc 68 WDT_IRQn = 16, /*!< 16 WDT */
AnnaBridge 171:3a7713b1edbc 69 RTC1_IRQn = 17, /*!< 17 RTC1 */
AnnaBridge 171:3a7713b1edbc 70 QDEC_IRQn = 18, /*!< 18 QDEC */
AnnaBridge 171:3a7713b1edbc 71 LPCOMP_IRQn = 19, /*!< 19 LPCOMP */
AnnaBridge 171:3a7713b1edbc 72 SWI0_IRQn = 20, /*!< 20 SWI0 */
AnnaBridge 171:3a7713b1edbc 73 SWI1_IRQn = 21, /*!< 21 SWI1 */
AnnaBridge 171:3a7713b1edbc 74 SWI2_IRQn = 22, /*!< 22 SWI2 */
AnnaBridge 171:3a7713b1edbc 75 SWI3_IRQn = 23, /*!< 23 SWI3 */
AnnaBridge 171:3a7713b1edbc 76 SWI4_IRQn = 24, /*!< 24 SWI4 */
AnnaBridge 171:3a7713b1edbc 77 SWI5_IRQn = 25 /*!< 25 SWI5 */
AnnaBridge 171:3a7713b1edbc 78 } IRQn_Type;
AnnaBridge 171:3a7713b1edbc 79
AnnaBridge 171:3a7713b1edbc 80
AnnaBridge 171:3a7713b1edbc 81 /** @addtogroup Configuration_of_CMSIS
AnnaBridge 171:3a7713b1edbc 82 * @{
AnnaBridge 171:3a7713b1edbc 83 */
AnnaBridge 171:3a7713b1edbc 84
AnnaBridge 171:3a7713b1edbc 85
AnnaBridge 171:3a7713b1edbc 86 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 87 /* ================ Processor and Core Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 88 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 89
AnnaBridge 171:3a7713b1edbc 90 /* ----------------Configuration of the Cortex-M0 Processor and Core Peripherals---------------- */
AnnaBridge 171:3a7713b1edbc 91 #define __CM0_REV 0x0301 /*!< Cortex-M0 Core Revision */
AnnaBridge 171:3a7713b1edbc 92 #define __MPU_PRESENT 0 /*!< MPU present or not */
AnnaBridge 171:3a7713b1edbc 93 #define __NVIC_PRIO_BITS 2 /*!< Number of Bits used for Priority Levels */
AnnaBridge 171:3a7713b1edbc 94 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
AnnaBridge 171:3a7713b1edbc 95 /** @} */ /* End of group Configuration_of_CMSIS */
AnnaBridge 171:3a7713b1edbc 96
AnnaBridge 171:3a7713b1edbc 97 #include "core_cm0.h" /*!< Cortex-M0 processor and core peripherals */
AnnaBridge 171:3a7713b1edbc 98 #include "system_nrf51.h" /*!< nrf51 System */
AnnaBridge 171:3a7713b1edbc 99
AnnaBridge 171:3a7713b1edbc 100
AnnaBridge 171:3a7713b1edbc 101 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 102 /* ================ Device Specific Peripheral Section ================ */
AnnaBridge 171:3a7713b1edbc 103 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 104
AnnaBridge 171:3a7713b1edbc 105
AnnaBridge 171:3a7713b1edbc 106 /** @addtogroup Device_Peripheral_Registers
AnnaBridge 171:3a7713b1edbc 107 * @{
AnnaBridge 171:3a7713b1edbc 108 */
AnnaBridge 171:3a7713b1edbc 109
AnnaBridge 171:3a7713b1edbc 110
AnnaBridge 171:3a7713b1edbc 111 /* ------------------- Start of section using anonymous unions ------------------ */
AnnaBridge 171:3a7713b1edbc 112 #if defined(__CC_ARM)
AnnaBridge 171:3a7713b1edbc 113 #pragma push
AnnaBridge 171:3a7713b1edbc 114 #pragma anon_unions
AnnaBridge 171:3a7713b1edbc 115 #elif defined(__ICCARM__)
AnnaBridge 171:3a7713b1edbc 116 #pragma language=extended
AnnaBridge 171:3a7713b1edbc 117 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 118 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 119 #elif defined(__TMS470__)
AnnaBridge 171:3a7713b1edbc 120 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 121 #elif defined(__TASKING__)
AnnaBridge 171:3a7713b1edbc 122 #pragma warning 586
AnnaBridge 171:3a7713b1edbc 123 #else
AnnaBridge 171:3a7713b1edbc 124 #warning Not supported compiler type
AnnaBridge 171:3a7713b1edbc 125 #endif
AnnaBridge 171:3a7713b1edbc 126
AnnaBridge 171:3a7713b1edbc 127
AnnaBridge 171:3a7713b1edbc 128 typedef struct {
AnnaBridge 171:3a7713b1edbc 129 __IO uint32_t CPU0; /*!< Configurable priority configuration register for CPU0. */
AnnaBridge 171:3a7713b1edbc 130 __IO uint32_t SPIS1; /*!< Configurable priority configuration register for SPIS1. */
AnnaBridge 171:3a7713b1edbc 131 __IO uint32_t RADIO; /*!< Configurable priority configuration register for RADIO. */
AnnaBridge 171:3a7713b1edbc 132 __IO uint32_t ECB; /*!< Configurable priority configuration register for ECB. */
AnnaBridge 171:3a7713b1edbc 133 __IO uint32_t CCM; /*!< Configurable priority configuration register for CCM. */
AnnaBridge 171:3a7713b1edbc 134 __IO uint32_t AAR; /*!< Configurable priority configuration register for AAR. */
AnnaBridge 171:3a7713b1edbc 135 } AMLI_RAMPRI_Type;
AnnaBridge 171:3a7713b1edbc 136
AnnaBridge 171:3a7713b1edbc 137 typedef struct {
AnnaBridge 171:3a7713b1edbc 138 __IO uint32_t SCK; /*!< Pin select for SCK. */
AnnaBridge 171:3a7713b1edbc 139 __IO uint32_t MOSI; /*!< Pin select for MOSI. */
AnnaBridge 171:3a7713b1edbc 140 __IO uint32_t MISO; /*!< Pin select for MISO. */
AnnaBridge 171:3a7713b1edbc 141 } SPIM_PSEL_Type;
AnnaBridge 171:3a7713b1edbc 142
AnnaBridge 171:3a7713b1edbc 143 typedef struct {
AnnaBridge 171:3a7713b1edbc 144 __IO uint32_t PTR; /*!< Data pointer. */
AnnaBridge 171:3a7713b1edbc 145 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to receive. */
AnnaBridge 171:3a7713b1edbc 146 __I uint32_t AMOUNT; /*!< Number of bytes received in the last transaction. */
AnnaBridge 171:3a7713b1edbc 147 } SPIM_RXD_Type;
AnnaBridge 171:3a7713b1edbc 148
AnnaBridge 171:3a7713b1edbc 149 typedef struct {
AnnaBridge 171:3a7713b1edbc 150 __IO uint32_t PTR; /*!< Data pointer. */
AnnaBridge 171:3a7713b1edbc 151 __IO uint32_t MAXCNT; /*!< Maximum number of buffer bytes to send. */
AnnaBridge 171:3a7713b1edbc 152 __I uint32_t AMOUNT; /*!< Number of bytes sent in the last transaction. */
AnnaBridge 171:3a7713b1edbc 153 } SPIM_TXD_Type;
AnnaBridge 171:3a7713b1edbc 154
AnnaBridge 171:3a7713b1edbc 155 typedef struct {
AnnaBridge 171:3a7713b1edbc 156 __O uint32_t EN; /*!< Enable channel group. */
AnnaBridge 171:3a7713b1edbc 157 __O uint32_t DIS; /*!< Disable channel group. */
AnnaBridge 171:3a7713b1edbc 158 } PPI_TASKS_CHG_Type;
AnnaBridge 171:3a7713b1edbc 159
AnnaBridge 171:3a7713b1edbc 160 typedef struct {
AnnaBridge 171:3a7713b1edbc 161 __IO uint32_t EEP; /*!< Channel event end-point. */
AnnaBridge 171:3a7713b1edbc 162 __IO uint32_t TEP; /*!< Channel task end-point. */
AnnaBridge 171:3a7713b1edbc 163 } PPI_CH_Type;
AnnaBridge 171:3a7713b1edbc 164
AnnaBridge 171:3a7713b1edbc 165
AnnaBridge 171:3a7713b1edbc 166 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 167 /* ================ POWER ================ */
AnnaBridge 171:3a7713b1edbc 168 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 169
AnnaBridge 171:3a7713b1edbc 170
AnnaBridge 171:3a7713b1edbc 171 /**
AnnaBridge 171:3a7713b1edbc 172 * @brief Power Control. (POWER)
AnnaBridge 171:3a7713b1edbc 173 */
AnnaBridge 171:3a7713b1edbc 174
AnnaBridge 171:3a7713b1edbc 175 typedef struct { /*!< POWER Structure */
AnnaBridge 171:3a7713b1edbc 176 __I uint32_t RESERVED0[30];
AnnaBridge 171:3a7713b1edbc 177 __O uint32_t TASKS_CONSTLAT; /*!< Enable constant latency mode. */
AnnaBridge 171:3a7713b1edbc 178 __O uint32_t TASKS_LOWPWR; /*!< Enable low power mode (variable latency). */
AnnaBridge 171:3a7713b1edbc 179 __I uint32_t RESERVED1[34];
AnnaBridge 171:3a7713b1edbc 180 __IO uint32_t EVENTS_POFWARN; /*!< Power failure warning. */
AnnaBridge 171:3a7713b1edbc 181 __I uint32_t RESERVED2[126];
AnnaBridge 171:3a7713b1edbc 182 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 183 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 184 __I uint32_t RESERVED3[61];
AnnaBridge 171:3a7713b1edbc 185 __IO uint32_t RESETREAS; /*!< Reset reason. */
AnnaBridge 171:3a7713b1edbc 186 __I uint32_t RESERVED4[9];
AnnaBridge 171:3a7713b1edbc 187 __I uint32_t RAMSTATUS; /*!< Ram status register. */
AnnaBridge 171:3a7713b1edbc 188 __I uint32_t RESERVED5[53];
AnnaBridge 171:3a7713b1edbc 189 __O uint32_t SYSTEMOFF; /*!< System off register. */
AnnaBridge 171:3a7713b1edbc 190 __I uint32_t RESERVED6[3];
AnnaBridge 171:3a7713b1edbc 191 __IO uint32_t POFCON; /*!< Power failure configuration. */
AnnaBridge 171:3a7713b1edbc 192 __I uint32_t RESERVED7[2];
AnnaBridge 171:3a7713b1edbc 193 __IO uint32_t GPREGRET; /*!< General purpose retention register. This register is a retained
AnnaBridge 171:3a7713b1edbc 194 register. */
AnnaBridge 171:3a7713b1edbc 195 __I uint32_t RESERVED8;
AnnaBridge 171:3a7713b1edbc 196 __IO uint32_t RAMON; /*!< Ram on/off. */
AnnaBridge 171:3a7713b1edbc 197 __I uint32_t RESERVED9[7];
AnnaBridge 171:3a7713b1edbc 198 __IO uint32_t RESET; /*!< Pin reset functionality configuration register. This register
AnnaBridge 171:3a7713b1edbc 199 is a retained register. */
AnnaBridge 171:3a7713b1edbc 200 __I uint32_t RESERVED10[3];
AnnaBridge 171:3a7713b1edbc 201 __IO uint32_t RAMONB; /*!< Ram on/off. */
AnnaBridge 171:3a7713b1edbc 202 __I uint32_t RESERVED11[8];
AnnaBridge 171:3a7713b1edbc 203 __IO uint32_t DCDCEN; /*!< DCDC converter enable configuration register. */
AnnaBridge 171:3a7713b1edbc 204 __I uint32_t RESERVED12[291];
AnnaBridge 171:3a7713b1edbc 205 __IO uint32_t DCDCFORCE; /*!< DCDC power-up force register. */
AnnaBridge 171:3a7713b1edbc 206 } NRF_POWER_Type;
AnnaBridge 171:3a7713b1edbc 207
AnnaBridge 171:3a7713b1edbc 208
AnnaBridge 171:3a7713b1edbc 209 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 210 /* ================ CLOCK ================ */
AnnaBridge 171:3a7713b1edbc 211 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 212
AnnaBridge 171:3a7713b1edbc 213
AnnaBridge 171:3a7713b1edbc 214 /**
AnnaBridge 171:3a7713b1edbc 215 * @brief Clock control. (CLOCK)
AnnaBridge 171:3a7713b1edbc 216 */
AnnaBridge 171:3a7713b1edbc 217
AnnaBridge 171:3a7713b1edbc 218 typedef struct { /*!< CLOCK Structure */
AnnaBridge 171:3a7713b1edbc 219 __O uint32_t TASKS_HFCLKSTART; /*!< Start HFCLK clock source. */
AnnaBridge 171:3a7713b1edbc 220 __O uint32_t TASKS_HFCLKSTOP; /*!< Stop HFCLK clock source. */
AnnaBridge 171:3a7713b1edbc 221 __O uint32_t TASKS_LFCLKSTART; /*!< Start LFCLK clock source. */
AnnaBridge 171:3a7713b1edbc 222 __O uint32_t TASKS_LFCLKSTOP; /*!< Stop LFCLK clock source. */
AnnaBridge 171:3a7713b1edbc 223 __O uint32_t TASKS_CAL; /*!< Start calibration of LFCLK RC oscillator. */
AnnaBridge 171:3a7713b1edbc 224 __O uint32_t TASKS_CTSTART; /*!< Start calibration timer. */
AnnaBridge 171:3a7713b1edbc 225 __O uint32_t TASKS_CTSTOP; /*!< Stop calibration timer. */
AnnaBridge 171:3a7713b1edbc 226 __I uint32_t RESERVED0[57];
AnnaBridge 171:3a7713b1edbc 227 __IO uint32_t EVENTS_HFCLKSTARTED; /*!< HFCLK oscillator started. */
AnnaBridge 171:3a7713b1edbc 228 __IO uint32_t EVENTS_LFCLKSTARTED; /*!< LFCLK oscillator started. */
AnnaBridge 171:3a7713b1edbc 229 __I uint32_t RESERVED1;
AnnaBridge 171:3a7713b1edbc 230 __IO uint32_t EVENTS_DONE; /*!< Calibration of LFCLK RC oscillator completed. */
AnnaBridge 171:3a7713b1edbc 231 __IO uint32_t EVENTS_CTTO; /*!< Calibration timer timeout. */
AnnaBridge 171:3a7713b1edbc 232 __I uint32_t RESERVED2[124];
AnnaBridge 171:3a7713b1edbc 233 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 234 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 235 __I uint32_t RESERVED3[63];
AnnaBridge 171:3a7713b1edbc 236 __I uint32_t HFCLKRUN; /*!< Task HFCLKSTART trigger status. */
AnnaBridge 171:3a7713b1edbc 237 __I uint32_t HFCLKSTAT; /*!< High frequency clock status. */
AnnaBridge 171:3a7713b1edbc 238 __I uint32_t RESERVED4;
AnnaBridge 171:3a7713b1edbc 239 __I uint32_t LFCLKRUN; /*!< Task LFCLKSTART triggered status. */
AnnaBridge 171:3a7713b1edbc 240 __I uint32_t LFCLKSTAT; /*!< Low frequency clock status. */
AnnaBridge 171:3a7713b1edbc 241 __I uint32_t LFCLKSRCCOPY; /*!< Clock source for the LFCLK clock, set when task LKCLKSTART is
AnnaBridge 171:3a7713b1edbc 242 triggered. */
AnnaBridge 171:3a7713b1edbc 243 __I uint32_t RESERVED5[62];
AnnaBridge 171:3a7713b1edbc 244 __IO uint32_t LFCLKSRC; /*!< Clock source for the LFCLK clock. */
AnnaBridge 171:3a7713b1edbc 245 __I uint32_t RESERVED6[7];
AnnaBridge 171:3a7713b1edbc 246 __IO uint32_t CTIV; /*!< Calibration timer interval. */
AnnaBridge 171:3a7713b1edbc 247 __I uint32_t RESERVED7[5];
AnnaBridge 171:3a7713b1edbc 248 __IO uint32_t XTALFREQ; /*!< Crystal frequency. */
AnnaBridge 171:3a7713b1edbc 249 } NRF_CLOCK_Type;
AnnaBridge 171:3a7713b1edbc 250
AnnaBridge 171:3a7713b1edbc 251
AnnaBridge 171:3a7713b1edbc 252 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 253 /* ================ MPU ================ */
AnnaBridge 171:3a7713b1edbc 254 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 255
AnnaBridge 171:3a7713b1edbc 256
AnnaBridge 171:3a7713b1edbc 257 /**
AnnaBridge 171:3a7713b1edbc 258 * @brief Memory Protection Unit. (MPU)
AnnaBridge 171:3a7713b1edbc 259 */
AnnaBridge 171:3a7713b1edbc 260
AnnaBridge 171:3a7713b1edbc 261 typedef struct { /*!< MPU Structure */
AnnaBridge 171:3a7713b1edbc 262 __I uint32_t RESERVED0[330];
AnnaBridge 171:3a7713b1edbc 263 __IO uint32_t PERR0; /*!< Configuration of peripherals in mpu regions. */
AnnaBridge 171:3a7713b1edbc 264 __IO uint32_t RLENR0; /*!< Length of RAM region 0. */
AnnaBridge 171:3a7713b1edbc 265 __I uint32_t RESERVED1[52];
AnnaBridge 171:3a7713b1edbc 266 __IO uint32_t PROTENSET0; /*!< Erase and write protection bit enable set register. */
AnnaBridge 171:3a7713b1edbc 267 __IO uint32_t PROTENSET1; /*!< Erase and write protection bit enable set register. */
AnnaBridge 171:3a7713b1edbc 268 __IO uint32_t DISABLEINDEBUG; /*!< Disable erase and write protection mechanism in debug mode. */
AnnaBridge 171:3a7713b1edbc 269 __IO uint32_t PROTBLOCKSIZE; /*!< Erase and write protection block size. */
AnnaBridge 171:3a7713b1edbc 270 } NRF_MPU_Type;
AnnaBridge 171:3a7713b1edbc 271
AnnaBridge 171:3a7713b1edbc 272
AnnaBridge 171:3a7713b1edbc 273 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 274 /* ================ AMLI ================ */
AnnaBridge 171:3a7713b1edbc 275 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 276
AnnaBridge 171:3a7713b1edbc 277
AnnaBridge 171:3a7713b1edbc 278 /**
AnnaBridge 171:3a7713b1edbc 279 * @brief AHB Multi-Layer Interface. (AMLI)
AnnaBridge 171:3a7713b1edbc 280 */
AnnaBridge 171:3a7713b1edbc 281
AnnaBridge 171:3a7713b1edbc 282 typedef struct { /*!< AMLI Structure */
AnnaBridge 171:3a7713b1edbc 283 __I uint32_t RESERVED0[896];
AnnaBridge 171:3a7713b1edbc 284 AMLI_RAMPRI_Type RAMPRI; /*!< RAM configurable priority configuration structure. */
AnnaBridge 171:3a7713b1edbc 285 } NRF_AMLI_Type;
AnnaBridge 171:3a7713b1edbc 286
AnnaBridge 171:3a7713b1edbc 287
AnnaBridge 171:3a7713b1edbc 288 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 289 /* ================ RADIO ================ */
AnnaBridge 171:3a7713b1edbc 290 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 291
AnnaBridge 171:3a7713b1edbc 292
AnnaBridge 171:3a7713b1edbc 293 /**
AnnaBridge 171:3a7713b1edbc 294 * @brief The radio. (RADIO)
AnnaBridge 171:3a7713b1edbc 295 */
AnnaBridge 171:3a7713b1edbc 296
AnnaBridge 171:3a7713b1edbc 297 typedef struct { /*!< RADIO Structure */
AnnaBridge 171:3a7713b1edbc 298 __O uint32_t TASKS_TXEN; /*!< Enable radio in TX mode. */
AnnaBridge 171:3a7713b1edbc 299 __O uint32_t TASKS_RXEN; /*!< Enable radio in RX mode. */
AnnaBridge 171:3a7713b1edbc 300 __O uint32_t TASKS_START; /*!< Start radio. */
AnnaBridge 171:3a7713b1edbc 301 __O uint32_t TASKS_STOP; /*!< Stop radio. */
AnnaBridge 171:3a7713b1edbc 302 __O uint32_t TASKS_DISABLE; /*!< Disable radio. */
AnnaBridge 171:3a7713b1edbc 303 __O uint32_t TASKS_RSSISTART; /*!< Start the RSSI and take one sample of the receive signal strength. */
AnnaBridge 171:3a7713b1edbc 304 __O uint32_t TASKS_RSSISTOP; /*!< Stop the RSSI measurement. */
AnnaBridge 171:3a7713b1edbc 305 __O uint32_t TASKS_BCSTART; /*!< Start the bit counter. */
AnnaBridge 171:3a7713b1edbc 306 __O uint32_t TASKS_BCSTOP; /*!< Stop the bit counter. */
AnnaBridge 171:3a7713b1edbc 307 __I uint32_t RESERVED0[55];
AnnaBridge 171:3a7713b1edbc 308 __IO uint32_t EVENTS_READY; /*!< Ready event. */
AnnaBridge 171:3a7713b1edbc 309 __IO uint32_t EVENTS_ADDRESS; /*!< Address event. */
AnnaBridge 171:3a7713b1edbc 310 __IO uint32_t EVENTS_PAYLOAD; /*!< Payload event. */
AnnaBridge 171:3a7713b1edbc 311 __IO uint32_t EVENTS_END; /*!< End event. */
AnnaBridge 171:3a7713b1edbc 312 __IO uint32_t EVENTS_DISABLED; /*!< Disable event. */
AnnaBridge 171:3a7713b1edbc 313 __IO uint32_t EVENTS_DEVMATCH; /*!< A device address match occurred on the last received packet. */
AnnaBridge 171:3a7713b1edbc 314 __IO uint32_t EVENTS_DEVMISS; /*!< No device address match occurred on the last received packet. */
AnnaBridge 171:3a7713b1edbc 315 __IO uint32_t EVENTS_RSSIEND; /*!< Sampling of the receive signal strength complete. A new RSSI
AnnaBridge 171:3a7713b1edbc 316 sample is ready for readout at the RSSISAMPLE register. */
AnnaBridge 171:3a7713b1edbc 317 __I uint32_t RESERVED1[2];
AnnaBridge 171:3a7713b1edbc 318 __IO uint32_t EVENTS_BCMATCH; /*!< Bit counter reached bit count value specified in BCC register. */
AnnaBridge 171:3a7713b1edbc 319 __I uint32_t RESERVED2[53];
AnnaBridge 171:3a7713b1edbc 320 __IO uint32_t SHORTS; /*!< Shortcuts for the radio. */
AnnaBridge 171:3a7713b1edbc 321 __I uint32_t RESERVED3[64];
AnnaBridge 171:3a7713b1edbc 322 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 323 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 324 __I uint32_t RESERVED4[61];
AnnaBridge 171:3a7713b1edbc 325 __I uint32_t CRCSTATUS; /*!< CRC status of received packet. */
AnnaBridge 171:3a7713b1edbc 326 __I uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 327 __I uint32_t RXMATCH; /*!< Received address. */
AnnaBridge 171:3a7713b1edbc 328 __I uint32_t RXCRC; /*!< Received CRC. */
AnnaBridge 171:3a7713b1edbc 329 __I uint32_t DAI; /*!< Device address match index. */
AnnaBridge 171:3a7713b1edbc 330 __I uint32_t RESERVED6[60];
AnnaBridge 171:3a7713b1edbc 331 __IO uint32_t PACKETPTR; /*!< Packet pointer. Decision point: START task. */
AnnaBridge 171:3a7713b1edbc 332 __IO uint32_t FREQUENCY; /*!< Frequency. */
AnnaBridge 171:3a7713b1edbc 333 __IO uint32_t TXPOWER; /*!< Output power. */
AnnaBridge 171:3a7713b1edbc 334 __IO uint32_t MODE; /*!< Data rate and modulation. */
AnnaBridge 171:3a7713b1edbc 335 __IO uint32_t PCNF0; /*!< Packet configuration 0. */
AnnaBridge 171:3a7713b1edbc 336 __IO uint32_t PCNF1; /*!< Packet configuration 1. */
AnnaBridge 171:3a7713b1edbc 337 __IO uint32_t BASE0; /*!< Radio base address 0. Decision point: START task. */
AnnaBridge 171:3a7713b1edbc 338 __IO uint32_t BASE1; /*!< Radio base address 1. Decision point: START task. */
AnnaBridge 171:3a7713b1edbc 339 __IO uint32_t PREFIX0; /*!< Prefixes bytes for logical addresses 0 to 3. */
AnnaBridge 171:3a7713b1edbc 340 __IO uint32_t PREFIX1; /*!< Prefixes bytes for logical addresses 4 to 7. */
AnnaBridge 171:3a7713b1edbc 341 __IO uint32_t TXADDRESS; /*!< Transmit address select. */
AnnaBridge 171:3a7713b1edbc 342 __IO uint32_t RXADDRESSES; /*!< Receive address select. */
AnnaBridge 171:3a7713b1edbc 343 __IO uint32_t CRCCNF; /*!< CRC configuration. */
AnnaBridge 171:3a7713b1edbc 344 __IO uint32_t CRCPOLY; /*!< CRC polynomial. */
AnnaBridge 171:3a7713b1edbc 345 __IO uint32_t CRCINIT; /*!< CRC initial value. */
AnnaBridge 171:3a7713b1edbc 346 __IO uint32_t TEST; /*!< Test features enable register. */
AnnaBridge 171:3a7713b1edbc 347 __IO uint32_t TIFS; /*!< Inter Frame Spacing in microseconds. */
AnnaBridge 171:3a7713b1edbc 348 __I uint32_t RSSISAMPLE; /*!< RSSI sample. */
AnnaBridge 171:3a7713b1edbc 349 __I uint32_t RESERVED7;
AnnaBridge 171:3a7713b1edbc 350 __I uint32_t STATE; /*!< Current radio state. */
AnnaBridge 171:3a7713b1edbc 351 __IO uint32_t DATAWHITEIV; /*!< Data whitening initial value. */
AnnaBridge 171:3a7713b1edbc 352 __I uint32_t RESERVED8[2];
AnnaBridge 171:3a7713b1edbc 353 __IO uint32_t BCC; /*!< Bit counter compare. */
AnnaBridge 171:3a7713b1edbc 354 __I uint32_t RESERVED9[39];
AnnaBridge 171:3a7713b1edbc 355 __IO uint32_t DAB[8]; /*!< Device address base segment. */
AnnaBridge 171:3a7713b1edbc 356 __IO uint32_t DAP[8]; /*!< Device address prefix. */
AnnaBridge 171:3a7713b1edbc 357 __IO uint32_t DACNF; /*!< Device address match configuration. */
AnnaBridge 171:3a7713b1edbc 358 __I uint32_t RESERVED10[56];
AnnaBridge 171:3a7713b1edbc 359 __IO uint32_t OVERRIDE0; /*!< Trim value override register 0. */
AnnaBridge 171:3a7713b1edbc 360 __IO uint32_t OVERRIDE1; /*!< Trim value override register 1. */
AnnaBridge 171:3a7713b1edbc 361 __IO uint32_t OVERRIDE2; /*!< Trim value override register 2. */
AnnaBridge 171:3a7713b1edbc 362 __IO uint32_t OVERRIDE3; /*!< Trim value override register 3. */
AnnaBridge 171:3a7713b1edbc 363 __IO uint32_t OVERRIDE4; /*!< Trim value override register 4. */
AnnaBridge 171:3a7713b1edbc 364 __I uint32_t RESERVED11[561];
AnnaBridge 171:3a7713b1edbc 365 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 366 } NRF_RADIO_Type;
AnnaBridge 171:3a7713b1edbc 367
AnnaBridge 171:3a7713b1edbc 368
AnnaBridge 171:3a7713b1edbc 369 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 370 /* ================ UART ================ */
AnnaBridge 171:3a7713b1edbc 371 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 372
AnnaBridge 171:3a7713b1edbc 373
AnnaBridge 171:3a7713b1edbc 374 /**
AnnaBridge 171:3a7713b1edbc 375 * @brief Universal Asynchronous Receiver/Transmitter. (UART)
AnnaBridge 171:3a7713b1edbc 376 */
AnnaBridge 171:3a7713b1edbc 377
AnnaBridge 171:3a7713b1edbc 378 typedef struct { /*!< UART Structure */
AnnaBridge 171:3a7713b1edbc 379 __O uint32_t TASKS_STARTRX; /*!< Start UART receiver. */
AnnaBridge 171:3a7713b1edbc 380 __O uint32_t TASKS_STOPRX; /*!< Stop UART receiver. */
AnnaBridge 171:3a7713b1edbc 381 __O uint32_t TASKS_STARTTX; /*!< Start UART transmitter. */
AnnaBridge 171:3a7713b1edbc 382 __O uint32_t TASKS_STOPTX; /*!< Stop UART transmitter. */
AnnaBridge 171:3a7713b1edbc 383 __I uint32_t RESERVED0[3];
AnnaBridge 171:3a7713b1edbc 384 __O uint32_t TASKS_SUSPEND; /*!< Suspend UART. */
AnnaBridge 171:3a7713b1edbc 385 __I uint32_t RESERVED1[56];
AnnaBridge 171:3a7713b1edbc 386 __IO uint32_t EVENTS_CTS; /*!< CTS activated. */
AnnaBridge 171:3a7713b1edbc 387 __IO uint32_t EVENTS_NCTS; /*!< CTS deactivated. */
AnnaBridge 171:3a7713b1edbc 388 __IO uint32_t EVENTS_RXDRDY; /*!< Data received in RXD. */
AnnaBridge 171:3a7713b1edbc 389 __I uint32_t RESERVED2[4];
AnnaBridge 171:3a7713b1edbc 390 __IO uint32_t EVENTS_TXDRDY; /*!< Data sent from TXD. */
AnnaBridge 171:3a7713b1edbc 391 __I uint32_t RESERVED3;
AnnaBridge 171:3a7713b1edbc 392 __IO uint32_t EVENTS_ERROR; /*!< Error detected. */
AnnaBridge 171:3a7713b1edbc 393 __I uint32_t RESERVED4[7];
AnnaBridge 171:3a7713b1edbc 394 __IO uint32_t EVENTS_RXTO; /*!< Receiver timeout. */
AnnaBridge 171:3a7713b1edbc 395 __I uint32_t RESERVED5[46];
AnnaBridge 171:3a7713b1edbc 396 __IO uint32_t SHORTS; /*!< Shortcuts for UART. */
AnnaBridge 171:3a7713b1edbc 397 __I uint32_t RESERVED6[64];
AnnaBridge 171:3a7713b1edbc 398 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 399 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 400 __I uint32_t RESERVED7[93];
AnnaBridge 171:3a7713b1edbc 401 __IO uint32_t ERRORSRC; /*!< Error source. Write error field to 1 to clear error. */
AnnaBridge 171:3a7713b1edbc 402 __I uint32_t RESERVED8[31];
AnnaBridge 171:3a7713b1edbc 403 __IO uint32_t ENABLE; /*!< Enable UART and acquire IOs. */
AnnaBridge 171:3a7713b1edbc 404 __I uint32_t RESERVED9;
AnnaBridge 171:3a7713b1edbc 405 __IO uint32_t PSELRTS; /*!< Pin select for RTS. */
AnnaBridge 171:3a7713b1edbc 406 __IO uint32_t PSELTXD; /*!< Pin select for TXD. */
AnnaBridge 171:3a7713b1edbc 407 __IO uint32_t PSELCTS; /*!< Pin select for CTS. */
AnnaBridge 171:3a7713b1edbc 408 __IO uint32_t PSELRXD; /*!< Pin select for RXD. */
AnnaBridge 171:3a7713b1edbc 409 __I uint32_t RXD; /*!< RXD register. On read action the buffer pointer is displaced.
AnnaBridge 171:3a7713b1edbc 410 Once read the character is consumed. If read when no character
AnnaBridge 171:3a7713b1edbc 411 available, the UART will stop working. */
AnnaBridge 171:3a7713b1edbc 412 __O uint32_t TXD; /*!< TXD register. */
AnnaBridge 171:3a7713b1edbc 413 __I uint32_t RESERVED10;
AnnaBridge 171:3a7713b1edbc 414 __IO uint32_t BAUDRATE; /*!< UART Baudrate. */
AnnaBridge 171:3a7713b1edbc 415 __I uint32_t RESERVED11[17];
AnnaBridge 171:3a7713b1edbc 416 __IO uint32_t CONFIG; /*!< Configuration of parity and hardware flow control register. */
AnnaBridge 171:3a7713b1edbc 417 __I uint32_t RESERVED12[675];
AnnaBridge 171:3a7713b1edbc 418 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 419 } NRF_UART_Type;
AnnaBridge 171:3a7713b1edbc 420
AnnaBridge 171:3a7713b1edbc 421
AnnaBridge 171:3a7713b1edbc 422 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 423 /* ================ SPI ================ */
AnnaBridge 171:3a7713b1edbc 424 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 425
AnnaBridge 171:3a7713b1edbc 426
AnnaBridge 171:3a7713b1edbc 427 /**
AnnaBridge 171:3a7713b1edbc 428 * @brief SPI master 0. (SPI)
AnnaBridge 171:3a7713b1edbc 429 */
AnnaBridge 171:3a7713b1edbc 430
AnnaBridge 171:3a7713b1edbc 431 typedef struct { /*!< SPI Structure */
AnnaBridge 171:3a7713b1edbc 432 __I uint32_t RESERVED0[66];
AnnaBridge 171:3a7713b1edbc 433 __IO uint32_t EVENTS_READY; /*!< TXD byte sent and RXD byte received. */
AnnaBridge 171:3a7713b1edbc 434 __I uint32_t RESERVED1[126];
AnnaBridge 171:3a7713b1edbc 435 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 436 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 437 __I uint32_t RESERVED2[125];
AnnaBridge 171:3a7713b1edbc 438 __IO uint32_t ENABLE; /*!< Enable SPI. */
AnnaBridge 171:3a7713b1edbc 439 __I uint32_t RESERVED3;
AnnaBridge 171:3a7713b1edbc 440 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
AnnaBridge 171:3a7713b1edbc 441 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
AnnaBridge 171:3a7713b1edbc 442 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
AnnaBridge 171:3a7713b1edbc 443 __I uint32_t RESERVED4;
AnnaBridge 171:3a7713b1edbc 444 __I uint32_t RXD; /*!< RX data. */
AnnaBridge 171:3a7713b1edbc 445 __IO uint32_t TXD; /*!< TX data. */
AnnaBridge 171:3a7713b1edbc 446 __I uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 447 __IO uint32_t FREQUENCY; /*!< SPI frequency */
AnnaBridge 171:3a7713b1edbc 448 __I uint32_t RESERVED6[11];
AnnaBridge 171:3a7713b1edbc 449 __IO uint32_t CONFIG; /*!< Configuration register. */
AnnaBridge 171:3a7713b1edbc 450 __I uint32_t RESERVED7[681];
AnnaBridge 171:3a7713b1edbc 451 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 452 } NRF_SPI_Type;
AnnaBridge 171:3a7713b1edbc 453
AnnaBridge 171:3a7713b1edbc 454
AnnaBridge 171:3a7713b1edbc 455 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 456 /* ================ TWI ================ */
AnnaBridge 171:3a7713b1edbc 457 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 458
AnnaBridge 171:3a7713b1edbc 459
AnnaBridge 171:3a7713b1edbc 460 /**
AnnaBridge 171:3a7713b1edbc 461 * @brief Two-wire interface master 0. (TWI)
AnnaBridge 171:3a7713b1edbc 462 */
AnnaBridge 171:3a7713b1edbc 463
AnnaBridge 171:3a7713b1edbc 464 typedef struct { /*!< TWI Structure */
AnnaBridge 171:3a7713b1edbc 465 __O uint32_t TASKS_STARTRX; /*!< Start 2-Wire master receive sequence. */
AnnaBridge 171:3a7713b1edbc 466 __I uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 467 __O uint32_t TASKS_STARTTX; /*!< Start 2-Wire master transmit sequence. */
AnnaBridge 171:3a7713b1edbc 468 __I uint32_t RESERVED1[2];
AnnaBridge 171:3a7713b1edbc 469 __O uint32_t TASKS_STOP; /*!< Stop 2-Wire transaction. */
AnnaBridge 171:3a7713b1edbc 470 __I uint32_t RESERVED2;
AnnaBridge 171:3a7713b1edbc 471 __O uint32_t TASKS_SUSPEND; /*!< Suspend 2-Wire transaction. */
AnnaBridge 171:3a7713b1edbc 472 __O uint32_t TASKS_RESUME; /*!< Resume 2-Wire transaction. */
AnnaBridge 171:3a7713b1edbc 473 __I uint32_t RESERVED3[56];
AnnaBridge 171:3a7713b1edbc 474 __IO uint32_t EVENTS_STOPPED; /*!< Two-wire stopped. */
AnnaBridge 171:3a7713b1edbc 475 __IO uint32_t EVENTS_RXDREADY; /*!< Two-wire ready to deliver new RXD byte received. */
AnnaBridge 171:3a7713b1edbc 476 __I uint32_t RESERVED4[4];
AnnaBridge 171:3a7713b1edbc 477 __IO uint32_t EVENTS_TXDSENT; /*!< Two-wire finished sending last TXD byte. */
AnnaBridge 171:3a7713b1edbc 478 __I uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 479 __IO uint32_t EVENTS_ERROR; /*!< Two-wire error detected. */
AnnaBridge 171:3a7713b1edbc 480 __I uint32_t RESERVED6[4];
AnnaBridge 171:3a7713b1edbc 481 __IO uint32_t EVENTS_BB; /*!< Two-wire byte boundary. */
AnnaBridge 171:3a7713b1edbc 482 __I uint32_t RESERVED7[3];
AnnaBridge 171:3a7713b1edbc 483 __IO uint32_t EVENTS_SUSPENDED; /*!< Two-wire suspended. */
AnnaBridge 171:3a7713b1edbc 484 __I uint32_t RESERVED8[45];
AnnaBridge 171:3a7713b1edbc 485 __IO uint32_t SHORTS; /*!< Shortcuts for TWI. */
AnnaBridge 171:3a7713b1edbc 486 __I uint32_t RESERVED9[64];
AnnaBridge 171:3a7713b1edbc 487 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 488 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 489 __I uint32_t RESERVED10[110];
AnnaBridge 171:3a7713b1edbc 490 __IO uint32_t ERRORSRC; /*!< Two-wire error source. Write error field to 1 to clear error. */
AnnaBridge 171:3a7713b1edbc 491 __I uint32_t RESERVED11[14];
AnnaBridge 171:3a7713b1edbc 492 __IO uint32_t ENABLE; /*!< Enable two-wire master. */
AnnaBridge 171:3a7713b1edbc 493 __I uint32_t RESERVED12;
AnnaBridge 171:3a7713b1edbc 494 __IO uint32_t PSELSCL; /*!< Pin select for SCL. */
AnnaBridge 171:3a7713b1edbc 495 __IO uint32_t PSELSDA; /*!< Pin select for SDA. */
AnnaBridge 171:3a7713b1edbc 496 __I uint32_t RESERVED13[2];
AnnaBridge 171:3a7713b1edbc 497 __I uint32_t RXD; /*!< RX data register. */
AnnaBridge 171:3a7713b1edbc 498 __IO uint32_t TXD; /*!< TX data register. */
AnnaBridge 171:3a7713b1edbc 499 __I uint32_t RESERVED14;
AnnaBridge 171:3a7713b1edbc 500 __IO uint32_t FREQUENCY; /*!< Two-wire frequency. */
AnnaBridge 171:3a7713b1edbc 501 __I uint32_t RESERVED15[24];
AnnaBridge 171:3a7713b1edbc 502 __IO uint32_t ADDRESS; /*!< Address used in the two-wire transfer. */
AnnaBridge 171:3a7713b1edbc 503 __I uint32_t RESERVED16[668];
AnnaBridge 171:3a7713b1edbc 504 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 505 } NRF_TWI_Type;
AnnaBridge 171:3a7713b1edbc 506
AnnaBridge 171:3a7713b1edbc 507
AnnaBridge 171:3a7713b1edbc 508 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 509 /* ================ SPIS ================ */
AnnaBridge 171:3a7713b1edbc 510 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 511
AnnaBridge 171:3a7713b1edbc 512
AnnaBridge 171:3a7713b1edbc 513 /**
AnnaBridge 171:3a7713b1edbc 514 * @brief SPI slave 1. (SPIS)
AnnaBridge 171:3a7713b1edbc 515 */
AnnaBridge 171:3a7713b1edbc 516
AnnaBridge 171:3a7713b1edbc 517 typedef struct { /*!< SPIS Structure */
AnnaBridge 171:3a7713b1edbc 518 __I uint32_t RESERVED0[9];
AnnaBridge 171:3a7713b1edbc 519 __O uint32_t TASKS_ACQUIRE; /*!< Acquire SPI semaphore. */
AnnaBridge 171:3a7713b1edbc 520 __O uint32_t TASKS_RELEASE; /*!< Release SPI semaphore. */
AnnaBridge 171:3a7713b1edbc 521 __I uint32_t RESERVED1[54];
AnnaBridge 171:3a7713b1edbc 522 __IO uint32_t EVENTS_END; /*!< Granted transaction completed. */
AnnaBridge 171:3a7713b1edbc 523 __I uint32_t RESERVED2[2];
AnnaBridge 171:3a7713b1edbc 524 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached */
AnnaBridge 171:3a7713b1edbc 525 __I uint32_t RESERVED3[5];
AnnaBridge 171:3a7713b1edbc 526 __IO uint32_t EVENTS_ACQUIRED; /*!< Semaphore acquired. */
AnnaBridge 171:3a7713b1edbc 527 __I uint32_t RESERVED4[53];
AnnaBridge 171:3a7713b1edbc 528 __IO uint32_t SHORTS; /*!< Shortcuts for SPIS. */
AnnaBridge 171:3a7713b1edbc 529 __I uint32_t RESERVED5[64];
AnnaBridge 171:3a7713b1edbc 530 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 531 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 532 __I uint32_t RESERVED6[61];
AnnaBridge 171:3a7713b1edbc 533 __I uint32_t SEMSTAT; /*!< Semaphore status. */
AnnaBridge 171:3a7713b1edbc 534 __I uint32_t RESERVED7[15];
AnnaBridge 171:3a7713b1edbc 535 __IO uint32_t STATUS; /*!< Status from last transaction. */
AnnaBridge 171:3a7713b1edbc 536 __I uint32_t RESERVED8[47];
AnnaBridge 171:3a7713b1edbc 537 __IO uint32_t ENABLE; /*!< Enable SPIS. */
AnnaBridge 171:3a7713b1edbc 538 __I uint32_t RESERVED9;
AnnaBridge 171:3a7713b1edbc 539 __IO uint32_t PSELSCK; /*!< Pin select for SCK. */
AnnaBridge 171:3a7713b1edbc 540 __IO uint32_t PSELMISO; /*!< Pin select for MISO. */
AnnaBridge 171:3a7713b1edbc 541 __IO uint32_t PSELMOSI; /*!< Pin select for MOSI. */
AnnaBridge 171:3a7713b1edbc 542 __IO uint32_t PSELCSN; /*!< Pin select for CSN. */
AnnaBridge 171:3a7713b1edbc 543 __I uint32_t RESERVED10[7];
AnnaBridge 171:3a7713b1edbc 544 __IO uint32_t RXDPTR; /*!< RX data pointer. */
AnnaBridge 171:3a7713b1edbc 545 __IO uint32_t MAXRX; /*!< Maximum number of bytes in the receive buffer. */
AnnaBridge 171:3a7713b1edbc 546 __I uint32_t AMOUNTRX; /*!< Number of bytes received in last granted transaction. */
AnnaBridge 171:3a7713b1edbc 547 __I uint32_t RESERVED11;
AnnaBridge 171:3a7713b1edbc 548 __IO uint32_t TXDPTR; /*!< TX data pointer. */
AnnaBridge 171:3a7713b1edbc 549 __IO uint32_t MAXTX; /*!< Maximum number of bytes in the transmit buffer. */
AnnaBridge 171:3a7713b1edbc 550 __I uint32_t AMOUNTTX; /*!< Number of bytes transmitted in last granted transaction. */
AnnaBridge 171:3a7713b1edbc 551 __I uint32_t RESERVED12;
AnnaBridge 171:3a7713b1edbc 552 __IO uint32_t CONFIG; /*!< Configuration register. */
AnnaBridge 171:3a7713b1edbc 553 __I uint32_t RESERVED13;
AnnaBridge 171:3a7713b1edbc 554 __IO uint32_t DEF; /*!< Default character. */
AnnaBridge 171:3a7713b1edbc 555 __I uint32_t RESERVED14[24];
AnnaBridge 171:3a7713b1edbc 556 __IO uint32_t ORC; /*!< Over-read character. */
AnnaBridge 171:3a7713b1edbc 557 __I uint32_t RESERVED15[654];
AnnaBridge 171:3a7713b1edbc 558 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 559 } NRF_SPIS_Type;
AnnaBridge 171:3a7713b1edbc 560
AnnaBridge 171:3a7713b1edbc 561
AnnaBridge 171:3a7713b1edbc 562 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 563 /* ================ SPIM ================ */
AnnaBridge 171:3a7713b1edbc 564 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 565
AnnaBridge 171:3a7713b1edbc 566
AnnaBridge 171:3a7713b1edbc 567 /**
AnnaBridge 171:3a7713b1edbc 568 * @brief SPI master with easyDMA 1. (SPIM)
AnnaBridge 171:3a7713b1edbc 569 */
AnnaBridge 171:3a7713b1edbc 570
AnnaBridge 171:3a7713b1edbc 571 typedef struct { /*!< SPIM Structure */
AnnaBridge 171:3a7713b1edbc 572 __I uint32_t RESERVED0[4];
AnnaBridge 171:3a7713b1edbc 573 __O uint32_t TASKS_START; /*!< Start SPI transaction. */
AnnaBridge 171:3a7713b1edbc 574 __O uint32_t TASKS_STOP; /*!< Stop SPI transaction. */
AnnaBridge 171:3a7713b1edbc 575 __I uint32_t RESERVED1;
AnnaBridge 171:3a7713b1edbc 576 __O uint32_t TASKS_SUSPEND; /*!< Suspend SPI transaction. */
AnnaBridge 171:3a7713b1edbc 577 __O uint32_t TASKS_RESUME; /*!< Resume SPI transaction. */
AnnaBridge 171:3a7713b1edbc 578 __I uint32_t RESERVED2[56];
AnnaBridge 171:3a7713b1edbc 579 __IO uint32_t EVENTS_STOPPED; /*!< SPI transaction has stopped. */
AnnaBridge 171:3a7713b1edbc 580 __I uint32_t RESERVED3[2];
AnnaBridge 171:3a7713b1edbc 581 __IO uint32_t EVENTS_ENDRX; /*!< End of RXD buffer reached. */
AnnaBridge 171:3a7713b1edbc 582 __I uint32_t RESERVED4[3];
AnnaBridge 171:3a7713b1edbc 583 __IO uint32_t EVENTS_ENDTX; /*!< End of TXD buffer reached. */
AnnaBridge 171:3a7713b1edbc 584 __I uint32_t RESERVED5[10];
AnnaBridge 171:3a7713b1edbc 585 __IO uint32_t EVENTS_STARTED; /*!< Transaction started. */
AnnaBridge 171:3a7713b1edbc 586 __I uint32_t RESERVED6[109];
AnnaBridge 171:3a7713b1edbc 587 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 588 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 589 __I uint32_t RESERVED7[125];
AnnaBridge 171:3a7713b1edbc 590 __IO uint32_t ENABLE; /*!< Enable SPIM. */
AnnaBridge 171:3a7713b1edbc 591 __I uint32_t RESERVED8;
AnnaBridge 171:3a7713b1edbc 592 SPIM_PSEL_Type PSEL; /*!< Pin select configuration. */
AnnaBridge 171:3a7713b1edbc 593 __I uint32_t RESERVED9[4];
AnnaBridge 171:3a7713b1edbc 594 __IO uint32_t FREQUENCY; /*!< SPI frequency. */
AnnaBridge 171:3a7713b1edbc 595 __I uint32_t RESERVED10[3];
AnnaBridge 171:3a7713b1edbc 596 SPIM_RXD_Type RXD; /*!< RXD EasyDMA configuration and status. */
AnnaBridge 171:3a7713b1edbc 597 __I uint32_t RESERVED11;
AnnaBridge 171:3a7713b1edbc 598 SPIM_TXD_Type TXD; /*!< TXD EasyDMA configuration and status. */
AnnaBridge 171:3a7713b1edbc 599 __I uint32_t RESERVED12;
AnnaBridge 171:3a7713b1edbc 600 __IO uint32_t CONFIG; /*!< Configuration register. */
AnnaBridge 171:3a7713b1edbc 601 __I uint32_t RESERVED13[26];
AnnaBridge 171:3a7713b1edbc 602 __IO uint32_t ORC; /*!< Over-read character. */
AnnaBridge 171:3a7713b1edbc 603 __I uint32_t RESERVED14[654];
AnnaBridge 171:3a7713b1edbc 604 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 605 } NRF_SPIM_Type;
AnnaBridge 171:3a7713b1edbc 606
AnnaBridge 171:3a7713b1edbc 607
AnnaBridge 171:3a7713b1edbc 608 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 609 /* ================ GPIOTE ================ */
AnnaBridge 171:3a7713b1edbc 610 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 611
AnnaBridge 171:3a7713b1edbc 612
AnnaBridge 171:3a7713b1edbc 613 /**
AnnaBridge 171:3a7713b1edbc 614 * @brief GPIO tasks and events. (GPIOTE)
AnnaBridge 171:3a7713b1edbc 615 */
AnnaBridge 171:3a7713b1edbc 616
AnnaBridge 171:3a7713b1edbc 617 typedef struct { /*!< GPIOTE Structure */
AnnaBridge 171:3a7713b1edbc 618 __O uint32_t TASKS_OUT[4]; /*!< Tasks asssociated with GPIOTE channels. */
AnnaBridge 171:3a7713b1edbc 619 __I uint32_t RESERVED0[60];
AnnaBridge 171:3a7713b1edbc 620 __IO uint32_t EVENTS_IN[4]; /*!< Tasks asssociated with GPIOTE channels. */
AnnaBridge 171:3a7713b1edbc 621 __I uint32_t RESERVED1[27];
AnnaBridge 171:3a7713b1edbc 622 __IO uint32_t EVENTS_PORT; /*!< Event generated from multiple pins. */
AnnaBridge 171:3a7713b1edbc 623 __I uint32_t RESERVED2[97];
AnnaBridge 171:3a7713b1edbc 624 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 625 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 626 __I uint32_t RESERVED3[129];
AnnaBridge 171:3a7713b1edbc 627 __IO uint32_t CONFIG[4]; /*!< Channel configuration registers. */
AnnaBridge 171:3a7713b1edbc 628 __I uint32_t RESERVED4[695];
AnnaBridge 171:3a7713b1edbc 629 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 630 } NRF_GPIOTE_Type;
AnnaBridge 171:3a7713b1edbc 631
AnnaBridge 171:3a7713b1edbc 632
AnnaBridge 171:3a7713b1edbc 633 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 634 /* ================ ADC ================ */
AnnaBridge 171:3a7713b1edbc 635 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 636
AnnaBridge 171:3a7713b1edbc 637
AnnaBridge 171:3a7713b1edbc 638 /**
AnnaBridge 171:3a7713b1edbc 639 * @brief Analog to digital converter. (ADC)
AnnaBridge 171:3a7713b1edbc 640 */
AnnaBridge 171:3a7713b1edbc 641
AnnaBridge 171:3a7713b1edbc 642 typedef struct { /*!< ADC Structure */
AnnaBridge 171:3a7713b1edbc 643 __O uint32_t TASKS_START; /*!< Start an ADC conversion. */
AnnaBridge 171:3a7713b1edbc 644 __O uint32_t TASKS_STOP; /*!< Stop ADC. */
AnnaBridge 171:3a7713b1edbc 645 __I uint32_t RESERVED0[62];
AnnaBridge 171:3a7713b1edbc 646 __IO uint32_t EVENTS_END; /*!< ADC conversion complete. */
AnnaBridge 171:3a7713b1edbc 647 __I uint32_t RESERVED1[128];
AnnaBridge 171:3a7713b1edbc 648 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 649 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 650 __I uint32_t RESERVED2[61];
AnnaBridge 171:3a7713b1edbc 651 __I uint32_t BUSY; /*!< ADC busy register. */
AnnaBridge 171:3a7713b1edbc 652 __I uint32_t RESERVED3[63];
AnnaBridge 171:3a7713b1edbc 653 __IO uint32_t ENABLE; /*!< ADC enable. */
AnnaBridge 171:3a7713b1edbc 654 __IO uint32_t CONFIG; /*!< ADC configuration register. */
AnnaBridge 171:3a7713b1edbc 655 __I uint32_t RESULT; /*!< Result of ADC conversion. */
AnnaBridge 171:3a7713b1edbc 656 __I uint32_t RESERVED4[700];
AnnaBridge 171:3a7713b1edbc 657 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 658 } NRF_ADC_Type;
AnnaBridge 171:3a7713b1edbc 659
AnnaBridge 171:3a7713b1edbc 660
AnnaBridge 171:3a7713b1edbc 661 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 662 /* ================ TIMER ================ */
AnnaBridge 171:3a7713b1edbc 663 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 664
AnnaBridge 171:3a7713b1edbc 665
AnnaBridge 171:3a7713b1edbc 666 /**
AnnaBridge 171:3a7713b1edbc 667 * @brief Timer 0. (TIMER)
AnnaBridge 171:3a7713b1edbc 668 */
AnnaBridge 171:3a7713b1edbc 669
AnnaBridge 171:3a7713b1edbc 670 typedef struct { /*!< TIMER Structure */
AnnaBridge 171:3a7713b1edbc 671 __O uint32_t TASKS_START; /*!< Start Timer. */
AnnaBridge 171:3a7713b1edbc 672 __O uint32_t TASKS_STOP; /*!< Stop Timer. */
AnnaBridge 171:3a7713b1edbc 673 __O uint32_t TASKS_COUNT; /*!< Increment Timer (In counter mode). */
AnnaBridge 171:3a7713b1edbc 674 __O uint32_t TASKS_CLEAR; /*!< Clear timer. */
AnnaBridge 171:3a7713b1edbc 675 __O uint32_t TASKS_SHUTDOWN; /*!< Shutdown timer. */
AnnaBridge 171:3a7713b1edbc 676 __I uint32_t RESERVED0[11];
AnnaBridge 171:3a7713b1edbc 677 __O uint32_t TASKS_CAPTURE[4]; /*!< Capture Timer value to CC[n] registers. */
AnnaBridge 171:3a7713b1edbc 678 __I uint32_t RESERVED1[60];
AnnaBridge 171:3a7713b1edbc 679 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
AnnaBridge 171:3a7713b1edbc 680 __I uint32_t RESERVED2[44];
AnnaBridge 171:3a7713b1edbc 681 __IO uint32_t SHORTS; /*!< Shortcuts for Timer. */
AnnaBridge 171:3a7713b1edbc 682 __I uint32_t RESERVED3[64];
AnnaBridge 171:3a7713b1edbc 683 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 684 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 685 __I uint32_t RESERVED4[126];
AnnaBridge 171:3a7713b1edbc 686 __IO uint32_t MODE; /*!< Timer Mode selection. */
AnnaBridge 171:3a7713b1edbc 687 __IO uint32_t BITMODE; /*!< Sets timer behaviour. */
AnnaBridge 171:3a7713b1edbc 688 __I uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 689 __IO uint32_t PRESCALER; /*!< 4-bit prescaler to source clock frequency (max value 9). Source
AnnaBridge 171:3a7713b1edbc 690 clock frequency is divided by 2^SCALE. */
AnnaBridge 171:3a7713b1edbc 691 __I uint32_t RESERVED6[11];
AnnaBridge 171:3a7713b1edbc 692 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
AnnaBridge 171:3a7713b1edbc 693 __I uint32_t RESERVED7[683];
AnnaBridge 171:3a7713b1edbc 694 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 695 } NRF_TIMER_Type;
AnnaBridge 171:3a7713b1edbc 696
AnnaBridge 171:3a7713b1edbc 697
AnnaBridge 171:3a7713b1edbc 698 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 699 /* ================ RTC ================ */
AnnaBridge 171:3a7713b1edbc 700 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 701
AnnaBridge 171:3a7713b1edbc 702
AnnaBridge 171:3a7713b1edbc 703 /**
AnnaBridge 171:3a7713b1edbc 704 * @brief Real time counter 0. (RTC)
AnnaBridge 171:3a7713b1edbc 705 */
AnnaBridge 171:3a7713b1edbc 706
AnnaBridge 171:3a7713b1edbc 707 typedef struct { /*!< RTC Structure */
AnnaBridge 171:3a7713b1edbc 708 __O uint32_t TASKS_START; /*!< Start RTC Counter. */
AnnaBridge 171:3a7713b1edbc 709 __O uint32_t TASKS_STOP; /*!< Stop RTC Counter. */
AnnaBridge 171:3a7713b1edbc 710 __O uint32_t TASKS_CLEAR; /*!< Clear RTC Counter. */
AnnaBridge 171:3a7713b1edbc 711 __O uint32_t TASKS_TRIGOVRFLW; /*!< Set COUNTER to 0xFFFFFFF0. */
AnnaBridge 171:3a7713b1edbc 712 __I uint32_t RESERVED0[60];
AnnaBridge 171:3a7713b1edbc 713 __IO uint32_t EVENTS_TICK; /*!< Event on COUNTER increment. */
AnnaBridge 171:3a7713b1edbc 714 __IO uint32_t EVENTS_OVRFLW; /*!< Event on COUNTER overflow. */
AnnaBridge 171:3a7713b1edbc 715 __I uint32_t RESERVED1[14];
AnnaBridge 171:3a7713b1edbc 716 __IO uint32_t EVENTS_COMPARE[4]; /*!< Compare event on CC[n] match. */
AnnaBridge 171:3a7713b1edbc 717 __I uint32_t RESERVED2[109];
AnnaBridge 171:3a7713b1edbc 718 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 719 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 720 __I uint32_t RESERVED3[13];
AnnaBridge 171:3a7713b1edbc 721 __IO uint32_t EVTEN; /*!< Configures event enable routing to PPI for each RTC event. */
AnnaBridge 171:3a7713b1edbc 722 __IO uint32_t EVTENSET; /*!< Enable events routing to PPI. The reading of this register gives
AnnaBridge 171:3a7713b1edbc 723 the value of EVTEN. */
AnnaBridge 171:3a7713b1edbc 724 __IO uint32_t EVTENCLR; /*!< Disable events routing to PPI. The reading of this register
AnnaBridge 171:3a7713b1edbc 725 gives the value of EVTEN. */
AnnaBridge 171:3a7713b1edbc 726 __I uint32_t RESERVED4[110];
AnnaBridge 171:3a7713b1edbc 727 __I uint32_t COUNTER; /*!< Current COUNTER value. */
AnnaBridge 171:3a7713b1edbc 728 __IO uint32_t PRESCALER; /*!< 12-bit prescaler for COUNTER frequency (32768/(PRESCALER+1)).
AnnaBridge 171:3a7713b1edbc 729 Must be written when RTC is STOPed. */
AnnaBridge 171:3a7713b1edbc 730 __I uint32_t RESERVED5[13];
AnnaBridge 171:3a7713b1edbc 731 __IO uint32_t CC[4]; /*!< Capture/compare registers. */
AnnaBridge 171:3a7713b1edbc 732 __I uint32_t RESERVED6[683];
AnnaBridge 171:3a7713b1edbc 733 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 734 } NRF_RTC_Type;
AnnaBridge 171:3a7713b1edbc 735
AnnaBridge 171:3a7713b1edbc 736
AnnaBridge 171:3a7713b1edbc 737 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 738 /* ================ TEMP ================ */
AnnaBridge 171:3a7713b1edbc 739 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 740
AnnaBridge 171:3a7713b1edbc 741
AnnaBridge 171:3a7713b1edbc 742 /**
AnnaBridge 171:3a7713b1edbc 743 * @brief Temperature Sensor. (TEMP)
AnnaBridge 171:3a7713b1edbc 744 */
AnnaBridge 171:3a7713b1edbc 745
AnnaBridge 171:3a7713b1edbc 746 typedef struct { /*!< TEMP Structure */
AnnaBridge 171:3a7713b1edbc 747 __O uint32_t TASKS_START; /*!< Start temperature measurement. */
AnnaBridge 171:3a7713b1edbc 748 __O uint32_t TASKS_STOP; /*!< Stop temperature measurement. */
AnnaBridge 171:3a7713b1edbc 749 __I uint32_t RESERVED0[62];
AnnaBridge 171:3a7713b1edbc 750 __IO uint32_t EVENTS_DATARDY; /*!< Temperature measurement complete, data ready event. */
AnnaBridge 171:3a7713b1edbc 751 __I uint32_t RESERVED1[128];
AnnaBridge 171:3a7713b1edbc 752 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 753 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 754 __I uint32_t RESERVED2[127];
AnnaBridge 171:3a7713b1edbc 755 __I int32_t TEMP; /*!< Die temperature in degC, 2's complement format, 0.25 degC pecision. */
AnnaBridge 171:3a7713b1edbc 756 __I uint32_t RESERVED3[700];
AnnaBridge 171:3a7713b1edbc 757 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 758 } NRF_TEMP_Type;
AnnaBridge 171:3a7713b1edbc 759
AnnaBridge 171:3a7713b1edbc 760
AnnaBridge 171:3a7713b1edbc 761 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 762 /* ================ RNG ================ */
AnnaBridge 171:3a7713b1edbc 763 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 764
AnnaBridge 171:3a7713b1edbc 765
AnnaBridge 171:3a7713b1edbc 766 /**
AnnaBridge 171:3a7713b1edbc 767 * @brief Random Number Generator. (RNG)
AnnaBridge 171:3a7713b1edbc 768 */
AnnaBridge 171:3a7713b1edbc 769
AnnaBridge 171:3a7713b1edbc 770 typedef struct { /*!< RNG Structure */
AnnaBridge 171:3a7713b1edbc 771 __O uint32_t TASKS_START; /*!< Start the random number generator. */
AnnaBridge 171:3a7713b1edbc 772 __O uint32_t TASKS_STOP; /*!< Stop the random number generator. */
AnnaBridge 171:3a7713b1edbc 773 __I uint32_t RESERVED0[62];
AnnaBridge 171:3a7713b1edbc 774 __IO uint32_t EVENTS_VALRDY; /*!< New random number generated and written to VALUE register. */
AnnaBridge 171:3a7713b1edbc 775 __I uint32_t RESERVED1[63];
AnnaBridge 171:3a7713b1edbc 776 __IO uint32_t SHORTS; /*!< Shortcuts for the RNG. */
AnnaBridge 171:3a7713b1edbc 777 __I uint32_t RESERVED2[64];
AnnaBridge 171:3a7713b1edbc 778 __IO uint32_t INTENSET; /*!< Interrupt enable set register */
AnnaBridge 171:3a7713b1edbc 779 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register */
AnnaBridge 171:3a7713b1edbc 780 __I uint32_t RESERVED3[126];
AnnaBridge 171:3a7713b1edbc 781 __IO uint32_t CONFIG; /*!< Configuration register. */
AnnaBridge 171:3a7713b1edbc 782 __I uint32_t VALUE; /*!< RNG random number. */
AnnaBridge 171:3a7713b1edbc 783 __I uint32_t RESERVED4[700];
AnnaBridge 171:3a7713b1edbc 784 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 785 } NRF_RNG_Type;
AnnaBridge 171:3a7713b1edbc 786
AnnaBridge 171:3a7713b1edbc 787
AnnaBridge 171:3a7713b1edbc 788 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 789 /* ================ ECB ================ */
AnnaBridge 171:3a7713b1edbc 790 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 791
AnnaBridge 171:3a7713b1edbc 792
AnnaBridge 171:3a7713b1edbc 793 /**
AnnaBridge 171:3a7713b1edbc 794 * @brief AES ECB Mode Encryption. (ECB)
AnnaBridge 171:3a7713b1edbc 795 */
AnnaBridge 171:3a7713b1edbc 796
AnnaBridge 171:3a7713b1edbc 797 typedef struct { /*!< ECB Structure */
AnnaBridge 171:3a7713b1edbc 798 __O uint32_t TASKS_STARTECB; /*!< Start ECB block encrypt. If a crypto operation is running, this
AnnaBridge 171:3a7713b1edbc 799 will not initiate a new encryption and the ERRORECB event will
AnnaBridge 171:3a7713b1edbc 800 be triggered. */
AnnaBridge 171:3a7713b1edbc 801 __O uint32_t TASKS_STOPECB; /*!< Stop current ECB encryption. If a crypto operation is running,
AnnaBridge 171:3a7713b1edbc 802 this will will trigger the ERRORECB event. */
AnnaBridge 171:3a7713b1edbc 803 __I uint32_t RESERVED0[62];
AnnaBridge 171:3a7713b1edbc 804 __IO uint32_t EVENTS_ENDECB; /*!< ECB block encrypt complete. */
AnnaBridge 171:3a7713b1edbc 805 __IO uint32_t EVENTS_ERRORECB; /*!< ECB block encrypt aborted due to a STOPECB task or due to an
AnnaBridge 171:3a7713b1edbc 806 error. */
AnnaBridge 171:3a7713b1edbc 807 __I uint32_t RESERVED1[127];
AnnaBridge 171:3a7713b1edbc 808 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 809 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 810 __I uint32_t RESERVED2[126];
AnnaBridge 171:3a7713b1edbc 811 __IO uint32_t ECBDATAPTR; /*!< ECB block encrypt memory pointer. */
AnnaBridge 171:3a7713b1edbc 812 __I uint32_t RESERVED3[701];
AnnaBridge 171:3a7713b1edbc 813 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 814 } NRF_ECB_Type;
AnnaBridge 171:3a7713b1edbc 815
AnnaBridge 171:3a7713b1edbc 816
AnnaBridge 171:3a7713b1edbc 817 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 818 /* ================ AAR ================ */
AnnaBridge 171:3a7713b1edbc 819 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 820
AnnaBridge 171:3a7713b1edbc 821
AnnaBridge 171:3a7713b1edbc 822 /**
AnnaBridge 171:3a7713b1edbc 823 * @brief Accelerated Address Resolver. (AAR)
AnnaBridge 171:3a7713b1edbc 824 */
AnnaBridge 171:3a7713b1edbc 825
AnnaBridge 171:3a7713b1edbc 826 typedef struct { /*!< AAR Structure */
AnnaBridge 171:3a7713b1edbc 827 __O uint32_t TASKS_START; /*!< Start resolving addresses based on IRKs specified in the IRK
AnnaBridge 171:3a7713b1edbc 828 data structure. */
AnnaBridge 171:3a7713b1edbc 829 __I uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 830 __O uint32_t TASKS_STOP; /*!< Stop resolving addresses. */
AnnaBridge 171:3a7713b1edbc 831 __I uint32_t RESERVED1[61];
AnnaBridge 171:3a7713b1edbc 832 __IO uint32_t EVENTS_END; /*!< Address resolution procedure completed. */
AnnaBridge 171:3a7713b1edbc 833 __IO uint32_t EVENTS_RESOLVED; /*!< Address resolved. */
AnnaBridge 171:3a7713b1edbc 834 __IO uint32_t EVENTS_NOTRESOLVED; /*!< Address not resolved. */
AnnaBridge 171:3a7713b1edbc 835 __I uint32_t RESERVED2[126];
AnnaBridge 171:3a7713b1edbc 836 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 837 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 838 __I uint32_t RESERVED3[61];
AnnaBridge 171:3a7713b1edbc 839 __I uint32_t STATUS; /*!< Resolution status. */
AnnaBridge 171:3a7713b1edbc 840 __I uint32_t RESERVED4[63];
AnnaBridge 171:3a7713b1edbc 841 __IO uint32_t ENABLE; /*!< Enable AAR. */
AnnaBridge 171:3a7713b1edbc 842 __IO uint32_t NIRK; /*!< Number of Identity root Keys in the IRK data structure. */
AnnaBridge 171:3a7713b1edbc 843 __IO uint32_t IRKPTR; /*!< Pointer to the IRK data structure. */
AnnaBridge 171:3a7713b1edbc 844 __I uint32_t RESERVED5;
AnnaBridge 171:3a7713b1edbc 845 __IO uint32_t ADDRPTR; /*!< Pointer to the resolvable address (6 bytes). */
AnnaBridge 171:3a7713b1edbc 846 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
AnnaBridge 171:3a7713b1edbc 847 during resolution. A minimum of 3 bytes must be reserved. */
AnnaBridge 171:3a7713b1edbc 848 __I uint32_t RESERVED6[697];
AnnaBridge 171:3a7713b1edbc 849 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 850 } NRF_AAR_Type;
AnnaBridge 171:3a7713b1edbc 851
AnnaBridge 171:3a7713b1edbc 852
AnnaBridge 171:3a7713b1edbc 853 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 854 /* ================ CCM ================ */
AnnaBridge 171:3a7713b1edbc 855 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 856
AnnaBridge 171:3a7713b1edbc 857
AnnaBridge 171:3a7713b1edbc 858 /**
AnnaBridge 171:3a7713b1edbc 859 * @brief AES CCM Mode Encryption. (CCM)
AnnaBridge 171:3a7713b1edbc 860 */
AnnaBridge 171:3a7713b1edbc 861
AnnaBridge 171:3a7713b1edbc 862 typedef struct { /*!< CCM Structure */
AnnaBridge 171:3a7713b1edbc 863 __O uint32_t TASKS_KSGEN; /*!< Start generation of key-stream. This operation will stop by
AnnaBridge 171:3a7713b1edbc 864 itself when completed. */
AnnaBridge 171:3a7713b1edbc 865 __O uint32_t TASKS_CRYPT; /*!< Start encrypt/decrypt. This operation will stop by itself when
AnnaBridge 171:3a7713b1edbc 866 completed. */
AnnaBridge 171:3a7713b1edbc 867 __O uint32_t TASKS_STOP; /*!< Stop encrypt/decrypt. */
AnnaBridge 171:3a7713b1edbc 868 __I uint32_t RESERVED0[61];
AnnaBridge 171:3a7713b1edbc 869 __IO uint32_t EVENTS_ENDKSGEN; /*!< Keystream generation completed. */
AnnaBridge 171:3a7713b1edbc 870 __IO uint32_t EVENTS_ENDCRYPT; /*!< Encrypt/decrypt completed. */
AnnaBridge 171:3a7713b1edbc 871 __IO uint32_t EVENTS_ERROR; /*!< Error happened. */
AnnaBridge 171:3a7713b1edbc 872 __I uint32_t RESERVED1[61];
AnnaBridge 171:3a7713b1edbc 873 __IO uint32_t SHORTS; /*!< Shortcuts for the CCM. */
AnnaBridge 171:3a7713b1edbc 874 __I uint32_t RESERVED2[64];
AnnaBridge 171:3a7713b1edbc 875 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 876 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 877 __I uint32_t RESERVED3[61];
AnnaBridge 171:3a7713b1edbc 878 __I uint32_t MICSTATUS; /*!< CCM RX MIC check result. */
AnnaBridge 171:3a7713b1edbc 879 __I uint32_t RESERVED4[63];
AnnaBridge 171:3a7713b1edbc 880 __IO uint32_t ENABLE; /*!< CCM enable. */
AnnaBridge 171:3a7713b1edbc 881 __IO uint32_t MODE; /*!< Operation mode. */
AnnaBridge 171:3a7713b1edbc 882 __IO uint32_t CNFPTR; /*!< Pointer to a data structure holding AES key and NONCE vector. */
AnnaBridge 171:3a7713b1edbc 883 __IO uint32_t INPTR; /*!< Pointer to the input packet. */
AnnaBridge 171:3a7713b1edbc 884 __IO uint32_t OUTPTR; /*!< Pointer to the output packet. */
AnnaBridge 171:3a7713b1edbc 885 __IO uint32_t SCRATCHPTR; /*!< Pointer to a "scratch" data area used for temporary storage
AnnaBridge 171:3a7713b1edbc 886 during resolution. A minimum of 43 bytes must be reserved. */
AnnaBridge 171:3a7713b1edbc 887 __I uint32_t RESERVED5[697];
AnnaBridge 171:3a7713b1edbc 888 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 889 } NRF_CCM_Type;
AnnaBridge 171:3a7713b1edbc 890
AnnaBridge 171:3a7713b1edbc 891
AnnaBridge 171:3a7713b1edbc 892 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 893 /* ================ WDT ================ */
AnnaBridge 171:3a7713b1edbc 894 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 895
AnnaBridge 171:3a7713b1edbc 896
AnnaBridge 171:3a7713b1edbc 897 /**
AnnaBridge 171:3a7713b1edbc 898 * @brief Watchdog Timer. (WDT)
AnnaBridge 171:3a7713b1edbc 899 */
AnnaBridge 171:3a7713b1edbc 900
AnnaBridge 171:3a7713b1edbc 901 typedef struct { /*!< WDT Structure */
AnnaBridge 171:3a7713b1edbc 902 __O uint32_t TASKS_START; /*!< Start the watchdog. */
AnnaBridge 171:3a7713b1edbc 903 __I uint32_t RESERVED0[63];
AnnaBridge 171:3a7713b1edbc 904 __IO uint32_t EVENTS_TIMEOUT; /*!< Watchdog timeout. */
AnnaBridge 171:3a7713b1edbc 905 __I uint32_t RESERVED1[128];
AnnaBridge 171:3a7713b1edbc 906 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 907 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 908 __I uint32_t RESERVED2[61];
AnnaBridge 171:3a7713b1edbc 909 __I uint32_t RUNSTATUS; /*!< Watchdog running status. */
AnnaBridge 171:3a7713b1edbc 910 __I uint32_t REQSTATUS; /*!< Request status. */
AnnaBridge 171:3a7713b1edbc 911 __I uint32_t RESERVED3[63];
AnnaBridge 171:3a7713b1edbc 912 __IO uint32_t CRV; /*!< Counter reload value in number of 32kiHz clock cycles. */
AnnaBridge 171:3a7713b1edbc 913 __IO uint32_t RREN; /*!< Reload request enable. */
AnnaBridge 171:3a7713b1edbc 914 __IO uint32_t CONFIG; /*!< Configuration register. */
AnnaBridge 171:3a7713b1edbc 915 __I uint32_t RESERVED4[60];
AnnaBridge 171:3a7713b1edbc 916 __O uint32_t RR[8]; /*!< Reload requests registers. */
AnnaBridge 171:3a7713b1edbc 917 __I uint32_t RESERVED5[631];
AnnaBridge 171:3a7713b1edbc 918 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 919 } NRF_WDT_Type;
AnnaBridge 171:3a7713b1edbc 920
AnnaBridge 171:3a7713b1edbc 921
AnnaBridge 171:3a7713b1edbc 922 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 923 /* ================ QDEC ================ */
AnnaBridge 171:3a7713b1edbc 924 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 925
AnnaBridge 171:3a7713b1edbc 926
AnnaBridge 171:3a7713b1edbc 927 /**
AnnaBridge 171:3a7713b1edbc 928 * @brief Rotary decoder. (QDEC)
AnnaBridge 171:3a7713b1edbc 929 */
AnnaBridge 171:3a7713b1edbc 930
AnnaBridge 171:3a7713b1edbc 931 typedef struct { /*!< QDEC Structure */
AnnaBridge 171:3a7713b1edbc 932 __O uint32_t TASKS_START; /*!< Start the quadrature decoder. */
AnnaBridge 171:3a7713b1edbc 933 __O uint32_t TASKS_STOP; /*!< Stop the quadrature decoder. */
AnnaBridge 171:3a7713b1edbc 934 __O uint32_t TASKS_READCLRACC; /*!< Transfers the content from ACC registers to ACCREAD registers,
AnnaBridge 171:3a7713b1edbc 935 and clears the ACC registers. */
AnnaBridge 171:3a7713b1edbc 936 __I uint32_t RESERVED0[61];
AnnaBridge 171:3a7713b1edbc 937 __IO uint32_t EVENTS_SAMPLERDY; /*!< A new sample is written to the sample register. */
AnnaBridge 171:3a7713b1edbc 938 __IO uint32_t EVENTS_REPORTRDY; /*!< REPORTPER number of samples accumulated in ACC register, and
AnnaBridge 171:3a7713b1edbc 939 ACC register different than zero. */
AnnaBridge 171:3a7713b1edbc 940 __IO uint32_t EVENTS_ACCOF; /*!< ACC or ACCDBL register overflow. */
AnnaBridge 171:3a7713b1edbc 941 __I uint32_t RESERVED1[61];
AnnaBridge 171:3a7713b1edbc 942 __IO uint32_t SHORTS; /*!< Shortcuts for the QDEC. */
AnnaBridge 171:3a7713b1edbc 943 __I uint32_t RESERVED2[64];
AnnaBridge 171:3a7713b1edbc 944 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 945 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 946 __I uint32_t RESERVED3[125];
AnnaBridge 171:3a7713b1edbc 947 __IO uint32_t ENABLE; /*!< Enable the QDEC. */
AnnaBridge 171:3a7713b1edbc 948 __IO uint32_t LEDPOL; /*!< LED output pin polarity. */
AnnaBridge 171:3a7713b1edbc 949 __IO uint32_t SAMPLEPER; /*!< Sample period. */
AnnaBridge 171:3a7713b1edbc 950 __I int32_t SAMPLE; /*!< Motion sample value. */
AnnaBridge 171:3a7713b1edbc 951 __IO uint32_t REPORTPER; /*!< Number of samples to generate an EVENT_REPORTRDY. */
AnnaBridge 171:3a7713b1edbc 952 __I int32_t ACC; /*!< Accumulated valid transitions register. */
AnnaBridge 171:3a7713b1edbc 953 __I int32_t ACCREAD; /*!< Snapshot of ACC register. Value generated by the TASKS_READCLEACC
AnnaBridge 171:3a7713b1edbc 954 task. */
AnnaBridge 171:3a7713b1edbc 955 __IO uint32_t PSELLED; /*!< Pin select for LED output. */
AnnaBridge 171:3a7713b1edbc 956 __IO uint32_t PSELA; /*!< Pin select for phase A input. */
AnnaBridge 171:3a7713b1edbc 957 __IO uint32_t PSELB; /*!< Pin select for phase B input. */
AnnaBridge 171:3a7713b1edbc 958 __IO uint32_t DBFEN; /*!< Enable debouncer input filters. */
AnnaBridge 171:3a7713b1edbc 959 __I uint32_t RESERVED4[5];
AnnaBridge 171:3a7713b1edbc 960 __IO uint32_t LEDPRE; /*!< Time LED is switched ON before the sample. */
AnnaBridge 171:3a7713b1edbc 961 __I uint32_t ACCDBL; /*!< Accumulated double (error) transitions register. */
AnnaBridge 171:3a7713b1edbc 962 __I uint32_t ACCDBLREAD; /*!< Snapshot of ACCDBL register. Value generated by the TASKS_READCLEACC
AnnaBridge 171:3a7713b1edbc 963 task. */
AnnaBridge 171:3a7713b1edbc 964 __I uint32_t RESERVED5[684];
AnnaBridge 171:3a7713b1edbc 965 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 966 } NRF_QDEC_Type;
AnnaBridge 171:3a7713b1edbc 967
AnnaBridge 171:3a7713b1edbc 968
AnnaBridge 171:3a7713b1edbc 969 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 970 /* ================ LPCOMP ================ */
AnnaBridge 171:3a7713b1edbc 971 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 972
AnnaBridge 171:3a7713b1edbc 973
AnnaBridge 171:3a7713b1edbc 974 /**
AnnaBridge 171:3a7713b1edbc 975 * @brief Low power comparator. (LPCOMP)
AnnaBridge 171:3a7713b1edbc 976 */
AnnaBridge 171:3a7713b1edbc 977
AnnaBridge 171:3a7713b1edbc 978 typedef struct { /*!< LPCOMP Structure */
AnnaBridge 171:3a7713b1edbc 979 __O uint32_t TASKS_START; /*!< Start the comparator. */
AnnaBridge 171:3a7713b1edbc 980 __O uint32_t TASKS_STOP; /*!< Stop the comparator. */
AnnaBridge 171:3a7713b1edbc 981 __O uint32_t TASKS_SAMPLE; /*!< Sample comparator value. */
AnnaBridge 171:3a7713b1edbc 982 __I uint32_t RESERVED0[61];
AnnaBridge 171:3a7713b1edbc 983 __IO uint32_t EVENTS_READY; /*!< LPCOMP is ready and output is valid. */
AnnaBridge 171:3a7713b1edbc 984 __IO uint32_t EVENTS_DOWN; /*!< Input voltage crossed the threshold going down. */
AnnaBridge 171:3a7713b1edbc 985 __IO uint32_t EVENTS_UP; /*!< Input voltage crossed the threshold going up. */
AnnaBridge 171:3a7713b1edbc 986 __IO uint32_t EVENTS_CROSS; /*!< Input voltage crossed the threshold in any direction. */
AnnaBridge 171:3a7713b1edbc 987 __I uint32_t RESERVED1[60];
AnnaBridge 171:3a7713b1edbc 988 __IO uint32_t SHORTS; /*!< Shortcuts for the LPCOMP. */
AnnaBridge 171:3a7713b1edbc 989 __I uint32_t RESERVED2[64];
AnnaBridge 171:3a7713b1edbc 990 __IO uint32_t INTENSET; /*!< Interrupt enable set register. */
AnnaBridge 171:3a7713b1edbc 991 __IO uint32_t INTENCLR; /*!< Interrupt enable clear register. */
AnnaBridge 171:3a7713b1edbc 992 __I uint32_t RESERVED3[61];
AnnaBridge 171:3a7713b1edbc 993 __I uint32_t RESULT; /*!< Result of last compare. */
AnnaBridge 171:3a7713b1edbc 994 __I uint32_t RESERVED4[63];
AnnaBridge 171:3a7713b1edbc 995 __IO uint32_t ENABLE; /*!< Enable the LPCOMP. */
AnnaBridge 171:3a7713b1edbc 996 __IO uint32_t PSEL; /*!< Input pin select. */
AnnaBridge 171:3a7713b1edbc 997 __IO uint32_t REFSEL; /*!< Reference select. */
AnnaBridge 171:3a7713b1edbc 998 __IO uint32_t EXTREFSEL; /*!< External reference select. */
AnnaBridge 171:3a7713b1edbc 999 __I uint32_t RESERVED5[4];
AnnaBridge 171:3a7713b1edbc 1000 __IO uint32_t ANADETECT; /*!< Analog detect configuration. */
AnnaBridge 171:3a7713b1edbc 1001 __I uint32_t RESERVED6[694];
AnnaBridge 171:3a7713b1edbc 1002 __IO uint32_t POWER; /*!< Peripheral power control. */
AnnaBridge 171:3a7713b1edbc 1003 } NRF_LPCOMP_Type;
AnnaBridge 171:3a7713b1edbc 1004
AnnaBridge 171:3a7713b1edbc 1005
AnnaBridge 171:3a7713b1edbc 1006 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1007 /* ================ SWI ================ */
AnnaBridge 171:3a7713b1edbc 1008 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1009
AnnaBridge 171:3a7713b1edbc 1010
AnnaBridge 171:3a7713b1edbc 1011 /**
AnnaBridge 171:3a7713b1edbc 1012 * @brief SW Interrupts. (SWI)
AnnaBridge 171:3a7713b1edbc 1013 */
AnnaBridge 171:3a7713b1edbc 1014
AnnaBridge 171:3a7713b1edbc 1015 typedef struct { /*!< SWI Structure */
AnnaBridge 171:3a7713b1edbc 1016 __I uint32_t UNUSED; /*!< Unused. */
AnnaBridge 171:3a7713b1edbc 1017 } NRF_SWI_Type;
AnnaBridge 171:3a7713b1edbc 1018
AnnaBridge 171:3a7713b1edbc 1019
AnnaBridge 171:3a7713b1edbc 1020 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1021 /* ================ NVMC ================ */
AnnaBridge 171:3a7713b1edbc 1022 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1023
AnnaBridge 171:3a7713b1edbc 1024
AnnaBridge 171:3a7713b1edbc 1025 /**
AnnaBridge 171:3a7713b1edbc 1026 * @brief Non Volatile Memory Controller. (NVMC)
AnnaBridge 171:3a7713b1edbc 1027 */
AnnaBridge 171:3a7713b1edbc 1028
AnnaBridge 171:3a7713b1edbc 1029 typedef struct { /*!< NVMC Structure */
AnnaBridge 171:3a7713b1edbc 1030 __I uint32_t RESERVED0[256];
AnnaBridge 171:3a7713b1edbc 1031 __I uint32_t READY; /*!< Ready flag. */
AnnaBridge 171:3a7713b1edbc 1032 __I uint32_t RESERVED1[64];
AnnaBridge 171:3a7713b1edbc 1033 __IO uint32_t CONFIG; /*!< Configuration register. */
AnnaBridge 171:3a7713b1edbc 1034
AnnaBridge 171:3a7713b1edbc 1035 union {
AnnaBridge 171:3a7713b1edbc 1036 __IO uint32_t ERASEPCR1; /*!< Register for erasing a non-protected non-volatile memory page. */
AnnaBridge 171:3a7713b1edbc 1037 __IO uint32_t ERASEPAGE; /*!< Register for erasing a non-protected non-volatile memory page. */
AnnaBridge 171:3a7713b1edbc 1038 };
AnnaBridge 171:3a7713b1edbc 1039 __IO uint32_t ERASEALL; /*!< Register for erasing all non-volatile user memory. */
AnnaBridge 171:3a7713b1edbc 1040 __IO uint32_t ERASEPCR0; /*!< Register for erasing a protected non-volatile memory page. */
AnnaBridge 171:3a7713b1edbc 1041 __IO uint32_t ERASEUICR; /*!< Register for start erasing User Information Congfiguration Registers. */
AnnaBridge 171:3a7713b1edbc 1042 } NRF_NVMC_Type;
AnnaBridge 171:3a7713b1edbc 1043
AnnaBridge 171:3a7713b1edbc 1044
AnnaBridge 171:3a7713b1edbc 1045 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1046 /* ================ PPI ================ */
AnnaBridge 171:3a7713b1edbc 1047 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1048
AnnaBridge 171:3a7713b1edbc 1049
AnnaBridge 171:3a7713b1edbc 1050 /**
AnnaBridge 171:3a7713b1edbc 1051 * @brief PPI controller. (PPI)
AnnaBridge 171:3a7713b1edbc 1052 */
AnnaBridge 171:3a7713b1edbc 1053
AnnaBridge 171:3a7713b1edbc 1054 typedef struct { /*!< PPI Structure */
AnnaBridge 171:3a7713b1edbc 1055 PPI_TASKS_CHG_Type TASKS_CHG[4]; /*!< Channel group tasks. */
AnnaBridge 171:3a7713b1edbc 1056 __I uint32_t RESERVED0[312];
AnnaBridge 171:3a7713b1edbc 1057 __IO uint32_t CHEN; /*!< Channel enable. */
AnnaBridge 171:3a7713b1edbc 1058 __IO uint32_t CHENSET; /*!< Channel enable set. */
AnnaBridge 171:3a7713b1edbc 1059 __IO uint32_t CHENCLR; /*!< Channel enable clear. */
AnnaBridge 171:3a7713b1edbc 1060 __I uint32_t RESERVED1;
AnnaBridge 171:3a7713b1edbc 1061 PPI_CH_Type CH[16]; /*!< PPI Channel. */
AnnaBridge 171:3a7713b1edbc 1062 __I uint32_t RESERVED2[156];
AnnaBridge 171:3a7713b1edbc 1063 __IO uint32_t CHG[4]; /*!< Channel group configuration. */
AnnaBridge 171:3a7713b1edbc 1064 } NRF_PPI_Type;
AnnaBridge 171:3a7713b1edbc 1065
AnnaBridge 171:3a7713b1edbc 1066
AnnaBridge 171:3a7713b1edbc 1067 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1068 /* ================ FICR ================ */
AnnaBridge 171:3a7713b1edbc 1069 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1070
AnnaBridge 171:3a7713b1edbc 1071
AnnaBridge 171:3a7713b1edbc 1072 /**
AnnaBridge 171:3a7713b1edbc 1073 * @brief Factory Information Configuration. (FICR)
AnnaBridge 171:3a7713b1edbc 1074 */
AnnaBridge 171:3a7713b1edbc 1075
AnnaBridge 171:3a7713b1edbc 1076 typedef struct { /*!< FICR Structure */
AnnaBridge 171:3a7713b1edbc 1077 __I uint32_t RESERVED0[4];
AnnaBridge 171:3a7713b1edbc 1078 __I uint32_t CODEPAGESIZE; /*!< Code memory page size in bytes. */
AnnaBridge 171:3a7713b1edbc 1079 __I uint32_t CODESIZE; /*!< Code memory size in pages. */
AnnaBridge 171:3a7713b1edbc 1080 __I uint32_t RESERVED1[4];
AnnaBridge 171:3a7713b1edbc 1081 __I uint32_t CLENR0; /*!< Length of code region 0 in bytes. */
AnnaBridge 171:3a7713b1edbc 1082 __I uint32_t PPFC; /*!< Pre-programmed factory code present. */
AnnaBridge 171:3a7713b1edbc 1083 __I uint32_t RESERVED2;
AnnaBridge 171:3a7713b1edbc 1084 __I uint32_t NUMRAMBLOCK; /*!< Number of individualy controllable RAM blocks. */
AnnaBridge 171:3a7713b1edbc 1085
AnnaBridge 171:3a7713b1edbc 1086 union {
AnnaBridge 171:3a7713b1edbc 1087 __I uint32_t SIZERAMBLOCK[4]; /*!< Deprecated array of size of RAM block in bytes. This name is
AnnaBridge 171:3a7713b1edbc 1088 kept for backward compatinility purposes. Use SIZERAMBLOCKS
AnnaBridge 171:3a7713b1edbc 1089 instead. */
AnnaBridge 171:3a7713b1edbc 1090 __I uint32_t SIZERAMBLOCKS; /*!< Size of RAM blocks in bytes. */
AnnaBridge 171:3a7713b1edbc 1091 };
AnnaBridge 171:3a7713b1edbc 1092 __I uint32_t RESERVED3[5];
AnnaBridge 171:3a7713b1edbc 1093 __I uint32_t CONFIGID; /*!< Configuration identifier. */
AnnaBridge 171:3a7713b1edbc 1094 __I uint32_t DEVICEID[2]; /*!< Device identifier. */
AnnaBridge 171:3a7713b1edbc 1095 __I uint32_t RESERVED4[6];
AnnaBridge 171:3a7713b1edbc 1096 __I uint32_t ER[4]; /*!< Encryption root. */
AnnaBridge 171:3a7713b1edbc 1097 __I uint32_t IR[4]; /*!< Identity root. */
AnnaBridge 171:3a7713b1edbc 1098 __I uint32_t DEVICEADDRTYPE; /*!< Device address type. */
AnnaBridge 171:3a7713b1edbc 1099 __I uint32_t DEVICEADDR[2]; /*!< Device address. */
AnnaBridge 171:3a7713b1edbc 1100 __I uint32_t OVERRIDEEN; /*!< Radio calibration override enable. */
AnnaBridge 171:3a7713b1edbc 1101 __I uint32_t NRF_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for NRF_1Mbit
AnnaBridge 171:3a7713b1edbc 1102 mode. */
AnnaBridge 171:3a7713b1edbc 1103 __I uint32_t RESERVED5[10];
AnnaBridge 171:3a7713b1edbc 1104 __I uint32_t BLE_1MBIT[5]; /*!< Override values for the OVERRIDEn registers in RADIO for BLE_1Mbit
AnnaBridge 171:3a7713b1edbc 1105 mode. */
AnnaBridge 171:3a7713b1edbc 1106 } NRF_FICR_Type;
AnnaBridge 171:3a7713b1edbc 1107
AnnaBridge 171:3a7713b1edbc 1108
AnnaBridge 171:3a7713b1edbc 1109 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1110 /* ================ UICR ================ */
AnnaBridge 171:3a7713b1edbc 1111 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1112
AnnaBridge 171:3a7713b1edbc 1113
AnnaBridge 171:3a7713b1edbc 1114 /**
AnnaBridge 171:3a7713b1edbc 1115 * @brief User Information Configuration. (UICR)
AnnaBridge 171:3a7713b1edbc 1116 */
AnnaBridge 171:3a7713b1edbc 1117
AnnaBridge 171:3a7713b1edbc 1118 typedef struct { /*!< UICR Structure */
AnnaBridge 171:3a7713b1edbc 1119 __IO uint32_t CLENR0; /*!< Length of code region 0. */
AnnaBridge 171:3a7713b1edbc 1120 __IO uint32_t RBPCONF; /*!< Readback protection configuration. */
AnnaBridge 171:3a7713b1edbc 1121 __IO uint32_t XTALFREQ; /*!< Reset value for CLOCK XTALFREQ register. */
AnnaBridge 171:3a7713b1edbc 1122 __I uint32_t RESERVED0;
AnnaBridge 171:3a7713b1edbc 1123 __I uint32_t FWID; /*!< Firmware ID. */
AnnaBridge 171:3a7713b1edbc 1124
AnnaBridge 171:3a7713b1edbc 1125 union {
AnnaBridge 171:3a7713b1edbc 1126 __IO uint32_t NRFFW[15]; /*!< Reserved for Nordic firmware design. */
AnnaBridge 171:3a7713b1edbc 1127 __IO uint32_t BOOTLOADERADDR; /*!< Bootloader start address. */
AnnaBridge 171:3a7713b1edbc 1128 };
AnnaBridge 171:3a7713b1edbc 1129 __IO uint32_t NRFHW[12]; /*!< Reserved for Nordic hardware design. */
AnnaBridge 171:3a7713b1edbc 1130 __IO uint32_t CUSTOMER[32]; /*!< Reserved for customer. */
AnnaBridge 171:3a7713b1edbc 1131 } NRF_UICR_Type;
AnnaBridge 171:3a7713b1edbc 1132
AnnaBridge 171:3a7713b1edbc 1133
AnnaBridge 171:3a7713b1edbc 1134 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1135 /* ================ GPIO ================ */
AnnaBridge 171:3a7713b1edbc 1136 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1137
AnnaBridge 171:3a7713b1edbc 1138
AnnaBridge 171:3a7713b1edbc 1139 /**
AnnaBridge 171:3a7713b1edbc 1140 * @brief General purpose input and output. (GPIO)
AnnaBridge 171:3a7713b1edbc 1141 */
AnnaBridge 171:3a7713b1edbc 1142
AnnaBridge 171:3a7713b1edbc 1143 typedef struct { /*!< GPIO Structure */
AnnaBridge 171:3a7713b1edbc 1144 __I uint32_t RESERVED0[321];
AnnaBridge 171:3a7713b1edbc 1145 __IO uint32_t OUT; /*!< Write GPIO port. */
AnnaBridge 171:3a7713b1edbc 1146 __IO uint32_t OUTSET; /*!< Set individual bits in GPIO port. */
AnnaBridge 171:3a7713b1edbc 1147 __IO uint32_t OUTCLR; /*!< Clear individual bits in GPIO port. */
AnnaBridge 171:3a7713b1edbc 1148 __I uint32_t IN; /*!< Read GPIO port. */
AnnaBridge 171:3a7713b1edbc 1149 __IO uint32_t DIR; /*!< Direction of GPIO pins. */
AnnaBridge 171:3a7713b1edbc 1150 __IO uint32_t DIRSET; /*!< DIR set register. */
AnnaBridge 171:3a7713b1edbc 1151 __IO uint32_t DIRCLR; /*!< DIR clear register. */
AnnaBridge 171:3a7713b1edbc 1152 __I uint32_t RESERVED1[120];
AnnaBridge 171:3a7713b1edbc 1153 __IO uint32_t PIN_CNF[32]; /*!< Configuration of GPIO pins. */
AnnaBridge 171:3a7713b1edbc 1154 } NRF_GPIO_Type;
AnnaBridge 171:3a7713b1edbc 1155
AnnaBridge 171:3a7713b1edbc 1156
AnnaBridge 171:3a7713b1edbc 1157 /* -------------------- End of section using anonymous unions ------------------- */
AnnaBridge 171:3a7713b1edbc 1158 #if defined(__CC_ARM)
AnnaBridge 171:3a7713b1edbc 1159 #pragma pop
AnnaBridge 171:3a7713b1edbc 1160 #elif defined(__ICCARM__)
AnnaBridge 171:3a7713b1edbc 1161 /* leave anonymous unions enabled */
AnnaBridge 171:3a7713b1edbc 1162 #elif defined(__GNUC__)
AnnaBridge 171:3a7713b1edbc 1163 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 1164 #elif defined(__TMS470__)
AnnaBridge 171:3a7713b1edbc 1165 /* anonymous unions are enabled by default */
AnnaBridge 171:3a7713b1edbc 1166 #elif defined(__TASKING__)
AnnaBridge 171:3a7713b1edbc 1167 #pragma warning restore
AnnaBridge 171:3a7713b1edbc 1168 #else
AnnaBridge 171:3a7713b1edbc 1169 #warning Not supported compiler type
AnnaBridge 171:3a7713b1edbc 1170 #endif
AnnaBridge 171:3a7713b1edbc 1171
AnnaBridge 171:3a7713b1edbc 1172
AnnaBridge 171:3a7713b1edbc 1173
AnnaBridge 171:3a7713b1edbc 1174
AnnaBridge 171:3a7713b1edbc 1175 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1176 /* ================ Peripheral memory map ================ */
AnnaBridge 171:3a7713b1edbc 1177 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1178
AnnaBridge 171:3a7713b1edbc 1179 #define NRF_POWER_BASE 0x40000000UL
AnnaBridge 171:3a7713b1edbc 1180 #define NRF_CLOCK_BASE 0x40000000UL
AnnaBridge 171:3a7713b1edbc 1181 #define NRF_MPU_BASE 0x40000000UL
AnnaBridge 171:3a7713b1edbc 1182 #define NRF_AMLI_BASE 0x40000000UL
AnnaBridge 171:3a7713b1edbc 1183 #define NRF_RADIO_BASE 0x40001000UL
AnnaBridge 171:3a7713b1edbc 1184 #define NRF_UART0_BASE 0x40002000UL
AnnaBridge 171:3a7713b1edbc 1185 #define NRF_SPI0_BASE 0x40003000UL
AnnaBridge 171:3a7713b1edbc 1186 #define NRF_TWI0_BASE 0x40003000UL
AnnaBridge 171:3a7713b1edbc 1187 #define NRF_SPI1_BASE 0x40004000UL
AnnaBridge 171:3a7713b1edbc 1188 #define NRF_TWI1_BASE 0x40004000UL
AnnaBridge 171:3a7713b1edbc 1189 #define NRF_SPIS1_BASE 0x40004000UL
AnnaBridge 171:3a7713b1edbc 1190 #define NRF_SPIM1_BASE 0x40004000UL
AnnaBridge 171:3a7713b1edbc 1191 #define NRF_GPIOTE_BASE 0x40006000UL
AnnaBridge 171:3a7713b1edbc 1192 #define NRF_ADC_BASE 0x40007000UL
AnnaBridge 171:3a7713b1edbc 1193 #define NRF_TIMER0_BASE 0x40008000UL
AnnaBridge 171:3a7713b1edbc 1194 #define NRF_TIMER1_BASE 0x40009000UL
AnnaBridge 171:3a7713b1edbc 1195 #define NRF_TIMER2_BASE 0x4000A000UL
AnnaBridge 171:3a7713b1edbc 1196 #define NRF_RTC0_BASE 0x4000B000UL
AnnaBridge 171:3a7713b1edbc 1197 #define NRF_TEMP_BASE 0x4000C000UL
AnnaBridge 171:3a7713b1edbc 1198 #define NRF_RNG_BASE 0x4000D000UL
AnnaBridge 171:3a7713b1edbc 1199 #define NRF_ECB_BASE 0x4000E000UL
AnnaBridge 171:3a7713b1edbc 1200 #define NRF_AAR_BASE 0x4000F000UL
AnnaBridge 171:3a7713b1edbc 1201 #define NRF_CCM_BASE 0x4000F000UL
AnnaBridge 171:3a7713b1edbc 1202 #define NRF_WDT_BASE 0x40010000UL
AnnaBridge 171:3a7713b1edbc 1203 #define NRF_RTC1_BASE 0x40011000UL
AnnaBridge 171:3a7713b1edbc 1204 #define NRF_QDEC_BASE 0x40012000UL
AnnaBridge 171:3a7713b1edbc 1205 #define NRF_LPCOMP_BASE 0x40013000UL
AnnaBridge 171:3a7713b1edbc 1206 #define NRF_SWI_BASE 0x40014000UL
AnnaBridge 171:3a7713b1edbc 1207 #define NRF_NVMC_BASE 0x4001E000UL
AnnaBridge 171:3a7713b1edbc 1208 #define NRF_PPI_BASE 0x4001F000UL
AnnaBridge 171:3a7713b1edbc 1209 #define NRF_FICR_BASE 0x10000000UL
AnnaBridge 171:3a7713b1edbc 1210 #define NRF_UICR_BASE 0x10001000UL
AnnaBridge 171:3a7713b1edbc 1211 #define NRF_GPIO_BASE 0x50000000UL
AnnaBridge 171:3a7713b1edbc 1212
AnnaBridge 171:3a7713b1edbc 1213
AnnaBridge 171:3a7713b1edbc 1214 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1215 /* ================ Peripheral declaration ================ */
AnnaBridge 171:3a7713b1edbc 1216 /* ================================================================================ */
AnnaBridge 171:3a7713b1edbc 1217
AnnaBridge 171:3a7713b1edbc 1218 #define NRF_POWER ((NRF_POWER_Type *) NRF_POWER_BASE)
AnnaBridge 171:3a7713b1edbc 1219 #define NRF_CLOCK ((NRF_CLOCK_Type *) NRF_CLOCK_BASE)
AnnaBridge 171:3a7713b1edbc 1220 #define NRF_MPU ((NRF_MPU_Type *) NRF_MPU_BASE)
AnnaBridge 171:3a7713b1edbc 1221 #define NRF_AMLI ((NRF_AMLI_Type *) NRF_AMLI_BASE)
AnnaBridge 171:3a7713b1edbc 1222 #define NRF_RADIO ((NRF_RADIO_Type *) NRF_RADIO_BASE)
AnnaBridge 171:3a7713b1edbc 1223 #define NRF_UART0 ((NRF_UART_Type *) NRF_UART0_BASE)
AnnaBridge 171:3a7713b1edbc 1224 #define NRF_SPI0 ((NRF_SPI_Type *) NRF_SPI0_BASE)
AnnaBridge 171:3a7713b1edbc 1225 #define NRF_TWI0 ((NRF_TWI_Type *) NRF_TWI0_BASE)
AnnaBridge 171:3a7713b1edbc 1226 #define NRF_SPI1 ((NRF_SPI_Type *) NRF_SPI1_BASE)
AnnaBridge 171:3a7713b1edbc 1227 #define NRF_TWI1 ((NRF_TWI_Type *) NRF_TWI1_BASE)
AnnaBridge 171:3a7713b1edbc 1228 #define NRF_SPIS1 ((NRF_SPIS_Type *) NRF_SPIS1_BASE)
AnnaBridge 171:3a7713b1edbc 1229 #define NRF_SPIM1 ((NRF_SPIM_Type *) NRF_SPIM1_BASE)
AnnaBridge 171:3a7713b1edbc 1230 #define NRF_GPIOTE ((NRF_GPIOTE_Type *) NRF_GPIOTE_BASE)
AnnaBridge 171:3a7713b1edbc 1231 #define NRF_ADC ((NRF_ADC_Type *) NRF_ADC_BASE)
AnnaBridge 171:3a7713b1edbc 1232 #define NRF_TIMER0 ((NRF_TIMER_Type *) NRF_TIMER0_BASE)
AnnaBridge 171:3a7713b1edbc 1233 #define NRF_TIMER1 ((NRF_TIMER_Type *) NRF_TIMER1_BASE)
AnnaBridge 171:3a7713b1edbc 1234 #define NRF_TIMER2 ((NRF_TIMER_Type *) NRF_TIMER2_BASE)
AnnaBridge 171:3a7713b1edbc 1235 #define NRF_RTC0 ((NRF_RTC_Type *) NRF_RTC0_BASE)
AnnaBridge 171:3a7713b1edbc 1236 #define NRF_TEMP ((NRF_TEMP_Type *) NRF_TEMP_BASE)
AnnaBridge 171:3a7713b1edbc 1237 #define NRF_RNG ((NRF_RNG_Type *) NRF_RNG_BASE)
AnnaBridge 171:3a7713b1edbc 1238 #define NRF_ECB ((NRF_ECB_Type *) NRF_ECB_BASE)
AnnaBridge 171:3a7713b1edbc 1239 #define NRF_AAR ((NRF_AAR_Type *) NRF_AAR_BASE)
AnnaBridge 171:3a7713b1edbc 1240 #define NRF_CCM ((NRF_CCM_Type *) NRF_CCM_BASE)
AnnaBridge 171:3a7713b1edbc 1241 #define NRF_WDT ((NRF_WDT_Type *) NRF_WDT_BASE)
AnnaBridge 171:3a7713b1edbc 1242 #define NRF_RTC1 ((NRF_RTC_Type *) NRF_RTC1_BASE)
AnnaBridge 171:3a7713b1edbc 1243 #define NRF_QDEC ((NRF_QDEC_Type *) NRF_QDEC_BASE)
AnnaBridge 171:3a7713b1edbc 1244 #define NRF_LPCOMP ((NRF_LPCOMP_Type *) NRF_LPCOMP_BASE)
AnnaBridge 171:3a7713b1edbc 1245 #define NRF_SWI ((NRF_SWI_Type *) NRF_SWI_BASE)
AnnaBridge 171:3a7713b1edbc 1246 #define NRF_NVMC ((NRF_NVMC_Type *) NRF_NVMC_BASE)
AnnaBridge 171:3a7713b1edbc 1247 #define NRF_PPI ((NRF_PPI_Type *) NRF_PPI_BASE)
AnnaBridge 171:3a7713b1edbc 1248 #define NRF_FICR ((NRF_FICR_Type *) NRF_FICR_BASE)
AnnaBridge 171:3a7713b1edbc 1249 #define NRF_UICR ((NRF_UICR_Type *) NRF_UICR_BASE)
AnnaBridge 171:3a7713b1edbc 1250 #define NRF_GPIO ((NRF_GPIO_Type *) NRF_GPIO_BASE)
AnnaBridge 171:3a7713b1edbc 1251
AnnaBridge 171:3a7713b1edbc 1252
AnnaBridge 171:3a7713b1edbc 1253 /** @} */ /* End of group Device_Peripheral_Registers */
AnnaBridge 171:3a7713b1edbc 1254 /** @} */ /* End of group nrf51 */
AnnaBridge 171:3a7713b1edbc 1255 /** @} */ /* End of group Nordic Semiconductor */
AnnaBridge 171:3a7713b1edbc 1256
AnnaBridge 171:3a7713b1edbc 1257 #ifdef __cplusplus
AnnaBridge 171:3a7713b1edbc 1258 }
AnnaBridge 171:3a7713b1edbc 1259 #endif
AnnaBridge 171:3a7713b1edbc 1260
AnnaBridge 171:3a7713b1edbc 1261
AnnaBridge 171:3a7713b1edbc 1262 #endif /* nrf51_H */